TMPZ84C00A

TMPZ84C00A TOSHIBA | Alldatasheet

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TMPZ84COOAP-6 / TMPZ84COOAM-6 / TMPZ84CO0AT-6 TMPZ84COOAP-8 / TMPZ84CO0AM-8 / TMPZ84CO0AT-8 TLCS-280 MPU : 8-BIT MICROPROCESSOR 1. OUTLINE AND FEATURES The TMPZ84COOA is an 8-bit microprocessor (hereinafter referred to as MPU), which provides low power operation and high performance. Built into the TMPZ84COOA are bus control, memory control and timing control circuits in addition to paired 6 general purpose registers, accumulator, flag registers and an arithmetic-and-logic unit. The TMPZ84CODA is fabricated using Toshiba’s CMOS Silicon gate Technology. The pricipal functions and features of the TMPZ84CO00A are as follows. Table 1.1 Operating Frequency and Supply Current Produce Name Peeueny AT ATRUN | stanp BY TMPZ84COOAP-| — 6MHz 15mA O.5pA 6/AM-6/AT-6 TMPZ84cOOAP- | — 8MHz 20mA O.SpA B/AM-8/AT-8 ‘060889 (1) Commands compatible with the Zilog Z80 MPU. (2) Low power consumption (3) DC to 8MHz operation (at 5V £10%) (4) Single 5V power supply (5V+10%) (5) Operating temperature (—40°C to 85°C) (6) Powerful set of 158 instrucitons available (7) Powerful interrupt function. (a) Non-maskable interrupt terminal (NMI) (b) Maskable interrupt terminal (INT) The following 3 modes are selectable: © 8080 compatible interrupt mode (interrupt by Non-Z80 family peripheral LSI) (Mode 0) © Restart interrupt (Mode 1) MPUZ80-1

$$ Sesser © Daisy chain structure interrupt using Z80 family peripheral LSI (Mode 2) (8) Anauxiliary resister provided to each of general purpose registers (9) Two index registers (10) 10 addressing modes (11) Built-in refresh circuit for dynamic memory (12) Molded in 40-pin DIP package (P), 40-pin SOP package (M) and 44-pin PLCC package (T). Further, in the following text and explanations for charts and tables, hexadecimal numbers are directly used without giving an identification to explanation of address, etc. to the extent not to cause confusions. Note: Z80 is a trademark of Zilog Inc., U.S.A. SSS MPUZ80-2

1. PIN ASSIGNMENT AND FUNCTIONS The pin assignment and I/O pin names and brief functions of TMPZ84CO00A are shown below. 2.1. PIN ASSIGNMENT (TOP View) ‘The pin assignment of the TMPZ84CO00A are as shown in Figure 2.1 and Figure 2.2. ands aopato ai? sapas aamace AB3g3 38 As Eeerereee eed Alaa 37D a7 epeeueeeseseseseasese: Ais 36 As 65.432 14403424140 axis aspas ade: 7 39 Sccpas oad uafias cee ie) 38 pas cade spas os 10 3 bae ost9 32A2 D6 Gash 1 35 PAT ost 10 afi wed 34 hao Vee 11 30 Hao Dd ta 32 2D RSH 02412 291 Vs5. o7g 15 3 pM 07413 28 D RFS bog 16 30 cD RESET ws ord 7 29" bBusRea bog14 27 MT "\\19202122232425262728 InTdi6 25 BUSREQ SreTHETHIEESEEEtTEEE wid 17 26 wait EEEEBP® ee k FACTO 18 23 D BUSACK Ee B WAREQG 19 2 PWR osoase ToRGG 20 21 fR6 oeoses Figure 2.1 DIP,SOPPin Assignment _ Figure 2.2. PLCC Package Pin Assignment MPUz80-3

2.2 PINNAMES AND FUNCTIONS

W/O pin names and functions are as shown Table 2.1. Table 2.1 Pin names and Functions. (172) Q'ty DO-D7 Input/output | The 8-bit bi-directional data bus. 3-state AO-A15 16 Output | The 16-bit address bus. 3state [These pins specify memory and 1/0 port addresses. During a refresh cycle, the refresh address is output 1 The Machine Cycle 1 signal. In an operation code fetch cycle, this pin goes “O" with the MREQ signal. At the execution of a 2-byte operation code, this pin goes “0” for each ‘operation code fetch. In a maskable interrupt acknowledge cycle, this pin goes "0" with the TORQ signal. Output | The Read signal. it indicates that the MPU is 3-state | ready for accepting data from memory or /O- device. The data from the addressed memory or VO devices is gated by this signal onto the MPU data bus. WR Output | The Write signal. This signal is output when the 3state | data to be stored in the addressed memory or I/O device is on the data bus. Output | The Memory Request signal. When the 3-state | execution address for memory access is on the address bus, this pin goes "0" . During a memory refresh cycle, this pin also goes “0” with RFSH signal TORQ Output | The Input/Output Request signal. This pin goes 3-state “0” when the address for an I/O read or write operation is on the low-order 8 bits (A0 through A7) of the address bus. The IORQ signal is also output with the M1 signal at interrupt acknowledge to tell an I/O device that the interrupt response vector can be placed on the data bus. CLK 1 Input | The Single-phase Clock input. | When the clock input is placed in the DC state (continued “1” or “0” level), this pin stops operating and holds the state of that time rrr) MPUZ80-4

(2/2) ay F |r| (Number) Tye arate RESET 1 Input The Reset signal input. RESET signal is used for initialization MPU and must be kept in active state ("0") for a period of at least 3 clocks. INT 1 Input. The Maskable Interrupt signal. An interrupt is | caused by the peripheral (SI. An interrupt is | acknowledged when the interrupt enable flip- flop (IFF) is set to “1" by software. The INT pin is normally wire-ORed and requires | an external pullup resistor for these applications. WATT 1 The Wait Request signal. This signal indicates to the MPU that the addressed memory or /O device is not ready for data transfer. As long as this signal is “0”, the MPU is in the Wait state. BUSREQ Input | The bus Request signal. The BUSREQ signal forces the MPU address bus, data bus, and control signals MREQ, IORQ, RD, and WR to be placed in the high-impedance state. This signal is normally Wire-ORed and requires an external puilup resistor for these applications. BUSACK Output | The Bus Acknowledge signal. In response to the BUSREQ signal, the BUSACK signal indicates to the requesting peripheral LSI that the MPU address bus, data bus, and control signals MREQ, TORQ, RD and WR have been put in the high- impedance state. HAUT Output | The Halt signal. This pin goes “0” when the MPU has executed a Halt instruction and isin the Halt state. RFSH Output | The refresh signal. When the dynamic memory refresh address is on the low-order 8 bits of the address bus, this signal goes "0" . At the same time, the MREQ signal also goes active ("0") The Non-maskable interrupt Request signal. This interrupt request has a higher priority than the maskable interrupt and is not dependent on the interrupt enable flip-flop (FF) state. NC Not connected internaly. (PLCC only) Please use by open. power supply 060089 eee MPUZ80-5

1. FUNCTIONAL DESCRIPTION ‘The system configuration, functions and basic operation of the TMPZ84CO0A are described here. 3.1. BLOCK DIAGRAM ‘The block diagram of the internal configuration is shown in Figure 3.1. om Address bus output circuit A] | [ Bregister |b register a aI ° Z| Z Lregster S =| [register | freasier | 2 2 vs ‘Stack pointer (SP) os g, : 5 vee—+| |€ 3 9 = 4 z fe : a Ce decoder es Eg Oo 2 Sz Datavo vo] Sontrel | S| |<— Reset [ert [irra | Control Control ignatte a6 WBA “ MI WaisraBt Control bus controller NMI INT JORG HALT WAIT MREQ RD WR BUSREQ BUSACK oss Figure 3.1 Block Diagram MPUZ80-6

3.2 SYSTEM CONFIGURATION

The MPU has the configuration shown in Figure 3.1. The address signal is put on the address bus via the address buffer. The data bus is controlled for input or output by the data bus interface. Both the address and data buses are put in the high-impedance state by the BUSEQ signal input to make them available for other peripheral LSIs. The Opcode read from memory via the data bus is written to the instruction register. This Opcode is decoded by the instruction decoder. According to the result of the decoding, control signals are sent to the relevant devices. Receiving these control signals, the ALU performs arithmetic operations. The register array temporarily hold the information required to perform operation. The following describes the MPU’s main components and functions which the user must understand to operate the TMPZ84C00A. [1] _ Internal Register Groups The configuration of the internal register groups is as follows: (1) Main registers A,F,B,C,D,E,H,L (2) Alternate registers A’, P,B’,C’,D’,E’,H’,L’ (3) Special purpose registers I,R, IX, TY, SP, PC Figure 3.3 shows the configuration of the internal register groups. The register groups, each being of a static RAM, consists of eighteen 8-bit registers and four 16-bit registers. The following describes the function of each register: (1) Main registers (A, F,B, C, D, E, H, L) (a) Accumulator (A) The accumulator is an 8-bit register used for arithmetic and data transfer operations. {b) Flag register (F) (see Fig. 3.2) ‘The flag register is an 8-bit register to hold the result of each arithmetic operation. Actually, the 6 of the 8 bits are set (“1”)/reset (“0”) according to the condition specified by an instruction. MPUZ80-7

TOSHIBA ‘TMPZ84CO0A With a block search instruction (CPI, CPIR, CPD or CPDR), the Z flag is set to “1” if the source data and the accumulator data match. With a block I/O instruction (INI, IND, OUTI or OUTD), the Z flag is set to “1” if the content of the B register used as the byte counter is “0” at the end of comparison. . Parity/overflow flag (P/V) ‘This flag has two functions. One is the parity flag (P) that indicates the result of a logical operation (AND A, Bete. ). The P flag is set to “1” if the parity iseven asa result of the operation on signed values by two’s complement. It is reset to “O” if the parity is odd. With a block search instruction (CPI, CPIR, CPD or CPDR) anda block transfer instruction (LDI or LDD), the P flag indicates the state of the byte counter (register pair B and C). It is set to “1” if the byte counter is not “0” and reset to “0” when the byte counter becomes “0” (at the end of comparison or data transfer). The content of the interrupt enable flip-flop (IFF) is saved to the P flag when the contents of the R register or I register are transferred to the accumulator. The other use of the P/V flag is the overflow flag (V) that indicates whether an overflow has occurred or not as a result of an arithmetic operation. The V flag is set to “1” when the value in the accumulator gets out of a range of the maximum value +127 and the minimum value —128 and therefore cannot be correctly represented as a two’s complement notation. Whether the P/V flag operates as the P flag or V flag is determined by the type of the instruction executed. e Carry flag (C) The C flag is set to “1” ifa carry occurs from bit 7 of the accumulator or a borrow occurs as a result of an operation. ‘The following two flags are not available to the programmer for the test and set ("reset (“0”) purposes. They are internally used by the MPU for BCD arithmetic operations. ° Halfcarry flag (H. The H flag is used for holding the carry or borrow from the low-order 4 bits of a BCD operation result. When a DAA instruction (decimal adjust) is executed, the MPU automatically uses the H flag to adjust the result of a decimal addition or subtraction. e Add/subtract flag (N In BCD operation, algorithm is different between addition and subtraction. The N flag indicates whether the executed operation is addition or subtraction. MPUZ80-9

For change of the flag state depending on the instruction, see 3.4 “TMPZ84CO0A Instruction Set” . (c) General-purpose registers (B, C, D, E, H, L) General-purpose registers consist of 8 bits each. They are used as 16-bit register pairs (BC, DE, HL) as well as independent 8-bit registers to supplement the accumulator. The B register and the register pair BC are used as counters when a block I/O, block transfer, or search instruction is executed. The register pair HL has various memory addressing features as compared with the register pairs BC and DE. (2) Alternate registers (A’, F’, B’, C’,D’, E’, H’, L') The configuration of the alternate registers is exactly the same as that of the main registers. There is no instruction that handles the alternate registers directly. The data in the alternate registers are processed by moving them into the main registers by means of exchange instructions as shown below: EX AF, AF’ (A@A’, FoF’) EXX (BoB, CoC’, DoD’, BoE’, HoH’, LoL) When a high-speed interrupt response has been requested within the system, these instruction can be used to quickly move the contents of the accumulator, flag registers, and general-purpose registers into the corresponding registers. This eliminates the need for transferring the register contents to/from the external stack during execution of the interrupt handling routine, thereby shortening the interrupt servicing time greatly. (3) Special purpose registers (I, R, IX, IY, SP, PC) (a) interrupt page address register (I) The TMPZ84CO0A provides two kinds of interrupts :maskable interrupt (INT) and non-maskable interrupt (NMI). The maskable interrupt provides three modes (0, 1, and 2) in which the interrupt is handled. These modes can be selected by instructions IMO, IM1, and IM2 respectively. In Mode 2, any memory location can be called indirectly depending on the interrupt. For this purpose, the I register stores the high-order 8 bits of the indirect address. The low-order 8 bits are supplied from the interrupting peripheral LSI. This scheme permits calling the interrupt handling routine from any memory location in an extremely short access time. For the details of interrupts, see [4] “Interrupt Capability”. MPUZ80-10

(b) Memory refresh register (R) The R register is used as the memory refresh counter when the dynamic RAM is used for memory. This permits using of the dynamic memory in the same manner as the static memory. The Low-order 7 bits of this 8-bit register is automatically incremented for each instruction fetch. While the MPU decodes and executes the fetched instruction, the contents of the R register are synchronized with the refresh signal to place the low-order 8 bits on the address bus. This operation is all performed by the MPU and, therefore, dose not need a special processing by program. The MPU operation is not delayed by this operation. During refresh, the contents of the I register are placed on the high-order 8 bits of the address bus. (<) Index registers (Ix, IY) ‘The two independent index registers IX and IY hold the 16-bit base address when used in the index addressing mode. In this addressing mode, the memory address obtained by adding the contents of an index register to the displacement value (for example, LD IX+40H) is specified. This mode is convenient for using data tables. Also these registers can be used separately for memory addressing and data retaining registers. (d) Stack pointer (SP) ‘The stack pointer is a 16-bit register to provide the start address information in the stack area in the external RAM. The content of the stack pointer is decremented at the execution of a CALL instruction or PUSH instruction or interrupt handling and is incremented at the execution of a return instruction or POP instruction. At the execution of a CALL instruction or interrupt handling, the current content of the program counter is saved into the stack. At the execution of a return instruction, the content is restored from the stack to the program counter. These operations are all performed by the MPU automatically. However, the other registers are not saved or restored automatically. For the storing of the contents of these registers, an exchange instruction (EX or EXX) for alternate register, a PUSH or a POP instructions must be used. When a PUSH instruction is executed, the contents of the specified register are saved into the stack. When a POP instruction is executed, the contents of the stack are moved to the specified register. These data are restored on a last-in, first-out basis. Use of the stack permits processing of multiple-level interrupts, deep subroutine nestings, and various data manipulation very easily. The stack pointer is not initialized in the hardware approach. Therefore, it is required to allocate the stack area in RAM to specify initialization (at the highest address of the stack area) in the initial program. MPUZB0-11

(ex) MEMORY The contents of the SP. MEMORY ADDRESS ADDRESS wstauction before the instruction . (HEX) is accepted. 5 § LOWER 7 Pa 1230 CALL. «1500H_ FFL FFEB 2 2 [a2] 3 ° : | reer es ° 1500 PUSH AF FFEF ; A=06, F=23 FEED 2 $ 1501. PUSH BC FFED : BrB2, C=CO Free | 05 | & 2 | FFEF [33 | : FFFO |

1600 POP BC FFEB

HIGHER | 1601 PoP AF FRED

1602 RET FFEF

‘The foregoing example shows the stack pointer and stack operations in which the instructions starting with the CALL at address 1230H and ending with the RET at address 1602H have been executed. However, it is assumed that there is no instruction or interrupt other than shown above that uses the stack during the execution. When the value the stack pointer before executing the CALL instruction at address 1230H indicates address FFF1H, address 1233H is stored at addresses FFFOH and FFEFH because the CALL instruction consists of 3 bytes, then the stack pointer is decremented. Similarly, the data are saved or restored sequentially according to the instructions. These stack and stack pointer operations are all performed automatically. (e) Program counter (PC) The program counter holds, in 16 bits, the memory address of the instruction to be executed next. The MPU fetches the instruction from the memory location indicated by the program counter. When the content of the program counter is put on the address bus, the program counter is incremented automatically. However, it is not incremented with a jump instruction, a call instruction, or interrupt processing. Instead, the specified new address is set on it. With a return instruction, the content restored from the stack is set on the program counter. These operations are all performed automatically and therefore, no care is required for programming. MPUz80-12

[2] Halt Capability When a HALT instruction has been executed, the MPU is put in the halt state. The halt capability can be used to halt the MPU against the external interrupts, thereby reducing the power dissipation. In the halt state the states of MPU’s internal registers are retained. The halt state is cleared by reset or when an interrupt is accepted. For the details of halt operation, see [3] “Basic Timing”. (1) Halt operation When a HALT instruction has been executed, the MPU sets the HALT signal to “0” to indicate that the MPU is going to be put in the halt state. Actually, the MPU in the halt state automatically continues executing NOP instructions if there is the system clock input. However, the program counter is not incremented. This keeps the refresh signal generated when the dynamic memory is used. During halt, the MPU’s internal states are retained. By using TLCS-Z80’s clock generator/controller (TMPZ84C60P or TMPZ84C61AP), the clock input control for these halt operations is realized easily. (2) Releasing the halt state The halt state is cleared by accepting an interrupt (the INT or NMI signal input) or by reset (the RESET signal input). When an interrupt is accepted, the halt state is cleared and the interrupt handling routine is executed. However, a maskable interrupt (INT) cannot be accepted unless the interrupt enable flip-flop (IFF) is set. Note that when the halt state is cleared by the RESET signal, the MPU is reset and the program counter is set to “0”. [3] RESET Signal Holding the RESET pin at the low level (“0”) under the following conditions, the MPU’s internal states are reset: (1) The supply voltage level is within the operational voltage range. (2) System clock stabilization. (3) Holding the RESET signal at the low level (“0”) for at least 3 full clock cycles. When the RESET signal goes high (“1”), the MPU starts executing instructions from address 0000H after at least 2T state dummy cycles. When reset, the MPU performs the following processing: (1) Program counter 0000H is set. MPUZ80-13

(2) Interrupt The interrupt enable flip-flop (IFF) is reset to “0” to disable the maskable interrupt. For the maskable interrupt processing, mode 0 is specified. (3) Control output All control outputs are made inactive (“1”). Therefore, the halt state is also cleared. (4) Interrupt page address register (I register) The content of the R register becomes 00H. (5) Refresh register (R register) The content of the R register becomes 00H. The contents of the registers other than above and the external memory do not change. ‘Therefore, they must be initialized as required. [4] Interrupt Capability ‘The interrupt capability is used to suspend the execution of the current program and execute the processing of the requested peripheral LSI. Normally, this interrupt processing routine contains the data exchange and transfer of status and control information between the MPU and the peripheral LSI. When this routine has been completed, the MPU returns to the active state before the interrupt has been accepted. The TMPZ84CO0A provides the non-maskable interrupt (NMI) and maskable interrupt (INT) capabilities which are detected by the NMI and INT interrupt request signals, respectively. A non-maskable interrupt, when caused by a peripheral LSI, is accepted unconditionally. This interrupt is used to support critical functions such as the protection of the system from unpredictable happening including power failure. A maskable interrupt can be enabled or disabled by program. For example, if the timer is used and, therefore, an interrupt is not desired, the system can be programmed to disable the interrupt. Table 3.1 lists the processing by interrupt source. SSS MPUZ80-14

(1) Interrupt enable/disable A non-maskable interrupt cannot be disabled by program, while a maskable interrupt can be enabled or disabled by program. The MPU has the interrupt enable flip-flop (IFF). A maskable interrupt can be enabled or disabled by setting this flip-flop to “1” (set) or “O” (reset) through an EI instruction (enable) or a DI instruction (disable) in program. Actually, the IFF consists of two flip-flops IFF1 and IFF2. IFF1 is used to select between the enable and disable of a maskable interrupt. IFF2 holds the state of IFF1 before a maskable interrupt has been accepted. Both IFF1 and IF F2 are reset to “0” when any of the following conditions occurs, disabling an interrupt: e MPU reset e Execution of DI instruction e — Acceptance of maskable interrupt Both IFF1 and IFF2 are set to “1” when the the following condition occurs, enabling an interrupt: e Execution of El instruction Actually, the waiting maskable interrupt request is accepted after the execution of the instruction that follows the El instruction. This delay by one instruction is caused by accepting an interrupt after completion of the execution of a return instruction if the instruction following the EI instruction is a return instruction. In the above operation, the contents of IFF1 and IFF2 are the same. MPUZ80-15

Table 3.1 Processing by Interrupt Source Interrupt Interrupt Source Priority | Programmed condition Vector address return instruction Non-maskable interrupt ‘Address 66H RETN {the falling edge of NMI) Instruction from Maskable interrupt (INT. 2 IFF=1 Mode0 | peripheral LSI. (Note) becomes “0” at Normally, CALL or RST RETI instruction's last clock) instruction. | Mode 1 | Address 38H. The address indicated by the data table (memory) at the address specified by | register (high-order 8 bits) and data from peripheral LSI (low- i order 8 bits, [SB = "0”). 60089 Note: Mode 0 applies when the instruction from peripheral LSI is CALL or RST instruetion, Parity flag (REIN) (LDA, lor LDA, R) (Determination of { IFF2 i actual INT enable Fr (For holding IFF1) (disable) Executed instruction oO oO : MPU reset. Di instruction INT acceptance 1 1 : Elinstruction RETN instruction when IFF2=1 oO state of IFF1 NMI acceptance before NMI acceptance 0889 Figure 3.4 Interrupt Enable Flip-Flop (IF) ee SSSSSSSSSSSSSSsSSSsSSSSSSSSsSSSSSSSSsSSFSSSeSSee MPUZ80-16

When a non-maskable interrupt has been accepted, IFF1 is reset to “0” (interrupt disable) until an EI or RETN instruction is executed, so as to prevent from accepting the next interrupt. For this purpose, the state (interrupt enable/disable) of IFF1 immediately before non-maskable interrupt acceptance must be stored. This state is copied into IFF2 upon acceptance of a non-maskable interrupt. The content of IFF'2 is copied into the parity flag at the execution of the following instructions, so that the copied data can be tested or stored: e. The load instruction (LD A, I) to load the contents of the I register into the accumulator. ° The load instruction (LD A, R) to load the contents of the R register into the accumulator. When the return instruction (RETN) from the non-maskable interrupt is executed, the contents of the current IFF2 are copied back to IFF1. If an operation which changes the contents of IFF2 (due to the execution of EI or DI instruction, for example) has not been performed during interrupt handling, IFF1 automatically returns to the state immediately before the interrupt acceptance. Table 3.2 lists the states of IFF1 and IFF2 after execution of interrupt-related instructions. Table 3.2 State of IFF1 and IFF2 [operoionsequene |r [| tenes | NPU reset 0) El 1 NMI acceptance 0 Wa! * Parity flageIFF2 RETN 1 [FF 1<—-1FF2 LDA,R * Parity flagcIFF2 INT acceptance 0 RETI * €l 1 NMI acceptance 0 DI Cy) RETN * Note : *=no change os0e89 (2) Interrupt processing With a non-maskable interrupt, the internal NMI flip-flop is set to “1” on the falling edge of the interrupt signal, NMI. The state of this flip-flop is sampled on the rising edge of the last clock of each instruction to accept an interrupt. A maskable interrupt is accepted if the interrupt signal INT is low (“0”) on the rising edge of the last clock of each instruction and the interrupt enable state (IFF=1 and BUSREQ signal=inactive (“1”)) is on. The following is the processing to be performed after a non-maskable interrupt and a maskable interrupt are accepted: MPUZ80-17

(a) Non-maskable interrupt (NMI) When a non-maskable interrupt has been accepted, the MPU performs the following processing: 1 The internal NMI flip-flop is reset to “0”. 2 IFF1 is reset to “0”, disabling the maskable interrupt. The contents of the IFF1 immediately before the interrupt acceptance are copied into the IFF2. 3 The contents of the current program counter are saved into the stack.

4 The instructions starting from non-maskable interrupt vector address 66H are

executed. A non-maskable interrupt processing program terminates after executing the RETN instruction. This return instruction performs the followings: 1 The contents of the current IFF2 are copied into IFF1. 2 The contents of the program counter are restored from the stack. Acceptance of non-maskable interrupt (NMI) Execution of ordinary program Address 0066H Execution of RETN instruction Figure 3.5 Non-Maskable Interrupt Processing (b) Maskable interrupt (INT) When a maskable interrupt has been accepted, the MPU performs the following processings: 1 Both IFF1 and IFF2 are reset to “0”, disabling the maskable interrupts. 2 The contents of the current program counter are saved into the stack. 3 A maskable interrupt is serviced in one of the three modes 0, 1 and 2. A mode is selected by executing the instruction IMO, IMlor IM2 before the interrupt is serviced. The instructions are executed starting from the vector address corresponding to the selected mode. MPUZ80-18

TOSHIBA TMPZ84C00A, The LSB of the table pointer is set to “0” because a 2-byte data is needed to specify the service routine start address in 16 bits and start that address from an even-number address. In the table, the start address begins with the low-order byte followed by the high-order byte as shown in Figure 3.8. Interrupt in mode 2 Table Execution of ar RET! instruction Iregister TLCS-280 family byte peripheral LS! | | osoae9 Figure 3.8 Interrupt Processing in Mode 2 Mode 2 is used in the daisy chain interrupt processing using TLCS-Z80 family LSI. TLCS-Z80 family peripheral LSIs all contain the interrupt priority controller in daisy chain structure. In this interrupt structure, the interrupt request signals are connected one after another and given priorities for processing when two or more maskable interrupt requests occur at.a time. Only the interrupt vector from the peripheral LSI having the highest priority is put on the data bus. By receiving the interrupt vector in mode 2, the processing for that peripheral LSI can be performed. When an interrupt requested by a peripheral LSI having a priority higher than that of the current peripheral LSI during the execution of the interrupt processing routine, the higher priority interrupt can be enabled by the El instruction to form an interrupt nesting. The maskable interrupt processing program terminates by executing an RETI instruction. This return instruction performs the following processings: © Restores the content of the program counter from the stack. © Notifies the requesting peripheral LSI of the termination of interrupt processing. MPUZ80-20

3.3. MPU STATUS TRANSITION DIAGRAM AND BASIC TIMING The following describes the MPU status transition and the basic timing of each MPU operation. (1] _ Instruction Cycle Each TMPZ84COO0A instruction is executed by combining the basic operations of memory read/write, input/output, bus request/acknowledge, and interrupt. These basic operations are performed synchronizing with the system clock (the CLK signal). One clock period is called a state (T). The smallest unit of each basic operation is called a machine cycle (M). Each instruction consists of 1 to 6 machine cycles and each machine cycle consists of 3 to 6 clock states basically. However, the number of clock states in a machine cycle can be increased by the WATT signal described later on. Figure 3.9 shows an example of the basic timing of a 3-machine-cycle instruction. The first machine cycle (M1) of each instruction is the cycle in which the Opcode of the instruction to be executed next is read (this is called the Opcode fetch cycle). The Opeode fetch cycle basically consists of 4 to 6 clock states. In the machine cycle that follows the Opcode fetch cycle, data is transferred between the MPU and the memory or peripheral LSIs. This operation basically consists of 3 to 5 clock states. Toycle CLK | MT } Te | 13 | Te | Tr | T2 | Ts | tT: | t2 | Ts Maachine cycle Mi M2 M3 (Opcode fetch) (Memory read) (Memory write) Cycle instruction 00885 Figure 3.9 Example of MPU Basic Timing (3-Machine-Cycle Instruction) eS MPUZ80-21

[2] Status Transition Diagram RESET -0 1 MT IMMEDIALELY AFTER ACCEPTING INT ? a ca as Law [eee JS 2 bw ‘pa [“Tom-0 rwwer aw vw ; Come] Kat <i> ws we ro wo cous Figure 3.10 Status Transition Diagram MPUZ80-22

[3] Basic Timing (1) Opcode fetch cycle (M1) In the Opcode fetch cycle, MPU fetches an Opcode in the machine-language codes in memory. This is also called the M1 cycle because it is the first machine cycle to execute each instruction, Figure 3.11 shows the basic timing of a basic Opcode fetch cycle. In clock state T1, the content of the program counter is put on the address bus. The Mi signal goes “0”, indicating-to the MPU that this is the Opcode fetch cycle. At the same time, MREQ and RD signals go “0”. When the MREQ signal goes “0”, the address signal has already been stabilized. Therefore, this signal can be used for the memory chip enable signal. The RD signal indicates that the MPU is ready to accept the data from memory. By these signals, the MPU accesses memory to fetch the Opcode in the instruction register. The MPU samples the WAIT signal on the falling edge of clock state T2. If the WAIT signal is “0” on the falling edge of clock state T2 and the following wait state (TW), the next state becomes clock state TW. Figure 3.12 shows the delay state of the Opcode fetch cycle caused by the WATT signal. ‘The data (Opcode) on the data bus is fetched on the rising edge of clock state T3 then, the MREQ, RD, and MI signals go “1”. In clock state T3, a memory refresh address is put on the low-order 8 bits of the address bus and the RFSH signal goes “0” and the MREQ signal goes “0” again. This signal indicates that the memory refresh cycle is on, At this time, the contents of the I register are put on the high- order 8 bits of the address bus and the 8 bits of the R register are put on the low- order 8 bits of the address bus. By using the RFSH and MREQ signals, memory refresh is performed in clock state T3 and T4. However, the RD signal remains “1” because the contents of the memory refresh address are not put on the data bus. In clock state T4, the MREQ signal returns to “1”. The refresh address is kept output until the rising edge of the clock state Tl in the next machine cycle, keeping the RFSH signal set to “0”. The cycle delay state caused by setting the WATT signal to “O” is the same in the memory read/write, input/output, and maskable interrupt acknowledge cycles. The diagram of the cycle delay state caused by the WAIT signal set to “0” is omitted in the following description. SSS MPUZ80-23

| th T2 T3 Ta Tr REQ STALL e\\1[1| 777 rs we [17 VL rs | "> an RFSH ai wow Figure 3.11 Opcode Fetch Timing —_ Micycle

1 Tz Tw Tw 3 Ts

Ao~Ats IX] __Programcounner_| | | X__Refresh agave 1 vate ATT ALA . So oo, PEt Ty Warr —a lal ei Figure 3.12 Opcode Fetch Timing Incliding Wait State MPUZ80-24

(5) Maskable interrupt acknowledge operation Figure 3.16 shows the basic timing of the maskable interrupt acknowledge. ‘The MPU samples the maskable interrupt request signal (INT) on the rising edge of the last clock of each instruction execution. If the INT signal is found “0”, a maskable interrupt is accepted except in the following cases: @ The interrupt enable flip-flop is reset to “0”. © The BUSREQ signal is “0”. When a maskable interrupt has been accepted, a special Opcode fetch cycle is generated. In this cycle, 2 clock states of wait state (TW*) is automatically inserted after the clock state 12. The WATT signal is sampled on the falling edges of the second clock state TW* and the following clock state TW and, if the WAIT signal is found “0”, the instruction cycle enters in the next clock state TW. In this Opeode fetch cycle, the IORQ signal goes “0” in the first TW* state instead of the MREQ signal while, in a normal Opcode fetch cycle, the MREQ signal goes “0” in clock state T1. This indicates to the maskable interrupt requesting LSI that the 8- bit interrupt vector can be put on the data bus. The MPU reads this data to perform interrupt processing. Therefore, the contents of the program counter put on the address bus are not used. Unlike an ordinary I/O operation, the RD signal does not go “0”. In clock state T3, the memory refresh address signal is put on the address bus for memory refresh like normal Opcode fetch cycle and the RFSH signal goes “0”. In the subsequent machine cycles (M2 and M83) , the contents of the current program counter are saved into the stack. In machine cycles M4 and M5, the contents of the I register (the high-order 8 bits) and the contents of the address indicated by the address of the vector (the low-order 8 bits) from the peripheral LSI are fetched in the program counter. MPUZ80-28

= last M cycle § Aa vs >] LastT j__state an T2 13 Ta Ts Th cLK nwt “DS Lo 7 NMi internal ~T7, - latch \\e--- Ao~Ars | TX Program counter |X Refresh address) ees a a LA a <= 28 = RFSH x | 60889 Figure 3.17 Non-Maaskable Inpterrupt Acknowledge Timing (7) Halt operation When a HALT instruction is fetched in the Opcode fetch cycle, the MPU sets the HALT signal to “0” synchronized with the falling edge of clock state T4 to indicate it to the peripheral LSI and stops operating. If the system clock is kept supplied in the halt state, the MPU continues executing NOP instructions. This is done to output refresh signals when the dynamic memory is used. The NOP instruction execution cycle is the same as the ordinary Opcode fetch cycle except the data on the data bus are ignored. The halt state is cleared when an interrupt is accepted or the RESET signal is set to “0” to reset the MPU. Figure 3.18 shows the halt state clear operation by interrupt acknowledge. An interrupt is sampled on the rising edge of the last clock (clock state T4) of the NOP instruction. A maskable interrupt can be accepted when the INT signal is “0”. A non-maskable interrupt is accepted when the internal NMI flip-flop which is set on the falling edge of the NMI signal is set at “1”, However, it is required that the interrupt enable flip-flop is set to “1” for a maskable interrupt to be accepted. The interrupt processing for the accepted interrupt starts from the next cycle. MPUZ80-30

3.4 TMPZ84CO0A INSTRUCTION SET

This subsection lists the TMPZ84CO0A instruction codes and their functions. The table below lists the symbols and abbreviations used to describe the instruction set. The symbols which require special attention are described in the locations in which they appear. © Symbols (1/2) [commer [om Register ng Register B,C,0,£,H, LA, t Register pair BC, DE, HL Stack pointer sP q Register pair BC, DE, HL, AF P Register pair BC, DE Index register x Stack pointer sP s Register pair BC, DE index register ly Stack pointer sp th Higher register of register pair (B,D, H) Higher 8 bits of stack pointer (SP) aH Higher register of register pair (B,D, H, A) 1X4 Higher 8 bits of index register IX Yu Higher 8 bits of index register IY PCH Higher 8 bits of program counter (PC) te Lower register of register pair (C,E,U) Lower 8 bits of stack pointer (SP) a Lower register of register pair (CE, LF) XL Lower 8 bits of index register IX YL Lower 8 bits of index register IY PCL Lower 8 bits of program counter (PC) rb Bit b (0-7) of register (B, C, D, E, H, L, A) 120889 MPUZ80-33

e@ Symbols (2/2) [eae [ome Memory mn Memory address represented in 16 bits. m indicates higher 8 bits and n, lower 8 bits. HU» Bit b (0-7) of the contents of the memory address indicated by register pair HL. (iX+d)p Bit b (0-7) of the contents of the memory address indicated by the value obtained by adding 8-bit data d to the content of index register IX. (YY +d)p Bit b (0-7) of the contents of the memory address indicated by the value obtained by adding 8-bit data d to the content of index register IY. Flag change symbol 0 Reset to "0" by operation. 1 Set to “1” by operation. - No change . Affected by operation x Undefined P Handled as parity flag. P=0: odd parity P=1: even parity v Handled as overflow flag. V=0: No overflow V=1: Overflow Operator oe Transfer ° Exchange + Add - Subtract A Logical and between bits v Logical or between bits. ® Exclusive or between bits Others \\FF Interrupt enable flip-flop cy Carry flag z Zero flag 720888 MPUZ80-34

TMPZ84CODA Instruction Set (1/9) roe mse |_| St) wt eww ie [ow cocenf Onno 8 os Joseudesed esnebacedeersndeernbern 9 | 900 coe .9e¢ ded dd . oe oe on on eo OL err 110 | A6erxe poe Po rare wvonof $4.808.988.. 14 seo Ld Lede alan to (ae on te eee veer (Wier ESET SSE SEY a7 to (ates) e/a oad tor” 00 (lieder ee eee See 6 dde dds |e bb Eeudunsedeind to Gyedje Pan ta tar Yeo (ivea)er SPTPePLEPOPIEL Ys Pie ° 01 110 ere | 704e pe i gg fa GbR NP ae Ga Ber Pao Gated SPDPRPIER POOLE sis 4 dd ddd ddd cl H i [Car cccey pee CORREO U7 he ee ed r oo 110 110 36 i Pilg @ |is a (ae) 0" oon" oid" | od “Tae (ae) ve eboryerry bobby (57 A,(0F) 00" it 010°] ia ae(oe) sisikieiet ep ete (al 3 iB "A Gay" o0" tT 010" Yan ae(en) vpcpr serps ers ay as Bae) YA Y00" 000" 048 Poa ee weyers be} 9 iw RT toe ton Pea pace carer erat ar healer) = 92.010 141.187. 7 se ccseoenenee senbeveed Posnscedeseed os oo 7 OX 000 1tt a7. foccd decd cedeccndeecen dened . PS no nn ann | pi i tye as a non aoe |m Poi bed woo Okan ii oii tor] 90" Titan SPIT PST PS Poe DE} o1 = 00 100 901 | 21 PET me | 10 MPUZ80-35

TMPZ84COO0A Instruction Set (2/9) fers] Assembler ° x | —msemone —B0ay [vex | Fntion Q ae Ce Tema a es 00 t00 oo: Jat i [ce CCA CC i ie Pe eis O90) MEd ETT en ane naa | L(ao) : : ac foo ame ene | ae Oe ve |or io enya te ton P26 precaal) mee rey oP eT geP we [10 or eet or | aaeexeao | regan) selit ie "ax, Gaay Pay ous aa” Poe ah ct ne Pais aoe eae eee Gre ey 00 ti 010 J2a Tr(an) i Pam cs CC sprdyiiiyeritiyp erie ° oo 10: 010 | 2a 1ye-(an) : fea (COC CR Ce / ed es Cee eee rie) a sana ana | enjrt Le Gan Pa ios aad Yew enviirig SPIDEY PLE ITIP Ty sD ae . or eo or faaeexca0 | (an)t Pan Cerconc eee PRTC Ree Ecsta ceriyiviyericicp yi ca 00 100 010 | 22 (en)IX, : i cme om Caen CRTC Gaiety ~ shrtytriyirbricb abe 00 100 10 | 22 (onyety, : Coat ae CC cys rer saps io sein] a ei tai” Yoo ‘Seek DeITH PITS ayie ie ea ae aaa tai” Yo sei SSP PEPlELy ay Ge wish" 14 gad Yor fesse RIS” | (SPRY aL (SPT ay, ie ee eee er) TC - SPe50-2 iL Be foo ist HK if Git isi Yoo (SP-2 BRS TE ape] oe on 41100 102, Jes |sPese-e ibd i L| at 20 Fi WV iy ti tei” f0 (Seaweed arf ai tooir [es |spesp2 i cloud unducebunedunck 00g ii" qqo" O03] eavaiea” | aye (SP ri) gee( SP), ceoypriyp pers | ay ie cee) SPHSPH2 . ‘

960 HY ii oi tei” Poo Txye(SP et) LR SRY vheyprryp ects ayia

ti toa.001 [ex | spespaz een eee ee bee WV Gait iar” Pro Bye (SPi) HHS) cereybriyp reel) yy ia 41 100 001 [e 5Pe5P42 L 06m i ioron [ee |oewnt Bx aR We Po0" 068 000" Toe Parana Ga ii 017 ocr Joa C8 wi at st” Note + tianyolthereghter pars8C, OF, HL.SP sanyo! the regster pais AF, 8C. DE, ML. (PAR (PAIR), refer to high order and low order eight bts ofthe register pair espectnvly (Ex) BC, =C,AFy= A. a1: ExcHANGE 120089 MPUZ80-36

TMPZB84CO0A Instruction Set (3/9) es 8 " = [ex _(S*), ML] 11100 011 [e> [Fe Gsreiy cots) Tinikinihie iain, fe Gee Par eet tor" foo. ike (3Pe1) Bap Phhpbhs ibs ¢ 14100 014 Jes nL Bae (SP) cdeedecebeea Focadocd & fee owe far ior ro ivye(SPsi) Dery ely Preis i 11 100 013 [es isis _ wor itor tor YD {0 F(HE)DEGEE SST we] ap 10,100 000, a0 Huestet Be bodotide ited ooh. Loa” 12101 101 oo (DE )+ (HL), DE*OE +1 with LOK: @ F058 21] [8c< 0) 1a 110 000 fo Lehr 8CeBC=1 Repeaturt 16-80-07 [too if ioe HOF Peo oe ei) EET SPDT OT yo ie te to 102 000. |e HLet-1,ae+80-1 Lede : Pearcy in ior tor feo" (oe ec) dee SPIES ETT ES Bi] rec > 0) cw 10 111 000 | 8a HL+HL-1,BC+BC-1 Repeat until A i 16 | *[8C-0) we [CPT An 101 408 > ‘AR(HL) Soy ee ays 16

4 Jt 100 001 far Pacem sa eceac-3 : ode nbonl

oo aie it toi ior” feo c(wcyotbentsi36ebE0 PSE EET PTY spar] pee oa a oo] t0.110,005,. au, [Repeacuntsascatyorecso fn ro) hog (wo ry retretren rs) (HL) PeQeeh ey Pye y es we] “Ge . 40.191,008,. |a9,. fmtentavecepend, eM oa iter a0” Jeo Roti tenia, weeaeea | SENET S YET Y EST SP aa orece v0 8 10 121 001 | 89 Repeat until A=(HL Jor BC=0 a se} As > (uty) A00,,Art ns) 32.900-Fer [aor baAer EREPeCET eR EEE oar fos ain" [a8 ooo 118” Jes aches PEPE yore apa iba "A GAL) Fab He” Tae aaa coher seevcos apa tae fo "Ai (axedy Pie ont to” foo hehe( tied) Pee ey ogee Ps Piel Span . to 000 110 |e Pee Bee 2 oa.aad asd. | ssa sdecdembendedand J 0 [oto Ra ccmenccoyn rrettetion ty weasiiveay peer ser voae sey isd eon ® 10 000 110 [36 pid w {S00 é ae aaa cea, | — lend User EP aa Gai ree Paws Paes “pee ey aes a afia ¢ AOC Ayn 11001 110 [ce Aemenecy eceikieixivigie 7 CACO ECTS Ca cS ee eee er rer ; S fave a Gad)" 1 ott tot” Too eke ikea x0 Pee yeas | apis = ro 00. 130 fee ni Fa ee ee ane ne a ee face aaa Par aay tor fro Bean (aveaynee SPORES EVES PT Se : to 001 110 |e : Fs nf 8.998.480. 8 , en a sig eo ota eee fader facta mn eeriyens tet pey © [see i1 o10 110” oe Reha SPST PPV RT VET Pe 7 sus "(hesdy” Pir ott a0 foo fea (tReay Debetbey tpi xo 010 110 [6 : o4.ddd ed@ 1d... oc et ee eee ee ai G¥eay fr tir aor T6 aeacyaveay SEPVEP EPP TES eps 10.010 110 | 98 : H A i de ese ate_|o i i Note: *M Pwtag wolfe resuitot BC—1 wO,otherwise PA «1 SH Zags HA (M0 otherseZz <0 {indicates the otal condition ofthe number of eclesand states indicated by aro ‘meansany ofthe repter 8,9, 6-H sone ee MPUz80-37

TMPZ84COOA instruction Set (4/9) cuss Assembler or jor ter | —moemone [Bay [ten | Funetion o: | SCA an rd Ce Se eae DY Be ‘SBC ALN 1 oil 110 | OE Ar A-a-CY ebebxberxi verse] 2] 7] e[o00 navn nnn | a jeseesencebrencebeenschereseetbere ¢ Joon sae Aw Ao eat 0 ae RRL See EV ET EST ap a] 0 fow Sec A,(rked) P11 O12 201" Yoo Avi=(Tked) OY eT See VS oe) ef ig] fon wo om 110 [ot : | 100 de 40d cod [a . cb EEL for BE MG | aE ior Po aaa) 4 shetyivtyiviitep bie] alin 19 on 110 {9 94, oad aad Ja ~ oes seddseendeetedentseceeedenn be ea Seca ee ee als < [aoe 11 100 110 | E6 AAA oboe eV ix: polo} af 7 ae a a = SUES TE ER Ore] a7 & fa” cresay" 7 14 “ios “00 mead) seer ee oo [sp is ° 10 100 110 [As i 44 442 ace, |e bee css bb © Jano” (Yea) iin tor [Fo AeAA(LY 8d) eek asks POLO] 8) 19 z 10 100 110 |A6 i < 34 dad aed |e Fda [RTE TTT ae Tie ree eae eave SKS eee ay = on" a iio 100 Fe ieavi Pepeyrory?e rete Papo we [oR GHC) 10110 140" Pa Pa ea) woeTero x eo ol et 7 & Joa (aieay Yar oni “iat” Yoo icaye tied) SPO EP Too | sp ae z 1 11a 110 fos : es aot ase [a cee | edeabenedeanel [oR (ive}" af nia gor] 0" mea ( Tid) sere oix: P igio] 5/19 < 10 110 110 | 86 . aa oat tea [a oe = pigs" io tot ere [Ager aeaee. wee oe eee ayy @ fons Preeti a Ee eee ee ee Sees i © Pitt io tor aio Tae fase i)” seen rebel y HOR {1X+6) tom 101 [00 Rony Tied) ere ier ox: RP foro] 8] 19 10 wi 110 Jae : . 4,404,204. |e tasers sgnctenersseressecernreeepseefcveecsefremnnseguan snd eve HOR {1¥+d) i 1 101 | FO Rony ( T¥ed) erelaloix: Pi e:o] 5/19 to wx 110 | ae ae i wr to'tit ree [ase ae coe eoe sy espe y ye bala en Wie a0" Te ras Pew ey ay a ew tere ae fear eee re eps) cP (1xed) M1 O11 tor [00 A-( Tid) ere oes ie wate) 6) ie wou iio [aE err Cee TCT icity PPP E WT eT elie win nie foe iver 0° rrr 00" [oasex@ rors ogo vos spate nc" (Hl)'"""} 00"110 "100" | 34 Gia @ggat ees ot] ay The Ray PET aan aE Pw Cased (koa Peeeyeeiy iv rors | ep aa 00 110 100 | 34 i i 2s oot 43 |e i Note F means any of the regsters A, B.C, 0,€, HL. 0089 MPUZ80-38

TMPZ84COOA Instruction Set (5/9) se] NN [Zany [ne] & ye PIN (Tyee) i itl 103 [FO (Bia) CD ied poL woe iki*ikiviai- 23 : ao 110 100 | 34 ppb ig Boece oa ere “ton ase “fei seeegeeiyey rho} pal fee F a foke 77 ity "| 00 tie tor fae Mic jeqitjet SPORE Ey ewer ee [a and poe = Ufo (raed) |v et a02 00 (iaedje(ieraj-i SOLEET EE WET TE] ofan [oon 2° a4.ead aoe. | 7 Sedge eed ben don E fou cd Coe eae ECT (iveaieitveS A Seeeeyive writ} ep al a fio es oo 130 101 [as ppppisrl Uo 2% as cad ase |e i i alin = 0m. feo-t004 er Dacjasl_sejuat scemulater] = dex -ie abe Bleu Go ie in fae ee * SPripipe re tia [wes iY tor tor” eo aeo-k eres cee cee rl iy é a1 000109, [aa . hedwdocbomtond eee sot in” far eer Sees 2| scr foo tio tir” far dove : So ea ape 5] ior 69" too" "to0” 96 ne opeestion Seals Sofia at tie aio [76° Ld ated Sor ipa

2 Glo AL iio “oir | es "eres Pee ee oe ed

oie iii oie” Tre iret fo eb aps elfen 103 ion” feo Set intenvust made SPIT SIT yap ad 01,900 110 | 48 fo douedocidean founded see} ii otto fed Sat iterapt ode Syrrigprisicp aye ge . on o%0 110 | s8 ; as Sele? a1 101 Yor | eo Bet intertupt mode 2 ee Sees oes ard od o1gin 110 | se i WOD__Mt_.]00 tei 001 fosvexto [mse ae ee papal pe moc wa] OL iai Peo pretend PEE TT ETO ve | ap 8] ae foo a3. t2i 010, | exrecro a ee se | ox ye fase HEE on aan feo Wishlcicey see were] apa] a |o = ay wo 010. | a2enxio . Cobo so} S [A00 Ike 11011 161 00 Ike 1X49 et oe oe cee nas 8 z {oo et 001 lorspxio | Li dedd alee = nS a ar ier] ro Weiss DPDEP EWTN IPO TS | ap Ga] Be yeo z oo s33 001, |osesxte codowbos oben}. | oe{ar < fives Go" et0 018 Possen ia {esi am ciypenebscrspspapve] a |io fie a i oir 101” 60 Tiere SODESPTERT DDE yaaa se fan =| oe 190 01: | 23 . . Ll La 8 pie aint ioi fo vei Semegereye Selly ey ie] Tete 2 00 200 011 | 23 . J odocduwedead rary Bee op ect oir | overt [ee CpEerecispers copy) oefen oes Tour aet | bo Teil SPDETIPP DPD TP ay aad nr fa0 Joo so1 on | 28 . fa on a seus bec TY iy ay t01 | ro Wety-a eieixi-ix frie 0 oo sot on [a He fie een feo LY $ i 8 x im Note + sssanyottherepiter pais 8C.05,HI,SP. PPisanyof the register sas DE. ‘tisanyof the regnterpaws 8C 06.15? 12069 MPUZ80-39

TMPZ84COOA Instruction Set (6/9) mr eo oi a far sieinloix:-ioiedal x i ARCA oo oor asi | ar -isixloixi-joe|ala oy oo ox iu far -ieixioixi-jo ef ala Rie “Viv coro ce . ~ =“ ae aie ee eer ee ed Oe) Bd Bd oo 000 rer | 00K a 8 [000 wie ly ii oot oii) ce phererety ee ere] aye] c foot 0 009 110 Jos ocsesioe ms o |o10 wae (eases | FF ont tt” 60 SP ee OP eT EP eT ale fou toot ont feo ol w [to 4 ded aad | (HL), (1X48), (14d) H parr a,009 110, | 06 Sd alin fate’ Giveay anni" Yeo PPPOE ROE] oY aa 11001 on [co i de vea cas |e E i a Ca ne ee ee it 001 011 | CB eieixioixieiote| 2] 8 BL aT oor 8a few ree er oe a ee eee dT a0 010 110, | 16 ae seeded we wea Aer" BO serie ee Pee] spa it 001 on [ce Cae) : i aa aes oad [a TAAL) (ra) Ee) ii i en ot Lib dcdeedad Bava] aa ot "Fo veeivre ye Pele) 6) a st 001 ont toe PEE dd ee ad 6s | a Pid H o9,o10, 110. | 16 il bo. ‘ie “Vit oor‘aii "] e8 : perp ye ere ae __| 09,001, rer. | ose POLE Bdocdoued ae (it if oot'o1t” fee serra wee ore al as ae (aaSGy YON Hat” To sreiyrviviy tery ype 1 oon ont [ce P(e) (1X8) CIF} : aa aes oot [a i RRC (TY+d) “Var iar ter™ Fo eieixroixn: Pio: *| 6f 23 i100 on Jee : : as asd oes | a zy Poa en a1 001 11” Jee seeoyeiye es vere y abe [90,011 err | 1846 nm . ay iW oot oit” fee oa Pees ars aie ieaay "| vega P80 broonntty) Seeeyrerer er ets] ea 11001 ont [8 : i aa aed cas | H H oo ort 110 te i i Note: rmesnsanyof the regaterA, 8,6 0,€.H, 120888 MPUZ80-40

TMPZ84CODA Instruction Set (7/9) sar ii oor ait [ce etek OK PR lore] 2] al eleer sta (tay Pa oar tor Too SEE Poe] ep as] e fou, 90 100 110 |26 Seg sbuntdcndennedeced ALE = ysra (He) 11 001 011 |cB eee OTR a ey ay ie “ ceca 4 00 101 110. fe ode i H wa [SRA TR Pa oad tor 00" oer lore: Pole) el as ‘sae it 001 oil [ce " ee eT ole ep tole) eye ‘SRO (ae) 11001 O11 [cB ere rkiorxie foie} alas oa dae aad |e o> GSo 8] ii i ALD mene yet ior | eo ererxrorn: ep ro:~[ sla] o, oy won ast far TED FEA ‘ino Hiei tet Peo” = eye a Pel isf 01 100 111 | 67 sG Bo) PBojmy Es cnneaf O4,bbb cee | aosdxaee | 20m aan 1 foo1 ol Bir Bay 11001 011 | cB woe lee ag ie x Pode 2 ow be ar so 130 [ase | ze iy i sfou nr 4/100 ¢ s fier Note ‘*1: Rotate digit left and right between the accmulator and location (Hi). Efi a MPUZ80-41

TOSHIBA ‘TMPZB4CO0A TMPZ84COOA instruction Set (8/9) coo] Assembler ° se anemone [Been [ver | Q Tea [a oat orf Tae Sp a1 001 011 [ce ‘Ie( The )y i ta cos oot [a o1, be» 210, | so-0x8 ce eae bisa) |i iar tor] Fo HPSTRT TERE TOT LT sy 30 ° 4s cae oad Ja 5 } 2 _ Jot ove 110, | aoenus, a hfs bye a1 oor oii” Jee mod ee ie eee ed) Oe Ec ole bee eer, [eosbeaer ; cd ESE TT] Pl-ppeee & [sev b.Gwey at oor ox | ca (Hi jyet SPIES PLEX PIPITIT GT Gs] c {oor < 1 bee 110 | cBxbx8 H bead Dior sive ebaeay a oak ior YoY aaa” morbetyeniygpreiad sg baat e fon . 11 oor ont jee i i HJ 100 ° a3 ded od | a H i cpio 2 ibe, 120, [ceexe ; Fccbocdoubonfondund | alin: e [set b.(i¥eay Pn tan tor feo (i¥edjgei SPIEYPIPS PD PIEIV 6D as ti oot oxt_ {ee Pees ES . ea dod oda [a i i i 0 [000 i ti pe 110 |cesexe pep bi + Joos RSET oon oir Yee rye SPLPP PIP PSPS 2] 8] 2 jor - 10,00, er, | sore aer : BELL sfoti ae eee CS ee Oo 0 Sblixesix ie yess) a] as] 4100 . _|ta,oee 130, |aseoxe i LLB] shies RES by (1Xea) [11 O11 101 | OD (1k+d)pee SPIPWPLEYPOPOP Lees] 6 |aao tr oor ont |e a i aha ca aot cae {a Bo . _ [ta oto, 130,[aeoxe . : 4 . ESB (aVeey Pi tae tor YEO . (1¥+4) peo SPIEL PI TST 6) 23 ti oot oit |ce : ca aed oat | oo 13 b00 110_{aesoxe : err eee ont Yes co TT ae aaa] ELE” Casea SPSS SE LLG) ye Peeersonin the wren oano : Jocfefadéreting ae sve" '00" cat 000" Ya seg SPLEP TIED PL ELT S| te] mace. awe -2 BEET Yaa a goo 8 decay coatage To Peete cece ep aww aa WeLEe a0 Ho" a09 "| 88 ifeuapestve See ETL GE 2 |mumoerinee BREE oe ton “000 | 28” iH 7s0;contnue. SESEPIERE EEE T 7 raese sn20 aa 2aa aaa |a ifzei, Pcesee SPDT E | alae ea ase EE Tadao” oe eae ee a eel jcosssnsennnseneenennnenep 8, B28, 288 5 a #291, continue, . TERETE M ate btabete he Bh. oanT Se ‘00010 000110 ‘BeB-1, 80, continue Sete eke Sees et 2. us ii ior 001 feo PCHHL Sees Sees Sees oe | cee] Conditon Note: # ave-2inthe opcode providesan etectveaddresofPC+easPCis incremented 2 betorethe addiionote, ep eel Condon

4 Sinscatesthe reference tothe ovation counter ale ofthe carer segment oo] Non

© the notaton hi (+d indcaes bit y@ 27 wnt the contents he epsie pa we ey The nctatont iar (Oto within her vegiter chou ise & asedinthe opcode prondesetfecve addressot PC +ea5Pisinremented by 2 pir tothe adétonote, i aa e| 20 Even ranty 2] 110] sgn postive sl ss] Sgonesatve ross MPUZ80-42

TMPZ84COOA Instruction Set (9/9) 2 11 101 oot feo oss Lda beedemedanedend 2 | cat ema ii cee 100 | C4exe PF Condition cismet, same as SPS EXT ISTP SPST 10K | 010 - nonnn nna fa CALL an. a S ie | ont Q ne moe ece |e iWeonditione notmetcontinue [== 2x yy zon | 100 er 11 01 001 [cs PCL+(SP). Pye (SPI) Ply le PS PLES 26K | 108 = nerve id eee” 060” [ea%eKs ” Litcondtioncsmet some asRer | ~~ x eS SSS sem [an WN ry (C) At toi 102 Jeo re(C) He+t10, only the flags eee eo aye 3 ine ii'ioi ior” Jeo CL yo(C) we BTN YL EE eT aa Yas > [INT 41101 ici Jeo (HL) *(C) BeB-1,HLHL ot RPP Ee eT TTY s Tai [800] > 10 110 910 | 82 Repeat until Bo i : Foc deeeden | AL 38] E80] [a © [two it tortor Yeo HL )+(C) ,BeB=i Hie =t ey RT TT a Tie 2 | inn 11101 101 Jeo (HL) ©(C) 8+ 8-2 HLeHL~2 ee ee eae ya (800) our (n).& 11010 G11 Jas inn eee oes Sees ee ett 2 four NE av tor aor Peo (cjer ar eke eee ie 07) = jour 11101 101 JED (C)*(ML) B+B-2 MLK oD eos oe KR OT YT aye ‘oria in toi iol] eo (heel) Be B-1 HLL ey EK OT es Tar] eaceooy ao 110 011, [83 Repeat untiB=0 a 4} 16] te) jt ouro Ya tor ve: Jeo (C)*( HL). B*B-a HUHL-i oe ee oe ee ee eee OTDR i101 tor Jeo (C)r(HL) BeB- 2 HLHL-E KoLsK kK Ki kcal |S fan] [Boo] 19 111 o10 [es Repeat unt B=0 4 [16 j +(8-0),

1 C#AO-AT ‘¢ Jece | Condition

3.5 USAGE

Basic TMPZ84CO0A configurations using memory and peripheral LSls are described below. 3.5.1 Memory Address Assignment. When the memory is being accessed, the MPU outputs address and control signals. These signals are used as the memory chip enable signals. The MPU uses 16-bit address signals to specify the addresses for 64K (0-FFFF). With systems having only one memory, memory addresses can be specified with these signals alone. When there are several memories, however, the memories must be arranged so that access is possible using 64K of space. Normally, several address buses are decoded to create this arrangement, several address buses are developed for use as one memory chip enable signal for all memories. Example: The addresses for an 8K X8-bit ROM and 8K X8-bit RAM are arranged as shown in Figure 3.21. Figure 3.22 shows am example using the MREQ signal, RD signal and address signal A13 as the chip enable signals. Address 000 8K x 8bit ROM 1FFF 2000 8K x 8bit RAM SFFF 60089 Figure 3.21 Address Assignment MPUZ80-44

TOSHIBA ‘TMPZ84CO00A

3.5.2 Connection with TLCS-Z80 family peripheral LSI

TMPZ84CO0A can connect with peripheral LSI directly. A simple connecting example of the TMPZ84C00A with peripheral LSI is shown in Figure 3.23. TMPZ84C00A AO~AI2 Address bus es 7 i Do~D? Data bi i [> wey 227K ata bus MREQ | 2 rs a og a CE CE Do~D7 Ao~Ar2 7 Do~D7 — Ao~Ai2 ROM (8K x8 bits) RAM (8K x 8 bits) eases Figure 3.22 Example Connection with Memories MPUZ80-45

Clock generator/controller TMPZ84C60P CGC i EB & = oe re Ss e¥E g TMPZ84CO0A MPU a 5 3 oe ir aor a ap a a AO~A15 TORQ i RD vo~o7 RO ee ” o BUSREQ 3) Is ae a) |e meer a £ TMPZ84C30A__ CTC ° g RESET b-J TMPZ84C4DA, 41A, 42A, 434 | SIO EET os RESET TMPZ84C20A | PIO LEE Do~p7 CLK ae ee oR aan [| [Fao [esol 7) 24 ai th || & % & & 2 git é TMPZ84C10A DMA w CLK T ee seen a Ce PEP rrr bem CPA te WR ia ° BUSREQ. | é FO | = BAI | eaeee Figure 3.23 Example Connection with TLCS-Z80 family peripheral LSIs MPUZ80-46

TOSHIBA TMPZ84C00A. 4. ELECTRICAL CHARACTERISTICS 4.1. ABSOLUTE MAXIMUM RATINGS Input Voltage =0.5~VCC +0.5 Power Dissipation 250 mw (TA = 85°C) Tsouer | Soldering 260 °C Temperature (10sec) TSTG Storage Temperature ~65~150 ToPR __| Operating Temprature

4.2 DC ELECTRICLAL CHARACTERISTICS

DC Characteristics (12) Topr= ~40°C~85°C, Vcc = 5V + 10%, VSS = OV Low Level Clock High Level Clock _ input Voltage | _[uec-as] — | vecr08 i" Input Low Voltage . vit (except CLK) } 05 v InputHigh Voltage | Vi euceptelk) | 22 Vee v 3 state Output current |Vss+0.4 S Vour +10 pA in Floating Ss Vec weaeee MpUz80-47

DC Characteristics (2/2) Eee ee [ene [moe oo] {CLK =(Note)|/am-e 15 22 Gees eooe (Operating) VILC=VIL Jamel — =0.2V iar Vec=5V pekece Bee | |e || (stand by) |Vcc-0.2V VilC=ViL=0.2V Notel — fe.K=1/TcC (MIN.) 60889 Note2 AtT4 “LOW” state after the halt instruciton fetch cycle.

4.3 AC ELECTRICAL CHARACTERISTICS (1/3)

Topr= —40°C~85°C, Voc =5V + 10%, VSS=0V AP-/AM-6 | AP-8/AM-B /AT-6 JAT-8 SYMBOL item UNIT fe] om | om ee [fee eect es |e [as | oe Po] [2 fea feoarniewantagn | «foe | = [oe fw | ee ce [Ste eam = fp fe freca ——leoartwasarnanioay [= [w= po a Pfr nta—ladrnviditG oem) [ae | [| =f | 2 [tactimrean | Clock | to MREQ | Delay oe 60 | ns ratte] oe [ie Trio neato Pos [= eo [| Fee oneon —feoawir@ toy [=e wf Clock | to RD | Delay 80 70 | ns Data Setup Time to Clock > [30] - | 30] -| os | Lie fro0o1 ——pssnewtiewiot of =| =P 3 | [ir fnwnriei—[watsevprne wont —-@ | =) [Lm | wears MPUZ80-48

AP-6/AM-6 | AP-8/AM-8 JAT-6 IAT-8 SYMBOL ITEM. UNIT em | oe | PE rere famwrmowaos | wf = [| Dm [is [rscriwin —(coatromioewy | -| | -| | | [20 frscronin —_[courriem foe | =| | - | [= | [ar [racrsn [coc toWH Joey | =| no] —| 95 | o | | [22 fracriesin [occ trow3Htoemy | - [oo] - |e] | [2s fraction cou sieA6 roe | —| | | 0] m | a [as [reanonan—[aairessabeeproroioney [ve —| | -| = | [ar fracrtonan—aoactweieRG ioe | - | =| -| | m | [as fracivoran lec stoioRoto8ay | —| | -| @| | [2s fraoiwan —[oatsubierrorowey | sf -| s| -| =| [so frecriwan—lcocsro wa yoem | -| | -| @] | [sr frwwe [eirusewien vas f - [oo | — | | [22 frecrowan [cca rowhrowy | - | | -| @| = | [22 faorwny —fooasubierroroway | asf - [ssf — | w | [se fracrovan [cca teoweyoeey | -| | -| | | [ss fram) [owustbieromiat | | -| =| -| =| [se fracroain [clea sre artery | [20] - [as] ms | [a7 [ron (atirusewam «| | - | | | | [ss [rssusneatco [susteOseuptimevecoat | so | -| | —| | peers peerimowens| of [of [=| | 49 [FacrBusacky [clock TtoBusack pelay | | 90 | = | 60 | ns _| | 41 [ractiausacks) [clocktjtoBUsACK Delay | — | 90 | = | a0 | as | | #2 [racrios) [clock 7toDataFioatdelay | — | 0 | = | 70 | os | few sar) — [=] — [+] [a [acta _|toartrondsenrontoeay | —[ | -| | | ory MPUz80-49

IAT-6 JAT-& sYMBOL ITEM (6mz) (8MH2) | UNIT Fan on] MREQ, IORQ, RD, and WR to ls | Tac) Address Hold Time | =| -[ =| -| * | a6 | TsREseTicr) RESET to Clock 7 setup Time [eo] — | | — | os | || TsINTr(Cr) INT to Clock ? Hold Time Pe] -[ | -| =| [2 frowstconan M4 #9TORG | Delay joss | - [2m] -| = | TACK(IORQ!) [Clock | to IORD | Delay [ =| |] - | 6 | os | TdcrllIORQr) [Clock t to IORO f Delay [ - {| m[ - | 6 | os | TdcHD) Clock | to Data Valid Delay | - | 130 roses Note1 AC'Test Condition VIH =2.4V, VIL=0.4V, VIHC = Voc -0.6V, VILC =0.6V VOH =2.2V, VOL=0.8V, CL=100PF Note2 Items with an asterisk (*) are non-compatible with NMOS Z80.

4.4 CAPACITANCE

TA=25°C SYMBOL ITEM TESTCONDITION | MIN. | TyP. | MAX. | UNIT | fa iMAe oe | LT Te Allpinsexcept = [= =f ‘Output Capacitance | connected to GND. [=] =} 10] Fr | cory MPUZ80-50

4.5 TIMING DIAGRAM

Figure 4.1 to 4.8 show the basic timings of respective operations. Numbers shown in the Figures correspond with those in the AC Electrical Characteristics Table in 4.3. , 1 r h cx FRO a a - @ | Ao~als “> Program,Counter [| [| k_ Refresh address] LO , | Ol. ne © fo) ® MREQ Oh ', =e_| be ° er ot Mote TT WAIT | __— mm OY = )+@ ‘ ®k ++ ® Do~D7 Kesinouroae | RFSH eo eases Figure 4.1 Operation Code Fetch Cycle TT ary Tw 13 CLK \\ i Is For AN~AIS |X] Program eoynter I yt tee Tt MREQ @I\\ i POE) i \\<® 0) @— ©, WaT [SS | | [SF Operation =i O->r" I \\ vo~o7 ys gE == r oWR ® orm \\ po~o7 rte cass Figure 4.2. Memory Read/Write Cycle MPUZ80-51

7 Tz Tw Tw B

OF | —— ao~ar | XT Por adaress | ITT 4 I atte | | i oa oS = A war NS ft elt Fe ig: Input ® +" Operation = _ ,_ 4 . | bye Te wens { am, 4 oon | Fe sy Note: 1 wait state (TW*) is inserted automatically by MPU. 060889 Figure 4.3 Input/Output Cycle i ts te Tw Tw Tw Ta oat? | INT © ro) A0~AIS [Program Counter | {| = @ j— -@ TORQ At © @ Owl] WAIT h / Note1 TLis the final state of the preceding instruction. Note 2 2 wait state (‘TW*) is inserted automatically by MPU. 060889 Figure 4.4 Interrupt Request/Acknowledge Cycle MPUZ80-52

1. PACKAGE DIMENSION 5.1. DIP PACKAGE DIP40-P-600 Unit : mm 49 2 5 1 20 ¥ | 50.720.2 | —— #8 a | ofa WUC OOO id ae f Zt eS ——— sits [254] 270289 Note1: This dimension is measured at the center of bending points of leads. Note2: Each lead pitch is 2.54mm, and all the leads are located within +0.25mm from their theoretical positions with respect to No.1 and No.40 leads, MPUZ80-55

TOSHIBA ‘TMPZ84CO0A

5.2 SOP PACKAGE

Unit: mm 49 a HARA AARORAAAARARARAS GOLD RR BOBBHBBRRHBBER u 20) 1.15Tye. | 9.35201 LstvP [os] 175402 ~ Pl £7, {S[o7) 2 = 0820.2 270289 Note: Package Width and length do not include Mold Protrusions, Allowable Mold Protrusion is 0.15mm. MPUZ80-56

oo eesssesesssssssssSsssssssSSSsSe TMP ZBACODA,

5.3 PLCC PACKAGE

17.52 0.2 Unit: mm Anoooosonns — Lo) 70 [39 U 0 q Hon) eg. q O se o| 2 q Db “| ie < q b *| & J 2 q A 3 0 0 3 q 0 vi [29 Coo ooo —* 18 28 -3 q i ator (Ie) 1576202 20289 eee MPUZ80-57

1. CAUTIONS Please observe the following cautions when using the TMPZ8400A. (1) The RESET signal input used for resetting must be held at “0” for at least 3 clocks. (2) When the MPU is not the bus master (BUSREQ=0), the memory is not refreshed because the RFSH signal is “1” and address signals are at high impedance. With systems using dynamic RAM, an external circuit is required for memory refresh if this condition persists for any length of time. Also, interrupts cannot be received when the MPU is not the bus master. (3) Whenexiting a power down operation with the MPU in hold status, supply the prescribed stabilized clock. (4) Maskable interrupt mode 2 is only for use with Z80 family peripheral LSIs. (5) Only the program counter, interrupt enable flip-flop, internal NMI flip-flop, I register and R register of the MPU are initialized. All other registers must be initialized by program when necessary. Also, set the interrupt mode to mode 0. (6) The interrupt enable flip-flop is set to “1” by the instruction following the El instruction to enable receipt of maskable interrupts. @ Only the program counter register is saved during interrupt processing. Save and restore interrupt processing routines as necessary. (8) When using maskable interrupt mode 2, a data table for the vector addresses must be created in the memory. (9) When periphral LSIs and memory are connected with the MPU on a PCB, use wiring as large as possible and the shortest routing for connecting Vss (GND) and Vee. Caution is necessary because of the large spike currents which can occur when signals change (01, 1->0) with high-speed versions. (10) As countermeasures for the above, connect a capacitor with good pulse response between Vcc and Vss (GND) of the MPU and other devices to absorb the pulse current. MPUZ80-58