TMP92C820FG

TMP92C820FG TOSHIBA | Alldatasheet

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TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/H1 Series TMP92C820FG Semiconductor Company

Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. Especially, take care below cautions. CAUTION How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = (INT0 to INT3, INTKEY , INTRTC, INTALM0 to INTALM4), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of f FPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt.

CMOS 32-bit Microcontrollers TMP92C820FG/JTMP92C820 1. Outline and Device Characteristics TMP92C820 is high-speed advanced 32-bit microcontroller developed for controlling equipment which processes mass data. TMP92C820 is a microcontroller which has a high-performance CPU (900/H1 CPU) and various built-in I/Os. TMP92C820FG is housed in a 144-pin flat package. JTMP92C820 is a 144-pad chip product. Device characteristics are as follows: (1) CPU: 32-bit CPU (900/H1 CPU)

• Compatible with TLCS-900, 900/L, 900/L1, 900/H’s instruction code
• 16 Mbytes of linear address space
• General-purpose register and register banks
• Micro DMA: 8 channels (250 ns/4 bytes at fSYS = 20 MHz, best case) (2) Minimum instruction execution time: 50 ns (at SYS = 20 MHz) RESTRICTIONS ON PRODUCT USE 070208EBP
• The information contained herein is subject to change without notice. 021023_D
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their i nherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfun ction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within s pecified operating ranges as set forth in the most recent TOSHIBA products specific ations. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconduct or Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for us age in equipment that requ ires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic ener gy control instruments, airplane or spaceship instruments, transportation instrument s, traffic signal instruments, com bustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. 021023_B
• The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implicat ion or otherwise under any patents or other rights of TOSHIBA or the third parties. 021023_C
• The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E
• For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S

(3) Internal memory

• Internal RAM: 8 Kbytes (can use for code section)
• Internal ROM: None (4) External memory expansion
• Expandable up to 136 Mbytes (Shared with program/data area)
• Can simultaneously support 8-/16-/32-bit width external data bus .... Dynamic data bus sizing
• Separate bus system (5) Memory controller
• Chip select outputs: 4 channels (6) 8-bit timers: 4 channels (7) 16-bit timer/event counter: 1 channel (8) General-purpose serial interface: 3 channels
• UART/synchronous mode
• IrDA (9) Serial bus interface: 1 channel
• I 2C bus mode
• Clock synchronous select mode (10) LCD controller
• Shift register/built-in RAM LCD driver
• Supported 16, 8 and 4 gray-levels and black and white
• Hardware blinking cursor (11) SDRAM controller
• Supported 16-M, 64-M and 128-Mbit SDRAM with 16-/32-bit data bus (12) Timer for real-time clock (RTC)
• Based on TC8521A
• Separate the power supply (13) Key-on wakeup (Interrupt key input) (14) 10-bit AD converter: 5 channels (15) Watchdog timer (16) Melody/alarm generator
• Melody: Output of clock 4 to 5461 Hz
• Alarm: Output of the 8 kinds of alarm pattern
• Output of the 5 kinds of interval interrupt (17) MMU
• Expandable up to 136 Mbytes (4 local areas/8 bank methods) (18) Interrupts: 45 interrupts
• 9 CPU interrupts: Software interrupt instruction and illegal instruction
• 31 internal interrupts: Seven selectable priority levels
• 5 external interrupts: Seven selectable priority levels (4-edge selectable)

(19) Input/output ports: 83 pins (Except Data bus (16bit), Address bus (24bit) and RD pin) (20) Standby function

• Three HALT modes: IDLE2 (Programmable), IDLE1, STOP (21) Triple-clock controller
• Clock gear function: Select a high-frequency clock fc to fc/16
• RTC (fs = 32.768 kHz) (22) Operating voltage
• DVCC = 3.0 to 3.6 V
• RTCVCC = 2.0 to 3.6 V (23) Package
• 144-pin QFP (P-LQFP144-1616-0.40C)
• Chip form supply also available. For details, contact your local Toshiba sales representative

Figure 1.1 TMP92C820 Block Diagram IX IY IZ SP LH ED CB AW XSP XIZ XIY XIX XHL XDE XBC XWA 900/H1 CPU FSR 32 bits PC 8-Kbyte RAM Serial I/O SIO0 (TXD0) PF0 (RXD0) PF1 (SCLK0/ CTS0 ) PF2 (TXD1) PF3 (RXD1) PF4 (SCLK1/ CTS1 ) PF5 ( CS2G /TXD2) P95 ( CSEXA RXD2) P96 (SCK) P90 (SO/SDA) P91 (SI/SCL) P92 Serial I/O SIO1 DVSS [4] DVCC [3] XT1 XT2 H-OSC Mode controller Port 0 10-bit 5-channel AD converter PG0 to PG4 (AN0 to AN4) ( ADTRG ) PG3 AVCC AVSS VREFH VREFL Port 9 ( CS2E ) P93 ( CS2F ) P94 8-bit timer (Timer 1) 8-bit timer (Timer 2) (TA0IN) PC0 8-bit timer (Timer 3) 16-bit timer (TA3OUT/INT2) PC5 (TB0OUT0/INT3) PC6 (TA1OUT/INT1) PC1 Serial bus I/F SBI0 Interrupt controller D0 to D7 P10 to P17 (D8 to D15) P20 to P27 (D16 to D23) P30 to P37 (D24 to D31) P40 to P47 (A0 to A7) P50 to P57 (A8 to A15) P60 to P67 (A16 to A23) P70 ( RD ) P71 ( WRLL ) P72 ( WRLU ) P73 ( WRUL ) P74 ( WRUU ) P75 (R/ W ) P76 ( WAIT ) P80 ( CS0 /SDCSH) P81 ( CS1 / SDCSL ) P82 ( CS2 / CS2A ) P83 ( CS3 ) P84 ( CS2B /EA24) P85 ( CS2C /EA25) P86 ( CS2D ) Watchdog timer (D1BSCP) PK0 (D2BLP) PK1 (D3BFR) PK2 (DLEBCD) PK3 (DOFFB) PK4 PL0 to PL7 (LD0 to LD7) ( SDRAS ) PJ0 ( SDCAS ) PJ1 ( SRWR / SDWE ) PJ2 ( SRLLB /SDLLDOM) PJ3 ( SRLUB /SDLUDOM) PJ4 ( SRULB /SDULDOM) PJ5 ( SRUUB /SDUUDOM) PJ6 (SDCKE) PJ7 (SDCLK) P87 Keyboard I/F PA0 to PA7 (KI0 to KI7) RTCVCC XT1/XT2/ BE ( ALARM / MLDALM /PK6) RTC Port 8 RESET AM0 AM1 PC3 (INT0) Serial I/O SIO2 SDRAM controller LCD controller 8-bit timer (Timer 0) MMU Clock gear L-OSC Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Melody/ alarm out

1. Pin Assignment and Functions The assignment of input/output pins for the TMP92C820, their names and functions are as follows:

2.1 Pin Assignment

0H Figure 2.1.1 shows the pin assignment of the TMP92C820FG. Figure 2.1.1 Pin Assignment Diagram (144-pin QFP) TMP92C820FG QFP144 Top view P67/A23 P66/A22 P65/A21 P64/A20 DVCC3 P63/A19 P62/A18 P61/A17 P60/A16 P57/A15 P56/A14 P55/A13 A54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/A7 P46/A6 P45/A5 P44/A4 P43/A3 P42/A2 P41/A1 P40/A0 P37/D31 P36/D30 DVSS3 P35/D29 P34/D28 P33/D27 P32/D26 P31/D25 P30/D24 P27/D23 P26/D22 VREFL VREFH PG0/AN0 PG1/AN1 PG2/AN2 PG3/AN3/ ADTRG PG4/AN4 PA3/KI3 PA4/KI4 PA5/KI5 PA6/KI6 PA7/AI7 PC0/TA0IN PC1/TA1OUT/INT1 PC5/TA3OUT/INT2 PC6/TB0OUT0/INT3 PF0/TXD0 PF1/RXD0 PF2/SCLK0/ CTS0 PF3/TXD1 PF4/RXD1 PF5/SCLK1/CTS1 PL0/LD0 PL1/LD1 PL2/LD2 PL3/LD3 PL4/LD4 PL5/LD5 PL6/LD6 PL7/LD7 PK0/D1BSCP PK1/D2BLP PK2/D3BFR PK3/DLEBCD PK4/DOFFB PK6/ ALARM/MLDALM RTCVCC XT1 XT2 BE DVCC1 DVSS1 AM0 AM1 RESET PC3/INT0 DVSS2 DVCC2 P00/D0 P01/D1 P02/D2 P03/D3 P04/D4 P05/D5 P06/D6 P07/D7 P10/D8 P11/D9 P12/D10 P13/D11 P14/D12 P15/D13 P16/D14 P17/D15 P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 5/D21 AVCC AVSS PA2/KI2 PA1/KI1 PA0/KI0 PJ7/SDCKE PJ6/SDUUDQM/ SRUUB PJ5/SDULDQM/SRULB PJ4/SDLUDQM/SRLUB PJ3/SDLLDQM/SRLLB PJ2/SDWE/SRWR PJ1/SDCAS PJ0/SDRAS P96/CSEXA/RXD2 P95/CS2G/TXD2 P94/CS2F P93/CS2E P92/SI/SCL P91/SO/SDA P90/SCK P87/SDCLK P86/ CS2D P85/EA25/CS2C P84/EA24/CS2B P83/CS3 P82/CS2/CS2A P81/CS1/SDCSL DVSS4 P80/ CS0/SDCSH P76/WAIT P75/RW P74/ WRUU P73/WRUL P72/WRLU P71/WRLL P70/RD 105 100 140 135 130 125 120 115 110

2.2 PAD Layout

Table 2.2.1 PAD Layout (144-pin chip) (Chip size 4.68 mm × 4.68 mm) Unit: μm Pin No. Name X Point Y Point Pin No. Name X Point Y Point Pin No. Name X Point Y Point

1 VREFL −2213 1945 49 DVSS2 −440 −2213 97 P55 2211 685

2 VREFH −2213 1820 50 DVCC2 −340 −2213 98 P56 2211 789

3 PG0 −2213 1694 51 P00 −240 −2213 99 P57 2211 894

4 PG1 −2213 1568 52 P01 −140 −2213 100 P60 2211 1000

5 PG2 −2213 1460 53 P02 −40 −2213 101 P61 2211 1107

6 PG3 −2213 1353 54 P03 59 −2213 102 P62 2211 1213

7 PG4 −2213 1249 55 P04 160 −2213 103 P63 2211 1321

8 PA3 −2213 1050 56 P05 260 −2213 104 DVCC3 2211 1430

9 PA4 −2213 946 57 P06 360 −2213 105 P64 2211 1546

10 PA5 −2213 842 58 P07 460 −2213 106 P65 2211 1672

11 PA6 −2213 739 59 P10 561 −2213 107 P66 2211 1798

12 PA7 −2213 635 60 P11 661 −2213 108 P67 2211 1924

13 PC0 −2213 531 61 P12 761 −2213 109 P70 1925 2211

14 PC1 −2213 427 62 P13 861 −2213 110 P71 1800 2211

15 PC5 −2213 326 63 P14 961 −2213 111 P72 1675 2211

16 PC6 −2213 224 64 P15 1062 −2213 112 P73 1558 2211

17 PF0 −2213 123 65 P16 1162 −2213 113 P74 1448 2211

18 PF1 −2213 23 66 P17 1263 −2213 114 P75 1346 2211

19 PF2 −2213 −77 67 P20 1363 −2213 115 P76 1243 2211

20 PF3 −2213 −179 68 P21 1474 −2213 116 P80 1141 2211

21 PF4 −2213 −284 69 P22 1589 −2213 117 DVSS4 1038 2211

22 PF5 −2213 −388 70 P23 1702 −2213 118 P81 937 2211

23 PL0 −2213 −493 71 P24 1814 −2213 119 P82 835 2211

24 PL1 −2213 −598 72 P25 1926 −2213 120 P83 734 2211

25 PL2 −2213 −704 73 P26 2211 −1924 121 P84 633 2211

26 PL3 −2213 −809 74 P27 2211 −1799 122 P85 532 2211

27 PL4 −2213 −914 75 P30 2211 −1674 123 P86 431 2211

28 PL5 −2213 −1024 76 P31 2211 −1548 124 P87 330 2211

29 PL6 −2213 −1132 77 P32 2211 −1426 125 P90 229 2211

30 PL7 −2213 −1243 78 P33 2211 −1311 126 P91 128 2211

31 PK0 −2213 −1354 79 P34 2211 −1199 127 P92 28 2211

32 PK1 −2213 −1464 80 P35 2211 −1087 128 P93 −72 2211

33 PK2 −2213 −1576 81 DVSS3 2211 −975 129 P94 −173 2211

34 PK3 −2213 −1701 82 P36 2211 −864 130 P95 −274 2211

35 PK4 −2213 −1826 83 P37 2211 −757 131 P96 −375 2211

36 PK6 −2213 −1953 84 P40 2211 −648 132 PJ0 −477 2211

37 RTCVCC −1962 −2213 85 P41 2211 −541 133 PJ1 −580 2211

38 XT1 −1851 −2213 86 P42 2211 −435 134 PJ2 −684 2211

39 XT2 −1574 −2213 87 P43 2211 −332 135 PJ3 −788 2211

40 BE −1466 −2213 88 P44 2211 −228 136 PJ4 −892 2211

41 DVCC1 −1360 −2213 89 P45 2211 −128 137 PJ5 −996 2211

42 X1 −1257 −2213 90 P46 2211 −28 138 PJ6 −1101 2211

43 DVSS1 −1057 −2213 91 P47 2211 71 139 PJ7 −1208 2211

44 X2 −957 −2213 92 P50 2211 171 140 PA0 −1319 2211

45 AM0 −840 −2213 93 P51 2211 272 141 PA1 −1430 2211

46 AM1 −740 −2213 94 P52 2211 374 142 PA2 −1555 2211

47 RESET −640 −2213 95 P53 2211 477 143 AVSS −1828 2211

48 PC3 −540 −2213 96 P54 2211 581 144 AVCC −1955 2211

2.3 Pin Names and Functions

The following table shows the names and functions of the input/output pins. Table 2.3.1 Pin Names and Functions (1/3) Pin Names Number of Pins I/O Functions D0 to D7 8 I/O Data: Data bus 0 to 7. P10 to P17 D8 to D15

8 I/O

Port 1: I/O port. Input or output specifiable in units of bits. Data: Data bus 8 to 15. P20 to P27 D16 to D23 Port 2: I/O port. Input or output specifiable in units of bits. Data: Data bus 16 to 23. P30 to P37 D24 to D31 Port 3: I/O port. Input or output specifiable in units of bits. Data: Data bus 24 to 31. P40 to P47 A0 to A7 Port 4: I/O port. Input or output specifiable in units of bits. Address: Address bus 0 to 7. P50 to P57 A8 to A15 Port 5: I/O port. Input or output specifiable in units of bits. Address: Address bus 8 to 15. P60 to P67 A16 to A23 Port 6: I/O port. Input or output specifiable in units of bits. Address: Address bus 16 to 23. P70 RD

1 Output

Port 70: Output port Read: Outputs strobe signal to read external memory. P71 WRLL Port 71: Output port Write: Output strobe signal for writing data on pins D0 to D7. P72 WRLU Port 72: Output port Write: Output strobe signal for writing data on pins D8 to D15. P73 WRUL Port 73: Output port Write: Output strobe signal for writing data on pins D16 to D23. P74 WRUU Port 74: Output port Write: Output strobe signal for writing data on pins D24 to D31. P75 R/ W Port 75: Output port Read/Write: 1 represents read or dummy cycle; 0 represents write cycle. P76 WAIT

1 I/O

Port 76: I/O port Wait: Signal used to request CPU bus wait. P80 CS0 SDCSH Output Output Output Port 80: Output port Chip select 0: Outputs “low” when address is within specified address area. Chip select for SDRAM: Outputs “0” when address is within SDRAM upper-address area. P81 CS1 SDCSL Output Output Output Port 81: Output port Chip select 1: Outputs “low” when address is within specified address area. Chip select for SDRAM: Outputs “0” when address is within SDRAM lower-address area. P82 CS2 CS2A Output Output Output Port 82: Output port Chip select 2: Outputs “low” when address is within specified address area. Expand chip select 2A: Outputs “0” when address is within specified address area. P83 CS3 1 Output Output Port 83: Output port Chip select 3: Outputs “low” when address is within specified address area. P84 EA24 CS2B Output Output Output Port 84: Output port Chip select 24: Outputs “0” when address is within specified address area. Expand chip select 2B: Outputs “0” when address is within specified address area. P85 EA25 CS2C Output Output Output Port 85: Output port Chip select 25: Outputs “0” when address is within specified address area. Expand chip select 2C: Outputs “0” when address is within specified address area. P86 CS2D 1 Output Output Port 86: Output port Expand chip select 2D: Outputs “0” when address is within specified address area. P87 SDCLK 1 Output Output Port 87: Output port Clock for SDRAM

Table 2.3.1 Pin Names and Functions (2/3) Pin Names Number of Pins I/O Functions P90 SCK 1 I/O I/O Port 90: I/O port Serial bus interface clock I/O data at SIO mode. P91 SO SDA 1 I/O Output I/O Port 91: I/O port Serial bus interface send data at SIO mode. Serial bus interface send/receive data at I C mode. (Open drain/output mode by programmable.) P92 SI SCL I/O Input I/O Port 92: I/O port Serial bus interface receive data at SIO mode. Serial bus interface clock I/O data at I C mode. (Open drain/output mode by programmable.) P93 CS2E 1 I/O Output Port 93: I/O port Expand chip select 2E: Outputs “0” when address is within specified address area. P94 CS2F 1 I/O Output Port 94: I/O port Expand chip select 2F: Outputs “0” when address is within specified address area. P95 CS2G TXD2 I/O Output Output Port 95: Output port Expand chip select 2G: Outputs “0” when address is within specified address area. Serial transmission data 2. Open drain/output pin by programmable. P96 RXD2 CSEXA I/O Input Output Port 96: Output port Serial receive data 2. Expand chip select EXA: Outputs “0” when address is within specified address area. PA0 to PA7 KI0 to KI7 8 Input Input A0 to A7 port: Pin used to input ports. Key input 0 to 7: Pin used of key-on wakeup 0 to 7. (Schmitt input, with pull-up resistor.) PC0 TA0IN 1 I/O Input Port C0: I/O port 8-bit timer 0 input: Timer 0 input. PC1 INT1 TA1OUT I/O Input Output Port C1: I/O port Interrupt request pin1 : Interrupt request pin with programmable rising /falling edge. 8-bit timer 1 output: Timer 1 output. PC3 INT0 1 I/O Input Port C3: I/O port Interrupt request pin 0: Interrupt request pin with programmable level/rising/falling edge. PC5 INT2 TA3OUT I/O Input Output Port C5: I/O port Interrupt request pin 2 : Interrupt request pin with programmable rising /falling edge. 8-bit timer 3 output: Timer 3 output. PC6 INT3 TB0OUT0 I/O Input Output Port C6: I/O port Interrupt request pin 3: Interrupt request pin with programmable rising /falling edge. Timer B0 output. PF0 TXD0 1 I/O Output Port F0: I/O port Serial 0 send data: Open drain/output pin by programmable. PF1 RXD0 1 I/O Input Port F1: I/O port Serial 0 receive data. PF2 SCLK0 0CTS I/O I/O Input Port F2: I/O port Serial 0 clock I/O. Serial 0 data send enable (Clear to send). PF3 TXD1 1 I/O Output Port F3: I/O port Serial 1 send data: Open drain/output pin by programmable. PF4 RXD1 1 I/O Input Port F4: I/O port Serial 1 receive data. PF5 SCLK1 1CTS I/O I/O Input Port F5: I/O port Serial 1 clock I/O. Serial 1 data send enable (Clear to send). PG0 to PG4 AN0 to AN4 ADTRG Input Input Input Port G0 to G4 port: Pin used to input ports. Analog input 0 to 4: Pin used to Input to AD conveter. AD trigger: Signal used to request AD start (with used to PG3).

Table 2.3.1 Pin Names and Functions (3/3) Pin Names Number of Pins I/O Functions PJ0 SDRAS 1 Output Output Port J0: Output port Row address strobe for SDRAM: Outputs “0” when address is within SDRAM address area. PJ1 SDCAS 1 Output Output Port J1: Output port Column address strobe for SDRAM: Outputs “0” when address is within SDRAM address area. PJ2 SDWE SRWR Output Output Output Port J2: Output port Write enable for SDRAM. Write for SRAM: Strobe signal for writing data . PJ3 SDLLDQM SRLLB Output Output Output Port J3: Output port Data enable for SDRAM on pins D0 to D7. Data enable for SRAM on pins D0 to D7. PJ4 SDLUDQM SRLUB Output Output Output Port J4: Output port Data enable for SDRAM on pins D8 to D15. Data enable for SRAM on pins D8 to D15. PJ5 SDULDQM SRULB Output Output Output Port J5: Output port Data enable for SDRAM on pins D16 to D23. Data enable for SRAM on pins D16 to D23. PJ6 SDUUDQM SRUUB Output Output Output Port J6: Output port Data enable for SDRAM on pins D24 to D32. Data enable for SRAM on pins D24 to D32. PJ7 SDCKE 1 Output Output Port J7: Output port Clock enable for SDRAM. PK0 D1BSCP 1 Output Output Port K0: Output port LCD driver output pin. PK1 D2BLP 1 Output Output Port K1: Output port LCD driver output pin. PK2 D3BFR 1 Output Output Port K2: Output port LCD driver output pin. PK3 DLEBCD 1 Output Output Port K3: Output port LCD driver output pin. PK4 DOFFB 1 Output Output Port K4: Output port LCD driver output pin. PK6 ALARM MLDALM Output Output Output Port K6: Output port RTC alarm output pin. Melody/alarm output pin (Inverted). PL0 to PL7 LD0 to LD7 8 I/O Output Port L0 to L7: I/O port Data bus for LCD driver. BE 1 Input Backup enable. AM0, AM1 2 Input Operation mode: Fix to AM1 = “0”, AM0 = “1”: 16-bit external bus or 8-/16-/32-bit dynamic sizing. Fix to AM1 = “1”, AM0 = “0”: 32-bit external bus or 8-/16-/32-bit dynamic sizing. X1/X2 2 I/O High-frequency o scillator connection pins. XT1/XT2 2 I/O Low-frequency oscillator connection pins. RESET 1 Input Reset: Initializes TMP92C820 (with pull-up resistor). VREFH 1 Input Pin for reference voltage input to AD converter (H). VREFL 1 Input Pin for reference voltage input to AD converter (L). AVCC 1 − Power supply pin for AD converter. AVSS 1 − GND pin for AD converter (0 V). DVCC 3 − Power supply pins (All DVCC pins should be connected with the power supply pin). DVSS 4 − GND pins (0 V) (All DVSS pins should be connected with GND (0V)). RTCVCC 1 − Power supply pin for RTC and low-frequency oscillator.

1. Operation This section describes the basic components, functions and operation of the TMP92C820.

3.1 CPU

The TMP92C820 contains an advanced high-speed 32-bit CPU (900/H1 CPU). For CPU operation, see the TLCS-900/H1 CPU. The following describe the unique function of the CPU used in the TMP92C820; these functions are not covered in the TLCS-900/H1 CPU section.

3.1.1 CPU Outline

900/H1 CPU is high-speed and high-performance CPU based on 900/L1 CPU. 900/H1 CPU has expanded 32-bit internal data bus to process instructions more quickly. Outline of 900/H1 CPU are as follows: Table 3.1.1 CPU Outline 900/H1 CPU Width of CPU address bus 24 bits Width of CPU data bus 32 bits Internal operating frequency 20 MHz Minimum bus cycle 1-clock access (50 ns at 20 MHz) Data bus sizing 8/16/32 bits Internal RAM 32 bits 1-clock access Internal I/O 8-/16-bit 8-/16-bit 2-clock access 5 to 6-clock access 900/H1 I/O 900/L1 I/O External device 8 bits 2-clock access (can insert some waits.) Minimum instruction Execution cycle 1 clock (50 ns at 20 MHz) Conditional jump 2 clocks (100 ns at 20 MHz) Instruction queue buffer 12 bytes Instruction set Compatible with TLCS-900, 900/L, 900/H, 900/L1 and 900/H2 (NORMAL, MAX, MIN and LDX instruction is deleted.) CPU mode Only maximum mode Micro DMA 8 channels

3.1.2 Reset Operation

When resetting the TMP92C820 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input low for at least 20 system clocks (16 μs at 40 MHz). When the reset has been accepted, the CPU performs the following:

• Sets the program counter (PC) as follows in accordance with the reset vector stored at address FFFF00H to FFFF02H: PC<7:0> ← Data in location FFFF00H PC<15:8> ← Data in location FFFF01H PC<23:16> ← Data in location FFFF02H
• Sets the stack pointer (XSP) to 00000000H.
• Sets bits <IFF0:2> of the status register (SR) to 111 (Thereby setting the interrupt level mask register to level 7).
• Clears bits <RFP0:1> of the status register to 00 (Thereby selecting register bank0). When the reset is released, the CPU starts executing instructions according to the program counter settings. CPU internal registers not mentioned above do not change when the reset is released. When the reset is accepted, the CPU sets internal I/O, ports and other pins as follows.
• Initializes the internal I/O registers as table of “Table of Special Function Registers (SFRs)” in section 5.
• Sets the port pins, including the pins that also act as internal I/O, to general-purpose input or output port mode. Internal RESET is released as soon as external reset is released. The operation of memory controller cannot be insured until power supply becomes stable after power-on reset. The external RAM data provided before turning on the TMP92C820 may be spoiled because the control signals are unstable until power supply becomes stable after power on reset.

Figure 3.1.1 Power on Reset Timing Example

3.1.3 Setting of AM0 and AM1

Set AM1 and AM0 pins to “10” to use 32-bit external bus, or set it to “01” to use 16-bit external bus. Table 3.1.2 Operation Mode Setup Table Mode Setup Input Pin Operation Mode RESET AM1 AM0 16-bit external bus or 8-/16-/32-bit dynamic bus sizing 0 1 32-bit external bus or 8-/16-/32-bit dynamic bus sizing 1 0 Osc warm-up time + 20 system clock 0 s (Min) VCC 3.3 V RESET 10 ms (Min)

3.2 Memory Map

1H Figure 3.2.1 is a memory map of the TMP92C820. 000000H 002000H 16-Mbyte area (R) ( −R) (R +) (R + R8/16) (R + d8/16) (nnn) Direct area (n) 64-Kbyte area (nn) Internal I/O (8 Kbytes) Internal RAM (8 Kbytes) 004000H 010000H ( = Internal area) FFFF00H FFFFFFH Vector table (256 bytes) External memory 000100H Provisional emulator control area (64 Kbytes) F00000H F10000H External memory 001FE0H (Note 1) (Note 2) Note 1: Provisional emulator control area is for emulator, it is mapped F00000H to F10000H address after reset. Note 2: Don’t use the last 16-byte area (FFFFF0H to FFFFFFH). This area is reserved. Note 3: On emulator WR signal and RD signal are asserted, when provisional emulator control area is accessed. Be careful to use external memory. Figure 3.2.1 Memory Map

3.3 Clock Function and Standby Function

TMP92C820 contains (1) Clock gear, (2) Standby controller, and (3) Noise reduction circuit. It is used for low-power, low-noise systems. This chapter is organized as follows: 2H 3.3.1 3H Block Diagram of System Clock 4H 3.3.2 5H SFR 6H 3.3.3 7H System Clock Controller 8H 3.3.4 9H Noise Reduction Circuits 10H 3.3.5 11H Standby Controller

The clock operating modes are as follows: (a) Single clock mode (X1, X2 pins only) and (b) Dual clock mode (X1, X2, XT1, and XT2 pins). 12H Figure 3.3.1 shows a transition figure. Interrupt Interrupt Instruction Instruction Interrupt Interrupt Instruction Reset (fOSCH/32) Release reset Instruction Interrupt STOP mode (Stops all circuits) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) (a) Single clock mode transition figure (b) Dual clock mode transition figure STOP mode (Stops all circuits) Instruction Reset (fOSCH/32) Release reset NORMAL mode (fOSCH/gear value/2) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Interrupt Instruction Instruction Instruction NORMAL mode (fOSCH/gear value/2) Interrupt Interrupt Instruction Instruction SLOW mode (fs/2) Figure 3.3.1 System Clock Block Diagram The clock frequency input from the X1 and X2 pins is called fc and the clock frequency input from the XT1 and XT2 pins is called fs. The clock frequency selected by SYSCR1<SYSCK> is called the system clock fFPH. The system clock fSYS is defined as the divided clock of fFPH, and one cycle of fSYS is defined to as one state.

3.3.1 Block Diagram of System Clock

SYSCR1<SYSCK> TMRA0 to TMRA3, TMRB0 fs fOSCH XT1 XT2 Warm-up timer (High-/low-frequency oscillator) SYSCR0<WUEF> SYSCR2<WUPTM1:0> ÷2 ÷16÷4 ÷8 fc/16 fc/8 fc/4 fc/2 fc SYSCR1<GEAR2:0> ÷4 ÷8 fFPH fSYS÷2 fSYS WDT PrescalerφT0 SIO0 to SIO2 Prescaler φT0 fs SYSCR0 <XEN> SBI Prescaler RTC MLD/ALM φT fs φT ÷2 fio fio CPU RAM Interrupt controller ADC I/O ports SDRAMC LCDC SYSCR0 <XTEN> Low-frequency oscillator High-frequency oscillator Figure 3.3.2 Block Diagram of System Clock

3.3.2 SFR

oscillator (fc) 0: Stop 1: Oscillation Low-frequency oscillator (fs) 0: Stop 1: Oscillation Warm-up timer 0: Write Don’t care 1: Write start timer 0: Read end warm up 1: Read do not end warm up Bit symbol SYSCK GEAR2 GEAR1 GEAR0 Read/Write R/W After reset 0 1 0 0 Function Select system clock. 0: fc 1: fs Select gear value of high frequency (fc) 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: 110: Reserved 111: Bit symbol − WUPTM1 WUPTM0 HALTM1 HALTM0 SELDRV DRVE Read/Write R/W R/W After reset 0 1 0 1 1 0 0 Function Always write “0”. Warm-up timer 00: Reserved 01: 2 /inputted frequency 10: 2 /inputted frequency 11: 2 /inputted frequency HALT mode 00: Reserved 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode <DRVE> mode select 0: STOP 1: IDLE1 Pin state control in STOP/ IDLE1 mode 0: I/O off 1: Remains the state before halt. Note 1: The unassigned register, SYSCR0<Bit5:3>, SYSCR0<Bit1:0>, SYSCR1<Bit7:4>, and SYSCR2<Bit7:6> are read as undefined value. Note 2: By reset, low-fr equency oscillator is enabled. Figure 3.3.3 SFR for System Clock SYSCR0 (10E0H) SYSCR1 (10E1H) SYSCR2 (10E2H)

Bit symbol PROTECT EXTIN DRVOSCH DRVOSCL Read/Write R R/W After reset 0 0 1 1 Function Protect flag 0: OFF 1: ON 1: fc external clock fc oscillator drive ability 1: Normal 0: Weak fs oscillator drive ability 1: Normal 0: Weak Bit symbol Read/Write After reset Function Switching the protect ON/OFF by write to following 1st-key, 2nd-key 1st-Key: EMCCR1 = 5AH, EMCCR2 = A5H in succession write 2nd-Key: EMCCR1 = A5H, EMCCR2 = 5AH in succession write Figure 3.3.4 SFR for Noise-reduction Note: In caseWhen restarting the oscillator in from the stop oscillation state (e.g. Restart restarting the oscillator in STOP mode), set EMCCR0<DRVOSCH>, <DRVOSCL>=”1”. EMCCR0 (10E3H) EMCCR1 (10E4H) EMCCR2 (10E5H)

3.3.3 System Clock Controller

The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O. It contains two oscillation circuits and a clock gear circuit for high-frequency (fc) operation. The register SYSCR1<SYSCK> changes the system clock to either fc or fs, SYSCR0<XEN> and SYSCR0<XTEN> control enabling and disabling of each oscillator, and SYSCR1<GEAR2:0> sets the high-frequency clock gear to either 1, 2, 4, 8, or 16 (fc, fc/2, fc/4, fc/8, or fc/16). These functions can reduce the power consumption of the equipment in which the device is installed. The combination of settings <XEN> = 1, <XTEN> = 1, <SYSCK> = 0 and <GEAR2:0> = 100 will cause the system clock (f SYS) to be set to fc/32 (fc/16 × 1/2) after reset. For example, fSYS is set to 1.25 MHz when the 40 MHz oscillator is connected to the X1 and X2 pins. (1) Switching from NORMAL mode to SLOW mode When the resonator is connected to the X1 and X2 pins, or to the XT1 and XT2 pins, the warm-up timer can be used to change the operation frequency after stable oscillation has been attained. The warm-up time can be selected using SYSCR2<WUPTM1:0>. This warm-up timer can be programmed to start and stop as shown in the following examples 1 and 2. 13H Table 3.3.1 shows the warm-up time. Note 1: When using an oscillator (other than a resonator) with stable oscillation, a warm-up timer is not needed. Note 2: The warm-up timer is operated by an oscillation clock. Hence, there may be some variation in warm-up time. Table 3.3.1 Warm-up Times Warm-up Time SYSCR2<WUPTM1:0> Change to NORMAL Mode (fc) Change to SLOW Mode (fs) 01 (2 /frequency) 6.4 [ μs] 7.8 [ms] 10 (2 /frequency) 409.6 [ μs] 500 [ms] 11 (2 /frequency) 1.638 [ms] 2000 [ms] at fOSCH =

40 MHz,

fs = 32.768 kHz

Example 1: Setting the clock Changing from high frequency (fc) to low frequency (fs). SYSCR0 EQU 10E0H SYSCR1 EQU 10E1H SYSCR2 EQU 10E2H LD (SYSCR2), 0X11 - - - - B ; Sets warm-up time to 2 /fs. SET 6, (SYSCR0) ; Enables low-frequency oscillation. SET 2, (SYSCR0) ; Clears and starts warm-up timer. WUP: BIT 2, (SYSCR0) ; JR NZ, WUP ; Detects stopping of warm-up timer. SET 3, (SYSCR1) ; Changes f SYS from fc to fs. RES 7, (SYSCR0) ; Disables high-frequency oscillation. X: Don’t care, −: No change Enables low frequency Clears and starts warm-up time r Chages fSYS from fc to fs End of warm-up time r Disables high frequenc y fc <XEN> X1 and X2 pins <XTEN> XT1 and XT2 pins Warm-up timer <SYSCK> System clock fSYS End of warm-up timer fs Counts up by fsCounts up by fSYS

Example 2: Setting the clock Changing from low frequency (fs) to high frequency (fc). SYSCR0 EQU 10E0H SYSCR1 EQU 10E1H SYSCR2 EQU 10E2H LD (SYSCR2), 0X10 - - - - B ; Sets warm-up time to 2 /fc. SET 7, (SYSCR0) ; Enables high-frequency oscillation. SET 2, (SYSCR0) ; Clears and starts warm-up timer. WUP: BIT 2, (SYSCR0) ; JR NZ, WUP ; Detects stopping of warm-up timer. RES 3, (SYSCR1) ; Changes f SYS from fs to fc. RES 6, (SYSCR0) ; Disables low-frequency oscillation. X: Don’t care, −: No change Counts up by fSYS Counts up by fc Disables low frequency Enables high frequency Clears and starts warm-up timer Chages f SYS from fs to fc End of warm-up timer <XEN> X1 and X2 pins <XTEN> XT1 and XT2 pins Warm-up timer <SYSCK> System clock f SYS End of warm-up timer fcfs

(2) Clock gear controller fFPH is set according to the contents of the clock gear select register SYSCR1<GEAR2:0> to either fc, fc/2, fc/4, fc/8 or fc/16. Using the clock gear to select a lower value of fFPH reduces power consumption. Example 3: Changing to a high-frequency gear SYSCR1 EQU 10E1H LD (SYSCR1), XXXX0000B ; Changes f SYS to fc/2. X: Don’t care (High-speed clock gear changing) To change the clock gear, write the register value to the SYSCR1<GEAR2:0> register. It is necessary the warm-up time until changing after writing the register value. There is the possibility that the instruction next to the clock gear changing instruction is executed by the clock gear before changing. To execute the instruction next to the clock gear switching instruction by the clock gear after changing, input the dummy instruction as follows (Instruction to execute the write cycle). (Example) SYSCR1 EQU 10E1H LD (SYSCR1), XXXX0001B ; Changes f SYS to fc/4. LD (DUMMY), 00H ; Dummy instruction Instruction to be executed after clock gear has changed

3.3.4 Noise Reduction Circuits

Noise reduction circuits are built in, allowing implementation of the following features. (1) Reduced drivability for hi gh-frequency oscillator (2) Reduced drivability for low-frequency oscillator (3) Single drive for high-frequency oscillator (4) Runaway provision with SFR protection register (1) Reduced drivability for hi gh-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) (Setting method) The drivability of the oscillator is reduced by writing “0” to EMCCR0<DRVOSCH> register. By reset, <DRVOSCH> is initialized to “1” and the oscillator starts oscillation by normal drive ability when the power supply is on. Note: This function (EMCCR0<DRVOSCH> = “0”) is available to use in case ofwhen fOSCH = 6 to 10 MHz condition. fOSCH Enable oscillation (STOP + EMCCR0<EXTIN>) EMCCR0<DRVOSCH> X1 pin X2 pin Resonator

(2) Reduced drivability for low-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) (Setting method) The drivability of the oscillator is reduced by writing 0 to the EMCCR0<DRVOSCL> register. By reset, <DRVOSCL> is initialized to “1”. (3) Single drive for high-frequency oscillator (Purpose) Not need twin-drive and protect mistake operation by inputted noise to X2 pin when the external oscillator is used. (Block diagram) (Setting method) The oscillator is disabled and starts operation as buffer by writing “1” to EMCCR0<EXTIN> register. X2 pin is always outputted “1”. By reset, <EXTIN> is initialized to “0”. fs Enable oscillation EMCCR0<DRVOSCL> XT1 pin XT2 pin Resonator Enable oscillation (STOP + EMCCR0<EXTIN>) fOSCH EMCCR0<DRVOSCH> X1 pin X2 pin

(4) Runaway provision with SFR protection register (Purpose) Provision in runaway of program by noise mixing. Write operation to specified SFR is prohibited so that provision program in runaway prevents that it is it in the state which is fetch impossibility by stopping of clock, memory control register (Memory controller, MMU) is changed. And error handling in runaway becomes easy by INTP0 interruption. Specified SFR list 1. Memory controller B0CSL/H, B1CSL/H, B2CSL/H, B3CSL/H, BECSL/H MSAR0, MSAR1, MSAR2, MSAR3, MAMR0, MAMR1, MAMR2, MAMR3, PMEMCR 2. MMU LOCAL 0/1/2/3 3. Clock gear SYSCR0, SYSCR1, SYSCR2, EMCCR0 (Operation explanation) Execute and release of protection (Write operation to specified SFR) become possible by setting up a double key to EMCCR1 and EMCCR2 register. (Double key) 1st-key: Succession writes in 5AH at EMCCR1 and A5H at EMCCR2 2nd-key: Succession writes in A5H at EMCCR1 and 5AH at EMCCR2 A state of protection can be confirmed by reading EMCCR0<PROTECT>. By reset, protection becomes OFF. And INTP0 interruption occurs when write operation to specified SFR was executed with protection on state.

3.3.5 Standby Controller

(1) HALT modes When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2<HALTM1:0> register. The subsequent actions performed in each mode are as follows: 1. IDLE2: Only the CPU halts. The internal I/O is available to select operation during IDLE2 mode by setting the following register. 14H Table 3.3.2 shows the registers of setting operation during IDLE2 mode. Table 3.3.2 SFR Setting Operation during IDLE2 Mode Internal I/O SFR TMRA01 TA01RUN<I2TA01> TMRA23 TA23RUN<I2TA23> TMRB0 TB0RUN<I2TB0> SIO0 SC0MOD1<I2S0> SIO1 SC1MOD1<I2S1> AD converter ADMOD1<I2AD> WDT WDMOD<I2WDT> SBI SBI0BR0<I2SBI0> 2. IDLE1: Only the oscillator, the RTC (Real time clock) and MLD (Melody-alarm generator) continue to operate. 3. STOP: All internal circuits stop operating. The operation of each of the different HALT modes is described in 15H Table 3.3.3. Table 3.3.3 I/O Operation during HALT Modes HALT Modes IDLE2 IDLE1 STOP SYSCR2<HALTM1:0> 11 10 01 CPU Stop I/O ports Keep the state when the HALT instruction was executed. See 16H Table 3.3.6, 17H Table 3.3.7 and 18H Table 3.3.8 TMRA, TMRB SIO, SBI (Note) AD converter WDT Available to select operation block (Note) LCDC, SDRAMC interrupt controller Stop Block RTC, MLD Operate Operate Note: Prohibited in the synchronous mode of SBI circuit.

(2) How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination between the states of interrupt mask register <IFF2:0> and the HALT modes. The details for releasing the halt status are shown in 19H Table 3.3.4. 1. Released by requesting an interrupt The operating released from the HALT mode depends on the interrupt enabled status. When the interrupt request level set before executing the HALT instruction exceeds the value of interrupt mask register, the interrupt due to the source is processed after releasing the HALT mode, and CPU status executing an instruction that follows the HALT instruction. When the interrupt request level set before executing the HALT instruction is less than the value of the interrupt mask register, releasing the HALT mode is not executed. (In non-maskable interrupts, interrupt processing is processed after releasing the HALT mode regardless of the value of the mask register.) However only for INT0 to INT3, INTKEY, INTRTC, and INTALM0 to INTALM4 interrupts, even if the interrupt request level set before executing the HALT instruction is less than the value of the interrupt mask register, releasing the HALT mode is executed. In this case, interrupt processing, and CPU starts executing the instruction next to the HALT instruction, but the interrupt request flag is held at “1”. Note: Usually, interrupts can release all halts status. However, the interrupts (INT0 to INT3, INTKEY , INTRTC, INTALM0 to INTALM4) which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of f FPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficulty. The priority of this interrupt is compared with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. 2. Releasing by resetting Releasing all halt status is executed by resetting. When the STOP mode is released by RESET, it is necessary enough resetting time (See 20H Table 3.3.5) to set the operation of the oscillator to be stable. When releasing the HALT mode by resetting, the internal RAM data keeps the state before the “HALT” instruction is executed. However the other settings contents are initialized. (Releasing due to interrupts keeps the state before the “HALT” instruction is executed.)

Table 3.3.4 Source of Halt State Clearance and Halt Clearance Operation Status of Received Interrupt Interrupt Enabled (Interrupt level) ≥ (Interrupt mask) Interrupt Disabled (Interrupt level) < (Interrupt mask) HALT Mode IDLE2 IDLE1 STOP IDLE2 IDLE1 STOP INTTA0 to 3, INTTB00 to 01 ♦ × × × × × INTRX0 to 2, TX0 to 2 ♦ × × × × × Interrupt Source of Halt State Clearance RESET Initialize LSI ♦: After clearing the HALT mode, CPU starts interrupt processing. ○: After clearing the HALT mode, CPU resumes executing starting from instruction following the HALT instruction. ×: It can not be used to release the HALT mode. −: The priority level (Interrupt request level) of non-ma skable interrupts is fixed to 7, the highest priority level. There is not this combination type. *1: Releasing the HALT mode is executed after passing the warm-up time. Note 1: When the HALT mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled status, hold level H until starting interrupt processing. If level L is set before holding level L, interrupt processing is correctly started. (Example releasing IDLE1 mode) An INT0 interrupt clears the halt state when the device is in IDLE1 mode. Address 8200H LD (PCFC), 04H ; Sets PC3F to INT0. 8203H LD (IIMC), 00H ; Selects INT0 interrupt rising edge. 8206H LD (INTE0AD), 06H ; Sets INT0 interrupt level to 6. 8209H EI 5 ; Sets interrupt level to 5 for CPU. 820BH LD (SYSCR2), 28H ; Sets HALT mode to IDLE1 mode. 820EH HALT ; Halts CPU. INT0 INT0 interrupt routine RETI 820FH LD XX, XX

1. STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator pin status in STOP mode depends on the settings in the summarizes the state of these pins in STOP mode. After STOP mode has been cleared system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize. 29H Figure 3.3.7 illustrates the timing for clearance of the STOP mode halt state by an interrupt. Interrupt o f releasing halt Data Data STOP mode A0 to A23 D0 to D15 RD WR Warm-up time Figure 3.3.7 Timing Chart for STOP Mode Halt State Cleared by Interrupt Table 3.3.5 Sample Warm-up Times after Clearance of STOP Mode at fOSCH = 40 MHz, fs = 32.768 kHz SYSCR2<WUPTM1:0> SYSCR0 <RSYSCK> 01 (28) 10 (2 14) 11 (2 16) 0 (fc) 6.4 μs 409.6 μs 1.638 ms

Table 3.3.6 Input Buffer State Table Input Buffer State In HALT mode (IDLE1/STOP) When the CPU is operating In HALT mode (IDLE2) Condition A (Note) Condition B (Note) Port Name Input Function Name During Reset When used as function pin When used as Input pin When used as Function pin When used as Input pin When used as Function pin When used as Input pin When used as Function pin When used as Input pin P10-P17 D8-D15 OFF P20-P27 D16-D23 P30-P37 D24-D31 16-bit start :ON 32-bit start :OFF ON upon external read ON upon external read of LCDC OFF OFF P40-P47 − P50-P57 − P60-P67 − OFF − − − − P76 WAIT OFF P90 SCK P91 SDA P92 SI, SCL ON ON OFF OFF P93 − P94 − P95 − − − OFF − − P96 RXD2 OFF OFF OFF OFF PA0-PA7 (*1) KI0-7 ON ON ON ON ON PC0 TA0IN OFF OFF PC1 INT1 OFF OFF OFF PC3 INT0 ON ON ON PC5 INT2 PC6 INT3 ON ON ON ON PF0 − − − OFF − − PF1 RXD0 PF2 SCLK0, CTS0 ON ON ON OFF OFF PF4 RXD1 PF5 SCLK1, CTS1 ON ON ON ON ON OFF OFF PG0-PG2, PG3 (*2) ADTRG OFF ON ON upon port read ON ON ON PL0-PL7 − − ON − OFF OFF OFF BE − RESET (*1) − AM0, AM1 − ON − ON − X1, XT1 ON ON − ON − IDLE1 : ON , STOP : OFF ON: The buffer is always turned on. A current flows the input buffer if the input pin is not driven. *1: Port having a pull-up/pull-down resistor. OFF: The buffer is always turned off. *2: AIN input does not cause a current to flow through the buffer. -: No applicable Note: Condition A/B are as follows. SYSCR2 register setting HALT mode <DRVE> <SELDRV> IDLE1 STOP 0 0 Condition B 0 1 Condition A Condition A 1 0 1 1 Condition B Condition B

Table 3.3.7 Output Buffer State Table (1/2) Output Buffer State In HALT mode (IDLE1/STOP) When the CPU is Operating In HALT mode (IDLE2) Condition A (Note) Condition B (Note) Port Name Output Function Name During Reset When used as Function Pin When Used as Output Port When Used as Function Pin When Used as Output Port When Used as Function Pin When Used as Output Port When Used as Function Pin When Used as Output Port P10-P17 D8-D15 P20-P27 D16-D23 P30-P37 D24-D31 OFF ON upon external write OFF ON OFF P40-P47 A0-A7 P50-P57 A8-A15 P60-P67 A16-A23 P70 RD P71 WRLL P72 WRLU P73 WRUL P74 WRUU P75 R/W ON ON ON OFF ON P80 CS0, SDCSH P81 CS1, SDCSL P82 CS2, CS2A P83 CS3 P84 EA24, CS2B P85 EA25, CS2C P86 CS2D P87 SDCLK ON P90 SCK P91 SO P92 SCL P93 CS2E P94 CS2F P95 CS2G TXD2 P96 CSEXA ON ON OFF ON PC1 TA1OUT ON ON OFF ON PC5 TA3OUT PC6 TB0OUT OFF ON ON ON ON OFF OFF ON ON

Table 3.3.8 Output Buffer State Table (2/2) Output Buffer State In HALT mode (IDLE1/STOP) When the CPU is Operating In HALT mode (IDLE2) Condition A (Note) Condition B (Note) Port Name Output Function Name During Reset When used as Function Pin When Used as Output Port When Used as Function Pin When Used as Output Port When Used as Function Pin When Used as Output Port When Used as Function Pin When Used as Output Port PF0 TXD0 ON ON OFF PF2 SCLK0 PF3 TXD1 ON ON OFF ON PF5 SCLK1 PJ0 SDRAS PJ1 SDCAS PJ2 SDWE SRWR PJ3 SDLLDQM SRLLB PJ4 SDLUDQM SRLUB PJ5 SDULDQM SRULB PJ6 SDUUDQM SRUUB OFF PJ7 SDCKE ON in self refresh cycle PK0 D1BSCP PK1 D2BLP PK2 D3BFR PK3 DLEBCD PK4 DOFFB PK6 ALARM MLDALM PL0-PL7 LD0-LD7 OFF ON ON OFF OFF ON ON X2 − IDLE1: ON, STOP: output “H” level XT2 − ON ON ON IDLE1: ON, STOP: High-Z ON: The buffer is always turned on. When the bus is released, however, output buffers for some pins are turned off. *1: Port having a pull-up/pull-down resistor. OFF: The buffer is always turned off. -: No applicable Note: Condition A/B are as follos. SYSCR2 register setting HALT mode <DRVE> <SELDRV> IDLE1 STOP 0 0 Condition B 0 1 Condition A Condition A 1 0 1 1 Condition B Condition B

3.4 Interrupts

Interrupts are controlled by the CPU interrupt mask register <IFF2:0> (Bits 12 to 14 of the status register) and by the built-in interrupt controller. The TMP92C820 has a total of 45 interrupts divided into the following five types: Interrupts generated by CPU: 9 sources

• Software interrupts: 8 sources
• Illegal Instruction interrupt: 1 source Internal interrupts: 31 sources
• Internal I/O interrupts: 23 sources
• Micro DMA transfer end interrupts: 8 sources External interrupts: 5 sources
• Interrupts on external pins (INT0 to INT3, INTKEY) A fixed individual interrupt vector number is assigned to each interrupt source. Any one of six levels of priority can also be assigned to each maskable interrupt. Non-maskable interrupts have a fixed priority level of 7, the highest level. When an interrupt is generated, the interrupt controller sends the priority of that interrupt to the CPU. When more than one interrupt are generated simultaneously, the interrupt controller sends the priority value of the interrupt is with the highest priority to the CPU. (The highest priority level is 7, the level used for non-maskable interrupts.) The CPU compares the interrupt priority level which it receives with the value held in the CPU interrupt mask register <IFF2:0>. If the priority level of the interrupt is greater than or equal to the value in the interrupt mask register, the CPU accepts the interrupt. However, software interrupts and illegal instruction interrupts generated by the CPU are processed irrespective of the value in <IFF2:0>. The value in the interrupt mask register <IFF2:0> can be changed using the EI instruction (EI num sets <IFF2:0> to num). For example, the command EI3 enables the acceptance of all non-maskable interrupts and of maskable interrupts whose priority level, as set in the interrupt controller, is 3 or higher. The commands EI and EI0 enable the acceptance of all non-maskable interrupts and of maskable interrupts with a priority level of 1 or above (hence both are equivalent to the command EI1). The DI instruction (Sets <IFF2:0> to 7) is exactly equivalent to the EI7 instruction. The DI instruction is used to disable all maskable interrupts (since the priority level for maskable interrupts ranges from 1 to 6). The EI instruction takes effect as soon as it is executed. In addition to the general-purpose interrupt processing mode described above, there is also a micro DMA processing mode. In micro DMA mode the CPU automatically transfers data in one-byte, two-byte or four-byte blocks; this mode allows high-speed data transfer to and from internal and external memory and internal I/O ports. In addition, the TMP92C820 also has a software start function in which micro DMA processing is requested in software rather than by an interrupt. 0H Figure 3.4.1 is a flowchart showing overall interrupts processing.

Figure 3.4.1 Interrupt and Micro DMA Processing Sequence Yes PUSH PC PUSH SR SR<IFF2:0> ← Level of accepted interrupt + 1 INTNEST ← INTNEST + 1 End PC ← (FFFF00H + V) Interrupt processing program Count ← Count − 1 Data transfer by micro DMA No Micro DMA processing RETI instruction POP SR POP PC INTNEST ← INTNEST − 1 Interrupt specified by micro DMA start vector? Clear vector register generating micro DMA transfer end interrupt (INTTC0 to INTTC7) Clear interrupt request flag Interrupt vector value “V” read Interrupt request F/F clear Interrupt processing Count = 0 Yes No General-purpose interrupt processing Micro DMA soft start request

3.4.1 General-purpose Interrupt Processing

When the CPU accepts an interrupt, it usually performs the following sequence of operations. However, in the case of software interrupts and illegal instruction interrupts generated by the CPU, the CPU skips steps (1) and (3), and executes only steps (2), (4), and (5). (1) The CPU reads the interrupt vector from the interrupt controller. When more than one interrupt with the same priority level has been generated simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt requests. (The default priority is determined as follows: The smaller the vector value, the higher the priority.) (2) The CPU pushes the program counter (PC) and status register (SR) onto the top of the stack (Pointed to by XSP). (3) The CPU sets the value of the CPU’s interrupt mask register <IFF2:0> to the priority level for the accepted interrupt plus 1. However, if the priority level for the accepted interrupt is 7, the register’s value is set to 7. (4) The CPU increments the interrupt nesting counter INTNEST by 1. (5) The CPU jumps to the address given by adding the contents of address FFFF00H + the interrupt vector, then starts the interrupt processing routine. On completion of interrupt processing, the RETI instruction is used to return control to the main routine. RETI restores the contents of the program counter and the status register from the stack and decrements the interrupt nesting counter INTNEST by 1. Non-maskable interrupts cannot be disabled by a user program. Maskable interrupts, however, can be enabled or disabled by a user program. A program can set the priority level for each interrupt source. (A priority level setting of 0 or 7 will disable an interrupt request.) If an interrupt request is received for an interrupt with a priority level equal to or greater than the value set in the CPU interrupt mask register <IFF2:0>, the CPU will accept the interrupt. The CPU interrupt mask register <IFF2:0> is then set to the value of the priority level for the accepted interrupt plus 1. If during interrupt processing, an interrupt is generated with a higher priority than the interrupt currently being processed, or if, during the processing of a non-maskable interrupt processing, a non-maskable interrupt request is generated from another source, the CPU will suspend the routine which it is currently executing and accept the new interrupt. When processing of the new interrupt has been completed, the CPU will resume processing of the suspended interrupt. If the CPU receives another interrupt request while performing processing steps (1) to (5), the new interrupt will be sampled immediately after execution of the first instruction of its interrupt processing routine. Specifying DI as the start instruction disables nesting of maskable interrupts. A reset, initializes the interrupt mask register <IFF2:0> to 111, disabling all maskable interrupts. 1H Table 3.4.1 shows the TMP92C820 interrupt vectors and micro DMA start vectors. FFFF00H to FFFFFFH (256 bytes) is designated as the interrupt vector area.

Table 3.4.1 TMP92C820 Interrupt Vectors and Micro DMA Start Vectors (1/2) Default Priority Type Interrupt Source and Source of Micro DMA Request Vector Value Address Refer to Vector Micro DMA Start Vector

1 Reset or [SWI0] instruction 0000H FFFF00H

2 [SWI1] instruction 0004H FFFF04H

3 Illegal instruction or [SWI2] instruction 0008H FFFF08H

4 [SWI3] instruction 000CH FFFF0CH 5 [SWI4] instruction 0010H FFFF10H 6 [SWI5] instruction 0014H FFFF14H 7 [SWI6] instruction 0018H FFFF18H 8 [SWI7] instruction 001CH FFFF1CH 9 (Reserved) 0020H FFFF20H Non maskable INTWD: Watchdog timer 0024H FFFF24H − Micro DMA − − − (Note 1)

11 INT0: INT0 pin input 0028H FFFF28H 0AH (Note 2)

12 INT1: INT1 pin input 002CH FFFF2CH 0BH

13 INT2: INT2 pin input 0030H FFFF30H 0CH

14 INT3: INT3 pin input 0034H FFFF34H 0DH

15 (Reserved) 0038H FFFF38H 0EH

16 INTALM0: ALM0 (8 kHz) 003CH FFFF3CH 0FH

17 INTALM1: ALM1 (512 Hz) 0040H FFFF40H 10H

18 INTALM2: ALM2 (64 Hz) 0044H FFFF44H 11H

19 INTALM3: ALM3 (2 Hz) 0048H FFFF48H 12H

20 INTALM4: ALM4 (1 Hz) 004CH FFFF4CH 13H

21 INTP0: Protect 0 (WR to SFR) 0050H FFFF50H 14H

22 (Reserved) 0054H FFFF54H 15H

23 INTTA0: 8-bit timer 0 0058H FFFF58H 16H

24 INTTA1: 8-bit timer 1 005CH FFFF5CH 17H

25 INTTA2: 8-bit timer 2 0060H FFFF60H 18H

26 INTTA3: 8-bit timer 3 0064H FFFF64H 19H

27 INTTB0: 16-bit timer 0 0068H FFFF68H 1AH

28 INTTB1: 16-bit timer 0 006CH FFFF6CH 1BH

29 INTKEY: Key wakeup 0070H FFFF70H 1CH

30 INTRTC: RTC (Alarm interrupt) 0074H FFFF74H 1DH

31 INTTBO0: 16-bit timer 0 (Overflow) 0078H FFFF78H 1EH

32 INTLCD: LCDC/LP pin 007CH FFFF7CH 1FH

33 INTRX0: Serial receive (Channel 0) 0080H FFFF80H 20H (Note 2)

34 INTTX0: Serial transmission (Channel 0) 0084H FFFF84H 21H

35 INTRX1: Serial receive (Channel 1) 0088H FFFF88H 22H (Note 2)

36 INTTX1: Serial transmission (Channel 1) 008CH FFFF8CH 23H

37 INTRX2: Serial receive (Channel 2) 0090H FFFF90H 24H (Note 2)

38 INTTX2: Serial transmission (Channel 2) 0094H FFFF94H 25H

39 (Reserved) 0098H FFFF98H 26H 40 (Reserved) 009CH FFFF9CH 27H 41 (Reserved) 00A0H FFFFA0H 28H 42 (Reserved) 00A4H FFFFA4H 29H 43 (Reserved) 00A8H FFFFA8H 2AH 44 (Reserved) 00ACH FFFFACH 2BH 45 (Reserved) 00B0H FFFFB0H 2CH 46 (Reserved) 00B4H FFFFB4H 2DH 47 (Reserved) 00B8H FFFFB8H 2EH

48 INTSBE0: SBI I

C bus transfer end (Channel 0) 00BCH FFFFBCH 2FH 49 (Reserved) 00C0H FFFFC0H 30H Maskable (Reserved) 00C4H FFFFC4H 31H

Table 3.4.1 TMP92C820 Interrupt Vectors and Micro DMA Start Vectors (2/2) Default Priority Type Interrupt Source and Source of Micro DMA Request Vector Value Address Refer to Vector Micro DMA Start Vector 51 (Reserved) 00C8H FFFFC8H 32H

52 INTAD: AD conversion end 00CCH FFFFCCH 33H

53 INTTC0: Micro DMA end (Channel 0) 00D0H FFFFD0H 34H

54 INTTC1: Micro DMA end (Channel 1) 00D4H FFFFD4H 35H

55 INTTC2: Micro DMA end (Channel 2) 00D8H FFFFD8H 36H

56 INTTC3: Micro DMA end (Channel 3) 00DCH FFFFDCH 37H

57 INTTC4: Micro DMA end (Channel 4) 00E0H FFFFE0H 38H

58 INTTC5: Micro DMA end (Channel 5) 00E4H FFFFE4H 39H

59 INTTC6: Micro DMA end (Channel 6) 00E8H FFFFE8H 3AH

60 INTTC7: Micro DMA end (Channel 7) 00ECH FFFFECH 3BH

(Reserved) 00F0H 00FCH FFFFF0H FFFFFCH Note 1: Micro DMA default priority. Micro DMA initiation takes priority over other maskable interrupt. Note 2: When initiating micro DMA, set at edge detect mode.

3.4.2 Micro DMA processing

In addition to general-purpose interrupt processing, the TMP92C820 also includes a micro DMA function. Micro DMA processing for interrupt requests set by micro DMA is performed at the highest priority level for maskable interrupts (Level 6), regardless of the priority level of the interrupt source. Because the micro DMA function is implemented though the CPU, when the CPU is placed in a state of standby by HALT instruction, the requirements of the micro DMA will be ignored (Pending). Micro DMA supports 8 channels and can be transferred continuously by specifying the micro DMA burst function as below. (1) Micro DMA operation When an interrupt request is generated by an interrupt source specified by the micro DMA start vector register, the micro DMA triggers a micro DMA request to the CPU at interrupt priority level 6 and starts processing the request. The eight micro DMA channels allow micro DMA processing to be set for up to 8 types of interrupt at once. When micro DMA is accepted, the interrupt request flip-flop assigned to that channel is cleared. Data in one-byte, two-byte or four-byte blocks, is automatically transferred at once from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decremented by 1. If the value of the counter after it has been decremented is not 0, DMA processing ends with no change in the value of the micro DMA start vector register. If the value of the decremented counter is 0, a micro DMA transfer end interrupt (INTTC0 to INTTC7) is sent from the CPU to the interrupt controller. In addition, the micro DMA start vector register is cleared to 0, the next micro DMA operation is disabled and micro DMA processing terminates. If micro DMA requests are set simultaneously for more than one channel, priority is not based on the interrupt priority level but on the channel number: The lower the channel number, the higher the priority (Channel 0 thus has the highest priority and channel 7 the lowest). If an interrupt request is triggered for the interrupt source in use during the interval between the time at which the micro DMA start vector is cleared and the next setting, general-purpose interrupt processing is performed at the interrupt level set. Therefore, if the interrupt is only being used to initiate micro DMA (and not as a general-purpose interrupt), the interrupt level should first be set to 0 (j.e, interrupt requests should be disabled). If micro DMA and general-purpose interrupts are being used together as described above, the level of the interrupt which is being used to initiate micro DMA processing should first be set to a lower value than all the other interrupt levels. (Note) In this case, edge-triggered interrupts are the only kinds of general interrupts which can be accepted. Note: If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows. In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking “Interrupt specified by micro DMA start vector” (in the 2H Figure 3.4.1) and reading interrupt vector with setting below. The vector shifts to that of INTyyy at the time. This is because the priority level of INTyyy is higher than that of INTxxx. In the interrupt routine, CPU reads the vector of INTyyy because cheking of micro DMA has finished. And INTyyy is generated regardless of transfer counter of micro DMA. INTxxx: level 1 without micro DMA INTyyy: level 6 with micro DMA

Although the control registers used for setting the transfer source and transfer destination addresses are 32 bits wide, this type of register can only output 24-bit addresses. Accordingly, micro DMA can only access 16 Mbytes (The upper 8 bits of a 32-bit address are not valid). Three micro DMA transfer modes are supported: One-byte transfer, two-byte (One word) transfers and four-byte transfers. After a transfer in any mode, the transfer source and transfer destination addresses will either be incremented or decremented, or will remain unchanged. This simplifies the transfer of data from I/O to memory, from memory to I/O, and from I/O to I/O. For details of the various transfer modes, see section 3.4.2 (4) “Detailed description of the transfer mode register”. Since a transfer counter is a 16-bit counter, up to 65536 micro DMA processing operations can be performed per interrupt source (Provided that the transfer counter for the source is initially set to 0000H). Micro DMA processing can be initiated by any one of 34 different interrupts – the 33 interrupts shown in the micro DMA start vectors in 3H Table 3.4.1 and a micro DMA soft start. 4H Figure 3.4.2 shows a 2-byte transfer carried out using a micro DMA cycle in transfer destination address INC mode (Micro DMA transfers are the same in every mode except counter mode). (The conditions for this cycle are as follows: external 8-bit bus, 0 waits, and even-numbered transfer source and transfer destination addresses). Note: In fact, src and dst address are not output to A23 to A0 pins because they are internal RAM address States 1 and 2: Instruction fetch cycle (Prefetches the next instruction code) If the instruction queue buffer is FULL, this cycle becomes a dummy cycle. State 3: Micro DMA read cycle. State 4: Micro DMA write cycle. State 5: (The same as in state 1, 2.) Figure 3.4.2 Timing for Micro DMA Cycle src dst CLK A0 to A23 One state 1 2 3 4 5

(2) Soft start function The TMP92C820 can initiate micro DMA either with an interrupt or by using the micro DMA soft start function, in which micro DMA is initiated by a Write cycle which writes to the register DMAR. Writing 1 to any bit of the register DMAR causes micro DMA to be performed once. (If write “0” to each bit, micro DMA doesn’t operate). On completion of the transfer, the bits of DMAR which support the end channel are automatically cleared to 0. Only one channel can be set for DMA request at once. (Do not write “1” to plural bits.) When writing again 1 to the DMAR register, check whether the bit is “0” before writing “1”. If read “1”, micro DMA transfer isn’t started yet. When a burst is specified by the DMAB register, data is transferred continuously from the initiation of micro DMA until the value in the micro DMA transfer counter is 0. If execatee soft start during micro DMA transfer by interrupt source, micro DMA transfer counter doesn’t change. Don’t use Read-modify-write instruction to avoid writign to other bits by mistake. Symbol Name Address 7 6 5 4 3 2 1 0 DREQ7 DREQ6 DREQ5 DREQ4 DRE Q3 DREQ2 DREQ1 DREQ0 R/W 0 0 0 0 0 0 0 0 DMAR DMA request 109H (Prohibit RMW) 1: DMA request in software (3) Transfer control registers The transfer source address and the transfer destination address are set in the following registers. An instruction of the form LDC cr,r can be used to set these registers. 8 bits 16 bits 32 bits Channel 0 DMAS0 DMAD0 DMAC0 DMAM0 Channel 7 DMAS7 DMAD7 DMAC7 DMAM7 DMA source address register 0: Using only lower 24 bits. DMA destination address register 0: Using only lower 24 bits. DMA counter register 0: 1 to 65536. DMA mode register 0. DMA source address register 7. DMA destination address register 7. DMA counter register 7. DMA mode register 7.

(4) Detailed description of the transfer mode register DMAM [4:0] Mode Description Execution Time 000ZZ Destination INC mode (DMADn+) ← (DMASn) DMACn ← DMACn − 1 if DMACn = 0 then INTTCn 5 states 001ZZ Destination DEC mode (DMADn−) ← (DMASn) DMACn ← DMACn − 1 if DMACn = 0 then INTTCn 5 states 010ZZ Source INC mode (DMADn) ← (DMASn +) DMACn ← DMACn − 1 if DMACn = 0 then INTTCn 5 states 011ZZ Source DEC mode (DMADn) ← (DMASn −) DMACn ← DMACn − 1 if DMACn = 0 then INTTCn 5 states 100ZZ Source and destination INC mode (DMADn+) ← (DMASn +) DMACn ← DMACn − 1 If DMACn = 0 then INTTCn 6 states 101ZZ Source and destination DEC mode (DMADn−) ← (DMASn −) DMACn ← DMACn − 1 If DMACn = 0 then INTTCn 6 states 110ZZ Destination and fixed mode (DMADn) ← (DMASn) DMACn ← DMACn − 1 If DMACn = 0 then INTTCn 5 states 11100 Counter mode DMASn ← DMASn + 1 DMACn ← DMACn − 1 if DMACn = 0 then INTTCn 5 states ZZ: 00 = 1-byte transfer 01 = 2-byte transfer 10 = 4-byte transfer 11 = Reserved Note 1: The execution time is measured at 1 states = 50 ns (Operation at internal 20 MHz). Note 2: n stands for the micro DMA channel number (0 to 7). DMADn+/DMASn+: Post increment (Register value is incremented after transfer). DMADn−/DMASn−: Post decrement (Register value is decremented after transfer). “I/O” signifies fixed memory addresses; “memory” signifies incremented or decremented memory addresses. Note2: The transfer mode register should not be set to any value other than those listed above. 0 0 0 Mode DMAM0 to DMAM7

3.4.3 Interrupt Controller Operation

The block diagram in 5H Figure 3.4.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 52 interrupt channels there is an interrupt request flag (consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register. The interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to zero in the following cases: when a reset occurs, when the CPU reads the channel vector of an interrupt it has received, when the CPU receives a micro DMA request (when micro DMA is set), when a micro DMA burst transfer is terminated, and when an instruction that clears the interrupt for that channel is executed (by writing a micro DMA start vector to the INTCLR register). An interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g., INTE0AD or INTE12). Six interrupt priorities levels (1 to 6) are provided. Setting an interrupt source’s priority level to 0 (or 7) disables interrupt requests from that source. The priority of non-maskable interrupt (Watchdog timer interrupts) is fixed at 7. If more than one interrupt request with a given priority level are generated simultaneously, the default priority (The interrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request is accepted first. The 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. If several interrupts are generated simultaneously, the interrupt controller sends the interrupt request for the interrupt with the highest priority and the interrupt’s vector address to the CPU. The CPU compares the mask value set in <IFF2:0> of the status register (SR) with the priority level of the requested interrupt; if the latter is higher, the interrupt is accepted. Then the CPU sets SR<IFF2:0> to the priority level of the accepted interrupt + 1. Hence, during processing of the accepted interrupt, new interrupt requests with a priority value equal to or higher than the value set in SR<IFF2:0> (e.g., interrupts with a priority higher than the interrupt being processed) will be accepted. When interrupt processing has been completed (e.g., after execution of a RETI instruction), the CPU restores to SR<IFF2:0> the priority value which was saved on the stack before the interrupt was generated. The interrupt controller also includes eight registers which are used to store the micro DMA start vector. Writing the start vector of the interrupt source for the micro DMA processing (See 6H Table 3.4.1 and 7H Table 3.4.), enables the corresponding interrupt to be processed by micro DMA processing. The values must be set in the micro DMA parameter registers (e.g., DMAS and DMAD) prior to micro DMA processing.

Figure 3.4.3 Block Diagram of Interrupt Controller Interrupt request signal to CPU Micro DMA start vector setting register During IDLE1 During STOP 2 2 4-input OR INT0, 1, 2, 3, INTKEY, INTRTC, INTALM Micro DMA channel priority encoder Priority encoder DMA0V DMA1V DMA2V DMA3V RESET Interrupt request F/F RESET Reset Priority setting register V = 20H V = 24H Interrupt controller CPU S Q R V = 28H V = 2CH V = 30H V = 34H V = 3CH V = 40H V = 44H V = 48H V = 4CH V = 58H V = D0H V = D4H V = D8H V = DCH V = E0H V = E4H V = E8H V = ECH D Q CLR A B C Dn Dn + 1 Dn + 2 Interrupt request F/F Interrupt vector read Micro DMA acknowledge Interrupt request F/F Dn + 3 A B C interrupt vector read A B Interrupt mask F/F Micro DMA request Halt release if INTRQ2 to 0 ≥ IFF 2 to 0 then 1. INTRQ2 to 0 IFF2:0 RESET EI1 to 7 DI Interrupt request signal Micro DMA channel specification RESET (Reserved) INTWD INT0 INT1 INT2 INT3 INTALM0 INTALM1 INTALM2 INTALM3 INTALM4 INTTA0 INTTC0 INTTC1 INTTC2 INTTC3 INTTC4 INTTC5 INTTC6 INTTC7 Interrupt vector generator Highest priority interrupt level select Decoder S Q R Interrupt level detect D Q CLR S Selector Interrupt vector read INTTC0 Soft start if IFF = 7 then 0 Micro DMA counter interrupt

(1) Interrupt priority setting registers Symbol Name Address 7 6 5 4 3 2 1 0 INTAD INT0 IADC IADM2 IADM1 IADM0 I0C I0M2 I0M1 I0M0 R R/W R R/W INTE0AD INT0& INTAD enable F0H 0 0 0 0 0 0 0 0 INT2 INT1 I2C I2M2 I2M1 I2M0 I1C I1M2 I1M1 I1M0 R R/W R R/W INTE12 INT1&INT2 enable D0H 0 0 0 0 0 0 0 0 − INT3 − − − − I3C I3M2 I3M1 I3M0 − − R R/W INTE3 INT3 enable D1H Always write “0”. 0 0 0 0 INTTA1 (TMRA1) INTTA0 (TMRA0) ITA1C ITA1M2 ITA1M1 ITA1M0 IT A0C ITA0M2 ITA0M1 ITA0M0 R R/W R R/W INTETA01 INTTA0& INTTA1 enable D4H 0 0 0 0 0 0 0 0 INTAT3 (TMRA3) INTAT2 (TMRA2) ITA3C ITA3M2 ITA3M1 ITA3M0 IT A2C ITA2M2 ITA2M1 ITA2M0 R R/W R R/W INTETA23 INTTA2& INTTA3 enable D5H 0 0 0 0 0 0 0 0 INTTB1 (TMRB1) INTTB0 (TMRB0) ITB1C ITB1M2 ITB1M1 ITB1M0 IT B0C ITB0M2 ITB0M1 ITB0M0 R R/W R R/W INTETB01 INTTB0& INTTB1 enable D8H 0 0 0 0 0 0 0 0 − INTTBO0 − − − − ITBO0C ITBO0M2 ITBO0M1 ITBO0M0 R R/W R R/W INTETBO0 INTTBO0 (Overflow) enable DAH 0 0 0 0 0 0 0 0 INTTX0 INTRX0 ITX0C ITX0M2 ITX0M1 ITX0M0 IRX0C IRX0M2 IRX0M1 IRX0M0 R R/W R R/W INTES0 INTRX0& INTTX0 enable DBH 0 0 0 0 0 0 0 0 INTTX1 INTRX1 ITX1C ITX1M2 ITX1M1 ITX1M0 IRX1C IRX1M2 IRX1M1 IRX1M0 R R/W R R/W INTES1 INTRX1& INTTX1 enable DCH 0 0 0 0 0 0 0 0 − INTSBE0 − − − − ISBE0C ISBE0M2 ISBE0M1 ISBE0M0 − − R R/W INTESB0 INTSBE0 enable E3H Always write “0”. 0 0 0 0 INTALM1 INTALM0 IA1C IA1M2 IA1M1 IA1M0 IA0C IA0M2 IA0M1 IA0M0 R R/W R R/W INTEALM 01 INTALM0& INTALM1 enable E5H 0 0 0 0 0 0 0 0 INTALM3 INTALM2 IA3C IA3M2 IA3M1 IA3M0 IA2C IA2M2 IA2M1 IA2M0 R R/W R R/W INTEALM 23 INTALM2& INTALM3 enable E6H 0 0 0 0 0 0 0 0

Symbol Name Address 7 6 5 4 3 2 1 0 − INTALM4 − − − − IA4C IA4M2 IA4M1 IA4M0 − − R R/W INTEALM4 INTALM4 enable E7H Always write “0”. 0 0 0 0 − INTRTC − − − − IRC IRM2 IRM1 IRM0 − − R R/W INTERTC INTRTC enable E8H Always write “0”. 0 0 0 0 − INTKEY − − − − IKC IKM2 IKM1 IKM0 − − R R/W INTECKEY INTKEY enable E9H Always write “0”. 0 0 0 0 − INTLCD − − − − ILCD1C ILCDM2 ILCDM1 ILCDM0 − − R R/W INTLCD INTLCD enable EAH Always write “0”. 0 0 0 0 INTTX2 INTRX2 ITX2C ITX2M2 ITX2M1 ITX2M0 IRX2C IRX2M2 IRX2M1 IRX2M0 R R/W R R/W INTES2 INTRX2& INTTX2 enable EDH 0 0 0 0 0 0 0 0 − INTP0 − − − − IP0C IP0M2 IP0M1 IP0M0 − − R R/W INTEP0 INTP0 enable EEH Always write “0”. 0 0 0 0 IxxM2 IxxM1 IxxM0 Function (Write) 0 0 0 Disables interrupt requests 0 0 1 Sets interrupt priority level to 1 0 1 0 Sets interrupt priority level to 2 0 1 1 Sets interrupt priority level to 3 1 0 0 Sets interrupt priority level to 4 1 0 1 Sets interrupt priority level to 5 1 1 0 Sets interrupt priority level to 6 1 1 1 Disables interrupt requests Interrupt request flag

Symbol Name Address 7 6 5 4 3 2 1 0 INTTC1 (DMA1) INTTC0 (DMA0) ITC1C ITC1M2 ITC1M1 ITC1M0 ITC0C ITC0M2 ITC0M1 ITC0M0 R R/W R R/W INTETC01 INTTC0& INTTC1 enable F1H 0 0 0 0 0 0 0 0 INTTC3 (DMA3) INTTC2 (DMA2) ITC3C ITC3M2 ITC3M1 ITC3M0 ITC2C ITC2M2 ITC2M1 ITC2M0 R R/W R R/W INTETC23 INTTC2& INTTC3 enable F2H 0 0 0 0 0 0 0 0 INTTC5 (DMA5) INTTC4 (DMA4) ITC5C ITC5M2 ITC5M1 ITC5M0 ITC4C ITC4M2 ITC4M1 ITC4M0 R R/W R R/W INTETC45 INTTC4& INTTC5 enable F3H 0 0 0 0 0 0 0 0 INTTC7 (DMA7) INTTC6 (DMA6) ITC7C ITC7M2 ITC7M1 ITC7M0 ITC6C ITC6M2 ITC6M1 ITC6M0 R R/W R R/W INTETC67 INTTC6& INTTC7 enable F4H 0 0 0 0 0 0 0 0 − INTWD − − R − INTWDT INTWD F7H Always write “0”. 0 − − − IxxM2 IxxM1 IxxM0 Function (Write) 0 0 0 Disables interrupt requests 0 0 1 Sets interrupt priority level to 1 0 1 0 Sets interrupt priority level to 2 0 1 1 Sets interrupt priority level to 3 1 0 0 Sets interrupt priority level to 4 1 0 1 Sets interrupt priority level to 5 1 1 0 Sets interrupt priority level to 6 1 1 1 Disables interrupt requests Interrupt request flag

(2) External interrupt control Symbol Name Address 7 6 5 4 3 2 1 0 I3EDGE I2EDGE I1EDGE I0EDGE I0LE − W W W W R/W R/W 0 0 0 0 0 0 IIMC Interrupt input mode control F6H (Prohibit RMW) INT3EDGE 0: Rising 1: Falling INT2EDGE 0: Rising 1: Falling INT1EDGE 0: Rising 1: Falling INT0EDGE 0: Rising 1: Falling INT0 0: Edge mode 1: Level mode Always write “0”. *INT0 level enable

0 Edge detect INT

1 “H” level INT Note 1: Disable INT0 request before changing INT0 pin mode from level sense to edge sense. Setting example: DI LD (IIMC), XXXXXX0 - B ; Switches from level to edge. LD (INTCLR), 0AH ; Clears interrupt request flag. EI Note 2: X: Don’t care, –: No change Note 3: See electrical characteristics in section 4 for external interrupt input pulse width. Settings of External Interrupt Pin Function Interrupt Pin Name Mode Setting Method Rising edge IIMC<I0LE> = 0, INT0EDGE = 0 Falling edge IIMC<I0LE> = 0, INT0EDGE = 1 INT0 PC3 High level IIMC<I0LE> = 1 Rising edge INT1EDGE = 0 INT1 PC1 Falling edge INT1EDGE = 1 Rising edge INT2EDGE = 0 INT2 PC5 Falling edge INT2EDGE = 1 Rising edge INT3EDGE = 0 INT3 PC6 Falling edge INT3EDGE = 1

(3) SIO receive interrupt control Symbol Name Address 7 6 5 4 3 2 1 0 IR2LE IR1LE IR0LE W W W 1 1 1 SIMC SIO interrupt mode control F5H (Prohibit RMW) 0: INTRX2 edge mode 1: INTRX2 level mode 0: INTRX1 edge mode 1: INTRX1 level mode 0: INTRX0 edge mode 1: INTRX0 level mode INTRX0 rising edge enable

0 Rising edge detect INTRX0

1 “H” level INTRX0 INTRX1 level enable

0 Rising edge detect INTRX1

1 “H” level INTRX1 INTRX2 level enable

0 Rising edge detect INTRX2

1 “H” level INTRX2

(4) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in 8H Table 3.4.1 to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction. INTCLR ← 0AH ; Clears interrupt request flag INT0. Symbol Name Address 7 6 5 4 3 2 1 0 CLRV7 CLRV6 CLRV5 CLRV4 CLRV3 CLRV2 CLRV1 CLRV0 W 0 0 0 0 0 0 0 0 INTCLR Interrupt clear control F8H (Prohibit RMW) Interrupt vector (5) Micro DMA start vector registers These registers assign micro DMA processing to an sets which source corresponds to DMA. The interrupt source whose micro DMA start vector value matches the vector set in one of these registers is designated as the micro DMA start source. When the micro DMA transfer counter value reaches zero, the micro DMA transfer end interrupt corresponding to the channel is sent to the interrupt controller, the micro DMA start vector register is cleared, and the micro DMA start source for the channel is cleared. Therefore, in order for micro DMA processing to continue, the micro DMA start vector register must be set again during processing of the micro DMA transfer end interrupt. If the same vector is set in the micro DMA start vector registers of more than one channel, the lowest numbered channel takes priority. Accordingly, if the same vector is set in the micro DMA start vector registers for two different channels, the interrupt generated on the lower-numbered channel is executed until micro DMA transfer is complete. If the micro DMA start vector for this channel has not been set in the channel’s micro DMA start vector register again, micro DMA transfer for the higher-numbered channel will be commenced. (This process is known as micro DMA chaining.)

Symbol Name Address 7 6 5 4 3 2 1 0 DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 R/W 0 0 0 0 0 0 DMA0V DMA0 start vector 100H DMA0 start vector DMA1V5 DMA1V4 DMA1V3 DMA1V2 DMA1V1 DMA1V0 R/W 0 0 0 0 0 0 DMA1V DMA1 start vector 101H DMA1 start vector DMA2V5 DMA2V4 DMA2V3 DMA2V2 DMA2V1 DMA2V0 R/W 0 0 0 0 0 0 DMA2V DMA2 start vector 102H DMA2 start vector DMA3V5 DMA3V4 DMA3V3 DMA3V2 DMA3V1 DMA3V0 R/W 0 0 0 0 0 0 DMA3V DMA3 start vector 103H DMA3 start vector DMA4V5 DMA4V4 DMA4V3 DMA4V2 DMA4V1 DMA4V0 R/W 0 0 0 0 0 0 DMA4V DMA4 start vector 104H DMA4 start vector DMA5V5 DMA5V4 DMA5V3 DMA5V2 DMA5V1 DMA5V0 R/W 0 0 0 0 0 0 DMA5V DMA5 start vector 105H DMA5 start vector DMA6V5 DMA6V4 DMA6V3 DMA6V2 DMA6V1 DMA6V0 R/W 0 0 0 0 0 0 DMA6V DMA6 start vector 106H DMA6 start vector DMA7V5 DMA7V4 DMA7V3 DMA7V2 DMA7V1 DMA7V0 R/W 0 0 0 0 0 0 DMA7V DMA7 start vector 107H DMA7 start vector

(6) Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer, once started, to continue until the value in the transfer counter register reaches zero. Setting any of the bits in the register DMAB which correspond to a micro DMA channel (as shown below) to 1 specifies that any micro DMA transfer on that channel will be a burst transfer. Symbol Name Address 7 6 5 4 3 2 1 0 DBST7 DBST6 DBST5 DBST4 D BST3 DBST2 DBST1 DBST0 R/W 0 0 0 0 0 0 0 0 DMAB DMA burst 108H 1: DMA request on Burst mode

(7) Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore, if immediately before an interrupt is generated, the CPU fetches an instruction which clears the corresponding interrupt request flag, the CPU may execute this instruction in between accepting the interrupt and reading the interrupt vector. In this case, the CPU will read the default vector 0004H and jump to interrupt vector address FFFF04H. To avoid this, an instruction which clears an interrupt request flag should always be preceded by a DI instruction. And in the case of setting an interrupt enable again by EI instruction after the execution of clearing instruction, execute EI instruction after clearing and more than 3-instructions (e.g., “NOP” × 3 times). If placed EI instruction without waiting NOP instruction after execution of clearing instruction, interrupt will be enable before request flag is cleared. In the case of changing the value of the interrupt mask register <IFF2:0> by execution of POP SR instruction, disable an interrupt by DI instruction before execution of POP SR instruction. In addition, please note that the following two circuits are exceptional and demand special attention. In level mode INT0 is not an edge-triggered interrupt. Hence, in level mode the interrupt request flip-flop for INT0 does not function. The peripheral interrupt request passes through the S input of the flip-flop and becomes the Q output. If the interrupt input mode is changed from edge mode to level mode, the interrupt request flag is cleared automatically. INT0 level mode If the CPU enters the interrupt response sequence as a result of INT0 going from 0 to 1, INT0 must then be held at 1 until the interrupt response sequence has been completed. If INT0 is set to level mode so as to release a halt state, INT0 must be held at 1 from the time INT0 changes from 0 to 1 until the halt state is released. (Hence, it is necessary to ensure that input noise is not interpreted as a 0, causing INT0 to revert to 0 before the halt state has been released.) When the mode changes from level mode to edge mode, interrupt request flags which were set in level mode will not be cleared. Interrupt request flags must be cleared using the following sequence. DI LD (IIMC), 00H ; Switches from level to edge. LD (INTCLR), 0AH ; Clears interrupt request flag. NOP ; Wait EI execution NOP NOP EI INTRX In edge mode (The register SIMC<IRxLE> set to “0”), the interrupt request flip-flop can only be cleared by a reset or by reading the serial channel receive buffer. It cannot be cleared by writing INTCLR register. Note: The following instructions or pin input state changes are equivalent to instructions which clear the interrupt request flag. INT0: Instructions which switch to level mode after an interrupt request has been generated in edge mode. The pin input changes from high to low after an interrupt request has been generated in level mode. (“H” → “L”) INTRX: Instructions which read the receive buffer.

3.5 Function of Ports

TMP92C820 has I/O port pins that are shown in 0H Table 3.5.1. In addition to functioning as general-purpose I/O ports, these pins are also used by internal CPU and I/O functions. 1H Table 3.5.2 lists I/O registers and their specifications. Table 3.5.1 Port Functions (1/2) (R: PU = with programmable pull-up resistor, U = with pull-up resistor) Port Name Pin Name Number of Pins I/O R I/O Setting Pin Name for Built-in Function Port 1 P10 to P17 8 I/O − Bit D8 to D15 Port 2 P20 to P27 8 I/O − Bit D16 to D23 Port 3 P30 to P37 8 I/O − Bit D24 to D31 Port 4 P40 to P47 8 I/O* − Bit* A0 to A7 Port 5 P50 to P57 8 I/O* − Bit* A8 to A15 Port 6 P60 to P67 8 I/O* − Bit* A16 to A23 P70 1 Output − (Fixed) RD P71 1 Output − (Fixed) WRLL P72 1 Output − (Fixed) WRLU P73 1 Output − (Fixed) WRUL P74 1 Output − (Fixed) WRUU P75 1 Output − (Fixed) R/ W Port 7 P76 1 I/O − Bit WAIT P80 1 Output − (Fixed) CS0 , SDCSH P81 1 Output − (Fixed) CS1 , SDCSL P82 1 Output − (Fixed) CS2 , CS2A P83 1 Output − (Fixed) CS3 P84 1 Output − (Fixed) EA24, CS2B P85 1 Output − (Fixed) EA25, CS2C P86 1 Output − (Fixed) CS2D Port 8 P87 1 Output − (Fixed) SDCLK P90 1 I/O − Bit SCK P91 1 I/O − Bit SO, SDA P92 1 I/O − Bit SI, SCL P93 1 I/O − Bit CS2E P94 1 I/O − Bit CS2F P95 1 I/O − Bit CS2G , TXD2 Port 9 P96 1 I/O − Bit CSEXA , RXD2 Port A PA0 to PA7 8 Input U (Fixed) KI0 to KI7 PC0 1 I/O − Bit TA0IN PC1 1 I/O − Bit INT1, TA1OUT PC3 1 I/O − Bit INT0 PC5 1 I/O − Bit INT2, TA3OUT Port C PC6 1 I/O − Bit INT3, TB0OUT0 PF0 1 I/O − Bit TXD0 PF1 1 I/O − Bit RXD0 PF2 1 I/O − Bit SCLK0, 0CTS PF3 1 I/O − Bit TXD1 PF4 1 I/O − Bit RXD1 Port F PF5 1 I/O − Bit SCLK1, 1CTS *: When these ports are used as general-purpose I/O port, each bit can be set individually for input or output. However, each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port. All of general-purpose I/O ports except for port that used as address bus are operated as output port. Please be careful when using this setting.

Table 3.5.1 Port Functions (2/2) (R: PU = with programmable pull-up resistor, U = with pull-up resistor) Port Name Pin Name Number of Pins I/O R I/O Setting Pin Name for Built-in Function Port G PG0 to PG4 5 Input − (Fixed) AN0 to AN4, ADTRG (PG3) PJ0 1 Output − (Fixed) SDRAS PJ1 1 Output − (Fixed) SDCAS PJ2 1 Output − (Fixed) SDWE , SRWR PJ3 1 Output − (Fixed) SDLLDQM , SRLLB PJ4 1 Output − (Fixed) SDLUDQM , SRLUB PJ5 1 Output − (Fixed) SDULDQM , SRULB PJ6 1 Output − (Fixed) SDUUDQM , SRUUB Port J PJ7 1 Output − (Fixed) SDCKE PK0 1 Output − (Fixed) D1BSCP PK1 1 Output − (Fixed) D2BLP PK2 1 Output − (Fixed) D3BFR PK3 1 Output − (Fixed) DLEBCD PK4 1 Output − (Fixed) DOFFB Port K PK6 1 Output − (Fixed) ALARM , MLDALM Port L PL0 to PL7 8 I/O − Bit LD0 to LD7

Table 3.5.2 I/O Registers and Specifications (1/3) I/O Register Port Pin Name Specification Pn PnCR PnFC PnFC2 PnODE Input port X 0 Output port X 1 0 Port 1 P10 to P17 D8 to D15 bus X X 1 None None Input port X 0 Output port X 1 Port 2 P20 to P27 D16 to D23 bus X X 1 None None Input port X 0 Output port X 1 Port 3 P30 to P37 D24 to D31 bus X X 1 None None Input port* X 0* Output port* X 1* Port 4 P40 to P47 A0 to A7 output X 0 1 None None Input port* X 0* Output port* X 1* 0 Port 5 P50 to P57 A8 to A15 output X 0 1 None None Input port* X 0* Output port* X 1* 0 Port 6 P60 to P67 A16 to A23 output X 0 1 None None P70 to P75 Output port X None 0 P70 RD output P71 WRLL output P72 WRLU output P73 WRUL output P74 WRUU output P75 R/ W output X None 1 Input port X 0 0 Output port X 1 0 Port 7 P76 WAIT input X 0 1 None None P80 to P87 Output port X 0 0 P80 CS0 output X 1 0 CS1 output X 1 0 P81 SDCS output X X 1 CS2 output X 1 0 P82 CS2A output X X 1 P83 CS3 output X 1 0 EA24 output X 1 0 P84 CS2B output X X 1 EA25 output X 1 0 P85 CS2C output X X 1 P86 CS2D output X X 1 Port 8 P87 SDCLK output X None 1 0 None X: Don’t care *: When these ports are used as general-purpose I/O port, each bit can be set individually for input or output. However, each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port. All of general-purpose I/O ports except for port that used as address bus are operated as output port. Please be careful when using this setting.

Table 3.5.2 I/O Registers and Specifications (2/3) I/O Register Port Pin Name Specification Pn PnCR PnFC PnFC2 PnODE Input port X 0 0 0 P90 to P96 Output port X 1 0 0 SCK input X 0 0 0 P90 SCK output X X 1 0/1 SO output X 1 1 0/1 P91 SDA X X 1 1 SI input X 0 0 0 P92 SCL X X 1 1 CS2E output X 1 1 X SSCMD input X 0 1 X SSCMD output X 0 1 0 P93 SSCMD (Open drain) X 0 1 1 CS2F output X 1 1 X SSDAT input X 0 1 X SSDAT output X 0 1 0 P94 SSDAT (Open drain) X 0 1 1 CS2G output X 1 1 X TXD2 output X 0 1 0 P95 TXD2 (Open drain) X 0 1 1 CSEXA output X 1 1 X Port 9 P96 RXD2 input X 0 1 None X Input port X 0 Port A PA0 to PA7 KI0 to KI7 input X None

1 None None

Input port X 0 0 PC0, PC1, PC3 PC5, PC6 Output port X 1 0 PC0 TA0IN input X X 1 TA1OUT output X 1 1 PC1 INT1 input 0 0 1 PC3 INT0 input X 0 1 INT2 input 0 0 1 PC5 TA3OUT 1 1 1 INT3 input 0 0 1 Port C PC6 TB0OUT0 1 1 1 None None Input port X 0 0 PF0 to PF5 Output port X 1 0 TXD0 1 0 1 PF0 TXD0 (Open drain) 1 1 1 PF1 RXD0 input X 0 None SCLK0 input/output 1 0/1 1 PF2 0CTS input 1 0 1 TXD1 1 0 1 PF3 TXD1 (Open drain) 1 1 1 PF4 RXD1 input X 0 None SCLK1 input/output 1 0/1 1 Port F PF5 1CTS input 1 0 1 None None Input port X PG0 to PG4 AN0 to AN4 input X Port G PG3 ADTRG input X None None None None X: Don’t care

Table 3.5.2 I/O Registers and Specifications (3/3) I/O Register Port Pin Name Specification Pn PnCR PnFC PnFC2 PnODE PJ0 to PJ7 Output port X 0 0 PJ0 SDRAS output X 1 0 PJ1 SDCAS output X 1 0 SDWE output X 1 0 PJ2 SRWR output X X 1 SDLLDQM output X 1 0 PJ3 SRLLB output X X 1 SDLUDQM output X 1 0 PJ4 SRLUB output X X 1 SDULDQM output X 1 0 PJ5 SRULB output X X 1 SDUUDQM output X 1 0 PJ6 SRUUB output X X 1 Port J PJ7 SDCKE output X None 1 0 None PK0 to PK6 Output port X 0 PK0 D1BSCP output X 1 PK1 D2BLP output X 1 PK2 D3BFR output X 1 PK3 DLEBCD output X 1 PK4 DOFFB output X 1 ALARM output 1 1 Port K PK6 MLDALM output 0 None None None Input port X 0 0 Output port X 1 0 Port L PL0 to PL7 LD0 to LD7 output X X 1 None None X: Don’t care After a reset the port pins listed below function as general-purpose I/O port pins. A reset sets I/O pins, which can be programmed for either input, or output to be input ports pins. Setting the port pins for internal function use must be done in software.

3.5.1 Port 1 (P10 to P17)

Port 1 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P1CR and function register P1FC. In addition to functioning as a general-purpose I/O port, port 1 can also function as a data bus (D8 to D15). AM1 AM0 Function Setting after Reset is Released Don’t use this setting Data bus (D8 to D15) Data bus (D8 to D15) Don’t use this setting Figure 3.5.1 Port 1 External access (Data write) Internal data bus Reset P1CR write Output latch P1 write S A Selector B P1 read Port 1 P10 to P17 (D8 to D15) Function control (on bit basis) P1FC write D8 to D15 External access (Data read) Output buffer Direction control (on bit basis)

Bit symbol P17 P16 P15 P14 P13 P12 P11 P10 Read/Write R/W After reset Data from external port (Output latch register is cleared to 0) Port 1 Control Register 7 6 5 4 3 2 1 0 Bit symbol P17C P16C P15C P14C P13C P12C P11C P10C Read/Write W After reset 0 0 0 0 0 0 0 0 Function Refer to port 1 function setting Port 1 Function Register 7 6 5 4 3 2 1 0 Bit symbol P1F Read/Write W After reset 1 Function Refer to port 1 function setting Port 1 function register Note 1:Read-modify-write is prohibited for the registers P1CR and P1FC. Note 2:<P1XC> show X bit of P1CR register. Figure 3.5.2 Register for Port 1 P1FC<P1xF> P1CR<P1xC> 0 1

0 Input port

1 Output port

(D15 to D8) (0004H) P1CR (0006H) P1FC (0007H)

3.5.2 Port 2 (P20 to P27)

Port 2 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P2CR and function register P2FC. In addition to functioning as a general-purpose I/O port, port 2 can also function as a data bus (D16 to D23). AM1 AM0 Function Setting after Reset is Released Don’t use this setting Input port Data bus (D16 to D23) Don’t use this setting Figure 3.5.3 Port 2 External access (Data write) Internal data bus Reset P2CR write Output latch P2 write S A Selector B P2 read Port 2 P20 to P27 (D16 to D23) Function control (on bit basis) P2FC write D16 to D23 External access (Data read) Output buffer Direction control (on bit basis)

Bit symbol P27 P26 P25 P24 P23 P22 P21 P20 Read/Write R/W After reset Data from external port (Output latch register is cleared to 0) Port 2 Control Register 7 6 5 4 3 2 1 0 Bit symbol P27C P26C P25C P24C P23C P22C P21C P20C Read/Write W After reset 0 0 0 0 0 0 0 0 Function 0: Input 1: Output Port 2 Function Register 7 6 5 4 3 2 1 0 Bit symbol P2F Read/Write W After reset 0/1 Note2 Function 0: Port 1: Data bus (D16 to D23) Port 2 function register Note 1:Read-modify-write is prohibited for the registers P2CR and P2FC. Note 2: It is set to “Port” or “Data bus” by AM pin setting. Note 3:<P2XC> show X bit of P2CR register. Figure 3.5.4 Register for Port 2 (0008H) P2FC (000BH) P2FC<P2xF> P2CR<P2xC> 0 1 (D16 to D23) P2CR (000AH)

3.5.3 Port 3 (P30 to P37)

Port 3 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P3CR and function register P3FC. In addition to functioning as a general-purpose I/O port, port 3 can also function as a data bus (D24 to D31). AM1 AM0 Function Setting after Reset is Released Don’t use this setting Input port Data bus (D24 to D31) Don’t use this setting Figure 3.5.5 Port 3 External access (Data write) Internal data bus Reset P3CR write Output latch P3 write S A Selector B P3 read Port 3 P30 to P37 (D24 to D31) Function control (on bit basis) P3FC write D24 to D31 External access (Data read) Output buffer Direction control (on bit basis)

Bit symbol P37 P36 P35 P34 P33 P32 P31 P30 Read/Write R/W After reset Data from external port (Output latch register is cleared to 0) Port 3 Control Register 7 6 5 4 3 2 1 0 Bit symbol P37C P36C P35C P34C P33C P32C P31C P30C Read/Write W After reset 0 0 0 0 0 0 0 0 Function 0: Input 1: Output Port 3 Function Register 7 6 5 4 3 2 1 0 Bit symbol P3F Read/Write W After reset 0/1 Note2 Function 0: Port 1: Data bus (D24 to D31) Port 3 function register Note 1:Read-modify-write is prohibited for the registers P3CR and P3FC. Note 2: It is set to “Port” or “Data bus” by AM pin setting. Note 3:<P3XC> show X bit of P3CR register. Figure 3.5.6 Register for Port 3 (000CH) P3CR (000EH) P3FC (000FH) P3FC<P3xF> P3CR<P3xC> 0 1 (D24 to D31)

3.5.4 Port 4 (P40 to P47)

Port 4 is an 8-bit general-purpose I/O ports*. Bits can be individually set as either inputs or outputs by control register P4CR and function register P4FC*. In addition to functioning as a general-purpose I/O port, port 4 can also function as an address bus (A0 to A7). AM1 AM0 Function Setting after Reset is Released Don’t use this setting Address bus (A0 to A7) Address bus (A0 to A7) Don’t use this setting *: When these ports are used as general-purpose I/O port, each bit can be set individually for input or output. However, each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port. All of general-purpose I/O ports except for port that used as address bus are operated as output port. Please be careful when using this setting. Figure 3.5.7 Port 4 Internal data bus Direction control (on bit basis)* Reset P4CR write Output latch P4 write S B Selector A P4 read Port 4 P40 to P47 (A0 to A7) Function control (on bit basis) P4FC write Output buffer Internal address bus A0 to A7

Bit symbol P47 P46 P45 P44 P43 P42 P41 P40 Read/Write R/W After reset Data from external port (Output latch register is cleared to 0) Port 4 Control Register 7 6 5 4 3 2 1 0 Bit symbol P47C P46C P45C P44C P43C P42C P41C P40C Read/Write W After reset 0 0 0 0 0 0 0 0 Function 0: Input 1: Output (Note2) Port 4 Function Register 7 6 5 4 3 2 1 0 Bit symbol P47F P46F P45F P44F P43F P42F P41F P40F Read/Write W After reset 1 1 1 1 1 1 1 1 Function 0: Port 1: Address bus (A0 to A7) (Note2) Note1: Read-modify-write is prohibited for the registers P4CR and P4FC. Note2: When these ports are used as general-purpose I/O port, each bit can be set individually for input or output. However, each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port. All of general-purpose I/O ports except for port that used as address bus are operated as output port. Please be careful when using this setting. Figure 3.5.8 Port 4 Registers (0010H) P4CR (0012H) P4FC (0013H)

3.5.5 Port 5 (P50 to P57)

Port 5 is an 8-bit general-purpose I/O ports*. Bits can be individually set as either inputs or outputs by control register P5CR and function register P5FC*. In addition to functioning as a general-purpose I/O port, port 5 can also function as an address bus (A8 to A15). AM1 AM0 Function Setting after Reset is Released Don’t use this setting Address bus (A8 to A15) Address bus (A8 to A15) Don’t use this setting *: When these ports are used as general-purpose I/O port, each bit can be set individually for input or output. However, each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port. All of general-purpose I/O ports except for port that used as address bus are operated as output port. Please be careful when using this setting. Figure 3.5.9 Port 5 Internal data bus Direction control (on bit basis)* Reset P5CR write Output latch P5 write S B Selector A P5 read Port 5 P50 to P57 (A8 to A15) Function control (on bit basis) P5FC write Output buffer Internal address bus A8 to A15

Bit symbol P57 P56 P55 P54 P53 P52 P51 P50 Read/Write R/W After reset Data from external port (Output latch register is cleared to 0) Port 5 Control Register 7 6 5 4 3 2 1 0 Bit symbol P57C P56C P55C P54C P53C P52C P51C P50C Read/Write W After reset 0 0 0 0 0 0 0 0 Function 0: Input 1: Output (Note2) Port 5 Function Register 7 6 5 4 3 2 1 0 Bit symbol P57F P56F P55F P54F P53F P52F P51F P50F Read/Write W After reset 1 1 1 1 1 1 1 1 Function 0: Port 1: Address bus (A8 to A15) (Note2) Note1: Read-modify-write is prohibited for the registers P5CR and P5FC. Note2: When these ports are used as general-purpose I/O port, each bit can be set individually for input or output. However, each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port. All of general-purpose I/O ports except for port that used as address bus are operated as output port. Please be careful when using this setting. Figure 3.5.10 Register for Port 5 (0014H) P5CR (0016H) P5FC (0017H)

3.5.6 Port 6 (P60 to P67)

Port 6 is an 8-bit general-purpose I/O ports*. Bits can be individually set as either inputs or outputs by control register P6CR and function register P6FC*. In addition to functioning as a general-purpose I/O port, port 6 can also function as an address bus (A16 to A23). AM1 AM0 Function Setting after Reset is Released Don’t use this setting Address bus (A16 to A23) Address bus (A16 to A23) Don’t use this setting *: When these ports are used as general-purpose I/O port, each bit can be set individually for input or output. However, each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port. All of general-purpose I/O ports except for port that used as address bus are operated as output port. Please be careful when using this setting. Figure 3.5.11 Port 6 Internal data bus Direction control (on bit basis)* Reset P6CR write Output latch P6 write S B Selector A P6 read Port 6 P60 to P67 (A16 to A23) Function control (on bit basis) P6FC write Output buffer Internal address bus A16 to A23

Bit symbol P67 P66 P65 P64 P63 P62 P61 P60 Read/Write R/W After reset Data from external port (Output latch register is cleared to 0) Port 6 Control Register 7 6 5 4 3 2 1 0 Bit symbol P67C P66C P65C P64C P63C P62C P61C P60C Read/Write W After reset 0 0 0 0 0 0 0 0 Function 0: Input 1: Output (Note2) Port 6 Function Register 7 6 5 4 3 2 1 0 Bit symbol P67F P66F P65F P64F P63F P62F P61F P60F Read/Write W After reset 1 1 1 1 1 1 1 1 Function 0: Port 1: Address bus (A16 to A23) (Note2) Note1: Read-modify-write is prohibited for the registers P6CR and P6FC. Note2: When these ports are used as general-purpose I/O port, each bit can be set individually for input or output. However, each bit cannot be set individually for input or output even if 1bit or more bits are used as address bus in same port. All of general-purpose I/O ports except for port that used as address bus are operated as output port. Please be careful when using this setting. Figure 3.5.12 Port 6 Registers (0018H) P6CR (001AH) P6FC (001BH)

3.5.7 Port 7 (P70 to P76)

Port 7 is a 7-bit general-purpose I/O port (P70 to P75 are used for output only). Bits can be individually set as either inputs or outputs by control register P7CR and function register P7FC. In addition to functioning as a general-purpose I/O port, P70 to P75 pins can also function as read/write strobe signals to connect with an external memory. P76 pin can also function as wait input. A reset initializes P70 to P75 pins to output port mode, and P76 pin to input port mode. AM1 AM0 Function Setting after Reset is Released Don’t use this setting RD pin RD pin Don’t use this setting Figure 3.5.13 Port 7 (P70) Internal data bus Reset Output latch P7 write S A Selector B P7 read P70 ( RD ) Function control (on bit basis) P7FC write Output buffer RD

Figure 3.5.16 Port 7 (P76) Internal data bus Function control (on bit basis) Reset P7CR write P7 read P76 ( WAIT ) P7 write Output buffer S Output latch Internal wait signal Direction control (on bit basis) P7FC write

Bit symbol P76 P75 P74 P73 P72 P71 P70 Read/Write R/W After reset Data from external port (Note) 1 1 1 1 1 1 Note: Output latch register is cleared to 0. Port 7 Control Register 7 6 5 4 3 2 1 0 Bit symbol P76C Read/Write W After reset 0 Function 0: Input 1: Output Port 7 Function Register 7 6 5 4 3 2 1 0 Bit symbol P76F P75F P74F P73F P72F P71F P70F Read/Write W After reset 0 0 0 0 0 0 1 Function 0: Port 1: WAIT 0: Port 1: R/ W 0: Port WRUU 0: Port WRUL 0: Port WRLU 0: Port WRLL 0: Port RD Note: Read-modify-write is prohibited for the registers P7CR and P7FC. Figure 3.5.17 Register for Port 7 (001CH) P7CR (001EH) P7FC (001FH)

3.5.8 Port 8 (P80 to P87)

Ports 80 to 87 are 8-bit output ports. Resetting sets output latch of P82 to “0” and output latches of P80 to P81, P83 to P87 to “1”. Port 8 also function as chip-select output (CS0 to CS3 ), extend address output (EA24, EA25), extend chip-select output (CS2A , CS2B , CS2C , CS2D ), port 8 also function as output pin for SDRAM controller (SDCSL , SDCSH , SDCLK), Above setting is used the function register P8FC. Writing “1” in the corresponding bit of P8FC, P8FC2 enables the respective functions. Resetting resets P87F of P8FC to “1”, P80F to P86F of P8FC to “0”, and P8FC2 to “0”, sets all bits to output ports. Figure 3.5.18 Port 8 Internal data bus Function control 2 (on bit basis) Reset P8FC2 write Output lacth P8 write S A Selector B C P8 read P80 ( CS0 , SDCSH ) P81 ( CS1 , SDCSL ) P82 ( CS2 , CS2A ) P83 ( CS3 ) P84 (EA24, CS2B ) P85 (EA25, CS2C ) P86 ( CS2D ) P87 (SDCLK) Function control (on bit basis) P8FC write SDCSH , SDCSL , CS2A , “1”, CS2B , CS2C , CS2D , “1” CS0 , CS1 , CS2 , CS3 , EA24, EA25, “1”, SDCLK

Bit symbol P87 P86 P85 P84 P83 P82 P81 P80 Read/Write R/W After reset 1 1 1 1 1 0 1 1 Port 8 Function Register 7 6 5 4 3 2 1 0 Bit symbol P87F − P85F P84F P83F P82F P81F P80F Read/Write W After reset 1 0 0 0 0 0 0 0 Function 0: Port 1: SDCLK Always write “0”. 0: Port 1: EA25 0: Port 1: EA24 0: Port CS3 0: Port CS2 0: Port CS1 0: Port CS0 Port 8 Function Register 2 7 6 5 4 3 2 1 0 Bit symbol − P86F2 P85F2 P84F2 − P82F2 P81F2 P80F2 Read/Write W After reset 0 0 0 0 0 0 0 0 Function Always write “0”. 0: <P86F> 1: CS2D 0: <P85F> CS2C 0: <P84F> CS2B Always write “0”. 0: <P82F> 1: CS2A 0: <P81F> 1: SDCSL 0: <P80F> SDCSH Note :Read-modify-write is prohibited for P8FC and P8FC2 . Figure 3.5.19 Registers for Port 8 (0020H) P8FC (0023H) P8FC2 (0021H)

3.5.9 Port 9 (P90 to P96)

P90 to P96 are 7-bit general-purpose I/O port. I/O can be set on bit basis using the control register. Resetting sets port 9 to input port and all bits of output latch to “1”. Writing in the corresponding bit of P9FC enables the respective functions. Resetting resets the P9FC to “0”, and sets all bits to input ports. (1) Port 90 (SCK), port 91 (SO/SDA), and port 92 (SI/SCL) Ports 90 to 92 are general-purpose I/O port. It is also used as SCK (Clock signal for SIO mode), SO (Data output for SIO mode), SDA (Data input for I2C mode), SI (Data input for SIO mode), and SCL (Clock input/output for I2C mode) for serial bus interface. Figure 3.5.20 Port 9 (P90 to P92) Internal data bus Direction control (on bit basis) Reset P9CR write P9 write P9 read P90 (SCK) P91 (SO/SDA) P92 (SI/SCL) Function control (on bit basis) P9FC write SCK output SO output SDA output SCL output S Output latch S B Selector A S A Selector B SCK input SDA input SI/SCL input Open-drain possible P9ODE<P91ODE> <P92ODE>

Bit symbol P96 P95 P94 P93 P92 P91 P90 Read/Write R/W After reset Data from external port (Output latch register is set to 1) Port 9 Control Register 7 6 5 4 3 2 1 0 Bit symbol P96C P95C P94C P93C P92C P91C P90C Read/Write W After reset 0 0 0 0 0 0 0 Function 0: Input 1: Output Port 9 Function Register 7 6 5 4 3 2 1 0 Bit symbol P96F P95F P94F P93F P92F P91F P90F Read/Write W After reset 0 0 0 0 0 0 0 Function 0: Port 1: RXD2, CSEXA 0: Port 1: TXD2, CS2G 0: Port 1: CS2F 0: Port CS2E 0: Port, SI, 1: SCL Note 2 0: Port 1: SO, SDA 0: Port, SCK input 1: SCK Output Note 2 CS2E setting <P93C> <P93F> 0 1

0 Input port Output port

1 (Reserved) CS2E CS2F setting <P94C> <P94F> 0 1 1 (Reserved) CS2F TXD2, CS2G setting <P95C> <P95F> 0 1

1 TXD2 CS2G

Bit symbol P95ODE − − P92ODE P91ODE Read/Write W W W W W After reset 0 0 0 0 0 Function 0: 3 states 1: Open drain Always write “0”. Always write “0”. 0: 3 states 1: Open drain 0: 3 states 1: Open drain Note 1: Read-modify-write is prohibited for P9CR, P9FC, and P9ODE. Note 2: When using SI and SCK input function, set P9FC<P92F,P90F> to “0” (Function setting). Figure 3.5.23 Register for Port 9 (0024H) P9CR (0026H) P9FC (0027H) P9ODE (0025H)

3.5.10 Port A (PA0 to PA7)

Ports A0 to A7 are 8-bit input ports with pull-up resistor. In addition to functioning as general-purpose I/O ports, ports A0 to A7 can also key-on wakeup function as keyboard interface. The various functions can each be enabled by writing a “1” to the corresponding bit of the port A function register (PAFC). Resetting resets all bits of the register PAFC to “0” and sets all pins to be input port. Figure 3.5.24 Port A When PAFC = “1”, if either of input of KI0 to KI7 pins falls down, INTKEY interrupt is generated. INTKEY interrupt can be used release all HALT mode. Internal data bus PA0 to PA7 (KI0 to KI7) INTKEY Start edge detection Key-on enable (on bit basis) PAFC write PA read Pull-up resistor Reset PA0 to PA7 8-input OR

Bit symbol PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Read/Write R After reset Data from external port Port A Function Register 7 6 5 4 3 2 1 0 Bit symbol PA7F PA6F PA5F PA4F PA3F PA2F PA1F PA0F Read/Write W After reset 0 0 0 0 0 0 0 0 Function 0: KEY-IN disable 1: KEY-IN enable Key-IN of Port A

0 Disable

1 Enable

Note: Read-modify-write is prohibited for the registers PAFC. Figure 3.5.25 Register for Port A PA (0028H) PAFC (002BH)

3.5.11 Port C (PC0, PC1, PC3, PC5 and PC6)

Port C is 5-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets port C to be an input port. In addition to functioning as a general-purpose I/O port, port C can also functions as I/O pin for timers (TA0IN, TA1OUT, TA3OUT, TB0OUT0), input pin for external interruption (INT0 to INT3). Above setting is used the function register PCFC and PCCR register. Edge select of external interruption establishes it with IIMC register, which there is in interruption controller. Resetting resets bits of the register PCCR and PCFC to “0” and sets all pins to be input port. (1) PC0 (TA0IN) In addition to function as I/O port, port 0 can also function as input pin TA0IN of timer channel 0. Figure 3.5.26 Port C (PC0) Note: Cannot read the output latch data when output mode. Internal data bus Direction control (on bit basis) Reset PCCR write PC read PC0 (TA0IN) PC write S Output latch S B Selector A Function control (on bit basis) PCFC write TA0IN

(2) PC1 (INT1, TA1OUT), PC5 (INT2, TA3OUT) and PC6 (INT3, TB0OUT0) Figure 3.5.27 Port C (PC1, PC5, PC6) Note: Cannot read the output latch data when output mode. Internal data bus Direction control (on bit basis) Reset PCCR write PC write PC read PC1 (INT1, TA1OUT) PC5 (INT2, TA3OUT) PC6 (INT3, TB0OUT0) Function control (on bit basis) PCFC write S Output latch Rising/falling edge detection IIMC<I1EDGE, I2EDGE, I3EDGE> A S Selector B INT1 INT2 INT3 S B Selector A TA1OUT TA3OUT TB0OUT0

(3) PC3 (INT0) Figure 3.5.28 Port C (PC3) Internal data bus Direction control (on bit basis) Reset PCCR write PC write PC read PC3 (INT0) Function control (on bit basis) PCFC write S Output latch S B Selector A Level/edge select and Rising/falling select IIMC<I0LE, I0EDGE> INT0

Bit symbol PC6 PC5 PC3 PC1 PC0 Read/Write R/W R/W R/W After reset Data from external port (Output latch register is set to 1) Data from external port (Output latch register is set to 1) Data from external port (Output latch register is set to 1) Port C Control Register 7 6 5 4 3 2 1 0 Bit symbol PC6C PC5C PC3C PC1C PC0C Read/Write W W W After reset 0 0 0 0 0 Function 0: Input 1: Output 0: Input 1: Output 0: Input 1: Output Port C Function Register 7 6 5 4 3 2 1 0 Bit symbol PC6F PC5F PC3F PC1F PC0F Read/Write W W W After reset 0 0 1 0 0 Function 0: Port 1: INT3 TB0OUT0 0: Port 1: INT2 TA3OUT 0: Port 1: INT0 0: Port 1: INT1 TA1OUT 0: Port 1: TA0IN INT1, TA1OUT setting <PC1C> <PC1F> 0 1

1 INT1 TA1OUT

INT2, TA3OUT setting <PC5C> <PC5F> 0 1

1 INT2 TA3OUT

INT3, TB0OUT0 setting <PC6C> <PC6F> 0 1

1 INT3 TB0OUT0

Note 1: Read-modify-write is prohibited for the registers PCCR and PCFC. Note 2: PC0/TA0IN pin does not have a register changing port/function. For example, when it is used as an input port, the input signal is inputted to 8-bit timer. Note 3: Cannot read the output latch data when PC0, PC1, PC5, and PC6 are output mode. Figure 3.5.29 Register for Port C PC (0030H) PCCR (0032H) PCFC (0033H)

3.5.12 Port F (PF0 to PF5)

Ports F0 to F5 are 6-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets PF0 to PF5 to be an input ports. It also sets all bits of the output latch register to “1”. In addition to functioning as general-purpose I/O port pins, PF0 to PF5 can also function as the I/O for serial channels 0 and 1. A pin can be enabled for I/O by writing a “1” to the corresponding bit of the port F function register (PFFC). By resetting, clears all bits of the registers PFCR and PFFC to 0 and sets all pins to be input ports. (1) Ports PF0 (TXD0) and PF3 (TXD1) As well as functioning as I/O port pins, port PF0 and PF3 can also function as serial channel TXD output pins. Figure 3.5.30 Port F (PF0 and PF3) Internal data bus Direction control (on bit basis) Reset PFCR write PF write PF read PF0 (TXD0) PF3 (TXD1) Function control (on bit basis) PFFC write S Output latch S B Selector A S A Selector B TXD0, TXD1 Open-drain set possible <PF0F = 1, PF0C = 0 PF3F = 1, PF3C = 0>

(2) Ports PF1 and PF4 (RXD0, RXD1) Ports PF1 and PF4 are I/O port pins and can also is used as RXD input for the serial channels. Figure 3.5.31 Port F (PF1 and PF4) Internal data bus Direction control (on bit basis) Reset PFCR write PF write PF read PF1 (RXD0) PF4 (RXD1) S Output latch S B Selector A RXD0, RXD1

(3) Ports PF2 ( CTS0 , SCLK0) and PF5 (CTS1 , SCLK1) Ports PF2 and PF5 are I/O port pins and can also be used as CTS input or SCLK input/output for the serial channels. Figure 3.5.32 Port F (PF2 and PF5) Internal data bus Direction control (on bit basis) Reset PFCR write PF write PF read PF2 (SCLK0, CTS0 ) PF5 (SCLK1, CTS1 ) Function control (on bit basis) PFFC write S Output latch S B Selector A S A Selector B SCLK0, SCLK1 output CTS0 , CTS1 SCLK0, SCLK1 input

Bit symbol PF5 PF4 PF3 PF2 PF1 PF0 Read/Write R/W After reset Data from external port (Output latch register is set to 1) Port F Control Register 7 6 5 4 3 2 1 0 Bit symbol PF5C PF4C PF3C PF2C PF1C PF0C Read/Write W After reset 0 0 0 0 0 0 Function 0: Input 1: Output Port F Function Register 7 6 5 4 3 2 1 0 Bit symbol PF5F PF3F PF2F PF0F Read/Write W W W After reset 0 0 0 0 Function 0: Port 1: SCLK1 output 0: Port 1: TXD1 0: Port 1: SCLK0 output 0: Port 1: TXD0 3 states, Open-drain setting <PF3C> <PF3F> 0 1

1 TXD1 (Open drain) TXD1 (3 states)

<PF1C> <PF1F> 0 1

1 TXD0 (Open drain) TXD0 (3 states)

Note 1: Read-modify-write is prohibited for the registers PFCR and PFFC. Note 2: PF1/RXD0 and PF4/RXD1 pins do not hav e a register changing Port/Function. For example, when it is used as an input port, the input signal is inputted to SIO as the serial receive data. Note 3: PF1 and PF3 pins dose not have a register changing 3 states/Open drain. Figure 3.5.33 Register for Port F PF (003CH) PFCR (003EH) PFFC (003FH)

3.5.13 Port G (PG0 to PG4)

PG0 to PG4 are 5-bit input port and can also be used as the analog input pins for the internal AD converter. PG3 can also be used as ADTRG pin for the AD converter. Figure 3.5.34 Port G Port G Register 7 6 5 4 3 2 1 0 Bit symbol PG4 PG3 PG2 PG1 PG0 Read/Write R After reset Data from external port Note: The input channel selection of AD converte r and the permission of ADTRG input are set by AD converter mode register ADMOD1. Figure 3.5.35 Register for Port G Internal data bus ADTRG (only PG3) PG read Port G PG0 to PG4 (AN0 to AN4) AD convertor Channel selector AD read Convertion result register PG (0040H)

3.5.14 Port J (PJ0 to PJ7)

PJ0 to PJ7 are 8-bit output port. Resetting sets the output latch PJ to “1” and PJ0 to PJ7 pins output “1”. In addition to functioning as output port, port J also functions as output pins for SDRAM ( SDRAS , SDCAS , SDWE , SDLLDQM, SDLUDQM, SDULDQM, SDUUDQM, SDCKE) and SRAM ( SRWR , SRLLB , SRLUB , SRULB , SRUUB ). Above setting is used the function register PJFC. Figure 3.5.36 Port J Internal data bus Function control2 (on bit basis) Reset PJFC2 write PJ write PJ read PJ0 ( SDRAS ) PJ1 ( SDCAS ) PJ2 ( SDWE , SRWR ) PJ3 (SDLLDQM, SRLLB ) PJ4 (SDLUDQM, SRLUB ) PJ5 (SDULDQM, SRULB ) PJ6 (SDUUDQM, SRUUB ) PJ7 (SDCKE) Function control (on bit basis) PJFC write Output latch S A Selector B C “1”, “1”, SRWR , SRLLB , SRLUB , SRULB , SRUUB , “1” SDRAS , SDCAS , SDWE , SDLLDQM, SDLUDQM, SDULDQM, SDUUDQM, SDCKE Outpt buffer

Bit symbol PJ7 PJ6 PJ 5 PJ4 PJ3 PJ2 PJ1 PJ0 Read/Write R/W After reset 1 1 1 1 1 1 1 1 Port J Function Register 7 6 5 4 3 2 1 0 Bit symbol PJ7F PJ6F PJ5F PJ4F PJ3F PJ2F PJ1F PJ0F Read/Write W After reset 0 0 0 0 0 0 0 0 Function 0: Port 1: SDCKE 0: Port 1: SDUUDQM 0: Port 1: SDULDQM 0: Port 1: SDLUDQM 0: Port 1: SDLLDQM 0: Port 1: SDWE 0: Port SDCAS 0: Port SDRAS Port J Function Register 2 7 6 5 4 3 2 1 0 Bit symbol − PJ6F2 PJ5F2 PJ4F2 PJ3F2 PJ2F2 − − Read/Write W After reset 0 0 0 0 0 0 0 0 Function Always write “0”. 0: <PJ6F> 1: SRUUB 0: <PJ5F> SRULB 0: <PJ4F> SRLUB 0: <PJ3F> SRLLB 0: <PJ2F> 1: SRWR Always write “0”. Always write “0”. Note: Read-modify-write is prohibit ed for the registers PJFC and PJFC2. Figure 3.5.37 Register for Port J PJ (004CH) PJFC (004FH) PJFC2 (004DH)

3.5.15 Port K (PK0 to PK4, PK6)

Port K is 6-bit output port. Resetting sets the output latch PK to “1”, and port K pins output to “1”. In addition to functioning as output ports, port K also functions as output pins for LCD controller (D1BSCP, D2BLP, D3BFR, DLEBCD and DOFFB), output pins for RTC alarm ( ALARM ) and output pin for melody/alarm generator (MLDALM, MLDALM ). Above setting is used the function register PKFC. Only PK6 has two output function which ALARM and MLDALM . This selection is used PK<PK6>. Resetting resets the function register PKFC to “0”, and sets all ports to output ports. Figure 3.5.38 Port K (PK0 to PK4) Internal data bus Reset Output latch PK write S A Selector B PK read PK0 (D1BSCP) PK1 (D2BLP) PK2 (D3BFR) PK3 (DLEBCD) PK4 (DOFFB) Function control (on bit basis) PKFC write Outpt buffer D1BSCP, D2BLP, D3BFR, DLEBCD, DOFFB

3.5.16 Port L (PL0 to PL7)

PL0 to PL7 are 8-bit general-purpose I/O ports. Each bit can be set individually for input or output using the control register PLCR. Resetting, the control register PLCR to “0” and sets port L to input ports. It also sets all bits of the output latch register to “1”. In addition to functioning as a general-purpose I/O port, port L can also function as a data bus for LCD controller (LD0 to LD7). Above setting is used the function register PLFC. Figure 3.5.41 Port L Internal data bus Direction control (on bit basis) Reset PLCR write PL write PL read Port E PL0 to PL7 (LD0 to LD7) Function control (on bit basis) PLFC write S Output latch S B Selector A S A Selector B LD7 to LD0

Bit symbol PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 Read/Write R/W After reset Data from external port (Output latch register is set to 1) Port L Control Register 7 6 5 4 3 2 1 0 Bit symbol PL7C PL6C PL5C PL4C PL3C PL2C PL1C PL0C Read/Write W After reset 0 0 0 0 0 0 0 0 Function 0: Input 1: Output Port L Function Register 7 6 5 4 3 2 1 0 Bit symbol PL7F PL6F PL5F PL4F PL3F PL2F PL1F PL0F Read/Write W After reset 0 0 0 0 0 0 0 0 Function 0: Port 1: Data bus for LCDC (LD7 to LD0) Figure 3.5.42 Register for Port L PL (0054H) PLCR (0056H) PLFC (0057H)

3.6 Memory Controller

3.6.1 Functions

TMP92C820 has a memory controller with a variable 4-block address area that controls as follows. (1) 4-block address area support Specifies a start address and a block size for 4-block address area (Block 0 to block 5). (2) Connecting memory specifications Specifies SRAM, ROM as memories to connect with the selected address areas. (3) Data bus size selection Whether 8 bits, 16 bits or 32 bits is selected as the data bus size of the respective block address areas. (4) Wait control Wait specification bit in the control register and WAIT input pin control the number of waits in the external bus cycle. Read cycle and write cycle can specify the number of waits individually. The number of waits is controlled in five mode mentioned below. 0 waits, 1 wait, 2 waits, 3 waits N waits (control with WAIT pin)

3.6.2 Control Register and Operation after Reset Release

This section describes the registers to control the memory controller, the state after reset release and necessary settings. (1) Control register The control registers of the memory controller are as follows.

• Control register: BnCSH/BnCSL (n = 0 to 3, EX) Sets the basic functions of the memory controller, that is the connecting memory type, the number of waits to be read and written.
• Memory start address register: MSARn (n = 0 to 3) Sets a start address in the selected address areas.
• Memory address mask register: MAMR (n = 0 to 3) Sets a block size in the selected address areas. In addition to setting of the above-mentioned registers, it is necessary to set the following registers to control ROM page mode access.
• Page ROM control register: PMEMCR Sets to executed ROM page mode accessing. (2) Operation after reset release The start data bus size is determined depending on the state of AM1/AM0 pins just after reset release. Then, the external memory is accessed as follows: AM1 AM0 Start Mode 0 0 Don’t use this setting 0 1 Start with 16-bit data bus 1 0 Start with 32-bit data bus 1 1 Don’t use this setting AM1/AM0 pins are valid only just after reset release. In the other cases, the data bus width is set to the value set to BnBUS bit of the control register. After reset, only control register (B2CSH/B2CSL) of the block address area 2 is automatically valid. The data bus width which is specified by AM1/AM0 pin is loaded to the bit to specify the bus width of the control register in the block address area 2. The block address area 2 is set to address 000000H to FFFFFFH after reset. After reset release, the block address areas are specified by the memory start address register (MSARn) and the memory address mask register (MAMRn). Then the control register (BnCS) is set. Set the enable bit (BnE) of the control register to “1” to enable the setting.

3.6.3 Basic Functions and Register Setting

In this section, setting of the block address area, the connecting memory, and the number of waits out of the memory controller’s functions are described. (1) Block address area specification The block address area is specified by two registers. The memory start address register (MSARn) sets the start address of the block address areas. The memory controller compares between the register value and the address every bus cycles. The address bit which is masked by the memory address mask register (MAMRn) is not compared by the memory controller. The block address area size is determined by setting the memory address mask register. The set value in the register is compared with the block address area on the bus. If the compared result is a match, the memory controller sets the chip select signal (CSn ) to “low”. (i) Setting memory st art address register The MS23 to MS16 bits of the memory start address register respectively correspond with addresses A23 to A16. The lower start address A15 to A0 are always set to address 0000H. Therefore the start address of the block address area are set to addresses 000000H to FF0000H every 64 Kbytes. (ii) Setting memory a ddress mask registers The memory address mask register sets whether an address bit is compared or not. Set the register to “0” to compare, or to “1” not to compare. The address bit to be set is depended on the block address area. Block address area 0: A20 to A8 Block address area 1: A21 to A8 Block address area 2 to 3: A22 to A15 The above-mentioned bits are always compared. The block address area size is determined by the compared result. The size to be set depending on the block address area is as follows. Size (bytes) CS Area 256 512 32 K 64 K 128 K 256 K 512 K 1 M 2 M 4 M 8 M Note: After reset release, only the control register of the block address area 2 is valid. The control register of the block address area 2 has <B2M> bit. Setting <B2M> bit to “0” sets the block address area 2 to addresses 000000H to FFFFFFH. Setting <B2M> bit to “1” specifies the start address and the address area size as it is in the other block address area.

(iii) Example of register setting To set the block address area 512 bytes from address 110000H, set the register as follows. MSAR1 Register 7 6 5 4 3 2 1 0 Bit symbol M1S23 M1S22 M1S21 M1S20 M1S19 M1S18 M1S17 M1S16 Specified value 0 0 0 1 0 0 0 1 M1S23 to M1S16 bits of the memory start address register MSAR1 correspond with address A23 to A16. A15 to A0 are set to “0”. Therefore setting MSAR1 to the above-mentioned value specifies the start address of the block address area to address 110000H. The start address is set as it is in the other block address areas. MAMR1 Register 7 6 5 4 3 2 1 0 Bit symbol M1V21 M1V20 M1V19 M1V18 M1V17 M1V16 M1V15 to M1V9 M1V8 Specified value 0 0 0 0 0 0 0 1 M1V21 to M1V16 and M1V8 bits of the memory address mask register MAMR1 set whether address A21 to A16 and A8 are compared or not. Set the register to “0” to compare, or to “1” not to compare. M1V15 to M1V9 bits set whether address A15 to A9 are compared or not with 1 bit. A23 and A22 are always compared. Setting the above-mentioned compares A23 to A9 with the values set as the start addresses. Therefore 512 bytes of addresses 110000H to 1101FFH are set as the block address area 1, and compared with the addresses on the bus. If the compared result is a match, the chip select signal CS1 is set to “low”. The other block address area sizes are specified like this. Similarly, A23 is always compared in block address areas 2 to 3. Whether A22 to A15 are compared or not is set to register. Note: When the set block address area over laps with the built-in memory area, or both two address areas overlap, the block address area is processed according to priority as follows. Built-in I/O > Built-in memory > Block address area 0 > 1 > 2 > 3 > CSEX also that any accessed areas out side the address spaces set by CS0 to CS3 are processed as the CSEX space. Therefore, settings of CSEX apply for the control of wait cycles, data bus width, etc,.

(2) Connection memory specification Setting the BnOM1 to 0 bit of the control register (BnCSH) specifies the memory type to be connected with the block address areas. The interface signal is output according to the set memory as follows BnOM1, BnOM0 Bit (BnCSH register) BnOM1 BnOM0 Function 0 0 SRAM/ROM (Default) 0 1 (Reserved) 1 0 (Reserved) 1 1 SDRAM SDRAM is set only in block address are 1. (3) Data bus width specification The data bus width is set for every block address area. The bus size is set by the BnBUS1 and BnBUS0 bits of the control register (BnCSH) as follows. BnBUS Bit (BnCSH register) BnBUS1 BnBUS0 Function 0 0 8-bit bus mode (Default) 0 1 16-bit bus mode 1 0 32-bit bus mode 1 1 (Reserved) This way of changing the data bus size depending on the address being accessed is called “dynamic bus sizing”. The part where the data is output to is depended on the data size, the bus width and the start address. Note: Since there is a possibility of abnormal writing/reading of the data if two memories with different bus width are put in consecutive address, do not execute a access to both memories with one command.

Size (Bit) Operand Start Address Memory Data Size (Bit) CPU Address D32 to D24 D23 to D16 D15 to D8 D7 to D0 4n + 0 8/16/32 4n + 0 xxxxx xxxxx xxxxx b7 to b0 8 4n + 1 xxxxx xxxxx xxxxx b7 to b0 4n + 1 16/32 4n + 1 xxxxx xxxxx b7 to b0 xxxxx 8/16 4n + 2 xxxxx xxxxx xxxxx b7 to b0 4n + 2 32 4n + 2 xxxxx b7 to b0 xxxxx xxxxx 8 4n + 3 xxxxx xxxxx xxxxx b7 to b0 16 4n + 3 xxxxx xxxxx b7 to b0 xxxxx 4n + 3 32 4n + 3 b7 to b0 xxxxx xxxxx xxxxx (1) 4n + 0 xxxxx xxxxx xxxxx b7 to b0 8 (2) 4n + 1 xxxxx xxxxx xxxxx b15 to b8 4n + 0 16/32 4n + 0 xxxxx xxxxx b15 to b8 b7 to b0 (1) 4n + 1 xxxxx xxxxx xxxxx b7 to b0 8 (2) 4n + 2 xxxxx xxxxx xxxxx b15 to b8 (1) 4n + 1 xxxxx xxxxx b7 to b0 xxxxx 16 (2) 4n + 2 xxxxx xxxxx xxxxx b15 to b8 4n + 1 32 4n + 1 xxxxx b15 to b8 b7 to b0 xxxxx (1) 4n + 2 xxxxx xxxxx xxxxx b7 to b0 8 (2) 4n + 1 xxxxx xxxxx xxxxx b15 to b8 16 4n + 2 xxxxx xxxxx b15 to b8 b7 to b0 4n + 2 32 4n + 2 b15 to b8 b7 to b0 xxxxx xxxxx (1) 4n + 3 xxxxx xxxxx xxxxx b7 to b0 8 (2) 4n + 4 xxxxx xxxxx xxxxx b15 to b8 (1) 4n + 3 xxxxx xxxxx b7 to b0 xxxxx 16 (2) 4n + 4 xxxxx xxxxx xxxxx b15 to b8 (1) 4n + 3 b7 to b0 xxxxx xxxxx xxxxx 4n + 3 (2) 4n + 4 xxxxx xxxxx xxxxx b15 to b8 (1) 4n + 0 xxxxx xxxxx xxxxx b7 to b0 (2) 4n + 1 xxxxx xxxxx xxxxx b15 to b8 (3) 4n + 2 xxxxx xxxxx xxxxx b23 to b16 (4) 4n + 3 xxxxx xxxxx xxxxx b31 to b24 (1) 4n + 0 xxxxx xxxxx b15 to b8 b7 to b0 16 (2) 4n + 2 xxxxx xxxxx b31 to b24 b23 to b16 4n + 0 32 4n + 0 b31 to b24 b23 to b16 b15 to b8 b7 to b0 (1) 4n + 0 xxxxx xxxxx xxxxx b7 to b0 (2) 4n + 1 xxxxx xxxxx xxxxx b15 to b8 (3) 4n + 2 xxxxx xxxxx xxxxx b23 to b16 (4) 4n + 3 xxxxx xxxxx xxxxx b31 to b24 (1) 4n + 1 xxxxx xxxxx b7 to b0 xxxxx (2) 4n + 2 xxxxx xxxxx b23 to b16 b15 to b8 (3) 4n + 4 xxxxx xxxxx xxxxx b31 to b24 (1) 4n + 1 b23 to b16 b15 to b8 b7 to b0 xxxxx 4n + 1 (2) 4n + 4 xxxxx xxxxx xxxxx b31 to b24 (1) 4n + 2 xxxxx xxxxx xxxxx b7 to b0 (2) 4n + 3 xxxxx xxxxx xxxxx b15 to b8 (3) 4n + 4 xxxxx xxxxx xxxxx b23 to b16 (4) 4n + 5 xxxxx xxxxx xxxxx b31 to b24 (1) 4n + 2 xxxxx xxxxx b15 to b8 b7 to b0 16 (2) 4n + 4 xxxxx xxxxx b31 to b24 b23 to b16 (1) 4n + 2 b15 to b8 b7 to b0 xxxxx xxxxx 4n + 2 (2) 4n + 4 xxxxx xxxxx b31 to b24 b23 to b16 (1) 4n + 3 xxxxx xxxxx xxxxx b7 to b0 (2) 4n + 4 xxxxx xxxxx xxxxx b15 to b8 (3) 4n + 5 xxxxx xxxxx xxxxx b23 to b16 (4) 4n + 6 xxxxx xxxxx xxxxx b31 to b24 (1) 4n + 3 xxxxx xxxxx b7 to b0 xxxxx (2) 4n + 4 xxxxx xxxxx b23 to b16 b15 to b8 (3) 4n + 6 xxxxx xxxxx xxxxx b31 to b24 (1) 4n + 3 b7 to b0 xxxxx xxxxx xxxxx 4n + 3 (2) 4n + 4 xxxxx b31 to b24 b23 to b16 b15 to b8 xxxxx: During a read, data input to t he bus is ignored. At write, the bus is at high impedance and the write strobe signal remains to non active.

(4) Wait control The external bus cycle completes a wait of two states at least (100 ns at 20 MHz). Setting the BnWW2 to BnWW0 and BnWR2 to BnWR0 of the control register (BnCSL) specifies the number of waits in the read cycle and the write cycle. BnWW is set with the same method as BnWR. BnWW/BnWR Bit (BnCSL register) BnWW2 BnWR2 BnWW1 BnWR1 BnWW0 BnWR0 Function 0 0 1 2states (0 waits) access fixed mode 0 1 0 3states (1 wait) access fixed mode (Default) 1 0 1 4states (2 waits) access fixed mode 1 1 0 5states (3 waits) access fixed mode 1 1 1 6states (4 waits) access fixed mode 0 1 1 WAIT pin input mode Others (Reserved) Note: When SDRAM is specified as a connecting memory, setting should be 4 states (2 waits) in RD cycle and 3 states (1 wait) in WR cycle. (i) Waits number fixed mode The bus cycle is completed with the set states. The number of states is selected from 2 states (0 waits) to 5 states (3 waits). (ii) WAIT pin input mode This mode samples the WAIT input pins. It continuously samples the WAIT pin state and inserts a wait if the pin is active. The bus cycle is minimum 2 states. The bus cycle is completed when the wait signal is non active (“High” level) at 2 states. The bus cycle extends if the wait signal is active at 2 states and more. (5) Insert recovery cycle If a lot of connected pertain ROM and etc. (Much data output floating time (tDF)), each other’s data-bus-output-recovery-time is trouble. However, by setting BnREC of control register (BnCSH), can insert dummy cycle of 1 state just before first bus cycle of starting access another block address. BnREC Bit (BnCSH register) 0 No dummy cycle is inserted (Default). 1 Dummy cycle is inserted. Note: When use MMU, built-in RAM type LCDD, this function cannot use.

• When not inserting a dummy cycle (0 waits)
• When inserting a dummy cycle (0 waits) (6) Basic bus timing
• External read/write bus cycle (0 waits)
• External read/write bus cycle (1 wait) SDCLK Address CSm CSn RD SDCLK Address CSm CSn RD Dummy CS WRxx RD Address Input Output Read Write SDCLK (20 MHz) D31 to D0 D31 to D0 T1 T2 CS RD Address Output SDCLK (20 MHz) D31 to D0 D31 to D0 T1 TW Input Read Write WRxx

• External read/write bus cycle (0 waits at WAIT pin input mode)
• External read/write bus cycle (n waits at WAIT pin input mode) CS RD Address Input Output Read Write SDCLK (20 MHz) D31 to D0 D31 to D0 T1 T2 WAIT Sampling WRxx CS RD Address Output SDCLK (20 MHz) D31 to D0 D31 to D0 T1 TW Input Read W WAIT SamplingSampling WRxx

• Example of WAIT input cycle (5 waits) CSn WR RD WAITD Q CK RES D Q CK RES D Q CK RES D Q CK RES D Q CK RES SDCLK FF0 FF1 FF2 FF3 FF4 SDCLK (20 MHz) 12 3 4 5 6 7 CSn RD WAIT FF_RES FF0_D FF0_Q FF1_Q FF2_Q FF3_Q

3.6.4 ROM Control (Page mode)

This section describes ROM page mode accessing and how to set registers. ROM page mode is set by the page ROM control register. (1) Operation and how to set the registers TMP92C820 supports ROM access of the page mode. The ROM access of the page mode is specified only in the block address area 2. ROM page mode is set by the page ROM control register (PMEMCR). Setting OPGE bit of the PMEMCR register to “1” sets the memory access of the block address area to ROM page mode access. The number of read cycles is set by the OPWR1 and OPWR0 bits of the PMEMCR register. OPWR1/OPWR0 Bit (PMEMCR register) OPWR1 OPWR0 Number of Cycle in a Page 0 0 1 state (n-1-1-1 mode) (n ≥ 2) 0 1 2 state (n-2-2-2 mode) (n ≥ 3) 1 0 3 state (n-3-3-3 mode) (n ≥ 4) 1 1 (Reserved) Note: Set the number of waits “n” to the control register (BnCSL) in each block address area. The page size (the number of bytes) of ROM in the CPU size is set to the PR1 and 0 bit of the PMCME register. When data is read out until a border of the set page, the controller completes the page reading operation. The start data of the next page is read in the normal cycle. The following data is set to page read again. PR1/PR0 Bit (PMEMCR register) PR1 PR0 ROM Page Size 0 0 64 bytes 0 1 32 bytes 1 0 16 bytes (Default) 1 1 8 bytes (2) Signal timing pulse tHA Data input Data input Data input Data input tCYC A0~A23 SDCLK D0~D31 RD CS2 +0 +1 +2 +3 tAD3 tAD2 tAD2 tAD2 tHRtHA tHAtHAtRD3

3.6.5 List of Registers

The memory control registers and the settings are described as follows. For the addresses of the registers, see Section 5 “Table of Special Function Registers (SFRs)”. (1) Control registers The control register is a pair of BnCSL and BnCSH. (n is a number of the block address area.) BnCSL has the same configuration regardless of the block address areas. In BnCSH, only B2CSH which is corresponded to the block address area 2 has a different configuration from the others. BnCSL 7 6 5 4 3 2 1 0 Bit symbol BnWW2 BnWW1 BnWW0 BnWR2 BnWR1 BnWR0 Read/Write W W After reset 0 1 0 0 1 0 BnWW<2:0> Specifies the number of write waits. 001 = 2 states (0 waits) access 010 = 3 states (1 wait) access 101 = 4 states (2 waits) access 110 = 5 states (3 waits) access 111 = 6 states (4 waits) access 011 = WAIT pin input mode Others = (Reserved) BnWR<2:0> Specifies the number of read waits. 001 = 2 states (0 waits) access 010 = 3 states (1 wait) access 101 = 4 states (2 waits) access 110 = 5 states (3 waits) access 111 = 6 states (4 waits) access 011 = WAIT pin input mode Others = (Reserved) B2CSH 7 6 5 4 3 2 1 0 Bit symbol B2E B2M B2REC B2OM1 B2OM0 B2BUS1 B2BUS0 Read/Write W W After reset 1 0 0 0 0 0/1 0/1 B2E: Enable bit 0 = No chip select signal output. 1 = Chip select signal output (Default). Note: After reset release, only the enable bit B2E of B2CS register is valid (“1”). B2M: Block address area specification 0 = Sets the block address area of CS2 to addresses 000000H to FFFFFFH (Default). 1 = Sets the block address area of CS2 to programmable. Note: After reset release, the block address area 2 is set to addresses 000000H to FFFFFFH.

B2REC: Sets the dummy cycle for data output recovery time. 0 = Not insert a dummy cycle (Default). 1 = Insert a dummy cycle. Note: When using MMU, LCD of built-in RAM type, this function cannot use. B2OM<1:0> 00 = SRAM or ROM (Default) Others = (Reserved) B2BUS<1:0> Sets the data bus width. 00 = 8 bits (Default) 01 = 16 bits 10 = 32 bits 11 = (Reserved) Note: The value of B2BUS bit is set according to the state of AM<1:0> pin after reset release. BnCSH (n = 0, 1, 3) 7 6 5 4 3 2 1 0 Bit symbol BnE BnREC BnOM1 BnOM0 BnBUS1 BnBUS0 Read/Write W W After reset 0 0 0 0 0 0 BnE: Enable bit 0 = No chip select signal output (Default). 1 = Chip select signal output. Note: After reset release, only the enable bit B2E of B2CS register is valid (“1”). BnREC: Sets the dummy cycle for data output. 0 = Not insert a dummy cycle (Default). 1 = Insert a dummy cycle. Note: When using MMU, LCD of built-in RAM type, this function cannot use. BnOM<1:0> 00 = SRAM or ROM (Default) 01 = (Reserved) 10 = (Reserved) 11 = SDRAM Note: SDRAM is set only by B1CSH. BnBUS<1:0> Sets the data bus width. 00 = 8 bits (Default) 01 = 16 bits 10 = 32 bits 11 = (Reserved)

Bit symbol BEXWW2 BEXWW1 BEXWW0 BEXWR2 BEXWR1 BEXWR0 Read/Write W W After reset 0 1 0 0 1 0 BEXWW<2:0> specifies the number of write waits. 001 = 2 states (0 waits) access 010 = 3 states (1 wait) access 101 = 4 states (2 waits) access 110 = 5 states (3 waits) access 111 = 6 states (4 waits) access 011 = WAIT pin input mode Others = (Reserved) BEXWR<2:0> Specifies the number of read waits. 001 = 2 states (0 waits) access 010 = 3 states (1 wait) access 101 = 4 states (2 waits) access 110 = 5 states (3 waits) access 111 = 6 states (4 waits) access 011 = WAIT pin input mode Others = (Reserved) BEXCSH 7 6 5 4 3 2 1 0 Bit symbol BEXOM1 BEXOM0 BEXBUS1 BEXBUS0 Read/Write W After reset 0 0 0 0 BEXOM<1:0> 00 = SRAM or ROM (Default) 01 = (Reserved) 10 = (Reserved) 11 = (Reserved) BEXBUS<1:0> Sets the data bus width. 00 = 8 bits (Default) 01 = 16 bits 10 = 32 bits 11 = (Reserved)

(2) Block address register A start address and an address area of the block address are specified by the memory start address register (MSARn) and the memory address mask register (MAMRn). The memory start address register sets all start address similarly regardless of the block address areas. The bit to be set by the memory address mask register is depended on the block address area. MSARn (n = 0 to 3) 7 6 5 4 3 2 1 0 Bit symbol MnS23 MnS22 MnS21 MnS20 MnS19 MnS18 MnS17 MnS16 Read/Write R/W After reset 1 1 1 1 1 1 1 1 MnS<23:16> Sets a start address. Sets the start address of the block address areas. The bits are corresponding to the address A23 to A16. MAMR0 7 6 5 4 3 2 1 0 Bit symbol M0V20 M0V19 M0V18 M0V17 M0V16 M0V15 M0V14 to M0V9 M0V8 Read/Write R/W After reset 1 1 1 1 1 1 1 1 M0V<20:8> Enables or masks comparison of the addresses. M0V20 to M0V8 are corresponding to addresses A20 to A8. The bits of M0V14 to M0V9 are corresponding to address A14 to A9 by 1 bit. If “0” is set, the comparison between the value of the address bus and the start address is enabled. If “1” is set, the comparison is masked. MAMR1 7 6 5 4 3 2 1 0 Bit symbol M1V21 M1V20 M1V19 M1V18 M1V17 M1V16 M1V15 to M1V9 M1V8 Read/Write R/W After reset 1 1 1 1 1 1 1 1 M1V<21:8> Enables or masks comparison of the addresses. M1V21 to M1V8 are corresponding to addresses A21 to A8. The bits of M1V15 to M1V9 are corresponding to address A15 to A9 by 1 bit. If “0” is set, the comparison between the value of the address bus and the start address is enabled. If “1” is set, the comparison is masked. MAMRn (n = 2 to 3) 7 6 5 4 3 2 1 0 Bit symbol MnV22 MnV21 MnV20 MnV19 MnV18 MnV17 MnV16 MnV15 Read/Write R/W After reset 1 1 1 1 1 1 1 1 MnV<22:15> Enables or masks comparison of the addresses. MnV22 to MnV15 are corresponding to addresses A22 to A15. If “0” is set, the comparison between the value of the address bus and the start address is enabled. If “1” is set, the comparison is masked. After a reset, MASR0 to MASR3 and MAMR0 to MAMR3 are set to “FFH”. B0CSH<B0E>, B1CSH<B1E>, and B3CSH<B3E> are reset to “0”. This disabling the CS0, CS1, and CS3 areas. However, B2CSH<B2M> is reset to “0” and B2CSH<B2E> to “1”, and CS2 is enabled 000000H to FFFFFFH. Also the bus width and number of waits specified in BEXCSH/L are used for accessing address except the specified CS0 to CS3 area.

(3) Page ROM control register (PMEMCR) The page ROM control register sets page ROM accessing. ROM page accessing is executed only in block address area 2. PMEMCR 7 6 5 4 3 2 1 0 Bit symbol OPGE OPWR1 OPWR0 PR1 PR0 Read/Write R/W After reset 0 0 0 1 0 OPGE enable bit 0 = No ROM page mode accessing (Default) 1 = ROM page mode accessing OPWR<1:0> Specifies the number of waits. 00 = 1 state (n-1-1-1 mode) (n ≥ 2) (Default) 01 = 2 states (n-2-2-2 mode) (n ≥ 3) 10 = 3 states (n-3-3-3 mode) (n ≥ 4) 11 = (Reserved) Note: Set the number of waits “n” to the control register (BnCSL) in each block address area. PR<1:0> ROM page size 00 = 64 bytes 01 = 32 bytes 10 = 16 bytes (Default) 11 = 8 bytes

Table 3.6.1 Control Register 7 6 5 4 3 2 1 0 Bit symbol B0WW2 B0WW1 B0WW0 B0WR2 B0WR1 B0WR0 Read/Write W W After reset 0 1 0 0 1 0 Bit symbol B0E − − B0REC B0OM1 B0OM0 B0BUS1 B0BUS0 Read/Write W After reset 0 0 (Note) 0 (Note) 0 0 0 0/1 0/1 Bit symbol M0V20 M0V19 M0V18 M0V17 M0V16 M0V15 M0V14-V9 M0V8 Read/Write R/W After reset 1 1 1 1 1 1 1 1 Bit symbol M0S23 M0S22 M0S21 M0S20 M0S19 M0S18 M0S17 M0S16 Read/Write R/W After reset 1 1 1 1 1 1 1 1 Bit symbol B1WW2 B1WW1 B1WW0 B1WR2 B1WR1 B1WR0 Read/Write W W After reset 0 1 0 0 1 0 Bit symbol B1E − − B1REC B1OM1 B1OM0 B1BUS1 B1BUS0 Read/Write W After reset 0 0 (Note) 0 (Note) 0 0 0 0/1 0/1 Bit symbol M1V21 M1V20 M1V19 M1V18 M1V17 M1V16 M1V15-V9 M1V8 Read/Write R/W After reset 1 1 1 1 1 1 1 1 Bit symbol M1S23 M1S22 M1S21 M1S20 M1S19 M1S18 M1S17 M1S16 Read/Write R/W After reset 1 1 1 1 1 1 1 1 Bit symbol B2WW2 B2WW1 B2WW0 B2WR2 B2WR1 B2WR0 Read/Write W W After reset 0 1 0 0 1 0 Bit symbol B2E B2M − B2REC B2OM1 B2OM0 B2BUS1 B2BUS0 Read/Write W After reset 1 0 0 (Note) 0 0 0 0/1 0/1 Bit symbol M2V22 M2V21 M2V20 M2V19 M2V18 M2V17 M2V16 M2V15 Read/Write R/W After reset 1 1 1 1 1 1 1 1 Bit symbol M2S23 M2S22 M2S21 M2S20 M2S19 M2S18 M2S17 M2S16 Read/Write R/W After reset 1 1 1 1 1 1 1 1 Bit symbol B3WW2 B3WW1 B3WW0 B3WR2 B3WR1 B3WR0 Read/Write W W After reset 0 1 0 0 1 0 Bit symbol B3E − − B3REC B3OM1 B3OM0 B3BUS1 B3BUS0 Read/Write W After reset 0 0 (Note) 0 (Note) 0 0 0 0/1 0/1 Bit symbol M3V22 M3V21 M3V20 M3V19 M3V18 M3V17 M3V16 M3V15 Read/Write R/W After reset 1 1 1 1 1 1 1 1 Bit symbol M3S23 M3S22 M3S21 M3S20 M3S19 M3S18 M3S17 M3S16 Read/Write R/W After reset 1 1 1 1 1 1 1 1 Bit symbol BEXOM1 BEXOM0 BEXBUS1 BEXBUS0 Read/Write W After reset 0 0 0 0 Bit symbol BEXWW2 BEXWW1 BEXWW0 BEXWR2 BEXWR1 BEXWR0 Read/Write W W After reset 0 1 0 0 1 0 Bit symbol OPGE OPWR1 OPWR0 PR1 PR0 Read/Write R/W After reset 0 0 0 1 0 Note: Always write “0”. B0CSL (0140H) B0CSH (0141H) MAMR0 (0142H) MSAR0 (0143H) B1CSL (0144H) B1CSH (0145H) MAMR1 (0146H) MSAR1 (0147H) B2CSL (0148H) B2CSH (0149H) MAMR2 (014AH) MSAR2 (014BH) B3CSL (014CH) B3CSH (014DH) MAMR3 (014EH) MSAR3 (014FH) BEXCSH (0159H) BEXCSL (0158H) PMEMCR (0166H)

3.6.6 Cautions

(1) Note on timing between CS and RD If the parasitic capacitance of the read signal (Output enable signal) is greater than that of the chip select signal, it is possible that an unintended read cycle occurs due to a delay in the read signal. Such an unintended read cycle may cause a trouble as in the case of (a) in 0H Figure 3.6.1 Figure 3.6.1 Read Signal Delay Read Cycle Example: When using an externally connected flash EEPROM which users JEDEC standard commands, note that the toggle bit may not be read out correctly. If the read signal in the cycle immediately preceding the access to the flash EEPROM does not go high in time, as shown in 1H Figure 3.6.2 an unintended read cycle like the one shown in (b) may occur. Figure 3.6.2 Flash EEPROM Toggle Bit Read Cycle When the toggle bit reverse with this unexpected read cycle, TMP92C820 always reads same value of the toggle bit, and cannot read the toggle bit correctly. To avoid this phenomena, the data polling control recommended. RD Address SDCLK (20 MHz) MEMORY 1CS MEMORY 2CS (a) Address SDCLK (20 MHz) Flash EEPROM Chip select Read (b) Toggle bit Memory access Toggle bit RD cycle 1

(2) The cautions at the time of the functional change of a CSn . A chip select signal output has the case of a combination terminal with a general-purpose port function. In this case, an output latch register and a function control register are initialized by the reset action, and an object terminal is initialized by the port output (“1” or “0”) by it. Functional change Although an object terminal is changed from a port to a chip select signal output by setting up a function control register (PnF C register), the short pulse for several ns may be outputted to the changing timing. Although it does not become especially a problem when using the usual memory, it may become a problem when using a special memory. XX n+2 Internal address bus Function control signal Pxx n n+2 A23 to A0 A port is set as CSn . n Output port CSn Internal Signal External Signal Output pulse tAD3 * XX is a function register address.(When an output port is initialized by “0”) The measure by software The countermeasures in S/W for avoiding this phenomenon are explained. Since CS signal decodes the address of the access area and is generated, an unnecessary pulse is outputted by access to the object CS area immediately after setting it as a CSn function. Then, if intern al area is accessed also immediately after setting a port as CS function, an unnecessary pulse will not output. 1. The ban on interruption under functional change (DI command) 2. A dummy command is added in order to carry out continuous internal access. 3. (Access to a functional change register is corresponded by 16-bit command. (LDW command)) XX+1 n+2 Internal address bus Function control signal Pxx n n+2 A23 to A0 A port is set asCSn . XX Output port CSn Internal signal External signal Dummy access

3.7 8-Bit Timers (TMRA) The TMP92C820 features 4 built-in 8-bit timers. These timers are paired into four modules: TMRA01 and TMRA23. Each module consists of two channels and can operate in any of the following four operating modes.

• 8-bit interval timer mode
• 16-bit interval timer mode
• 8-bit programmable square wave pulse generation output mode (PPG: Variable duty cycle with variable period)
• 8-bit pulse width modulation output mode (PWM: Variable duty cycle with constant period) Each channel consists of an 8-bit up counter, an 8-bit comparator and an 8-bit timer register. In addition, a timer flip-flop and a prescaler are provided for each pair of channels. The operation mode and timer flip-flops are controlled by five controls SFR (Special function register). Each of the two modules (TMRA01 and TMRA23) can be operated independently. All modules operate in the same manner; hence only the operation of TMRA01 is explained here. The contents of this chapter are as follows.

3.7.1 Block Diagrams

3.7.2 Operation of Each Circuit

3.7.3 SFRs

3.7.4 Operation in Each Mode

(1) 8-bit timer mode (2) 16-bit timer mode (3) 8-bit PPG (Programmable pulse generation) output mode (4) 8-bit PWM output mode (5) Mode setting Table 3.7.1 Registers and Pins for Each Module Module TMRA01 TMRA23 Input pin for external clock TA0IN (shared with PC0) No External pin Output pin for timer flip-flop TA1OUT (shared with PC1) TA3OUT (Shared with PC5) Timer run register TA01RUN (1100H) TA23RUN (1108H) Timer register TA0REG (1102H) TA1REG (1103H) TA2REG (110AH) TA3REG (110BH) Timer mode register TA01MOD (1104H) TA23MOD (110CH) SFR (Address) Timer flip-flop control register TA1FFCR (1105H) TA3FFCR (110DH)

Figure 3.7.1 TMRA01 Block Diagram φT1 φT16 φT256 8-bit comparator (CP1) 8-bit comparator (CP0) 8-bit up counter (UC0) n overflow 8-bit up counter (UC1) Timer flip-flop TA1FF Match detect Match detect 8-bit timer register TA1REG φT1 φT4 φT16 512 256 128 64 32 16 8 4 2 φT1 φT4 φT16 φT256 Run/clear Prescaler External input clock: TA0IN TA01MOD <TA0CLK1:0> Prescaler clock: φT0 TA01RUN<TA0RUN> Selector 8-bit timer register TA0REG TA01MOD <PWM01:00> TA01MOD <TA01M1:0> TMRA0 interrupt output: INTTA0 TMRA0 match output: TA0TRG TA01MOD <TA1CLK1:0> TA01RUN<TA1RUN> TA1FFCR Timer flip-flop output: TA1OUT TMRA1 interrupt output: INTTA1 Internal data bus TA01RUN <TA0RDE> TA01RUN <TA01PRUN> Selector Internal data bus TA0TRG Register buffer 0

Figure 3.7.2 TMRA23 Block Diagram φT1 φT16 φT256 8-bit comparator register (CP3) 8-bit comparator (CP2) 8-bit up counter (UC2) n overflow 8-bit up counter (UC3) Timer flip-flop TA3FF Match detect Match detect 8-bit timer register TA3REG φT1 φT4 φT16 512 256 128 64 32 16 8 4 2 φT1 φT4 φT16 φT256 Run/clear Prescaler TA23MOD <TA2CLK1:0> Prescale r clock: φT0 TA23RUN<TA2RUN> Selector 8-bit timer register TA2REG TA23MOD <PWM21:20> TA23MOD <TA23M1:0> TMRA2 interrupt output: INTTA2 TMRA2 match output: TA2TRG TA23MOD <TA3CLK1:0> TA23RUN<TA3RUN> TA3FFCR Timer flip-flop output: TA3OUT (Supply to LCDC) TMRA3 interrupt output: INTTA3 Internal data bus TA23RUN <TA2RDE> TA23RUN <TA23PRUN> Selecto r Internal data bus TA2TRG Register buffer 2

(1) Prescalers A 9-bit prescaler generates the input clock to TMRA01. The clock φT0 is divided into 8 by the CPU clock fSYS and input to this prescaler. The prescaler operation can be controlled using TA01RUN<TA01PRUN> in the timer control register. Setting <TA01PRUN> to “1” starts the count; setting <TA01PRUN> to “0” clears the prescaler to 0 and stops operation. 2H Table 3.7.2 shows the various prescaler output clock resolutions. Table 3.7.2 Prescaler Output Clock Resolution Timer counter input clock TMRA prescaler TAxMOD<TAxCLK1:0> Clock gear selection SYSCR1 <GEAR2:0> System clock selection SYSCR1 <SYSCK> − 1 (fs) fs/16 fs/64 fs/256 fs/4096 000 (1/1) fc/16 fc/64 fc/256 fc/4096 001 (1/2) fc/32 fc/128 fc/512 fc/8192 010 (1/4) fc/64 fc/256 fc/1024 fc/16384 011 (1/8) fc/128 fc/512 fc/2048 fc/32768 100 (1/16) 0 (fc) fc/256 fc/1024 fc/4096 fc/65536 (2) Up counters (UC0 and UC1) These are 8-bit binary counters which count up the input clock pulses for the clock specified by TA01MOD. The input clock for UC0 is selectable and can be either the external clock input via the TA0IN pin or one of the three internal clocks φT1, φT4 or φT16. The clock setting is specified by the value set in TA01MOD<TA01CLK1:0>. The input clock for UC1 depends on the operation mode. In 16-bit timer mode, the overflow output from UC0 is used as the input clock. In any mode other than 16-bit timer mode, the input clock is selectable and can either be one of the internal clocks φT1, φT16, or φT256, or the comparator output (The match detection signal) from TMRA0. For each interval timer the timer operation control register bits TA01RUN<TA0RUN> and TA01RUN<TA1RUN> can be used to stop and clear the up counters and to control their count. A reset clears both up counters, stopping the timers.

(3) Timer registers (TA0REG and TA1REG) These are 8-bit registers, which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up counter, the comparator match detect signal goes active. If the value set in the timer register is 00H, the signal goes active when the up counter overflows. The TA0REG are double buffer structure, each of which makes a pair with register buffer. The setting of the bit TA01RUN<TA0RDE> determines whether TA0REG’s double buffer structure is enabled or disabled. It is disabled if <TA0RDE> = “0” and enabled if <TA0RDE> = “1”. When the double buffer is enabled, data is transferred from the register buffer to the timer register when a 2 n overflow occurs in PWM mode, or at the start of the PPG cycle in PPG mode. Hence the double buffer cannot be used in timer mode. A reset initializes <TA0RDE> to “0”, disabling the double buffer. To use the double buffer, write data to the timer register, set <TA0RDE> to “1”, and write the following data to the register buffer 3H Figure 3.7.3 show the configuration of TA0REG. Figure 3.7.3 Configuration of TA0REG Note: The same memory address is allocated to the timer register and the register buffer. When <TA0RDE> = 0, the same value is written to the register buffer and the timer register; when <TA0RDE> = 1, only the register buffer is written to. The address of each timer register is as follows. TA0REG: 001102H TA1REG: 001103H TA2REG: 00110AH TA3REG: 00110BH All these registers are wr ite-only and cannot be read. Internal data bus TA01RUN<TA0RDE> Timer registers 0 (TA0REG) Register buffers 0 Shift trigger B Selector SA Write Write to TA0REG Matching detection in PPG cycle n overflow of PWM

(4) Comparator (CP0) The comparator compares the value in an up counter with the value set in a timer register. If they match, the up counter is cleared to zero and an interrupt signal (INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time. (5) Timer flip-flop (TA1FF) The timer flip-flop (TA1FF) is a flip-flop inverted by the match detects signal (8-bit comparator output) of each interval timer. Whether inversion is enabled or disabled is determined by the setting of the bit TA1FFCR<TA1FFIE> in the timer flip-flops control register. A reset clears the value of TA1FF to “0”. Writing “01” or “10” to TA1FFCR<TA1FFC1:0> sets TA1FF to 0 or 1. Writing “00” to these bits inverts the value of TA1FF (this is known as software inversion). The TA1FF signal is output via the TA1OUT pin (which can also be used as PC1). When this pin is used as the timer output, the timer flip-flop should be set beforehand using the port C function register PCFC. Note: When the double buffer is enabled for an 8-bit timer in PWM or PPG mode, caution is required as explained below. If new data is written to the register buffer immediately before an overflow occurs by a match between the timer register value and t he up-counter value, the timer flip-flop may output an unexpected value. For this reason, make sure that in PWM mode new data is written to the register buffer by six cycles (f SYS × 6) before the next overflow occurs by using an overflow interrupt. When using PPG mode, make sure that new data is written to the register buffer by six cycles before the next cycle compare matc h occurs by using a cycle compare match interrupt. Example when using PWM mode TA1OUT n overflow interrupt (INTTA0) tPWM (PWM cycle) Match between TA0REG and up-counter Desired PWM cycle change point Write new data to the register buffer before the next overflow occurs by using an overflow interrupt

Bit symbol TA0RDE I2TA01 TA01PRUN TA1RUN TA0RUN Read/Write R/W R/W R/W After reset 0 0 0 0 0 TMRA01 prescaler UP counter (UC1) UP counter (UC0) Function Double buffer 0: Disable 1: Enable IDLE2 0: Stop 1: Operate 0: Stop and clear 1: Run (Count up) Timer run/stop control

0 Stop and clear

1 Run (Count up)

TA0REG double buffer control Note: The values of bits 4 to 6 of TA01RUN are undefined when read. TMRA23 Run Register 7 6 5 4 3 2 1 0 Bit symbol TA2RDE I2TA23 TA23PRUN TA3RUN TA2RUN Read/Write R/W R/W R/W After reset 0 0 0 0 0 TMRA23 prescaler UP counter (UC3) UP counter (UC4) Function Double buffer 0: Disable 1: Enable IDLE2 0: Stop 1: Operate 0: Stop and clear 1: Run (Count up) Timer run/stop control TA2REG double buffer control Note: The values of bits 4 to 6 of TA23RUN are undefined when read. Figure 3.7.4 TMRA Registers (1) TA01RUN (1100H) TA23RUN (1108H)

Bit symbol TA01M1 TA01M0 PWM01 PWM 00 TA1CLK1 TA1CLK0 TA0CLK1 TA0CLK0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode PWM cycle 00: Reserved 01: 2 10: 2 11: 2 Source clock for TMRA1 00: TA0TRG 01: φT1 10: φT16 11: φT256 Source clock for TMRA0 00: TA0IN pin (Note) 01: φT1 10: φT4 11: φT16 TMRA0 source clock selection

00 TA0IN (External input)

01 φT1 10 φT4 11 φT16 TMRA1 source clock selection TA01MOD <TA01M1:0> ≠ 01 TA01MOD <TA01M1:0> = 01

00 Comparator output from

01 φT1 10 φT16 11 φT256 Overflow output from TMRA0 (16-bit timer mode) PWM cycle selection

00 Reserved

× Source clock 10 2 × Source clock 11 2 × Source clock TMRA01 operation mode selection

00 Two 8-bit timers

11 8-bit PWM (TMRA0) + 8-bit timer (TMRA1) Note: When set TA0IN pin, must set TA01MOD after set port C. Figure 3.7.5 TMRA Registers (2) TA01MOD (1104H)

Bit symbol TA23M1 TA23M0 PWM21 PWM 20 TA3CLK1 TA3CLK0 TA2CLK1 TA2CLK0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode PWM cycle 00: Reserved 01: 2 10: 2 11: 2 TMRA3 clock for TMRA3 00: TA2TRG 01: φT1 10: φT16 11: φT256 TMRA2 clock for TMRA2 00: Reserved 01: φT1 10: φT4 11: φT16 TMRA2 source clock selection

00 Do not set

01 φT1 10 φT4 11 φT16 TMRA3 source clock selection TA23MOD <TA23M1:0> ≠ 01 TA23MOD <TA23M1:0> = 01 01 φT1 10 φT16 11 φT256 Overflow output from TMRA2 (16-bit timer mode) PWM cycle selection × Source clock 10 2 × Source clock 11 2 × Source clock TMRA23 operation mode selection 11 8-bit PWM (TMRA2) + 8-bit timer (TMRA3) Figure 3.7.6 TMRA Registers (3) TA23MOD (110CH)

TMRA1 Flip-Flop Control Register 7 6 5 4 3 2 1 0 Bit symbol TA1FFC1 TA1FFC0 TA1FFIE TA1FFIS Read/Write R/W R/W After reset 1 1 0 0 Function 00: Invert TA1FF 01: Set TA1FF 10: Clear TA1FF 11: Don’t care TA1FF control for inversion 0: Disable 1: Enable TA1FF1 inversion select 0: TMRA0 1: TMRA1 Inverse signal for timer flop-flop 1 (TA1FF) (Don’t care except in 8-bit timer mode)

0 Inversion by TMRA0

1 Inversion by TMRA1

0 Disabled

1 Enabled

00 Inverts the value of TA1FF

01 Sets TA1FF to “1”

10 Clears TA1FF to “0”

11 Don’t care

Note: The values of bits 4 to 7 of TA1FFCR are undefined when read. Figure 3.7.7 TMRA Registers (4) TA1FFCR (1105H) Read-modify -write instructions are prohibited.

TMRA3 Flip-Flop Control Register 7 6 5 4 3 2 1 0 Bit symbol TA3FFC1 TA3FFC0 TA3FFIE TA3FFIS Read/Write R/W R/W After reset 1 1 0 0 Function 00: Invert TA3FF 01: Set TA3FF 10: Clear TA3FF 11: Don’t care TA3FF control for inversion 0: Disable 1: Enable TA3FF inversion select 0: TMRA2 1: TMRA3 Inverse signal for timer flip-flop 3 (TA3FF) (Don’t care except in 8-bit timer mode)

0 Inversion by TMRA2

1 Inversion by TMRA3

00 Inverts the value of TA3FF

01 Sets TA3FF to “1”

10 Clears TA3FF to “0”

Note: The values of bits 4 to 7 of TA3FFCR are undefined when read. Figure 3.7.8 TMRA Register TA3FFCR (110DH) Read-modify -write instructions are prohibited.

TMRA Register (TA0REG to TA3REG) Symbol Address 7 6 5 4 3 2 1 0 W TA0REG 1102H Undefined W TA1REG 1103H Undefined W TA2REG 110AH Undefined W TA3REG 110BH Undefined Note: Read-modify-write instruction is prohibited for above registers. Figure 3.7.9 Register for 8-Bit Timers

(1) 8-bit timer mode Both timer 0 and timer 1 can be used independently as 8-bit interval timers. 1. Generating interrupts at a fixed interval (using TMRA1) To generate interrupts at constant intervals using timer 1 (INTTA1), first stop TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and TA1REG register, respectively. Then, enable the interrupt INTTA1 and start TMRA1 counting. Example: To generate an INTTA1 interrupt every 40 μs at fC = 40 MHz, set each register as follows: MSB LSB 7 6 5 4 3 210 TA01RUN ← − X X X − − 0 − Stop TMRA1 and clear it to 0. TA01MOD ← 0 0 − − 0 1 − − Select 8-bit timer mode and select φT1 (=(16/fc)s at fC = 40 MHz) as the input clock. TA1REG ← 0 1 1 0 0 1 0 0 Set TA1REG to 40 μs ÷ φT1 = 100 = 64H INTETA01 ← X 1 0 1 − − − − Enable INTTA1 and set it to level 5. TA01RUN ← − X X X − 11 − Start TMRA1 counting. X: Don’t care, −: No change Select the input clock using 4H Table 3.7.3 Table 3.7.3 Selecting Interrupt Interval and the Input Clock Using 8-Bit Timer Input Clock Interrupt Interval (at f SYS = 20 MHz) Resolution φT1 (8/fSYS) φT4 (32/fSYS) φT16 (128/fSYS) φT256 (2048/fSYS) 0.4 μs to 102.4 μs 1.6 μs to 409.6 μs 6.4 μs to 1.638 ms 102.4 μs to 26.21 ms 0.4 μs 1.6 μs 6.4 μs 102.4 μs Note: The input clocks for TMRA0 and TMRA1 differ as follows: TMRA0: Uses TMRA0 input (TA0IN) and can be selected from φT1, φT4, or φT16 TMRA1: Match output of TMRA0 (TA0TRG) and can be selected from φT1, φT16, φT256

1. Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF1) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 2.4 μs square wave pulse from the TA1OUT pin at fC = 40 MHz, use the following procedure to make the appropriate register settings. This example uses timer 1; however, either timer 0 or timer 1 may be used. 7 6 5 4 3 210 TA01RUN ← − X X X − − 0 − Stop TMRA1 and clear it to 0. TA01MOD ← 0 0 − − 0 1 − − Select 8-bit timer mode and select φT1 (=(16/fc)s at fC = 40 MHz) as the input clock. TA1REG ← 0 0 0 0 0 0 1 1 Set the timer register to 2.4 μs ÷ φT1 ÷ 2 = 3 TA1FFCR ← X X X X 1 0 1 1 Clear TA1FF to 0 and set it to invert on the match detect signal from timer 1. PCFC ← X − − X − X1 − Set PC1 to function as the TA1OUT pin. TA01RUN ← − X X X − 11 − Start TMRA1 counting. X: Don’t care, −: No change Figure 3.7.10 Square Wave Output Timing Chart (50% duty) 1.2 μs at fC = 40 MHz 0 1 2 3 0 1 2 3 0 1 2 3 0 φT1 TA01RUN <TA1RUN> Bit7 to 2 Bit1 Bit0 INTTA1 TA1FF TA1OUT Up counter Comparator timing Comparator output (Match detect) UC1 Clear

1. Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Figure 3.7.11 TMRA1 Count Up on Signal from TMRA0 (2) 16-bit timer mode A 16-bit interval timer is configured by pairing the two 8-bit timers TMRA0 and TMRA1. To make a 16-bit interval timer in which TMRA0 and TMRA1 are cascaded together, set TA01MOD<TA01M1:0> to 01. In 16-bit timer mode, the overflow output from TMRA0 is used as the input clock for TMRA1, regardless of the value set in TA01MOD<TA1CLK1:0>. 5H Table 3.7.4 shows the relationship between the timer (Interrupt) cycle and the input clock selection. To set the timer interrupt interval, set the lower eight bits in timer register TA0REG and the upper eight bits in TA1REG. Be sure to set TA0REG first (as entering data in TA0REG temporarily disables the compare, while entering data in TA1REG starts the compare). Example: To generate an INTTA1 interrupt every 0.4 s at fC = 40 MHz, set the timer registers TA0REG and TA1REG as follows: If φT16 (=(256/fc)s at fSYS = 20 MHz) is used as the input clock for counting, set the following value in the registers: 0.4 s ÷=(256/fc)s = 62500 = F424H; e.g., set TA1REG to F4H and TA0REG to 24H. 2 3451 2345 12 3 1 1 2 1 Comparator output (Timer 0 match) Timer 0 up counter (when TA0REG = 5) Timer 1 up counter (when TA1REG = 2) Timer 1 match output

Example: To generate 1/4 duty 62.5 kHz pulses (at f C = 40 MHz): Calculate the value which should be set in the timer register. To obtain a frequency of 62.5 kHz, the pulse cycle t should be: t = 1/62.5 kHz = 16 μs φT1 (=(16/fc)) (at fC = 40 MHz); 16 μs ÷(16/fc)s = 40 Therefore set TA1REG to 40 (28H) The duty is to be set to 1/4: t × 1/4 = 16 μs × 1/4 = 4 μs 4 μs ÷ (16/fc)s = 10 Therefore, set TA0REG = 10 = 0AH. 7 6 5 4 3 210 TA01RUN ← 0 X X X − 0 0 0 Stop TMRA0 and TMRA1 and clear it to “0”. TA01MOD ← 1 0 − − − − 0 1 Set the 8-bit PPG mode, and select φT1 as input clock. TA0REG ← 0 0 0 0 1 0 1 0 Write 0AH TA1REG ← 0 0 1 0 1 0 0 0 Write 28H TA1FFCR ← X X X X 0 1 1 − Set TA1FF, enabling both inversion and the double buffer. 10 generates a negative logic pulse. PCFC ← X − − X − X1 − Set PC1 as the TA1OUT pin. TA01RUN ← 1 X X X − 1 1 1 Start TMRA0 and TMRA1 counting. X: Don’t care, −: No change 16 μs

In this mode the value of the register buffer will be shifted into TA0REG if 2n overflow is detected when the TA0REG double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Figure 3.7.18 Register Buffer Operation Example: To output the following PWM waves on the TA1OUT pin at f C = 40 MHz: To achieve a 51.2 μs PWM cycle by setting φT1 to 0.4 μs (at f C = 40 MHz): 51.2 μs ÷ (16/fc)s = 128 n = 128 Therefore n should be set to 7. Since the low-level period is 36.0 μs when φT1 = (16/fc) μs, set the following value for TREG0: 36.0 μs ÷(16/fc)s = 90 = 5AH MSB LSB 7 6 5 4 3 210 TA01RUN ← − X X X − − − 0 Stop TMRA0 and clear it to 0. TA01MOD ← 1 1 1 0 − − 0 1 Select 8-bit PWM mode (Cycle: 2 ) and select φT1 as the input clock. TA0REG ← 0 1 0 1 1 0 1 0 Write 5AH. TA1FFCR ← X X X X 1 0 1 − Clear TA1FF to 0, enable the inversion and double buffer. PCFC ← X − − X − X1 − Set PC1 and the TA1OUT pin. TA01RUN ← 1 X X X − 1 − 1 Start TMRA0 counting. X: Don’t care, −: No change Q2 Q1 Match with TA0REG Q3 Q2 Up counter = Q1 Up counter = Q2 Shift into TA0REG TA0REG (Register buffer) write TA0REG (Value to be compared) Register buffer n overflow 36.0 μs 51.2 μs

Table 3.7.4 PWM Cycle PWM cycle TAxxMOD<PWMx1:0> (x64) 2 (x128) 2 (x256) TAxxMOD<TAxCLK1:0> TAxxMOD<TA xCLK1:0> TAxxMOD<TAxCLK1:0> Clock gear SYSCR1 <GEAR2:0> System clock SYSCR0 <SYSCK> φT1(x2) φT4(x8) φT16(x32) φT1(x2) φT4(x8) φT16(x32) φT1(x2) φT4(x8) φT16(x32) − 1(fs) 1024/fs 4096/fs 16384/fs 2048/fs 8192/ fs 32768/fs 4096/fs 16384/fs 65536/fs 000(x1) 1024/fc 4096/fc 16384/fc 2048/fc 8192/ fc 32768/fc 4096/fc 16384/fc 65536/fc 001(x2) 2048/fc 8192/fc 32768/fc 4096/fc 16384 /fc 65536/fc 8192/fc 32768/fc 131072/fc 010(x4) 4096/fc 16384/fc 65536/fc 8192/fc 32768 /fc 131072/fc 16384/fc 65536/fc 262144/fc 011(x8) 8192/fc 32768/fc 131072/fc 16384/fc 65536/fc 262144/fc 32768/fc 131072/fc 524288/fc 100(x16) 0(fc) 16384/fc 65536/fc 262144/fc 32768/fc 131072/fc 524288/fc 65536/fc 262144/fc 1048576/fc (5) Mode setting 8H Table 3.7.5 shows the SFR settings for each mode. Table 3.7.5 Timer Mode Setting Registers Register Name TA01MOD TA1FFCR <Bit symbol> <TA01M1:0> <PWM01:00 > <TA1CLK1:0> <TA0CLK1:0> <TA1FFIS> Function Timer Mode PWM Cycle Upper Timer Input Clock Lower Timer Input Clock Timer F/F Invert Signal Select 8-bit timer × 2 channels 00 − Lower timer match, φT1, φT16, φT256 (00, 01, 10, 11) External clock, φT1, φT4, φT16 (00, 01, 10, 11) 0: Lower timer output 1: Upper timer output 16-bit timer mode 01 − − External clock, φT1, φT4, φT16 (00, 01, 10, 11) 8-bit PPG × 1 channel 10 − − External clock, φT1, φT4, φT16 (00, 01, 10, 11) 8-bit PWM × 1 channel 11 2 , 2 , 2 (01, 10, 11) − External clock, φT1, φT4, φT16 (00, 01, 10, 11) 8-bit timer × 1 channel 11 − φT1, φT16, φT256 (01, 10, 11) − Output disabled −: Don’t care

3.8 External Memory Extension Function (MMU)

This is MMU function which can expand program/data area to 136 Mbytes by having 4 local area. Address pins to external memory are 2 extended address bus pins (EA24, EA25) and 8 extended chip select pins (CS2A to CS2G and CSEXA ) in addition to 24 address bus pins (A0 to A23) which are common specification of TLCS-900/H1 and 4 chip select pins (CS0 to CS3 ) output from MEMC. The feature and the recommendation setting method of two types are shown below. In addition, AH in the table is the value which number address 23 to 16 displayed as hex. Purpose Item For Standard Extended Memory For Many Kinds Class Extended Memory Maximum memory size 2 Mbytes: COMMON2 + 14 Mbytes: BANK (16 Mbytes × 1 pcs) Used local area, BANK number LOCAL2 (AH = C0 to DF: 2 Mbytes × 7 BANK) Setting MEMC Setup AH = “80 to FF” to CS2 Program ROM Used CS pin CS2A Maximum memory size 96 Mbytes (16 Mbytes × 6 pcs) Used local area, BANK number LOCAL3 (AH = 80 to BF: 4 Mbytes × 24 BANK) Setting MEMC Setup AH = “80 to FF” to CS2 Data ROM Used CS pin CS2B , CS2C , CS2D , CS2E , CS2F , CS2G Maximum memory size 2 Mbytes: COMMON1 + 14 Mbytes: BANK (16 Mbytes × 1 pcs) Used local area, BANK number LOCAL1 (AH = 40 to 5F: 2 Mbytes × 7 BANK) Setting MEMC Setup AH = “40 to 7F” to CS1 Data SDRAM* Used CS pin CS1 Maximum memory size 1 Mbyte: COMMON0 + 7 Mbytes: BANK (8 Mbytes × 1 pcs) Used local area, BANK number LOCAL0 (AH = 10 to 1F: 1 Mbyte × 7 BANK) Setting MEMC Setup AH = “00 to 1F” to CS3 Data RAM Used CS pin CS3 Maximum memory size 1 Mbyte (1 Mbyte × 1 pcs) Used local area, BANK number None Setting MEMC Setup AH = “20 to 2F” to CS0 Extended memory 1 Used CS pin CS0 Maximum memory size 256 Kbytes (256 Kbytes × 1 pcs) Used local area, BANK number None Setting MEMC Setup AH = “30 to 3F” to CSEX Extended memory 2 Used CS pin CSEXA Maximum memory size 256 Kbytes (64 Kbytes × 4 pcs) Used local area, BANK number None Setting MEMC Setup AH = “30 to 3F” to CSEX Extended memory 3 (Direct address assigned built-in type LCD driver) Used CS pin D1BSCP, D2BLP, D3BFR, DLEBCD Maximum memory size 512 Kbytes Used local area, BANK number None Setting MEMC Setup AH = “30 to 3F” to CSEX Extended memory 4 Used CS pin None *Note: SDRAM must be mapped in LOCAL1 area. It can’t use other area.

3.8.1 Recommendable Memory Map

The recommendation logic address memory map at the time of variety extension memory correspondence is shown in 0H Figure 3.8.1. And, a physical-address map is shown in 1H Figure 3.8.2. However, when memory area is less than 16 Mbytes and is not expanded, please refer to section of MEMC. Setting of register in MMU is not necessary. Since it is being fixed, the address of a local-area cannot be changed. When SDRAM is used, must locate to LOCAL1 area. Figure 3.8.1 Logical Address Map 256 bytes

64 Kbytes

512 Kbytes

1 Mbyte

1 Mbyte COMMON0

256 Kbytes

2 Mbytes

4 Mbytes

Address Size Memory map BANK CS3 CS0 CSEX CSEX CSEX CSEX CSEX CSEX CS1 CS2 CS2 CS/WAIT CS pin CS3 CS0 to CSEXA D1BSCP D2BLP D3BFR DLEBCD CS1 CS2B (BANK0 to BANK3) CS2C (BANK4 to BANK7) CS2D (BANK8 to BANK11) CS2E (BANK12 to BANK15) CS2F (BANK16 to BANK19) CS2G (BANK20 to BANK23) CS2A : Internal area : Overlapped with COMMON area

Figure 3.8.2 Physical Address Map BANK3 BANK2 BANK0 BANK1 BANK0 BANK1 BANK2 BANK3 BANK4 BANK5 BANK6 BANK7 BANK0 BANK1 BANK2 BANK3 BANK4 BANK5 BANK6 BANK7 BANK0 BANK1 BANK2 BANK3 BANK4 BANK5 BANK6 BANK7 BANK15 BANK14 BANK12 BANK13 000000H Internal-I/O and RAM 800000H 1000000H LOCAL0 CS3 for data RAM (SDRAM non support) (8 Mbytes) LOCAL1 CS1 for option program ROM (SDRAM support) (16 Mbytes) LOCAL2 CS2A for program ROM (16 Mbytes) LOCAL3 CS2B CS2E for data ROM (16 Mbytes × 6) BANK7 BANK6 BANK4 BANK5 BANK19 BANK18 BANK16 BANK17 CS2F CS2C 1000000H 000000H Reset and Interrupt vector area BANK11 BANK10 BANK8 BANK9 BANK23 BANK22 BANK20 BANK21 CS2G CS2D 1000000H 000000H : Internal area : Overlapped with COMMON area TMP92C820

3.8.2 Block Diagram

Figure 3.8.3 Block Diagram of MMU L0E L1E L2E L3E Decoder EA22 to EA20 EA23 to EA21 EA23 to EA21 EA26 to EA22 Selector A23 to A20 CPU out address A23 to A8 LOCAL0 register LOCAL1 register LOCAL2 register LOCAL3 register Internal data bus Selector Physical address VA26 to VA20 A23 to A16 Physical address WA26 to WA7 (To external address bus pins) CPU out address A19 to A7 Decoder CS2A CS2B CS2C CS2D CS2E CS2F CS2G CSEXA CPU out address A23 to A16 LOCAL3 area detect signal LOCAL3 register LOCAL3 area detect signal

3.8.3 Control Registers

Bit symbol L0E L0EA22 L0EA21 L0EA20 Read/Write R/W R/W After reset 0 0 0 0 Function Use BANK for LOCAL0 0: Not use 1: Use Setting BANK number for LOCAL0 LOCAL1 Register 7 6 5 4 3 2 1 0 Bit symbol L1E L1EA23 L1EA22 L1EA21 Read/Write R/W R/W After reset 0 0 0 0 Function Use BANK for LOCAL1 0: Not use 1: Use Setting BANK number for LOCAL1 LOCAL2 Register 7 6 5 4 3 2 1 0 Bit symbol L2E L2EA23 L2EA22 L2EA21 Read/Write R/W R/W After reset 0 0 0 0 Function Use BANK for LOCAL2 0: Disable 1: Enable Setting BANK number for LOCAL2 LOCAL3 Register 7 6 5 4 3 2 1 0 Bit symbol L3E L3EA26 L3EA25 L3EA24 L3EA23 L3EA22 Read/Write R/W R/W After reset 0 0 0 0 0 0 Function Use BANK for LOCAL3 0: Disable 1: Enable 00000 to 00011 CS2B 00100 to 00111 CS2C 01000 to 01011 CS2D 01100 to 01111 CS2E 10000 to 10011 CS2F 10100 to 10111 CS2G 11000 to 11111: Set prohibition Figure 3.8.4 MMU Control Register LOCAL0 (01D0H) LOCAL1 (01D1H) LOCAL2 (01D2H) LOCAL3 (01D3H)

3.8.4 Operational Description

Setup bank value and bank use in bank setting register of each local area of LOCAL register in common area. Moreover, in that case, a combination pin is set up and the MEMC simultaneously sets up mapping. When CPU outputs logical address of the local area, MMU outputs physical address to the outside pin according to value of bank setting register. Access of external memory becomes possible therefore. Common area located in each local area should be passed surely when changing BANK. For example, when the program jump BANK0 of LOCAL2 to BANK6, please jump from BANK0 to COMMON2 once and afterwards jump to BANK6. Please do not use as bank that overlaps with another bank since this common area overlaps with either of eight banks of local area on the physical map. Example program is as next page follows.

• In case of 16-bit bus memory, address connection is …: CPU A1 = Memory A0, CPU A2 = Memory A1… * In case of 8-bit bus memory, address connection is …: CPU A0 = Memory A0, CPU A1 = Memory A1… Figure 3.8.5 H/W Setting Example At, 2H Figure 3.8.5 it shows example of connection TMP92C820 and some memories: Program ROM: MROM, 16 Mbytes, Data ROM: MROM, 64 Mbytes, Data RAM of 8-bit bus: SRAM, 8 Mbytes, Display RAM: SDRAM, 16 Mbytes. In case of 16-bit bus memory connection, it needs to shift 1-bit address bus from TMP92C820 and 8-bit bus case, direct connection address bus from TMP92C820. In that figure, logical address and physical address are shown. And each memory allot each chip select signal, RAM: CS0 , SDRAM: CS1 , Program MROM: CS2 , Data MROM: CS3 . In case of this example, as data MROM is 64 Mbytes, this MROM connect to EA24 and EA25. Initial condition after reset, because TMP92C820 access from CS2 area, CS2 area allots to program ROM. It can set free setting except program ROM. SRAM

8 Mbytes

WRLL , WRLU , WRUL , WRUU SRLLB , SRLUB , SRULB , SRUUB : SRAM SDCLK, SDCKE SDLLDQM, SDLUDQM, SDULDRM, SDUUDQM SDCSL , SDCSH , SDRAS , SDCAS , SDWE CS0 EA24, EA25 TMP92C820 CS1 CS3 CS2 MROM

16 Mbytes

64 Mbytes

000000H~1FFFFFH (Logical) 000000H~7FFFFFH (Physical) Display SDRAM CS1 400000H~7FFFFFH (Logical) 000000H~FFFFFFH (Physical) Program ROM CS2 C00000H~FFFFFFH (Logical) 000000H~FFFFFFH (Physical) Data ROM CS3 800000H~BFFFFFH (Logical) 000000H~3FFFFFH (Physical)

; Initial Setting ; CS0 LD (MSAR0), 00H ; Logical address area: 000000H to 1FFFFFH LD (MAMR0), FFH ; Logical address size: 2 Mbytes LD (B0CSL), 22H ; Condition: WR 3 st ates (1 wait), RD 3 states (1 wait) LD (B0CSH), 80H ; SRAM, 8 bits ; CS1 LD (MSAR1), 40H ; Logical address area: 400000H to 7FFFFFH LD (MAMR1), FFH ; Logical address size: 4 Mbytes LD (B1CSL), 11H ; Condition: WR 2 states (0 waits) RD 2 states (0 waits) LD (B1CSH), 8DH ; Condition: SDRAM, 16 bits ; CS2 LD (MSAR2),C0H ; Logical address area: C00000H to FFFFFFH LD (MAMR2), 7FH ; Logical address size: 4 Mbytes LD (B2CSL), 11H ; Condition: WR 2 states (0 waits) RD 2 states (0 waits) LD (B2CSH), 0C1H ; Condition: ROM, 16 bits ; CS3 LD (MSAR3), 80H ; Logical address area: 800000H to BFFFFFH LD (MAMR3), 7FH ; Logical address size: 4 Mbytes LD (B3CSL), 66H ; Condition: WR 5 states (3 waits), RD 5 states (3 waits) LD (B3CSH), 81H ; Condition: ROM,16 bits ; CSX LD (BEXCSL), 11H ; Condition: WR 2 stat es (0 waits), RD 2 states (0 waits) LD (BEXCSH), 01H ; Condition: 16 bits ; Port LD (P8FC), 3FH ; CS0 to CS3 , EA24, EA25: port 8 setting LD (P8FC2), 02H ; CS1 → SDCSL setting LDW (P7CR), 1F1FH ; WRUU , WRUL , WRLU , WRLL , RD LD (PJFC), 0FFH ; PJ<7:0> = SDRAM control LD (SDACR), 083H ; Add-MUX sele ct type B, SDRAM, auto init enable ~ SDRAM setup time LD (SDRCR), 01H ; Interval refresh Figure 3.8.6 Bank Operation S/W Example 1 Secondly, it shows example of initial setting at 3H Figure 3.8.6. Because CS0 connect to RAM: 8-bit bus, 8 Mbytes, it need to set 8-bit bus. At this example, it set 3 states setting. In the same way CS1 set to 16-bit bus and 2 states, CS2 set 16-bit bus and 2 states, CS3 set 16-bit bus and 5 states. By MEMC controller, each chip selection signal’s memory size, don’t set actual connect memory size, need to set that logical address size: fitting to each local area. Actual physical address is set by each area’s BANK register setting. CSEX setting of MEMC is except above CS0 to CS3’s setting. This program example isn’t used CSEX setting. Finally pin condition is set. Ports 80 to 85 set to CS0 , CS1 , CS2 , CS3 , EA24, EA25, and SDRAM condition.

; Bank Operation ORG 000000H ; Program ROM: Start address at BANK0 of LOCAL2 ORG 200000H ; Program ROM: Start address at BANK1 of LOCAL2 ORG 400000H ; Program ROM: Start address at BANK2 of LOCAL2 ORG 600000H ; Program ROM: Start address at BANK3 of LOCAL2 ORG 800000H ; Program ROM: Start address at BANK4 of LOCAL2 ORG a00000H ; Program ROM: Start address at BANK5 of LOCAL2 ORG c00000H ; Program ROM: Start address at BANK6 of LOCAL2 ORG E00000H ; Program ROM: Start address at BANK7 ( = COMMON2) of LOCAL2 ; Logical address E00000H to FFFFFFH ; Physical address 0E00000H to 0FFFFFFH LD (LOCAL3), 85H ; LOCAL3 BANK5 set 14xxxxH LDW HL, (800000H) ; Load data (5555H) form BANK5 (140000H: Physical address) of LOCAL3 ( CS3 ) LD (LOCAL3), 88H ; LOCAL3 BANK8 set 20xxxxH LDW BC, (800000H) ; Load data (AAAAH) form BANK8 (200000H: Physical address) of LOCAL3 ( CS3 ) ORG FFFFFFH ; Program ROM: End address at BANK7 ( = COMMON2) of LOCAL2 ORG 0000000H ; Data ROM: Start address at BANK0 of LOCAL3 ORG 0400000H ; Data ROM: Start address at BANK1 of LOCAL3 ORG 0800000H ; Data ROM: Start address at BANK2 of LOCAL3 ORG 0C00000H ; Data ROM: Start address at BANK3 of LOCAL3 ORG 1000000H ; Data ROM: Start address at BANK4 of LOCAL3 ORG 1400000H ; Data ROM: Start address at BANK5 of LOCAL3 dw 5555H ORG 1800000H ; Data ROM: Start address at BANK6 of LOCAL3 ORG 1C00000H ; Data ROM: Start address at BANK7 of LOCAL3 ORG 2000000H ; Data ROM: Start address at BANK8 of LOCAL3 dw AAAAH ORG 2400000H ; Data ROM: Start address at BANK9 of LOCAL3 ORG 2800000H ; Data ROM: Start address at BANK10 of LOCAL3 ORG 2C00000H ; Data ROM: Start address at BANK11 of LOCAL3 ORG 3000000H ; Data ROM: Start address at BANK12 of LOCAL3 ORG 3400000H ; Data ROM: Start address at BANK13 of LOCAL3 ORG 3800000H ; Data ROM: Start address at BANK14 of LOCAL3 ORG 3C00000H ; Data ROM: Start address at BANK15 of LOCAL3 ORG 3FFFFFFH ; Data ROM: End address at BANK15 of LOCAL3 Figure 3.8.7 Bank Operation S/W Example 2 Here shows example of data access between one BANK and other BANK. 4H Figure 3.8.7 is one software example. A dot line square area shows one memory and each dot line square shows CS2 ’s program ROM and CS3 ’s data ROM. Program start from E00000H address, firstly, write to BANK register of LOCAL3 area upper 5-bit address of access point. In case of this example, because most upper address bit of physical address is EA25, most upper address bit of BANK register is meaningless. 4 bits of upper 5 bits address means 16 BANKs. After setting BANK5, accessing 800000H to BFFFFFH address: Logical LOCAL3 address, actually access to physical 1400000H to 1700000H address.

; Bank Operation ORG 000000H ; Program ROM: Start address at BANK0 of LOCAL2 ORG 200000H ; Program ROM: Start address at BANK1 of LOCAL2 NOP ; Operation at BANK1 of LOCAL2 JP E00100H ; Jump to BANK7 ( = COMMON2) of LOCAL2 ORG 400000H ; Program ROM: Start address at BANK2 of LOCAL2 ORG 600000H ; Program ROM: Start address at BANK3 of LOCAL2 NOP ; Operation at BANK3 of LOCAL2 JP E00200H ; Jump to BANK7 ( = COMMON2) of LOCAL2 ORG 800000H ; Program ROM: Start address at BANK4 of LOCAL2 ORG a00000H ; Program ROM: Start address at BANK5 of LOCAL2 ORG c00000H ; Program ROM: Start address at BANK6 of LOCAL2 ORG E00000H ; Program ROM: Start address at BANK7 ( = COMMON2) of LOCAL2 ; Logical address E00000H to FFFFFFH ; Physical address 0E00000H to 0FFFFFFH LD (LOCAL2), 81H ; LOCAL2 BANK1 set 20xxxxH JP C00000H ; Jump to BANK1 (200000H: Physical address) of LOCAL2 ORG E00100H LD (LOCAL2), 83H ; LOCAL2 BANK3 set 60xxxxH JP C00000H ; Jump to BANK3 (600000H: Physical address) of LOCAL2 ORG E00200H LD (LOCAL1), 00H ; Disable Bank! ~ ; LCD display set LD (LSARCH), 60H ; C_area start address LD (LSARCM), 00H ; C_area start address LD (LSARCL), 00H ; C_area start address SET 0, (LCTCTL) ; LCD Display start ORG FFFFFFH ; Program ROM: End address at BANK7 ( = COMMON2) of LOCAL2 ORG 000000H ; SDRAM: Start address at BANK0 of LOCAL1 ORG 200000H ; SDRAM: Start address at BANK1 of LOCAL1 ORG 400000H ; SDRAM: Start address at BANK2 of LOCAL1 ORG 600000H ; SDRAM: Start address at BANK3 ( = COMMON1) of LOCAL1 dl 01234567H ; display data ORG 800000H ; SDRAM: Start address at BANK4 of LOCAL1 ORG a00000H ; SDRAM: Start address at BANK5 of LOCAL1 ORG c00000 ; SDRAM: Start address at BANK6 of LOCAL1 ORG E00000H ; SDRAM: Star t address at BANK7 of LOCAL1 ORG FFFFFFH ; SDRAM: End address at BANK7 of LOCAL1 Figure 3.8.8 Bank Operation S/W Example 3

At 5H Figure 3.8.8, it shows example of program jump. In the same way with before example, two dot line squares show each CS2 ’s program ROM and CS1 ’s (SDCS) SDRAM. Program start from E00000H common address, firstly, write to BANK register of LOCAL2 area upper 3-bit address of jumping point. After setting BANK1, jumping C00000H to DFFFFFH address: Logical LOCAL2 address, actually jump to physical 200000H to 3FFFFFH address. When return to common area, it can only jump to E00000H to FFFFFFH without writing to BANK register of LOCAL2 area. By a way of setting of BANK register, the setting that BANK address and common address conflict with is possi ble. When two kinds or more logical addresses to show common area exist, management of BANK is confused. We recommends not to use the BANK setting, BANK address and common address conflict with. Please set similarly when jumping through CS . After setting BANK4, jumping 400000H to 5FFFFFH address: Logical local area of CS1 , actually jump to physical 800000H to 9FFFFFH address. When using LCD display data for SDRAM, we recommend setting display area to common area in SDRAM. Because of, LCD displays DMA occurs at synchronous less. If SDRAM bank is change; you don’t need to care only common area. It is a mark paid attention to here, it needs to go by way of common area by all means when moves from a bank to a bank. In other words, it must write to BANK register only in common area and it prohibits writing the BANK registers in BANK area. If it modify the BANK register’s data in BANK area, program run away. Please do not set bank function of MMU as display RAM. This is because reading LCDC display data is not controlled by the CPU. Therefore if BANK of display area is changed during LCD displaying, it cannot display. It is recommended to allocate display data to a common area.

3.9 Serial Channels (SIO)

The TMP92C820 includes three serial I/O channels. For each channel either UART mode (Asynchronous transmission) or I/O interface mode (Synchronous transmission) can be selected. (Channel 2 can be selected only UART mode.)

• I/O interface mode Mode 0: For transmitting and receiving I/O data using the synchronizing signal SCLK for extending I/O. Mode 1: 7-bit data
• UART mode Mode 2: 8-bit data Mode 3: 9-bit data In mode 1 and mode 2 a parity bit can be added. Mode 3 has a wakeup function for making the master controller start slave controllers via a serial link (Multi-controller system). Each channel can be used independently. Each channel operates in the same fashion except for the following points; hence only the operation of channel 0 is explained below. Table 3.9.1 Differences between Channels 0 to 2 Channel 0 Channel 1 Channel 2 Pin name TXD0 (PF0) RXD0 (PF1) 0CTS /SCLK0 (PF2) TXD1 (PF3) RXD1 (PF4) 1CTS /SCLK1 (PF5) TXD2 (P95) RXD2 (P96) IrDA mode Yes No No This chapter contains the following sections: 3H 3.9.1 4H Block Diagrams 5H 3.9.2 6H Operation for Each Circuit 7H 3.9.3 8H SFRs 9H 3.9.4 10H Operation in Each Mode 11H 3.9.5 12H Support for IrDA

Figure 3.9.1 Data Formats Stop Bit0 1 2 3 4 5 6 7 Bit0 1 2 3 4 5 6S t o pStart Bit0 1 2 3 4 5 Parity StopStart 6 Bit0 1 2 3 4 5 7S t o pStart Bit0 1 2 3 4 5 Parity Stop Start 7 Bit0 1 2 3 4 5 8 Stop Start Bit0 1 2 3 4 5Start Bit8 Transfer direction

• Mode 0 (I/O interface mode)
• Mode 1 (7-bit UART mode) No parity Parity No parity Parity
• Mode 2 (8-bit UART mode)
• Mode 3 (9-bit UART mode) When bit8 = 1, address (Select code) is denoted. When bit8 = 0, data is denoted. Wakeup

3.9.1 Block Diagrams

Figure 3.9.2 Block Diagram of Serial Channel 0 Selector φT0 φT2 φT8 φT32 SC0MOD0 <SC1:0> Receive buffer 1 (Shift register) RXDCLK SC0MOD0 <CTSE> Prescaler Selector TA0TRG (from TMRA0) UART mode BR0CR <BR0S3:0> Baud rate generator Selector SC0MOD0 <SM1:0> Selector I/O interface mode SC0CR <IOC> Receive counter (UART only ÷ 16) Transmision counter (UART only ÷ 16) Receive control Transmission control INTRX0 INTTX0 Receive buffer 2 (SC0BUF)RB8 Error flag SC0CR Serial channel interrupt control TB8 CTS0 (Shared with PF2) TXD0 (Shared with PF0) Transmission buffer (SC0BUF) RXD0 (Shared with PF1) TXDCLK SC0MOD0 <WU> fIO SC0MOD0 <RXE> SCLK0 OUT (Shared with PF2) SCLK0 IN (Shared with PF2) SIOCLK Internal data bus Parity control SC0CR <PE> <EVEN> Serial clock generation circuit BR0CR<BR0CK1:0> BR0ADD <BR0K3:0> BR0CR <BR0ADDE> I/O interface mode φT0 2 64 4 8 16 32 Prescaler φT2 φT8 φT32 INT request

Figure 3.9.3 Block Diagram of Serial Channel 1 Selector φT0 φT2 φT8 φT32 SC1MOD0 <SC1:0> Receive buffer 1 (Shift register) RXDCLK SC1MOD0 <CTSE> Prescaler Selector TA0TRG (from TMRA0) UART mode BR1CR <BR1S3:0> Baud rate generator Selector SC1MOD0 <SM1:0> Selector I/O interface mode SC1CR <IOC> Receive counter (UART only ÷ 16) Transmision counter (UART only ÷ 16) Receive control Transmission control INTRX1 INTTX1 Receive buffer 2 (SC1BUF)RB8 Error flag SC1CR Serial channel interrupt control TB8 CTS1 (Shared with PF5) TXD1 (Shared with PF3) Transmission buffer (SC1BUF) RXD1 (Shared with PF4) TXDCLK SC1MOD0 <WU> fIO SC1MOD0 <RXE> SCLK1 OUT (Shared with PF5) SCLK1 IN (Shared with PF5) SIOCLK Internal data bus Parity control SC1CR <PE> <EVEN> Serial clock generation circuit BR1CR<BR1CK1:0> BR1ADD <BR1K3:0> BR1CR <BR1ADDE> I/O interface mode φT0 2 64 4 8 16 32 Prescaler φT2 φT8 φT32 INT request

Figure 3.9.4 Block Diagram of Serial Channel 2 Selector φT0 φT2 φT8 φT32 SC2MOD0 <SC1:0> Receive buffer 1 (Shift register) RXDCLK Prescaler Selector TA0TRG (from TMRA0) UART mode BR2CR <BR2S3:0> Baud rate generator Selector SC2MOD0 <SM1:0> Selector I/O interface mode SC2CR <IOC> Receive counter (UART only ÷ 16) Transmision counter (UART only ÷ 16) Receive control Transmission control INTRX2 INTTX2 Receive buffer 2 (SC2BUF)RB8 Error flag SC2CR Serial channel interrupt control TB8 TXD2 (Shared with P95) Transmission buffer (SC2BUF) RXD2 (Shared with P96) TXDCLK SC2MOD0 <WU> fIO SC2MOD0 <RXE> SCLK1 IN (Shared with PF5) SIOCLK Internal data bus Parity control SC2CR <PE> <EVEN> Serial clock generation circuit BR2CR<BR2CK1:0> BR2ADD <BR2K3:0> BR2CR <BR2ADDE> φT0 2 64 4 8 16 32 Prescaler φT2 φT8 φT32 INT request

3.9.2 Operation for Each Circuit

(1) Prescaler, prescaler clock select There is a 6-bit prescaler for waking serial clock. The prescaler can be run by selecting the baud rate generator as the waking serial clock. 13H Table 3.9.2 shows prescaler clock resolution into the baud rate generator. Table 3.9.2 Prescaler Clock Resolution to Baud Rate Generator Baud rate generator input clock SIO prescaler BR0CR<BR0CK1:0> − Clock gear selection SYSCR1 <GEAR2:0> 000(1/1) fc/8 fc/32 fc/128 fc/512 001(1/2) fc/16 fc/64 fc/256 fc/1024 010(1/4) fc/32 fc/128 fc/512 fc/2048 011(1/8) fc/64 fc/256 fc/1024 fc/4096 fc 100(1/16) fc/128 fc/512 fc/2048 fc/8192 The baud rate generator selects between 4 clock inputs: φT0, φT2, φT8, and φT32 among the prescaler outputs.

(2) Baud rate generator The baud rate generator is a circuit which generates transmission and receiving clocks that determine the transfer rate of the serial channels. The input clock to the baud rate generator, φT0, φT2, φT8, or φT32, is generated by the 6-bit prescaler which is shared by the timers. One of these input clocks is selected using the BR0CR<BR0CK1:0> field in the baud rate generator control register. The baud rate generator includes a frequency divider, which divides the frequency by 1 or N + (16 − K)/16 or 16 values, thereby determining the transfer rate. The transfer rate is determined by the settings of BR0CR<BR0ADDE, BR0S3:0> and BR0ADD<BR0K3:0>.

• In UART mode (1) When BR0CR<BR0ADDE> = 0 The settings BR0ADD<BR0K3:0> are ignored. The baud rate generator divides the selected prescaler clock by N, which is set in BR0CK<BR0S3:0>. (N = 1, 2, 3…16) (2) When BR0CR<BR0ADDE> = 1 The N + (16 − K)/16 division function is enabled. The baud rate generator divides the selected prescaler clock by N + (16 − K)/16 using the value of N set in BR0CR<BR0S3:0> (N = 2, 3…15) and the value of K set in BR0ADD<BR0K3:0> (K = 1, 2, 3…5) Note: If N = 1 or N = 16, the N + (16 − K)/16 division function is disabled. Set BR0CR<BR0ADDE> to 0.
• In I/O interface mode The N + (16 − K)/16 division function is not available in I/O interface mode. Set BR0CR<BR0ADDE> to 0 before dividing by N. The method for calculating the transfer rate when the baud rate generator is used is explained below.
• In UART mode Input clock of baud rate generator Baud rate = Frequency divider for baud rate generator ÷ 16
• In I/O interface mode Input clock of baud rate generator Baud rate = Frequency divider for baud rate generator ÷ 2

• Integer divider (N divider) For example, when the source clock frequency (fC) is 39.3216 MHz, the input clock is φT2 (fC/32), the frequency divider N (BR0CR<BR0S3:0>) = 8, and BR0CR<BR0ADDE> = 0, the baud rate in UART mode is as follows: * Clock state Clock gear: 1/1 (f C) fC/32 Baud rate = 8 ÷ 16 = 39.3216 × 106 ÷ 16 ÷ 8 ÷ 16 = 9600 (bps) Note: The N + (16 − K)/16 division function is disabled and setting BR0ADD<BR0K3:0> is invalid.
• N + (16 − K)/16 divider (UART mode only) Accordingly, when the source clock frequency (fC) = 31.9488 MHz, the input clock is φT2 (fC/32), the frequency divider N (BR0CR<BR0S3:0>) = 6, K (BR0ADD<BR0K3:0>) = 8, and BR0CR<BR0ADDE> = 1, the baud rate in UART mode is as follows: * Clock state Clock gear: 1/1 (f C) fC/32 (16 − 8) Baud rate = 6 + 16 ÷ 16 = 31.9488 × 106 ÷ 16 ÷ (6 + 16 ) ÷ 16 = 9600 (bps) 14H Table 3.9.3 show examples of UART mode transfer rates. Additionally, the external clock input is available in the serial clock (Serial channels 0 and 1). The method for calculating the baud rate is explained below:
• In UART mode Baud rate = External clock input frequency ÷ 16 It is necessary to satisfy (External clock input cycle) ≥ 4/fSYS
• In I/O interface mode Baud rate = External clock input frequency It is necessary to satisfy (External clock input cycle) ≥ 16/fSYS

Table 3.9.3 Selection of Transfer Rate (1) (When baud rate generator is used and BR0CR<BR0ADDE> = 0) Unit (kbps) fSYS [MHz] Input Clock Frequency Divider φT0 (fSYS/4) φT2 (fSYS/16) φT8 (fSYS/64) φT32 (fSYS/256) ↑ 4 38.400 9.600 2.400 0.600 ↑ 8 19.200 4.800 1.200 0.300 ↑ 10 9.600 2.400 0.600 0.150 ↑ A 19.200 4.800 1.200 0.300 ↑ 3 76.800 19.200 4.800 1.200 ↑ 6 38.400 9.600 2.400 0.600 ↑ C 19.200 4.800 1.200 0.300 ↑ 2 153.600 38.400 9.600 2.400 ↑ 4 76.800 19.200 4.800 1.200 ↑ 8 38.400 9.600 2.400 0.600 ↑ 10 19.200 4.800 1.200 0.300 ↑ 2 192.000 48.000 12.000 3.000 ↑ 4 96.000 24.000 6.000 1.500 ↑ 5 76.800 19.200 4.800 1.200 ↑ 8 48.000 12.000 3.000 0.750 ↑ A 38.400 9.600 2.400 0.600 ↑ 10 24.000 6.000 1.500 0.375 Note: Transfer rates in I/O interface mode are eight times faster than the values given above. In UART mode, TMRA match detect sign al (TA0TRG) can be used for serial transfer clock. Method for calculating the timer output frequency which is needed when outputting trigger of timer TA0TRG frequency = Baud rate × 16 Note: The TMRA0 match detect signal cannot be used as the transfer clock in I/O Interface mode.

(3) Serial clock generation circuit This circuit generates the basic clock for transmitting and receiving data.

• In I/O interface mode In SCLK output mode with the setting SC0CR<IOC> = 0, the basic clock is generated by dividing the output of the baud rate generator by 2, as described previously. In SCLK input mode with the setting SC0CR<IOC> = 1, the rising edge or falling edge will be detected according to the setting of the SC0CR<SCLKS> register to generate the basic clock.
• In UART mode The SC0MOD0<SC1:0> setting determines whether the baud rate generator clock, the internal clock fIO, the match detect signal from timer TMRA0 or the external clock (SCLK0) is used to generate the basic clock SIOCLK. (4) Receiving counter The receiving counter is a 4-bit binary counter used in UART mode, which counts up the pulses of the SIOCLK clock. It takes 16 SIOCLK pulses to receive 1 bit of data; each data bit is sampled three times–on the 7th, 8th, and 9th clock cycles. The value of the data bit is determined from these three samples using the majority rule. For example, if the data bit is sampled respectively as 1, 0 and 1 on 7th, 8th and 9th clock cycles, the received data bit is taken to be 1. A data bit sampled as 0, 0 and 1 is taken to be 0. (5) Receiving control
• In I/O interface mode In SCLK output mode with the setting SC0CR<IOC> = 0, the RXD0 signal is sampled on the rising or falling edge of the shift clock which is output on the SCLK0 pin, according to the SC0CR<SCLKS> setting. In SCLK input mode with the setting SC0CR<IOC> = 1, the RXD0 signal is sampled on the rising or falling edge of the SCLK0 input, according to the SC0CR<SCLKS> setting.
• In UART mode The receiving control block has a circuit, which detects a start bit using the majority rule. Received bits are sampled three times; when two or more out of three samples are 0, the bit is recognized as the start bit and the receiving operation commences. The values of the data bits that are received are also determined using the majority rule.

(6) The receiving buffers To prevent overrun errors, the receiving buffers are arranged in a double-buffer structure. Received data is stored one bit at a time in receiving buffer 1 (which is a shift register). When 7 or 8 bits of data have been stored in receiving buffer 1, the stored data is transferred to receiving buffer 2 (SC0BUF); this causes an INTRX0 interrupt to be generated. The CPU only reads receiving buffer 2 (SC0BUF). Even before the CPU reads receiving buffer 2 (SC0BUF), the received data can be stored in receiving buffer 1. However, unless receiving buffer 2 (SC0BUF) is read before all bits of the next data are received by receiving buffer 1, an overrun error occurs. If an overrun error occurs, the contents of receiving buffer 1 will be lost, although the contents of receiving buffer 2 and SC0CR<RB8> will be preserved. SC0CR<RB8> is used to store either the parity bit−added in 8-bit UART mode−or the most significant bit (MSB) −in 9-bit UART mode. In 9-bit UART mode the wakeup function for the slave controller is enabled by setting SC0MOD0<WU> to 1; in this mode INTRX0 interrupts occur only when the value of SC0CR<RB8> is 1. SIO interrupt mode is selectable by the register SIMC. (7) Transmission counter The transmission counter is a 4-bit binary counter which is used in UART mode and which, like the receiving counter, counts the SIOCLK clock pulses; a TXDCLK pulse is generated every 16 SIOCLK clock pulses. Figure 3.9.5 Generation of the Transmission Clock (8) Transmission controller

• In I/O interface mode In SCLK output mode with the setting SC0CR<IOC> = 0, the data in the transmission buffer is output one bit at a time to the TXD0 pin on the rising or falling edge of the shift clock which is output on the SCLK0 pin, according to the SC0CR<SCLKS> setting. In SCLK input mode with the setting SC0CR<IOC> = 1, the data in the transmission buffer is output one bit at a time on the TXD0 pin on the rising or falling edge of the SCLK0 input, according to the SC0CR<SCLKS> setting.
• In UART mode When transmission data sent from the CPU is written to the transmission buffer, transmission starts on the rising edge of the next TXDCLK, generating a transmission shift clock TXDSFT. 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 SIOCLK TXDCLK

(9) Transmission buffer The transmission buffer (SC0BUF) shifts out and sends the transmission data written from the CPU form the least significant bit (LSB) in order. When all the bits are shifted out, the transmission buffer becomes empty and generates an INTTX0 interrupt. (10) Parity control circuit When SC0CR<PE> in the serial channel control register is set to 1, it is possible to transmit and receive data with parity. However, parity can be added only in 7-bit UART mode or 8-bit UART mode. The SC0CR<EVEN> field in the serial channel control register allows either even or odd parity to be selected. In the case of transmission, parity is automatically generated when data is written to the transmission buffer SC0BUF. The data is transmitted after the parity bit has been stored in SC0BUF<TB7> in 7-bit UART mode or in SC0MOD0<TB8> in 8-bit UART mode. SC0CR<PE> and SC0CR<EVEN> must be set before the transmission data is written to the transmission buffer. In the case of receiving, data is shifted into receiving buffer 1, and the parity is added after the data has been transferred to receiving buffer 2 (SC0BUF), and then compared with SC0BUF<RB7> in 7-bit UART mode or with SC0CR<RB8> in 8-bit UART mode. If they are not equal, a parity error is generated and the SC0CR<PERR> flag is set. (11) Error flags Three error flags are provided to increase the reliability of data reception. 1. Overrun error <OERR> If all the bits of the next data item have been received in receiving buffer 1 while valid data still remains stored in receiving buffer 2 (SC0BUF), an overrun error is generated. The below is a recommended flow when the overrun error is generated. (INTRX interrupt routine) (1) Read receiving buffer (2) Read error flag (3) If <OERR> = 1 then (a) Set to disable receiving (Write “0” to SC0MOD0<RXE>) (b) Wait to terminate current frame (c) Read receiving buffer (d) Read error flag (e) Set to enable receiving (Write “1” to SC0MOD0<RXE>) (f) Request to transmit again (4) Other 2. Parity error <PERR> The parity generated for the data shifted into receiving buffer 2 (SC0BUF) is compared with the parity bit received via the RXD pin. If they are not equal, a parity error is generated.

1. Framing error <FERR> The stop bit for the received data is sampled three times around the center. If the majority of the samples are 0, a framing error is generated. (12) Timing generation 1. In UART mode Receiving Mode 9 Bits (Note) 8 Bits + Parity (Note) 8 Bits, 7 Bits + Parity, 7 Bits Interrupt timing Center of last bit (Bit8) Center of last bit (Parity bit) Center of stop bit Framing error timing Center of stop bit Center of stop bit Center of stop bit Parity error timing − Center of last bit (Parity bit) Center of stop bit Overrun error timing Center of last bit (Bit8) Center of last bit (Parity bit) Center of stop bit Note1: In 9-bit and 8-bit  parity modes, interrupts coincide with the ninth bit pulse. Thus, when servicing the interrupt, it is necessary to wait for a 1-bit period (to allow the stop bit to be transferred) to allow checking for a framing error. Note2: The higher the transfer rate, the later than the middle receive interrupts and errors occur. Transmitting Mode 9 Bits 8 Bits + Parity 8 Bits, 7 Bits + Parity, 7 Bits Interrupt timing Just before stop bit is transmitted ← ← 2. I/O interface SCLK output mode Immediately after last bit data. (See 15H Figure 3.9.25) Transmission Interrupt timing SCLK input mode Immediately after rise of last SCLK signal rising mode, or immediately after fall in falling mode.) (See 16H Figure 3.9.26) SCLK output mode Timing used to transfer received to data receive buffer 2 (SC0BUF) (e.g., immediately after last SCLK) (See 17H Figure 3.9.27) Receiving Interrupt timing SCLK input mode Timing used to transfer received data to receive buffer 2 (SC0BUF) (e.g., immediately after last SCLK). (See 18H Figure 3.9.28)

3.9.3 SFRs

Bit symbol TB8 CTSE RXE WU SM1 SM0 SC1 SC0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Transfer data bit8 Hand shake 0: CTS disable 1: CTS enable Receive function 0: Receive disable 1: Receive enable Wakeup function 0: Disable 1: Enable Serial transmission mode 00: I/O interface mode 01: 7-bit UART mode 10: 8-bit UART mode 11: 9-bit UART mode Serial transmission clock (UART) 00: TA0TRG 01: Baud rate generator 10: Internal clock f IO 11: External clock (SCLK0 input) Serial transmission clock source (UART)

00 TMRA0 match detect signal

01 Baud rate generator

10 Internal clock f IO

11 External clock (SCLK0 input)

Note: The clock selection for the I/O interface mode is controlled by the serial control register (SC0CR). Serial transmission mode

00 I/O interface mode

0 Interrupt generated

1 Interrupt generated

SC0CR<RB8> = 1 Don’t care Receiving function

0 Receive disabled

1 Receive enabled

Handshake function ( CTS pin)

0 Disabled (Always transferable)

Figure 3.9.8 Serial Mode Control Register (Channel 0, SC0MOD0) SC0MOD0 (1202H)

Bit symbol TB8 CTSE RXE WU SM1 SM0 SC1 SC0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Transfer data bit8 Hand shake 0: CTS disable 1: CTS enable Receive function 0: Receive disable 1: Receive enable Wakeup function 0: Disable 1: Enable Serial transmission mode 00: I/O interface mode 01: 7-bit UART mode 10: 8-bit UART mode 11: 9-bit UART mode Serial transmission clock (UART) 00: TA0TRG 01: Baud rate generator 10: Internal clock f IO 11: External clock (SCLK1 input) Serial transmission clock source (for UART)

11 External clock (SCLK1 input)

Note: The clock selection for the I/O interface mode is controlled by the serial control register (SC1CR). Serial transmission mode SC1CR<RB8> = 1 Don’t care Receiving function Handshake function ( CTS pin) Figure 3.9.9 Serial Mode Control Register (Channel 1, SC1MOD0) SC1MOD0 (120AH)

Bit symbol TB8 − RXE WU SM1 SM0 SC1 SC0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Transfer data bit8 Always write “0”. Receive function 0: Receive disable 1: Receive enable Wakeup function 0: Disable 1: Enable Serial transmission mode 00: I/O interface mode 01: 7-bit UART mode 10: 8-bit UART mode 11: 9-bit UART mode Serial transmission clock (UART) 00: TA0TRG 01: Baud rate generator 10: Internal clock f IO 11: Reserved Serial transmission clock source (for UART)

11 Reserved

SC2CR<RB8> = 1 Don’t care Receiving function Figure 3.9.10 Serial Mode Control Register (Channel 2, SC2MOD0) SC2MOD0 (1212H)

Bit symbol RB8 EVEN PE OERR PERR FERR SCLKS IOC Read/Write R R/W R (Cleared to 0 when read) R/W After reset Undefined 0 0 0 0 0 0 0 1: Error Function Received data bit8 Parity 0: Odd 1: Even Parity addition 0: Disable 1: Enable Overrun Parity Framing 0: SCLK0 1: SCLK0 0: Baud rate generato r 1: SCLK0 pin input I/O interface input clock selection

0 Baud rate generator

1 SCLK0 pin input

Edge selection for SCLK pin (Input/Output mode)

0 Transmits and receives

SCLK0.

1 Transmits and receives

SCLK0. Framing error flag Parity error flag Overrun error flag Parity additions enable Even parity addition/check

0 Odd parity

1 Even parity

Note: As all error flags are cleared after reading do not test only a single bit with a bit-testing instruction. Figure 3.9.11 Serial Control Register (Channel 0, SC0CR) SC0CR (1201H) Cleared to 0 when read

Bit symbol RB8 EVEN PE OERR PERR FERR SCLKS IOC Read/Write R R/W R (Cleared to 0 when read) R/W After reset Undefined 0 0 0 0 0 0 0 1: Error Function Received data bit8 Parity 0: Odd 1: Even Parity addition 0: Disable 1: Enable Overrun Parity Framing 0: SCLK1 1: SCLK1 0: Baud rate generato r 1: SCLK1 pin input I/O interface input clock select

1 SCLK1 pin input

Edge selection for SCLK pin (Input/Output mode) SCLK1. SCLK1. Framing error flag Parity error flag Overrun error flag Parity additions enable Even parity addition/check Note: As all error flags are cleared after reading do not test only a single bit with a bit-testing instruction. Figure 3.9.12 Serial Control Register (Channel 1, SC1CR) SC1CR (1209H) Cleared to 0 when read

Bit symbol RB8 EVEN PE OERR PERR FERR − − Read/Write R R/W R (Cleared to 0 when read) R/W After reset Undefined 0 0 0 0 0 0 0 1: Error Function Received data bit8 Parity 0: Odd 1: Even Parity addition 0: Disable 1: Enable Overrun Parity Framing Always write “0”. Always write “0”. Framing error flag Parity error flag Overrun error flag Parity additions enable Even parity addition/check Note: As all error flags are cleared after reading do not test only a single bit with a bit-testing instruction. Figure 3.9.13 Serial Control Register (Channel 2, SC2CR) SC2CR (1211H) Cleared to 0 when read

Bit symbol − BR0ADDE BR0CK1 BR0CK0 BR0S3 BR0S2 BR0S1 BR0S0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Always write “0”. + (16 − K)/16 division 0: Disable 1: Enable 00: φT0 01: φT2 10: φT8 11: φT32 Divided frequency setting + (16 − K)/16 division enable Setting the input clock of baud rate generator 7 6 5 4 3 2 1 0 Bit symbol BR0K3 BR0K2 BR0K1 BR0K0 Read/Write R/W After reset 0 0 0 0 Function Sets frequency divisor “K” (divided by N + (16 − K)/16) Sets baud rate generator frequency divisor BR0CR<BR0ADDE> = 1 BR0CR<BR0ADDE> = 0 BR0CR <BR0S3:0> BR0ADD <BR0K3:0> 0000 (N = 16) or 0001 (N = 1) 0010 (N = 2) to 1111 (N = 15) 0001 (N = 1) (UART only) to 1111 (N = 15) 0000 (N = 16)

0000 Disable Disable

0001 (K = 1) to 1111 (K = 15) Disable Divided by N + (16 − K)/16 Divided by N Note1: Availability of +(16-K)/16 division function N UART mode I/O mode 2 to 15 ○ × 1 , 16 × × The baud rate generator can be set to “1” in UART mode only when the +(16-K)/16 division function is not used. Do not use in I/O interface mode. Note2: Set BR0CR <BR0ADDE> to 1 after setting K (K = 1 to 15) to BR0ADD<BR0K3:0> when +(16-K)/16 division function is used. Writes to unused bits in the BR0ADD register do not affect operation, and undefined data is read from these unused bits. Figure 3.9.14 Baud Rate Generator Control (Channel 0, BR0CR, BR0ADD) BR0ADD (1204H) BR0CR (1203H)

00 Internal clock φT0

01 Internal clock φT2

10 Internal clock φT8

11 Internal clock φT32

Bit symbol − BR1ADDE BR1CK1 BR1CK0 BR1S3 BR1S2 BR1S1 BR1S0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Always write “0”. + (16 − K)/16 division 0: Disable 1: Enable 00: φT0 01: φT2 10: φT8 11: φT32 Divided frequency setting + (16 − K)/16 division enable Input clock selection for baud rate generator 7 6 5 4 3 2 1 0 Bit symbol BR1K3 BR1K2 BR1K1 BR1K0 Read/Write R/W After reset 0 0 0 0 Function Set frequency divisor K (divided by N + (16 − K)/16) Baud rate generator frequency divisor setting BR1CR<BR1ADDE> = 1 BR1CR<BR1ADDE> = 0 BR1CR <BR1S3:0> BR1ADD <BR1K3:0> 0000 (N = 16) or 0001 (N = 1) 0010 (N = 2) to 1111 (N = 15) 0001 (N = 1) (UART only) to 1111 (N = 15) 0000 (N = 16) 0001 (K = 1) to 1111 (K = 15) Disable Divided by N + (16 − K)/16 Divided by N Note1: Availability of +(16-K)/16 division function N UART mode I/O mode 2 to 15 ○ × 1 , 16 × × The baud rate generator can be set “1” in UART mode only when the +(16-K)/16 division function is not used. Do not use in I/O interface mode. Note2: Set BR1CR <BR1ADDE> to 1 after setting K (K = 1 to 15) to BR1ADD<BR1K3:0> when the +(16-K)/16 division function is used. Writes to unused bits in the BR1ADD register do not affect operation, and undefined data is read from these unused bits. Figure 3.9.15 Baud Rate Generator Control (Channel 1, BR1CR, BR1ADD) BR1CR (120BH) (120CH)

Bit symbol − BR2ADDE BR2CK1 BR2CK0 BR2S3 BR2S2 BR2S1 BR2S0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Always write “0”. + (16 − K)/16 division 0: Disable 1: Enable 00: φT0 01: φT2 10: φT8 11: φT32 Divided frequency setting + (16 − K)/16 division enable Input clock selection for baud rate generator 7 6 5 4 3 2 1 0 Bit symbol BR2K3 BR2K2 BR2K1 BR2K0 Read/Write R/W After reset 0 0 0 0 Function Set frequency divisor K (divided by N + (16 − K)/16) Baud rate generator frequency divisor setting BR2CR<BR2ADDE> = 1 BR2CR<BR2ADDE> = 0 BR2CR <BR2S3:0> BR2ADD <BR2K3:0> 0000 (N = 16) or 0001 (N = 1) 0010 (N = 2) to 1111 (N = 15) 0001 (N = 1) (UART only) to 1111 (N = 15) 0000 (N = 16) 0001 (K = 1) to 1111 (K = 15) Disable Divided by N + (16 − K)/16 Divided by N Note1: Availability of +(16-K)/16 division function N UART mode I/O mode 2 to 15 ○ × 1 , 16 × × The baud rate generator can be set “1” in UART mode only when the +(16-K)/16 division function is not used. Do not use in I/O interface mode. Note2: Set BR2CR <BR2ADDE> to 1 after setting K (K = 1 to 15) to BR2ADD<BR2K3:0> when the +(16-K)/16 division function is used. Writes to unused bits in the BR2ADD register do not affect operation, and undefined data is read from these unused bits. Figure 3.9.16 Baud Rate Generator Control (Channel 2, BR2CR, BR2ADD) BR2CR (1213H) (1214H)

3.9.4 Operation in Each Mode

(1) Mode 0 (I/O interface mode) This mode allows an increase in the number of I/O pins available for transmitting data to or receiving data from an external shift register. This mode includes the SCLK output mode to output synchronous clock SCLK and SCLK input mode to input external synchronous clock SCLK. Figure 3.9.23 SCLK Output Mode Connection Example Figure 3.9.24 Example of SCLK Input Mode Connection Output extension TC74HC595 or equivalent A B SI C D SCK E F RCK G H TXD SCLK Port Shift register TMP92C820 Input extension TC74HC165 or equivalent A B QH C D CLOCK E F L G H RXD SCLK Port Shift register TMP92C820 Output extension TC74HC595 or equivalent A B SI C D SCK E F RCK G H TXD SCLK Port Shift register TMP92C820 Input extension TC74HC165 or equivalent A B QH C D CLOCK E F L G H RXD SCLK Port Shift register TMP92C820 External clock External clock

1. Transmission and receiving (Full duplex mode) When full duplex mode is used, set the receive interrupt level to 0 and set enable the level of transmit interrupt. Ensure that the program which transmits the interrupt reads the receiving buffer before setting the next transmit data. The following is an example of this: Example: Channel 0, SCLK output Baud rate = 9600 bps fC = 4.9152 MHz * Clock state Clock gear 1/1 (f C) Main routine 7 6 5 4 3 210 INTES0 ← X 0 0 1 X 0 0 0 Set the INTTX0 level to 1. Set the INTRX0 level to 0. PFCR ← X X − − − 1 0 1 Set PF0, PF1, and PF2 to function as the TXD0, RXD0, PFFC ← X X − X − 1 X 1 and SCLK0 pins respectively. SC0MOD0 ← − − − − 0 0 − − Enable receiving and select I/O interface mode. SC0MOD1 ← 1 1 X X X X X X Select full duplex mode. SC0CR ← 0 0 0 0 0 0 0 0 SCLK output, transmit on negative edge, receive on positive edge. BR0CR ← 0 0 0 1 1 0 0 0 Baud rate = 9600 bps. SC0MOD0 ← − − 1 − − − − − Enable receiving. SC0BUF ← * * * * * * * * Set the transmit data and start. INTTX0 interrupt routine Acc ←SC0BUF Read the receiving buffer. SC0BUF * * * * * * * * Set the next transmit data. X: Don’t care, −: No change

(2) Mode 1 (7-bit UART mode) 7-bit UART mode is selected by setting the serial channel mode register SC0MOD0<SM1:0> field to 01. In this mode a parity bit can be added. Use of a parity bit is enabled or disabled by the setting of the serial channel control register SC0CR<PE> bit; whether even parity or odd parity will be used is determined by the SC0CR<EVEN> setting when SC0CR<PE> is set to 1 (Enabled). Example: When transmitting data of the following form at, the control registers should be set as described below. Transmission direction (Transmission rate: 2400 bps at fSYS = 39.3216 MHz) * Clock state Clock gear 1/1 (f C) 7 6 5 4 3 210 PFFC ← X X − X − − X1 Set PF0 to function as the TXD0 pin. SC0MOD0 ← − 0 − − 0 101 Select 7-bit UART mode. SC0CR ← − 1 1 − − − 00 Add even parity. BR0CR ← 0 0 1 0 1 0 0 0 Set the transfer rate to 2400 bps. INTES0 ← X 1 0 0 − − − − Enable the INTTX0 interrupt and set it to interrupt level 4. SC0BUF ← * * * * * * * * Set data for transmission. X: Don’t care, −: No change (3) Mode 2 (8-bit UART mode) 8-bit UART mode is selected by setting SC0MOD0<SM1:0> to 10. In this mode a parity bit can be added (Use of a parity bit is enabled or disabled by the setting of SC0CR<PE>); whether even parity or odd parity will be used is determined by the SC0CR<EVEN> setting when SC0CR<PE> is set to 1 (Enabled). Example: When receiving data of the following forma t, the control registers should be set as described below. Transmission direction (Transmission rate: 9600 bps at fC = 39.3216 MHz) * Clock state Clock gear 1/1 (f C) Main settings 7 6 5 4 3 210 PFCR ← X X − − − − 0 − Set PF1 to function as the RXD0 pin. SC0MOD0 ← − 0 1 − 1 001 Enable receiving in 8-bit UART mode. SC0CR ← − 0 1 − − − 00 Add odd parity. BR0CR ← 0 0 0 1 1 0 0 0 Set the transfer rate to 9600 bps. INTES0 ← − − − − X 100 Enable the INTRX0 interrupt and set it to interrupt level 4. Interrupt processing Acc ( SC0CR AND 00011100 if Acc ( 0 then ERROR Check for errors. Acc ( SC0BUF Read the received data. X: Don’t care, (: No change Bit0 1 2 3 4 5 Even parity StopStart 6 Bit0 1 2 3 4 5 Odd parity StopStart 6

(4) Mode 3 (9-bit UART mode) 9-bit UART mode is selected by setting SC0MOD0<SM1:0> to 11. In this mode parity bit cannot be added. In the case of transmission the MSB (9th bit) is written to SC0MOD0<TB8>. In the case of receiving it is stored in SC0CR<RB8>. When the buffer is written and read, the MSB is read or written first, before the rest of the SC0BUF data. Wakeup function In 9-bit UART mode, the wakeup function for slave controllers is enabled by setting SC0MOD0<WU> to 1. The interrupt INTRX0 can only be generated when <RB8> = 1. Note: The TXD pin of each slave controller must be in open-drain output mode. Figure 3.9.29 Serial Link Using Wakeup Function TXD RXD Master TXD RXD Slave 1 TXD RXD Slave 2 TXD RXD Slave 3

1. Select 9-bit UART mode on the master and slave controllers. 2. Set the SC0MOD0<WU> bit on each slave controller to 1 to enable data receiving. 3. The master controller transmits data one fr ame at a time. Each frame includes an 8-bit select code which identifies a slave controller. The MSB (Bit8) of the data (<TB8>) is set to 1. 4. Each slave controller receives the above frame. Each controller checks the above select code against its own select code. The controller whose code matches clears its <WU> bit to 0. 5. The master controller transmits data to the specified slave controller (The controller whose SC0MOD0<WU> bit has been cleared to 0). The MSB (Bit8) of the data (<TB8>) is cleared to 0. 6. The other slave controllers (whose <WU> bits remain at 1) ignore the received data because their MSBs (Bit8 or <RB8>) are set to 0, disabling INTRX0 interrupts. The slave controller whose <WU> bit = 0 can also transmit to the master controller. In this way it can signal the master controller that the data transmission from the master controller has been completed. Start B i t 0 1 23456 Select code of slave controller

7 Stop 8

“1” Start B i t 0 1 23456 Data

7 Stop Bit8

“0”

Example: To link two slave controllers serially wi th the master controller using the internal clock fIO as the transfer clock. Since serial channels 0 and 1 operate in exactly the same way, channel 0 only is used for the purposes of this explanation.

• Setting the master controller Main 7 6 5 4 3 210 PFCR PFFC ← X X − X − − X1 Set PF0 and PF1 to function as the TXD0 and RXD0 pins respectively. INTES0 ← 1 1 0 0 1 1 0 1 Enable the INTTX0 interrupt and set it to interrupt level 4. Enable the INTRX0 interrupt and set it to interrupt level 5. SC0MOD0 ← 1 0 1 0 1 1 1 0 Set fIO as the transmission clock for 9-bit UART mode. SC0BUF ← 0 0 0 0 0 0 0 1 Set the select code for slave controller 1. INTTX0 interrupt SC0MOD0 SC0BUF ← * * * * * * * * Set data for transmission.
• Setting the slave controller Main 7 6 5 4 3 210 PFCR PFFC ← X X − X − − X1 Select PF1 and PF0 to function as the RXD and TXD pins respectively (Open-drain output). INTES0 ← 1 1 0 1 1 1 1 0 Enable INTRX0 and INTTX0. SC0MOD0 ← 0 0 1 1 1 1 1 0 Set <WU> to 1 in 9-bit UART transmission mode using f SYS as the transfer clock. INTRX0 interrupt Acc ← SC0BUF if Acc = select code TXD RXD Master TXD RXD Slave 1 TXD RXD Slave 2 Select code 00000001 Select code 00001010

3.9.5 Support for IrDA

SIO0 includes support for the IrDA 1.0 infrared data communication specification. 19H Figure 3.9.30 shows the block diagram. TMP92C820 Figure 3.9.30 Block Diagram (1) Modulation of the transmission data When the transmit data is 0, the modem outputs 1 to TXD0 pin with either 3/16 or 1/16 times for width of baud-rate. The pulse width is selected by the SIRCR<PLSEL>. When the transmit data is 1, the modem outputs 0. Figure 3.9.31 Transmission Example (2) Modulation of the receive data When the receive data is the effective width of pulse “1”, the modem outputs “0” to SIO0. Otherwise the modem outputs “1” to SIO0. The effective pulse width is selected by SIRCR<RXSEL>. Figure 3.9.32 Receiving Example Transmission data SIO0 IR modulator IR demodulator Receive data IR transmitter&LED IR receiver Modem IR transceiver module TXD0 RXD0 IR output IR input Start Transmission data Stop0 0 0010 1 1 TXD0 pin Start Data after modulation Stop1 1001 0 1 0 Receiving pulse <RXSEL> = “0” Receiving pulse <RXSEL> = “1”

(3) Data format The data format is fixed as follows: y Data length: 8 bits y Parity bits: None y Stop bits: 1 (4) SFRs 20H Figure 3.9.33 shows the control register SIRCR. Set the data SIRCR during SIO0 is stopping. The following example describes how to set this register: 1) SIO setting ; Set the SIO to UART mode. 2) LD (SIRCR), 07H ; Set the receive data pulse width to 16X. 3) LD (SIRCR), 37H ; TXEN, RXEN enable the transmission and receiving. 4) Start transmission and receiving for SIO0 ; The modem operates as follows: y SIO0 starts transmitting. y IR receiver starts receiving. (5) Notes The IrDA 1.0 specification is defined in 21H Table 3.9.4. 1. Making baud rate when using IrDA In baud rate during using IrDA, must set “01” to SC0MOD0<SC1:0> in SIO by using baud rate generator. TA0TRG, fIO, SCLK0 input can not using. 2. Output pulse width and baud rate generator during transmission IrDA As the IrDA 1.0 physical layer specification, the data transfer speed and infra-red pulse width is specified. Table 3.9.4 Baud Rate and Pulse Width Specifications Baud Rate Modulation Rate Tolerance (% of rate) Pulse Width (Minimum) Pulse Width (Typical) Pulse Width (Maximum) The pulse width is defined either baud rate TX 3/16 or 1.6 μs (1.6 μs is equal to 3/16 pulse width when baud rate is 115.2 kbps). The TMP92C820 has the function selects the pulse width of transmission either 3/16 or 1/16. But 1/16 pulse width can be selected when the baud rate is equal or less than 38.4 kbps.

As the same reason, + (16 − k)/16 division function in the baud rate generator of SIO0 can not be used to generate 115.2 kbps baud rate. Also when the 38.4 kbps and 1/16 pulse width, + (16 − k)/16 division function can not be used. Table 3.9.5 Baud Rate and Pulse Width for (16 − k)/16 Division Function Baud Rate Pulse Width ○: Can be used (16 − k)/16 division function ×: Can not be used (16 − k)/16 division function −: Can not be set to 1/16 pulse width 7 6 5 4 3 2 1 0 Bit symbol PLSEL RXSEL TXEN RXEN SIRWD3 SIRWD2 SIRWD1 SIRWD0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Select transmit pulse width 0: 3/16 1: 1/16 Receive data 0: “H” pulse 1: “L” pulse Transmit 0: Disable 1: Enable Receive 0: Disable 1: Enable Select receive pulse width Set effective pulse width for equal or more than 2x (Value + 1) + 100ns Can be set: 1 to 14 Can not be set: 0, 15 Select receive pulse width Formula: Effective pulse width ≥ 2x × (Value + 1) + 100ns x = 1/fSYS

0000 Can not be set

Equal to or more than 4x + 100 ns 0001 to 1110 Equal to or more than 30x + 100 ns

1111 Cannot be set

(Received input is ignored.) (Input from SIO is ignored.) Select transmit pulse width 0 3/16 1 1/16 Note: If a pulse width complying with the IrDA1.0 standard (1.6 μs min.) can be guaranteed with a low baud rate, setting this bit to “1” will result in result reduced power dissipation. Figure 3.9.33 IrDA Control Register SIRCR (1207H)

3.10 Serial Bus Interface (SBI)

The TMP92C820 has 1-channel serial bus interface which employs a clocked-synchronous 8-bit SIO mode and an I2C bus mode. It is called SBI0. The serial bus interface is connected to an external device through P91 (SDA) and P92 (SCL) in the I2C bus mode; and through P90 (SCK), P91 (SO), P92 (SI) in the clocked-synchronous 8-bit SIO mode. Each pin is specified as follows. P9ODE<P92ODE, P91ODE> P9CR<P92C, P91C, P90C> P9FC<P92F, P91F, P90F> I C Bus Mode 11 11X 11X Clocked Synchronous 8-Bit SIO Mode XX 011 010 011 010 (Note) X: Don’t care Note : When using SI input function and SCK input function, set P9FC<P92F,P90F> to “0” (Function setting).

3.10.1 Configuration

Figure 3.10.1 Serial Bus Interface 0 (SBI0) P90 (SCK) SIO clock control Divider I C bus clock sync. + control SBI0CR2/ SBI0SR SCL SCK Input/ output control SO SI SDA I2C0AR SBI0BR SBI0CR1 SBI0BR0, 1 Shift register Transfer control circuit Noise canceller φT Noise canceller I C bus data control SIO data control INTSBE0 interrupt request (Address/data) P91 (SO/SDA) P92 (SI/SCL) SBI0 control register 2/ SBI0 status register I C bus 0 address register SBI0 data buffer register SBI0 control register 1 SBI0 baud rate register 0, 1

3.10.2 Serial Bus Interface (SBI) Control

The following registers are used to control the serial bus interface and monitor the operation status.

• Serial bus interface 0 control register 1 (SBI0CR1)
• Serial bus interface 0 control register 2 (SBI0CR2)
• Serial bus interface 0 data buffer register (SBI0DBR)
• I2C bus 0 address register (I2C0AR)
• Serial bus interface 0 status register (SBI0SR)
• Serial bus interface 0 baud rate register 0 (SBI0BR0)
• Serial bus interface 0 baud rate register 1 (SBI0BR1) The above registers differ depending on a mode to be used. Refer to section 3.10.4 “I2C Bus Mode Control Register” and 3.10.7 “Clocked-synchronous 8-Bit SIO Mode Control”.

3.10.3 The Data Formats in the I 2C Bus Mode

The data formats in the I2C bus mode are shown below. (a) Addressing format (b) Addressing format (with restart) (c) Free data format (data transferred from master device to slave device) Figure 3.10.2 Data Format in the I2C Bus Mode S Slave address R W Data A C K A C K S Slave address R W Data A C K A C K P 8 bits 1 1 to 8 bits 1 8 bits 1 1 to 8 bits 1 1 1 or more 1 1 or more S Slave address R W Data A C K A C K Data A C K P 8 bits 1 1 to 8 bits 1 1 to 8 bits 1 1 1 or more S Data Data A C K A C K Data A C K P 8 bits 1 1 to 8 bits 1 1 to 8 bits 1 1 1 or more S: Start condition R/ W : Direction bit ACK: Acknowledge bit P: Stop condition

3.10.4 I 2C Bus Mode Control Register

The following registers are used to control and monitor the operation status when using the serial bus interface (SBI) in the I2C bus mode. Serial Bus Interface 0 Control Register 1 7 6 5 4 3 2 1 0 Bit symbol BC2 BC1 BC0 ACK SCK2 SCK1 SCK0/ SWRMON Read/Write W R/W W R/W After reset 0 0 0 0 0 0 0/1 (Note 3) Function Number of transferred bits (Note 1) Acknowl- edge mode specifica- tion 0: Not generate 1: Generate Internal serial clock selection and software reset monitor (Note 2) Internal serial clock selection <SCK2:0> at write 000 001 010 011 100 101 110 111 n = 5 n = 6 n = 7 n = 8 n = 9 n = 10 n = 11 Reserved − (Note 4) − (Note 4) − (Note 4) 75.8 kHz 38.5 kHz 19.4 kHz 9.73 kHz (Reserved) System clock: f SYS fSYS = 20 MHz (internal SCL output) fscl = [Hz] Software reset state monitor <SWRMON> at read

0 During software reset

1 Initial data

Acknowledge mode specification

0 Not generate clock pulse for acknowledge signal

1 Generate clock pulse for acknowledge signal

Number of bits transferred <ACK> = 0 <ACK> = 1 <BC2:0> Number of clock pulses Bits Number of clock pulses Bits 000 001 010 011 100 101 110 111 Note 1: Set the <BC2:0> to “000” before switching to a clocked-synchronous 8-bit SIO mode. Note 2: For the frequency of the SCL pin clock, see 3.10.5 (3) “Serial clock”. Note 3: Initial data of SCK0 is “0”, SWRMON is “1”. Note 4: This I2C bus circuit does not support Fast-mode, it supports the Standard mode only. Although the I 2C bus circuit itself allows the setting of a baud rate over 100kbps, the compliance with the I2C specification is not guaranteed in that case. Figure 3.10.3 Registers for the I2C Bus Mode fSYS n + 8 SBI0CR1 (1240H) Prohibit read- modify- write

Serial Bus Interface 0 Control Register 2 7 6 5 4 3 2 1 0 Bit symbol MST TRX BB PIN SBIM1 SBIM0 SWRST1 SWRST0 Read/Write W W (Note 1) W (Note 1) After reset 0 0 0 1 0 0 0 0 Function Master/ slave selection Transmitter/ receiver selection Start/stop condition generation Cancel INTSBE0 interrupt request Serial bus interface operating mode selection (Note 2) 00: Port mode 01: SIO mode 10: I C bus mode 11: (Reserved) Software reset generate write “10” and “01”, then an internal software reset signal is generated. Serial bus interface operating mode selection (Note 2)

00 Port mode (Serial bus interface output disabled)

01 Clocked-synchronous 8-bit SIO mode

11 (Reserved) INTSBE0 interrupt request 0 −

1 Cancel interrupt request

Start/stop condition generation

0 Generates the stop condition

1 Generates the start condition

Transmitter/receiver selection

0 Receiver

1 Transmitter

Note 1: Reading this register function as SBI0SR register. Note 2: Switch a mode to port mode after confirming that the bus is free. Switch a mode between I C bus mode and clocked-synchronous 8-bit SIO mode after confirming that input signals via port are high level. Figure 3.10.4 Registers for the I2C Bus Mode SBI0CR2 (1243H) Prohibit read- modify- write

Serial Bus Interface 0 Status Register 7 6 5 4 3 2 1 0 Bit symbol MST TRX BB PIN AL AAS AD0 LRB Read/Write R After reset 0 0 0 1 0 0 0 0 Function Master/ slave status monitor Transmitter/ receiver status monitor I C bus status monitor INTSBE0 interrupt request monitor Arbitration lost detection monitor 0: − 1: Detected Slave address match detection monitor 0: Undetected 1: Detected GENERAL CALL detection monitor 0: Undetected 1: Detected Last received bit monitor 0: “0” 1: “1” Last received bit monitor

0 Last received bit was “0”

1 Last received bit was “1”

GENERAL CALL detection monitor

0 Undetected

1 GENERAL CALL detected

Slave address match detection monitor

1 Slave address match or GENERAL

Arbitration lost detection monitor 0 −

1 Arbitration lost

INTSBE0 interrupt request monitor

0 Interrupt requested

1 Interrupt canceled

I C bus status monitor

0 Free

Transmitter/receiver status monitor Master/slave status monitor 0S l a v e 1M a s t e r Note: Writing in this register functions as SBI0CR2. Figure 3.10.5 Registers for the I2C Bus Mode SBI0SR (1243H) Prohibit read- modify- write

Serial Bus Interface 0 Baud Rate Register 0 7 6 5 4 3 2 1 0 Bit symbol − I 2 S B I 0 Read/Write W R/W After reset 0 0 Function Always write “0”. IDLE2 0: Stop 1: Run Operation during IDLE2 mode

0 Stop

1 Operation

Serial Bus Interface 0 Baud Rate Register 1 7 6 5 4 3 2 1 0 Bit symbol P4EN − Read/Write W W After reset 0 0 Function Internal clock 0: Stop 1: Operate Always write “0”. Baud rate clock control

1 Operate

Serial Bus Interface 0 Data Buffer Register 7 6 5 4 3 2 1 0 Bit symbol DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Read/Write R (Received)/W (Transfer) After reset Undefined Note 1: When writing transmitted data, start from the MSB (Bit7). Receiving data is placed from LSB (Bit0). Note 2: SBI0DBR can’t be read the written data. Therefore read-modify-write instruction (e.g., “BIT” instruction) is prohibitted. I2C Bus 0 Address Register 7 6 5 4 3 2 1 0 Bit symbol SA6 SA5 SA4 SA3 SA2 SA1 SA0 ALS Read/Write W After reset 0 0 0 0 0 0 0 0 Function Slave address selection for when device is operating as slave device Address recognition mode specification Address recognition mode specification

0 Slave address recognition

1 Non slave address recognition

Figure 3.10.6 Registers for the I2C Bus Mode SBI0BR0 (1244H) Prohibit read- modify- write SBI0BR1 (1245H) Prohibit read- modify- write SBI0DBR (1241H) Prohibit read- modify- write I2C0AR (1242H) Prohibit read- modify- write

3.10.5 Control in I 2C Bus Mode

(1) Acknowledge mode specification Set the SBI0CR1<ACK> to “1” for operation in the acknowledge mode. The TMP92C820 generates an additional clock pulse for an acknowledge signal when operating in master mode. In the transmitter mode during the clock pulse cycle, the SDA pin is released in order to receive the acknowledge signal from the receiver. In the receiver mode during the clock pulse cycle, the SDA pin is set to the low in order to generate the acknowledge signal. Clear the <ACK> to “0” for operation in the non-acknowledge mode. The TMP92C820 does not generate a clock pulse for the acknowledge signal when operating in the master mode. (2) Number of transfer bits Since the SBI0CR1<BC2:0> is cleared to “000” on start up, a slave address and direction bit transmissions are executed in 8 bits. Other than these, the <BC2:0> retains a specified value. (3) Serial clock 1. Clock source The SBI0CR1<SCK2:0> is used to specify the maximum transfer frequency for output on the SCL pin in the master mode. Set the baud rates, which have been calculated according to the formula below, to meet the specifications of the I 2C bus, such as the smallest pulse width of tLOW. SBI0CR1<SCK2:0> n 000 5 001 6 010 7 011 8 100 9 101 10 110 11 Figure 3.10.7 Clock Source tHIGH tLOW 1/fscl tLOW = 2 n − 1 /fSBI tHIGH = 2 n−1 /fSBI + 8/fSBI fscl = 1/(tLOW + tHIGH) = fSBI n + 8 Note: f SBI is the clock fSYS.

1. Clock synchronization In the I2C bus mode, in order to wired-AND a bus, a master device which pulls down a clock pin to the low level, in the first place, invalidate a clock pulse of another master device which generates a high-level clock pulse. The master device with a high-level clock pulse needs to detect the situation and implement the following procedure. This device has a clock synchronization function which allows normal data transfer even when more than one master exists on the bus. The following example explains the clock synchronization procedures used when there are two masters present on the bus. Figure 3.10.8 Clock Synchronization When master A pulls the internal SCL output to the low level at point “a”, the bus’s SCL pin goes to the low level. After detecting this, master B resets a counter of high-level width of an own clock pulse and sets the internal SCL output the low level. Master A finishes counting low-level width of an own clock pulse at point “b” and sets the internal SCL output to the high level. Since master B is holding the bus’s SCL pin the low level, master A waits for counting high-level width of an own clock pulse. After master B has finished counting low-level width of an own clock pulse at point “c” and master A detects the SCL pin of the bus at the high level, and starts counting high level of an own clock pulse. The clock pulse on the bus is determined by the master device with the shortest high-level width and the master device with the longest low-level width from among those master devices connected to the bus. (4) Slave address and address re cognition mode specification When this device is to be used as a slave device, set the slave address <SA6:0> and <ALS> in I2C0AR. Clear the <ALS> to “0” for the address recognition mode. (5) Master/slave selection To operate this device as a master device set the SBI0CR2<MST> to “1”. To operate it as a slave device clear the SBI0CR2<MST> to “0”. The <MST> is cleared to “0” in hardware when a stop condition is detected on the bus or when arbitration is lost. Start couting high-level width of a clock pulse Internal SCL output (Master A) Internal SCL output (Master B) SCL pin Wait counting high-level width of a clock pulse Reset a counter of high-level width of a clock pulse ab c

(8) Interrupt service requests and interrupt cancellation When a serial bus interface interrupt request 0 by transfer of the slave address or the data (INTSBE0) is generated, the SBI0SR<PIN> is cleared to “0”. The SCL pin is pulled down to the low-level while the <PIN> = “0”. The <PIN> is cleared to “0” when a single word of data is transmitted or received. Either writing data to or reading data from SBI0DBR sets the <PIN> to “1”. The time from the <PIN> being set to “1” until the release of the SCL pin is tLOW. In the address recognition mode (e.g., when <ALS> = “0”), the <PIN> is cleared to “0” when the slave address matches the value set in I2C0AR or when a GENERAL CALL is received (All 8-bit data are “0” after a start condition). Although the SBI0CR2<PIN> can be set to “1” by a program, writing “0” to the SBI0CR2<PIN> does not clear it to “0”. (9) Serial bus interface operation mode selection The SBI0CR2<SBIM1:0> is used to specify the serial bus interface operation mode. Set the SBI0CR2<SBIM1:0> to “10” when the device is to be used in I 2C bus mode after confirming pin condition of serial bus interface to “H”. Switch a mode to port after confirming a bus is free. (10) Arbitration lost detection monitor Since more than one master device can exist simultaneously on the bus in I2C bus mode, a bus arbitration procedure has been implemented in order to guarantee the integrity of transferred data. Data on the SDA pin is used for I2C bus arbitration. The following example illustrates the bus arbitration procedure when there are two master devices on the bus. Master A and master B output the same data until point “a”. After master A outputs “L” and master B, “H”, the SDA pin of the bus is wire-AND and the SDA pin is pulled down to the low level by master A. When the SCL pin of the bus is pulled up at point “b”, the slave device reads the data on the SDA pin, that is, data in master A. Data transmitted from master B becomes invalid. The master B state is known as “ARBITRATION LOST”. Master B device which loses arbitration releases the internal SDA output in order not to affect data transmitted from other masters with arbitration. When more than one master sends the same data at the first word, arbitration occurs continuously after the second word. Figure 3.10.11 Arbitration Lost Internal SDA output becomes “1” after arbitration has been lost. SCL pin Internal SDA output (Master A) Internal SDA output (Master B) SDA pin ab

This device compares the levels on the bus’s SDA pin with those of the internal SDA output on the rising edge of the SCL pin. If the levels do not match, arbitration is lost and the SBI0SR<AL> is set to “1”. When the <AL> is set to “1”, the SBI0SR<MST,TRX> are cleared to “00” and the mode is switched to a slave receiver mode. Thus, clock output is stopped in data transfer after setting <AL> = “1”. The <AL> is cleared to “0” when data is written to or read from SBI0DBR or when data is written to SBI0CR2. Figure 3.10.12 Example of a Master Device B (D7A = D7B, D6A = D6B) (11) Slave address match detection monitor The SBI0SR<AAS> is set to “1” in the slave mode, in the address recognition mode (e.g., when the I2C0AR<ALS> = “0”), when a GENERAL CALL is received, or when a slave address matches the value set in I2C0AR. When the I2C0AR<ALS> = “1”, the SBI0SR<AAS> is set to “1” after the first word of data has been received. The SBI0SR<AAS> is cleared to “0” when data is written to or read from the data buffer register SBI0DBR. (12) GENERAL CALL detection monitor The SBI0SR<AD0> is set to “1” in the slave mode, when a GENERAL CALL is received (all 8-bit received data is “0”, after a start condition). The SBI0SR<AD0> is cleared to “0” when a start condition or stop condition is detected on the bus. (13) Last received bit monitor The value on the SDA pin detected on the rising edge of the SCL pin is stored in the SBI0SR<LRB>. In the acknowledge mode, immediately after an INTSBE0 interrupt request has been generated, an acknowledge signal is read by reading the contents of the SBI0SR<LRB>. <AL> <MST> <TRX> Stop the clock pulse Keep internal SDA output to high level as losing arbitration Accessed to SBI0DBR or SBI0CR2 Internal SCL output Internal SDA output Internal SDA output Internal SCL output Master A Master B 2 3456789 1 2 34 D7A D6B D5A D4A D3A D2A D1A D0A D7A’ D6A’ D5A’ D4A’ 1 2 3 4 D7B D6A

(14) Software reset function The software reset function is used to initialize the SBI circuit, when SBI is rocked by external noises, etc. An internal reset signal pulse can be generated by setting SBI0CR2<SWRST1:0> to “10” and “01”. This initializes the SBI circuit internally. All command (except SBI0CR2<SBIM1:0>) registers and status registers are initialized as well. The SBI0CR1<SWRMON> is automatically set to “1” after the SBI circuit has been initialized. (15) Serial bus interface data buffer register (SBI0DBR) The received data can be read and the transferred data can be written by reading or writing the SBI0DBR. When the start condition has been generated in the master mode, the slave address and the direction bit are set in this register. (16) I2C bus address register (I2C0AR) I2C0AR<SA6:0> is used to set the slave address when this device functions as a slave device. The slave address output from the master device is recognized by setting I2C0AR<ALS> is set to “0”. The data format is the addressing format. When the slave address in not recognized at the <ALS> is set to “1”, the data format is the free data format. (17) Baud rate register (SBI0BR1) Write “1” to the SBI0BR1<P4EN> before operation commences. (18) Setting register for IDLE2 mode operation (SBI0BR0) The setting of SBI0BR0<I2SBI0> determines whether the device is operating or is stopped in IDLE2 mode. Therefore, setting <I2SBI0> is necessary before the HALT instruction is executed.

3.10.6 Data Transfer in I 2C Bus Mode

(1) Device initialization Set the SBI0BR1<P4EN> and the SBI0CR1<ACK, SCK2:0>. Set the SBI0BR1<P4EN> to “1” and clear bits 7 to 5 and 3 of the SBI0CR1 to “0”. Set a slave address in I2C0AR<SA6:0> and the I2C0AR<ALS> (<ALS> = “0” when an addressing format.) For specifying the default setting to a slave receiver mode, clear “000” to the <MST, TRX, BB>, set “1” to the <PIN>, set “10” to the <SBIM1:0> and set “00” to the <SWRST1:0>. (2) Start condition generation and slave address generation 1. Master mode In the master mode the start condition and the slave address are generated as follows. Check a bus free status (when <BB> = “0”). Set the SBI0CR1<ACK> to “1” (Acknowledge mode) and specify a slave address and a direction bit to be transmitted to the SBI0DBR. When the <BB> is ”0”, the start condition is generated by writing “1111” to the SBI0CR2<MST, TRX, BB, PIN>. Subsequently to the start condition, 9 clocks are output from the SCL pin. While 8 clocks are output, the slave address and the direction bit which are set to the SBI0DBR. At the 9th clock pulse the SDA pin is released and the acknowledge signal is received from the slave device. An INTSBE0 interrupt request occurs on the falling edge of the 9th clock pulse. The <PIN> is cleared to “0”. In the master mode the SCL pin is pulled down to the low level while the <PIN> is “0”. When an INTSBE0 interrupt request occurs, the value of <TRX> is changed according to the direction bit setting only if the slave device returns an acknowledge signal. 2. Slave mode In the slave mode the start condition and the slave address are received. After the start condition has been received from the master device, while 8 clocks are output from the SCL pin, the slave address and the direction bit which are output from the master device are received. When a GENERAL CALL or an address matching the slave address set in I2C0AR is received, the SDA pin is pulled down to the low level at the 9th clock pulse and an acknowledge signal is output. An INTSBE0 interrupt request occurs on the falling edge of the 9th clock pulse. The <PIN> is cleared to “0”. In the slave mode the SCL pin is pulled down to the low-level while the <PIN> = “0”. When an interrupt request occurs, the value of <TRX> is changed according to the direction bit setting only if the slave device returns an acknowledge signal.

1. When the <MST> is “0” (Slave mode) In the slave mode, this device operates either in normal slave mode or in slave mode after losing arbitration. In the slave mode, an INTSBE0 interrupt request occurs when this device receives a slave address or a GENERAL CALL from the master device, or when a GENERAL CALL is received and data transfer is complete, or after matching a received slave address. In the master mode, this device operates in a slave mode if it is losing arbitration. An INTSBE0 interrupt request occurs when word data transfer terminates after losing arbitration. When an INTSBE0 interrupt request occurs, the <PIN> is cleared to “0”, and the SCL pin is pulled down to the low level. Either reading data to or writing data from the SBI0DBR, or setting the <PIN> to “1” releases the SCL pin after taking tLOW time. Check the SBI0SR<AL>, <TRX>, <AAS>, and <AD0> and implements processes according to conditions listed in the next table.

Table 3.10.1 Operation in the Slave Mode <TRX> <AL> <AAS> <AD0> Conditions Process 1 1 0 This device loses arbitration when transmitting a slave address and receives a slave address of which the value of the direction bit sent from another master is “1”. 1 0 In the slave receiver mode, this device receives a slave address of which the value of the direction bit sent from the master is “1”. Set the number of bits in 1 word to the <BC2:0> and write the transmitted data to the SBI0DBR. 0 0 In the slave transmitter mode, 1-word data is transmitted. Check the <LRB>. If the <LRB> is set to “1”, set the <PIN> to “1” since the receiver does not request the next data. Then, clear the <TRX> to “0” to release the bus. If the <LRB> is cleared to “0”, set the number of bits in a word to the <BC2:0> and write transmitted data to the SBI0DBR since the receiver requests next data. 1 1/0 This device loses arbitration when transmitting a slave address and receives a GENERAL CALL or slave address of which the value of the direction bit sent from another master is “0”. 0 0 This device loses arbitration when transmitting a slave address or data and terminates transferring word data. 1 1/0 In the slave receiver mode, this device receives a GENERAL CALL or slave address of which the value of the direction bit sent from the master is “0”. Read the SBI0DBR for setting the <PIN> to “1” (Reading dummy data) or set the <PIN> to “1”. 0 1/0 In the slave receiver mode, the device terminates receiving 1-word data. Set the number of bits in a word to the <BC2:0> and read received data from the SBI0DBR.

(5) Restart Restart is used during data transfer between a master device and a slave device to change the data transfer direction. The following description explains how to restart when this device is in the master mode. Clear the SBI0CR2<MST, TRX, BB> to “000” and set the SBI0CR2<PIN> to “1” to release the bus. The SDA line remains the high level and the SCL pin is released. Since a stop condition is not generated on the bus, other devices assume the bus to be in a busy state. Check the SBI0SR<BB> until it becomes “0” to check that the SCL pin of this device is released. Check the <LRB> until it becomes 1 to check that the SCL line on a bus is not pulled down to the low level by other devices. After confirming that the bus stays in a free state, generate a start condition with procedure described in 3.10.6 (2). In order to meet setup time when restarting, take at least 4.7 μs of waiting time by software from the time of restarting to confirm that the bus is free until the time to generate the start condition. Figure 3.10.19 Timing Diagram when Restarting Start condition <LRB> SCL line Internal SCL output SDA line <PIN> 4.7 μs (Min) <BB>

3.10.7 Clocked-synchronous 8-Bit SIO Mode Control

The following registers are used to control and monitor the operation status when the serial bus interface (SBI) is being operated in clocked-synchronous 8-bit SIO mode. Serial Bus Interface 0 Control Register 1 7 6 5 4 3 2 1 0 Bit symbol SIOS SIOINH SIOM1 SIOM0 SCK2 SCK1 SCK0 Read/Write W W W After reset 0 0 0 0 0 0 0 Function Transfer start 0: Stop 1: Start Continue/ abort transfer 0: Continue transfer 1: Abort transfer Transfer mode select 00: Transmit mode 01: (Reserved) 10: Transmit/Receive mode 11: Receive mode Serial clock selection and reset monitor Serial clock selection <SCK2:0> at write 000 001 010 011 100 101 110 n = 4 n = 5 n = 6 n = 7 n = 8 n = 9 n = 10

1.25 MHz

78.1 kHz 39.1 kHz 19.5 kHz System clock: f SYS fSYS = 20 MHz (output to SCK pin) fscl = [Hz] 111 − External clock: SCK0 Transfer mode selection 00 8-bit transmit mode 01 (Reserved) 10 8-bit transmit/receive mode 11 8-bit receive mode Continue/abort transfer

0 Continue transfer

1 Abort transfer (Automatically cleared after transfer

aborted) Indicate transfer start/stop Note: Set the transfer mode and the serial clock a fter setting <SIOS> to “0” and <SIOINH> to “1”. Serial Bus Interface 0 Data Buffer Register 7 6 5 4 3 2 1 0 Bit symbol DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Read/Write R (Receiver)/W (Transfer) After reset Undefined Figure 3.10.20 Register for the SIO Mode fSYS n SBI0CR1 (1240H) Prohibit read- modify- write SBI0DBR (1241H) Prohibit read- modify-write

Serial Bus Interface 0 Control Register 2 7 6 5 4 3 2 1 0 Bit symbol SBIM1 SBIM0 − − Read/Write W W W After reset 0 0 0 0 Function Serial bus interface operation mode selection 00: Port mode 01: SIO mode 10: I C bus mode 11: (Reserved) (Note 2) (Note 2) Serial bus interface operation mode selection 11 (Reserved) Serial Bus Interface 0 Status Register 7 6 5 4 3 2 1 0 Bit symbol SIOF SEF Read/Write R After reset 0 0 Function Serial transfer operation status monitor Shift operation status monitor Serial transfer operating status monitor Shift operation status monitor

0 Transfer terminated 0 Shift operation terminated

1 Transfer in progress 1 Shift operation in progress

Serial Bus Interface 0 Baud Rate Register 0 7 6 5 4 3 2 1 0 Bit symbol − − Read/Write W R/W After reset 0 0 Function Always write “0”. Always write “0”. Note: Clocked-synchronous mode cannot operate in IDLE2 mode. Serial Bus Interface 0 Baud Rate Register 1 7 6 5 4 3 2 1 0 Bit symbol P4EN − Read/Write W W After reset 0 0 Function Internal clock 0: Stop 1: Operate Always write “0”. Baud rate clock control Figure 3.10.21 Registers for the SIO Mode Note 1: Set the SBI0CR1<BC2:0> “000” before switching to a clocked-synchronous 8-bit SIO mode. Note 2: Please always write “00” to SBICR2<1:0>. SBI0CR2 (1243H) Prohibit read- modify- write SBI0SR (1243H) SBI0BR0 (1244H) Prohibit read- modify- write SBI0BR1 (1245H) Prohibit read- modify- write

1. Shift edge Data is transmitted on the leading edge of the clock and received on the trailing edge. (a) Leading edge shift Data is shifted on the leading edge of the serial clock (on the falling edge of the SCK pin input/output). (b) Trailing edge shift Data is shifted on the trailing edge of the serial clock (on the rising edge of the SCK pin input/output). Figure 3.10.24 Shift Edge SCK pin output SO pin output Bit0 Bit1 Bit7 (a) Leading edge SCK pin SI pin (b) Trailing edge *: Don’t care Bit2 Bit3 Bit4 Bit5 Bit6 Bit0 Bit1 Bit7 Bit2 Bit3 Bit4 Bit5 Bit6

(2) Transfer modes The SBI0CR1<SIOM1:0> is used to select a transmit, receive or transmit/receive mode. 1. 8-bit transmit mode Set a control register to a transmit mode and write transmission data to the SBI0DBR. After the transmit data has been written, set the SBI0CR1<SIOS> to “1” to start data transfer. The transmitted data is transferred from the SBI0DBR to the shift register and output, starting with the least significant bit (LSB), via the SO pin and synchronized with the serial clock. When the transmission data has been transferred to the shift register, the SBI0DBR becomes empty. The INTSBE0 (Buffer empty) interrupt request is generated to request new data. When the internal clock is used, the serial clock will stop and the automatic wait function will be initiated if new data is not loaded to the data buffer register after the specified 8-bit data is transmitted. When new transmission data is written, the automatic wait function is canceled. When the external clock is used, data should be written to the SBI0DBR before new data is shifted. The transfer speed is determined by the maximum delay time between the time when an interrupt request is generated and the time when data is written to the SBI0DBR by the interrupt service program. When the transmit is started, after the SBI0SR<SIOF> goes “1” output from the SO pin holds final bit of the last data until falling edge of the SCK. Data transmission ends when the <SIOS> is cleared to “0” by the INTSBE0 interrupt service program or when the <SIOINH> is set to “1”. When the <SIOS> is cleared to “0”, the transmitted mode ends when all data is output. In order to confirm whether data is being transmitted properly by the program, the <SIOF> (Bit3 of the SBI0SR) to be sensed. The SBI0SR<SIOF> is cleared to “0” when transmission has been completed. When the <SIOINH> is set to “1”, transmitting data stops. The <SIOF> turns “0”. When the external clock is used, it is also necessary to clear the <SIOS> to “0” before new data is shifted; otherwise, dummy data is transmitted and operation ends.

Figure 3.10.25 Transfer Mode Example: Program to stop data transmission (when an external clock is used) STEST1: BIT 2, (SBI0SR) ; If <SEF> = 1 then loop JR NZ, STEST1 STEST2: BIT 0, (P9) ; If SCK0 = 0 then loop JR Z, STEST2 LD (SBI0CR1), 00000111B ; <SIOS> ← 0 <SIOS> (b) External clock Clear <SIOS> <SIOF> <SEF> SCK pin (Input) Write transmitted data SO pin INTSBE0 interrupt request SBI0DBR b b7 * <SIOS> (a) Internal clock a2 a1 a 4a3 a 6a5 b0a7 b2b1 b4b3 b6b5a0 Clear <SIOS> <SIOF> <SEF> SCK pin (Output) a Write transmitted data SO pin INTSBE0 interrupt request SBI0DBR b7 * a2 a1 a 4a3 a 6a5 b0a7 b2b1 b4b3 b6b5a0 b a

Figure 3.10.26 Transmitted Data Hold Time at End of Transmission 2. 8-bit receive mode Set the control register to receive mode and set the SBI0CR1<SIOS> to “1” for switching to receive mode. Data is received into the shift register via the SI pin and synchronized with the serial clock, starting from the least significant bit (LSB). When the 8-bit data is received, the data is transferred from the shift register to the SBI0DBR. The INTSBE0 (Buffer full) interrupt request is generated to request that the received data be read. The data is then read from the SBI0DBR by the interrupt service program. When the internal clock is used, the serial clock will stop and the automatic wait function will be in effect until the received data is read from the SBI0DBR. When the external clock is used, since shift operation is synchronized with an external clock pulse, the received data should be read from the SBI0DBR before the next serial clock pulse is input. If the received data is not read, further data to be received is canceled. The maximum transfer speed when an external clock is used is determined by the delay time between the time when an interrupt request is generated and the time when the received data is read. Receiving of data ends when the <SIOS> is cleared to “0” by the INTSBE0 interrupt service program or when the <SIOINH> is set to “1”. If <SIOS> is cleared to “0”, received data is transferred to the SBI0DBR in complete blocks. The received mode ends when the transfer is complete. In order to confirm whether data is being received properly by the program, the SBI0SR<SIOF> to be sensed. The <SIOF> is cleared to “0” when receiving is complete. When it is confirmed that receiving has been completed, the last data is read. When the <SIOINH> is set to “1”, data receiving stops. The <SIOF> is cleared to “0”. (The received data becomes invalid, therefore no need to read it.) Note: When the transfer mode is changed, the contents of the SBI0DBR will be lost. If the mode must be changed, conclude data receiving by clearing the <SIOS> to “0”, read the last data, then change the mode. SCK pin Bit7 Bit6 <SIOF> SO pin tSODH = 3.5/fSYS [s] (Min)

Figure 3.10.27 Receiver Mode (Example: Internal clock) 3. 8-bit transmit/receive mode Set a control register to a transmit/receive mode and write data to the SBI0DBR. After the data is written, set the SBI0CR<SIOS> to “1” to start transmitting/receiving. When data is transmitted, the data is output from the SO pin, starting from the least significant bit (LSB) and synchronized with the leading edge of the serial clock signal. When data is received, the data is input via the SI pin on the trailing edge of the serial clock signal. 8-bit data is transferred from the shift register to the SBI0DBR and the INTSBE0 interrupt request is generated. The interrupt service program reads the received data from the data buffer register and writes the data which is to be transmitted. The SBI0DBR is used for both transmitting and receiving. Transmitted data should always be written after received data is read. When the internal clock is used, the automatic wait function will be in effect until the received data is read and the next data is written. When the external clock is used, since the shift operation is synchronized with the external clock, the received data is read and transmitted data is written before a new shift operation is executed. The maximum transfer speed when the external clock is used is determined by the delay time between the time when an interrupt request is generated and the time at which received data is read and transmitted data is written. When the transmit is started, after the SBI0SR<SIOF> goes “1” output from the SO pin holds final bit of the last data until falling edge of the SCK. Transmitting/receiving data ends when the <SIOS> is cleared to “0” by the INTSBE0 interrupt service program or when the SBI0CR1<SIOINH> is set to “1”. When the <SIOS> is cleared to “0”, received data is transferred to the SBI0DBR in complete blocks. The transmit/receive mode ends when the transfer is complete. In order to confirm whether data is being transmitted/received properly by the program, set the SBI0SR to be sensed. The <SIOF> is set to “0” when transmitting/receiving is completed. When the <SIOINH> is set to “1”, data transmitting/receiving stops. The <SIOF> is then cleared to “0”. Note: When the transfer mode is changed, the contents of the SBI0DBR will be lost. If the mode must be changed, conclude data transmitting/receiving by clearing the <SIOS> to “0”, read the last data, then change the transfer mode. b <SIOS> a2a1 a4a3 a6a5 b0a7 b2b1 b4 b3 b 6 b5 a0 Clear <SIOS> <SIOF> <SEF> SCK pin (Output) a Read receiver data SI pin INTSBE0 interrupt request SBI0DBR Read receiver data

3.11 Analog/Digital Converter

The TMP92C820 incorporates a 10-bit successive approximation-type analog/digital converter (AD converter) with 5-channel analog input. 0H Figure 3.11.1 is a block diagram of the AD converter. The 5-channel analog input pins (AN0 to AN4) are shared with the input-only port (Port G) so they can be used as an input port. Note: When IDLE2, IDLE1 or STOP mode is selected , as to reduce the power, with some timings the system may enter a standby mode even though the internal comparator is still enabled. Therefore be sure to check that AD converter operations are halted before a HALT instruction is executed. Figure 3.11.1 Block Diagram of AD Converter Internal data bus AD mode control register 0 ADMOD0 AD mode control register 1, 2 ADMOD1, ADMOD2 <ADCH3:0> <VREFON> <ADTRGE> AD Converter control circuit Scan Repeat Interrupt Busy End Start ADTRG AD Conversion result register ADREG0L to ADREG4L ADREG0H to ADREG4H DA converter Sample and hold Multi- plexer Decoder Channel select AN4 (PG4) AN3/ADTRG (PG3) AN2 (PG2) AN1 (PG1) AN0 (PG0) VREFH VREFL INTAD interrupt Analog input Comparator

3.11.1 Analog/Digital Converter Registers

The AD converter is controlled by the three AD mode control registers: ADMOD0, ADMOD1 and ADMOD2. The five AD conversion data result registers (ADREG0H/L to ADREG4H/L) store the results of AD conversion. 1H Figure 3.11.2 shows the registers related to the AD converter. AD Mode Control Register 0 7 6 5 4 3 2 1 0 Bit symbol EOCF ADBF − − ITM0 REPEAT SCAN ADS Read/Write R R/W After reset 0 0 0 0 0 0 0 0 Function AD conversion end flag 0: Conversion in progress 1: Conversion complete AD conversion busy flag 0: Conversion stopped 1: Conversion in progress Always write “0”. Always write “0”. Interrupt specification in conversion channel fixed repeat mode 0: Every conversion 1: Every fourth conversion Repeat mode specification 0: Single conversion 1: Repeat conversion mode Scan mode specification 0: Conversion channel fixed mode 1: Conversion channel scan mode AD conversion start 0: Don’t care 1: Start conversion Always 0 when read AD conversion start

0 Don’t care

1 Start AD conversion

Note: Always read as 0. AD scan mode setting

0 AD conversion channel fixed mode

1 AD conversion channel scan mode

0 AD single conversion mode

1 AD repeat conversion mode

Specify AD conversion interrupt for channel fixed repeat conversion mode Channel fixed repeat conversion mode 0 Generates interrupt every conversion. 1 Generates interrupt every fourth conversion. AD conversion busy flag

0 AD conversion stopped

1 AD conversion in progress

0 Before or during AD conversion

1 AD conversion complete

Figure 3.11.2 AD Converter Related Register ADMOD0 (12B8H)

AD Mode Control Register 1 7 6 5 4 3 2 1 0 Bit symbol VREFON I2AD − − − ADCH2 ADCH1 ADCH0 Read/Write R/W R/W R/W After reset 0 0 0 0 0 0 0 0 Function VREF application 0: OFF 1: ON IDLE2 0: Stop 1: Operate Always write “0”. Always write “0”. Always write “0”. Analog input channel selection Analog input channel selection <SCAN> <ADCH2:0> Channel fixed Channel scanned

000 AN0 AN0

001 AN1 AN0 → AN1

010 AN2 AN0 → AN1 → AN2

011 (Note) AN3 AN0 → AN1 → AN2 → AN3 100 (Note) AN4 AN0 → AN1 → AN2 → AN3 → AN4 IDLE2 control

0 Stopped

1 In operation

Control of application of reference voltage to AD converter 0O F F 1O N Before starting conversion (before writing 1 to ADMOD0<ADS>), set the <VREFON> bit to 1. AD Mode Control Register 2 7 6 5 4 3 2 1 0 B i t s y m b o l A D T R G E Read/Write R/W After reset 0 Function AD external trigger start control 0: Disable 1: Enable AD conversion start control by external trigger ( ADTRG input) Note: As pin AN3 also function as the ADTRG input pin, do not set <ADCH2:0> = “011, 100” when using ADTRG with <ADTRGE> set to “1”. Figure 3.11.3 AD Converter Related Register ADMOD1 (12B9H) ADMOD2 (12BAH)

AD Conversion Result Register 0 Low 7 6 5 4 3 2 1 0 Bit symbol ADR01 ADR00 ADR0RF Read/Write R R After reset Undefined 0 Function Stores lower 2 bits of AD conversion result. AD conversion data storage flag 1: Conver- sion result stored AD Conversion Result Register 0 High 7 6 5 4 3 2 1 0 Bit symbol ADR09 ADR08 ADR07 ADR06 ADR05 ADR04 ADR03 ADR02 Read/Write R After reset Undefined Function Stores upper eight bi ts AD conversion result. AD Conversion Result Register 1 Low 7 6 5 4 3 2 1 0 Bit symbol ADR11 ADR10 ADR1RF Read/Write R R After reset Undefined 0 Function Stores lower 2 bits of AD conversion result. AD conversion result flag 1: Conver- sion result stored AD Conversion Result Register 1 High 7 6 5 4 3 2 1 0 Bit symbol ADR19 ADR18 ADR17 ADR16 ADR15 ADR14 ADR13 ADR12 Read/Write R After reset Undefined Function Stores upper eight bits of AD conversion result. 9 8 76543210 Channel x conversion result 7 6 543210 76543 2 1 0 Figure 3.11.4 AD Converter Related Registers ADREGxH ADREGxL

• Bits 5 to 1 are always read as 1.
• Bit0 is the AD conversion data storage flag <ADRxRF>. When the AD conversion result is stored, the flag is set to 1. When either of the registers (ADREGxH, ADREGxL) is read, the flag is cleared to 0. ADREG0L (12A0H) ADREG0H (12A1H) ADREG1L (12A2H) ADREG1H (12A3H)

AD Conversion Result Register 2 Low 7 6 5 4 3 2 1 0 Bit symbol ADR21 ADR20 ADR2RF Read/Write R R After reset Undefined 0 Function Stores lower 2 bits of AD conversion result. AD conversion data storage flag 1: Conver- sion result stored AD Conversion Result Register 2 High 7 6 5 4 3 2 1 0 Bit symbol ADR29 ADR28 ADR27 ADR26 ADR25 ADR24 ADR23 ADR22 Read/Write R After reset Undefined Function Stores upper eight bits of AD conversion result. AD Conversion Result Register 3 Low 7 6 5 4 3 2 1 0 Bit symbol ADR31 ADR30 ADR3RF Read/Write R R After reset Undefined 0 Function Stores lower 2 bits of AD conversion result. AD conversion data storage flag 1: Conver- sion result stored AD Conversion Result Register 3 High 7 6 5 4 3 2 1 0 Bit symbol ADR39 ADR38 ADR37 ADR36 ADR35 ADR34 ADR33 ADR32 Read/Write R After reset Undefined Function Stores upper eight bits of AD conversion result. 9 8 76543210 Channel x conversion result 7 6 543210 76543 2 1 0 Figure 3.11.5 AD Converter Related Registers ADREGxH ADREGxL

• Bits 5 to 1 are always read as 1.
• Bit0 is the AD conversion data storage flag <ADRxRF>. When the AD conversion result is stored, the flag is set to 1. When either of the registers (ADREGxH, ADREGxL) is read, the flag is cleared to 0. ADREG2L (12A4H) ADREG2H (12A5H) ADREG3L (12A6H) ADREG3H (12A7H)

AD Conversion Result Register 4 Low 7 6 5 4 3 2 1 0 Bit symbol ADR41 ADR40 ADR4RF Read/Write R R After reset Undefined 0 Function Stores lower 2 bits of AD conversion result. AD conversion data storage flag 1: Conver- sion result stored AD Conversion Result Register 4 High 7 6 5 4 3 2 1 0 Bit symbol ADR49 ADR48 ADR47 ADR46 ADR45 ADR44 ADR43 ADR42 Read/Write R After reset Undefined Function Stores upper eight bits of AD conversion result. 9 8 76543210 Channel x conversion result 7 6 543210 76543 2 1 0 Figure 3.11.6 AD Converter Related Registers ADREGxH ADREGxL

• Bits 5 to 1 are always read as 1.
• Bit0 is the AD conversion data storage flag <ADRxRF>. When the AD conversion result is stored, the flag is set to 1. When either of the registers (ADREGxH, ADREGxL) is read, the flag is cleared to 0. ADREG4L (12A8H) ADREG4H (12A9H)

3.11.2 Description of Operation

(1) Analog reference voltage A high-level analog reference voltage is applied to the VREFH pin; a low-level analog reference voltage is applied to the VREFL pin. To perform AD conversion, the reference voltage, the difference between VREFH and VREFL, is divided by 1024 using string resistance. The result of the division is then compared with the analog input voltage. To turn off the switch between VREFH and VREFL, write a 0 to ADMOD1 <VREFON> in AD mode control register 1. To start AD conversion in the OFF state, first write a 1 to ADMOD1<VREFON>, wait 3 μs until the internal reference voltage stabilizes (This is not related to fc.), then set ADMOD0<ADS> to 1. (2) Analog input channel selection The analog input channel selection varies depends on the operation mode of the AD converter.

• In analog input channel fixed mode (ADMOD0<SCAN> = 0) Setting ADMOD1<ADCH2:0> selects one of the input pins AN0 to AN4 as the input channel.
• In analog input channel scan mode (ADMOD0<SCAN> = 1) Setting ADMOD1<ADCH2:0> selects one of the five scan modes. 2H Table 3.11.1 illustrates analog input channel selection in each operation mode. On a reset, ADMOD0<SCAN> is set to 0 and ADMOD1<ADCH2:0> is initialized to 000. Thus pin AN0 is selected as the fixed input channel. Pins not used as analog input channels can be used as standard input port pins. Table 3.11.1 Analog Input Channel Selection <ADCH2:0> Channel Fixed <SCAN> = “0” Channel Scan <SCAN> = “1”

011 AN3 AN0 → AN1 → AN2 → AN3

100 AN4 AN0 → AN1 → AN2 → AN3 → AN4

(3) Starting AD conversion To start AD conversion, write a 1 to ADMOD0<ADS> in AD mode control register “0” or ADMOD2<ADTRGE> in AD mode control register 2, and input falling edge on ADTRG pin. When AD conversion starts, the AD conversion busy flag ADMOD0<ADBF> will be set to 1, indicating that AD conversion is in progress. During A/D conversion, a falling edge input on the ADTRG pin will be ignored. (4) AD conversion modes and the AD conversion end interrupt The four AD conversion modes are:

• Channel fixed single conversion mode
• Channel scan single conversion mode
• Channel fixed repeat conversion mode
• Channel scan repeat conversion mode The ADMOD0<REPEAT> and ADMOD0<SCAN> settings in AD mode control register 0 determine the AD mode setting. Completion of AD conversion triggers an INTAD AD conversion end interrupt request. Also, ADMOD0<EOCF> will be set to 1 to indicate that AD conversion has been completed. a. Channel fixed single conversion mode Setting ADMOD0<REPEAT> and ADMOD0<SCAN> to 00 selects conversion channel fixed single conversion mode. In this mode data on one specified channel is converted once only. When the conversion has been completed, the ADMOD0<EOCF> flag is set to 1, ADMOD0<ADBF> is cleared to 0, and an INTAD interrupt request is generated. b. Channel scan single conversion mode Setting ADMOD0<REPEAT> and ADMOD0<SCAN> to 01 selects conversion channel scan single conversion mode. In this mode data on the specified scan channels is converted once only. When scan conversion has been completed, ADMOD0<EOCF> is set to 1, ADMOD0<ADBF> is cleared to 0, and an INTAD interrupt request is generated.

c. Channel fixed repeat conversion mode Setting ADMOD0<REPEAT> and ADMOD0<SCAN> to 10 selects conversion channel fixed repeat conversion mode. In this mode data on one specified channel is converted repeatedly. When conversion has been completed, ADMOD0<EOCF> is set to 1 and ADMOD0<ADBF> is not cleared to 0 but held at 1. INTAD interrupt request generation timing is determined by the setting of ADMOD0<ITM0>. Setting <ITM0> to 0 generates an interrupt request every time an AD conversion is completed. Setting <ITM0> to 1 generates an interrupt request on completion of every fourth conversion. d. Channel scan repeat conversion mode Setting ADMOD0<REPEAT> and ADMOD0<SCAN> to 11 selects conversion channel scan repeat conversion mode. In this mode data on the specified scan channels is converted repeatedly. When each scan conversion has been completed, ADMOD0<EOCF> is set to 1 and an INTAD interrupt request is generated. ADMOD0<ADBF> is not cleared to 0 but held at 1. To stop conversion in a repeat conversion mode (e.g., in cases c. and d.), write a 0 to ADMOD0<REPEAT>. After the current conversion has been completed, the repeat conversion mode terminates and ADMOD0<ADBF> is cleared to 0. Switching to a halt state (IDLE2 mode with ADMOD1<I2AD> cleared to 0, IDLE1 mode or STOP mode) immediately stops operation of the AD converter even when AD conversion is still in progress. In repeat conversion modes (e.g., in cases c. and d.), when the halt is released, conversion restarts from the beginning. In single conversion modes (e.g., in cases a. and b.), conversion does not restart when the halt is released (The converter remains stopped). 3H Table 3.11.2 shows the relationship between the AD conversion modes and interrupt requests. Table 3.11.2 Relationship between AD Conversion Modes and Interrupt Requests ADMOD0 Mode Interrupt Request Generation <ITM0> <REPEAT> <SCAN> Channel Fixed Single Conversion Mode After completion of conversion X 0 0 Channel Scan Single Conversion Mode After completion of scan conversion X 0 1 Every conversion 0 Channel Fixed Repeat Conversion Mode Every 4th conversion 1 1 0 Channel Scan Repeat Conversion Mode After completion of every scan conversion X 1 1 X: Don’t care

(5) AD conversion time 132 state (6.6 μs at fSYS = 20 MHz) are required for the AD conversion of one channel. (6) Storing and reading the results of AD conversion The AD conversion data upper and lower registers (ADREG0H/L to ADREG4H/L) store the results of AD conversion. (ADREG0H/L to ADREG4H/L are read-only registers.) In channel fixed repeat conversion mode, the conversion results are stored successively in registers ADREG0H/L to ADREG3H/L. In other modes the AN0, AN1, AN2, AN3, AN4 conversion results are stored in ADREG0H/L, ADREG1H/L, ADREG2H/L, ADREG3H/L and ADREG4H/L respectively. 4H Table 3.11.3 shows the correspondence between the analog input channels and the registers which are used to hold the results of AD conversion. Table 3.11.3 Correspondence between Analog Input Channels and AD Conversion Result Registers AD Conversion Result Register Analog Input Channel (Port G) Conversion Modes other than at Right Channel Fixed Repeat Conversion Mode (<ITM0>=1) AN0 ADREG0H/L AN1 ADREG1H/L AN2 ADREG2H/L AN3 ADREG3H/L AN4 ADREG4H/L <ADRxRF>, bit0 of the AD conversion data lower register, is used as the AD conversion data storage flag. The storage flag indicates whether the AD conversion result register has been read or not. When a conversion result is stored in the AD conversion result register, the flag is set to 1. When either of the AD conversion result registers (ADREGxH or ADREGxL) is read, the flag is cleared to 0. Reading the AD conversion result also clears the AD conversion end flag ADMOD0<EOCF> to 0. ADREG0H/L ADREG1H/L ADREG2H/L ADREG3H/L

Setting example: 1. Convert the analog input voltage on the AN3 pin and write the result, to memory address 0800H using the AD interrupt (INTAD) processing routine. Main routine: 7 6 5 4 3 210 INTE0AD ← 1 1 0 0 − − − − Enable INTAD and set it to interrupt level 4. ADMOD1 ← 1 1 0 0 0 0 1 1 Set pin AN3 to be the analog input channel. ADMOD0 ← − − 0 0 0 0 0 1 Start conversion in channel fi xed single conversion mode. Interrupt routine processing example: WA ←ADREG3 Read value of ADREG3L and ADREG3H into 16-bit general-purpose register WA. WA > > 6 Shift contents read into WA 6 times to right and zero-fill upper bits. (0800H) ←WA Write contents of WA to memory address 0800H. 2. This example repeatedly converts the analog input voltages on the three pins AN0, AN1 and AN2, using channel scan repeat conversion mode. INTE0AD ← 1 0 0 0 − − − − Disable INTAD. ADMOD1 ← 1 1 0 0 0 0 1 0 Set pins AN0 to AN2 to be the analog input channels. ADMOD0 ← − − 0 0 0 1 1 1 Start conversion in channel scan repeat conversion mode. X: Don’t care, (: No change

3.12 Watchdog Timer (Runaway detection timer)

The TMP92C820 contains a watchdog timer of runaway detecting. The watchdog timer (WDT) is used to return the CPU to the normal state when it detects that the CPU has started to malfunction (Runaway) due to causes such as noise. When the watchdog timer detects a malfunction, it generates a non-maskable interrupt INTWD to notify the CPU of the malfunction. Connecting the watchdog timer output to the reset pin internally forces a reset. (The level of external RESET pin is not changed.)

3.12.1 Configuration

0H Figure 3.12.1 is a block diagram of the watchdog timer (WDT). Figure 3.12.1 Block Diagram of Watchdog Timer Note: Care must be exercised in the overall design of the apparatus since the watchdog timer may fail to function correctly due to external noise, etc. WDMOD <WDTE> RESET Selector Binary counter (22 stages) Q R S WDT control register WDCR Write B1HWrite 4EH Reset control WDMOD<RESCR> Internal reset INTWD interrupt Internal reset fIO WDMOD <WDTP1:0> Internal data bus Reset

3.12.2 Operation

The watchdog timer generates an INTWD interrupt when the detection time set in the WDMOD<WDTP1:0> has elapsed. The watchdog timer must be cleared to zero in software before an INTWD interrupt will be generated. If the CPU malfunctions (e.g., if runaway occurs) due to causes such as noise, but does not execute the instruction used to clear the binary counter, the binary counter will overflow and an INTWD interrupt will be generated. The CPU will detect malfunction (runaway) due to the INTWD interrupt, and in this case it is possible to return the CPU to normal operation by means of an anti-malfunction program. The watchdog timer begins operating immediately on release of the watchdog timer reset. The watchdog timer is reset and halted in IDLE1 or STOP mode. The watchdog timer counter continues counting during bus release (when BUSAK goes low). When the device is in IDLE2 mode, the operation of the WDT depends on the WDMOD<I2WDT> setting. Ensure that WDMOD<I2WDT> is set before the device enters IDLE2 mode. The watchdog timer consists of a 22-stage binary counter which uses the clock fSYS as the input clock. The binary counter can output 215/fIO, 217/fIO, 219/fIO and 221/fIO. Figure 3.12.2 Normal Mode The runaway detection result can also be connected to the reset pin internally. In this case, the reset time will be between 44 and 58 system clocks (35.2 to 46.4μs at f OSCH = 40 MHz) as shown in 1H Figure 3.12.3. After a reset, the fIO clock (1 cycle = 1 state) is fFPH/4, where fFPH is generated by dividing the high-speed oscillator clock (fOSCH) by sixteen through the clock gear function Figure 3.12.3 Reset Mode 44 to 58 system clocks (35.2 to 46.4 μs at fSYS = 20 MHz) n WDT counter WDT interrupt Overflow Internal reset Overflow n 0 WDT counter WDT interrupt WDT clear (Software) Write clear code

3.12.3 Control Registers

The watchdog timer WDT is controlled by two control registers WDMOD and WDCR. (1) Watchdog timer mode register (WDMOD) a. Setting the detection time for the watchdog timer in <WDTP1:0> This 2-bit register is used for setting the watchdog timer interrupt time used when detecting runaway. On a reset this register is initialized to WDMOD<WDTP1:0> = 00. The detection times for WDT is 215/fIO [s]. (The number of system clocks is approximately 65,536.) b. Watchdog timer enable/disable control register <WDTE> At reset, the WDMOD<WDTE> is initialized to 1, enabling the watchdog timer. To disable the watchdog timer, it is necessary to set this bit to 0 and to write the disable code (B1H) to the watchdog timer control register WDCR. This makes it difficult for the watchdog timer to be disabled by runaway. However, it is possible to return the watchdog timer from the disabled state to the enabled state merely by setting <WDTE> to 1. c. Watchdog timer out reset connection <RESCR> This register is used to connect the output of the watchdog timer with the RESET terminal internally. Since WDMOD<RESCR> is initialized to 0 at reset, a reset by the watchdog timer will not be performed. (2) Watchdog timer control register (WDCR) This register is used to disable and clear the binary counter for the watchdog timer.

• Disable control The watchdog timer can be disabled by clearing WDMOD<WDTE> to 0 and then writing the disable code (B1H) to the WDCR register. WDCR ← 0 1 0 0 1 110 W r i t e t h e c l e a r c ode (4EH). WDMOD ← 0 − − X 0 − − 0 Clear WDMOD<WDTE> to 0. WDCR ← 1 0 1 1 0 0 0 1 Write the disable code (B1H).
• Enable control Set WDMOD<WDTE> to 1.
• Watchdog timer clear control To clear the binary counter and cause counting to resume, write the clear code (4EH) to the WDCR register. WDCR ← 0 1 0 0 1 1 1 0 Write the clear code (4EH). Note1: If the disable control is used, set the disable c ode (B1H) to WDCR after writing the clear code (4EH) once. (Please refer to setting example.) Note2: If the watchdog timer setting is changed, change setting after setting to disable condition once.

Bit symbol WDTE WDTP1 WDTP0 − I2WDT RESCR − Read/Write R/W R/W After reset 1 0 0 0 0 0 0 Function WDT control 1: Enable Select detecting time 00: 2 /fIO 01: 2 /fIO 10: 2 /fIO 11: 2 /fIO Always write “0”. IDLE2 0: Stop 1: Operate 1: Internally connects WDT out to the reset pin Always write “0”. Watchdog timer out control 0 −

1 Connects WDT out to a reset

Watchdog timer detection time 00 2 /fIO (Approximately 3.28 ms at fOSCH = 40 MHz) 01 2 /fIO (Approximately 13.1 ms at fOSCH = 40 MHz) 10 2 /fIO (Approximately 52.4 ms at fOSCH = 40 MHz) 11 2 /fIO (Approximately 210 ms at fOSCH = 40 MHz) Watchdog timer enable/disable control Figure 3.12.4 Watchdog Timer Mode Register 7 6 5 4 3 2 1 0 Bit symbol − Read/Write W After reset − Function B1H: WDT disable code 4EH: WDT clear code WDT disable/clear control B1H Disable code 4EH Clear code Others − Figure 3.12.5 Watchdog Timer Control Register WDCR (1301H) Prohibit read- modify- write WDMOD (1300H)

3.13 Real Time Clock (RTC)

3.13.1 Function Description for RTC

(1) Clock function (Hour, minute, second) (2) Calendar function (Month and day, day of the week, and leap year) (3) 24 or 12-hour (AM/PM) clock function (4) ±30 second adjustment function (by software) (5) ALARM function (Alarm output) (6) Alarm interrupt generate (7) Divided power supply

3.13.2 Block Diagram

Figure 3.13.1 RTC Block Diagram Note 1: Western calendar year column: This product uses only the final two digits of t he year. Therefore, the year following 99 is 00 years. In use, please take into account the first two digits when handling years in the western calendar. Note 2: Leap year: A leap year is divisible by 4, but the exception is any leap year which is divisible by 100; this is not considered a leap year. However, any year which is divisible by 400, is a leap year. This product does not take into account the above exceptions . Since this product accounts only for leap years divisible by 4, please adjust the system for any problems. Divider 32 kHz clock ALARM register Comparator Clock Carry hold (1s) ALARM select Adjust Read/Write control

16 Hz clock

1 Hz clock

3.13.3 Detailed Explanation of Control Register

RTC is not initialized by system reset. Therefore, all registers must be initialized at the beginning of the program. (1) Second column register (for PAGE0 only) 7 6 5 4 3 2 1 0 Bit symbol SE6 SE5 SE4 SE3 SE2 SE1 SE0 SECR (1320H) Read/Write R/W After reset Undefined Function "0" is read. 40 sec. column 20 sec. column 10 sec. column 8 sec. column 4 sec. column 2 sec. column 1 sec. column 0 0 0 0 0 0 0 0 sec 0 0 0 0 0 0 1 1 sec 0 0 0 0 0 1 0 2 sec 0 0 0 0 0 1 1 3 sec 0 0 0 0 1 0 0 4 sec 0 0 0 0 1 0 1 5 sec 0 0 0 0 1 1 0 6 sec 0 0 0 0 1 1 1 7 sec 0 0 0 1 0 0 0 8 sec 0 0 0 1 0 0 1 9 sec 0 0 1 0 0 0 0 10 sec 0 0 1 1 0 0 1 19 sec 0 1 0 0 0 0 0 20 sec 0 1 0 1 0 0 1 29 sec 0 1 1 0 0 0 0 30 sec 0 1 1 1 0 0 1 39 sec 1 0 0 0 0 0 0 40 sec 1 0 0 1 0 0 1 49 sec 1 0 1 0 0 0 0 50 sec 1 0 1 1 0 0 1 59 sec Note: Do not set data other than as shown above.

(2) Minute column register (for PAGE0/1) 7 6 5 4 3 2 1 0 Bit symbol MI6 MI5 MI4 MI3 MI2 MI1 MI0 MINR (1321H) Read/Write R/W After reset Undefined Function “0” is read. 40 min column 20 min column 10 min column 8 min column 4 min column 2 min column 1 min column 0 0 0 0 0 0 0 0 min 0 0 0 0 0 0 1 1 min 0 0 0 0 0 1 0 2 min 0 0 0 0 0 1 1 3 min 0 0 0 0 1 0 0 4 min 0 0 0 0 1 0 1 5 min 0 0 0 0 1 1 0 6 min 0 0 0 0 1 1 1 7 min 0 0 0 1 0 0 0 8 min 0 0 0 1 0 0 1 9 min 0 0 1 0 0 0 0 10 min 0 0 1 1 0 0 1 19 min 0 1 0 0 0 0 0 20 min 0 1 0 1 0 0 1 29 min 0 1 1 0 0 0 0 30 min 0 1 1 1 0 0 1 39 min 1 0 0 0 0 0 0 40 min 1 0 0 1 0 0 1 49 min 1 0 1 0 0 0 0 50 min 1 0 1 1 0 0 1 59 min Note: Do not set data other than as shown above.

(3) Hour column register (for PAGE0/1) 1. In 24-hour clock mode (MONTHR<MO0> = “1”) 7 6 5 4 3 2 1 0 Bit symbol HO5 HO4 HO3 HO2 HO1 HO0 HOURR (1322H) Read/Write R/W After reset Undefined Function “0” is read. 20 hours column 10 hours column 8 hours column 4 hours column 2 hours column 1 hour column 0 0 0 0 0 0 0 o’clock 0 0 0 0 0 1 1 o’clock 0 0 0 0 1 0 2 o’clock 0 0 1 0 0 0 8 o’clock 0 0 1 0 0 1 9 o’clock 0 1 0 0 0 0 10 o’clock 0 1 1 0 0 1 19 o’clock 1 0 0 0 0 0 20 o’clock 1 0 0 0 1 1 23 o’clock Note: Do not set data other than as shown above. 2. In 12-hour clock mode (MONTHR<MO0> =“0”) 7 6 5 4 3 2 1 0 Bit symbol HO5 HO4 HO3 HO2 HO1 HO0 HOURR (1322H) Read/Write R/W After reset Undefined Function “0” is read. PM/AM 10 hours column 8 hours column 4 hours column 2 hours column 1 hour column 0 0 0 0 0 0 0 o’clock (AM) 0 0 0 0 0 1 1 o’clock 0 0 0 0 1 0 2 o’clock 0 0 1 0 0 1 9 o’clock 0 1 0 0 0 0 10 o’clock 0 1 0 0 0 1 11 o’clock 1 0 0 0 0 0 0 o’clock (PM) 1 0 0 0 0 1 1 o’clock Note: Do not set data other than as shown above.

(4) Day of the week column register (for PAGE0/1) 7 6 5 4 3 2 1 0 Bit symbol WE2 WE1 WE0 DAYR (1323H) Read/Write R/W After reset Undefined Function “0” is read. W2 W1 W0 0 0 0 Sunday 0 0 1 Monday 0 1 0 Tuesday 0 1 1 Wednesday 1 0 0 Thursday 1 0 1 Friday 1 1 0 Saturday Note: Do not set data other than as shown above. (5) Day column register (PAGE0/1) 7 6 5 4 3 2 1 0 Bit symbol DA5 DA4 DA3 DA2 DA1 DA0 DATER (1324H) Read/Write R/W After reset Undefined Function “0” is read. Day 20 Day 10 Day 8 Day 4 Day 2 Day 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1st day 0 0 0 0 1 0 2nd day 0 0 0 0 1 1 3rd day 0 0 0 1 0 0 4th day 0 0 1 0 0 1 9th day 0 1 0 0 0 0 10th day 0 1 0 0 0 1 11th day 0 1 1 0 0 1 19th day 1 0 0 0 0 0 20th day 1 0 1 0 0 1 29th day 1 1 0 0 0 0 30th day 1 1 0 0 0 1 31st day Note1: Do not set data other than as shown above. Note2: Do not set for non-existent days (e.g.: 30th Feb).

(6) Month column register (for PAGE0 only) 7 6 5 4 3 2 1 0 Bit symbol MO4 MO4 MO2 MO1 MO0 MONTHR (1325H) Read/Write R/W After reset Undefined Function “0” is read. 10 months 8 months 4 months 2 months 1 month 0 0 0 0 1 January 0 0 0 1 0 February 0 0 0 1 1 March 0 0 1 0 0 April 0 0 1 0 1 May 0 0 1 1 0 June 0 0 1 1 1 July 0 1 0 0 0 August 0 1 0 0 1 September 1 0 0 0 0 October 1 0 0 0 1 November 1 0 0 1 0 December Note: Do not set data other than as shown above. (7) Select 24-hour clock or 12 -hour clock (for PAGE1 only) 7 6 5 4 3 2 1 0 Bit symbol MO0 MONTHR (1325H) Read/Write R/W After reset Undefined Function “0” is read. 1: 24-hour 0: 12-hour

(8) Year column register (for PAGE0 only) 7 6 5 4 3 2 1 0 Bit symbol YE7 YE6 YE5 YE4 YE3 YE2 YE1 YE0 YEARR (1326H) Read/Write R/W After reset Undefined Function 80 years 40 years 20 years 10 years 8 years 4 years 2 years 1 year 0 0 0 0 0 0 0 0 00 years 0 0 0 0 0 0 0 1 01 years 0 0 0 0 0 0 1 0 02 years 0 0 0 0 0 0 1 1 03 years 0 0 0 0 0 1 0 0 04 years 0 0 0 0 0 1 0 1 05 years 1 0 0 1 1 0 0 1 99 years Note: Do not set data other than as shown above. (9) Leap year register (for PAGE1 only) 7 6 5 4 3 2 1 0 Bit symbol LEAP1 LEAP0 YEARR (1326H) Read/Write R/W After reset Undefined Function “0” is read. 00: Leap year 01: One year after leap year 10: Two years after leap year 11: Three years after leap year 0 0 Current year is a leap year

01 Current year is the year

10 Current year is two years after

11 Current year is three years

(10) Setting PAGE register (for PAGE0/1) 7 6 5 4 3 2 1 0 Bit symbol INTENA ADJUST ENATMR ENAALM PAGE PAGER (1327H) Read/Write R/W W R/W R/W After reset 0 Undefined Undefined Undefined Read-modify-write instruction is prohibited. Function INTRTC 0: Disable 1: Enable “0” is read. 0: Don’t care 1: Adjust Clock 0: Disable 1: Enable ALARM 0: Disable 1: Enable “0” is read. PAGE selection Note: Please keep the setting order below of <ENATMR> , <ENAAML> and <INTENA>. Set different times for Clock/Alarm setting and interrupt setting. (Example) Clock setting/Alarm setting ld (pager), 0ch : Clock, Alarm enable ld (pager), 8ch : Interrupt enable

0 Select Page0 PAGE

1 Select Page1

1 Adjust sec. counter. When this bit is set to “1” the sec. counter becomes “0” when the value of the sec. counter is 0 – 29. When the value of the sec. counter is 30-59, the min. counter is carried and sec. counter becomes "0". Output Adjust signal during 1 cycle of f SYS. After being adjusted once, Adjust is released automatically. (PAGE0 only) (11) Setting reset register (for PAGE0/1) 7 6 5 4 3 2 1 0 Bit symbol DIS1Hz DIS16Hz RSTTMR RSTALM − − − − RESTR (1328H) Read/Write W After reset Undefined Read-modify write-instructio n is prohibited. Function 1Hz 0: Enable 1: Disable 16Hz 0: Enable 1: Disable 1:Clock reset 1: Alarm reset Always write “0”

0 Unused RSTALM

1 Reset alarm register

0 Unused RSTTMR

1 Reset counter

<DIS1HZ> <DIS1HZ> (PAGER) <ENAALM> Source signal 1 1 1 Alarm 0 1 0 1Hz 1 0 0 16Hz Others Output “0”

3.13.4 Operational description

(1) Reading clock data 1. Using 1Hz interrupt 1Hz interrupt and the count up of internal data synchronize. Therefore, data can read correctly if reading data after 1Hz interrupt occurred. 2. Using two times reading There is a possibility of incorrect clock data reading when the internal counter carries over. To ensure correct data reading, please read twice, as follows: Figure 3.13.2 Flowchart of clock data read Start END PAGER<PAGE> = “0” , Select PAGE0 Read the clock data (1st) Read the clock data (2nd) 1st data = 2nd data NO YES

(2) Writing clock data When a carry over occurs during a write operation, the data cannot be written correctly. Please use the following method to ensure data is written correctly. 1. Using 1Hz interrupt 1Hz interrupt and the count up of internal data synchronize. Therefore, data can write correctly if writing data after 1Hz interrupt occurred. 2. Resetting a counter There are 15-stage counter inside the RTC, which generate a 1Hz clock from 32,768 KHz. The data is written after reset this counter. However, if clearing the counter, it is counted up only first writing at half of the setting time, first writing only. Therefore, if setting the clock counter correctly, after clearing the counter, set the 1Hz-interrupt to enable. And set the time after the first interrupt (occurs at 0.5Hz) is occurred. Figure 3.13.3 Flowchart of data write Start END PAGER<PAGE> = “0” , Select PAGE0 RESTR<RSTTMR> = “1” reset counter RESTR<DIS1HZ> = “0” enable 1Hz interrupt First interrupts occur (After 0.5S) NO YES Sets the time

1. Disabling the clock A clock carry over is prohibited when “0” is written to PAGER<ENATMR> in order to prevent malfunction caused by the Carry hold circuit. While the clock is prohibited, the Carry hold circuit holds a one sec. carry signal from a divider. When the clock becomes enabled, the carry signal is output to the clock, the time is revised and operation continues. However, the clock is delayed when clock-disabled state continue s for one second or more. Note that at this time system power is down while the clock is disabled. . In this case the clock is stopped and clock is delayed. Figure 3.13.4 Flowchart of Clock disable Start End Disable the clock Read the clock data Enable the clock

3.13.5 Explanation of the interrupt signal and alarm signal

The alarm function used by setting the PAGE1 register and outputting either of the following three signals from ALARM pin by writing “1” to PAGER<PAGE>. INTRTC outputs a 1-shot pulse when the falling edge is detected. RTC is not initialized by RESET. Therefore, when the clock or alarm function is used, clear interrupt request flag in INTC (interrupt controller). (1) When the alarm register and the clock correspond, output “0”. (2) 1Hz Output clock . (3) 16Hz Output clock. (1) When the alarm register and the clock correspond, output “0” When PAGER<ENAALM>= “1”, and the value of PAGE0 clock corresponds with PAGE1 alarm register, output “0” to ALARM pin and generate INTRTC. The methods for using the alarm are as follows: Initialization of alarm is done by writing “1” to RESTR<RSTALM>. All alarm settings become Don’t care. In this case, the alarm always corresponds with value of the clock, and if PAGER<ENAALM> is “1”, INTRTC interrupt request is generated. Setting alarm min., alarm hour, alarm date and alarm day is done by writing data to the relevant PAGE1 register. When all setting contents correspond, RTC generates an INTRTC interrupt if PAGER<INTENA><ENAALM> is “1”. However, contents which have not been set up (don't care state) are always considered to correspond. Contents which have already been set up, cannot be returned independently to the Don't care state. In this case, the alarm must be initialized and alarm register reset. The following is an example program for outputting an alarm from ALARM -pin at noon (PM12:00) every day. LD (PAGER), 09H ; Alarm disable, setting PAGE1 LD (RESTR), D0H ; Alarm initialize LD (DAYR), 01H ; W0 LD (DATAR),01H 1 day LD (HOURR), 12H ; Setting 12 o’clock LD (MINR), 00H ; Setting 00 min ; Set up time 31 μs (Note) LD (PAGER), 0CH ; Alarm enable ( LD (PAGER), 8CH ; Interrupt enable ) When the CPU is operating at high frequency oscillation, it may take a maximum of one clock at 32 kHz (about 30us) for the time register setting to become valid. In the above example, it is necessary to set 31us of set up time between setting the time register and enabling the alarm register. Note: This set up time is unnecessary w hen you use only internal interruption.

(2) With 1Hz output clock RTC outputs a clock of 1Hz to ALARM pin by setting up PAGER<ENAALM>= “0”, RESTR<DIS1HZ>= “0”, <DIS16HZ>= “1”. RTC also generates an INTRC interrupt on the falling edge of the clock. (3) With 16Hz output clock RTC outputs a clock of 16Hz to ALARM pin by setting up PAGER<ENAALM>= “0”, RESTR<DIS1HZ>= “1”, <DIS16HZ>= “0”. RTC also generates INTRC an interrupt on the falling edge of the clock.

3.14 LCD Controller (LCDC)

The TMP92C820 incorporates two types liquid crystal display driving circuit for controlling LCD driver LSI. One circuit handles a RAM built-in type LCD driver that can store display data in the LCD driver itself, and the other circuit handles a shift-register type LCD driver that must serially transfer the display data to LCD driver for each display picture.

• Shift-register type LCD driver control mode (SR mode) Set the mode of operation, start address of source data save memory and LCD size to control register before setting start register. After set start register LCDC outputs bus release request to CPU and read data from source memory. After that LCDC transmits data of volume of LCD size to external LCD driver through data bus. At this time, control signals connected LCD driver output specified waveform synchronizes with data transmission. After finish data transmission, LCDC cancels the bus release request and CPU will re-start. As the DISPLAY RAM, SDRAM burst mode can be used in TMP92C820.
• RAM built-in type LCD driver control mode (RAM mode) Data transmission to LCD driver is executed by move instruction of CPU. After setting mode of operation to control register, when moves instruction of CPU is executed, LCDC outputs chip select signal to LCD driver connected to the outside from control pin (D1BSCP etc). Therefore control of data transmission numbers corresponding to LCD size is controlled by instruction of CPU. This section is constituted as follows.

3.14.1 Feature of LCDC of Each Mode

3.14.2 Block Diagram

3.14.3 SFRs

3.14.4 Shift Register Type LCD Driver Control Mode (SR mode)

3.14.4.1 Operation

3.14.4.2 Grayscale Mode Indication

3.14.4.3 Memory Mapping

3.14.4.4 Hardware Cursor

3.14.4.5 Frame Signal Settlement

3.14.4.6 Timing Charts of Interpreting Memory Codes

3.14.4.7 Examples to Use

3.14.4.8 Sample Program

3.14.5 RAM Built-in Type LCD Driver Control Mode (RAM mode)

3.14.5.1 Operation

3.14.5.2 Examples to Use

3.14.5.3 Sample Program

Each feature and operation of pin is as follows. Table 3.14.1 Feature of LCDC of Each Mode Shift-register Type LCD Driver Control Mode RAM Built-in Type LCD Driver Control Mode The number of picture elements can be handled Common (Row): 128, 160, 200, 240, 320, 400, 480 Segment (Column): 128, 160, 240, 320, 400, 480, 560, 640 There is not a limitation Transfer data bus width 32 bits or 16 bits 8 bits fixed Internal RAM Not allow to use Allow to use Transfer rate (at fSYS = 20 [MHz]) 50 ns/1 word at SDRAM/BURST 100 ns/1 word at SRAM − LCD data bus: LD7 to LD0 pin Data bus: Connect to data input pin of column driver. Not used Data bus: D7 to D0 pin Not used Data bus: Connect to data input pin of LCD driver. Bus state: R/W pin Not used Bus state: Connect with /WR pin of column/row driver. Address bus: A0 pin Not used Address 0: Connect with D/I pin of column driver. When A0 = 1 data bus value means display data, when A0 = 0 data bus means instruction data. Shift clock pulse: D1BSCP pin Shift clock pulses: Connect with SCP pin of column driver. LCD driver latches data bus value by falling edge of this pin. Chip enable for column driver 1: Connect with CE pin of column driver 1. Latch pulse: D2BLP pin Latch pulses output: Connect with LP/EIO1 pin of column/row driver. Display data is latched in 1st shift register in LCD driver by rising edge of this pin. And shift to next shift register by LP and SCP = “H”. Chip enable for column driver 2: Connect with CE pin of column driver 2. Frame: D3BFR pin LCD frame output: Connect with FR pin of column/row driver. Chip enable for column driver 3: Connect with CE pin of column driver 3. Cascade pulse: DLEBCD pin Cascade pulses output: Connect with DIO1 pin of row driver. These pin outputs 1 shot pulse by every D3BFR pin changes. Chip enable for row driver: Connect with LE pin of row driver. External pins Display OFF: DOFF pin Display OFF output: Connect with DSPOF terminal of column/row driver. “L” means display off and “H” means display ON.

Figure 3.14.1 LCDC Block Diagram COLUMN INCREMENTOR ROW INCREMENTOR Selector CPU address bus: A0 to A23 MMU External data bus: A0 to A23 LCD bus LD0 to LD7 Clear InnerSCP generate System clock: fSYS CPU BUSAK output COLUMN counter (9 bits) ComparatorCOLUMN register R S Q SCPEN D1BSCP COLUMN END <START> BUSRQ GLCDC address bus Lower rate clock: fs TA3OUT Shift register increment (14 bits) LP generateROW register External D2BLP BCD generate FP register External DLEBCD ROW counter FR generate External D3BFR Internal I/O data bus Internal I/O data bus To internal INT (Rising edge) LP output circuit Cursor control Gray scale control External data bus: D0 to D15 FR driver DVM register 1 DVM register 2 FR driver <TA3LCDCK> 80 bytes FIFO and SCP generator 2×, 4×, 8× clock divider fSYS

Bit symbol BAE AAE SCPW1 SCPW0 TA3LCDCK BULK RAMTYPE MODE Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 1 0 0 0 0 0 Function B-area 0: Disable 1: Enable A-area 0: Disable 1: Enable 00: Base SCP 01: 2 clocks 10: 4 clocks 11: 8 clocks Select low- frequency clock 0: 32 kHz 1: TA3OUT Byte- number/ Common 0: 512 bytes 1: 1024 bytes * (Note 4) Display RAM 0: SRAM 1: SDRAM Mode selection 0: RAM 1: SR Note 1: <BULK> is effective when <RAMTYPE> is set to “1”. <BULK> shows how to generate address for next common. Note 2: The SDRAM accessing way of LCDC is only “Burst 1CLK access”. Note 4: Refer to 0H Table 3.14.1. Table 3.14.2 SDRAM BULK and Column Address LCDMODE<BULK> 0 1 SDRAMC SDACR<SMUXW> Type A Type B Bulk of 1 page 512 bytes 1024 bytes Divide FRM Register 7 6 5 4 3 2 1 0 Bit symbol FMN7 FMN6 FMN5 FMN4 FMN3 FMN2 FMN1 FMN0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Setting DVM bit7 to 0 LCD Size Setting Register 7 6 5 4 3 2 1 0 Bit symbol COM3 COM2 COM1 COM0 SEG3 SEG2 SEG1 SEG0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 0 Function Setting the LCD common number for SR mode 0000: 128 0101: 400 0001: 160 0110: 480 0010: 200 0011: 240 0100: 320 Other: Reserved Setting the LCD segment number for SR mode 0000: 128 0101: 480 0001: 160 0110: 560 0010: 240 0111: 640 0011: 320 0100: 400 Other: Reserved LCDMODE (0200H) LCDDVM (0201H) LCDSIZE (0202H)

Bit symbol LCDON ALL0 FRMON − FP9 MMULCD FP8 START Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 0 Function DOFF port 0: OFF 1: ON LD bus output control 0: Normal 1: All display data = 0 Divided FR mode 0: Disable 1: Enable Always write “0”. Setting bit9 for f FP [9:0] Type selection of LCD driver with built-in RAM 0: Sequential access type 1: Random access type Setting bit8 for f FP [9:0] Start control in SR mode 0: Stop 1: Start LCDC start/stop bit

0 LCDC stop

1 LCDC start

RAM internal LCD driver TYPE selection

0 Sequential access type

1 Random access type

Flame frequency division mode

0 Normal

1 All “0”

Note: This bit is forced setting it to “0” (light OFF) by writing “1” that data transfer to LCDD. Usually, writing “0”. Pin of LCD driver: DOFF

0 Driver OFF

1 Driver ON

Note: This bit decide state of DOFF pin. Case of “0”: output “0” Case of “1”: output “1” Figure 3.14.2 LCDC Control Register 1 LCDCTL (0203H)

Bit symbol FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Setting bit7 to 0 for f FP LCD Gray Level Setting Register 7 6 5 4 3 2 1 0 Bit symbol GRAY1 GRAY0 Read/Write R/W After reset 0 0 Function 00: Monochrome 01: 4 levels 10: 8 levels 11: 16 levels Figure 3.14.3 LCDC Control Register 2 Table 3.14.3 LCD Start/End Address Register Start Address Register End Address Register H (Bit23 to Bit16) M (Bit15 to Bit8) L (Bit7 to Bit0) H (Bit23 to Bit16) M (Bit15 to Bit8) L (Bit7 to Bit0) A-area LSARAH (0211H) LSARAM (0210H) − LEARAH (0213H) LEARAM (0212H) − After reset 40H 00H − 40H 00H − B-area LSARBH (0215H) LSARBM (0214H) − LEARBH (0217H) LEARBM (0216H) − After reset 40H 00H − 40H 00H − C-area LSARCH (021AH) LSARCM (0219H) LSARCL (0218H) − − − After reset 40H 00H 00H − − − Note: All registers are available for R (Read)/W (Write). LCDFFP (0204H) LCDGL (0205H)

LCD Cursor Setting Register 7 6 5 4 3 2 1 0 Bit symbol CDE CCS CBE1 CBE0 Read/Write R/W R/W R/W R/W After reset 0 0 0 0 Function Cursor 0: OFF 1: ON Cursor color 0: White 1: Black Cursor blink interval (XT1: 32 kHz) 00: Don’t blink 01: 2 Hz 10: 1 Hz 11: 0.5 Hz Note 1: Cursor brink interval make using low clock (fs). This function doesn’t depend on LCDMODE. Therefore if you use blink function, you set low clock condition. Note 2: Also case of using timer out “TA3OUT” to LCDCK, cursor brink internal depend on fs. LCD Cursor Width Setting Register 7 6 5 4 3 2 1 0 Bit symbol CW4 CW3 CW2 CW1 CW0 Read/Write R/W R/W R/W R/W R/W After reset 0 0 0 0 0 Function Cursor width (X size) 00000: 1 dot (Min) 11111: 32 dots (Max) LCD Cursor Height Setting Register 7 6 5 4 3 2 1 0 Bit symbol CH4 CH3 CH2 CH1 CH0 Read/Write R/W R/W R/W R/W R/W After reset 0 0 0 0 0 Function Cursor height (Y size) 00000: 1 dot (Min) 11111: 32 dots (Max) Figure 3.14.4 LCDC Control Register 3 LCDCM (0206H) LCDCW (0207H) LCDCH (0208H)

LCDC1L, LCDC1H, LCDC2L, LCDC2H, LCDC3L, LCDC3H, LCDR1L and LCDR1H Register 7 6 5 4 3 2 1 0 Bit symbol D7 D6 D5 D4 D3 D2 D1 D0 Read/Write Depend on the specification of external LCD driver After reset Depend on the specification of external LCD driver Function Depend on the specificati on of external LCD driver Figure 3.14.7 LCDC Control Register 6 These registers do not exist on TMP92C820. These are image for instruction registers and display registers of external RAM built-in sequential access type LCD driver. Address as 1H Figure 3.14.4 is assigned to these registers, and the following chip enable pin becomes active when accesses corresponding address. And, the area of these address is external area, so RD , WR terminal becomes active by external access. 2H Figure 3.14.5 shows the address map in the case of controlling RAM built-in random access type LCD driver. The explanation part of MMU circuit also explains this. This setup is performed by LCDCTL<MMULCD>. Table 3.14.4 Memory Mapping for Built-in RAM Sequential Access Type Register Address Purpose Sequential Access Type Chip Enable Terminal Terminal LCDC1L 1FE0H Instruction 0 LCDC1H 1FE1H RAM built-in type column driver 1 Display data D1BSCP LCDC2L 1FE2H Instruction 0 LCDC2H 1FE3H RAM built-in type column driver 2 Display data D2BLP LCDC3L 1FE4H Instruction 0 LCDC3H 1FE5H RAM built-in type column driver 3 Display data D3BFR LCDR1L 1FE6H Instruction 0 LCDR1H 1FE7H RAM built-in type row driver Display data DLEBCD

Table 3.14.5 Memory Mapping for Built-in RAM Random Access Type Address Purpose Random Access Type Chip Enable Terminal 3C0000H to 3CFFFFH RAM built-in type driver 1 D1BSCP 3D0000H to 3DFFFFH RAM built-in type driver 2 D2BLP 3E0000H to 3EFFFFH RAM built-in type driver 3 D3BFR 3F0000H to 3FFFFFH RAM built-in type driver DLEBCD Note 1: We call built-in RAM sequential access type LCD driver that use register to access to display RAM without address. (Example: T6B65A, T6C84 etc., mar/2000) Note 2: We call built-in RAM random access type LCD driver that is same method to access to SRAM. (Example: T6C23,T6K01 etc., mar/2000)

Set the mode of operation, start address of source data save memory, grayscale level and LCD size to control registers before setting start register. After set start register LCDC outputs bus release request to CPU and read data from source memory. After that LCDC transmits data of volume of LCD size to external LCD driver through LD bus (LCD personal bus). At this time, control signals (DIBSCP etc.) connected LCD driver output specified waveform synchronizes with data transmission. After finish data transmission, LCDC cancels the bus release request and CPU will re-start. Note: SR mode LCDC, during data reading ( during DMA operation), CPU is stopped by internal BUSREQ signal. When using SR mode LCDC, programmer need to care the CPU stop time. For detail, see the 3H Table 3.14.4.

Monochrome, 4, 8 and 16 grayscale mode can be selected by setting LCDGL<GRAY1:0>. And when SDRAM mode, you can select the size of SDRAM by setting (LCDMODE)<BULK>. TMP92C820 realize grayscale display by thinning out the frame. Grayscale control palette is defined by 16 bit register (LGnL/H) shown in 4H Table 3.14.6. Palette is selected ON/OFF for data of each level (e.g., each density) can modify by 16-bit register (LGnL/H). However each register of palette has a initial value, it is possible to adjust finely which matches to LCD driver you use and the characteristic of LCD panel. Table 3.14.6 Grayscale Control Palette Default Setting Level Code Density Data Setting Register (Address/After reset) Bit 0 123456789 1 0 1 1 1 2 1 3 1 4 1 5

• : Display ON, ○: Display OFF Table 3.14.7 Grayscale Control Palette Effective Registers for Each Gray Level LG0 L/H LG1 L/H LG2 L/H LG3 L/H LG4 L/H LG5 L/H LG6 L/H LG7 L/H LG8 L/H LG9 L/H LGA L/H LGB L/H LGC L/H LGD L/H LGE L/H LGE L/H ×: Don’t care, •: Effective D3BFR t

The LCDC can display the LCD panel image which is divided horizontally into 3 parts; upper, middle and lower. Each area calls A, B and C area that has some characteristics showing below. Start/End address of each area in the physical memory space can be defined in the LCD Start/End address registers (See 6H Table 3.14.3). (C area can be defined only start address.) A and B areas are programmable visibility and they are set enable or not in LCDMODE register. When A and B area are disable, the C area take over all panel space. When the size of A or B area is greater than LCD panel, the area of the panel is all C area because the displaying priority is A > B > C. If the A area set to enable while the panel area is defined as all C area (that is A and B area are disable), C area is shifted to under the LCD panel and A area is inserted from the top of the LCD panel. Similarly if the B area set to enable while the panel area is defined as all C area, B area is inserted from the bottom of the C area overlapping. Figure 3.14.8 Memory Mapping from Physical Memory to LCD Panel Column address A area B area Ya Yb Yc C area A area B area C area Vertical pan Logic address 400000H 600000H Horizontal pan Row address Reserved area for horizontal pan of C area * Display data cannot input closely when you don’t use the pan function. Memory map image LCD panel image Ya Yc Yb X

• Display memory mapping and panning function LCDC can change the panel window if only you change each start address of A, B and C area. A and B area can be vertical panned by changing row address. While C area can be vertical and horizontal panned by changing row and column address. An important thing is that display data from one line to the next line, cannot be input continuously even if you don’t use the panning function. One row address of display RAM corresponds to 1st line of display panel. Now display data of 2nd line cannot be set within the 1st row address of display RAM even if the necessary data for the size you want to display do not fill the capacity of 1st row address of display RAM. Adding the one line to display panel is equal to adding one address to row address of display RAM. And another important thing is, this limitation is also for SRAM as display RAM without address multiplex. When you use SDRAM as display RAM, you can select the size for display RAM capacity of one line (Number of column address: select 512 byte = 64 Mbytes 1024 byte = 128 Mbytes) bit. But in case of using SRAM, display RAM capacity of one line is fixed to 512 bytes. Figure 3.14.9 Memory Mapping Image for SRAM as Display RAM Display panel of 1st line memory area Reserved area for vertical panning (Display 1st line) Display panel of 2nd line memory area Reserved area for vertical panning (Display 2nd line) Reserved area for vertical panning (Display 3rd line) Memory area for display 1st line (When using SRAM, this area is fixed to 512 bytes.) Memory area for display 2nd line (When using SRAM, this area is fixed to 512 bytes.) Memory area for display 3rd line (When using SRAM, this area is fixed to 512 bytes.) Display panel of 3rd line memory area 16-bit bus width Start address

TMP92C820 has a cursor that is blinking interval, color and size can be specified, and maximum size is 32 × 32. A programmer can control the cursor attributes easily by filling those cursor registers, for example color (White/black), blinking interval time, size and precise pixel location. Its space location is specified by left-up hot point. (See 11H Figure 3.14.12) The precise location of the hot point is determined by memory address (LCDCPH, LCDCPM, LCDCPL) and bit correction number (LCDCP). For example, however 1 pixel for displaying needs 2 bits of setting data under 4 gray mode, you can correct the location of hot point every 1 bit by setting pixel number which you want to move in the register (LCDCP). Cursor image is showed under the setting A, B, C area are enable, 4 gray mode, start address = 410004H and correction bit (LCDCP) = 3H in the following figure. Figure 3.14.12 Cursor Hot Point Position and Size Note: If panning function is set to enable during hardwar e cursor displaying, the cursor moves with the data in the memory. Because TMP92C820 sets the hardware cursor in the memory address. A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0SDRAM size <BULK> = 1 <BULK> = 0 Column address Row address Cursor start address “0” Ignore A area B area C area A area B area C area Row address Logic address 400000H 600000H Memory map image LCD panel image 410000H Correction bit: 3H Cursor width Cursor height Hot point Column address Cursor start address 410004H

LCD Cursor Setting Register 7 6 5 4 3 2 1 0 Bit symbol CDE CCS CBE1 CBE0 Read/Write R/W R/W R/W R/W After reset 0 0 0 0 Function Cursor 0: OFF 1: ON Cursor color 0: White 1: Black Cursor blink interval 00: Don’t blink 01: 2 Hz 10: 1 Hz 11: 0.5 Hz Note 1: The function of cursor blink is effectiv e only when low-frequency oscillator is input 32 kHz. Note 2: The function of cursor blink depends on the low-fr equency oscillator even if you use timer out “TA3OUT” as LCDCK. LCD Cursor Width Setting Register 7 6 5 4 3 2 1 0 Bit symbol CW4 CW3 CW2 CW1 CW0 Read/Write R/W R/W R/W R/W R/W After reset 0 0 0 0 0 Function Cursor width (X size) 00000: 1 dot (Min) 11111: 32 dots (Max) LCD Cursor Height Setting Register 7 6 5 4 3 2 1 0 Bit symbol CH4 CH3 CH2 CH1 CH0 Read/Write R/W R/W R/W R/W R/W After reset 0 0 0 0 0 Function Cursor height (Y size) 00000: 1 dot (Min) 11111: 32 dots (Max) LCD Cursor Start Address Setting Register 7 6 5 4 3 2 1 0 Bit symbol CAP7 CAP6 CAP5 CAP4 CAP3 CAP2 CAP1 CAP0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 0 Function Setting bit7 to bit0 for cursor start address LCD Cursor Start Address Setting Register 7 6 5 4 3 2 1 0 Bit symbol CAP15 CAP14 CAP13 CAP12 CAP11 CAP10 CAP9 CAP8 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 0 Function Setting bit15 to bit8 for cursor start address LCD Cursor Start Address Setting Register 7 6 5 4 3 2 1 0 Bit symbol CAP23 CAP22 CAP21 CAP20 CAP19 CAP18 CAP17 CAP16 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 1 0 0 0 0 0 0 Function Setting bit23 to bit16 for cursor start address LCDCM (0206H) LCDCW (0207H) LCDCH (0208H) LCDCPL (020AH) LCDCPM (020BH) LCDCPH (020CH)

LCD Cursor Hot Point Pixel Number (Bit correction) Setting Register 7 6 5 4 3 2 1 0 Bit symbol APB3 APB2 APB1 APB0 Read/Write R/W After reset 0 0 0 0 Function Setting bit3 to bit0 of pixel for correction of hot point (for 1-dot correction) In case of monochrome (SRAM mode) 0000: 0 pixels correct 1111: 0 pixels correct In case of monochrome (SDRAM mode) x000: 0 pixels correct x100: 4 pixels correct and 4 gray levels x001: 1 pixel correct x101: 5 pixels correct x010: 2 pixels correct x110: 6 pixels correct x011: 3 pixels correct x111: 7 pixels correct In case of 8 and 16 gray levels xx00: 0 pixels correct xx10: 2 pixels correct xx01: 1 pixel correct xx11: 3 pixels correct X: Don’t care Here, it is possible to correct the cursor per 1 bit from the start address set before. Pixel number should be adjusted in response to the gray mode setting showing above. For example, when 4 gray levels and 16-bit bus mode, correction should be less than 7 because the smallest pixel is 8 pixels that can set by start address setting. Similarly correction pixel should be less than 15 at monochrome mode, 3 at 8 or 16 gray modes. Example: When monochrome mode, correction value is (LCDCP) = 011H, and cursor size = (8 × 8) Figure 3.14.13 The Location Hot Point by Setting of Pixel LCDCP (0209H) Hot point 3 bits move Start address (LCDCPH/M/L) CURSOR LCD panel

TMP92C820 defines so-called frame period (refresh interval for LCD panel) by the value set in fFP [9:0]. DLEBCD pin outputs pulse every frame period. D3BFR pin usually outputs the signal inverts polarity every frame period. And TMP92C820 has a special function that can set the timing of inverting frame polarity irrelevant to above frame frequency for the purpose of preventing the patches of display. LCD Control Register 7 6 5 4 3 2 1 0 Bit symbol LCDON ALL0 FRMON − FP9 MMULCD FP8 START Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 0 Function DOFF port 0: OFF 1: ON Setting all column ports to 0 0: Normal 1: All display data = 0 Divided FR mode 0: Disable 1: Enable Always write “0”. Setting bit9 for f FP [9:0] Type setting of LCD driver with built-in RAM 0: Sequen -tial access type 1: Random access type Setting bit8 for f FP [9:0] Start control in SR mode 0: Stop 1: Start LCD fFP Register 7 6 5 4 3 2 1 0 Bit symbol FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Setting bit7 to 0 for f FP Divide FRM Register 7 6 5 4 3 2 1 0 Bit symbol FMN7 FMN6 FMN5 FMN4 FMN3 FMN2 FMN1 FMN0 Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Setting DVM bit7 to 0 LCDCTL (0203H) LCDFFP (0204H) LCDDVM (0201H)

(1) Settlement of frame frequency function Basic frame period; DLEBCD signal, is made according to the resister fFP [9:0] setting mentioned before. However this fFP [9:0] setting is generally equal to common number, frame period can be corrected by increasing fFP [9:0] with ease. This function cannot correct frame frequency higher than that of 12H Table 3.14.8. If it is necessary to set frame frequency higher or detailed, please refer to (3) Timer out LCDCK. The equation can calculate frame period. Frame period = LCDCK/(D × fFP) [Hz] D: Constant for each common (13H Table 3.14.8) fFP: Setting of fFP [9:0] register LCDCK: Source clock of LCD (Low clock is usually selected) Please select the value of fFP [9:0] as the frame period you want to set in the 14H Table 3.14.8 Note: Please make the value set to f FP [9:0] into the following range. COM (Common number) ≤ fFP ≤ 1024 Example 1: In the case where frame pe riod is set to 72.10 Hz by 240 coms. f FP = 240 (COM) + 63 = 303 = 12FH (by 15H Table 3.14.8) Therefore, LCDCTL<FP8> = 1_hex and LCDFFP<FP7:0> = 2FH are setup. (2) Frame invert adjustment function This mode can prevent the deterioration of display (e.g., patches of display). *Note 1: If N is set in (LCDDVM) register while this function is set to enable in register (LCDCTL)(<FRMON> “1”), D3BFR pin outputs the signal inverted polarity every (D2BLP × N) timing. If this function isn’t necessary, D3BFR pin outputs the signal inverted polarity every frequency of DLEBCD pin after setting this function disable ((LCDCTL) <FRMON> = “0”). And it is no change wave and timing for DLEBCD pin by LCDDVM setting. Note: Effects of this function have some di fferences as the LCD driver or LCD panel you use actually.

(3) Timer out LCDCK LCD source clock (LCDCK) can select low frequency (XT1, XT2: 32.768 [kHz]) or timer out (TA3OUT) outputs from internal TMRA23. Example 2: Here indicates the method that frame period is set 70 [Hz] by selecting TA3OUT for source clock of LCD. (fc = 6 [MHz], 128 COM) The next equation calculates frame period. Frame period = 1/(tLP × fFP) [Hz] t LP: The period of D2BLP Source clock for LCDC defines as XT [Hz] and then this tLP represents t LP = D/XT D: The value is 3 at 128 COM Therefore if you set the frame period at 70 [Hz] under 128 COM, XT = 128 × 3 × 70 = 26880 [Hz] XT should be above value. In order to make XT = 26880 [Hz] under fc = 6 [MHz] with φT1 of timer3, 1/XT = T3 × 2 × 8 × 2/ fc [s] T3: the value of timer register (TA3REG) in short, However T3 = (TA3REG) is 6.98 after calculate, it’s impossible to set the value under a decimal point. So if (TA3REG) is set 06H, XT = 31250 [Hz]. And because of D = 3, Frame period = 31250/(128 × 3) = 81.38 [Hz] Further if f FP is 148 (COM + 20) with correction, Frame period = 31250/(148 × 3) = 70.38 [Hz] Reference: To maintain quality for display, please refer to following value for each grayscale. (You have to use settlement of frame frequency function, frame invert adjustment function and timer out LCDCK.) Monochrome: Frame period = 70 [Hz] 4/8/16 gray levels: Frame period = 140 [Hz]

Table 3.14.8 fFP Table for Each Common Number (1/2) D 3 2.5 2 1.5 1.5 1 1 COM 128 160 200 240 320 400 480

Table 3.14.8 fFP Table for Each Common Number (2/2) D 3 2.5 2 1.5 1.5 1 1 COM 128 160 200 240 320 400 480 Note: The above time distance are value which used fs = 32.768 [kHz].

Table 3.14.9 Performance Listing for Each Segment and Common Number (1) SDRAM (Burst) 16 bits, 8/16 gray levels Common 128 160 200 240 320 400 480 D 3 2.5 2 1.5 1.5 1 1 Segment (2) SDRAM (Burst) 16 bits, 4 gray levels Common 128 160 200 240 320 400 480 D 3 2.5 2 1.5 1.5 1 1 Segment

(3) SDRAM (Burst) 16 bits, monochrome Common 128 160 200 240 320 400 480 D 3 2.5 2 1.5 1.5 1 1 Segment (4) SRAM (2 states) 16 bits, 8/16 gray levels (Note 2) Common 128 160 200 240 320 400 480 D 3 2.5 2 1.5 1.5 1 1 Segment

(5) SRAM (2 states) 16 bits, 4 gray levels (Note 2) Common 128 160 200 240 320 400 480 D 3 2.5 2 1.5 1.5 1 1 Segment (6) SRAM (2 states) 16 bi ts, monochrome (Note 2) Common 128 160 200 240 320 400 480 D 3 2.5 2 1.5 1.5 1 1 Segment Note 1: These tables are calculated at following condition. 1) f SYS = 20 [MHz] 2) fs = 32.768 [kHz] 3) Overhead state number are 8 states for SDRAM and 3 states for SRAM. Note 2: For SRAM tables ((4) to (6)), tSTOP is calculated at 2-state accessing.

Table 3.14.10 Possible Panel Size of Panning 64-Mbit SDRAM/BURST Horizontal SEG 128 160 240 320 400 480 560 640 Vertical COM 128 160 200 240 320 400 480 128-Mbit SDRAM/BURST Horizontal SEG 128 160 240 320 400 480 560 640 Vertical COM 128 160 200 240 320 400 480 SRAM Horizontal SEG 128 160 240 320 400 480 560 640 Vertical COM 128 160 200 240 320 400 480

Note 1: The value of the Table 3.14.8 is at fFPH = 36 [MHz]. Note 2: CPU stop time; tSTOP (in the Figure 3.14.17) is the time which CPU reads the memory of transferring with 0 waits. Note 3: The following equation can calculate tLP listed below. (fs = 32.768 [kHz]) t LP = D/32768 [s] Example: If the row is 240 and D = 1.5 by the above table t LP = 1.5/32768 = 45.8 [μs] Figure 3.14.17 Stop Time and BUS Occupation Rate of CPU D3BFR pin DLEBCD pin D2BLP pin D1BSCP pin D7 to D0 pin 1 2 3 1 2 3 1 2 120 120 tLP BUS occupation time of CPU tSTOP BUS occupation rate of CPU = tSTOP/tLP

TMP92C820 supports different memory accessing. They are SRAM with waits, SDRAM burst modes, and the size of SDRAM is 64 or 128 Mbits. The access signals for the LCD panel are shown in 16H Figure 3.14.18. TMP92C820 include 80 bytes FIFO. Therefore, If CPU operate high speed, TMP92C820 can to use low-speed LCD driver. To catch low speed LCD drivers, 4 types of SCP rates (fSYS, fSYS/2, fSYS/4, and fSYS/8) can be selected. The output data (LD7:0) will be issued from the built-in FIFO at the rising edge of D1BSCP when the FIFO is no empty. The work of the FIFO is illustrated in 17H Figure 3.14.19, where the buffer size 80 bytes. The FIFO latches BaseLD<7:0> signal at the falling edge of BaseSCP that is shown in 18H Figure 3.14.20 and 19H Figure 3.14.21 for SRAM and SDRAM modes respectively. The FIFO is always reset to the empty state by the rising edge of D2BLP . In base SCP mode (e.g., for SCPW1:0 = 00), D1BCP is equal to BaseSCP , LD<7:0> equal to BaseLD<7:0> and no FIFO used. Generally, the data input rate of FIFO should be greater than the output one. To make FIFO work correctly, the following condition have to be satisfied by setting SFR properly. (SegNum/8 + 1) × tcw + 24 × tFPH < tLP − tLPH Here, SegNum is the segment number, and tCW D1BSCP clock cycle width. Referring 20H Figure 3.14.22, we can know this relation means that the last LD<7:0> data must be generated before the rising edge of D2BLP . For example, in case of fFPH =

36 MHz, XT = 32 kHz, 4 gray levels, 240 commons, 640 segments, and SDRAM burst

mode, the following table can be obtained, which tells user that 8 clock mode is impossible and base, 2, 4 clock modes can be used. Table 3.14.11 f FPH = 36 [MHz], XT = 32 [kHz], 4 Grayscale, 240 Common, 640 Segment, SDRAM Burst Mode SCPW D1BSCP Rate (MHz) tcw (ns) (SegNum/8 + 1) × tcw + 24 × tFPH (ns) tLP − tLPH (ns) Judgment Base 9 111.2 9674.4 31250 OK 2 CLK 9 111.2 9674.4 31250 OK 4 CLK 4.5 222.4 18681.6 31250 OK 8 CLK 2.25 444.8 36696 31250 Error Note: In case of SDRAM burst mode and 8/16 gray, t he speed of base setting is equal to that of 2 CLK. Figure 3.14.18 Timing Diagram for The LCD Driver Access Signals OUT − 1 OUT OUT + 1 OUT + 2 OUT + 3 OUT + 4 OUT − 1 OUT OUT + 1 OUT − 1 OUT fSYS D1BSCP LD7 to LD0 D1BSCP LD7 to LD0 D1BSCP LD7 to LD0 2-clock SCP 4-clock SCP 8-clock SCP

Note: D1BCP = BaseSCP and LD<7:0> = BaseLD<7:0> in BaseSCP mode (e.g., for SCPW<1:0> = 00) Figure 3.14.19 Timing Diagram for FIFO OUT + 1 80 bytes FIFO BaseSCP OUT OUT + 1 OUT fSYS/2, fSYS/4, fSYS/8 fSYS D2BLP BaseLD7 to BaseLD0 LD7 to LD0 D1BSCP

Note 1: 4t FPH ≤ T_bufdly ≤ tc + 2tFPH Note 2: T_busdly is about 11 times as long as f SYS period (22 tFPH). Figure 3.14.22 Timing Diagram for Maximum FIFO Delay Time OUT + 1 OUT + 1 OUT + 2 OUT + 2 OUT + 3 OUT + 1 IN + 2 IN + 3 IN + 4 IN + 5 IN + 6 IN + 7IN + 1 Row 227 fSYS A23 to A0 D15 to D0 BaseSCP LD7 to LD0 D1BSCP D2BLP IN OUTOUT OUT OUT tcw T_bufdly RD BaseLD7 to BaseLD0 T_busdly (SegNum/8) × tcw + T_bufdly tLPH tLP Column Monochrome

Note 1: Display memory support only 16-bit bus. Note 2: Other circuit is necessary for LCD drive power supply for LCD driver display. Figure 3.14.23 Interface Example for Shift Register Type LCD Driver Note: Because the connection between the line of disp lay RAM data and output bus: LD<0:7> is just the mirror invertion, please care of connection. The data LSB of display RAM is output from LD7. In the above figure, LD0 should be connected to DI7 of LCDD driver, and LD1 to DI6. For detail information, please refer to 21H Figure 3.14.11. VDD O001 VSS DIR TEST DI7 to DI0 DUAL SCP S/C VCCL/R, V0L/R, V1L/R, V4L/R, V5L/R O240 EIO2 EIO1 DSPOF FR LP VDD VSS DLEBCD D1BSCP D2BLP D3BFR DOFF LD0 to LD7 Control signal D0 to D15 A0 to A23 SCP LP FR DSPOF DI7 to DI0 EIO1 EIO2 DIR VDD S/C VSS TEST DUAL VCCLR V0LR, V2LR, VSSLR, V3LR, V5LR VDD VSS Open VSS Open Axx to Axx D0 to D15 Control signal O001 O240 COM001 240 commons × 240 segments LCD COM240 SEG001 SEG240 T6C13B (240-row driver selection) TMP92C820 Display memory (SDRAM/SRAM selection) T6C13B (240-column driver selection) Power circuit Power circuit

Figure 3.14.24 Display Reference below Sample Program 240 commons (Dots) 240 segments (Dots) 60 dots 60 dots 60 dots 60 dots 20 dots 20 dots Cursor blink (Black 2 Hz)

• Setting example: In case of use 240 segments × 240 commons, 4-level grayscale display, 64-Mbit SDRAM. This sample program operate correctly, LCD panel shows 22H Figure 3.14.18 display. ld (sdacr), 2bH ; Add-MUX enable, 64-Mbit select ld (sdrcr), 01H ; Interval refresh ld (lcdmode), 17H ; A/B area OFF, SDRAM 64 Mbits, SR type ; SCP width 2clocks ld (lcddvm), 11 ; 11-count DVM set ld (lcdsize), 32H ; COM = 240, SEG = 240 ld (lcdctl), 20H ; Divi de frame ON, display OFF ld (lcdffp), 240 ; Frame frequency correction (91 Hz) ld (lcdgl), 01H ; 4-level grayscale ld (lcdcm), 0c1H ; Cursor ON, Black, 2 Hz blink ld (lcdcw), 19 ; Width = 20 dots ld (lcdch), 19 ; Height = 20 dots ld (lcdcp), 00H ; Pixel = 0 ld (lcdcpl), 00H ; Cursor address ld (lcdcpm), 00H ; Cursor address ld (lcdcph), 40H ; Cursor address ld (lsarch), 40H ; C_area start address ld (lsarcm), 00H ; C_area start address ld (lsarcl), 00H ; C_area start address ld xix, 400000H ; ld wa, 0000H ; Write data 0/4-level data (0000000000000000B) loop1: ld (xix), wa ; inc 2, xix ; cp xix, 407800H ; 400000H to 4077FFH: 60 rows (Dots) jr nz, loop1 ; ld xix, 407800H ; ld wa, 05555H ; Write data 1/4-level data (0101010101010101B) loop2: ld (xix), wa ; inc 2, xix ; cp xix, 40F000H ; 407800H to 40EFFFH: 60 rows (Dots) jr nz, loop2 ; ld xix, 40F000H ; ld wa, 0aaaaH ; Write data 2/4-level data (1010101010101010B) loop3: ld (xix), wa ; inc 2, xix ; cp xix, 416800H ; 40F000H to 4167FFH: 60 rows (Dots) jr nz, loop3 ;

ld xix, 416800H ; ld wa, 0ffffH ; Write data 3/4-level data (1111111111111111B) loop4: ld (xix), wa ; inc 2, xix ; cp xix, 41e000H ; 416800H to 41DFFFH: 60 rows (Dots) jr nz, loop4 ; ld (lg0l), 00H ; 0/4 grayscale palette 0000B ld (lg1l), 05H ; 2/4 grayscale palette 0101B ld (lg2l), 0eH ; 3/4 grayscale palette 1110B ld (lg3l), 0fH ; 4/4 grayscale palette 1111B ld (lcdctl), 0a1H ; Display ON, divide ON

Data transmission to LCD driver is executed by move instruction of CPU. After setting mode of operation to control register, when move instruction of CPU is executed LCDC outputs chip select signal to LCD driver connected to the outside from control pin (D1BSCP etc.). Therefore control of data transmission numbers corresponding to LCD size is controlled by instruction of CPU. There are 2 kinds of address of LCD driver in this case, and which is chosen determines by LCDCTL<MMULCD> register. It corresponds to LCD driver which has every 1 byte of instruction register and display data register in LCD driver at the time of <MMULCD> = “0”. Please make the transmission place address at this time into either of FE0H to FE7F. (SEQUENTIAL ACCESS TYPE: See 23H Table 3.14.4.) It corresponds to address direct writing type LCD driver at the time of <MMULCD> = “1.” The transmission place address at this time can also assign the memory area of 3C0000H to 3FFFFF to four area for every 64 Kbytes. (RANDOM ACCESS TYPE) Note: This operation mode cannot use cursor function. 24H Figure 3.14.25 shows access timing example in <MMULCD> = “0”. Also, 25H Figure 3.14.26 shows example of connection. Note 1: This waveform is the case of 3-state access. Note 2: Note the different rising timing for D1BSCP etc. Figure 3.14.25 Example of Access Timing for RAM Built-in Type LCD Driver (Wait = 0) Data-out System clock: fSYS A23 to A0 R/W D1BSCP, D2BLP, D3BFR, DLEBCD D7 to D0 Data-in [Write cycle] [Read cycle]

Note: Other circuit is necessary for LCD drive power supply for LCD driver display. Figure 3.14.26 Interface Example for RAM Built-in Type Sequential Access Type LCD Driver VDD COM001 VSS VLC1, VLC2, VLC3, VLC4, VLC5 COM065 LE DB0 to DB5 DSPOF WR VDD VSS DLEBCD D1BSCP WR DOFF D0 to D7 CE WR D/I DSPOF DB0 to DB7 EIO1 EIO2 VDD VSS VLC2, VLC3 VLC5 VDD VSS Open SEG001 SEG080 COM001

65 COM × 80 SEG

(65-row driver) TMP92C820 T6B65A (80-column driver) Power circuit Power circuit

• Setting example: In case of use 80 segment × 65 commons LCD driver. Assign external column driver to LCDC1 and row driver to LCDR1. This example used LD instruction in setting of instruction and used burst function of micro DMA by soft start in setting of display data. In case of store 650 bytes transfer data to LCD driver. ; Setting external terminal LD (PDFC), 19H ; CE for LCDC1: D1BSCP , ; LE for LCDR1: DLEBCD, ; Setting for DOFF ; Setting for LCDC LD (LCDMODE), 00H ; Select RAM mode LD (LCDCTL), 00H ; Sequential access mode ; Setting for mode of LCDC1/LCDR1 LD (LCDC1L), XX ; Setti ng instruction for LCDC1 LD (LCDR1L), XX ; Setti ng instruction for LCDR1 ; Setting for micro DMA and INTTC (ch0) LD A, 08H ; Source address INC mode LDC DMAM0, A ; LD WA, 650 ; Count = 650 LDC DMAC0, WA ; LD XWA, 400000H ; Source address = 400000H LDC DMAS0, XWA ; LD XWA, 1FE1H ; Destination address = 1FE1H (LCDC0H) LDC DMAD0, XWA ; LD (INTETC01), 06H ; INTTC0 level = 6 EI 6 ; Interrupt level = 6 LD (DMAB), 01H ; Burst mode LD (DMAR), 01H ; Soft start

3.15 Melody/Alarm Generator (MLD)

The TMP92C820 contains a melody function an d alarm function, both of which are output from the MLDALM pin. Five kinds of fixed cycle interrupt are generated using a 15-bit counter for use as the alarm generator. The features are as follows. 1) Melody generator The Melody function generates signals of any frequency (4 Hz to 5461 Hz) based on a low-speed clock (32.768 kHz), and outputs the signals from the MLDALM pin. The melody tone can easily be heard by connecting an external loudspeaker. 2) Alarm generator The alarm function generates eight kinds of alarm waveform having a modulation frequency (4096 Hz) determined by the low-speed clock (32.768 kHz). This waveform can be inverted by setting a value to a register. The alarm tone can easily be heard by connecting an external loudspeaker. Five kinds of fixed cycle interrupts are ge nerated (1 Hz, 2 Hz, 64 Hz, 512 Hz, and 8192 Hz) by using a counter which is used for the alarm generator. This section is constituted as follows. 0H 3.15.1 1H Block Diagram 2H 3.15.2 3H Control Registers 4H 3.15.3 5H Operational Description 6H 3.15.3.1 7H Melody Generator 8H 3.15.3.2 9H Alarm Generator

3.15.1 Block Diagram

Figure 3.15.1 MLD Block Diagram MELFH, MELFL register Comparator (CP0) 12-bit counter (UC0) F/F Melody generator Edge detector ALMINT <IALM4E:0E> 15-bit counter (UC1) 8-bit counter (UC2) Alarm waveform generator ALM register Invert MELALMC <ALMINV> Selector ALMOUT MELOUT MELALMC <FC1:0> Internal data bus Reset MELFH <MELON> Stop and clea r Low-speed clock Invert MELOUT Alarm generator Internal data bus Reset INTALM0 (8192Hz) INTALM1 (512 Hz) INTALM2 (64 Hz) INTALM3 (2 Hz) INTALM4 (1 Hz) INTALMH (HALT release) MLDALM pin 4096 Hz Clea r MELALMC <MELALM>

3.15.2 Control Registers

Bit symbol AL8 AL7 AL6 AL5 AL4 AL3 AL2 AL1 ALM (1330H) Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Setting alarm pattern MELALMC Register 7 6 5 4 3 2 1 0 Bit symbol FC1 FC0 ALMINV − − − − MELALMMELALMC (1331H) Read/Write R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 0 Function Free-run counter control 00: Hold 01: Restart 10: Clear 11: Clear and start Alarm waveform invert 1: Invert Always write “0” Output waveform select 0: Alarm 1: Melody Note 1: MELALMC<FC1> is always read “0”. Note 2: When setting MELALMC register except <FC1:0> wh ile the free-run counter is running, <FC1:0> is kept “01”. MELFL Register 7 6 5 4 3 2 1 0 Bit symbol ML7 ML6 ML5 ML4 ML3 ML2 ML1 ML0 MELFL (1332H) Read/Write R/W After reset 0 0 0 0 0 0 0 0 Function Setting melody frequency (Lower 8 bits) MELFH Register 7 6 5 4 3 2 1 0 Bit symbol MELON ML11 ML10 ML9 ML8 MELFH (1333H) Read/Write R/W R/W After reset 0 0 0 0 0 Function Control melody counter 0: Stop and clear 1: Start Setting melody frequency (Upper 4 bits) ALMINT Register 7 6 5 4 3 2 1 0 Bit symbol − IALM4E IALM3E IALM2E IALM1E IALM0E ALMINT (1334H) Read/Write R/W R/W After reset 0 0 0 0 0 0 Function Always write “0” 1: Interrupt enable for INTALM4 to INTALM0

3.15.3 Operational Description

3.15.3.1 Melody Generator

The Melody function generates signals of any frequency (4 Hz to 5461 Hz) based on a low-speed clock (32.768 kHz) and outputs the signals from the MLDALM pin. The melody tone can easily be heard by connecting an external loud speaker. (Operation) MELALMC<MELALM> must first be set as 1 in order to select the melody waveform to be output from MLDALM. The melody output frequency must then be set to 12-bit registers MELFH and MELFL. The following are examples of settings and calculations of melody output frequency. (Formula for calculating of melody waveform frequency) at fs = 32.768 [kHz] Melody output waveform f MLD [Hz] = 32768/(2 × N + 4) Setting value for melody N = (16384/ fMLD) − 2 (Note: N = 1 to 4095 (001H to FFFH), 0 is not acceptable.) (Example program) When outputting an “A” musical note (440 Hz) LD (MELALMC), − − X X X X X 1 B ; Select melody waveform LD (MELFL), 23H ; N = 16384/440 − 2 = 35.2 = 023H LD (MELFH), 80H ; Start to generate waveform (Reference: Basic Musical Scale Setting Table) Scale Frequency [Hz] Register Value: N C 264 03CH D 297 035H E 330 030H F 352 02DH G 396 027H A 440 023H B 495 01FH C 528 01DH

3.15.3.2 Alarm Generator

The alarm function generates eight kinds of alarm waveform having a modulation frequency of 4096 Hz determined by the low-speed clock (32.768 kHz). This waveform is reversible by setting a value to a register. The alarm tone can easily be heard by connecting an external loud speaker . Five kinds of fixed cycle (interrupts can be generated 1 Hz, 2 Hz, 64 Hz, 512 Hz, 8 192 Hz) by using a counter which is used for the alarm generator. (Operation) MELALMC<MELALM> must first be set as 0 in order to select the alarm waveform to be output from MLDALMC. The “10” must be set on the MELALMC <FC1:0> register, and clear internal counter. Finally the alarm pattern must then be set on the 8-bit register of ALM. If it is inverted output-data, set <ALMINV> as invert. The following are examples of program, setting value of alarm pattern and waveform of each setting value. (Setting Value of Alarm Pattern) Setting Value for ALM Register Alarm Waveform 00H “0” fixed 01H AL1 pattern 02H AL2 pattern 04H AL3 pattern 08H AL4 pattern 10H AL5 pattern 20H AL6 pattern 40H AL7 pattern 80H AL8 pattern Other Undefined (do not set) (Example program) When outputting AL2 pattern (31.25 ms/8 times/1 s) LD (MELALMC), C0H ; Set output alarm waveform ; Free-run counter start LD (ALM), 02H ; Set AL2 pattern, start

Example: Waveform of alarm pattern for each setting value: Not inverted frequency (4096 Hz) 31.25 ms 1 s 1 2 8 1 500 ms 62.5 ms 1 s 1 2 1 62.5 ms 1 s 1 2 1 3 62.5 ms 62.5 ms 1 2 250 ms AL1 pattern (Continuous output) AL2 pattern (31.25 ms/8 times/1 s) AL3 pattern (500 ms/once) AL4 pattern (62.5 ms/twice/1 s) AL5 pattern (62.5 ms/3 times/1 s) AL6 pattern (62.5 ms/once) AL7 pattern (62.5 ms/twice) AL8 pattern (250 ms/once)

3.16 SDRAM Controller (SDRAMC)

TMP92C820 includes SDRAM controller which supports SDRAM access by CPU/LCDC. The features are as follows. (1) Support SDRAM 16-M/64-M/128-Mbit SDRAM (× 16 bits × 2/4 banks) 64-M/128-Mbit SDRAM (× 32 bits × 4 banks) (2) Automatic initialize function

• All bank pre-charge command generate
• Mode register set generate
• 8 times auto refresh (3) Access mode CPU Access LCDC Access Burst length 1 word Full page Addressing mode Sequential Sequential Cas latency (Clock) 2 2 Write mode Single write − (4) Access cycle
• CPU access (Read/write) Read cycle: 4 states (200 ns at fSYS =20 MHz) Write cycle: 3 states (150 ns at fSYS =20 MHz) Access data width: 8 bits/16 bits/32 bits
• LCDC burst access (Read only) Read cycle: 1 state (50 ns at fSYS =20 MHz) Over head: 4 states (200 ns at fSYS =20 MHz) Access data width: 16 bits/32 bits (5) Refresh cycle auto generate
• Auto refresh is generated while another area is being accessed.
• Refresh interval is programmable.
• Self refresh is supported Notes:
• Display data for LCDC must be set from the head of each page.
• Program is not operated on SDRAM.
• Condition of SDRAM’s area is set by CS1 setting of Memory Controller.

3.16.1 Control Registers

0H Figure 3.16.1 shows the SDRAMC control registers. Setting these registers controls the operation of SDRAMC. SDRAM Access Control Register 7 6 5 4 3 2 1 0 Bit symbol SDINI SDBUS1 SDBUS0 SMUXW1 SMUXW0 SMAC Read/Write R/W R/W R/W R/W After reset 0 0 0 0 0 0 Function Auto initialize 0: Disable 1: Enable Selecting structure of data bus 00: 16 bits × 1 01: 16 bits × 2 10: 32 bits × 1 Selecting address multiplex type 00: Type A 01: Type B 10: Type C 11: Reserved SDRAM controller 0: Disable 1: Enable SDRAM Refresh Control Register 7 6 5 4 3 2 1 0 Bit symbol SFRC SRS2 SRS1 SRS0 SASFRC SRC Read/Write R/W R/W R/W R/W After reset 0 0 0 0 0 0 Function Self refresh 0: Disable 1: Enable Refresh interval 000: 78 states 100: 195 states 001: 97 states 101: 210 states 010: 124 states 110: 249 states 011: 156 states 111: 312 states Auto self refresh 0: Disable 1: Enable Interval refresh 0: Disable 1: Enable Figure 3.16.1 SDRAMC Control Registers SDACR (0250H) SDRCR (0251H)

3.16.2 Operation Description

(1) Memory access control Access control block is enabled when SDACR<SMAC> = 1. And then SDRAM control signals (SDCSL, SDCSH, SDRAS, SDCAS, SDWE, SDLLDQM, SDLUDQM, SDULDQM, SDUUDQM, SDCLK and SDCKE) are operating during the time CPU or LCDC accesses CS1 area. 1. Address multiplex function In the access cycle, address multiplex outputs row/column address through A1 to A15 pin. And multiplex width is decided by setting SDACR<SMUXW0:1> of use memory size. The relation between multiplex width and memory sizeRow/Column address is below. Table 3.16.1 Address Multiplex Address of SDRAM Accessing Cycle Row Address 92C820 Pin Name Column Address Type A SDACR <SMUXW> = “00” Type B SDACR <SMUXW> = “01” Type C SDACR <SMUXW> = “10” A0 A0 A0 A0 A0 A1 A1 A9 A10 A11 A2 A2 A10 A11 A12 A3 A3 A11 A12 A13 A4 A4 A12 A13 A14 A5 A5 A13 A14 A15 A6 A6 A14 A15 A16 A7 A7 A15 A16 A17 A8 A8 A16 A17 A18 A9 A9 A17 A18 A19 A10 A10 A18 A19 A20 A11 A11 A19 A20 A21 A12 A12 A20 A21 A22 A13 A13 A21 A22 A23 A14 A14 A22 A23 A14 A15 A15 A23 A15 A15 2. Burst length SDRAM access by CPU is performed by the 1-word burst mode. And SDRAM access by LCDC is performed by the full-page burst mode. SDRAM accessing cycle number is depending on B1CSL register setting. For read cycle, setting of 4 states is necessary (B1CSL<B1WRn>). For write cycle, setting of 3 states is necessary (B1CSL<B1WWn>). In the burst read cycle by LCDC, a mode setup and a pre-charge cycle are automatically inserted in a read cycle front and back.

Figure 3.16.14 Timing of LCDC Burst Read Cycle SDUUDQM SDCLK SDCKE SDULDQM SDLUDQM SDLLDQM SDCSL SDCSH SDRAS SDCAS SDWE A11 A1 to A15 D0 to D31 RA Bank active Full page mode set RA 227 RD CA (n + 4)CA (n) D (n) CA (n + 8) CA (n + 12) 1-word mode set All bank precharge 85 states (320-byte read)

(2) Refresh control TMP92C820 can generate automatically an auto-refresh cycle for data maintenance of SDRAM. Auto-refresh cycle is generated by setting SDRCR<SRC> to “1”. Interval of auto refresh can be set by SDRCR<SRS0:2> from the 78 states to the 312 states (3.9 μs to 15.6 μs at 20 MHz). The generating timing of an auto-refresh cycle becomes into accessing cycles other than SDRAM area (CS1). The auto-refresh cycle is shown in 3H Figure 3.16.15 moreover, the interval of auto refresh is shown in 4H Table 3.16.2. Figure 3.16.15 Timing of Auto-refresh Cycle Table 3.16.2 Refresh Cycle Insertion Interval (Unit: μs) SDRCR<SRS0:2> fSYS Frequency (System clock) SRS2 SRS1 SRS0 Insertion Interval (State) 5 MHz 10 MHz 12.5 MHz 15 MHz 17.5 MHz 20 MHz It does not generate an auto-refresh cycle during the burst access to SDRAM by LCDC. The demand of auto-refresh cycle is held in this period. When it returns to CPU access cycle, an auto-refresh cycle is generated. Furthermore, TMP92C820 can to generate a self-refresh cycle. The timing of a self-refresh cycle is shown in 5H Figure 3.16.16. SDUUDQM SDCLK SDCKE SDULDQM SDLUDQM SDLLDQM SDCSL SDCSH SDRAS SDCAS SDWE Auto refresh 2 states

Figure 3.16.16 Timing of Self-refresh Cycle Note 1: When IDLE2 mode, continue with output clock. Therefore, If want to stop SDCLK, switch PF6 to output port before execution HALT instruction. Note 2: Pin condition in IDLE1/STOP mode depends on SYSCR2<DRVE> setting. However, when self-refresh mode, pin don’t depend on SYSCR2<DRVE>, and output low level. If SDRCR<SFRC> is set to “1”, the self-refresh cycle shown in 6H Figure 3.16.16 will occur. The self-refresh mode is used when using the standby mode (STOP , IDLE1), which an internal clock stops. In the case of standby mode using self refresh, please set SDRCR<SFRC> to “1”, before HALT instruction (STOP , IDLE1). Release of a self-refresh cycle is automatically performed by release in the standby mode. It inserts automatically one auto refresh after self refresh is released, and returns to the auto refresh mode. Note: When standby mode is cancelled by a reset, the I/O registers are initialized, therefore, auto refresh is not performed. Please do not place the command which accesses SDRAM, just before setting SDRCR<SFRC> to “1”. After setting SDRCR<SFRC> to “1”, at least 4 times of “NOP (s)” are required before halt command execution. Example: SET 7, (SDRCR) NOP NOP NOP NOP HALT * at least 4 times NOP(s). SDUUDQM SDCLK SDCKE SDULDQM SDLUDQM SDLLDQM SDCSL SDCSH SDRAS SDCAS SDWE Self-refresh entry Auto refresh Self-refresh exit

(3) SDRAM initialize TMP92C820 can generate the following SDRAM initialize routine after injection power-supply to SDRAM. The cycle is shown in 7H Figure 3.16.17. 1. Precharge of all banks 2. The initial configuration to a mode register 3. The auto-refresh cycle of 8 cycles The above cycle is generated by setting SDACR<SDINI> to “1”. While performing this cycle, operation (an instruction fetch, command execution) of CPU is stopped. In addition, before performing an initialization cycle, a port needs to be set as SDRAM control signal and an address signal (A1 to A12). After the initialization cycle is finished, SDACR<SDINI> is cleared to “0” automatically. Figure 3.16.17 Timing of Initialization Cycle SDUUDQM SDCLK SDCKE SDULDQM SDLUDQM SDLLDQM SDCSL SDCSH SDRAS SDCAS SDWE A11 A1 to A15 All bank precharge 220 620 Auto refresh 1-word mode set Auto refresh Auto refresh Auto refresh Auto refresh 8 times refresh cycle

(4) Connection example The example of connection with SDRAM is shown in 8H Figure 3.16.18 to 9H Figure 3.16.20. Table 3.16.3 Connection with SDRAM SDRAM Pin Name Data Bus Width 16 Bits Data Bus Width 32 Bits TMP92C820 Pin Name

16 Mbits 64 Mbits 128 Mbits

16 Mbits ×

16 Bits × 2

64 Mbits ×

32 Bits

128 Mbits ×

(A9) (A9) A2 A1 (A10) (A10) (A11) (A10) (A10) (A10) (A10) (A10) (A10) A3 A2 (A11) (A11) (A12) (A11) (A11) (A11) (A11) (A11) (A11) A4 A3 (A12) (A12) (A13) (A12) (A12) (A12) (A12) (A12) (A12) A5 A4 (A13) (A13) (A14) (A13) (A13) (A13) (A13) (A13) (A13) A6 A5 (A14) (A14) (A15) (A14) (A14) (A14) (A14) (A14) (A14) A7 A6 (A15) (A15) (A16) (A15) (A15) (A15) (A15) (A15) (A15) A8 A7 (A16) (A16) (A17) (A16) (A16) (A16) (A16) (A16) (A16) A9 A8 (A17) (A17) (A18) (A17) (A17) (A17) (A17) (A17) (A17) A10 A9 (A18) (A18) (A19) (A18) (A18) (A18) (A18) (A18) (A18) A11 A10 (A19) A10 (A19) A10 (A20) (A19) (A19) (A19) (A19) (A19) (A19) A12 BS (A20) A11 (A20) A11 (A21) A10 (A20) A10 (A20) A10 (A20) A10 (A20) A10 (A20) A10 (A20) A13 − BS0 (A21) BS0 (A22) BS (A21) BS (A21) A11 (A21) A11 (A21) BS0 (A21) A11 (A21) A14 − BS1 (A22) BS1 (A23) − − BS0 (A22) BS0 (A22) BS1 (A22) BS0 (A22) (A23) BS1 (A23) − BS1 (A23) SDCSL CS CS CS − CS − CS CS CS SDUUDQM − − − UDQM UDQM DQM3 DQM3 SDULDQM − − − LDQM LDQM DQM2 DQM2 SDLUDQM UDQM UDQM UDQM UDQM UDQM DQM1 DQM1 SDLLDQM LDQM LDQM LDQM LDQM LDQM DQM0 DQM0 SDRAS RAS RAS RAS RAS RAS RAS RAS RAS RAS SDCAS CAS CAS CAS CAS CAS CAS CAS CAS CAS SDWE WE WE WE WE WE WE WE WE WE SDCKE CKE CKE CKE CKE CKE CKE CKE CKE CKE SDCLK CLK CLK CLK CLK CLK CLK CLK CLK CLK SDACR <SDBUS> 00: 16 bits × 1 00: 16 bits × 1 00: 16 bits × 1 01: 16 bits × 2 01: 16 bits × 2 10: 32 bits × 1 10: 32 bits × 1 SDACR <SMUXW> 00: Type A 00: Type A 01: Type B 00: Ty pe A 00: Type A 00: Type A 00: Type A (An): Row address : Command address pin of SDRAM

Figure 3.16.18 Connection with SDRAM (1 Mwords × 16 bits) Figure 3.16.19 Connection with SDRAM (1 Mwords × 16 bits × 2) TMP92C820 SDRAM

1 Mwords × 4 banks × 16 bits

(A22) A14 (A21) A13 A12 to A1 D15 to D0 SDRAS SDCAS SDWE SDCSL SDLUDQM SDLLDQM CLK CKE BS1 BS0 A11 to A0 D15 to D0 RAS CAS WE CS UDQM LDQM TMP92C820 SDRAM (A23) A15 (A22) A14 A13 to A2 D31 to D0 SDRAS SDCAS SDWE SDCSH SDUUDQM SDULDQM SDCSL SDLUDQM SDLLDQM CLK CKE BS1 BS0 A11 to A0 D15 to D0 RAS CAS WE CS UDQM LDQM CLK CKE BS1 BS0 A11 to A0 D15 to D0 RAS CAS WE CS UDQM LDQM

Figure 3.16.20 Connection with SDRAM (512 kwords × 32 bits) SDCLK SDCKE (A22) A14 (A21) A13 A12 to A2 D31 to D0 SDRAS SDCAS SDWE SDCSL SDUUDQM SDULDQM SDLUDQM SDLLDQM CLK CKE BS1 BS0 A10 to A0 D31 to D0 RAS CAS WE CS DQM3 DQM2 DQM1 DQM0 TMP92C820 SDRAM 512 kwords × 4 banks × 32 bits

(5) Limitation point for SDRAM There are some points to notice when using SDRAMC. Please refer to the section under below and take care. 1) WAIT access When using SDRAM, it is added some limitation of access to all other memories. Under the WAIT pin input setting of Memory Controller, it is prohibited inserting the time over (14 × refresh interval time; in Auto Refresh function controlled by SDRAM controller). 2) Execution of SDRAM command before HALT instruction (SR(Self refresh)-Entry , Initialize , Mode-set) It requires execution time (a few states) to execute the command that SDRAMC has (SR- Entry, Initialize). Therefore when executing HALT instruction after the SDRAM command, please insert over 10 bytes NOP or other 10 bytes instructions before HALT instruction. 3) AR (Auto Refresh) interval time When using SDRAM, system clock freque ncy must be set suitable speed for SDRAM’s specification that is minimu m operating clock and minimum Refresh interval time. When using SDRAM under slow mode or down the Clock Gear, please design the system with special care for Auto Refresh interval time. And please set Auto Refresh interval time after adding 10 states to distributed Auto Refresh interval time, because it might not meet the A.C specification of SDRAM by stopping Auto Refresh. (Example of calculation) Condition: fSYS = 20MHz, SDRAM specification of distributed Auto Refresh interval time = 4096 times/64 ms 64ms/ 4096 times = 15.625 μs/1 time = 312.5state/1 time 312.5 – 10 = 302.5 state/less than 1 time is needed Æ 247 state is needed

4) Auto Exit problem when exiting from Self Refresh Mode of SDRAM When using Self Refresh function together with stand-by function of CPU or changing clock, it might not be suit specification of SDRAM. Because automatic releasing Self Refresh function (Auto Exit function) operates by CPU releasing HALT mode. Following figure shows example for avoid this problem by S/W. (Outline concept to control) *The target ports to change are SDCKE pin and SDCS pin. *The method of Self refresh Entry includes the condition 4). * SR : Self refresh , AR : Auto refresh HALT mode Gear-down or Change to Low clock Change to port Change CLK HALT Interrupt SR condition AR condition Auto EXIT SR condition SR condition General port setting SDRAM control pin Gear-up or Change to High clock fSYS CPU Port condition SDRAM controller internal condition SR ENTRY SR EXIT Change to port Change CLK SR ENTRY AR condition SDRAM condition AR condition AR condition AR condition SDRAM control pin 20MHz 32KHz

3.17 16-Bit Timer/Event Counters (TMRB) The TMP92C820 incorporates one multifunctional 16-bit timer/event counter (TMRB0) which have the following operation modes:

• 16-bit interval timer mode
• 16-bit event counter mode
• 16-bit programmable pulse generation (PPG) mode Timer/event counter consists of a 16-bit up co unter, two 16-bit timer registers (one of them with a double-buffer structure), a 16-bit captur e registers, two comparators, a capture input controller, a timer flip-flop and a control circuit. Timer/event counter is controlled by an 11-byte control SFR. This chapter consists of the following items:

3.17.1 Block Diagram

3.17.2 Operation

3.17.3 SFRs

3.17.4 Operation in Each Mode

(1) 16-bit timer mode (2) 16-bit programmable pulse generation (PPG) output mode Table 3.17.1 Pins and SFR of TMRB0 Channel Spec TMRB0 External clock/capture trigger input pins None External Pins Timer flip-flop output pins TB0OUT0 (also used as PC6) Timer run register TB0RUN (1180H) Timer mode register TB0MOD (1182H) Timer flip-flop control register TB0FFCR (1183H) TB0RG0L (1188H) TB0RG0H (1189H) TB0RG1L (118AH) Timer register TB0RG1H (118BH) TB0CP0L (118CH) TB0CP0H (118DH) TB0CP1L (118EH) SFR (Address) Capture register TB0CP1H (118FH)

Figure 3.17.1 Block Diagram of TMRB0 Internal data busInternal data bus Run/ clear Match detection 16-bit comparator (CP10) 16-bit up counter (UC10) 16-bit time register TB0RG1H/L Match detection Count clock TB0MOD<TB0CLK1:0> TB0RUN <TB0RDE> Slelector Capture, external INT input control TB1MOD <TB0CPM1:0> Prescaler clock: φT0 External INT input INT7 (Unused), INT8 (Unused) TA1OUT φT1 φT4 φT16 TB0RUN<TB0RUN> TB0MOD<TB0CLE> (from TMRA01) Capture register 0 TB0CP0H/L TB0MOD <TB0CP0I> Caputure register 1 TB0CP1H/L 32 16 8 4 2 φT1 φT4 φT16 TB0RUN <TB0PRUN> Internal data bus Internal data bus Timer flip-flop control TB0FF0 TB0FF1 TB0OUT0 TB0OUT1 (Unused) Overflow INT INTTBOF0 Timer flip-flop output Register 0 INTTB00 Register 1 INTTB01 INT output 16-bit comparator (CP11) 16-bit timer register TB0RG0H/L Register buffer 10 Timer flip-flop

(1) Prescaler The 5-bit prescaler generates the source clock for timer 0. The prescaler clock (φT0) is divided clock (Divided by 8) from the fFPH. This prescaler can be started or stopped using TB0RUN<TB0PRUN>. Counting starts when <TB0PRUN> is set to 1; the prescaler is cleared to 0 and stops operation when <TB0PRUN> is cleared to 0. Table 3.17.2 Prescaler Clock Resolution Timer counter input clock TMRB prescaler TB0MOD<TB0CLK1:0> Clock gear selection SYSCR1 <GEAR2:0> System clock selection SYSCR1 <SYSCK> − 1 (fs) fs/16 fs/64 fs/256 000 (1/1) fc/16 fc/64 fc/256 001 (1/2) fc/32 fc/128 fc/512 010 (1/4) fc/64 fc/256 fc/1024 011 (1/8) fc/128 fc/512 fc/2048 100 (1/16) 0 (fc) fc/256 fc/1024 fc/4096 (2) Up counter (UC10) UC10 is a 16-bit binary counter which counts up pulses input from the clock specified by TB0MOD<TB0CLK1:0>. Any one of the prescaler internal clocks φT1, φT4 and φT16 or an external clock input via the TB0IN0 pin can be selected as the input clock. Counting or stopping and clearing of the counter is controlled by TB0RUN<TB0RUN>. When clearing is enabled, the up counter UC10 will be cleared to 0 each time its value matches the value in the timer register TB0RG1H/L. If clearing is disabled, the counter operates as a free-running counter. Clearing can be enabled or disabled using TB0MOD<TB0CLE>. A timer overflow interrupt (INTTBOF0) is generated when UC10 overflow occurs.

(3) Timer registers (TB0RG 0H/L and TB0RG1H/L) These two 16-bit registers are used to set the interval time. When the value in the up counter UC10 matches the value set in th is timer register, the comparator match detect signal will go active. Setting data for both Upper and Lower timer registers is always needed. For example, either using a 2-byte data transfer instruction or using 1-byte date transfer instruction twice for the lower 8 bits and upper 8 bits in order. The TB0RG0H/L timer register has a double-buffer structure, which is paired with a register buffer. The value set in TB0RUN<TB0RDE> determines whether the double-buffer structure is enabled or disabled: It is disabled when <TB0RDE> = 0, and enabled when <TB0RDE> = 1. When the double buffer is enabled, data is transferred from the register buffer to the timer register when the values in the up counter (UC10) and the timer register TB0RG1H/L match. After a reset, TB0RG0H/L and TB0RG1H/L are undefined. If the 16-bit timer is to be used after a reset, data should be written to it beforehand. On a reset <TB0RDE> is initialized to 0, disabling the double buffer. To use the double buffer, write data to the timer register, set <TB0RDE> to 1, then write data to the register buffer as shown below. TB0RG0H/L and the register buffer both have the same memory addresses (001188H and 001189H) allocated to them. If <TB0RDE> = 0, the value is written to both the timer register and the register buffer. If <TB0RDE> = 1, the value is written to the register buffer only. The addresses of the timer registers are as follows: Note: The timer registers are write-only registers and thus cannot be read. Upper 8 bits (TB0RG0H) Lower 8 bits (TB0RG0L) TB0RG0H/L 1189H 1188H Upper 8 bits (TB0RG1H) Lower 8 bits (TB0RG1L) TB0RG1H/L 118BH 118AH TMRB0

(4) Capture registers (T B0CP0H/L, TB0CP1H/L) These 16-bit registers are used to latch the values in the up counters. All 16 bits of data in the capture registers should be read both Upper and Lower. For example, using a 2-byte data load instruction or two 1-byte data load instructions. The least significant byte is read first, followed by the most significant byte. The addresses of the capture registers are as follows: Note: The capture registers are read-onl y registers and thus cannot be written to. (5) Capture input control This circuit controls the timing to latch the value of the up counter UC10 into TB0CP0H/L, TB0CP1H/L. The value in the up counter can be loaded into a capture register by software. Whenever 0 is written to TB0MOD<TB0CP0I>, the current value in the up counter is loaded into capture register TB0CP0H/L. It is necessary to keep the prescaler in Run Mode (i.e., TB0RUN<TB0PRUN> must be held at a value of 1). Note: As described above, whenever 0 is programmed to TB0MOD<TB0CP0I>, the current value in the up counter is loaded into capture register TB0CP0H/L. However, note that the current value in the up count er is also loaded into capture register TB0CP0H/L when 1 is programmed to TB0MOD<TB0CP0I> while this bit is holding (6) Comparators (CP10 and CP11) CP10 and CP11 are 16-bit comparators which compare the value in the up counter UC10 with the value set in TB0RG0 or TB0RG1 respectively, in order to detect a match. If a match is detected, the comparator generates an interrupt (INTTB00 or INTTB01 respectively). (7) Timer flip-flops (TB0FF0) These flip-flops are inverted by the match detect signals from the comparators and the latch signals to the capture registers. Inversion can be enabled and disabled for each element using TB0FFCR<TB0C0T1, TB0E1T1, TB0E0T1>. After a reset the value of TB0FF0 is undefined. If “00” is written to TB0FFCR<TB0FF0C1:0>, TB0FF0 will be inverted. If “01” is written to the capture registers, the value of TB0FF0 will be set to “1”. If “10” is written to the capture registers, the value of TB0FF0 will be cleared to “0”. The values of TB0FF0 can be output via the timer output pin TB0OUT0 (which is shared with PC6). Timer output should be specified using the port C function register. Write to TBnMOD register TBnMOD <TBnCP0I> Capture operation Capture Capture Capture NOP Notice Upper 8 bits (TB0CP0H) Lower 8 bits (TB0CP0L) TB0CP0H/L 118DH 118CH TMRB0 Upper 8 bits (TB0CP1H) Lower 8 bits (TB0CP1L) TB0CP1H/L 118FH 118EH

Bit symbol TB0RDE − I2TB0 TB0PRUN TB0RUN Read/Write R/W R/W R/W R/W R/W After reset 0 0 0 0 0 TMRB0 Prescaler Up counter (UC10) Function Double buffer 0: Disable 1: Enable Always write “0”. IDLE2 0: Stop 1: Operate 0: Stop and clear 1: Run (Count up) Count operation

1 Count

Note: 1, 4, and 5 of TB0RUN are read as undefined values. Figure 3.17.2 The Registers for TMRB TB0RUN (1180H)

Bit symbol − − TB0CP0I TB0CPM1 TB0CPM0 TB0CLE TB0CLK1 TB0CLK0 Read/Write R/W W * R/W After reset 0 0 1 0 0 0 0 0 Function Always write “0”. Execute software capture 0: Software capture 1: Undefined Capture timing 00: Disable 01: Reserved 10: Reserved 11: TA1OUT↑ TA1OUT↓ Control up counter 0: Disable clearing 1: Enable clearing TMRB0 source clock 00: Reserved 01: φT1 10: φT4 11: φT16 TMRB0 source clock 01 φT1 10 φT4 11 φT16 Up counter (UC10) clear control 1 Enable clearing on match with TB0RG1H/L. Capture/interrupt timing Capture control

00 Disable

01 Reserved

10 Reserved

11 Capture to TB0CP0H/L at rising edge of TA1OUT

Capture to TB0CP1H/L at falling edge of TA1OUT Software capture

0 The value in the up counter is captured to

TB0CP0H/L.

1 Undefined (Note)

Note: Whenever programming “0” to TB0MOD<TB0CP0I> bit, present value of up counter is received to capture register TB0CP0H/L. But, program “1” to TB0MOD<TB0CP0I> in condition of programmed “0” to TB0MOD<TB0CP0I> bit, present value of up counter is received to capture register TB0CP0H/L. Therefore you must to regard. Figure 3.17.3 The Registers for TMRB TB0MOD (1182H) Prohibit read- modify- write

TMRB0 Flip-Flop Control Register 7 6 5 4 3 2 1 0 Bit symbol − − TB0C1T1 TB0C0T1 TB0E1T1 TB0E0T1 TB0FFC1 TB0FFC0 Read/Write W R/W W * After reset 1 1 0 0 0 0 1 1 TB0FF0 inversion trigger 0: Disable trigger 1: Enable trigger Function Always write “11”. Invert when the UC10 value is loaded into TB0CP1H/L. Invert when the UC10 value is loaded into TB0CP0H/L. Invert when the UC10 value matches the value in TB0RG1H/L. Invert when the UC10 value matches the value in TB0RG0H/L. Control TB0FF0 00: Invert 01: Set 10: Clear 11: Don’t care * Always read as 11. Timer flip-flop control (TB0FF0)

00 Invert

01 Set to 1

10 Clear to 0

Inverted when the UC10 value matches the value in TB0RG0H/L.

0 Disable trigger

1 Enable trigger

Inverted when the UC10 value matches the value in TB0RG1H/L. Inverted when the UC10 value is loaded in to TB0CP0H/L. Inverted when the UC10 value is loaded in to TB0CP1H/L. Figure 3.17.4 The Registers for TMRB TB0FFCR (1183H) Prohibit read- modify- write

bit Symbol − Read/Write W TB0RG0L (1188H) After reset Undefined bit Symbol − Read/Write W TB0RG0H (1189H) After reset Undefined bit Symbol − Read/Write W TB0RG1L (118AH) After reset Undefined bit Symbol − Read/Write W TB0RG1H (118BH) After reset Undefined bit Symbol − Read/Write W TB0CP0L (118CH) After reset Undefined bit Symbol − Read/Write W TB0CP0H (118DH) After reset Undefined bit Symbol − Read/Write W TB0CP1L (118EH) After reset Undefined bit Symbol − Read/Write W TB0CP1H (118FH) After reset Undefined Note: All registers are prohibited to execute read-modify-write instruction. Figure 3.17.5 The Registers for TMRB

(1) 16-bit timer mode Generating interrupts at fixed intervals In this example, the interrupt INTTB01 is set to be generated at fixed intervals. The interval time is set in the timer register TB0RG1H/L. 7 6 5 4 3 210 TB0RUN ← 0 0 X X − 0 X 0 Stop TMRB0. INTTB01 ← X 1 0 0 X 0 0 0 Enable INTTB01 and set interrupt level 4. Disable INTTB00. TB0FFCR ← 1 1 0 0 0 0 1 1 Disable the trigger. TB0MOD ← 0 0 1 0 0 1 ( = 01, 10, 11) Select internal clock for input and disable the capture function. TB0RG1 ← * * * * * * * * Set the interval time (16 bits). TB0RUN ← 0 0 X X − 1X1 S t a r t T M R B 0 . X: Don’t care, −: No change (2) 16-bit programmable pulse generation (PPG) output mode Square wave pulses can be generated at any frequency and duty ratio. The output pulse may be either low active or high active. The PPG mode is obtained by inversion of the timer flip-flop TB0FF0 that is enabled by the match of the up counter UC10 with timer register TB0RG0H/L or TB0RG1H/L and is output to TB0OUT0. In this mode the following conditions must be satisfied. (Value set in TB0RG0H/L) < (Value set in TB0RG1H/L) Figure 3.17.6 Programmable Pulse Generation (PPG) Output Waveforms When the TB0RG0 double buffer is enabled in this mode, the value of register buffer 0 will be shifted into TB0RG0 at match with TB0RG1. This feature facilitates the handling of low-duty waves. Figure 3.17.7 Operation of Register Buffer Match with TB0RG0 (INTTB00 interrupt) Match with TB0RG1 (INTTB01 interrupt) TB0OUT0 pin Shift into TB0RG1H/L Up counter = Q1 Up counter = Q2 Match with TB0RG0H/L Match with TB0RG1H/L TB0RG0H/L (Value to be compared) Register buffer 0 Write TB0RG0H/L

The following block diagram illustrates this mode. Figure 3.17.8 Block Diagram of 16-Bit Mode The following example shows how to set 16-bit PPG output mode: 7 6 5 4 3 210 TB0RUN ← 0 0 X X − 0 X 0 Disable the TB0RG0H/L double buffer and stop TMRB0. TB0RG0H/L ← * * * * * * * * Set the duty ratio (16 bits). TB0RG1H/L ← * * * * * * * * Set the frequency (16 bits). TB0RUN ← 1 0 X X − 0 X 0 Enable the TB0RG0H/L double buffer. (The duty and frequency are changed on an INTTB01 interrupt.) TB0FFCR ← 1 1 0 0 1 1 1 0 Set the mode to invert TB0FF0 at the match with TB0RG0H/L/TB0RG1H/L. Set TB0FF0 to 0. TB0MOD ← 0 0 1 0 0 1 ( = 01, 10, 11) Select the Prescaler output clock as the input clock and disable the capture function. PCFC ← X 1 − X − X − − Set PC6 to function as TB0OUT0. TB0RUN ← 1 0 X X − 1X1 S t a r t T M R B 0 . X: Don’t care, −: No change Selector Selector TB0RUN<TB0RDE> Match 16-bit up counter UC10 16-bit comparator Internal data bus TB0RG1H/L TB0RG0H/L-WR φT1 φT4 φT16 TB0OUT0 (PPG output) TB0RUN<TB0RUN> Clear Register buffer 10 TB0RG0H/L 16-bit comparator F/F (TB0FF0)

3.18 PSB (Power supply backup)

The power supply input of TMP92C820 is divided into three systems as follows;

• Analog power supply input (AVCC to AVSS)
• Digital power supply input (DVCC to DVSS)
• Digital power supply input for RTC (RTCVCC to DVSS) The individual power supply input is isolated from each other. Figure 3.18.1 Power Supply Input System Figure 3.18.2 Outside Circuit Example for PSB XT2 XT1BE DVSS1 to DVSS4AVSS CPU control and Other logic ADC control RTC control High OSC Low-OSC AVCC DVCC1 to DVCC3 RTCVCC TMP92C820 BE RTC 32K_OSC TMP92C820 Sub battery for RTC Main power source for CPU and Other device DVCC RTCVCC DVSS

1. Electrical Characteristics

4.1 Absolute Maximum Ratings

Parameter Symbol Rating Unit Power supply voltage V CC −0.5 to 4.0 Input voltage V IN −0.5 to VCC + 0.5 V Output current (Per pin) I OL 2 Output current (Per pin) I OH −2 Output current (Total) ΣIOL 80 Output current (Total) ΣIOH −80 mA Power dissipation (Ta = 85°C) P D 600 mW Soldering temperature (10 s) Tsolder 260 Storage temperature Tstg −65 to +150 Operation temperature Topr −20 to +70 Note: The absolute maximum ratings are rated values that must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, the device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products that include this device, ensure that no absolute maximum rating value will ever be exceeded. Solderability of lead-free products Test parameter Test condition Note (1) Use of Sn-37Pb solder Bath Solder bath temperature =230ºC, Dipping time = 5 seconds The number of times = one, Use of R-type flux Solderability (2) Use of Sn-3.0Ag-0.5Cu solder bath Solder bath temperature =245 ºC, Dipping time = 5 seconds The number of times = one, Use of R-type flux (use of lead-free) Pass: solderability rate until forming ≥95%

4.2 DC Electrical Characteristics

VCC = 3.3 ± 0.3 V/X1 = 4 to 40 MHz/Ta = −20 to 70°C Parameter Symbol Condition Min Typ. Max Unit Power supply voltage (DVCC = AVCC = RTCVCC) (DVSS = AVSS = 0 V) VCC X1 = 4 to 40 MHz (Internal 2 to 20 MHz) XT1 = 30 to 34 kHz 3.0 3.6 V Input low voltage D0 to D7 P10 to P17 (D8 to D15) P20 to P27 (D16 to D23) P30 to P37 (D24 to D31) V IL0 0.6 Input low voltage P40 to P47 P50 to P57 P60 to P67 P76 P95 PF0, PF3 PG0 to PG4 PL0 to PL7 V IL1 0.3V CC Input low voltage P90 to P94, P96 PA0 to PA7 PC0, PC1, PC3, PC5, PC6 PF1, PF2, PF4, PF5 BE RESET VIL2 0.25V CC Input low voltage AM0 to AM1 VIL3 0.3 Input low voltage X1, XT1 V IL4 −0.3 0.2V CC V Input high voltage D0 to D 7 P10 to P17 (D8 to D15) P20 to P27 (D16 to D23) P30 to P37 (D24 to D31) V IH0 2.0 Input high voltage P40 to P47 P50 to P57 P60 to P67 P76 P95 PF0, PF3 PG0 to PG4 PL0 to PL7 V IH1 0.7 × VCC Input high voltage P90 to P94, P96 PA0 to PA7 PC0, PC1, PC3, PC5, PC6 PF1, PF2, PF4, PF5 BE RESET VIH2 0.75 × VCC Input high voltage AM0 to AM1 VIH3 VCC − 0.3 Input high voltage X1, XT1 V IH4 0.8 × VCC VCC + 0.3 V

VCC = 3.3 ± 0.3 V/X1 = 4 to 40 MHz/Ta = −20 to 70°C Parameter Symbol Condition Min Typ. Max Unit Output low voltage V OL I OL = 1.6 mA 0.45 V Output high voltage V OH I OH = −400 μA 2.4 V Input leakage current I LI 0.0 ≤ Vin ≤ VCC 0.02 ±5 μA Output leakage current I LO 0.2 ≤ Vin ≤ VCC − 0.2 0.05 ±10 μA Power down voltage at STOP (for internal RAM backup) VSTOP VIL2 = 0.2 VCC, VIH2 = 0.8 VCC 1.8 3.6 V Pull-up resistor RESET R RST Programmable pull-up resistor R KH 100 400 k Ω Pin capacitance C IO fc = 1 MHz 10 pF Schmitt width V TH P90 to P94, P96, PA0 to PA7, PC0, PC1, PC3, PC5, PC6, PF1, PF2, PF4, PF5, BE , RESET 0.4 1.0 V Operating current (NORMAL) ICC 37.0 60 mA IDLE2 mode ICC IDLE2 26.0 39 mA IDLE1 mode ICC IDLE1 DVCC = 3.6 V, X1 = 40 MHz (Internal 20 MHz) 2.7 5.0 mA STOP ICC STOP DV CC = 3.6 V 0.4 15 μA SLOW ICCS 43.0 100 μA SLOW, IDEL2 mode ICCS IDLE2 30.0 70 μA SLOW, IDLE1 mode ICCS IDLE1 DVCC = 3.6 V, XT1 = 32.768 kHz (Internal 15.8625 kHz) 8.0 40 μA RTCVCC = 3.6 V, XT1 = 32.768 kHz 4.0 7.0 RTC VCC power dissipation ICCRTC RTCVCC = 2.0 V, XT1 = 32.768 kHz 1.0 2.0 μA

4.3 AC Characteristics

4.3.1 Basic Bus Cycle

Read cycle V CC = 3.3 ± 0.3 V/X1 = 4 to 40 MHz/Ta = −20 to 70°C No. Parameter Symbol Min Max at 20 MHz at 16 MHz Unit 1 OSC period (X1/X2) t OSC 25 250 25 31.25 ns 2 System clock period ( = T) t CYC 50 500 50 62.5 ns 3 SDCLK low width t CL 0.5T − 15 10 16 ns 4 SDCLK low width t CH 0.5T − 15 10 16 ns 5-1 A0 to A23 valid → D0 to D31 input at 0 waits tAD 2.0T − 30 70 95 ns 5-2 A0 to A23 valid → D0 to D31 input at 1 wait tAD3 3.0T − 30 120 157.5 ns 6-1 RD fall → D0 to D31 input at 0 waits tRD 1.5T − 30 45 63.75 ns 6-2 RD fall → D0 to D31 input at 1 wait tRD3 2.5T − 30 95 126.25 ns 7-1 RD low width at 0 waits t RR 1.5T − 20 55 74 ns 7-2 RD low width at 1 wait t RR3 2.5T − 20 105 136 ns 8 A0 to A23 valid → RD fall t AR 0.5T − 20 5 11 ns 9 RD rise → SDCLK rise t RK 0.5T − 20 5 11 ns

10 A0 to A23 valid → D0 to D31 hold t HA 0 0 0 ns

11 RD rise → D0 to D31 hold t HR 0 0 0 ns

12 WAIT setup time t TK 15 15 15 ns

13 WAIT hold time t KT 5 5 5 ns

14 Data byte control access time for SRAM t SBA 1.5T − 30 45 63.75 ns Write cycle V CC = 3.3 ± 0.3 V/X1 = 4 to 40 MHz/Ta = −20 to 70°C No. Parameter Symbol Min Max at 20 MHz at 16 MHz Unit 15-1 D0 to D31 valid → WRxx rise at 0 waits t DW 1.25T − 35 28 43 ns 15-2 D0 to D31 valid → WRxx rise at 1 wait t DW3 2.25T − 35 78 106 ns 16-1 WRxx low width at 0 waits t WW 1.25T − 30 33 48 ns 16-2 WRxx low width at 1 wait t WW3 2.25T − 30 83 111 ns 17 A0 to A23 valid → WR fall t AW 0.5T − 20 5 11 ns 18 WRxx fall → SDCLK rise t WK 0.5T − 20 5 11 ns 19 WRxx rise → A0 to A23 hold t WA 0.25T − 5 8 11 ns 20 WRxx rise → D0 to D31 hold t WD 0.25T − 5 8 11 ns 21 RD rise → D0 to D31 output t RDO 0.5T − 5 20 26.25 ns 22 Write pulse width for SRAM t SWP 1.25T − 30 32.5 48.125 ns 23 Data byte control to end of write for SRAM t SBW 1.25T − 30 32.5 48.125 ns 24 Address setup time for SRAM t SAS 0.5T − 20 5 11.25 ns 25 Write recovery time for SRAM t SWR 0.25T − 5 7.5 10.625 ns 26 Data setup time for SRAM t SDS 1.25T − 35 27.5 43.125 ns 27 Data hold time for SRAM t SDH 0.25T − 5 7.5 10.625 ns AC condition

• Output: High = 0.7 VCC, Low = 0.3 VCC, CL = 50 pF
• Input: High = 0.9 VCC, Low = 0.1 VCC

(1) Read cycle (0 waits) Note: The phase relation between X1 input signal and the other signals is unsettled. The timing chart above is an example. SDCLK tCH tTK tAD tHA tHR tRR tSBA WAIT A0 to A23 D0 to D31 SRxB Data-in tOSC CSx RD SRWR tCYC tAR tRK tRD

(2) Write cycle (0 waits) Note: The phase relation between X1 input signal and the other signals is unsettled. The timing chart above is an example. SDCLK A0 to A23 D0 to D31 WAIT RD Data-out tOSC tCH t CL tCYC tTK tKT tAW t WK tWA tWW tDW tWD tSWR tSDH tSBW tSDS tSWPtSAS CSx WRxx SRxB SRWR tRDO

(3) Read cycle (1 wait) (4) Write cycle (1 wait) A0 to A23 WAIT Data-in tRD3 tRR3 tAD3 SDCLK D0 to D31 RD CSx A0 to A23 WAIT Data-out SDCLK D0 to D31 RD CSx tWW3 tDW3 tRD0 WRxx

4.3.2 Page ROM Read Cycle

(1) 3-2-2-2 mode V CC = 3.3 ± 0.3 V/X1 = 4 to 40 MHz/Ta = −20 to 70°C No. Parameter Symbol Min Max at 20 MHz at 16 MHz Unit 1 System clock period ( = T) t CYC 50 500 50 62.5 ns 2 A0 and A1 → D0 to D31 input t AD2 2.0T − 50 50 75 ns 3 A2 to A23 → D0 to D31 input t AD3 3.0T − 50 100 138 ns 4 RD fall → D0 to D31 input t RD3 2.5T − 45 80 111 ns

5 A0 to A23 invalid → D0 to D31 hold t HA 0 0 0 ns

6 RD rise → D0 to D31 hold t HR 0 0 0 ns

• Output: High = 0.7VCC, Low = 0.3VCC, CL = 50 pF
• Input: High = 0.9VCC, Low = 0.1VCC (2) Page ROM read cycle (3-2-2-2 mode) tHA Data-in Data-in Data-in Data-in tCYC A0 to A23 SDCLK D0 to D31 RD CS2 +0 +1 +2 +3 tAD3 tAD2 tAD2 tAD2 tHRtRD3tHAtHAtRD3

4.4 SDRAM Controller AC Electrical Characteristics

V CC = 3.3 ± 0.3 V/X1 = 4 to 40 MHz/Ta = −20 to 70°C Variable at 20 MHz at 16 MHz No. Parameter Symbol Min Max Min Max Min Max Unit

1 Ref/active to Ref/active command period t RC 2T 100 125 ns

2 Active to precharge command period t RAS 2T 100 125 ns

3 Active to read/write command delay time t RCD T 50 62.5 ns 4 Precharge to active command period t RP T 50 62.5 ns 5 Active to active command period t RRD 3T 150 187.5 ns 6 Write recovery time (CL * = 2) t WR T 50 62.5 ns 7 CLK cycle time (CL * = 2) t CK T 50 62.5 ns 8 CLK high level width t CH 0.5T − 15 10 16.25 ns 9 CLK low level width t CL 0.5T − 15 10 16.25 ns 10 Access time from CLK (CL * = 2) t AC T − 30 20 32.5 ns

11 Output data hold time t OH 0 0 0 ns

12 Data-in setup time t DS T − 35 15 27.5 ns 13 Data-in hold time t DH T − 5 45 57.50 ns 14 Address setup time t AS 0.75T − 35 2.5 11.88 ns

15 Address hold time t AH 3 3 3 ns

16 CKE setup time t CKS 0.5T − 15 10 16.25 ns 17 Command setup time t CMS 0.5T − 15 10 16.25 ns 18 Command hold time t CMH 0.5T − 15 10 16.25 ns 19 Mode register set cycle time t RSC T 50 62.5 ns Note 1: CL* is CAS latency. Note 2: AC measuring conditions

• Output level: High = 0.7 VCC, Low = 0.3 VCC, CL = 50 pF
• Input level: High = 0.9 VCC, Low = 0.1 VCC.

• SDRAM read timing (CPU ac cess or LCDC normal access) tCH Data-in A1 to A10 SDCLK D0 to D15 16-bit data bus Row Column Row Column Row Column tCL tRP tRCD tRAS tRP tCMS tCMS tCMH tCMH tRRD tAHtAS tAS tAH tAC tOH SDxDQM SDCS SDRAS SDCAS SDWE A11 A12 to A15 Data-in A1 to A11 D0 to D31 32-bit data bus Row Column Row Column Row Column tAHtAS tAS tAH tAC tOH A12 A13 to A15 tCK

• SDRAM write timing (CPU access) tCH Data-out A1 to A12 SDCLK D0 to D15 16-bit data bus Row Column Row Column Row Column tCL tRP tRCD tWR tRP tCMS tCMS tCMH tAHtAS tAS tAH tDS tDH SDxDQM SDCS SDRAS SDCAS SDWE A11 A12 to A15 A1 to A11 D0 to D31 32-bit data bus A12 A13 to A15 tCK tRRD tCMH tRAS Data-out Row Column Row Column Row Column tAHtAS tAS tAH tDS tDH

• SDRAM burst read timing (Start of burst cycle) Data-in A1 to A11 or A1 to A10 SDCLK D0 to D31 Row Column Row Column tRP tCMS tCM tAHtAS tAC SDxDQM SDCS SDRAS SDCAS SDWE A12 or A11 A13 to A15 or A12 to A15 tCK tRCD tCMS tCM tCM tCM 227 Row0 tAC Data-in Data-in tAC tOH tOH tAH tAS tAS

• SDRAM burst read timing (End of burst cycle) Data-in A1 to A11 or A1 to A10 SDCLK D0 to D31

220 Column

0 Column Row

• SDRAM initialize timing A1 to A12 SDCLK 220 tCMS tAS SDxDQM SDCS SDRAS SDCAS SDWE A20 to A23 (BS0 and BS1) tCK tCM tCH tRSC tRC tCL tCMS tCM tCM tCM tAH tAS

• SDRAM refresh timing
• SDRAM self refresh timing SDCLK tCMS SDxDQM SDCS SDRAS SDCAS SDWE tCK tRC tRC tCM tCMS tCM tCK tCKS tCKS tRC SDCLK SDxDQM SDCS SDRAS SDCAS SDWE SDCKE

4.5 AD Conversion Characteristics

Parameter Symbol Min Typ. Max Unit Analog reference voltage (+) V REFH V CC − 0.2 V CC V CC Analog reference voltage (−) V REFL VSS VSS VSS + 0.2 AD converter power supply voltage A VCC V CC V CC V CC AD converter ground A VSS VSS VSS VSS Analog input voltage A VIN VREFL VREFH V Analog current for analog reference voltage <VREFON> = 1 0.8 1.2 mA Analog current for analog reference voltage <VREFON> = 0 IREF 0.02 5.0 UA Total error (Quantize error of ±0.5 LSB is included) ET ±1.0 ±4.0 LSB

4.6 Event Counter (TI0, TI4, TI8, TI9, TIA, and TIB)

Variable 20 MHz 16 MHz Parameter Symbol Min Max Min Max Min Max Unit Clock cycle T VCK 8T + 100 500 600 ns Clock low width T VCKL 4T + 40 240 290 ns Clock high width T VCKH 4T + 40 240 290 ns

4.7 Serial Channel Timing

(1) SCLK input mode (I/O interface mode) Variable 20 MHz 16 MHz Parameter Symbol Min Max Min Max Min Max Unit SCLK cycle T SCY 16T 0.8 1.0 μs Output data → SCLK rise T OSS TSCY/2 − 4T − 110 90 140 SCLK rise → Output data hold T OHS TSCY/2 + 2T + 0 500 625 SCLK rise → Input data hold T HSR 0 0 0 SCLK rise → Input data valid T SRD T SCY − 0 800 1000 Input data → SCLK rise T RDS 0 0 ns (2) SCLK output mode (I/O interface mode) Variable 20 MHz 16 MHz Parameter Symbol Min Max Min Max Min Max Unit SCLK cycle (Programmable) T SCY 16T 8192T 0.8 409.6 1.0 512 μs Output data → SCLK rise T OSS T SCY/2 − 40 360 460 SCLK rise → Output data hold T OHS T SCY/2 − 40 360 460 SCLK rise → Input data hold T HSR 0 0 0 SCLK rise → Input data valid T SRD TSCY − 1T − 180 570 757.5 Input data → SCLK rise T RDS 0 0 0 ns SCLK Output mode/ Input rising mode SCLK (Input falling mode) tSCY Input data RXD

0 Output data

4.8 Interrupt Operation

Variable 20 MHz 16 MHz Parameter Symbol Min Max Min Max Min Max Unit INT0 to INT3 low width T INTAL 4T + 40 200 290 INT0 to INT3 high width T INTAH 4T + 40 200 290 ns

4.9 LCD Controller SR Mode

V CC = 3.3 ± 0.3 V/X1 = 4 to 40 MHz/Ta = −20 to 70°C Variable

20 MHz

(tm = 0)

16 MHz

(tm = 0) No. Parameter Symbol Min Max Min Max Min Max Unit 1 Data vaild → D1BSCP fall t DSU 0.5T − 20 + tm 5 11.25 ns 2 D1BSCP fall → Data hold t DHD 0.5T − 5 + tm 20 26.25 ns 3 D1SBCP → Clock high width t CWH 0.5T − 10 + tm 15 21.25 ns 4 D1BSCP → Clock low width t CWL 0.5T − 10 + tm 15 21.25 ns 5 D1BSCP → Clock cycle t CW T + 2tm 50 62.5 ns Note: tm = (2scpw − 1) ×, e.g., if Scpw = 3 (8 clock mode) and 20 MHz, tm = (23 − 1) × 50 = 350 LD0 to LD7 out tDHDtDSU LD0 to LD7 D1BSCP tCWL tCWH tCW

4.10 Recommended Oscillation Circuit

The TMP92C820 has been evaluate by below the oscillator vender below. Use this information when selecting external parts. Note: The total load value of the oscillation is the sum of external loads (C1 and C2) and the floating load of the actual assembled board. There is a possibility of operating error when using C1 and C2 values in the table below. When designing the board, design the minimum length pattern around the oscillator. We also recommend that oscillator evaluation be carried out using the actual board. (1) Connection example Figure 4.10.1 High-frequency Oscillator F igure 4.10.2 Low-frequency Oscillator (2) TMP92C820 recommended ceramic oscillator: Murata Manufacturing Co., Ltd; JAPAN Note 1: The figure in parentheses ( ) under C1 and C2 is the built-in condenser type. Note 2: The product numbers and specificati ons of the osillators made by Murata Manufacturing Co., Ltd. are subject to change. For up-to-date information, please refer to the following URL: http://www.murata.co.jp/ Parameter of Elements Running Condition MCU Oscillation Frequency [MHz] Type Oscillator Product number C1 [pF] Note1 [pF] Note1 Rf [Ω] Rd [Ω] Voltage [V] Tc [ °C] 2.000 SMD CSTCC2M00G56-R0 (47) (47) Open 0 1.8~2.7 SMD CSTCR4M00G55-R0 (39) (39) Open 0 4.000 Lead CSTLS4M00G56-B0 (47) (47) Open 0 SMD CSTCR6M00G55-R0 (39) (39) Open 0 6.000 Lead CSTLS6M00G56-B0 (47) (47) Open 0 SMD CSTCE10M0G52-R0 (10) (10) Open 0 CSTLS10M0G53-B0 (15) (15) Open 0 2.7~3.6 10.000 Lead CSTLS10M0G53-B0 (15) (15) Open 0

12.000 SMD CSTCE12M5G52-R0 (10) (10) Open 0

1.8~2.7 TMP92C820FG 20.000 SMD CSTCG20M0V53-R0 (15) (15) Open 0 2.7~3.6 −20~ +80 X1 X2 C2 C1 Rd XT1 XT2 C2 C1 Rd

1. Table of Special Function Registers (SFRs) The SFRs (Special function registers) include the I/O ports and peripheral control registers allocated to the 8-Kbyte address space from 000000H to 001FFFH. (1) I/O port (2) I/O port control (3) Interrupt control (4) DMA controller (5) Memory controller (6) MMU (7) Clock gear (8) LCD controller (9) SDRAM controller (10) 8-bit timer (11) 16-bit timer (12) UART/serial channel (13) I 2C bus/serial channel (14) AD converter (15) Watchdog timer (16) RTC (Real time clock) (17) Melody/alarm generator Table layout Note: “Prohibit RMW” in the table means that y ou cannot use RMW instructions on these registers. Example) When setting bit0 only of the register P0CR, the instruction “SET 0, (PxCR)” cannot be used. The LD (Transfer) instruction must be used to write all eight bits. Read/Write R/W: Both read and write are possible. R: Only read is possible. W: Only write is possible. W*: Both read and write are possible (when this bit is read as 1). Prohibit RMW: Read-modify-write instru ctions are prohibited. (EX, ADD, ADC, BUS, SBC, INC, DEC,AND, OR, XOR, STCF, RES, SET, CHG, TSET, RLC, RRC, RL, RR, SLA, SRA, SLL, SRL, RLD, RRD instructions are read-modify-write instructions.) Prohibit RMW *: Read-modify-write is prohibited when controlling the pull-up resistor. Symbol Address Name 7 6 1 0 Bit symbol Read/Write Initial value after reset Remarks

Table 5.1 I/O Register Address Map [1] Port Address Name Address Name Address Name Address Name 0000H AH BH CH DH EH FH P1CR P1FC P2CR P2FC P3CR P3FC 0010H AH BH CH DH EH FH P4CR P4FC P5CR P5FC P6CR P6FC P7CR P7FC 0020H AH BH CH DH EH FH P8FC2 P8FC P9ODE P9CR P9FC PA PAFC 0030H AH BH CH DH EH FH PC PCCR PCFC PF PFCR PFFC Address Name Address Name 0040H AH BH CH DH EH FH PG PJ PJFC2 PJFC 0050H AH BH CH DH EH FH PK PKFC PL PLCR PLFC Note: Do not access un-named addresses.

[2] INTC [3] DMAC Address Name Address Name Address Name Address Name 00D0H AH BH CH DH EH FH INTE12 INTE3 INTETA01 INTETA23 INTETB01 INTETBO0 INTES0 INTES1 00E0H AH BH CH DH EH FH Reserved Reserved Reserved INTESB0 Reserved INTALM01 INTALM23 INTALM4 INTERTC INTEKEY INTLCD Reserved Reserved INTES2 INTEP0 00F0H AH BH CH DH EH FH INTE0AD INTETC01 INTETC23 INTETC45 INTETC67 SIMC IIMC INTWDT INTCLR 0100H AH BH CH DH EH FH DMA0V DMA1V DMA2V DMA3V DMA4V DMA5V DMA6V DMA7V DMAB DMAR Reserved [4] MEMC [5] MMU Address Name Address Name Address Name Address Name 0140H AH BH CH DH EH FH B0CSL B0CSH MAMR0 MSAR0 B1CSL B1CSH MAMR1 MSAR1 B2CSL B2CSH MAMR2 MSAR2 B3CSL B3CSH MAMR3 MSAR3 0150H AH BH CH DH EH FH BEXCSL BEXCSH 0160H AH BH CH DH EH FH PMEMCR 01D0H AH BH CH DH EH FH LOCAL0 LOCAL1 LOCAL2 LOCAL3 Note: Do not access un-named addresses.

[6] CGEAR [7] LCDC-1 Address Name Address Name Address Name 10E0H AH BH CH DH EH FH SYSCR0 SYSCR1 SYSCR2 EMCCR0 EMCCR1 EMCCR2 Reserved Reserved Reserved 0200H AH BH CH DH EH FH LCDMODE LCDDVM LCDSIZE LCDCTL LCDFFP LCDGL LCDCM LCDCW LCDCH LCDCP LCDCPL LCDCPM LCDCPH Reserved 0210H AH BH CH DH EH FH LSARAM LSARAH LEARAM LEARAH LSARBM LSARBH LEARBM LEARBH LSARCL LSARCM LSARCH [7] LCDC-2 Address Name Address Name Address Name 0220H AH BH CH DH EH FH LG0L LG0H LG1L LG1H LG2L LG2H LG3L LG3H LG4L LG4H LG5L LG5H LG6L LG6H LG7L LG7H 0230H AH BH CH DH EH FH LG8L LG8H LG9L LG9H LGAL LGAH LGBL LGBH LGCL LGCH LGDL LGDH LGEL LGEH LGFL LGFH 0240H AH BH CH DH EH FH Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Note: Do not access un-named addresses.

[8] SDRAMC [9] 8-bit timer [10] 16-bit timer Address Name Address Name Address Name 0250H AH BH CH DH EH FH SDACR SDRCR 1100H AH BH CH DH EH FH TA01RUN TA0REG TA1REG TA01MOD TA01FFCR TA23RUN TA2REG TA3REG TA23MOD TA3FFCR 1180H AH BH CH DH EH FH TB0RUN TB0MOD TB0FFCR TB0RG0L TB0RG0H TB0RG1L TB0RG1H TB0CP0L TB0CP0H TB0CP1L TB0CP1H [11] SIO [12] SBI Address Name Address Name Address Name 1200H AH BH CH DH EH FH SC0BUF SC0CR SC0MOD0 BR0CR BR0ADD SC0MOD1 SIRCR SC1BUF SC1CR SC1MOD0 BR1CR BR1ADD SC1MOD1 1210H AH BH CH DH EH FH SC2BUF SC2CR SC2MOD0 BR2CR BR2ADD SC2MOD1 1240H AH BH CH DH EH FH SBI0CR1 SBI0DBR I2C0AR SBI0CR2/SBI0SR SBI0BR0 SBI0BR1 Note: Do not access un-named addresses.

[13] 10-bit ADC [14] WDT Address Name Address Name Address Name 12A0H AH BH CH DH EH FH ADREG0L ADREG0H ADREG1L ADREG1H ADREG2L ADREG2H ADREG3L ADREG3H ADREG4L ADREG4H Reserved Reserved Reserved Reserved Reserved Reserved 12B0H AH BH CH DH EH FH ADMOD0 ADMOD1 ADMOD2 Reserved 1300H AH BH CH DH EH FH WDMOD WDCR [15] RTC [16] MLD Address Name Address Name 1320H AH BH CH DH EH FH SECR MINR HOURR DAYR DATER MONTHR YEARR PAGER RESTR 1330H AH BH CH DH EH FH ALM MELALMC MELFL MELFH ALMINT Note: Do not access un-named addresses.

(1) I/O port Symbol Name Address 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 R/W P1 Port 1 0004H Data from external port (Output latch register is cleared to 0) P27 P26 P25 P24 P23 P22 P21 P20 R/W P2 Port 2 0008H Data from external port (Output latch register is cleared to 0) P37 P36 P35 P34 P33 P32 P31 P30 R/W P3 Port 3 000CH Data from external port (Output latch register is cleared to 0) P47 P46 P45 P44 P43 P42 P41 P40 R/W P4 Port 4 0010H Data from external port (Output latch register is cleared to 0) P57 P56 P55 P54 P53 P52 P51 P50 R/W P5 Port 5 0014H Data from external port (Output latch register is cleared to 0) P67 P66 P65 P64 P63 P62 P61 P60 R/W Data from external port (Output latch register is cleared to 0) P6 Port 6 0018H P76 P75 P74 P73 P72 P71 P70 R/W P7 Port 7 001CH Data from external port Note1 1 1 1 1 1 1 P87 P86 P85 P84 P83 P82 P81 P80 R/W P8 Port 8 0020H 1 1 1 1 1 0 1 1 P96 P95 P94 P93 P92 P91 P90 R/W P9 Port 9 0024H Data from external port (Output latch register is set to 1) PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 R PA Port A 0028H Data from external port PC6 PC5 PC3 PC1 PC0 R/W R/W R/W PC Port C 0030H Data from external port Note2 Data from external port Note2 Data from external port Note2 PF5 PF4 PF3 PF2 PF1 PF0 R/W PF Port F 003CH Data from external port (Output latch register is set to 1) PG4 PG3 PG2 PG1 PG0 R PG Port G 0040H Data from external port PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 R/W PJ Port J 004CH 1 1 1 1 1 1 1 1 PK6 PK4 PK3 PK2 PK1 PK0 R/W R/W PK Port K 0050H 1 1 1 1 1 1 PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 R/W PL Port L 0054H Data from external port (Output latch register is set to 1) Note 1: Output latch register is cleared to 0. Note 2: Output latch register is set to 1

(2) I/O port control (1/3) Symbol Name Address 7 6 5 4 3 2 1 0 P17C P16C P15C P14C P13C P12C P11C P10C W 0 0 0 0 0 0 0 0 P1CR Port 1 control register 0006H (Prohibit RMW) 0: Input 1: Output P 1 F W

1 P1FC

(Prohibit RMW) 0: Port 1:Data bus (D8 to D15) P27C P26C P25C P24C P23C P22C P21C P20C W 0 0 0 0 0 0 0 0 P2CR Port 2 control register 000AH (Prohibit RMW) 0: Input 1: Output P 2 F W 0 / 1 P2FC Port 2 function register 000BH (Prohibit RMW) 0: Port 1: Data bus (D16 to D23) P37C P36C P35C P34C P33C P32C P31C P30C W 0 0 0 0 0 0 0 0 P3CR Port 3 control register 000EH (Prohibit RMW) 0: Input 1: Output P 3 F W 0 / 1 P3FC Port 3 function register 000FH (Prohibit RMW) 0: Port 1: Data bus (D24 to D31) P47C P46C P45C P44C P43C P42C P41C P40C W 0 0 0 0 0 0 0 0 P4CR Port 4 control register 0012H (Prohibit RMW) 0: Input 1: Output P47F P46F P45F P44F P43F P42F P41F P40F W 1 1 1 1 1 1 1 1 P4FC Port 4 function register 0013H (Prohibit RMW) 0: Port 1: Address bus (A0 to A7) P57C P56C P55C P54C P53C P52C P51C P50C W 0 0 0 0 0 0 0 0 P5CR Port 5 control register 0016H (Prohibit RMW) 0: Input 1: Output P57F P56F P55F P54F P53F P52F P51F P50F W 1 1 1 1 1 1 1 1 P5FC Port 5 function register 0017H (Prohibit RMW) 0: Port 1: Address bus (A8 to A15) P67C P66C P65C P64C P63C P62C P61C P60C W 0 0 0 0 0 0 0 0 P6CR Port 6 control register 001AH (Prohibit RMW) 0: Input 1: Output P67F P66F P65F P64F P63F P62F P61F P60F W 1 1 1 1 1 1 1 1 P6FC Port 6 function register 001BH (Prohibit RMW) 0: Port 1: Address bus (A16 to A23)

I/O port control (2/3) Symbol Name Address 7 6 5 4 3 2 1 0 P76C W

0 P7CR

(Prohibit RMW) 0: Input 1: Output P76F P75F P74F P73F P72F P71F P70F W 0 0 0 0 0 0 1 P7FC Port 7 function register 001FH (Prohibit RMW) 0: Port 1: WAIT 0: Port 1: R/W 0: Port WRUU 0: Port WRUL 0: Port WRLU 0: Port WRLL 0: Port RD P87F − P85F P84F P83F P82F P81F P80F W 1 0 0 0 0 0 0 0 P8FC Port 8 function register 0023H (Prohibit RMW) 0: Port 1: SDCLK Always write 0. 0: Port 1: EA25 0: Port 1: EA24 0: Port CS3 0: Port 1: CS2 0: Port CS1 0: Port CS0 − P86F2 P85F2 P84F2 − P82F2 P81F2 P80F2 W 0 0 0 0 0 0 0 0 P8FC2 Port 8 function register 2 0021H (Prohibit RMW) Always write “0” 0: <P86F> 1: CS2D 0: <P85F> 1: CS2C 0: <P84F> CS2B Always write “0”. 0: <P82F> 1: CS2A 0: <P81F> 1: SDCSL 0: <P80F> SDCSH P96C P95C P94C P93C P92C P91C P90C W 0 0 0 0 0 0 0 P9CR Port 9 control register 0026H (Prohibit RMW) 0: Input 1: Output P96F P95F P94F P93F P92F P91F P90F W 0 0 0 0 0 0 0 P9FC Port 9 function register 0027H (Prohibit RMW) 0: Port 1: RXD2, CSEXA 0: Port 1: TXD2, CS2G 0: Port 1: CS2F 0: Port CS2E 0: Port, SI 1: SCL Note 0: Port 1: SO, SDA 0: Port, SCK input 1: SCK output Not e P95ODE − − P92ODE P91ODE W 0 0 0 0 0 P9ODE Port 9 ODE register 0025H (Prohibit RMW) 0: 3 states 1: Open drain Always write “0” Always write “0” 0: 3 states 1: Open drain 0: 3 states 1: Open drain PA7F PA6F PA5F PA4F PA3F PA2F PA1F PA0F W 0 0 0 0 0 0 0 0 PAFC Port A function register 002BH (Prohibit RMW) 0: KEY-IN disable 1: KEY-IN enable PC6C PC5C PC3C PC1C PC0C W W W 0 0 0 0 0 PCCR Port C control register 0032H (Prohibit RMW) 0: Input 1: Output 0: Input 1: Output 0: Input 1: Output PC6F PC5F PC3F PC1F PC0F W W W 0 0 1 0 0 PCFC Port C function register 0033H (Prohibit RMW) 0: Port 1: INT3 TB0OUT0 0: Port 1: INT2 TA3OUT 0: Port 1: INT0 0: Port 1: INT1 TA1OUT 0: Port 1: TA0IN Note : When using SI and SCK input function, set P9FC<P92F, P90F> to “0” (Function setting).

I/O port control (3/3) Symbol Name Address 7 6 5 4 3 2 1 0 PF5C PF4C PF3C PF2C PF1C PF0C W 0 0 0 0 0 0 PFCR Port F control register 003EH (Prohibit RMW) 0: Input 1: Output PF5F PF3F PF2F PF0F W W W 0 0 0 0 PFFC Port F function register 003FH (Prohibit RMW) 0: Port 1: SCLK1 output 0: Port 1: TXD1 0: Port 1: SCLK0 output 0: Port 1: TXD0 PJ7F PJ6F PJ5F PJ4F PJ3F PJ2F PJ1F PJ0F W 0 0 0 0 0 0 0 0 PJFC Port J function register 004FH (Prohibit RMW) 0: Port 1: SDCKE 0: Port 1: SDUUDQM 0: Port 1: SDULDQM 0: Port 1: SDLUDQM 0: Port 1: SDLLDQM 0: Port SDWE 0: Port SDCAS 0: Port SDRAS − PF6F2 PF5F2 PF4F2 PF3F2 PF2F2 − − W 0 0 0 0 0 0 0 0 PJFC2 Port J function register 2 004DH (Prohibit RMW) Always write “0”. 0: <PJ6F> 1: SRUUB 0: <PJ5F> 1: SRULB 0: <PJ4F> SRLUB 0: <PJ3F> SRLLB 0: <PJ2F> SRWR Always write “0”. Always write “0”. PK6F PK4F PK3F PK2F PK1F PK0F W W 0 0 0 0 0 0 PKFC Port K function register 0053H (Prohibit RMW) 0: Port 1: ALARM at <PK6> = 1 1: MLDALM at <PK6> = 0 0: Port 1: DOFFB 0: Port 1: DLEBCD 0: Port 1: D3BFR 0: Port 1: D2BLP 0: Port 1: D1BSCP PL7C PL6C PL5C PL4C PL3C PL2C PL1C PL0C W 0 0 0 0 0 0 0 0 PLCR Port L control register 0056H (Prohibit RMW) 0: Input 1: Output PL7F PL6F PL5F PL4F PL3F PL2F PL1F PL0F W 0 0 0 0 0 0 0 0 PLFC Port L function register 0057H (Prohibit RMW) 0: Port 1: Data bus for LCDC (LD7 to LD0)

(3) Interrupt control (1/3) Symbol Name Address 7 6 5 4 3 2 1 0 INT2 INT1 I2C I2M2 I2M1 I2M0 I1C I1M2 I1M1 I1M0 R R/W R R/W 0 0 0 0 0 0 0 0 INTE12 INT1& INT2 enable 00D0H 1: INT2 Level of request interrupt 1: INT1 Level of request interrupt − INT3 − − − − I3C I3M2 I3M1 I3M0 − − R R/W − − − − 0 0 0 0 INTE3 INT3 enable 00D1H Always write “0”. 1: INT3 Level of request interrupt INTTA1 (TMRA1) INTTA0 (TMRA0) ITA1C ITA1M2 ITA1M1 ITA1M0 IT A0C ITA0M2 ITA0M1 ITA0M0 R R/W R R/W 0 0 0 0 0 0 0 0 INTETA01 INTTA0& INTTA1 enable 00D4H 1: INTTA1 Level of request interrupt 1: INTTA0 Level of request interrupt INTTA3 (TMRA3) INTTA2 (TMRA2) ITA3C ITA3M2 ITA3M1 ITA3M0 IT A2C ITA2M2 ITA2M1 ITA2M0 R R/W R R/W 0 0 0 0 0 0 0 0 INTETA23 INTTA2& INTTA3 enable 00D5H 1: INTTA3 Level of request interrupt 1: INTTA2 Level of request interrupt INTTB1 (TMRB1) INTTB0 (TMRB0) ITB1C ITB1M2 ITB1M1 ITB1M0 IT B0C ITB0M2 ITB0M1 ITB0M0 R R/W R R/W 0 0 0 0 0 0 0 0 INTETB01 INTTB0& INTTB1 enable 00D8H 1: INTTB1 Level of request interrupt 1: INTTB0 Level of request interrupt − INTTBO0 − − − − ITBO0C ITBO0M2 ITBO0M1 ITBO0M0 − − R R/W − − − − 0 0 0 0 INTETBO0 INTTBO0 (Overflow) enable 00DAH Always write “0”. 1: INTTBO0 Level of request interrupt INTTX0 INTRX0 ITX0C ITX0M2 ITX0M1 ITX0M0 IRX0C IRX0M2 IRX0M1 IRX0M0 R R/W R R/W 0 0 0 0 0 0 0 0 INTES0 INTRX0& INTTX0 enable 00DBH 1: INTTX0 Level of request interrupt 1: INTRX0 Level of request interrupt INTTX1 INTRX1 ITX1C ITX1M2 ITX1M1 ITX1M0 IRX1C IRX1M2 IRX1M1 IRX1M0 R R/W R R/W 0 0 0 0 0 0 0 0 INTES1 INTRX1& INTTX1 enable 00DCH 1: INTTX1 Level of request interrupt 1: INTRX1 Level of request interrupt − INTSBE0 − − − − ISBE0C ISBE0M2 ISBE0M1 ISBE0M0 − − R R/W − − − − 0 0 0 0 INTESB0 INTSBE0 enable 00E3H Always write “0”. 1: INTSBE0 Level of request interrupt INTALM1 INTALM0 IA1C IA1M2 IA1M1 IA1M0 IA0C IA0M2 IA0M1 IA0M0 R R/W R R/W 0 0 0 0 0 0 0 0 INTEALM01 INTALM0 INTALM1 enable 00E5H 1: INTALM1 Level of request interrupt 1: INTALM0 Level of request interrupt INTALM3 INTALM2 IA3C IA3M2 IA3M1 IA3M0 IA2C IA2M2 IA2M1 IA2M0 R R/W R R/W 0 0 0 0 0 0 0 0 INTEALM23 INTALM2 INTALM3 enable 00E6H 1: INTALM3 Level of request interrupt 1: INTALM2 Level of request interrupt

Interrupt control (2/3) Symbol Name Address 7 6 5 4 3 2 1 0 − INTALM4 − − − − IA4C IA4M2 IA4M1 IA4M0 − − R R/W − − − − 0 0 0 0 INTEALM4 INTALM4 enable 00E7H Always write “0”. 1: INTALM4 Level of request interrupt − INTRTC − − − − IRC IRM2 IRM1 IRM0 − − R R/W − − − − 0 0 0 0 INTERTC INTRTC enable 00E8H Always write “0”. 1: INTRTC Level of request interrupt − INTKEY − − − − IKC IKM2 IKM1 IKM0 − − R R/W − − − − 0 0 0 0 INTECKEY INTKEY enable 00E9H Always write “0”. 1: INTKEY Level of request interrupt − INTLCD − − − − ILCD1C ILCDM2 ILCDM1 ILCDM0 − − R R/W − − − − 0 0 0 0 INTLCD INTLCD enable 00EAH Always write “0”. 1: INTLCD Level of request interrupt INTTX2 INTRX2 ITX2C ITX2M2 ITX2M1 ITX2M0 IRX2C IRX2M2 IRX2M1 IRX2M0 R R/W R R/W 0 0 0 0 0 0 0 0 INTES2 INTRX2& INTTX2 enable 00EDH 1: INTTX2 Level of request interrupt 1: INTRX2 Level of request interrupt − INTP0 − − − − IP0C IP0M2 IP0M1 IP0M0 − − R R/W − − − − 0 0 0 0 INTEP0 INTP0 enable 00EEH Always write “0”. 1: INTP0 Level of request interrupt

Interrupt control (3/3) Symbol Name Address 7 6 5 4 3 2 1 0 INTAD INT0 IADC IADM2 IADM1 IADM0 I0C I0M2 I0M1 I0M0 R R/W R R/W 0 0 0 0 0 0 0 0 INTE0AD INT0& INTAD enable 00F0H 1: INTAD Level of request interrupt 1: INT0 Level of request interrupt INTTC1 (DMA1) INTTC0 (DMA0) ITC1C ITC1M2 ITC1M1 ITC1M0 ITC0C ITC0M2 ITC0M1 ITC0M0 R R/W R R/W 0 0 0 0 0 0 0 0 INTETC01 INTTC0& INTTC1 enable 00F1H 1: INTTC1 Level of request interrupt 1: INTTC0 Level of request interrupt INTTC3 (DMA3) INTTC2 (DMA2) ITC3C ITC3M2 ITC3M1 ITC3M0 ITC2C ITC2M2 ITC2M1 ITC2M0 R R/W R R/W 0 0 0 0 0 0 0 0 INTETC23 INTTC2& INTTC3 enable 00F2H 1: INTTC3 Level of request interrupt 1: INTTC2 Level of request interrupt INTTC5 (DMA5) INTTC4 (DMA4) ITC5C ITC5M2 ITC5M1 ITC5M0 ITC4C ITC4M2 ITC4M1 ITC4M0 R R/W R R/W 0 0 0 0 0 0 0 0 INTETC45 INTTC4& INTTC5 enable 00F3H 1: INTTC5 Level of request interrupt 1: INTTC4 Level of request interrupt INTTC7 (DMA7) INTTC6 (DMA6) ITC7C ITC7M2 ITC7M1 ITC7M0 ITC6C ITC6M2 ITC6M1 ITC6M0 R R/W R R/W 0 0 0 0 0 0 0 0 INTETC67 INTTC6& INTTC7 enable 00F4H 1: INTTC7 Level of request interrupt 1: INTTC6 Level of request interrupt IR2LE IR1LE IR0LE W 1 1 1 SIMC SIO interrupt mode control 00F5H (Prohibit RMW) 0: INTRX2 edge mode 1: INTRX2 level mode 0: INTRX1 edge mode 1: INTRX1 level mode 0: INTRX0 edge mode 1: INTRX0 level mode I3EDGE I2EDGE I1EDGE I0EDGE I0LE − W R/W 0 0 0 0 0 0 IIMC Interrupt input mode control 00F6H (Prohibit RMW) INT3EDGE 0: Rising 1: Falling INT2EDGE 0: Rising 1: Falling INT1EDGE 0: Rising 1: Falling INT0EDGE 0: Rising 1: Falling 0: INT0 edge mode 1: INT0 l level mode Always write “0”. − INTWD − − R − INTWDT INTWD 00F7H Always write “0”. 1: I NTWD − CLRV7 CLRV6 CLRV5 CLRV4 CLRV3 CLRV2 CLRV1 CLRV0 W 0 0 0 0 0 0 0 0 INTCLR Interrupt clear control 00F8H (Prohibit RMW) Interrupt vector

(4) DMA controller Symbol Name Address 7 6 5 4 3 2 1 0 DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 R/W 0 0 0 0 0 0 DMA0V DMA0 start vector 0100H DMA0 start vector DMA1V5 DMA1V4 DMA1V3 DMA1V2 DMA1V1 DMA1V0 R/W 0 0 0 0 0 0 DMA1V DMA1 start vector 0101H DMA1 start vector DMA2V5 DMA2V4 DMA2V3 DMA2V2 DMA2V1 DMA2V0 R/W 0 0 0 0 0 0 DMA2V DMA2 start vector 0102H DMA2 start vector DMA3V5 DMA3V4 DMA3V3 DMA3V2 DMA3V1 DMA3V0 R/W 0 0 0 0 0 0 DMA3V DMA3 start vector 0103H DMA3 start vector DMA4V5 DMA4V4 DMA4V3 DMA4V2 DMA4V1 DMA4V0 R/W 0 0 0 0 0 0 DMA4V DMA4 start vector 0104H DMA4 start vector DMA5V5 DMA5V4 DMA5V3 DMA5V2 DMA5V1 DMA5V0 R/W 0 0 0 0 0 0 DMA5V DMA5 start vector 0105H DMA5 start vector DMA6V5 DMA6V4 DMA6V3 DMA6V2 DMA6V1 DMA6V0 R/W 0 0 0 0 0 0 DMA6V DMA6 start vector 0106H DMA6 start vector DMA7V5 DMA7V4 DMA7V3 DMA7V2 DMA7V1 DMA7V0 R/W 0 0 0 0 0 0 DMA7V DMA7 start vector 0107H DMA7 start vector DBST7 DBST6 DBST5 DBST4 D BST3 DBST2 DBST1 DBST0 R/W 0 0 0 0 0 0 0 0 DMAB DMA burst 0108H 1: DMA request on burst mode DREQ7 DREQ6 DREQ5 DREQ4 DRE Q3 DREQ2 DREQ1 DREQ0 R/W 0 0 0 0 0 0 0 0 DMAR DMA request 0109H (Prohibit RMW) 1: DMA request in software

(5) Memory controller (1/3) Symbol Name Address 7 6 5 4 3 2 1 0 B0WW2 B0WW1 B0WW0 B0WR2 B0WR1 B0WR0 W W 0 1 0 0 1 0 B0CSL BLOCK0 MEMC control register low 0140H (Prohibit RMW) Write waits 001: 2 states (0 waits) 010: 3 states (1 wait) 101: 4 states (2 waits) 110: 5 states (3 waits) 111: 6 states (4 waits) 011: WAIT pin input mode Others: (Reserved) Read waits 001: 2 states (0 waits) 010: 3 states (1 wait) 101: 4 states (2 waits) 110: 5 states (3 waits) 111: 6 states (4 waits) 011: WAIT pin input mode Others: (Reserved) B0E B0REC B0OM1 B0OM0 B0BUS1 B0BUS0 W W 0 0 0 0 0 0 B0CSH BLOCK0 MEMCT control register high 0141H (Prohibit RMW) CS select 0: Disable 1: enable 0: No insert dummy cycle (Default) 1: Insert dummy cycle 00: ROM/SRAM 01: Reserved 10: Reserved 11: Reserved Data bus width 00: 8 bits 01: 16 bits 10: 32 bits 11: Reserved B1WW2 B1WW1 B1WW0 B1WR2 B1WR1 B1WR0 W W 0 1 0 0 1 0 B1CSL BLOCK1 MEMC control register low 0144H (Prohibit RMW) Write waits 001: 2 states (0 waits) 010: 3 states (1 wait) 101: 4 states (2 waits) 110: 5 states (3 waits) 111: 6 states (4 waits) 011: WAIT pin input mode Others: (Reserved) Read waits 001: 2 states (0 waits) 010: 3 states (1 wait) 101: 4 states (2 waits) 110: 5 states (3 waits) 111: 6 states (4 waits) 011: WAIT pin input mode Others: (Reserved) B1E B1REC B1OM1 B1OM0 B1BUS1 B1BUS0 W W 0 0 0 0 0 0 B1CSH BLOCK1 MEMC control register high 0145H (Prohibit RMW) CS select 0: Disable 1: Enable 0: No insert dummy cycle (Default) 1: Insert dummy cycle 00: ROM/SRAM 01: Reserved 10: Reserved 11: SDRAM Data bus width 00: 8 bits 01: 16 bits 10: 32 bits 11: Reserved B2WW2 B2WW1 B2WW0 B2WR2 B2WR1 B2WR0 W W 0 1 0 0 1 0 B2CSL BLOCK2 MEMC control register low 0148H (Prohibit RMW) Write waits 001: 2 states (0 waits) 010: 3 states (1 wait) 101: 4 states (2 waits) 110: 5 states (3 waits) 111: 6 states (4 waits) 011: WAIT pin input mode Others: (Reserved) Read waits 001: 2 states (0 waits) 010: 3 states (1 wait) 101: 4 states (2 waits) 110: 5 states (3 waits) 111: 6 states (4 waits) 011: WAIT pin input mode Others: (Reserved) B2E B2M B2REC B2OM1 B2OM0 B2BUS1 B2BUS0 W W 1 0 0 0 0 0/1 0/1 B2CSH BLOCK2 MEMC control register high 0149H (Prohibit RMW) CS select 0: Disable 1: Enable 0: 16 Mbytes 1: Sets area 0: No insert dummy cycle (Default) 1: Insert dummy cycle 00: ROM/SRAM 01: Reserved 10: Reserved 11: Reserved Data bus width 00: 8 bits 01: 16 bits 10: 32 bits 11: Reserved

Memory controller (2/3) Symbol Name Address 7 6 5 4 3 2 1 0 B3WW2 B3WW1 B3WW0 B3WR2 B3WR1 B3WR0 W W 0 1 0 0 1 0 B3CSL BLOCK3 MEMC control register low 014CH (Prohibit RMW) Write waits 001: 2 states (0 waits) 010: 3 states (1 wait) 101: 4 states (2 waits) 110: 5 states (3 waits) 111: 6 states (4 waits) 011: WAIT pin input mode Others: (Reserved) Read waits 001: 2 states (0 waits) 010: 3 states (1 wait) 101: 4 states (2 waits) 110: 5 states (3 waits) 111: 6 states (4 waits) 011: WAIT pin input mode Others: (Reserved) B3E B3REC B3OM1 B3OM0 B3BUS1 B3BUS0 W W 0 0 0 0 0 0 B3CSH BLOCK3 MEMC control register high 014DH (Prohibit RMW) CS select 0: Disable 1: Enable 0: No insert dummy cycle (Default) 1: Insert dummy cycle 00: ROM/SRAM 01: Reserved 10: Reserved 11: Reserved Data bus width 00: 8 bits 01: 16 bits 10: 32 bits 11: Reserved BEXWW2 BEXWW1 BEXWW0 BEXWR2 BEXWR1 BEXWR0 W W 0 1 0 0 1 0 BEXCSL BLOCK EX MEMC control register low 0158H Prohibit RMW Write waits 001: 2 states (0 waits) 010: 3 states (1 wait) 101: 4 states (2 waits) 110: 5 states (3 waits) 111: 6 states (4 waits) 011: WAIT pin input mode Others: (Reserved) Read waits 001: 2 states (0 waits) 010: 3 states (1 wait) 101: 4 states (2 waits) 110: 5 states (3 waits) 111: 6 states (4 waits) 011: WAIT pin input mode Others: (Reserved) BEXOM1 BEXOM0 BEXBUS1 BEXBUS0 W 0 0 0 0 BEXCSH BLOCK EX MEMC control register high 0159H (Prohibit RMW) 00: ROM/SRAM 01: Reserved 10: Reserved 11: Reserved Data bus width 00: 8 bits 01: 16 bits 10: 32 bits 11: Reserved OPGE OPWR1 OPWR0 PR1 PR0 R / W 0 0 0 1 0 PMEMCR Page ROM control register 0166H ROM page access 0: Disable 1: Enable Wait number on page 00: 1 state (n-1-1-1 mode) 01: 2 states (n-2-2-2 mode) 10: 3 states (n-3-3-3 mode) 11: (Reserved) Byte number in a page 00: 64 bytes 01: 32 bytes 10: 16 bytes (Default) 11: 8 bytes

Memory control (3/3) Symbol Name Address 7 6 5 4 3 2 1 0 M0V20 M0V19 M0V18 M0V17 M0V16 M0V15 M0V14-9 M0V8 R/W 1 1 1 1 1 1 1 1 MAMR0 Memory register 0 0142H 0: Compare enable 1: Compare disable M0S23 M0S22 M0S21 M0S20 M0S19 M0S18 M0S17 M0S16 R/W 1 1 1 1 1 1 1 1 MSAR0 Memory start address register 0 0143H Set start address A23 to A16 M1V21 M1V20 M1V19 M1V18 M1V17 M1V16 MV15-9 M1V8 R/W 1 1 1 1 1 1 1 1 MAMR1 Memory address mask register 1 0146H 0: Compare enable 1: Compare disable M1S23 M1S22 M1S21 M1S20 M1S19 M1S18 M1S17 M1S16 R/W 1 1 1 1 1 1 1 1 MSAR1 Memory start address register 1 0147H Set start address A23 to A16 M2V22 M2V21 M2V20 M2V19 M2V18 M2V17 M2V16 M2V15 R/W 1 1 1 1 1 1 1 1 MAMR2 Memory register 2 014AH 0: Compare enable 1: Compare disable M2S23 M2S22 M2S21 M2S20 M2S19 M2S18 M2S17 M2S16 R/W 1 1 1 1 1 1 1 1 MSAR2 Memory start address register 2 014BH Set start address A23 to A16 M3V22 M3V21 M3V20 M3V19 M3V18 M3V17 M3V16 M3V15 R/W 1 1 1 1 1 1 1 1 MAMR3 Memory register 3 014EH 0: Compare enable 1: Compare disable M3S23 M3S22 M3S21 M3S20 M3S19 M3S18 M3S17 M3S16 R/W 1 1 1 1 1 1 1 1 MSAR3 Memory start address register 3 014FH Set start address A23 to A16

(6) MMU Symbol Name Address 7 6 5 4 3 2 1 0 L0E L0EA22 L0EA21 L0EA20 R/W R/W 0 0 0 0 LOCAL0 LOCAL0 register 01D0H Use BANK for LOCAL0 0: Not use 1: Use Setting BANK number for LOCAL0 L1E L1EA23 L1EA22 L1EA21 R/W R/W 0 0 0 0 LOCAL1 LOCAL1 register 01D1H Use BANK for LOCAL1 0: Not use 1: Use Setting BANK number for LOCAL1 L2E L2EA23 L2EA22 L2EA21 R/W R/W 0 0 0 0 LOCAL2 LOCAL2 register 01D2H Use BANK for LOCAL2 0: Disable 1: Enable Setting BANK number for LOCAL2 L3E L3EA26 L3EA25 L3EA24 L3EA23 L3EA22 R/W R/W 0 0 0 0 0 0 LOCAL3 LOCAL3 register 01D3H Use BANK for LOCAL3 0: Disable 1: Enable 00000 to 00011: CS2B 00100 to 00111: CS2C 01000 to 01011: CS2D 01100 to 01111: CS2E 10000 to 10011: CS2F 10100 to 10111: CS2G 11000 to 11111: Set prohibition

(7) Clock gear (1/2) Symbol Name Address 7 6 5 4 3 2 1 0 XEN XTEN WUEF R/W R/W 1 1 0 SYSCR0 System clock control register 0 10E0H High- frequency oscillator (fc) 0: Stop 1: Oscillation Low- frequency oscillator (fs) 0: Stop 1: Oscillation Warm-up timer 0: Write Don’t care 1: Write start timer 0: Read end warm up 1: Read do not end warm up SYSCK GEAR2 GEAR1 GEAR0 R / W 0 1 0 0 SYSCR1 System clock control register 1 10E1H S e l e c t system clock 0: fc 1: fs Select gear value of high frequency (fc) 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) − WUPTM1 WUPTM0 HALTM1 HALTM0 SELDRV DRVE R/W R/W 0 1 0 1 1 0 0 SYSCR2 System clock control register 2 10E2H Always write “0”. Warm-up timer 00: Reserved 01: 2 /inputted frequency 10: 2 /inputted frequency 11: 2 /inputted frequency HALT mode 00: Reserved 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode <DRVE> mode select 0: Stop 1: IDLE1 Pin state control in STOP/ IDLE1 mode 0: I/O off 1: Remains the state before halt

Clock gear (2/2) Symbol Name Address 7 6 5 4 3 2 1 0 PROTECT EXTIN DRVOSCH DRVOSCL R R/W 0 0 1 1 EMCCR0 EMC control register 0 10E3H Protect flag 0: OFF 1: ON 1: External clock fc oscillator driver ability 1: Normal 0: Weak fs oscillator driver ability 1: Normal 0: Weak EMCCR1 EMC control register 1 10E4H EMCCR2 EMC control register 2 10E5H Switching the protect ON/OFF by write to following 1st-Key, 2nd-Key 1st-Key: EMCCR1 = 5AH, EMCCR2 = A5H in succession write 2nd-Key: EMCCR1 = A5H, EMCCR2 = 5AH in succession write

(8) LCD controller (1/6) Symbol Name Address 7 6 5 4 3 2 1 0 BAE AAE SCPW1 SCPW0 TA3LCDCK BULK RAMTYPE MODE R/W 0 0 1 0 0 0 0 0 LCDMODE LCD mode register 0200H Used by B area 0: Disable 1: Enable Used by A area 0: Disable 1: Enable SCP width 00: BaseSCP 01: 2 clocks 10: 4 clocks 11: 8 clocks Select low frequency 0: fs (32 kHz) 1: TA3OUT Byte- number/ common 0: 512 bytes 1: 1024 bytes Display RAM selection 0: SRAM 1: SDRAM Mode selection 0: RAM 1: SR FMN7 FMN6 FMN5 FMN4 FMN3 FMN2 FMN1 FMN0 R/W 0 0 0 0 0 0 0 0 LCDDVM Divide FRM register 0201H Setting DVM bit7 to 0 COM3 COM2 COM1 COM0 SEG3 SEG2 SEG1 SEG0 R/W 0 0 0 0 0 0 0 0 LCDSIZE LCD size register 0202H Setting the LCD common number for SR mode 000: 128 0101: 400 0001: 160 0110: 480 0010: 200 0011: 240 0100: 320 Others: Reserved Setting the LCD segment number for SR mode 0000: 128 0101: 480 0001: 160 0110: 560 0010: 240 0111: 640 0011: 320 0100: 400 Others: Reserved LCDON ALL0 FRMON − FP9 MMULCD FP8 START R/W 0 0 0 0 0 0 0 0 LCDCTL LCD control register 0203H DOFF port 0: OFF 1: ON LD bus output control 0: OFF (= Normal) 1: ON (= ALL 0) Divided FR mode 0: Disable 1: Enable Always write “0”. Setting bit 9 for fFP [9:0] Type selection of LCD driver with built-in RAM 0: Sequential access 1:Random access Setting bit 8 for fFP [9:0] Start control in SR mode 0: Stop 1: Start FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0 R/W 0 0 0 0 0 0 0 0 LCDFFP LCD frequency register 0204H fFP set value bit7 to 0 G R A Y 1 G R A Y 0 R / W 0 0 LCDGL LCD gray level register 0205H 00: Monochrome 01: 4 levels 10: 8 levels 11: 16 levels

LCD controller (2/6) Symbol Name Address 7 6 5 4 3 2 1 0 CDE CCS CBE1 CBE0 R/W R/W 0 0 0 0 LCDCM LCD cursor mode register 0206H Cursor 0: OFF 1: ON Cursor color 0: White 1: Black Cursor blink interval 00: Don’t blink 01: 2 Hz 10: 1 Hz 11: 0.5 Hz CW4 CW3 CW2 CW1 CW0 R / W 0 0 0 0 0 LCDCW LCD cursor width register 0207H Cursor width (X size) 00000: 1 dot (Min) 11111: 32 dots (Max) CH4 CH3 CH2 CH1 CH0 R / W 0 0 0 0 0 LCDCH LCD cursor height register 0208H Cursor height (Y size) 00000: 1 dot (Min) 11111: 32 dots (Max) APB3 APB2 APB1 APB0 R / W 0 0 0 0 LCDCP LCD cursor APB register 0209H Setting bit3 to 0 for cursor absolute position CAP7 CAP6 CAP5 CAP4 CAP3 CAP2 CAP1 CAP0 R/W 0 0 0 0 0 0 0 0 LCDCPL LCD cursor AP register low 020AH Setting bit7 to 0 for cursor absolute position CAP15 CAP14 CAP13 CAP12 CAP11 CAP10 CAP9 CAP8 R/W 0 0 0 0 0 0 0 0 LCDCPM LCD cursor AP register medium 020BH Setting bit15 to 8 for cursor absolute position CAP23 CAP22 CAP21 CAP20 CAP19 CAP18 CAP17 CAP16 R/W 0 1 0 0 0 0 0 0 LCDCPH LCD cursor AP register high 020CH Setting bit23 to 16 for cursor absolute position

LCD controller (3/6) Symbol Name Address 7 6 5 4 3 2 1 0 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 R/W 0 0 0 0 0 0 0 0 LSARAM A area start address register medium 0210H Setting start address A15 to A8 for the source data memory in A area SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 R/W 0 1 0 0 0 0 0 0 LSARAH A area start address register high 0211H Setting start address A23 to A16 for the source data memory in A area EA15 EA14 EA13 EA12 EA11 EA10 EA9 EA8 R/W 0 0 0 0 0 0 0 0 LEARAM A area end address register medium 0212H Setting end address A15 to A8 for the source data memory in A area EA23 EA22 EA21 EA20 EA19 EA18 EA17 EA16 R/W 0 1 0 0 0 0 0 0 LEARAH A area end address register high 0213H Setting end address A23 to A16 for the source data memory in A area SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 R/W 0 0 0 0 0 0 0 0 LSARBM B area start address register medium 0214H Setting start address A15 to A8 for the source data memory in B area SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 R/W 0 1 0 0 0 0 0 0 LSARBH B area start address register high 0215H Setting start address A23 to A16 for the source data memory in B area EA15 EA14 EA13 EA12 EA11 EA10 EA9 EA8 R/W 0 0 0 0 0 0 0 0 LEARBM B area end address register medium 0216H Setting end address A15 to A8 for the source data memory in B area EA23 EA22 EA21 EA20 EA19 EA18 EA17 EA16 R/W 0 1 0 0 0 0 0 0 LEARBH B area end address register high 0217H Setting end address A23 to A16 for the source data memory in B area SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W 0 0 0 0 0 0 0 0 LSARCL C area start address register low 0218H Setting start address A7 to A0 for the source data memory in C area SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 R/W 0 0 0 0 0 0 0 0 LSARCM C area start address register medium 0219H Setting start address A15 to A8 for the source data memory in C area SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 R/W 0 1 0 0 0 0 0 0 LSARCH C area start address register high 021AH Setting start address A23 to A16 for the source data memory in C area

LCD controller (4/6) Symbol Name Address 7 6 5 4 3 2 1 0 R/W 0 0 0 0 0 0 0 0 LG0L LCD gray level data setting register low 0220H R/W 0 0 0 0 0 0 0 0 LG0H LCD gray level data setting register high 0221H R/W 0 0 0 0 0 0 0 0 LG1L LCD gray level data setting register low 0222H R/W 1 0 0 0 0 0 0 0 LG1H LCD gray level data setting register high 0223H R/W 1 0 0 0 0 0 0 0 LG2L LCD gray level data setting register low 0224H R/W 1 0 0 0 0 0 0 0 LG2H LCD gray level data setting register high 0225H R/W 1 0 0 0 0 0 0 0 LG3L LCD gray level data setting register low 0226H R/W 1 0 0 0 1 0 0 0 LG3H LCD gray level data setting register high 0227H R/W 1 0 0 0 1 0 0 0 LG4L LCD gray level data setting register low 0228H R/W 1 0 0 0 1 0 0 0 LG4H LCD gray level data setting register high 0229H R/W 1 0 0 0 1 0 1 0 LG5L LCD gray level data setting register low 022AH R/W 1 0 0 0 1 0 0 0 LG5H LCD gray level data setting register high 022BH R/W 1 0 0 0 1 0 1 0 LG6L LCD gray level data setting register low 022CH R/W 1 0 0 0 1 0 1 0 LG6H LCD gray level data setting register high 022DH

LCD controller (5/6) Symbol Name Address 7 6 5 4 3 2 1 0 R/W 1 0 1 0 1 0 1 0 LG7L LCD gray level data setting register low 022EH R/W 1 0 0 0 1 0 1 0 LG7H LCD gray level data setting register high 022FH R/W 1 0 1 0 1 0 1 0 LG8L LCD gray level data setting register low 0230H R/W 1 0 1 0 1 0 1 0 LG8H LCD gray level data setting register high 0231H R/W 0 1 0 1 0 1 0 1 LG9L LCD gray level data setting register low 0232H R/W 1 1 0 1 0 1 0 1 LG9H LCD gray level data setting register high 0233H R/W 1 1 0 1 0 1 0 1 LGAL LCD gray level data setting register low 0234H R/W 1 1 0 1 0 1 0 1 LGAH LCD gray level data setting register high 0235H R/W 1 1 0 1 0 1 0 1 LGBL LCD gray level data setting register low 0236H R/W 1 1 0 1 1 1 0 1 LGBH LCD gray level data setting register high 0237H R/W 1 1 0 1 1 1 0 1 LGCL LCD gray level data setting register low 0238H R/W 1 1 0 1 1 1 0 1 LGCH LCD gray level data setting register high 0239H R/W 1 1 0 1 1 1 0 1 LGDL LCD gray level data setting register low 023AH R/W 1 1 1 1 1 1 0 1 LGDH LCD gray level data setting register high 023BH

LCD controller (6/6) Symbol Name Address 7 6 5 4 3 2 1 0 R/W 1 1 0 1 1 1 0 1 LGEL LCD gray level data setting register low 023CH R/W 1 1 0 1 1 1 0 1 LGEH LCD gray level data setting register high 023DH R/W 1 1 1 1 1 1 1 1 LGFL LCD gray level data setting register low 023EH R/W 1 1 1 1 1 1 1 1 LGFH LCD gray level data setting register high 023FH

(9) SDRAM controller Symbol Name Address 7 6 5 4 3 2 1 0 SDINI SDBUS1 SDBU0 SMUXW1 SMUXW0 SMAC R/W R/W R/W 0 0 0 0 0 0 SDACR SDRAM address control 0250H Auto initialize 0: Disable 1: Enable Selecting structure of data bus 00: 16 bits × 1 01: 16 bits × 2 10: 32 bits × 1 Selecting address multiplex type 00: Type A 01: Type B 10: Type C 11: Reserved SDRAM controller 0: Disable 1: Enable SFRC SRS2 SRS1 SRS0 SASFRC SRC R/W R/W 0 0 0 0 0 0 SDRCR SDRAM refresh control 0251H Self refresh 0: Disable 1: Enable Refresh interval 000: 78 states 100: 195 states 001: 97 states 101: 210 states 010: 124 states 110: 249 states 011: 156 states 111: 312 states Auto/self refresh 0: Disable 1: Enable Interval refresh 0: Disable 1: Enable

(10) 8-bit timer Symbol Name Address 7 6 5 4 3 2 1 0 TA0RDE I2TA01 TA01PRUN TA1RUN TA0RUN R/W R/W 0 0 0 0 0 TMRA01 Prescaler Up counter (UC1) Up counter (UC0) TA01RUN TMRA01 RUN register 1100H Double buffer 0: Disable 1: Enable IDLE2 0: Stop 1: Operate 0: Stop and clear 1: Run (Count up) W TA0REG 8-bit timer register 0 1102H Prohibit RMW Undefined W TA1REG 8-bit timer register 1 1103H Prohibit RMW Undefined TA01M1 TA01M0 PWM01 PWM00 TA1CLK1 TA1CLK0 TA0CLK1 TA0CLK0 R/W 0 0 0 0 0 0 0 0 TA01MOD TMRA01 mode register 1104H Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode PWM cycle 00: Reserved 01: 2 10: 2 11: 2 Source clock for TMRA1 00: TA0TRG 01: φT1 10: φT16 11: φT256 Source clock for TMRA0 00: TA0IN pin 01: φT1 10: φT4 11: φT16 TA1FFC1 TA1FFC0 TA1FFIE TA1FFIS W R/W 1 1 0 0 TA1FFCR TMRA1 flip-flop control register 1105H Prohibit RMW 00: Invert TA1FF 01: Set TA1FF 10: Clear TA1FF 11: Don’t care TA1FF Control for inversion 0: Disable 1: Enable TA1FF Inversion select 0: TMRA0 1: TMRA1 TA2RDE I2TA23 TA23PRUN TA3RUN TA2RUN R/W R/W 0 0 0 0 0 TMRA23 Prescaler Up counter (UC3) Up counter (UC2) TA23RUN TMRA23 RUN register 1108H Double buffer 0: Disable 1: Enable IDLE2 0: Stop 1: Operate 0: Stop and clear 1: Run (Count up) W TA2REG 8-bit timer register 2 110AH Prohibit RMW Undefined W TA3REG 8-bit timer register 3 110BH Prohibit RMW Undefined TA23M1 TA23M0 PWM21 PWM20 TA3CLK1 TA3CLK0 TA2CLK1 TA2CLK0 R/W 0 0 0 0 0 0 0 0 TA23MOD TMRA23 mode register 110CH Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode PWM cycle 00: Reserved 01: 2 10: 2 11: 2 Source clock for TMRA1 00: TA2TRG 01: φT1 10: φT16 11: φT256 Source clock for TMRA2 00: Reserved 01: φT1 10: φT4 11: φT16 TA3FFC1 TA3FFC0 TA3FFIE TA3FFIS W R/W 1 1 0 0 TA3FFCR TMRA3 flip-flop control register 110DH Prohibit RMW 00: Invert TA3FF 01: Set TA3FF 10: Clear TA3FF 11: Don’t care TA3FF Control for inversion 0: Disable 1: Enable TA3FF Inversion select 0: TMRA2 1: TMRA3

(11) 16-bit timer Symbol Name Address 7 6 5 4 3 2 1 0 TB0RDE − I2TB0 TB0PRUN TB0RUN R/W R/W R/W 0 0 0 0 0 TMRB0 prescaler Up counter (UC10) TB0RUN TMRB0 RUN register 1180H Double buffer 0: Disable 1: Enable Always write “0”. IDLE2 0: Stop 1: Operate 0: Stop and clear 1: Run (Count up) − − TB0CP0I TB0CPM1 TB0CPM0 TB0CLE TB0CLK1 TB0CLK0 R/W W R/W 0 0 1 0 0 0 0 0 TB0MOD TMRB0 mode register 1182H Prohibit RMW Always write “0”. Execute software capture 0: Software capture 1: Undefined Capture timing 00: Disable 01: Reserved 10: Reserved 11: TA1OUT↑ TA1OUT↓ Control up counter 0: Disable clearing 1: Enable clearing TMRB0 source clock 00: Reserved 01: φT1 10: φT4 11: φT16 − − TB0C1T1 TB0C0T1 TB0E1T1 TB0E0T1 TB0FF0C1 TB0FF0C0 W R/W W * 1 1 0 0 0 0 1 1 TB0FF0 inversion trigger 0: Disable trigger 1: Enable trigger TB0FFCR TMRB0 flip-flop control register 1183H Prohibit RMW Always write “11”. Invert when the UC10 value is loaded in to TB0CP1H/L. Invert when the UC10 value is loaded in to TB0CP0H/L. Invert when the UC10 value matches the value in TB0RG1H/L. Invert when the UC10 value matches the value in TB0RG0H/L. Control TB0FF0 00: Invert 01: Set 10: Clear 11: Don’t care * Always read as 11. W TB0RG0L 16-bit timer register 0 low 1188H Prohibit RMW Undefined W TB0RG0H 16-bit timer register 0 high 1189H Prohibit RMW Undefined W TB0RG1L 16-bit timer register 1 low 118AH Prohibit RMW Undefined W TB0RG1H 16-bit timer register 1 high 118BH Prohibit RMW Undefined R TB0CP0L Capture register 0 low 118CH Undefined R TB0CP0H Capture register 0 high 118DH Undefined R TB0CP1L Capture register 1 low 118EH Undefined R TB0CP1H Capture register 1 high 118FH Undefined

(12) UART/serial channel (1/3) Symbol Name Address 7 6 5 4 3 2 1 0 RB7 TB7 RB6 TB6 RB5 TB5 RB4 TB4 RB3 TB3 RB2 TB2 RB1 TB1 RB0 TB0 R (Receiving)/W (Transmission) SC0BUF Serial channel 0 buffer register 1200H Prohibit RMW Undefined RB8 EVEN PE OERR PERR FERR SCLKS IOC R R/W R (Clear to 0 after reading) R/W Undefined 0 0 0 0 0 0 0 1: Error SC0CR Serial channel 0 control register 1201H Receive data bit8 Parity 0: Odd 1: Even Parity 0: Disable 1: Enable Overrun Parity Framing 0: SCLK0↑ 1: SCLK0↓ 0: Baud rate generator 1: SCLK0 pin input TB8 CTSE RXE WU SM1 SM0 SC1 SC0 R/W 0 0 0 0 0 0 0 0 SC0MOD0 Serial channel 0 mode 0 register 1202H Trans- mission data bit8 0: CTS disable 1: CTS enable 0: Receive disable 1: Receive enable Wakeup 0: Disable 1: Enable 00: I/O interface mode 01: 7-bit UART mode 10: 8-bit UART mode 11: 9-bit UART mode 00: TA0TRG 01: Baud rate generator 10: Internal clock fIO 11: External clock (SCLK0 input) − BR0ADDE BR0CK1 BR0CK0 BR0S3 BR0S2 BR0S1 BR0S0 R/W 0 0 0 0 0 0 0 0 BR0CR Serial channel 0 baud rate control register 1203H Always write “0”. (16 − K)/16 divided 0: Disable 1: Enable 00: φT0 01: φT2 10: φT8 11: φT32 Divided frequency setting BR0K3 BR0K2 BR0K1 BR0K0 R / W 0 0 0 0 BR0ADD Serial channel 0 K setting register 1204H Sets frequency divisor “K” (divided by N + (16 − K)/16). I2S0 FDPX0 R/W R/W 0 0 SC0MOD1 Serial channel 0 mode 1 register 1205H IDLE2 0: Stop 1: Operate Duplex 1: Full duplex 0: Half duplex PLSEL RXSEL TXEN RXEN SIRWD3 SIRWD2 SIRWD1 SIRWD0 R/W 0 0 0 0 0 0 0 0 SIRCR IrDA control register 1207H Select transmit pulse width 0: 3/16 1: 1/16 Receive data 0: “H” pulse 1: “L” pulse Transmit 0: Disable 1: Enable Receive 0: Disable 1: Enable Select receive pulse width Set effective pulse width for equal or more than 2x × (Value + 1) + 100ns Can be set: 1 to 14 Can not be set: 0 and 15

UART/serial channel (2/3) Symbol Name Address 7 6 5 4 3 2 1 0 RB7 TB7 RB6 TB6 RB5 TB5 RB4 TB4 RB3 TB3 RB2 TB2 RB1 TB1 RB0 TB0 R (Receiving)/W (Transmission) SC1BUF Serial channel 1 buffer register 1208H Prohibit RMW Undefined RB8 EVEN PE OERR PERR FERR SCLKS IOC R R/W R (Clear to 0 after reading) R/W Undefined 0 0 0 0 0 0 0 1: Error SC1CR Serial channel 1 control register 1209H Receive data bit8 Parity 0: Odd 1: Even Parity 0: Disable 1: Enable Overrun Parity Framing 0: SCLK1↑ 1: SCLK1↓ 0: Baud rate generator 1: SCLK1 pin input TB8 CTSE RXE WU SM1 SM0 SC1 SC0 R/W 0 0 0 0 0 0 0 0 SC1MOD0 Serial channel 1 mode 0 register 120AH Trans- mission data bit8 0: CTS disable 1: CTS enable 0: Receive disable 1: Receive enable Wakeup 0: Disable 1: Enable 00: I/O interface mode 01: 7-bit UART mode 10: 8-bit UART mode 11: 9-bit UART mode 00: TA0TRG 01: Baud rate generator 10: Internal clock f IO 11: External clock (SCLK1 input) − BR1ADDE BR1CK1 BR1CK0 BR1S3 BR1S2 BR1S1 BR1S0 R/W 0 0 0 0 0 0 0 0 BR1CR Serial channel 1 baud rate control register 120BH Always write “0”. (16 − K)/16 divided 0: Disable 1: Enable 00: φT0 01: φT2 10: φT8 11: φT32 Divided frequency setting BR1K3 BR1K2 BR1K1 BR1K0 R / W 0 0 0 0 BR1ADD Serial channel 1 K setting register 120CH Sets frequency divisor “K” (divided by N + (16 − K)/16) I2S1 FDPX1 R / W 0 0 SC1MOD1 Serial channel 1 mode 1 register 120DH IDLE2 0: Stop 1: Operate Duplex 1: Full duplex 0: Half duplex

UART/serial channel (3/3) Symbol Name Address 7 6 5 4 3 2 1 0 RB7 TB7 RB6 TB6 RB5 TB5 RB4 TB4 RB3 TB3 RB2 TB2 RB1 TB1 RB0 TB0 R (Receiving)/W (Transmission) SC2BUF Serial channel 2 buffer register 1210H Prohibit RMW Undefined RB8 EVEN PE OERR PERR FERR − − R R/W R (Clear to 0 after reading) R/W Undefined 0 0 0 0 0 0 0 1:Error SC2CR Serial channel 2 control register 1211H Receive data bit8 Parity 0: Odd 1: Even Parity 0: Disable 1: Enable Overrun Parity Framing Always write “0”. Always write “0”. TB8 − RXE WU SM1 SM0 SC1 SC0 R/W 0 0 0 0 0 0 0 0 SC2MOD0 Serial channel 2 mode 0 register 1212H Trans- mission data bit8 Always write “0”. 0: Receive disable 1: Receive enable Wakeup 0: Disable 1: Enable 00: I/O interface mode 01: 7-bit UART mode 10: 8-bit UART mode 11: 9-bit UART mode 00: TA0REG 01: Baud rate generator 10: Internal clock f IO 11: Reserved − BR2ADDE BR2CK1 BR2CK0 BR2S3 BR2S2 BR2S1 BR2S0 R/W 0 0 0 0 0 0 0 0 BR2CR Serial channel 2 baud rate control register 1213H Always write “0”. (16 − K)/16 divided 0: Disable 1: Enable 00: φT0 01: φT2 10: φT8 11: φT32 Divided frequency setting BR2K3 BR2K2 BR2K1 BR2K0 R / W 0 0 0 0 BR2ADD Serial channel 2 K setting register 1214H Sets frequency divisor “K” (divided by N + (16 − K)/16) I2S2 FDPX2 R / W 0 0 SC2MOD1 Serial channel 2 mode 1 register 1215H IDLE2 0: Stop 1: Operate Duplex 1: Full duplex 0: Half duplex

(13) I2C bus/serial channel (1/2) Symbol Name Address 7 6 5 4 3 2 1 0 BC2 BC1 BC0 ACK SCK2 SCK1 SCK0/ SWRMON W R/W W R/W 0 0 0 0 0 0 0/1 I C mode 1240H (Prohibit RMW) Number of transfer bits 000: 8 001: 1 010: 2 011: 3 100: 4 101: 5 110: 6 111: 7 Acknow -ledge mode 0: Disable 1: Enable Setting of the divide value “n” 000: 5 001: 6 010: 7 011: 8 100: 9 101: 10 110: 11 111: Reserved SIOS SIOINH SIOM1 SIOM0 SCK2 SCK1 SCK0 W W 0 0 0 0 0 0 0 SBI0CR1 SBI0 control register 1 SIO mode 1240H (Prohibit RMW) Transfer 0: Stop 1: Start Transfer 0: Continue 1: Abort Transfer mode 00: 8 bits transmit 10: 8 bits transmit/receive 11: 8 bits receive Setting of the divide value “n” 000: 4 001: 5 010: 6 011: 7 100: 8 101: 9 110: 10 111: External clock SCK0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R (Receiving)/W (Transmission) SBI0DBR SBI0 buffer register 1241H (Prohibit RMW) Undefined SA6 SA5 SA4 SA3 SA2 SA1 SA0 ALS W 0 0 0 0 0 0 0 0 I2C0AR I CBUS0 Address register 1242H (Prohibit RMW) Setting slave address Address recognition 0: Enable 1: Disable MST TRX BB PIN SBIM1 SBIM0 SWRST1 SWRST0 W 0 0 0 1 0 0 0 0 I C mode 1243H (Prohibit RMW) 0: Slave 1: Master 0: Receive 1: Transmit Start/Stop condition generation 0: Stop 1: Start INTSBE0 interrupt 0: Request 1: Cancel Operation mode selection 00: Port mode 01: SIO mode 10: I C mode 11: Reserved Software reset generate write “10” and “01”, then an internal reset signal is generated. SBIM1 SBIM0 − − W 0 0 0 0 SBI0CR2 SBI0 control register 2 SIO mode 1243H (Prohibit RMW) Operation mode selection 00: Port mode 01: SIO mode 10: I C mode 11: Reserved Always write “0”. Always write “0”. MST TRX BB PIN AL AAS AD0 LRB R 0 0 0 1 0 0 0 0 I C mode 1243H (Prohibit RMW) 0: Slave 1: Master 0: Receive 1: Transmit Bus status monitor 0: Free 1: Busy INTSBE0 interrupt 0: Request 1: Cancel Arbitration lost detection 1: Detect Slave address match detection monitor 1: Detect General call detection 1: Detect Last receive bit monitor 0: 0 1: 1 SIOF SEF R 0 0 SBI0SR SBI0 status register SIO mode 1243H (Prohibit RMW) T r a n s f e r status 0: Stopped 1: In progress Shift status 0: Stopped 1: In progress

I 2C bus/serial channel (2/2) Symbol Name Address 7 6 5 4 3 2 1 0 − I2SBI0 W R/W 0 0 I C mode 1244H (Prohibit RMW) Always write “0”. IDLE2 0: Stop 1: Operate − − W R/W 0 0 SBI0BR0 SBI0 baud rate register 0 SBI mode 1244H (Prohibit RMW) Always write “0”. Always write “0”. P4EN − W 0 0 SBI0BR1 SBI0 baud rate register 1 1245H (Prohibit RMW) Clock control 0: Stop 1: Operate Always write “0”.

(14) AD converter Symbol Name Address 7 6 5 4 3 2 1 0 EOCF ADBF − − ITM0 REPET SCAN ADS R R/W 0 0 0 0 0 0 0 0 ADMOD0 AD mode control register 0 12B8H AD conversion end flag 1: End AD conversion busy flag 1: Busy Always write “0”. Always write “0”. 0: Every 1 time 1: Every 4 times Repeat mode 0: Single mode 1: Repeat mode Scan mode 0: Fixed channel mode 1: Channel scan mode AD conversion start 1: Start Always read as “0” VREFON I2AD − − − ADCH2 ADCH1 ADCH0 R/W 0 0 0 0 0 0 0 0 ADMOD1 AD mode control register 1 12B9H Ladder resistance 0: OFF 1: ON IDLE2 0: Stop 1: Operate Always write “0”. Always write “0”. Always write “0”. Input channel 000: AN0 AN0 001: AN1 AN0 → AN1 010: AN2 AN0 → AN1 → AN2 011: AN3 AN0 → AN1 → AN2 → AN3 100: AN4 AN0 → AN1 → AN2 → AN3 → AN4 A D T R G R / W ADMOD2 AD mode control register 1 12BAH A D external trigger start control 0: Disable 1: Enable ADR01 ADR00 ADR0RF R R ADREG0L AD result register 0 low 12A0H Undefined 0 ADR09 ADR08 ADR07 ADR06 ADR05 ADR04 ADR03 ADR02 R ADREG0H AD result register 0 high 12A1H Undefined ADR11 ADR10 ADR1RF R R ADREG1L AD result register 1 low 12A2H Undefined 0 ADR19 ADR18 ADR17 ADR16 ADR15 ADR14 ADR13 ADR12 R ADREG1H AD result register 1 high 12A3H Undefined ADR21 ADR20 ADR2RF R R ADREG2L AD result register 2 low 12A4H Undefined 0 ADR29 ADR28 ADR27 ADR26 ADR25 ADR24 ADR23 ADR22 R ADREG2H AD result register 2 high 12A5H Undefined ADR31 ADR30 ADR3RF R R ADREG3L AD result register 3 low 12A6H Undefined 0 ADR39 ADR38 ADR37 ADR36 ADR35 ADR34 ADR33 ADR32 R ADREG3H AD result register 3 high 12A7H Undefined ADR21 ADR20 ADR4RF R R ADREG4L AD result register 4 low 12A8H Undefined 0 ADR29 ADR28 ADR27 ADR26 ADR25 ADR24 ADR23 ADR22 R ADREG4H AD result register 4 high 12A9H Undefined

(15) Watchdog timer Symbol Name Address 7 6 5 4 3 2 1 0 WDTE WDTP1 WDTP0 − I2WDT RESCR − R/W R/W 1 0 0 0 0 0 0 WDMOD WDT mode register 1300H WDT control 1: Enable WDT select detecting time 00: 2 /fIO 01: 2 /fIO 10: 2 /fIO 11: 2 /fIO Always write “0”. IDLE2 0: Stop 1: Operate 1: Internally connects WDT out to the reset pin Always write “0”. W WDCR WDT control register 1301H Prohibit RMW B1H: WDT disable code 4EH: WDT clear code

(16) RTC (Real time clock) Symbol Name Address 7 6 5 4 3 2 1 0 SE6 SE5 SE4 SE3 SE2 SE1 SE0 R/W Undefined SECR Second register 1320H “0” is read. 40 sec 20 sec 10 sec 8 sec 4 sec 2 sec 1 sec MI6 MI5 MI4 MI3 MI2 MI1 MI0 R/W Undefined MINR Minute register 1321H HO5 HO4 HO3 HO2 HO1 HO0 R/W Undefined HOURR Hour register 1322H “0” is read. 20 hour (PM/AM) 10 hour 8 hour 4 hour 2 hour 1 hour WE2 WE1 WE0 R / W Undefined DAYR Day register 1323H “0” is read. W2 W1 W0 DA5 DA4 DA3 DA2 DA1 DA0 R/W Undefined DATER Date register 1324H “0” is read. 20 day 10 day 8 day 4 day 2 day 1 day MO4 MO3 MO2 MO1 MO0 R / W 1325H Undefined PAGE 0 “0” is read. 10 month 8 month 4 month 2 month 1 month MONTHR Month register PAGE 1 “0” is read. 0: Indicator for 12 hours 1: Indicator for 24 hours YE7 YE6 YE5 YE4 YE3 YE2 YE1 YE0 R/W 1326H Undefined PAGE 0 80 year 40 year 20 year 10 year 8 year 4 year 2 year 1 year YEARR Year register PAGE 1 “0” is read. Leap year setting 00: Leap year 01: One year after 10: Tow year after 11: Three year after INTENA ADJUST ENATMR ENAALM PAGE R/W W R/W R/W

0 Undefined UndefinedPAGER Page

0:disable 1:enable “0” is read. 0:Don’t care 1:Adjust Clock 0:disable 1:enable Alarm 0:disable 1:enable “0” is read. PAGE setting DIS1HZ DIS16HZ RSTTMR RSTALM RE3 RE2 RE1 RE0 W Undefined RESTR Reset register 1328H Prohibit RMW 1 Hz 0:disable 1:enable 16 Hz 0:disable 1:enable 1: Reset clock 1: Reset alarm Always write “0”.

(17) Melody/alarm generator Symbol Name Address 7 6 5 4 3 2 1 0 AL8 AL7 AL6 AL5 AL4 AL3 AL2 AL1 R/W 0 0 0 0 0 0 0 0 ALM Alarm- pattern register 1330H Alarm pattern set FC1 FC0 ALMINV − − − − MELALM R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 MELALMC Melody/ Alarm control register 1331H Free-run counter control 00: Hold 01: Restart 10: Clear 11: Clear & start Alarm frequency invert 1: Invert Always write “0”. Output frequency 0: Alarm 1: Melody ML7 ML6 ML5 ML4 ML3 ML2 ML1 ML0 R/W 0 0 0 0 0 0 0 0 MELFL Melody frequency L-register 1332H Melody frequency set (Low 8 bits ) MELON ML11 ML10 ML9 ML8 R/W R/W 0 0 0 0 0 MELFH Melody frequency H-register 1333H Melody counter control 0: Stop & clear 1: Start Melody frequency set (Upper 4 bits) − IALM4E IALM3E IALM2E IALM1E IALM0E R/W R/W 0 0 0 0 0 0 ALMINT Alarm interrupt enable register 1334H Always write “0”. INTALM4 to INTALM0 alarm interrupt enable

1. Port Section Equivalent Circuit Diagram ■ Reading the circuit diagram Basically, the gate symbols written are the same as those used for the standard CMOS logic IC [74HCXX] series. The dedicated signal is described below. STOP: This signal becomes active “1” when the HALT mode setting register is set to the STOP mode and the CPU executes the HALT instruction. When the drive enable bit <DRVE> is set to “1”, however, STOP remains at “0”. The input protection resistance ranges from several tens of ohms to several hundreds of ohms. ■ D0 to D7, P1 (D8 to D15), P2 (D 16 to D23), P3 (D24 to D31), P4 (A0 to A7), P5 (A8 to A15), P6 (A16 to A23), P76 and PL0 to PL7 ■ P90, P96, PC0, PC1, PC3, PC5, PC6, PF1, PF2, PF4, PF5 VCC Output data Output enable STOP Input data I/O Input enable P-ch N-ch VCC Output data Output enable STOP Input data I/O Input enable P-ch N-ch

■ P70 to P75, P80 to P87, P J0 to PJ7, PK0 to PK4 and PK6 ■ PA ■ P91 (SO/SDA), P92 (SI/SCL), P93 and P94 ■ P95 (TXD2), PF0, PF3 VCC Output data Open-drain output enable STOP Input data I/O Input enable P-ch N-ch Input data Input VCC VCC Output data Open-drain output enable STOP Input data I/O Input enable P-ch N-ch VCC Output P-ch N-ch Output data STOP

■ PG (AN0 to AN4) ■ RESET ■ X1 and X2 ■ XT1 and XT2 RESET Input VCC WDTOUT Reset enable Schmitt 100 kΩ (Typ.) Analog input channel select Analog input Input data Input Input enable P-ch N-ch Clock High-frequency oscillation enable N-ch P-ch Oscillator Clock Low-frequency oscillation enable XT2 N-ch XT1 P-ch Oscillator

■ VREFH and VREFL ■ SDCLK ■ BE ■ AM0 to AM1 VREF ON VREFH P-ch VREFL String resistance Output CLKOUT1 VCC Internal reset Output enable P-ch N-ch P-ch VCC BE Input Input data Input

1. Points to Note and Restrictions

7.1 Notation

(1) The notation for built-in/I/O registers is as follows register symbol <Bit symbol> Example: TA01RUN<TA0RUN> denotes bit TA0RUN of register TA01RUN. (2) Read-modify-write instructions (RMW) An instruction in which the CPU reads data from memory and writes the data to the same memory location in one instruction. Example 1: SET 3, (TA01RUN ); Set bit3 of TA01RUN. Example 2: INC 1, (100H); Increment the data at 100H.

• Examples of read-modify-write instructions on the TLCS-900 Exchange instruction EX (mem), R Arithmetic operations ADD (mem), R/# ADC (mem), R/# SUB (mem), R/# SBC (mem), R/# INC #3, (mem) DEC #3, (mem) Logic operations AND (mem), R/# OR (mem), R/# XOR (mem), R/# Bit manipulation operations STCF #3/A, (mem) RES #3, (mem) SET #3, (mem) CHG #3, (mem) TSET #3, (mem) Rotate and shift operations RLC (mem) RRC (mem) RL (mem) RR (mem) SLA (mem) SRA (mem) SLL (mem) SRL (mem) RLD (mem) RRD (mem) (3) fc, fs, f FPH, fSYS and one state The clock frequency input on ins X1 and 2 is called fOSCH. The clock selected by DFMCR0<ACT1:0> is called fc. The clock selected by SYSCR1<SYSCK> is called fFPH. The clock frequency give by fFPH divided by 2 is called fSYS. One cycle of fSYS is referred to as one state.

7.2 Points to Note

(1) AM0 and AM1 pins This pin is connected to the VCC or the VSS pin. Do not alter the level when the pin is active. (2) EMU0 and EMU1 Open pins. (3) Reserved address areas The TMP92C820 does not have any reserved areas. (4) Warm-up counter The warm-up counter operates when STOP mode is released, even if the system is using an external oscillator. As a result a time equivalent to the warm-up time elapses between input of the release request and output of the system clock. (5) Programmable pull-up resistance The programmable pull-up resistor can be turned ON/OFF by a program when the ports are set for use as input ports. When the ports are set for use as output ports, they cannot be turned ON/OFF by a program. The data registers (e.g., P5) are used to turn the pull-up/pull-down resistors ON/OFF. Consequently read-modify-write instructions are prohibited. (6) Watchdog timer The watchdog timer starts operation immediately after a reset is released. When the watchdog timer is not to be used, disable it. (7) AD converter The string resistor between the VREFH and VREFL pins can be cut by a program so as to reduce power consumption. When STOP mode is used, disable the resistor using the program before the HALT instruction is executed. (8) CPU (Micro DMA) Only the “LDC cr, r” and “LDC r, cr” instructions can be used to access the control registers in the CPU. (e.g., The transfer source address register (DMASn).) (9) Undefined SFR The value of an undefined bit in an SFR is undefined when read. (10) POP SR instruction Please execute the POP SR instruction during DI condition. (11) Releasing the HALT mode by requesting an interruption Usually, interrupts can release all halts status. However, the interrupts = (INT0 to INT3, INTKEY, INTRTC and INTALM0 to INTALM4) which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of f FPH) with IDLE1 or STOP mode (IDLE2 is not applicable). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, release halt status can be released without difficulty. The priority of this interrupt is compared with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt.

1. Package Dimensions P-LQFP144-1616-0.40C Unit: mm Note: Palladium plating