TMP90C041 TOSHIBA | Alldatasheet
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Technical content
- Pin Assignment and Functions The assignment of input/output pins, their names and functions are described below.
2.1 Pin Assignment
Figure 2.1 (1) shows pin assignment of the TMP90C041N. Figure 2.1-(1). Pin Assignment (Shrink Dual Inline Package)
Figure 2.1 (2) shows pin assignment of the TMP90C041F. Figure 2.1 (2). Pin Assignment (Flat Package)
2.2 Pin Names and Functions
The names of input/output pins and their functions are summa- rized in Table 2.2. Table 2.2 Pin Names and Functions (1/2) Pin Name No. of pins I/O 3 states Function D0 ~ D7 8 3 states Data bus: Also functions as 8-bit bidirectional data bus for external memory A0 ~ A7 8 Output Address bus: The lower 8 bits address bus for external memory A8 ~ A15 8 Output Address bus: The upper 8 bits address bus for external memory P30 /RxD 1 Input Port 30: 1-bit input port Receiver Serial Data P31 /RxD 1 Input Port 31: 1-bit input port Receiver Serial Data P32 /TxD /RTS /SCLK
1 Output
Port 32: 1-bit input port Transmitter Serial Data Request to send Serial Data Serial clock output P33 /TxD 1 Output Port 33: 1-bit output port Transmitter Serial Data P34 /CTS
1 Input
Port 34: 1-bit input port Clear to send Serial Data RD 1 Output Read: Generates strobe signal for reading external memory WR 1 Output Write: Generates strobe signal for writing into external memory P37 /WAIT 1 Input Port 37: 1-bit input port Wait: Input pin for connecting slow speed memory or peripheral LSI
Table 2.2 Pin Names and Functions (2/2) Pin Name No. of Pins I/O 3 states Function P40 ~ P43 /A16 ~ A19 4 Output Port 4: 4-bit output port that allows selection of Port/Address Bus on bit basis Address bus: Also functions as address bus for external memory (4 bits of bank address) P50 ~ P55 /AN0 ~ AN5 6 Input Port 5: 6-bit input port Analog input: 6 analog input to A/D converter VREF 1 – Input of reference voltage to A/D converter AGND 1 – Ground pin for A/D converter P60 ~ P63 /M00 ~ M03 /TO1 I/O Port 6: 4-bit I/O port that allows I/O selection on bit basis Output Stepping motor control port 0 Output T imer output 1: Output of Timer 0 or 1 P70 ~ P73 /M10 ~ M13 /TO3 I/O Port 7: 4-bit I/O port that allows I/O selection on bit basis Output Stepping motor control port 1 Output T imer output 3: Output of Timer 2 or 3 P80 /INTO 1 Input Port 80: 1-bit input port Interrupt request pin 0: Interrupt request pin (Level/rising edge is programmable) P81 /INT1 /TI4 Port 81: 1-bit input port Interrupt request pin 1: Interrupt request pin (Rising/falling edge is programmable) Timer input 4: Counter/capture trigger signal for Timer 4 P82 /INT2 /TI5 Port 82: 1-bit input port Interrupt request pin 2: rising edge interrupt request pin Timer input 5: capture trigger signal for Timer 4 P83 /TO3/T04 1 Output Port 83: 1-bit output port Timer output 3/4: Output of Timer 2, 3 or 4 NMI Non-maskable interrupt request pin: Falling edge interrupt request pin CLK 1 Output Clock output: Generates clock pulse at 1/4 frequency of clock oscillation. It is Pulled up internally during resetting. EA 1 Input External access: Connects with GND pin in the TMP90C041 with no internal ROM. RESET 1 Input Reset: Initializes the TMP90C041. (Built-in pull-up resistor) X1/X2 2 Input/ Output Pin for quartz crystal or ceramic resonator V CC 1 – Power supply (+5V) V SS (GND) 1 – Ground (0V)
- Operation The following explains the TMP90C041 functions and basic operations. The CPU functions and internal I/O functions of the TMP90C041 are the same as the TMP90C840A. Refer to the “TMP90C840A” section concerning functions which are not explained in the following.
3.1 CPU
The TMP90C041 has an internal high-performance 8-bit CPU. Refer to the book TLCS Series CPU Core Architecture concerning CPU operation.
3.2 Memory Map
The TMP90C041 supports a program memory of up to 64K bytes and a data memory of maximum 1M bytes. The program memory may be assigned to the address space from 00000H to 0FFFFH, while the data memory can be allocated to any address from 00000H to FFFFFH. (1) Internal I/O The TMP90C041 provides a 48-byte address space as an internal I/O area, whose addresses range from FFC0H to FFEFH. This I/O area can be accessed by the CPU using a short opcode in the “direct addressing mode”. Figure 3.1 is a memory map indicating the areas accessible by the CPU in the respective addressing mode.
Figure 3.2. Memory Map 4. Electrical Characteristics TMP90C041N/TMP90C041F Note: I DAR is guaranteed for a total of up to 8 optional ports.
4.1 Absolute Maximum Ratings
Symbol Parameter Rating Unit V CC Supply voltage -0.5 ~ + 7 V V IN Input voltage -0.5 ~ V CC + 0.5 V P D Power dissipation (Ta = 70 F 500 mW N 600 T SOLDER Soldering temperature (10s) 260 C T STG Storage temperature -65 ~ 150 C T OPR Operating temperature -20 ~ 70 C
4.2 DC Characteristics
TA = -20 ~ 70 C V CC = 5V 10% Typical Values are for TA = 25 C and V CC = 5V. Symbol Parameter Min Max Unit Test Conditions V IL Input Low Voltage (D0 ~ D7) -0.3 0.2V CC - 0.1 V – V IL1 P3, P5, P6, P7, P8 -0.3 0.3V CC V IL2 RESET, INT0, NMI -0.3 0.25V CC V IL4 X1 -0.3 0.2V CC V IH Input Low Voltage (D0 ~ D7) 0.2V CC + 1.1 V CC + 0.3 V – V IH1 P3, P5, P6, P7, P8 0.7V CC V CC + 0.3 V – V IH2 RESET, INT0, NMI 0.75V CC V CC + 0.3 V – V IH4 X1 0.8V CC V CC + 0.3 V – V OL Output Low Voltage – 0.45 V I OL = 1.6mA V OH V OH1 V OH2 Output High Voltage 2.4 0.75V CC 0.9V CC V V V I OH = -400 m A I OH = -100 m A I OH = -20 m A I DAR Darlington Drive Current (8 I/O pins) -1.0 -3.5 mA V EXT = 1.5V R EXT = 1.1k W I LI Input Leakage Current 0.02 (Typ) m A 0.0 Vin V CC I LO Output Leakage Current 0.05 (Typ) m A 0.2 Vin V CC - 0.2 I CC Operating Current (RUN) Idle 1 Idle 2 20 (Typ) 1.5 (Typ) 9 (Typ) mA mA mA tosc = 12.5MHz STOP (TA = -20 ~ 70 STOP (TA = 0 ~ 50 C) 0.2 (Typ) 50 m A m A 0.2 Vin V CC - 0.2 R RST RESET Pull Up Register 50 150 K W CIO Pin Capacitance – 10 pF testfreq = 1MHz V TH Schmitt width RESET, NMI, INT0 0.4 1.0 (Typ) V –
- AC output level High 2.2V/Low 0.8V
- AC input level High 2.4V/Low 0.45V (D0 – D7) High 0.8V CC /Low 0.2V CC (excluding D0 – D7)
4.3 AC Characteristics
TA = -20 ~ 70 C V CC = 5V 10% CL = 50pF Symbol Parameter Variable 10MHz Clock 12.5MHz Clock Unit Min Max Min Max Min Max t OSC OSC. Period = x 80 1000 100 - 80 – ns t CYC CLK Period 4x 4x 400 – 320 – ns t WL CLK Low width 2x - 40 – 160 – 120 – ns t WH CLK High width 2x - 40 – 160 – 120 – ns t AC Address Setup to RD, WR x - 45 – 55 – 35 – ns t RR RD Low width 2.5x - 40 – 210 – 160 – ns t CA Address Hold Time After RD, WR 0.5x - 30 – 20 – 10 – ns t AD Address to Valid Data In - 3.5x - 95 – 255 – 185 ns t RD RD to Valid Data In - 2.5x - 80 – 170 – 120 ns t HR Input Data Hold After RD 0 – 0–0– n s t WW WR Low width 2.5x - 40 – 210 – 160 – ns t DW Data Setup to WR 2x - 50 – 150 – 110 – ns t WD Data Hold After WR 30 90 30 90 30 90 ns t CWA RD, WR to Valid WAIT – 1.5x - 100 – 50 – 20 ns t AWA Address to Valid WAIT – 2.5x - 130 – 120 – 70 ns t WAS WAIT Setup to CLK 70 – 70 – 70 – ns t WAH WAIT Hold After CLK 0 – 0–0– n s t RV RD/WR Recovery Time 1.5x - 35 – 115 – 85 – ns t CPW CLK to Port Data Output – x + 200 – 300 – 280 ns t PRC Port Data Setup to CLK 200 – 200 – 200 – ns t CPR Port Data Hold After CLK 100 – 100 – 100 – ns t CHCL RD/WR Hold After CLK x-60 – 40 – 20 – ns t CLC RD/WR Setup to CLK 1.5x - 25 – 100 – 70 – ns t CLHA Address Hold After CLK 1.5x - 80 – 70 – 40 – ns t ACL Address Setup to CLK 2.5x - 80 – 170 – 120 – ns t CLD Data Setup to CLK x - 50 – 50 – 30 – ns
4.4 A/D Conversion Characteristics
TA = -20 ~ 70 C V CC = 5V 10% Symbol Parameter Min Typ Max Unit V REF Analog reference voltage V CC - 1.5 V CC VCC VAGND Analog reference voltage V SS VSS VSS VAIN Allowable analog input voltage V SS –V CC IREF Supply current for analog reference voltage – 0.5 1.0 mA Error Total error (TA = 25°C, VCC = VREF = 5.0V) – – 1.0 LSB Total error – – 2.5
4.5 Zero-Cross Characteristics
TA = -20 ~ 70°C VCC = 5V – 10% Symbol Parameter Condition Min Max Unit VZX Zero-cross detection input AC coupling C = 0.1 mF 1 1.8 VAC p - p AZX Zero-cross accuracy 50/60Hz sine wave – 135 mV FZX Zero-cross detection input frequency – 0.04 1 kHz
4.6 Serial Channel Timing-I/O Interface Mode
TA = –20 ~ 70°C VCC = 5V – 10% CL = 50pF Symbol Parameter Variable 10MHz Clock 12.5MHz Clock Unit Min Max Min Max Min Max tSCY Serial Port Clock Cycle Time 8x – 800 – 640 – ns tOSS Output Data Setup SCLK Rising Edge 6x - 150 – 450 – 330 – ns tOHS Output Data Hold After SCLK Rising Edge 2x - 120 – 80 – 40 – ns tHSR Input Data Hold After SCLK Rising Edge 0 – 0–0– n s tSRD SCLK Rising Edge to Input DATA Valid – 6x - 150 – 450 – 330 ns 4.7 16-bit Event Counter TA = –20 ~ 70°C VCC = 5V – 10% Symbol Parameter Variable 10MHz Clock 12.5MHz Clock Unit Min Max Min Max Min Max tVCK TI4 clock cycle 8x + 100 – 900 – 740 – ns tVCKL TI4 Low clock pulse width 4x + 40 – 440 – 360 – ns tVCKH TI4 High clock pulse width 4x + 40 – 440 – 360 – ns
(Reference) Definition of IDAR
4.9 I/O Interface Mode Timing Chart
4.8 Interrupt Operation
TA = -20 ~ 70°C VCC = 5V – 10% Symbol Parameter Variable 10MHz Clock 12.5MHz Clock Unit Min Max Min Max Min Max tINTAL NMI, INT0 Low level pulse width 4x – 400 – 320 – ns tINTAH NMI, INT0 High level pulse width 4x – 400 – 320 – ns tINTBL INT1, INT2 Low level pulse width 8x + 100 – 900 – 740 – ns tINTBH INT1, INT2 High level pulse width 8x + 100 – 900 – 740 – ns
4.10 Timing Chart
- Differences Between TMP90C841A and TMP90C041 Specifications of TMP90C841A and TMP90C041 are the same except below. TMP90C841A system, not using internal RAM and internal I/O functions as shown below, can be substituted by TMP90C041 system. To substitute the TMP90C841A system using the internal RAM by the TMP90C041 system, it is neces- sary to attach the external RAM to the address corresponded to the internal address. * Note: Connect EA pin with GND pin. Name TMP90C841A TMP90C041 RAM 256 bytes of internal RAM are provided. (0FEC0H ~ 0FFBFH) External memory area. A0 ~ A15 High-Impedance state during reset Driving state during reset. P0 (0FFC1H) P1 (0FFC1H) P2 (0FFC4H) Provided (same chip as TMP90C840A) R/W function is not provided. P01CR (0FFC2H) Provided EXT, P1C, P0C is not provided. P2CR (0FFC5H) Provided P2XC register is not provided