TMP86CH47AUG

TMP86CH47AUG TOSHIBA | Alldatasheet

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Technical content

8 Bit Microcontroller

The information contained herein is subject to change without notice. 021023 _ D TOSHIBA is continually working to improve the qual ity and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautio ns and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A The Toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These Toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ( “Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, tr ansportation instruments, traffic signal instruments, combustion control instruments, medical instrument s, all types of safety devices, etc. Unintended Usage of Toshiba products listed in this document shall be made at the customer's own risk. 021023_B The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohib ited under any applicable laws and regulations. 060106_Q The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSH IBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C The products described in this document may include products subject to the foreign exchange and foreign trade laws. 021023_F For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S © 2007 TOSHIBA CORPORATION All Rights Reserved

Revision History

2005/10/27 1 First Release 2005/10/28 2 Contents Revised 2005/12/15 3 内容改訂 2006/6/29 4 Periodical updating.No change in contents. 2006/7/27 5 Periodical updating.No change in contents. 2006/8/21 6 Contents Revised 2007/2/14 7 Contents Revised 2007/3/16 8 Contents Revised

i Table of Contents TMP86CH47AUG 2. Operational Description

2.2.2.1 Configuration of timing generator

2.2.2.2 Machine cycle

2.2.3.1 Single-clock mode

2.2.3.2 Dual-clock mode

2.2.3.3 STOP mode

2.2.4.1 STOP mode

2.2.4.2 IDLE1/2 mode and SLEEP1/2 mode

2.2.4.3 IDLE0 and SLEEP0 modes (IDLE0, SLEEP0)

2.2.4.4 SLOW mode

1. Interrupt Control Circuit

3.4.2.1 Using PUSH and POP instructions

3.4.2.2 Using data transfer instructions

1. Special Function Register (SFR) 5. I/O Ports 6. Time Base Timer (TBT) 7. Watchdog Timer (WDT) 8. 16-Bit TimerCounter 1 (TC1)

1. 8-Bit TimerCounter (TC3, TC4)

9.3.9.1 Low-Frequency Warm-up Counter Mode

(NORMAL1 → NORMAL2 → SLOW2 → SLOW1)

9.3.9.2 High-Frequency Warm-Up Counter Mode

(SLOW1 → SLOW2 → NORMAL2 → NORMAL1) 10. Synchronous Serial Interface (SIO)

10.3.1.1 Clock source

10.3.1.2 Shift edge

10.3.2.1 Transmit mode

10.3.2.2 Receive mode

10.3.2.3 Transmit/receive mode

10.3.3.1 Transmit mode

10.3.3.2 Receive mode

10.3.3.3 Transmit/receive mode

1. Asynchronous Serial interface (UART )

1. 10-bit AD Converter (ADC) 13. Key-on Wakeup (KWU) 14. Input/Output Circuitry 15. Electrical Characteristics 16. Package Dimensions This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/C (LSI).

CMOS 8-Bit Microcontroller

• The information contained herein is subject to change without notice. 021023_D
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent el ectrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, pleas e ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A
• The TOSHIBA products listed in this document are intended for usage in general electronics applic ations (computer, personal eq uip- ment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neithe r intended nor warranted for usage in equipment that requires extr aordinarily high quality and/or re liability or a malfunctionor failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instru- ments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B
• The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q
• The information contained herein is present ed only as a guide for the applications of our products. No responsibility is assum ed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by impli- cation or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C
• The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E
• For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S TMP86CH47AUG

1.1 Features

1. 8-bit single chip microcomputer TLCS-870/C series - Instruction execution time : 0.25 µs (at 16 MHz) 122 µs (at 32.768 kHz) - 132 types & 731 basic instructions 2. 18interrupt sources (External : 6 Internal : 12) 3. Input / Output ports (35 pins) Large current output: 19pins (Typ. 20mA), LED direct drive 4. Prescaler - Time base timer - Divider output function 5. Watchdog Timer 6. 16-bit timer counter: 1 ch - Timer, External trigger, Wi ndow, Pulse width measurement, Event counter, Programmable pulse generate (PPG) modes 7. 8-bit timer counter : 2 ch - Timer, Event counter, Programmable divider output (PDO), Pulse width modulation (PWM) output, Programmable pulse generation (PPG) modes 8. High-Speed SIO: 1ch Product No. ROM (MaskROM) RAM Package FLASH MCU Emulation Chip TMP86CH47AUG 16384 bytes 512 bytes LQFP44-P-1010-0.80B TMP86FH47AUG TMP86C947XB

1.1 Features TMP86CH47AUG

1. 8-bit UART : 1 ch 10. 10-bit successive approximation type AD converter - Analog input: 8 ch 11. Key-on wakeup : 4 ch 12. Clock operation Single clock mode Dual clock mode 13. Low power consumption operation STOP mode: Oscillation stops. (Battery/Capacitor back-up.) SLOW1 mode: Low power consumption operation usin g low-frequency clock.(High-frequency clock stop.) SLOW2 mode: Low power consumption operation usin g low-frequency clock.(High-frequency clock oscillate.) IDLE0 mode: CPU stops, and only the Time-Based-Tim er(TBT) on peripherals operate using high fre- quency clock. Release by falling edge of the source clock which is set by TBTCR<TBTCK>. IDLE1 mode: CPU stops and peripherals operate us ing high frequency clock. Release by interru- puts(CPU restarts). IDLE2 mode: CPU stops and peripherals operate using high and low frequency clock. Release by inter- ruputs. (CPU restarts). SLEEP0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using low fre- quency clock.Release by falling edge of the source clock which is set by TBTCR<TBTCK>. SLEEP1 mode: CPU stops, and peripherals operate using low frequency clock. Release by interru- put.(CPU restarts). SLEEP2 mode: CPU stops and peripherals operate using high and low frequency clock. Release by interruput. 14. Wide operation voltage: 4.5 V to 5.5 V at 16MHz /32.768 kHz 2.7 V to 5.5 V at 8 MHz /32.768 kHz 1.8 V to 5.5 V at 4.2MHz /32.768 kHz

1.2 Pin Assignment

P10 (TC3/PDO3/PWM3) P31 (AIN1) P32 (AIN2) P34 (AIN4/STOP2) P33 (AIN3) P37 (AIN7/STOP5) P36 (AIN6/STOP4) P35 (AIN5/STOP3) P30 (AIN0) P11 (INT1) P12 (INT2/TC1) VAREF AVDD AVSS P40 P42 P43 P44 P45 P46 P47 P41 VSS XOUT TEST VDD (XTIN) P21 (XTOUT) P22 RESET (INT5/STOP) P20 (INT0) P00 (PDO4/PWM4/PPG4/TC4) P01 XIN P02(RXD) P04(SO) P05(SI) P06(SCK) P17 P16 P15(INT3) P14(PPG) P13(DVO) P03(TXD) P07(INT4)

1.3 Block Diagram TMP86CH47AUG

1.3 Block Diagram

1.4 Pin Names and Functions

Table 1-1 Pin Names and Functions(1/2) Pin Name Pin Number Input/Output Functions P07 INT4 17 IO I PORT07 External interrupt 4 input P06 SCK 16 IO IO PORT06 Serial clock input/output P05 SI 15 IO I PORT05 Serial data input P04 SO 14 IO O PORT04 Serial data output P03 TXD 13 IO O PORT03 UART data output P02 RXD 12 IO I PORT02 UART data input P01 TC4 PDO4/PWM4/PPG4 IO I O PORT01 TC4 input PDO4/PWM4/PPG4 output P00 INT0 10 IO I PORT00 External interrupt 0 input P17 18 IO PORT17 P16 19 IO PORT16 P15 INT3 20 IO I PORT15 External interrupt 3 input P14 PPG 21 IO O PORT14 PPG output P13 DVO 22 IO O PORT13 Divider Output P12 INT2 TC1 IO I I PORT12 External interrupt 2 input TC1 input P11 INT1 24 IO I PORT11 External interrupt 1 input P10 TC3 PDO3/PWM3 IO I O PORT10 TC3 input PDO3/PWM3 output P22 XTOUT 7 IO O PORT22 Resonator connecting pins(32.768kHz) for inputting external clock P21 XTIN 6 IO I PORT21 Resonator connecting pins(32.768kHz) for inputting external clock P20 STOP INT5 IO I I PORT20 STOP mode release signal input External interrupt 5 input P37 AIN7 STOP5 IO I I PORT37 Analog Input7 STOP5 input

1.4 Pin Names and Functions TMP86CH47AUG

I I PORT36 Analog Input6 STOP4 input P35 AIN5 STOP3 IO I I PORT35 Analog Input5 STOP3 input P34 AIN4 STOP2 IO I I PORT34 Analog Input4 STOP2 input P33 AIN3 29 IO I PORT33 Analog Input3 P32 AIN2 28 IO I PORT32 Analog Input2 P31 AIN1 27 IO I PORT31 Analog Input1 P30 AIN0 26 IO I PORT30 Analog Input0 P47 44 IO PORT47 P46 43 IO PORT46 P45 42 IO PORT45 P44 41 IO PORT44 P43 40 IO PORT43 P42 39 IO PORT42 P41 38 IO PORT41 P40 37 IO PORT40 XIN 2 I Resonator connecting pins for high-frequency clock XOUT 3 O Resonator connecting pins for high-frequency clock RESET 8 IO Reset signal TEST 4 I Test pin for out-going test. Normally, be fixed to low. VAREF 34 I Analog Base Voltage Input Pin for A/D Conversion AVDD 35 I Analog Power Supply AVSS 36 I Analog Power Supply VDD 5 I Power Supply VSS 1 I 0(GND) Table 1-1 Pin Names and Functions(2/2) Pin Name Pin Number Input/Output Functions

1. Operational Description

2.1 CPU Core Functions

The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit.

2.1.1 Memory Address Map

The TMP86CH47AUG memory is composed MaskROM, RAM and SFR(Special function register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the TMP86CH47AUG memory address map. Figure 2-1 Memory Address Map

2.1.2 Program Memory (MaskROM)

The TMP86CH47AUG has a 16384 bytes (Address C000H to FFFFH) of program memory (MaskROM ).

2.1.3 Data Memory (RAM)

The TMP86CH47AUG has 512bytes (Address 0040H to 023FH) of internal RAM. The first 192 bytes (0040H to 00FFH) of the internal RA M are located in the direct area; inst ructions with shorten operations are available against such an area. The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. SFR 0000H 64 bytes SFR: RAM: Special function register includes: I/O ports Peripheral control registers Peripheral status registers System control registers Program status word Random access memory includes: Data memory Stack 003F H RAM 0040H 512 bytes 023FH C000H MaskROM: Program memory MaskROM 16384 bytes FFC0H Vector table for vector call instructions (32 bytes)FFDFH FFE0H Vector table for interrupts (32 bytes)FFFFH

1. Operational Description

2.2 System Clock Controller TMP86CH47AUG

2.2 System Clock Controller

The system clock controller consists of a clock generator, a timing generator, and a standby controller. Figure 2-2 System Colck Control

2.2.1 Clock Generator

The clock generator generates the basic clock which pr ovides the system clocks supplied to the CPU core and peripheral hardware. It contains two oscillation ci rcuits: One for the high-frequency clock and one for the low-frequency clock. Power consumption can be reduced by switching of the standby controller to low-power operation based on the low-frequency clock. The high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator between the XIN/XOUT and XTIN/XTOUT pins respectively. Clock input from an exte rnal oscillator is also possible. In this case, external clock is applied to XIN/XTIN pin with XOUT/XTOUT pin not connected. Example :Clears RAM to “00H”. (TMP86CH47AUG) LD HL, 0040H ; Start address setup LD A, H ; Initial value (00H) setup LD BC, 01FFH SRAMCLR: LD (HL), A INC HL DEC BC JRS F, SRAMCLR TBTCR SYSCR2SYSCR1 XIN XOUT XTIN XTOUT fc 0036H 0038H 0039H fs Timing generator control register Timing generator Standby controller System clocks Clock generator control High-frequency clock oscillator Low-frequency clock oscillator Clock generator System control registers

Figure 2-3 Examples of Resonator Connection Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with dis- abling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. The system to require the adjustment of the oscillation frequency should create the program for the adjust- ment in advance. XOUTXIN (Open) XOUTXIN XTOUTXTIN (Open) XTOUTXTIN (a) Crystal/Ceramic resonator (b) External oscillator (c) Crystal (d) External oscillator High-frequency clock Low-frequency clock

1. Operational Description

2.2.2 Timing Generator

The timing generator generates the various system cloc ks supplied to the CPU core and peripheral hardware from the basic clock (fc or fs). The timing generator provides the following functions. 1. Generation of main system clock 2. Generation of divider output ( DVO) pulses 3. Generation of source clocks for time base timer 4. Generation of source clocks for watchdog timer 5. Generation of internal source clocks for timer/counters 6. Generation of warm-up clocks for releasing STOP mode The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator, and machine cycle counters. An input clock to the 7th stage of the divider depends on the operating mode, SYSCR2<SYSCK> and TBTCR<DV7CK>, that is shown in Figure 2-4. As reset and STOP mode star ted/canceled, the prescaler and the divider are cleared to “0”. Figure 2-4 Configuration of Timing Generator Multi- plexer High-frequency clock fc Low-frequency clock fs Divider SYSCK fc/4 fc or fs Machine cycle countersMain system clock generator 1 21 432 87 109 1211 1413 1615 DV7CK Multiplexer Warm-up controller Watchdog timer A S B Y S A0 Y0 A1 Y1 5 6 17 18 19 20 21 Timer counter, Serial interface, Time-base-timer, divider output, etc. (Peripheral functions)

Note 1: In single clock mode, do not set DV7CK to “1”. Note 2: Do not set “1” on DV7CK while the low-frequency clock is not operated stably. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care Note 4: In SLOW1/2 and SLEEP1/2 modes, the DV7CK setting is ineffective, and fs is input to the 7th stage of the divider. Note 5: When STOP mode is entered from NORMAL1/2 mode, the DV7CK setting is ineffective during the warm-up period after release of STOP mode, and the 6th stage of the divider is input to the 7th stage during this period. Instruction execution and peripheral hardware operation are synchronized with the main system clock. The minimum instruction execution uni t is called an “machine cycle”. There are a total of 10 different types of instructions for the TLCS-870/C Series: Ra nging from 1-cycle instructions which require one machine cycle for execution to 10-cyc le instructions which require 10 machine cycles fo r execution. A machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock. Figure 2-5 Machine Cycle

2.2.3 Operation Mode Control Circuit

The operation mode control circuit starts and stops th e oscillation circuits for the high-frequency and low- frequency clocks, and switches the main system clock. There are three operating modes: Single clock mode, dual clock mode and STOP mode. These modes are cont rolled by the system cont rol registers (SYSCR1 and SYSCR2). Figure 2-6 shows the operating mode transition diagram. Only the oscillation circuit for the high-frequenc y clock is used, and P21 (XTIN) and P22 (XTOUT) pins are used as input/output ports . The main-system clock is obtained from the high-frequency clock. In the single-clock mode, the machine cycle time is 4/fc [s]. (1) NORMAL1 mode In this mode, both the CPU core and on-chip pe ripherals operate using the high-frequency clock. The TMP86CH47AUG is placed in this mode after reset. Timing Generator Control Register TBTCR (0036H) 76 5 432 1 0 (DVOEN) (DVOCK) DV7CK (TBTEN) (TBTCK) (Initial value: 0000 0000) DV7CK Selection of input to the 7th stage of the divider 0: fc/28 [Hz] 1: fs R/W Main system clock State Machine cycle S3S2S1S0 S3S2S1S0 1/fc or 1/fs [s]

1. Operational Description

(2) IDLE1 mode In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are halted; however on-chip peripherals remain active (Operate using the high-frequency clock). IDLE1 mode is started by SYSCR2<IDLE> = "1", and IDLE1 mode is released to NORMAL1 mode by an interrupt request from the on-chip peripherals or external interrupt inputs. When the IMF (Interrupt master enable flag) is “1” (Interrupt enable), the execution will resume with the acceptance of the interrupt, and the operation will return to normal after the interrupt service is completed. When the IMF is “0” (Interrupt disable), the execution will resume with the instruction which follows the IDLE1 mode start instruction. (3) IDLE0 mode In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. This mode is enabled by SYSCR2<TGHALT> = "1". When IDLE0 mode starts, the CPU stops and the timing generator stops feeding the clock to the peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected with TBTCR<TBTCK>, the timing generator starts feeding the clock to all peripheral circuits. When returned from IDLE0 mode, the CPU rest arts operating, entering NORMAL1 mode back again. IDLE0 mode is entered and returned regardless of how TBTCR<TBTEN> is set. When IMF = “1”, EF6 (TBT interrupt individual enable flag) = “1”, and TB TCR<TBTEN> = “1”, interrupt pro- cessing is performed. When IDLE0 mode is entered while TBTCR<TBTEN> = “1”, the INTTBT interrupt latch is set after returning to NORMAL1 mode. Both the high-frequency and low-frequency oscillatio n circuits are used in th is mode. P21 (XTIN) and P22 (XTOUT) pins cannot be used as input/output ports. The main system clock is obtained from the high-frequency clock in NORMAL2 and IDLE2 modes, and is obtained from the low-frequency clock in SLOW and SLEEP modes. Th e machine cycle time is 4/fc [s] in the NORMAL2 and IDLE2 modes, and 4/fs [s] (122 µs at fs = 32.768 kHz) in the SLOW and SLEEP modes. The TLCS-870/C is placed in the signal-clock mode during reset. To use the dual-clock mode, the low- frequency oscillator should be turned on at the start of a program. (1) NORMAL2 mode In this mode, the CPU core operates with the high-frequency clock. On-chip peripherals operate using the high-frequency clock and/or low-frequency clock. (2) SLOW2 mode In this mode, the CPU core operates with the lo w-frequency clock, while both the high-frequency clock and the low-frequency clock are operated. As the SYSCR2<SYSCK> becomes "1", the hard- ware changes into SLOW2 mode. As the SYSCR2 <SYSCK> becomes “0”, the hardware changes into NORMAL2 mode. As the SYSCR2<XEN> beco mes “0”, the hardware changes into SLOW1 mode. Do not clear SYSCR2<XTEN> to “0” during SLOW2 mode. (3) SLOW1 mode This mode can be used to reduce power-consu mption by turning off oscillation of the high-fre- quency clock. The CPU core and on-chip peripherals operate using the low-frequency clock.

Switching back and forth between SLOW1 and SLOW2 modes are performed by SYSCR2<XEN>. In SLOW1 and SLEEP modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. (4) IDLE2 mode In this mode, the internal oscillation circuit remain active. The CPU and the watchdog timer are halted; however, on-chip peripherals remain activ e (Operate using the high-frequency clock and/or the low-frequency clock). Starting and releasing of IDLE2 mode are the same as for IDLE1 mode, except that operation returns to NORMAL2 mode. (5) SLEEP1 mode In this mode, the internal oscillation circuit of the low-frequency clock remains active. The CPU, the watchdog timer, and the internal oscillation circuit of the high-frequency clock are halted; how- ever, on-chip peripherals remain active (Operate using the low-frequency clock). Starting and releas- ing of SLEEP mode are the same as for IDLE1 mode, except that operation returns to SLOW1 mode. In SLOW1 and SLEEP1 modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. (6) SLEEP2 mode The SLEEP2 mode is the idle mode corresponding to the SLOW2 mode. The status under the SLEEP2 mode is same as that under the SLEEP1 mode, except for the oscillation circuit of the high- frequency clock. (7) SLEEP0 mode In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. This mode is enabled by setting “1” on bit SYSCR2<TGHALT>. When SLEEP0 mode starts, the CP U stops and the timing generator stops feeding the clock to the peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected with TBTCR<TBTCK>, the timing generator starts feeding the clock to all peripheral circuits. When returned from SLEEP0 mode, the CPU restarts operating, entering SLOW1 mode back again. SLEEP0 mode is entered and returned regardless of how TBTCR<TBTEN> is set. When IMF = “1”, EF6 (TBT interrupt individual enable flag) = “1”, and TBTCR<TBTEN> = “1”, interrupt pro- cessing is performed. When SLEEP0 mode is entered while TBTCR<TBTEN> = “1”, the INTTBT interrupt latch is set after returning to SLOW1 mode. In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The internal status immediately prior to the halt is held with a lowest power consumption during STOP mode. STOP mode is started by the syst em control register 1 (SYSCR1), an d STOP mode is released by a inputting (Either level-sensitive or edge-sens itive can be programmably selected) to the STOP pin. After the warm-up period is completed, the execution resumes with the instruction which follows the STOP mode start instruction.

1. Operational Description

Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1 and IDLE2 are called IDLE; SLEEP0, SLEEP1 and SLEEP2 are called SLEEP. Note 2: The mode is released by falling edge of TBTCR<TBTCK> setting. Figure 2-6 Operating Mode Transition Diagram Table 2-1 Operating Mode and Conditions Operating Mode Oscillator CPU Core TBT Other Peripherals Machine Cycle TimeHigh Frequency Low Frequency Single clock RESET Oscillation Stop Reset Reset Reset 4/fc [s] NORMAL1 Operate Operate Operate IDLE1 HaltIDLE0 Halt STOP Stop Halt – Dual clock NORMAL2 Oscillation Oscillation Operate with high frequency Operate Operate 4/fc [s] IDLE2 Halt SLOW2 Operate with low frequency 4/fs [s] SLEEP2 Halt SLOW1 Stop Operate with low frequency SLEEP1 HaltSLEEP0 Halt STOP Stop Halt – Note 2 SYSCR2<XEN> = "1" STOP pin input STOP pin input STOP pin input Interrupt Interrupt SYSCR2<XEN> = "0" SYSCR2<SYSCK> = "1" SYSCR2<XTEN> = "0" SYSCR2<SYSCK> = "0" SYSCR1<STOP> = "1" SYSCR1<STOP> = "1" SYSCR1<STOP> = "1" SYSCR2<IDLE> = "1" SYSCR2<IDLE> = "1" Interrupt SYSCR2<IDLE> = "1" SYSCR2<IDLE> = "1" Interrupt SYSCR2<TGHALT> = "1" Reset release NORMAL1 mode IDLE0 mode (a) Single-clock mode IDLE1 mode NORMAL2 mode IDLE2 mode SYSCR2<XTEN> = "1" SLOW2 mode SLEEP2 mode SLOW1 mode SLEEP1 mode SLEEP0 mode RESET (b) Dual-clock mode STOP SYSCR2<TGHALT> = "1"Note 2

Note 1: Always set RETM to “0” when transiting from NORMAL mode to STOP mode. Always set RETM to “1” when transiting from SLOW mode to STOP mode. Note 2: When STOP mode is released with RESET pin input, a return is made to NORMAL1 regardless of the RETM contents. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *; Don’t care Note 4: Bits 1 in SYSCR1 are read as undefined data when a read instruction is executed. Note 5: As the hardware becomes STOP mode under OUTEN = “0”, input value is fixed to “0”; therefore it may cause external interrupt request on account of falling edge. Note 6: When the key-on wakeup is used, RELM should be set to "1". Note 7: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes High-Z mode. Note 8: The warmig-up time should be set correctly for using oscillator. Note 1: A reset is applied if both XEN and XTEN are cleared to “0”, XEN is cleared to “0” when SYSCK = “0”, or XTEN is cleared to “0” when SYSCK = “1”. Note 2: *: Don’t care, TG: Timing generator, *; Don’t care Note 3: Bits 3, 1 and 0 in SYSCR2 are always read as undefined value. Note 4: Do not set IDLE and TGHALT to “1” simultaneously. Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the period of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR<TBTCK>. Note 6: When IDLE1/2 or SLEEP1/2 mode is released, IDLE is automatically cleared to “0”. Note 7: When IDLE0 or SLEEP0 mode is released, TGHALT is automatically cleared to “0”. System Control Register 1 S Y S C R 1 76543210 (0038H) STOP RELM RETM OUTEN WUT (Initial value: 0000 000*) STOP STOP mode start 0: CPU core and peripherals remain active 1: CPU core and peripherals are halted (Start STOP mode) R/W RELM Release method for STOP mode 0: Edge-sensitive release 1: Level-sensitive release R/W RETM Operating mode after STOP mode 0: Return to NORMAL1/2 mode 1: Return to SLOW1 mode R/W OUTEN Port output during STOP mode 0: High impedance 1: Output kept R/W WUT Warm-up time at releasing STOP mode Return to NORMAL mode Return to SLOW mode R/W 000 010 100 110 *01 *11 3 x 2 16/fc 216/fc 3 x 214/fc 214/fc 3 x 210/fc 210/fc 3 x 213/fs 213/fs 3 x 26/fs 26/fs 3 x 26/fs 26/fs System Control Register 2 SYSCR2 (0039H) 76543210 XEN XTEN SYSCK IDLE TGHALT (Initial value: 1000 *0**) XEN High-frequency oscillator control 0: Turn off oscillation 1: Turn on oscillation R/WXTEN Low-frequency oscillator control 0: Turn off oscillation 1: Turn on oscillation SYSCK Main system clock select (Write)/main system clock moni- tor (Read) 0: High-frequency clock (NORMAL1/NORMAL2/IDLE1/IDLE2) 1: Low-frequency clock (SLOW1/SLOW2/SLEEP1/SLEEP2) IDLE CPU and watchdog timer control (IDLE1/2 and SLEEP1/2 modes) 0: CPU and watchdog timer remain active 1: CPU and watchdog timer are stopped (Start IDLE1/2 and SLEEP1/2 modes) R/W TGHALT TG control (IDLE0 and SLEEP0 modes) 0: Feeding clock to all peripherals from TG 1: Stop feeding clock to peripherals except TBT from TG. (Start IDLE0 and SLEEP0 modes)

1. Operational Description

Note 8: Before setting TGHALT to “1”, be sure to stop peripherals. If peripherals are not stopped, the interrupt latch of peripherals may be set after IDLE0 or SLEEP0 mode is released.

2.2.4 Operating Mode Control

STOP mode is controlled by the system control register 1, the STOP pin input and key-on wakeup input (STOP5 to STOP2) which is controlled by the STOP mode release control register (STOPCR). The STOP pin is also used both as a port P20 and an INT5 (external interrupt input 5) pin. STOP mode is started by setting SYSCR1<STOP> to “1”. During STOP mode, the following status is maintained. 1. Oscillations are turned off, and all internal operations are halted. 2. The data memory, registers, the program status wo rd and port output latches are all held in the status in effect before STOP mode was entered. 3. The prescaler and the divider of th e timing generator are cleared to “0”. 4. The program counter holds the address 2 ahead of the instruction (e.g., [SET (SYSCR1).7]) which started STOP mode. STOP mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be selected with the SYSCR1<RELM>. Do not use any key-on wakeup input (STOP5 to STOP2) for releas- ing STOP mode in edge-sensitive mode. Note 1: The STOP mode can be released by either the STOP or key-on wakeup pin (STOP5 to STOP2). However, because the STOP pin is different from the key-on wakeup and can not inhibit the release input, the STOP pin must be used for releasing STOP mode. Note 2: During STOP period (from start of STOP mode to end of warm up), due to changes in the external interrupt pin signal, interrupt latches may be set to “1” and interrupts may be accepted immediately after STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before enabling interrupts after STOP mode is released, clear unnecessary interrupt latches. (1) Level-sensitive release mode (RELM = “1”) In this mode, STOP mode is released by setting the STOP pin high or setting the STOP5 to STOP2 pin input which is enabled by STOPCR. This mo de is used for capacitor backup when the main power supply is cut off and long term battery backup. Even if an instruction for starting STOP mode is executed while STOP pin input is high or STOP5 to STOP2 input is low, STOP mode does not start but instead the warm-up sequence starts immedi- ately. Thus, to start STOP mode in the level-sensitive release mode, it is necessary for the program to first confirm that the STOP pin input is low or STOP5 to STOP2 input is high. The following two methods can be used for confirmation. 1. Testing a port. 2. Using an external interrupt input INT5 (INT5 is a falling edge-sensitive input). Example 1 :Starting STOP mode from NORMAL mode by testing a port P20. LD (SYSCR1), 01010000B ; Sets up the level-sensitive release mode SSTOPH: TEST (P2PRD). 0 ; Wait until the STOP pin input goes low level JRS F, SSTOPH DI ; IMF ← 0 SET (SYSCR1). 7 ; Starts STOP mode

Figure 2-7 Level-sensitive Release Mode Note 1: Even if the STOP pin input is low after warm-up start, the STOP mode is not restarted. Note 2: In this case of changing to the level-sensitive mode from the edge-sensitive mode, the release mode is not switched until a rising edge of the STOP pin input is detected. (2) Edge-sensitive release mode (RELM = “0”) In this mode, STOP mode is released by a rising edge of the STOP pin input. This is used in appli- cations where a relatively short pr ogram is executed repeat edly at periodic intervals. This periodic signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In the edge-sensitive release mode, STOP mode is started even when the STOP pin input is high level. Do not use any STOP5 to STOP2 pin input for releasing STOP mode in edge-sensitive release mode. Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt. PINT5: TEST (P2PRD). 0 ; To reject noise, STOP mode does not start if JRS F, SINT5 port P20 is at high LD (SYSCR1), 01010000B ; Sets up the level-sensitive release mode. DI ; IMF ← 0 SET (SYSCR1). 7 ; Starts STOP mode SINT5: RETI Example :Starting STOP mode from NORMAL mode DI ; IMF ← 0 LD (SYSCR1), 10010000B ; Starts after specified to the edge-sensitive release mode VIH NORMAL operation Warm upSTOP operation Confirm by program that the STOP pin input is low and start STOP mode. Always released if the STOP pin input is high. STOP pin XOUT pin STOP mode is released by the hardware. NORMAL operation

1. Operational Description

Figure 2-8 Edge-sensitive Release Mode STOP mode is released by the following sequence. 1. In the dual-clock mode, when returning to NORMAL2, both the high-frequency and low- frequency clock oscillators are turned on; when returning to SLOW1 mode, only the low- frequency clock oscillator is turned on. In the single-clock mode, only the high-frequency clock oscillator is turned on. 2. A warm-up period is inserted to allow oscillation time to stabilize. During warm up, all internal operations remain halted. Six different warm-up times can be selected with the SYSCR1<WUT> in accordance with the resonator characteristics. 3. When the warm-up time has elapsed, normal operation resumes with the instruction follow- ing the STOP mode start instruction. Note 1: When the STOP mode is released, the start is made after the prescaler and the divider of the timing generator are cleared to "0". Note 2: STOP mode can also be released by inputting low level on the RESET pin, which immediately performs the normal reset operation. Note 3: When STOP mode is released with a low hold voltage, the following cautions must be observed. The power supply voltage must be at the operating voltage level before releasing STOP mode. The RESET pin input must also be “H” level, rising together with the power supply voltage. In this case, if an external time constant circuit has been connected, the RESET pin input voltage will increase at a slower pace than the power supply voltage. At this time, there is a danger that a reset may occur if input voltage level of the RESET pin drops below the non-inverting high-level input voltage (Hysteresis input). Note 1: The warm-up time is obtained by dividing the basic clock by the divider. Therefore, the warm-up time may include a certain amount of error if there is any fluctuation of the oscillation frequency when STOP mode is released. Thus, the warm-up time must be considered as an approximate value. Table 2-2 Warm-up Time Example (at fc = 16.0 MHz, fs = 32.768 kHz) WUT Warm-up Time [ms] Return to NORMAL Mode Return to SLOW Mode 000 010 100 110 *01 *11 12.288 4.096 3.072 1.024 0.192 0.064 750 250 5.85 1.95 5.9 2.0 NORMAL operation NORMAL operation VIH STOP mode is released by the hardware at the rising edge of STOP pin input. Warm up STOP mode started by the program. STOP operation STOP operation STOP pin XOUT pin

Figure 2-9 STOP Mode Start/Release Instruction address a + 4 Instruction address a + 3 Turn on Turn on Warm up Halt SET (SYSCR1). 7 Turn off (a) STOP mode start (Example: Start with SET (SYSCR1). 7 instruction located at address a) a + 6 a + 5 a + 4 a + 3 a + 2 n + 2 n + 3 n + 4 a + 3 n + 1 Instruction address a + 2 210 3 (b) STOP mode release Count up Turn off Halt Oscillator circuit Program counter Instruction execution Divider Main system clock Oscillator circuit STOP pin input Program counter Instruction execution Divider Main system clock

1. Operational Description

IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following status is maintained during these modes. 1. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to operate. 2. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before these modes were entered. 3. The program counter holds the address 2 ahead of the instruction which starts these modes. Figure 2-10 IDLE1/2 and SLEEP1/2 Modes ResetReset input “0” “1” (Interrupt release mode) Yes No No CPU and WDT are halted Interrupt request IMF Interrupt processing Normal release mode Yes Starting IDLE1/2 and SLEEP1/2 modes by instruction Execution of the instruc- tion which follows the IDLE1/2 and SLEEP1/2 modes start instruction

• Start the IDLE1/2 and SLEEP1/2 modes After IMF is set to "0", set the individual inte rrupt enable flag (EF) which releases IDLE1/2 and SLEEP1/2 modes. To start IDLE1/2 and SLEEP1/2 modes, set SYSCR2<IDLE> to “1”.
• Release the IDLE1/2 and SLEEP1/2 modes IDLE1/2 and SLEEP1/2 modes include a normal release mode and an interrupt release mode. These modes are selected by interrupt master en able flag (IMF). After releasing IDLE1/2 and SLEEP1/2 modes, the SYSCR2<IDLE> is automatically cleared to “0” and the operation mode is returned to the mode preceding IDLE1/2 and SLEEP1/2 modes. IDLE1/2 and SLEEP1/2 modes can also be released by inputting low level on the RESET pin. After releasing reset, the operation mode is started from NORMAL1 mode. (1) Normal release mode (IMF = “0”) IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled by the individual interrupt enable flag (EF). After the interrupt is generated, the program operation is resumed from the instruction following the IDLE1/2 and SLEEP1/2 mo des start instruction. Normally, the interrupt latches (IL) of the interrupt source used for releasing must be cleared to “0” by load instructions. (2) Interrupt release mode (IMF = “1”) IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled with the individual interrupt enable flag (EF) and the interrupt processi ng is started. After the interrupt is processed, the program operation is resumed from the instruction following the instruction, which starts IDLE1/2 and SLEEP1/2 modes. Note: When a watchdog timer interrupts is generated immediately before IDLE1/2 and SLEEP1/2 modes are started, the watchdog timer interrupt will be processed but IDLE1/2 and SLEEP1/2 modes will not be started.

1. Operational Description

Figure 2-11 IDLE1/2 and SLEEP1/2 Modes Start/Release Halt Halt Halt Halt Operate Instruction address a + 2 a + 3 a + 2 a + 4 a + 3 a + 3 Halt SET (SYSCR2). 4 Operate Operate Operate Acceptance of interrupt 㽲㩷Normal release mode 㽳㩷Interrupt release mode Main system clock Interrupt request Program counter Instruction execution Watchdog timer Main system clock Interrupt request Program counter Instruction execution Watchdog timer Main system clock Interrupt request Program counter Instruction execution Watchdog timer (a) IDLE1/2 and SLEEP1/2 modes start (Example: Starting with the SET instruction located at address a) (b) IDLE1/2 and SLEEP1/2 modes release

IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes. 1. Timing generator stops feeding clock to peripherals except TBT. 2. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before IDLE0 and SLEEP0 modes were entered. 3. The program counter holds the address 2 ahead of the instruction which starts IDLE0 and SLEEP0 modes. Note: Before starting IDLE0 or SLEEP0 mode, be sure to stop (Disable) peripherals. Figure 2-12 IDLE0 and SLEEP0 Modes Yes (Normal release mode) Yes (Interrupt release mode) No YesReset input CPU and WDT are halted Reset TBTsource clock falling edge TBTCR<TBTEN> = "1" Interrupt processing IMF = "1" Yes TBT interrupt enable No No No No Stopping peripherals by instruction Yes Starting IDLE0, SLEEP0 modes by instruction Execution of the instruction which follows the IDLE0, SLEEP0 modes start instruction

1. Operational Description

• Start the IDLE0 and SLEEP0 modes Stop (Disable) peripherals such as a timer counter. To start IDLE0 and SLEEP0 modes, set SYSCR2<TGHALT> to “1”.
• Release the IDLE0 and SLEEP0 modes IDLE0 and SLEEP0 modes include a normal release mode and an interrupt release mode. These modes are selected by inte rrupt master flag (IMF), the i ndividual interrupt enable flag of TBT and TBTCR<TBTEN>. After releasing IDLE0 and SLEEP0 modes, the SYSCR2<TGHALT> is automatically cleared to “0” and the operation mode is returned to the mode preceding IDLE0 and SLEEP0 modes. Before starting the IDLE0 or SLEEP0 mode, when the TBTCR<TBTEN> is set to “1”, INTTBT interrupt latch is set to “1”. IDLE0 and SLEEP0 modes can also be re leased by inputting low level on the RESET pin. After releasing reset, the operation mode is started from NORMAL1 mode. Note: IDLE0 and SLEEP0 modes start/release wi thout reference to TBTCR<TBTEN> setting. (1) Normal release mode (IMF •EF6•TBTCR<TBTEN> = “0”) IDLE0 and SLEEP0 modes are released by the source clock falling edge, which is setting by the TBTCR<TBTCK>. After the falling edge is detect ed, the program operation is resumed from the instruction following the IDLE0 and SLEEP0 modes start instruction. Before starting the IDLE0 or SLEEP0 mode, when the TBTCR<TBTEN> is set to “1”, INTTBT interrupt latch is set to “1”. (2) Interrupt release mode (IMF •EF6•TBTCR<TBTEN> = “1”) IDLE0 and SLEEP0 modes are released by the source clock falling edge, which is setting by the TBTCR<TBTCK> and INTTBT interrupt processing is started. Note 1: Because returning from IDLE0, SLEEP0 to NORMAL1, SLOW1 is executed by the asynchro- nous internal clock, the period of IDLE0, SLEEP0 mode might be the shorter than the period set- ting by TBTCR<TBTCK>. Note 2: When a watchdog timer interrupt is generated immediately before IDLE0/SLEEP0 mode is started, the watchdog timer interrupt will be processed but IDLE0/SLEEP0 mode will not be started.

Figure 2-13 IDLE0 and SLEEP0 Modes Start/Release Halt Halt Operate Instruction address a + 2 Halt Operate SET (SYSCR2). 2 Halt Operate Acceptance of interrupt Halt 㽲㩷Normal release mode 㽳㩷Interrupt release mode Main system clock Interrupt request Program counter Instruction execution Watchdog timer Main system clock TBT clock TBT clock Program counter Instruction execution Watchdog timer Main system clock Program counter Instruction execution Watchdog timer a + 3 a + 2 a + 4 a + 3 a + 3 (a) IDLE0 and SLEEP0 modes start (Example: Starting with the SET instruction located at address a (b) IDLE and SLEEP0 modes release

1. Operational Description

SLOW mode is controlled by the system control register 2 (SYSCR2). The following is the methods to switch the mode with the warm-up counter. (1) Switching from NORMAL2 mode to SLOW1 mode First, set SYSCR2<SYSCK> to switch the main system clock to the low-frequency clock for SLOW2 mode. Next, clear SYSCR2<XEN> to turn off high-frequency oscillation. Note: The high-frequency clock can be co ntinued oscillation in order to return to NORMAL2 mode from SLOW mode quickly. Always turn off oscillation of high-frequency clock when switching from SLOW mode to stop mode. Example 1 :Switching from NORMAL2 mode to SLOW1 mode. SET (SYSCR2). 5 ; SYSCR2<SYSCK> ← 1 (Switches the main system clock to the low-frequency clock for SLOW2) CLR (SYSCR2). 7 ; SYSCR2<XEN> ← 0 (Turns off high-frequency oscillation) Example 2 :Switching to the SLOW1 mode after low-frequency clock has stabilized. SET (SYSCR2). 6 ; SYSCR2<XTEN> ← 1 LD (TC3CR), 43H ; Sets mode for TC4, 3 (16-bit mode, fs for source) LD (TC4CR), 05H ; Sets warming-up counter mode LDW (TTREG3), 8000H ; Sets warm-up time (Depend on oscillator accompanied) DI ; IMF ← 0 SET (EIRH). 1 ; Enables INTTC4 EI ; IMF ← 1 SET (TC4CR). 3 ; Starts TC4, 3 PINTTC4: CLR (TC4CR). 3 ; Stops TC4, 3 SET (SYSCR2). 5 ; SYSCR2<SYSCK> ← 1 (Switches the main system clock to the low-frequency clock) CLR (SYSCR2). 7 ; SYSCR2<XEN> ← 0 (Turns off high-frequency oscillation) RETI VINTTC4: DW PINTTC4 ; INTTC4 vector table

(2) Switching from SLOW1 mode to NORMAL2 mode Note: After SYSCK is cleared to “0”, executing the instructions is continiued by the low-frequency clock for the period synchronized with low-frequency and high-frequency clocks. First, set SYSCR2<XEN> to turn on the high-fre quency oscillation. When time for stabilization (Warm up) has been taken by the timer/counter (TC4,TC3), clear SYSCR2<SYSCK> to switch the main system clock to the high-frequency clock. SLOW mode can also be released by inputting low level on the RESET pin. After releasing reset, the operation mode is started from NORMAL1 mode. Example :Switching from the SLOW1 mode to the NORMAL2 mode (fc = 16 MHz, warm-up time is 4.0 ms). SET (SYSCR2). 7 ; SYSCR2<XEN> ← 1 (Starts high-frequency oscillation) LD (TC3CR), 63H ; Sets mode for TC4, 3 (16-bit mode, fc for source) LD (TC4CR), 05H ; Sets warming-up counter mode LD (TTREG4), 0F8H ; Sets warm-up time DI ; IMF ← 0 SET (EIRH). 1 ; Enables INTTC4 EI ; IMF ← 1 SET (TC4CR). 3 ; Starts TC4, 3 PINTTC4: CLR (TC4CR). 3 ; Stops TC4, 3 CLR (SYSCR2). 5 ; SYSCR2<SYSCK> ← 0 (Switches the main system clock to the high-frequency clock) RETI VINTTC4: DW PINTTC4 ; INTTC4 vector table High-frequency clock Low-frequency clock Main system clock SYSCK

1. Operational Description

Figure 2-14 Switching between the NORMAL2 and SLOW Modes SET (SYSCR2). 7 NORMAL2 mode CLR (SYSCR2). 7SET (SYSCR2). 5 NORMAL2 mode Turn off (a) Switching to the SLOW mode SLOW1 mode SLOW2 mode CLR (SYSCR2). 5 (b) Switching to the NORMAL2 mode High- frequency clock Low- frequency clock Main system clock Instruction execution SYSCK XEN High- frequency clock Low- frequency clock Main system clock Instruction execution SYSCK XEN SLOW1 mode Warm up during SLOW2 mode

2.3 Reset Circuit

The TMP86CH47AUG has four types of reset generation pr ocedures: An external rese t input, an address trap reset, a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and the system clock reset are a malfunction reset. When the malfunction rese t request is detected, reset occurs during the maximum 24/fc[s] (The RESET pin outputs "L" level). The malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initial- ized when power is turned on. Therefore, reset may occur during maximum 24/fc[s] (1.5 µs at 16.0 MHz) when power is turned on. RESET pin outputs "L" level during maximum 24/fc[s] (1.5µs at 16.0MHz). Table 2-3 shows on-chip hardware initialization by reset action.

2.3.1 External Reset Input

The RESET pin contains a Schmitt trigger (Hysteresis) with an internal pull-up resistor. When the RESET pin is held at “L” level for at least 3 machine cycles (12/fc [s]) with the power supply volt- age within the operating voltage range and oscillation stab le, a reset is applied and the internal state is initial- ized. When the RESET pin input goes high, the reset operation is rele ased and the program execution starts at the vector address stored at addresses FFFEH to FFFFH. Figure 2-15 Reset Circuit Table 2-3 Initializing Internal Status by Reset Action On-chip Hardware Initial Value On-chip Hardware Initial Value Program counter (PC) (FFFEH) Prescaler and divider of timing generator 0Stack pointer (SP) Not initialized General-purpose registers (W, A, B, C, D, E, H, L, IX, IY) Not initialized Jump status flag (JF) Not initialized Watchdog timer Enable Zero flag (ZF) Not initialized Output latches of I/O ports Refer to I/O port circuitry Carry flag (CF) Not initialized Half carry flag (HF) Not initialized Sign flag (SF) Not initialized Overflow flag (VF) Not initialized Interrupt master enable flag (IMF) 0 Interrupt individual enable flags (EF) 0 Control registers Refer to each of control registerInterrupt latches (IL) 0 RAM Not initialized Internal resetRESET VDD Malfunction reset output circuit Watchdog timer reset Address trap reset System clock reset

1. Operational Description

2.3 Reset Circuit TMP86CH47AUG

2.3.2 Address trap reset

If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (when WDTCR1<ATAS> is set to “1”) or the SFR area, address trap reset will be gen- erated. The reset time is maximum 24/fc[s] (1.5µs at 16.0 MHz). Then, the RESET pin outputs "L" level during maximum 24/fc[s]. Note:The operating mode under address trapped is alternative of reset or interrupt. The address trap area is alter- native. Note 1: Address “a” is in the SFR or on-chip RAM (WDTCR1<ATAS> = “1”) space. Note 2: During reset release, reset vector “r” is read out, and an instruction at address “r” is fetched and decoded. Note 3: Varies on account of external condition: voltage or capacitance Figure 2-16 Address Trap Reset

2.3.3 Watchdog timer reset

Refer to Section “Watchdog Timer”.

2.3.4 System clock reset

If the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of the CPU. (The oscillation is continued without stopping.) - In case of clearing SYSCR2<XEN> an d SYSCR2<XTEN> simultaneously to “0”. - In case of clearing SYSCR2<XEN> to “0”, when the SYSCR2<SYSCK> is “0”. - In case of clearing SYSCR2<XTEN> to “0”, when the SYSCR2<SYSCK> is “1”. The reset time is maximum 24/fc (1.5 µs at 16.0 MHz). Then, the RESET pin outputs "L" level during maxi- mum 24/fc[s] (1.5µs at 16.0MHz). Instruction at address r 16/fc [s]Maximum 24/fc [s] Instruction execution Internal reset signal RESET output JP a Reset release Address trap is occurred ("L" output) 4/fc to 12/fc [s] Note 3

1. Operational Description

1. Interrupt Control Circuit The TMP86CH47AUG has a total of 18 interrupt sources excluding reset, of which 2 source levels are multi- plexed. Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest are maskable. Interrupt sources are provided with interrupt latches (IL) , which hold interrupt requests, and independent vectors. The interrupt latch is set to “1” by the generation of its interrupt request wh ich requests the CPU to accept its inter- rupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable flag (EF). If more than one interrupts are generated simultaneously, interrup ts are accepted in order which is domi- nated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts. Note 1: The INTSEL register is used to select the interrupt source to be enabled for each multiplexed source level (see 3.3 Inte r- rupt Source Selector (INTSEL)). Note 2: To use the address trap interrupt (INTATRAP), clear WDTCR1<ATOUT> to “0” (It is set for the “reset request” after reset is cancelled). For details, see “Address Trap”. Note 3: To use the watchdog timer interrupt (INTWDT), clear WDTCR1<WDTOUT> to "0" (It is set for the "Reset request" after reset is released). For details, see "Watchdog Timer".

3.1 Interrupt latches (IL15 to IL2)

An interrupt latch is provided for eac h interrupt source, except for a software interrupt and an executed the unde- fined instruction interrupt. When interrupt request is genera ted, the latch is set to “1”, and the CPU is requested to accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting inter- rupt. All interrupt latches are initialized to “0” during reset. The interrupt latches are located on address 003CH and 003DH in SFR area. Each latch can be cleared to "0" indi- vidually by instruction. However, IL2 and IL3 should not be cleared to "0" by software. For clearing the interrupt latch, load instruction should be used and then IL2 and IL3 should be set to "1". If the read-modify-write instructions such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if inter- rupt is requested while such instructions are executed. Interrupt latches are not set to “1” by an instruction. Interrupt Factors Enable Condition Interrupt Latch Vector Address Priority Internal/External (Reset) Non-maskable – FFFE 1 Internal INTSWI (Software interrupt) Non-maskable – FFFC 2 Internal INTUNDEF (Executed the undefined instruction interrupt) Non-maskable – FFFC 2 Internal INTATRAP (Address trap interrupt) Non-maskable IL2 FFFA 2 Internal INTWDT (Watchdog timer interrupt) Non-maskable IL3 FFF8 2 External INT0 IMF• EF4 = 1, INT0EN = 1 IL4 FFF6 5 External INT1 IMF• EF5 = 1 IL5 FFF4 6 Internal INTTBT IMF• EF6 = 1 IL6 FFF2 7 Internal INTTC1 IMF• EF7 = 1 IL7 FFF0 8 External INT2 IMF• EF8 = 1 IL8 FFEE 9 Internal INTTC4 IMF• EF9 = 1 IL9 FFEC 10 Internal INTTC3 IMF• EF10 = 1 IL10 FFEA 11 External INT3 IMF• EF11 = 1 IL11 FFE8 12 Internal INTSIO IMF• EF12 = 1 IL12 FFE6 13 Internal INTRXD IMF• EF13 = 1 IL13 FFE4 14 External INT4 IMF• EF14 = 1, IL14ER = 0 IL14 FFE2 15 Internal INTTXD IMF• EF14 = 1, IL14ER = 1 External INT5 IMF• EF15 = 1, IL15ER = 0 IL15 FFE0 16 Internal INTADC IMF• EF15 = 1, IL15ER = 1

1. Interrupt Control Circuit

3.2 Interrupt enable register (EIR) TMP86CH47AUG

Since interrupt latches can be read, the status for interrupt requests can be monitored by software. Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1".

3.2 Interrupt enab le register (EIR)

The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable interrupts (Software interrupt, undefined instruction interr upt, address trap interrupt and watchdog interrupt). Non- maskable interrupt is accepted regardless of the contents of the EIR. The EIR consists of an interrupt mast er enable flag (IMF) and the individua l interrupt enable flags (EF). These registers are located on address 003AH and 003BH in SFR ar ea, and they can be read and written by an instructions (Including read-modify-write instructions such as bit manipulation or operation instructions).

3.2.1 Interrupt ma ster enable flag (IMF)

The interrupt enable register (IMF ) enables and disables the acceptance of the whole maskable interrupt. While IMF = “0”, all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (EF). By setting IMF to “1”, the interrupt becomes acceptable if the individuals are enabled. When an interrupt is accepted, IMF is cleared to “0” after the latest status on IMF is stacked. Thus the maskable inter- rupts which follow are disabled. By executing return interrupt instruction [RETI/RETN], the stacked data, which was the status before interrupt acceptance, is loaded on IMF again. The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruction. The IMF is normally set and cl eared by [EI] and [DI] instruction respectively. During reset, the IMF is initial- ized to “0”.

3.2.2 Individual interrupt enable flags (EF15 to EF4)

Each of these flags enables and disables the acceptan ce of its maskable interrupt . Setting the corresponding bit of an individual interrupt enable flag to “1” enables acceptance of its interrupt, and setting the bit to “0” dis- ables acceptance. During reset, all the individual interrupt enable flags (EF15 to EF4) are initialized to “0” and all maskable interrupts are not accepted until they are set to “1”. Note:In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute nor- mally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulat- ing EF or IL should be executed before setting IMF="1". Example 1 :Clears interrupt latches DI ; IMF ← 0 LDW (ILL), 111010000011 1111B ; IL12, IL10 to IL6 ← 0 EI ; IMF ← 1 Example 2 :Reads interrupt latchess LD WA, (ILL) ; W ← ILH, A ← ILL Example 3 :Tests interrupt latches TEST (ILL). 7 ; if IL7 = 1 then jump JR F, SSET

Example 1 :Enables interrupts individually and sets IMF DI ; IMF ← 0 LDW (EIRL), 1110100010100000B ; EF15 to EF13, EF11, EF7, EF5 ← 1 Note: IMF should not be set. EI ; IMF ← 1 Example 2 :C compiler description example unsigned int _io (3AH) EIRL; /* 3AH shows EIRL address */ _DI(); EIRL = 10100000B; _EI();

1. Interrupt Control Circuit

Note 1: To clear any one of bits IL7 to IL4, be sure to write "1" into IL2 and IL3. Note 2: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on inter- rupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be exe- cuted before setting IMF="1". Note 3: Do not clear IL with read-modify-write instructions such as bit operations. Note 1: *: Don’t care Note 2: Do not set IMF and the interrupt enable flag (EF15 to EF4) to “1” at the same time. Note 3: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on inter- rupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be exe- cuted before setting IMF="1". Interrupt Latches (Initial value: 00000000 000000) ILH,ILL (003DH, 003CH) 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 IL15 IL14 IL13 IL12 IL11 IL10 IL9 IL8 IL7 IL6 IL5 IL4 IL3 IL2 ILH (003DH) ILL (003CH) IL15 to IL2 Interrupt latches at RD 0: No interrupt request 1: Interrupt request at WR 0: Clears the interrupt request 1: (Interrupt latch is not set.) R/W Interrupt Enable Registers (Initial value: 00000000 0000*0) EIRH,EIRL (003BH, 003AH) 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 EF15 EF14 EF13 EF12 EF11 EF10 EF9 EF8 EF7 EF6 EF5 EF4 IMF EIRH (003BH) EIRL (003AH) EF15 to EF4 Individual-interrupt enable flag (Specified for each bit) Disables the acceptance of each maskable interrupt. Enables the acceptance of each maskable interrupt. R/W IMF Interrupt master enable flag 0: Disables the acceptance of all maskable interrupts Enables the acceptance of all maskable interrupts

3.3 Interrupt Sour ce Selector (INTSEL)

Each interrupt source that shares the interrupt source level with another interrupt source is allowed to enable the interrupt latch only when it is selected in the INTSEL register. The interrupt controller does not hold interrupt requests corresponding to interrupt sources that are not selected in the INTSEL register. Therefore, the INTSEL reg- ister must be set appropriately before interrupt requests are generated. The following interrupt sources share their interrupt source level; the source is selected onnthe register INTSEL. 1. INT4 and INTTXD share th e interrupt source level whose priority is 15. 2. INT5 and INTADC share the interrupt source level whose priority is 16.

3.4 Interrupt Sequence

An interrupt request, which raised inte rrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to “0” by resetting or an instruction. Interrupt acceptance sequence requires 8 machine cycles (2 µs @16 MHz) after the completion of the current instruction. The interrupt service task terminates upon execution of an interrupt return instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). Figure 3-1 shows the timing chart of interrupt acceptance processing. 3.4.1 Interrupt acceptance proc essing is packaged as follows. a. The interrupt master enab le flag (IMF) is cleared to “0” in order to disable the acceptance of any fol- lowing interrupt. b. The interrupt latch (IL) for the interrupt source accepted is cleared to “0”. c. The contents of the program coun ter (PC) and the program status word, including the interrupt master enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Mean- while, the stack pointer (SP) is decremented by 3. d. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vec- tor table, is transferred to the program counter. e. The instruction stored at the entry address of the interrupt service program is executed. Note:When the contents of PSW are saved on the stack, the contents of IMF are also saved. Interrupt source selector INTSEL (003EH) 76543210 IL14ER Selects INT4 or INTTXD 0: INT4 1: INTTXD R/W IL15ER Selects INT5 or INTADC 0: INT5 1: INTADC R/W

1. Interrupt Control Circuit

3.4 Interrupt Sequence TMP86CH47AUG

Note 1: a: Return address entry address, b: Entry address, c: Address which RETI instruction is stored Note 2: On condition that interrupt is enabled, it takes 38/fc [s] or 38/fs [s] at maximum (If the interrupt latch is set at the first machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set. Figure 3-1 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction Example: Correspondence be tween vector table address for INTTBT an d the entry address of the interrupt service program Figure 3-2 Vector table address,Entry address A maskable interrupt is not accepted until the IMF is set to “1” even if the maskable interrupt higher than the level of current servicing interrupt is requested. In order to utilize nested interrupt service, the IMF is set to “1” in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting IMF to “1”. As for non-maskable interrupt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested.

3.4.2 Saving/restoring general-purpose registers

During interrupt acceptance processing , the program counter (PC) and the program status word (PSW, includes IMF) are automatically saved on the stack, but the accumulator and others are not. These registers are saved by software if necessary. When multiple interrupt se rvices are nested, it is also necessary to avoid using the same data memory area for saving registers. The fo llowing methods are used to save/restore the general- purpose registers. aba c + 1 Execute instruction SP PC Execute instruction nn − 2 n - 3 n − 2n − 1n − 1n a + 2a + 1c + 2b + 3b + 2b + 1a + 1aa − 1 Execute RETI instructionInterrupt acceptanceExecute instruction Interrupt service task1-machine cycle Interrupt request Interrupt latch (IL) IMF D2H 03H D203H D204H 06H Vector table address Entry address 0FH Vector Interrupt service program FFF2H FFF3H

If only a specific register is saved or interrupts of the same source are nested, general-purpose registers can be saved/restored using the PUSH/POP instructions. Figure 3-3 Save/store register using PUSH and POP instructions To save only a specific register without nested interrupts, data transfer instructions are available. Example :Save/store register using PUSH and POP instructions PINTxx: PUSH WA ; Save WA register (interrupt processing) POP WA ; Restore WA register RETI ; RETURN Example :Save/store register using data transfer instructions PINTxx: LD (GSAVA), A ; Save A register (interrupt processing) LD A, (GSAVA) ; Restore A register RETI ; RETURN PCL PCH PSW At acceptance of an interrupt At execution of PUSH instruction At execution of RETI instruction At execution of POP instruction b-4 b-3 b-2 b-1 b PCL PCH PSW PCL PCH PSW SP Address (Example) SP SP SP A W b-5

1. Interrupt Control Circuit

Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing

3.4.3 Interrupt return

Interrupt return instructions [RETI]/[RETN] perform as follows. As for address trap interrupt (INTATRAP), it is requir ed to alter stacked data for program counter (PC) to restarting address, during interrupt service program. Note:If [RETN] is executed with the above data unaltered, the program returns to the address trap area and INTATRAP occurs again.When interrupt acceptance processing has completed, stacked data for PCL and PCH are located on address (SP + 1) and (SP + 2) respectively. Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next inter- rupt can be accepted immediately after the interrupt return instruction is executed. [RETI]/[RETN] Interrupt Return 1. Program counter (PC) and program status word (PSW, includes IMF) are restored from the stack. 2. Stack pointer (SP) is incremented by 3. Example 1 :Returning from address trap interrupt (INTATRAP) service program PINTxx: POP WA ; Recover SP by 2 LD WA, Return Address ; PUSH WA ; Alter stacked data (interrupt processing) RETN ; RETURN Example 2 :Restarting without returning interrupt (In this case, PSW (Includes IMF) before interrupt acceptance is discarded.) PINTxx: INC SP ; Recover SP by 3 INC SP ; INC SP ; (interrupt processing) LD EIRL, data ; Set IMF to “1” or clear it to “0” JP Restart Address ; Jump into restarting address Interrupt acceptance Interrupt service task Restoring registers Saving registers Interrupt return Saving/Restoring general-purpose registers using PUSH/POP data transfer instruction Main task

Note 1: It is recommended that stack pointer be return to rate before INTATRAP (Increment 3 times), if return inter- rupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Example 2). Note 2: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task.

3.5 Software Interrupt (INTSW)

Executing the SWI instruction generates a software interr upt and immediately starts interrupt processing (INTSW is highest prioritized interrupt). Use the SWI instruction only for detection of the address error or for debugging.

3.5.1 Address error detection

FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent memory address during single chip mode. Code FFH is th e SWI instruction, so a software interrupt is gener- ated and an address error is detect ed. The address error detection range can be further expanded by writing FFH to unused areas of the program memory. Address trap reset is generated in case that an instruction is fetched from RAM or SFR areas.

3.5.2 Debugging

Debugging efficiency can be increased by placing the SWI instruction at the software break point setting address.

3.6 Undefined Instruct ion Interrupt (INTUNDEF)

Taking code which is not defined as authorized instruction for instruction causes INTUNDEF. INTUNDEF is gen- erated when the CPU fetches such a code and tries to execute it. INTUNDEF is accepted even if non-maskable inter- rupt is in process. Contemporary process is broken and INTUNDEF interrupt process starts, soon after it is requested. Note: The undefined instruction interrupt (INTUNDEF) forces CPU to jump into vector address, as software interrupt (SWI) does.

3.7 Address Trap Interrupt (INTATRAP)

Fetching instruction from unauthorized area for instructio ns (Address trapped area) causes reset output or address trap interrupt (INTATRAP). INTATRAP is accepted even if non-maskable inte rrupt is in pro cess. Contemporary process is broken and INTATRAP interrupt process starts, soon after it is requested. Note: The operating mode under address trapped, whether to be reset output or interrupt processing, is selected on watchdog timer control register (WDTCR).

3.8 External Interrupts

The TMP86CH47AUG has 6 external interrupt inputs. These in puts are equipped with digital noise reject circuits (Pulse inputs of less than a certain time are eliminated as noise). Edge selection is also possible with INT1 to INT4. The INT0/P00 pin can be configured as either an external inter- rupt input pin or an input/output port, and is configured as an input port during reset. Edge selection, noise reject control and INT0/P00 pin function selection are performed by the external interrupt control register (EINTCR).

1. Interrupt Control Circuit

3.8 External Interrupts TMP86CH47AUG

Note 1: In NORMAL1/2 or IDLE1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "sig- nal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch. Note 2: When INT0EN = "0", IL4 is not set even if a falling edge is detected on the INT0 pin input. Note 3: When a pin with more than one function is used as an output and a change occurs in data or input/output status, an inter- rupt request signal is generated in a pseudo manner. In this case, it is necessary to perform appropriate processing such as disabling the interrupt enable flag. Source Pin Enable Conditions Release Edge (level) Digital Noise Reject INT0 INT0 IMF ΠEF4 ΠINT0EN=1 Falling edge Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 7/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are consid- ered to be signals. INT1 INT1 IMF ΠEF5 = 1 Falling edge or Rising edge Pulses of less than 15/fc or 63/fc [s] are elimi- nated as noise. Pulses of 49/fc or 193/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. INT2 INT2 IMF ΠEF8 = 1 Falling edge or Rising edge Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 25/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are consid- ered to be signals. INT3 INT3 IMF ΠEF11 = 1 Falling edge or Rising edge Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 25/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are consid- ered to be signals. INT4 INT4 IMF ΠEF14 = 1 and IL14ER=0 Falling edge, Rising edge, Falling and Rising edge or H level Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 25/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are consid- ered to be signals. INT5 INT5 IMF ΠEF15 = 1 and IL15ER=0 Falling edge Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 7/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are consid- ered to be signals.

Note 1: fc: High-frequency clock [Hz], *: Don’t care Note 2: When the system clock frequency is switched between high and low or when the external interrupt control register (EINTCR) is overwritten, the noise canceller may not operate normally. It is recommended that external interrupts are dis- abled using the interrupt enable register (EIR). Note 3: The maximum time from modifying INT1NC until a noise reject time is changed is 26/fc. Note 4: In case RESET pin is released while the state of INT4 pin keeps "H" level, the external interrupt 4 request is not generated even if the INT4 edge select is specified as "H" level. The rising edge is needed after RESET pin is released. External Interrupt Control Register E I N T C R 76543210 (0037H) INT1NC INT0EN INT4ES INT3ES INT2ES INT1ES (Initial value: 0000 000*) INT1NC Noise reject time select 0: Pulses of less than 63/fc [s] are eliminated as noise 1: Pulses of less than 15/fc [s] are eliminated as noise R/W INT0EN P00/ INT0 pin configuration 0: P00 input/output port 1: INT0 pin (Port P00 should be set to an input mode) R/W INT4 ES INT4 edge select 00: Rising edge 01: Falling edge 10: Rising edge and Falling edge 11: H level R/W INT3 ES INT3 edge select 0: Rising edge 1: Falling edge R/W INT2 ES INT2 edge select 0: Rising edge 1: Falling edge R/W INT1 ES INT1 edge select 0: Rising edge 1: Falling edge R/W

1. Interrupt Control Circuit

1. Special Function Register (SFR) The TMP86CH47AUG adopts the memory mapped I/O system , and all peripheral control and data transfers are performed through the special function register (SFR). The SFR is mapped on address 0000H to 003FH. This chapter shows the arrangement of the special function register (SFR) for TMP86CH47AUG.

4.1 SFR

1. Special Function Register (SFR)

4.1 SFR TMP86CH47AUG

Note 1: Do not access reserved areas by the program. Note 2: − ; Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). 0028H SIORDB SIOTDB 0029H Reserved 002AH Reserved 002BH Reserved 002CH Reserved 002DH Reserved 002EH Reserved 002FH Reserved 0030H Reserved 0031H - STOPCR 0032H Reserved 0033H Reserved 0034H - WDTCR1 0035H - WDTCR2 0036H TBTCR 0037H EINTCR 0038H SYSCR1 0039H SYSCR2 003AH EIRL 003BH EIRH 003CH ILL 003DH ILH 003EH INTSEL 003FH PSW Address Read Write

1. I/O Ports The TMP86CH47AUG have 5 parallel input/output ports (35 pins) as follows. Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external input data should be externally held until the input data is read from outside or reading should be performed several times before processing. Figure 5-1 shows input/output timing examples. External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction. This timing cannot be recognized from outside, so that transient input such as chattering must be processed by the pro- gram. Output data changes in the S2 state of the write cycle du ring execution of the instruct ion which writes to an I/O port. Note: The positions of the read and write c ycles may vary, depending on the instruction. Figure 5-1 Input/Output Timing (Example) Primary Function Secondary Functions Port P0 8-bit I/O port External interrupt input, serial and timer/counter input/output Port P1 8-bit I/O port External interrupt input, timer/counter input/output, and divider output Port P2 3-bit I/O port Low-frequncy resonator connections, external interrupt input, and STOP mode release signal input Port P3 8-bit I/O port Analog input, and STOP mode release signal input Port P4 8-bit I/O port /K49/K6E/K73/K74/K72/K75/K63/K74/K69/K6F/K6E /K65/K78/K65/K63/K75/K74/K69/K6F/K6E /K63/K79/K63/K6C/K65 /K49/K6E/K73/K74/K72/K75/K63/K74/K69/K6F/K6E /K65/K78/K65/K63/K75/K74/K69/K6F/K6E /K63/K79/K63/K6C/K65 /K49/K6E/K70/K75/K74 /K73/K74/K72/K6F/K62/K65 /K44/K61/K74/K61 /K69/K6E/K70/K75/K74 /K45/K78/K3A /K4C/K44 /K41/K2C /K28/K78/K29 /K46/K65/K74/K63/K68 /K63/K79/K63/K6C/K65 /K46/K65/K74/K63/K68 /K63/K79/K63/K6C/K65 /K52/K65/K61/K64 /K63/K79/K63/K6C/K65 /K53/K30/K9 /K53/K31/K9 /K53/K32/K9 /K53/K33/K9 /K53/K30/K9 /K53/K31/K9 /K53/K32/K9 /K53/K33/K9 /K53/K30/K9 /K53/K31/K9 /K53/K32/K9 /K53/K33 /K4F/K75/K74/K70/K75/K74 /K73/K74/K72/K6F/K62/K65 /K44/K61/K74/K61 /K6F/K75/K74/K70/K75/K74 /K45/K78/K3A /K4C/K44 /K28/K78/K29/K2C /K41 /K46/K65/K74/K63/K68 /K63/K79/K63/K6C/K65 /K46/K65/K74/K63/K68 /K63/K79/K63/K6C/K65 /K57/K72/K69/K74/K65 /K63/K79/K63/K6C/K65 /K53/K30/K9 /K53/K31/K9 /K53/K32/K9 /K53/K33/K9 /K53/K30/K9 /K53/K31/K9 /K53/K32/K9 /K53/K33/K9 /K53/K30/K9 /K53/K31/K9 /K53/K32/K9 /K53/K33 /K28/K61/K29 /K49/K6E/K70/K75/K74 /K74/K69/K6D/K69/K6E/K67 /K28/K62/K29 /K4F/K75/K74/K70/K75/K74 /K74/K69/K6D/K69/K6E/K67

1. I/O Ports

5.1 Port P0 (P07 to P00) TMP86CH47AUG

5.1 Port P0 (P07 to P00)

Port P0 is an 8-bit input/outpu t port which is also used as an external interrupt input, serial interface input/output and timer/counter input/output. When used as an input port or a secondary function pins, the respective output latch (P0D R) should be set to “1”. When used as an output port, the respective P0DR bit should be set data. During reset, the output latch is initialized to “1”. P0 port output latch (P0DR) and P0 port terminal input (P0PRD) are located on their respective address. When read the output latch data, the P0DR should be r ead and when read the terminal input data, the P0PRD reg- ister should be read. P00 port ( INT0) can be configured as either an I/O po rt or as external interrupt input with INT0EN (bit 6 in EINTCR). During reset, P00 port (INT0) is configured as an input port. Figure 5-2 Port P0 P0DR (0000H) R/W 76543210 P07 INT4 P06 SCK P05 SI P04 SO P03 TXD P02 RXD P01 PWM4 TC4 PDO4 PPG4 P00 INT0 (Initial value: 1111 1111) P0PRD (0008H) Read only 76543210 P07 P06 P05 P04 P03 P02 P01 P00 /K4F/K75/K74/K70/K75/K74 /K6C/K61/K74/K63/K68 /K50/K6F/K72/K74 /K64/K61/K74/K61 /K28/K50/K30/K50/K52/K44/K29 /K44/K61/K74/K61 /K6F/K75/K74/K70/K75/K74 /K43/K6F/K6E/K74/K72/K6F/K6C /K6F/K75/K74/K70/K75/K74 /K53/K54 /K4F/K50 /K4F/K55/K54/K45/K4E /K4F/K75/K74/K70/K75/K74 /K6C/K61/K74/K63/K68 /K64/K61/K74/K61 /K28/K50/K30/K44/K52/K29 /K43/K6F/K6E/K74/K72/K6F/K6C /K69/K6E/K70/K75/K74 /K50/K30/K69 /K4E/K6F/K74/K65 /K3A/K69/K3D/K37 /K74/K6F /K30 /K44/K9 /K51

5.2 Port P1 (P17 to P10)

Port P1 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit under software control. Input/output mode is specified by the corresponding bit in the port P1 input/output control register (P1CR). Port P1 is configured as an input if its corresponding P1CR bit is cleared to “0”, and as an output if its corresponding P1CR bit is set to “1”. During reset, the P1CR is initialized to “0” and port P1 is input mode. The P1 output latches are also initialized to “0”. Port P1 is also used as an external interrupt input, a timer/counter input/output, and a divider output. When used as an input port, an external interrupt input or a timer/counter input, the corresponding bit of P1CR is cleared to “0”. When used as an output port, a timer/counter output or di vider output, the corresponding bit of P1CR is set to “1” and beforehand the corresponding output latch should be set to “1”. Data can be written into the output latch regard- less of P1CR contents, therefore initial output data should be written into the output latch before setting P1CR. Figure 5-3 Port P1 Note: Ports set to the input mode read the pin states. Ports set to the output mode read the output latch. When input pin and ou t- put pin exist in port P1 together, the contents of the output latch which is specified as an input mode may be rewritten by executing the bit manipulation instructions. P1DR (0001H) R/W 76543210 P17 P16 P15 INT3 P14 PPG P13 DVO P12 INT2 TC1 P11 INT1 P10 PWM3 TC3 PDO3 (Initial value: 0000 0000) P1CR (000DH) 76543210 (Initial value: 0000 0000) P1CR I/O port for P1 port (specified for each bit) 0: Input mode 1: Output mode R/W /K4F/K75/K74/K70/K75/K74 /K6C/K61/K74/K63/K68 /K50/K31/K43/K52/K69 /K69/K6E/K70/K75/K74 /K44/K61/K74/K61 /K6F/K75/K74/K70/K75/K74 /K4F/K75/K74/K70/K75/K74 /K6C/K61/K74/K63/K68 /K50/K31/K43/K52/K69 /K43/K6F/K6E/K74/K72/K6F/K6C /K6F/K75/K74/K70/K75/K74 /K53/K54 /K4F/K50 /K4F/K55/K54/K45/K4E /K44/K61/K74/K61 /K69/K6E/K70/K75/K74 /K43/K6F/K6E/K74/K72/K6F/K6C /K69/K6E/K70/K75/K74 /K50/K31/K69 /K4E/K6F/K74/K65 /K3A/K69/K3D/K37 /K74/K6F /K30 /K44/K9 /K51 /K44/K9 /K51

1. I/O Ports

5.3 Port P2 (P22 to P20) TMP86CH47AUG

5.3 Port P2 (P22 to P20)

Port P2 is a 3-bit input/output port. It is also used as an external interrupt, a STOP mode release signal input, and low-frequency crystal oscillator con- nection pins. When used as an input port or a secondary function pins, respective output latch (P2DR) should be set to “1”. During reset, the P2DR is initialized to “1”. A low-frequency crystal osci llator (32.768 kHz) is connected to pins P21 (XTIN) and P22 (XTOUT) in the dual- clock mode. In the single-clock mode, pins P21 and P22 can be used as normal input/output ports. It is recommended that pin P20 should be used as an external interrupt input, a STOP mode release signal input, or an input port. If it is used as an output port, the interrupt latch is set on the falling edge of the output pulse. P2 port output latch (P2DR) and P2 port terminal input (P2PRD) are located on their respective address. When read the output latch data, the P2DR should be r ead and when read the terminal input data, the P2PRD reg- ister should be read. If a read instruction is executed for port P2, read data of bits 7 to 3 are unstable. Figure 5-4 Port P2 P2DR (0002H) R/W 76543210 P22 XTOUT P21 XTIN P20 INT5 STOP (Initial value: **** *111) P2PRD (000AH) Read only 76543210 P22 P21 P20 /K4F/K75/K74/K70/K75/K74 /K6C/K61/K74/K63/K68 /K4F/K75/K74/K70/K75/K74 /K6C/K61/K74/K63/K68 /K4F/K75/K74/K70/K75/K74 /K6C/K61/K74/K63/K68 /K44/K61/K74/K61 /K69/K6E/K70/K75/K74 /K28/K50/K32/K30/K50/K52/K44/K29 /K44/K61/K74/K61 /K69/K6E/K70/K75/K74 /K28/K50/K32/K31/K29 /K44/K61/K74/K61 /K6F/K75/K74/K70/K75/K74 /K44/K61/K74/K61 /K6F/K75/K74/K70/K75/K74 /K44/K61/K74/K61 /K69/K6E/K70/K75/K74 /K28/K50/K32/K30/K29 /K43/K6F/K6E/K74/K72/K6F/K6C /K69/K6E/K70/K75/K74 /K44/K61/K74/K61 /K69/K6E/K70/K75/K74 /K28/K50/K32/K31/K50/K52/K44/K29 /K44/K61/K74/K61 /K69/K6E/K70/K75/K74 /K28/K50/K32/K32/K29 /K44/K61/K74/K61 /K69/K6E/K70/K75/K74 /K28/K50/K32/K32/K50/K52/K44/K29 /K44/K61/K74/K61 /K6F/K75/K74/K70/K75/K74 /K53/K54 /K4F/K50 /K4F/K55/K54/K45/K4E /K58/K54/K45/K4E /K66/K73 /K50/K32/K32 /K28/K58/K54 /K4F/K55/K54/K29 /K50/K32/K31 /K28/K58/K54/K49/K4E/K29 /K50/K32/K30 /K28/K49/K4E/K54/K35/K2C/K53/K54 /K4F/K50/K29 /K4F/K73/K63/K2E /K65/K6E/K61/K62/K6C/K65 /K44/K9 /K51 /K44/K9 /K51 /K44/K9 /K51

5.4 Port P3 (P37 to P30)

Port P3 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit under software control. Port P3 is also used as an analog input, key on wake up input. Input/output mode is specified by the corre- sponding bit in the port P3 input/output cont rol register (P3CR), and ADCCR1<A INDS>. During reset, P3CR are initialized to “0” and ADCCR1<AINDS> is set to “1”, therefore port P3 is configured as an input. When used as an analog input, se t an analog input channel to AD CCR1<SAIN> and clear ADCCR1<AINDS> to “0”. When ADCCR1<AINDS> is “0”, the pin which is specified as an analog input is used as analog input indepen- dent on the value of P3CR and P3DR. When used as an input port or key on wake up input, the corresponding bit of P3CR is cleared to “0” without spec- ifying as an analog input. When the AD converter is enabled ( ADCCR1<AINDS> is “0”), the data of por t which is selected as an analog input is read “0”. and the data of port which is not selected as an analog input is read “0” or “1”, depend on the volt- age level. When used as an output port, the corresponding bit of P3 CR is set to “1” without specifying as an analog input. Data can be written into the output latch regardless of P3CR contents, therefore initial output data should be written into the output latch before setting P3CR. The pins not used as analog input can be used as an input/output port. But output instructions should not be exe- cuted to keep a precision. In addition, a variable signal should not be input to an adjacent port to the analog input during AD conversion. Figure 5-5 Port P3 Note: Ports set to the input mode read the pin states. Ports set to the output mode read the output latch. When input pin and ou t- put pin exist in port P3 together, the contents of the output latch which is specified as an input mode may be rewritten by executing the bit manipulation instructions. P3DR (0003H) R/W 76543210 P37 AIN7 STOP5 P36 AIN6 STOP4 P35 AIN5 STOP3 P34 AIN4 STOP2 P33 AIN3 P32 AIN2 P31 AIN1 P30 AIN0 (Initial value: 0000 0000) P3CR (000EH) 76543210 (Initial value: 0000 0000) P3CR I/O control (Specified for each bit) 0: Input mode 1: Output mode R/W Output latch Data input (P3DR) Key on wake up Analog input Data output (P3DR) STOP STOPj OUTEN AINDS SAIN P3CRi P3i Note: i = 7 to 0 j = 5 to 2 Output latch P3CRi input D Q D Q

1. I/O Ports

5.5 Port P4 (P47 to P40) TMP86CH47AUG

5.5 Port P4 (P47 to P40)

Port P4 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit under software control. Input/output mode is specified by the corresponding bit in the port P4 input/output control register (P4CR). Port P4 is configured as an input if its corresponding P4CR bit is cleared to “0”, and as an output if its corresponding P4CR bit is set to “1”. During reset, the P4CR is initialized to “0” and port P4 is input mode. The P4 output latches are also initialized to “0”. When used as an input port, the corresponding bit of P4CR is cleared to “0”. When used as an output port, the corresponding bit of P4CR is set to “1”. Data can be written into the output latch regardless of P4CR contents, therefore initial output data should be written into the output latch before setting P4CR. Figure 5-6 Port P4 Note: Ports set to the input mode read the pin states. Ports set to the output mode read the output latch. When input pin and ou t- put pin exist in port P4 together, the contents of the output latch which is specified as an input mode may be rewritten by executing the bit manipulation instructions. P4DR (0004H) R/W 76543210 P47 P46 P45 P44 P43 P42 P41 P40 (Initial value: 0000 0000) P4CR (000FH) 76543210 (Initial value: 0000 0000) P4CR I/O control for port P4 (Specified for each bit) 0: Input mode 1: Output mode R/W /K4F/K75/K74/K70/K75/K74 /K6C/K61/K74/K63/K68 /K44/K61/K74/K61 /K69/K6E/K70/K75/K74 /K28/K50/K34/K44/K52/K29 /K44/K61/K74/K61 /K6F/K75/K74/K70/K75/K74 /K53/K54 /K4F/K50 /K4F/K55/K54/K45/K4E /K50/K34/K43/K52/K69 /K50/K34/K43/K52/K69 /K69/K6E/K70/K75/K74 /K50/K34/K69 /K4E/K6F/K74/K65/K3A /K69 /K3D /K37 /K74/K6F /K30 /K44/K9 /K51 /K44/K9 /K51

1. Time Base Timer (TBT) The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base timer interrupt (INTTBT).

6.1 Time Base Timer

6.1.1 Configuration

Figure 6-1 Time Base Timer configuration

6.1.2 Control

Time Base Timer is controled by Time Base Timer control register (TBTCR). Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz], *; Don't care Time Base Timer Control Register 76543210 TBTCR (0036H) (DVOEN) (DVOCK) (DV7CK) TBTEN TBTCK (Initial Value: 0000 0000) TBTEN Time Base Timer enable / disable 0: Disable 1: Enable TBTCK Time Base Timer interrupt Frequency select : [Hz] NORMAL1/2, IDLE1/2 Mode SLOW1/2 SLEEP1/2 Mode R/W DV7CK = 0 DV7CK = 1 000 fc/2 23 fs/215 fs/215 001 fc/221 fs/213 fs/213 010 fc/216 fs/28 – 011 fc/214 fs/26 – 100 fc/213 fs/25 – 101 fc/212 fs/24 – 110 fc/211 fs/23 – 111 fc/29 fs/2 – fc/223 or fs/215 fc/221 or fs/213 fc/216 or fs/28 fc/214 or fs/26 fc/213 or fs/25 fc/212 or fs/24 fc/211 or fs/23 fc/29 or fs/2 TBTCR TBTENTBTCK MPX Source clock Falling edge detector Time base timer control register INTTBT interrupt request IDLE0, SLEEP0 release request

1. Time Base Timer (TBT)

6.1 Time Base Timer TMP86CH47AUG

Note 2: The interrupt frequency (TBTCK) must be selected with the time base timer disabled (TBTEN="0"). (The interrupt fre- quency must not be changed with the disable from the enable state.) Both frequency selection and enabling can be per- formed simultaneously.

6.1.3 Function

An INTTBT ( Time Base Timer Interrupt ) is generated on the first falling edge of source clock ( The divider output of the timing generato which is selected by TBTCK. ) after time base timer has been enabled. The divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set interrupt period ( Figure 6-2 ). Figure 6-2 Time Base Timer Interrupt Example :Set the time base timer frequency to fc/216 [Hz] and enable an INTTBT interrupt. LD (TBTCR) , 00000010B ; TBTCK ← 010 LD (TBTCR) , 00001010B ; TBTEN ← 1 DI ; IMF ← 0 SET (EIRL) . 6 Table 6-1 Time Base Timer Interrupt Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz ) TBTCK Time Base Timer Interrupt Frequency [Hz] NORMAL1/2, IDLE1/2 Mode NORMAL1/2, IDLE1/2 Mode SLOW1/2, SLEEP1/2 Mode DV7CK = 0 DV7CK = 1 000 1.91 1 1 001 7.63 4 4 010 244.14 128 – 011 976.56 512 – 100 1953.13 1024 – 101 3906.25 2048 – 110 7812.5 4096 – 111 31250 16384 – Source clock Enable TBT Interrupt period TBTCR<TBTEN> INTTBT

6.2 Divider Output ( DVO)

Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. Divider output is from DVO pin.

6.2.1 Configuration

6.2.2 Control

The Divider Output is controlled by the Time Base Timer Control Register. Note: Selection of divider output frequency (DVOCK) must be made whil e divider output is disabled (DVOEN="0"). Also, in other words, when changing the state of the divider output frequency from enabled (DVOEN="1") to disable(DVOEN="0"), do not change the setting of the divider output frequency. Time Base Timer Control Register 76 5 43 2 1 0 TBTCR (0036H) DVOEN DVOCK (DV7CK) (TBTEN) (TBTCK) (Initial value: 0000 0000) DVOEN Divider output enable / disable 0: Disable 1: Enable R/W DVOCK Divider Output ( DVO) frequency selection: [Hz] NORMAL1/2, IDLE1/2 Mode SLOW1/2 SLEEP1/2 Mode R/W DV7CK = 0 DV7CK = 1 00 fc/213 fs/25 fs/25 01 fc/212 fs/24 fs/24 10 fc/211 fs/23 fs/23 11 fc/210 fs/22 fs/22 TBTCR Output latch Port output latch MPX DVOEN TBTCR<DVOEN> DVO pin output DVOCK Divider output control register (a) configuration (b) Timing chart Data output A B C Y D S D Q DVO pin fc/213 or fs/25 fc/212 or fs/24 fc/211 or fs/23 fc/210 or fs/22

1. Time Base Timer (TBT)

6.2 Divider Output (DVO) TMP86CH47AUG

Example :1.95 kHz pulse output (fc = 16.0 MHz) LD (TBTCR) , 00000000B ; DVOCK ← "00" LD (TBTCR) , 10000000B ; DVOEN ← "1" Table 6-2 Divider Output Frequency ( Exam ple : fc = 16.0 MHz, fs = 32.768 kHz ) DVOCK Divider Output Frequency [Hz] NORMAL1/2, IDLE1/2 Mode SLOW1/2, SLEEP1/2 ModeDV7CK = 0 DV7CK = 1 00 1.953 k 1.024 k 1.024 k 01 3.906 k 2.048 k 2.048 k 10 7.813 k 4.096 k 4.096 k 11 15.625 k 8.192 k 8.192 k

1. Watchdog Timer (WDT) The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spu- rious noises or the deadlock conditions, and return the CPU to a system recovery routine. The watchdog timer signal for detecting malfunctions can be programmed only once as “reset request” or “inter- rupt request”. Upon the reset release, this signal is initialized to “reset request”. When the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic inter- rupt. Note: Care must be taken in system des ign since the watchdog timer functions are not be operated completely due to effect of disturbing noise.

7.1 Watchdog Timer Configuration

Figure 7-1 Watchdog Timer Configuration 0034H Overflow WDT output Internal reset Binary counters WDTOUTWriting clear code Writing disable code WDTEN WDTT 0035 H Watchdog timer control registers WDTCR1 WDTCR2 INTWDT interrupt request Interrupt request Reset request Reset release Clock Clear 1 2 Controller Q SR S R Q Selector fc/223 or fs/215 fc/221 or fs/213 fc/219 or fs/211 fc/217 or fs/29

1. Watchdog Timer (WDT)

7.2 Watchdog Timer Control TMP86CH47AUG

7.2 Watchdog Timer Control

The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watch- dog timer is automatically enabled after the reset release.

7.2.1 Malfunction Detection Me thods Using the Watchdog Timer

The CPU malfunction is detected, as shown below. 1. Set the detection time, select the output, and clear the binary counter. 2. Clear the binary counter repeatedly within the specified detection time. If the CPU malfunctions such as endless loops or the deadlock conditions occur for some reason, the watch- dog timer output is activated by the binary-counter overflow unless the binary counters are cleared. When WDTCR1<WDTOUT> is set to “1” at this time, the reset request is generated and the RESET pin outputs a low-level signal, then internal hardware is initia lized. When WDTCR1<WDTOUT> is set to “0”, a watchdog timer interrupt (INTWDT) is generated. The watchdog timer temporarily stops counting in th e STOP mode including the warm-up or IDLE/SLEEP mode, and automatically restarts (continues counting) when the STOP/IDLE/SLEEP mode is inactivated. Note:The watchdog timer consists of an internal divider and a two-stage binary counter. When the clear code 4EH is written, only the binary counter is cleared, but not the internal divider. The minimum binary-counter overflow time, that depends on the timing at which the clear code (4EH) is written to the WDTCR2 register, may be 3/ 4 of the time set in WDTCR1<WDTT>. Therefore, write the clear code using a cycle shorter than 3/4 of the time set to WDTCR1<WDTT>. Example :Setting the watchdog timer detection time to 221/fc [s], and resetting the CPU malfunction detection LD (WDTCR2), 4EH : Clears the binary counters. LD (WDTCR1), 00001101B : WDTT ← 10, WDTOUT ← 1 LD (WDTCR2), 4EH : Clears the binary counters (always clears immediately before and after changing WDTT). Within 3/4 of WDT detection time LD (WDTCR2), 4EH : Clears the binary counters. Within 3/4 of WDT detection time LD (WDTCR2), 4EH : Clears the binary counters.

Note 1: After clearing WDTOUT to “0”, the program cannot set it to “1”. Note 2: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care Note 3: WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions. If WDTCR1 is read, a don’t care is read. Note 4: To activate the STOP mode, disable the watchdog timer or clear the counter immediately before entering the STOP mode. After clearing the counter, clear the counter again immediately after the STOP mode is inactivated. Note 5: To clear WDTEN, set the register in accordance with the procedures shown in “1.2.3 Watchdog Timer Disable”. Note 1: The disable code is valid only when WDTCR1<WDTEN> = 0. Note 2: *: Don’t care Note 3: The binary counter of the watchdog timer must not be cleared by the interrupt task. Note 4: Write the clear code 4EH using a cycle shorter than 3/4 of the time set in WDTCR1<WDTT>.

7.2.2 Watchdog Timer Enable

Setting WDTCR1<WDTEN> to “1” enables the watc hdog timer. Since WDTCR1<WDTEN> is initialized to “1” during reset, the watchdog timer is enabled automatically after the reset release. Watchdog Timer Control Register 1 WDTCR1 (0034H) 76543210 (ATAS) (ATOUT) WDTEN WDTT WDTOUT (Initial value: **11 1001) WDTEN Watchdog timer enable/disable 0: Disable (Writing the disable code to WDTCR2 is required.) 1: Enable Write only WDTT Watchdog timer detection time [s] NORMAL1/2 mode SLOW1/2 mode Write only DV7CK = 0 DV7CK = 1 00 225/fc 2 17/fs 2 17/fs 01 223/fc 2 15/fs 2 15fs 10 221fc 2 13/fs 2 13fs 11 219/fc 2 11/fs 2 11/fs WDTOUT Watchdog timer output select 0: Interrupt request 1: Reset request Write only Watchdog Timer Control Register 2 WDTCR2 (0035H) 76543210 WDTCR2 Write Watchdog timer control code 4EH: Clear the watchdog timer binary counter (Clear code) B1H: Disable the watchdog timer (Disable code) D2H: Enable assigning address trap area Others: Invalid Write only

1. Watchdog Timer (WDT)

7.2.3 Watchdog Timer Disable

To disable the watchdog timer, set the register in accordance with the fo llowing procedures. Setting the reg- ister in other procedures causes a malfunction of the microcontroller. 1. Set the interrupt master flag (IMF) to “0”. 2. Set WDTCR2 to the clear code (4EH). 3. Set WDTCR1<WDTEN> to “0”. 4. Set WDTCR2 to the disable code (B1H). Note:While the watchdog timer is disabled, the binary counters of the watchdog timer are cleared.

7.2.4 Watchdog Time r Interrupt (INTWDT)

When WDTCR1<WDTOUT> is cleared to “0”, a watchdog timer interrupt request (INTWDT) is generated by the binary-counter overflow. A watchdog timer interrupt is the non-maskable interr upt which can be accepted regardless of the interrupt master flag (IMF). When a watchdog timer interrupt is generated while the other interrupt including a watchdog timer interrupt is already accepted, the new watchdog timer interrupt is processed immediately and the previous interrupt is held pending. Therefore, if watchdog timer interrupts are generated continuously without execution of the RETN instruction, too many levels of nesting may cause a malfunction of the microcontroller. To generate a watchdog timer interrupt, set the stack pointer before setting WDTCR1<WDTOUT>. Example :Disabling the watchdog timer DI : IMF ← 0 LD (WDTCR2), 04EH : Clears the binary coutner LDW (WDTCR1), 0B101H : WDTEN ← 0, WDTCR2 ← Disable code Table 7-1 Watchdog Timer Detection Time (Example: fc = 16.0 MHz, fs = 32.768 kHz) WDTT Watchdog Timer Detection Time[s] NORMAL1/2 mode SLOW modeDV7CK = 0 DV7CK = 1 00 2.097 4 4 01 524.288 m 1 1 10 131.072 m 250 m 250 m 11 32.768 m 62.5 m 62.5 m Example :Setting watchdog timer interrupt LD SP, 023FH : Sets the stack pointer LD (WDTCR1), 00001000B : WDTOUT ← 0

7.2.5 Watchdog Timer Reset

When a binary-counter overflow occurs while WDT CR1<WDTOUT> is set to “1”, a watchdog timer reset request is generated. When a watchdog timer reset request is generated, the RESET pin outputs a low-level sig- nal and the internal hardware is reset. The reset time is maximum 24/fc [s] (1.5 µs @ fc = 16.0 MHz). Note:When a watchdog timer reset is generated in the SL OW1 mode, the reset time is maximum 24/fc (high-fre- quency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccura- cies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors. Figure 7-2 Watchdog Timer Interrupt/Reset Clock Binary counter Overflow INTWDT interrupt request (WDTCR1<WDTOUT>= "0") 217/fc 219/fc [s] (WDTT=11) Write 4EH to WDTCR2 1 2 30 1 2 3 0 Internal reset (WDTCR1<WDTOUT>= "1") WDT reset output (High-Z) A reset occurs

1. Watchdog Timer (WDT)

7.3 Address Trap TMP86CH47AUG

7.3 Address Trap

The Watchdog Timer Control Register 1 and 2 share the a ddresses with the control regi sters to generate address traps.

7.3.1 Selection of Address Tr ap in Internal RAM (ATAS)

WDTCR1<ATAS> specifies whether or not to generate address traps in the inte rnal RAM area. To execute an instruction in the internal RA M area, clear WDTCR1<ATAS> to “0 ”. To enable the WDTCR1<ATAS> setting, set WDTCR1<ATAS> and then write D2H to WDTCR2. Executing an instruction in the SFR area generates an address trap unc onditionally regardless of the setting in WDTCR1<ATAS>.

7.3.2 Selection of Operati on at Address Trap (ATOUT)

When an address trap is generated, either the inte rrupt request or the reset request can be selected by WDTCR1<ATOUT>.

7.3.3 Address Trap Interrupt (INTATRAP)

While WDTCR1<ATOUT> is “0”, if the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on -chip RAM (while WDTCR1<ATAS> is “1”) or the SFR area, address trap interrupt (INTATRAP) will be generated. An address trap interrupt is a non-maskable interrupt which can be accepted regardless of the interrupt mas- ter flag (IMF). When an address trap interrupt is generated while th e other interrupt including a watchdog timer interrupt is already accepted, the new address trap is processed immediately and the previous interrupt is held pending. Therefore, if address trap interrupts are generated continuously without execution of the RETN instruction, too many levels of nesting may cause a malfunction of the microcontroller. To generate address trap interrupts, set the stack pointer beforehand. Watchdog Timer Control Register 1 WDTCR1 (0034H) 7654 3 21 0 ATAS ATOUT (WDTEN) (WDTT) (WDTOUT) (Initial value: **11 1001) ATAS Select address trap generation in the internal RAM area 0: Generate no address trap 1: Generate address traps (After setting ATAS to “1”, writing the control code D2H to WDTCR2 is reguired) Write only ATOUT Select opertion at address trap 0: Interrupt request 1: Reset request Watchdog Timer Control Register 2 WDTCR2 (0035H) 76543210 WDTCR2 Write Watchdog timer control code and address trap area control code D2H: Enable address trap area selection (ATRAP control code) 4EH: Clear the watchdog timer binary counter (WDT clear code) B1H: Disable the watchdog timer (WDT disable code) Others: Invalid Write only

7.3.4 Address Trap Reset

While WDTCR1<ATOUT> is “1”, if the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on -chip RAM (while WDTCR1<ATAS> is “1”) or the SFR area, address trap reset will be generated. When an address trap reset request is generated, the RESET pin outputs a low-level signal and the internal hardware is reset. The reset time is maximum 24/fc [s] (1.5 µs @ fc = 16.0 MHz). Note:When an address trap reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-fre- quency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccura- cies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors.

1. Watchdog Timer (WDT)

1. 16-Bit TimerCounter 1 (TC1)

8.1 Configuration

Figure 8-1 TimerCounter 1 (TC1) 㪧㪧㪞 pin TC1㩷㫇㫀㫅 METT1 Start Capture Clear Source clock PPG output mode Write to TC1CR 16-bit up-counter Clear TC1DRB Selector TC1DRA TC1CR TC1 control register Match INTTC1 interript TFF1 ACAP1 TC1CK Window mode Set Toggle Q Toggle Set Clear Q Y A D B CS B A Y S TC1S clear MPPG1 PPG output mode Internal reset S Enable MCAP1 S Y A B TC1S Set Clear Command startDecoder External trigger start Edge detector Note: Function I/O may not operate depending on I/O port setting. For more details, see the chapter "I/O Port". Port (Note) QPulse width measurement mode FallingRising trigger External CMP 16-bit timer register A, B Pulse width measurement mode Port (Note) fc/211, fs/23 fc/27 fc/23

1. 16-Bit TimerCounter 1 (TC1)

8.2 TimerCounter Control TMP86CH47AUG

8.2 TimerCounter Control

The TimerCounter 1 is controlled by the TimerCounter 1 control register (TC1CR) and two 16-bit timer registers (TC1DRA and TC1DRB). Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz] Note 2: The timer register consists of two shift registers. A value set in the timer register becomes valid at the rising edge of the first source clock pulse that occurs after the upper byte (TC1DRAH and TC1DRBH) is written. Therefore, write the lower byte and the upper byte in this order (it is recommended to write the register with a 16-bit access instruction). Writing only the lower byte (TC1DRAL and TC1DRBL) does not enable the setting of the timer register. Note 3: To set the mode, source clock, PPG output control and timer F/F control, write to TC1CR1 during TC1S=00. Set the timer F/F1 control until the first timer start after setting the PPG mode. Timer Register 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 TC1DRA (0011H, 0010H) TC1DRAH (0011H) TC1DRAL (0010H) (Initial value: 1111 1111 1111 1111) Read/Write TC1DRB (0013H, 0012H) TC1DRBH (0013H) TC1DRBL (0012H) (Initial value: 1111 1111 1111 1111) Read/Write (Write e nabled only in the PPG output mode) TimerCounter 1 Control Register TC1CR (0014H) 76543210 TFF1 ACAP1 MCAP1 METT1 MPPG1 TC1S TC1CK TC1M Read/Write (Initial value: 0000 0000) TFF1 Timer F/F1 control 0: Clear 1: Set R/W ACAP1 Auto capture control 0:Auto-capture disable 1:Auto-capture enable R/W MCAP1 Pulse width measure- ment mode control 0:Double edge capture 1:Single edge capture METT1 External trigger timer mode control 0:Trigger start 1:Trigger start and stop MPPG1 PPG output control 0:Continuous pulse generation 1:One-shot TC1S TC1 start control Timer Extrig- ger Event Win- dow Pulse PPG R/W 00: Stop and counter clear OOOOOO 0 1 : C o m m a n d s t a r t O––––O 10: Rising edge start (Ex-trigger/Pulse/PPG) Rising edge count (Event) Positive logic count (Window) –OOOOO 11: Falling edge start (Ex-trigger/Pulse/PPG) Falling edge count (Event) Negative logic count (Window) –OOOOO TC1CK TC1 source clock select [Hz] NORMAL1/2, IDLE1/2 mode Divider SLOW, SLEEP mode R/W DV7CK = 0 DV7CK = 1 00 fc/211 fs/23 DV9 fs/23 01 fc/27 fc/27 DV5 – 10 fc/23 fc/23 DV1 –

11 External clock (TC1 pin input)

00: Timer/external trigger timer/event counter mode 01: Window mode 10: Pulse width measurement mode 11: PPG (Programmable pulse generate) output mode R/W

Note 4: Auto-capture can be used only in the timer, event counter, and window modes. Note 5: To set the timer registers, the following relationship must be satisfied. TC1DRA > TC1DRB > 1 (PPG output mode), TC1DRA > 1 (other modes) Note 6: Set TFF1 to “0” in the mode except PPG output mode. Note 7: Set TC1DRB after setting TC1M to the PPG output mode. Note 8: When the STOP mode is entered, the start control (TC1S) is cleared to “00” automatically, and the timer stops. After the STOP mode is exited, set the TC1S to use the timer counter again. Note 9: Use the auto-capture function in the operative condition of TC1. A captured value may not be fixed if it's read after the execution of the timer stop or auto-capture disable. Read the capture value in a capture enabled condition. Note 10:Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting TC1CR<ACAP1> to "1". Therefore, to read the captured value, wait at least one cycle of the internal source clock before reading TC1DRB for the first time.

1. 16-Bit TimerCounter 1 (TC1)

8.3 Function TMP86CH47AUG

8.3 Function

TimerCounter 1 has six types of operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output modes.

8.3.1 Timer mode

In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the timer register 1A (TC1DRA) value is detected, an INTTC1 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Setting TC1CR<ACAP1> to “1” captures the up-counter value into the timer reg- ister 1B (TC1DRB) with the auto-capture function. Use the auto-capture function in the operative condition of TC1. A cap- tured value may not be fixed if it's read after the execution of the timer stop or auto-capture disable. Read the capture value in a capture enabled condition. Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting TC1CR<ACAP1> to "1". Therefore, to read the captured value, wait at least one cycle of the internal source clock before reading TC1DRB for the first time. Note: Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting TC1CR<ACAP1> to "1". Therefore, to read the captured value, wait at least one cycle of the internal source clock before reading TC1DRB for the first time. Table 8-1 Internal Source Clock for TimerCounter 1 (Example: fc = 16 MHz, fs = 32.768 kHz) TC1CK NORMAL1/2, IDLE1/2 mode SLOW, SLEEP mode DV7CK = 0 DV7CK = 1 Resolution [µs] Maximum Time Setting [s] Resolution [µs] Maximum Time Setting [s] Resolution [µs] Maximum Time Set- ting [s] 01 8.0 0.524 8.0 0.524 – – 10 0.5 32.77 m 0.5 32.77 m – – Example 1 :Setting the timer mode with source clock fc/211 [Hz] and generating an interrupt 1 second later (fc = 16 MHz, TBTCR<DV7CK> = “0”) LDW (TC1DRA), 1E84H ; Sets the timer register (1 s ÷ 211/fc = 1E84H) DI ; IMF = “0” SET (EIRL). 7 ; Enables INTTC1 EI ; IMF = “1” LD (TC1CR), 00000000B ; Selects the source clock and mode LD (TC1CR), 00010000B ; Starts TC1 Example 2 :Auto-capture LD (TC1CR), 01010000B ; ACAP1 ← 1 : : LD WA, (TC1DRB) ; Reads the capture value

Figure 8-2 Timer Mode Timing Chart Match detect ACAP1 TC1DRB TC1DRA INTTC1 interruput request Source clock Counter Source clock Counter (a) Timer mode (b) Auto-capture 763450 Timer start 12321 40 Counter clear Capture n + 1n n n m + 2m + 1m m Capture m + 2m + 1 n + 1 n m − 1 m − 1 m − 2 n − 1 n − 1 n − 1

1. 16-Bit TimerCounter 1 (TC1)

8.3.2 External Trigger Timer Mode

In the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the TC1 pin, and counts up at the edge of the internal clock. For the trigger edge used to start counting, either the rising or falling edge is defined in TC1CR<TC1S>.

• When TC1CR<METT1> is set to “1” (trigger start and stop) When a match between the up-counter and the TC1DRA value is detected after the timer starts, the up-counter is cleared and halted and an INTTC1 interrupt request is generated. If the edge opposite to trigger edge is detected before detecting a match between the up-counter and the TC1DRA, the up-counter is cleared and ha lted without generating an interrupt request. Therefore, this mode can be used to detect exceeding the specified pulse by interrupt. After being halted, the up-counter restarts counting when the trigger edge is detected.
• When TC1CR<METT1> is set to “0” (trigger start) When a match between the up-counter and the TC1DRA value is detected after the timer starts, the up-counter is cleared and halted and an INTTC1 interrupt request is generated. The edge opposite to the trigger edge has no effect in count up. The trigger edge for the next count- ing is ignored if detecting it before detecting a match between the up-counter and the TC1DRA. Since the TC1 pin input has the noise rejection, pulses of 4/fc [s] or less are rejected as noise. A pulse width of 12/fc [s] or more is required to ensure edge detectio n. The rejection circuit is turned off in the SLOW1/2 or SLEEP1/2 mode, but a pulse width of one machine cycle or more is required. Example 1 :Generating an interrupt 1 ms after the rising edge of the input pulse to the TC1 pin (fc =16 MHz) LDW (TC1DRA), 007DH ; 1ms ÷ 27/fc = 7DH DI ; IMF = “0” SET (EIRL). 7 ; Enables INTTC1 interrupt EI ; IMF = “1” LD (TC1CR), 00000100B ; Selects the source clock and mode LD (TC1CR), 00100100B ; Starts TC1 external trigger, METT1 = 0 Example 2 :Generating an interrupt when the low-level pulse with 4 ms or more width is input to the TC1 pin (fc =16 MHz) LDW (TC1DRA), 01F4H ; 4 ms ÷ 27/fc = 1F4H DI ; IMF = “0” SET (EIRL). 7 ; Enables INTTC1 interrupt EI ; IMF = “1” LD (TC1CR), 00000100B ; Selects the source clock and mode LD (TC1CR), 01110100B ; Starts TC1 external trigger, METT1 = 0

Figure 8-3 External Trigger Timer Mode Timing Chart INTTC1 interrupt request Source clock Up-counter TC1DRA TC1 pin input INTTC1 interrupt request Source clock Up-counter TC1DRA TC1 pin input At the rising edge (TC1S = 10) At the rising edge (TC1S = 10) (a) Trigger start (METT1 = 0) Count start Match detect Count start 0 1 2 3 4 2 3 n (b) Trigger start and stop (METT1 = 1) Count start Count start 0 1 2 3 m 0 n n 0 Count clear Note: m < n Count clear 1 2 3 m − 1 n − 1 Match detect Count clear

1. 16-Bit TimerCounter 1 (TC1)

8.3.3 Event Counter Mode

In the event counter mode, the up-counter counts up at the edge of the input pulse to the TC1 pin. Either the rising or falling edge of the input pulse is selected as the count up edge in TC1CR<TC1S>. When a match between the up-counter and the TC1DRA value is detected, an INTTC1 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting at each edge of the input pulse to the TC1 pin. Since a match between the up-counter and the value set to TC1DRA is detected at the edge opposite to the selected edge, an INTTC1 interrupt request is generated after a match of the value at the edge opposite to the selected edge. Two or more machine cycles are required for the low-or high-level pulse input to the TC1 pin. Setting TC1CR<ACAP1> to “1” captures the up-counter value into TC1DRB with the auto capture function. Use the auto-capture function in the operative condition of TC1. A captured value may not be fixed if it's read after the execution of the timer stop or auto-capture disable. Read the capture value in a capture enabled condi- tion. Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting TC1CR<ACAP1> to "1". Theref ore, to read the captured value, wait at least one cycle of the internal source clock before reading TC1DRB for the first time. Figure 8-4 Event Counter Mode Timing Chart Table 8-2 Input Pulse Width to TC1 Pin Minimum Pulse Width [s] NORMAL1/2, IDLE1/2 Mode SLOW1/2, SLEEP1/2 Mode High-going 23/fc 2 3/fs Low-going 23/fc 2 3/fs At the rising edge (TC1S = 10) INTTC1 interrput request TC1 pin Input Up-counter TC1DRA ? 210 n Timer start 210 n Match detect Counter clear n − 1

8.3.4 Window Mode

In the window mode, the up-counter counts up at the rising edge of the pulse that is logical ANDed product of the input pulse to the TC1 pin (window pulse) and the internal source clock. Either the positive logic (count up during high-going pulse) or negative logic (count up during low-going pulse) can be selected. When a match between the up-counter and the TC1DRA value is detected, an INTTC1 interrupt is generated and the up-counter is cleared. Define the window pulse to the frequency which is sufficiently lower than the internal source clock pro- grammed with TC1CR<TC1CK>. Figure 8-5 Window Mode Timing Chart Match detect TC1DRA INTTC1 interrput request interrput request Internal clock Counter TC1DRA TC1 pin input Internal clock Counter TC1 pin input INTTC1 (a) Positive logic (TC1S = 10) (b) Negative logic (TC1S = 11) Match detect 54631210 53 620 2 3 Counter clear Timer start 89 0 1 Timer start Counter clear Count start Count stop Count start Count start Count stop Count start

1. 16-Bit TimerCounter 1 (TC1)

8.3.5 Pulse Width Measurement Mode

In the pulse width measurement mode, the up-counter starts counting by the input pulse triggering of the TC1 pin, and counts up at the edge of the internal clock. Either the rising or falling edge of the internal clock is selected as the trigger edge in TC1CR<TC1S>. Either the single- or double-edge capture is selected as the trig- ger edge in TC1CR<MCAP1>.

• When TC1CR<MCAP1> is set to “1” (single-edge capture) Either high- or low-level input pulse width can be measured. To measure the high-level input pulse width, set the rising edge to TC1CR<TC1S>. To measure the low-level input pulse width, set the falling edge to TC1CR<TC1S>. When detecting the edge opposite to the trigger ed ge used to start countin g after the timer starts, the up-counter captures the up-counter value in to TC1DRB and generates an INTTC1 interrupt request. The up-counter is cleared at this time, a nd then restarts counting wh en detecting the trigger edge used to start counting.
• When TC1CR<MCAP1> is set to “0” (double-edge capture) The cycle starting with either the high- or low-going input pulse can be measured. To measure the cycle starting with the high-going pulse, set the rising edge to TC1CR<TC1S>. To measure the cycle starting with the low-going pulse, set the falling edge to TC1CR<TC1S>. When detecting the edge opposite to the trigger ed ge used to start countin g after the timer starts, the up-counter captures the up-counter value in to TC1DRB and generates an INTTC1 interrupt request. The up-counter continues counting up, and captures the up-counter value into TC1DRB and generates an INTTC1 interrupt request when detecting the trigger edge used to start counting. The up-counter is cleared at this time, and then continues counting. Note 1: The captured value must be read from TC1DRB until the next trigger edge is detected. If not read, the cap- tured value becomes a don’t care. It is recommended to use a 16-bit access instruction to read the captured value from TC1DRB. Note 2: For the single-edge capture, the counter after capturing the value stops at “1” until detecting the next edge. Therefore, the second captured value is “1” larger than the captured value immediately after counting starts. Note 3: The first captured value after the timer starts may be read incorrectively, therefore, ignore the first captured value.

Example :Duty measurement (resolution fc/27 [Hz]) CLR (INTTC1SW). 0 ; INTTC1 serv ice switch initial setting Address set to convert INTTC1SW at each INTTC1 LD (TC1CR), 00000110B ; Sets the TC1 mode and source clock DI ; IMF = “0” SET (EIRL). 7 ; Enables INTTC1 EI ; IMF = “1” LD (TC1CR), 00100110B ; Starts TC1 with an external trigger at MCAP1 = 0 PINTTC1: CPL (INTTC1SW). 0 ; INTTC1 interrupt, inverts and tests INTTC1 service switch JRS F, SINTTC1 LD A, (TC1DRBL) ; Reads TC1DRB (High-level pulse width) LD W,(TC1DRBH) LD (HPULSE), WA ; Stores high-level pulse width in RAM RETI SINTTC1: LD A, (TC1DRBL) ; Reads TC1DRB (Cycle) LD W,(TC1DRBH) LD (WIDTH), WA ; Stores cycle in RAM RETI ; Duty calculation VINTTC1: DW PINTTC1 ; INTTC1 Interrupt vector WIDTH HPULSE TC1 pin INTTC1 interrupt request INTTC1SW

1. 16-Bit TimerCounter 1 (TC1)

Figure 8-6 Pulse Width Measurement Mode TC1DRB INTTC1 interrupt request interrupt request TC1 pin input Counter Internal clock (MCAP1 = "1") 23n Count start Count start Trigger (TC1S = "10") 1321 40 n Capture n - 1 TC1DRB INTTC1 TC1 pin input Counter Internal clock (MCAP1 = "0") 12n Count start Count start (TC1S = "10") 321 40 n Capture Capture n + 1 m - 2n + 3n + 2n + 1 m - 1 m0 m [Application] High-or low-level pulse width measurement [Application] (1) Cycle/frequency measurement (2) Duty measurement (a) Single-edge capture (b) Double-edge capture

8.3.6 Programmable Pulse Generate (PPG) Output Mode

In the programmable pulse generation (PPG) mode, an arbitrary duty pulse is generated by counting per- formed in the internal clock. To start the timer, TC1C R<TC1S> specifies either the edge of the input pulse to the TC1 pin or the command start. TC1CR<MPPG1> specifies whether a duty pulse is produced continuously or not (one-shot pulse).

• When TC1CR<MPPG1> is set to “0” (Continuous pulse generation) When a match between the up-counter and the TC1DRB value is detected after the timer starts, the level of the PPG pin is inverted and an INTTC1 interrupt request is generated. The up-counter contin- ues counting. When a match between the up-counter and the TC1DRA value is detected, the level of the PPG pin is inverted and an INTTC1 interrupt requ est is generated. The up-counter is cleared at this time, and then continues counting and pulse generation. When TC1S is cleared to “00” during PPG output, the PPG pin retains the level immediately before the counter stops.
• When TC1CR<MPPG1> is set to “1” (One-shot pulse generation) When a match between the up-counter and the TC1DRB value is detected after the timer starts, the level of the PPG pin is inverted and an INTTC1 interrupt request is generated. The up-counter contin- ues counting. When a match between the up-counter and the TC1DRA value is detected, the level of the PPG pin is inverted and an INTTC1 interrupt re quest is generated. TC1CR<TC1S> is cleared to “00” automatically at this time, and the timer stops. The pulse generated by PPG retains the same level as that when the timer stops. Since the output level of the PPG pin can be set with TC1CR<TFF1> when the timer starts, a positive or neg- ative pulse can be generated. Since the inverted level of the timer F/F1 output level is output to the PPG pin, specify TC1CR<TFF1> to “0” to set the high level to the PPG pin, and “1” to set the low level to the PPG pin. Upon reset, the timer F/F1 is initialized to “0”. Note 1: To change TC1DRA or TC1DRB during a run of the timer, set a value sufficiently larger than the count value of the counter. Setting a value smaller than the count value of the counter during a run of the timer may generate a pulse different from that specified. Note 2: Do not change TC1CR<TFF1> during a run of the timer. TC1CR<TFF1> can be set correctly only at initial- ization (after reset). When the timer stops during PPG, TC1CR<TFF1> can not be set correctly from this point onward if the PPG output has the level which is inverted of the level when the timer starts. (Setting TC1CR<TFF1> specifies the timer F/F1 to the level inverted of the programmed value.) Therefore, the timer F/F1 needs to be initialized to ensure an arbitrary level of the PPG output. To initialize the timer F/F1, change TC1CR<TC1M> to the timer mode (it is not required to start the timer mode), and then set the PPG mode. Set TC1CR<TFF1> at this time. Note 3: In the PPG mode, the following relationship must be satisfied. TC1DRA > TC1DRB Note 4: Set TC1DRB after changing the mode of TC1M to the PPG mode.

1. 16-Bit TimerCounter 1 (TC1)

Example :Generating a pulse which is high-going for 800 µs and low-going for 200 µs (fc = 16 MHz) Setting port LD (TC1CR), 10000111B ; Sets the PPG mode, selects the source clock LDW (TC1DRA), 007DH ; Sets the cycle (1 ms ÷ 27/fc ms = 007DH) LDW (TC1DRB), 0019H ; Sets the low-level pulse width (200 µs ÷ 27/fc = 0019H) LD (TC1CR), 10010111B ; Starts the timer Example :After stopping PPG , setting the PPG pin to a high-level to restart PPG (fc = 16 MHz) Setting port LD (TC1CR), 10000111B ; Sets the PPG mode, selects the source clock LDW (TC1DRA), 007DH ; Sets the cycle (1 ms ÷ 2 7/fc µs = 007DH) LDW (TC1DRB), 0019H ; Sets the low-level pulse width (200 µs ÷ 27/fc = 0019H) LD (TC1CR), 10010111B ; Starts the timer LD (TC1CR), 10000111B ; Stops the timer LD (TC1CR), 10000100B ; Sets the timer mode LD (TC1CR), 00000111B ; Sets the PPG mode, TFF1 = 0 LD (TC1CR), 00010111B ; Starts the timer Q R D PPG pin Function output Port output enableI/O port output latch shared with PPG output Data output Toggle Set Clear Q TC1CR<TFF1> Write to TC1CR Internal reset Match to TC1DRB Match to TC1DRA TC1CR<TC1S> clear Timer F/F1 INTTC1 interrupt request

Figure 8-8 PPG Mode Timing Chart INTTC1 TC1DRA Internal clock Counter TC1DRB TC1DRA PPG pin output INTTC1 interrupt request interrupt request 12 m 0 1 2 n m 0 1 n 2n n + 1 n + 1 m (a) Continuous pulse generation (TC1S = 01) TC1DRB Trigger Count start Timer start Counter Internal clock TC1 pin input PPG pin output 0 1m n n n + 1 m (b) One-shot pulse generation (TC1S = 10) Match detect Note: m > n Note: m > n [Application] One-shot pulse output

1. 16-Bit TimerCounter 1 (TC1)

1. 8-Bit TimerCounter (TC3, TC4)

9.1 Configuration

Figure 9-1 8-Bit TimerCouter 3, 4 8-bit up-counter DecodeEN A Y B S A B Y C D E F G H S A Y B S S A Y B Toggle Q Set Clear 8-bit up-counter A B Y C D E F G H S DecodeEN Toggle Q Set Clear PWM mode PDO, PPG mode PDO mode PWM, PPG mode PWM mode PWM mode 16-bit mode 16-bit mode 16-bit mode 16-bit mode Timer, Event Counter mode Overflow Overflow Timer, Event Couter mode 16-bit mode Clear Clear fc/2 fc/2 fc/2 fc/2 fc fc/2 fc/2 fc/2 fc/2 fc PDO, PWM, PPG mode PDO, PWM mode 16-bit mode fc/211 or fs/23 fc/211 or fs/23 fs fs TC4CR TC3CR TTREG4 PWREG4 TTREG3 PWREG3 TC3 pin TC4 pin TC4S TC3S INTTC3 interrupt request INTTC4 interrupt request TFF4 TFF3 PDO 4/PWM4/ PPG4 pin PDO3/PWM3/ pin TC3CK TC4CK TC3M TC3S TFF3 TC4M TC4S TFF4 Timer F/F4 Timer F/F3

1. 8-Bit TimerCounter (TC3, TC4)

9.1 Configuration TMP86CH47AUG

9.2 TimerCounter Control

The TimerCounter 3 is controlled by the TimerCounter 3 control register (TC3CR) and two 8-bit timer registers (TTREG3, PWREG3). Note 1: Do not change the timer register (TTREG3) setting while the timer is running. Note 2: Do not change the timer register (PWREG3) setting in the operating mode except the 8-bit and 16-bit PWM modes while the timer is running. Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock[Hz] Note 2: Do not change the TC3M, TC3CK and TFF3 settings while the timer is running. Note 3: To stop the timer operation (TC3S= 1 → 0), do not change the TC3M, TC3CK and TFF3 settings. To start the timer oper- ation (TC3S= 0 → 1), TC3M, TC3CK and TFF3 can be programmed. Note 4: To use the TimerCounter in the 16-bit mode, set the operating mode by programming TC4CR<TC4M>, where TC3M must be fixed to 011. Note 5: To use the TimerCounter in the 16-bit mode, select the source clock by programming TC3CK. Set the timer start control and timer F/F control by programming TC4CR<TC4S> and TC4CR<TFF4>, respectively. Note 6: The operating clock settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 9-1 and Table 9-2. TimerCounter 3 Timer Register TTREG3 (0018H) R/W 76543210 (Initial value: 1111 1111) PWREG3 (001AH) R/W 76543210 (Initial value: 1111 1111) TimerCounter 3 Control Register TC3CR (0016H) 76543210 TFF3 TC3CK TC3S TC3M (Initial value: 0000 0000) TFF3 Time F/F3 control 0: Clear Set R/W TC3CK Operating clock selection [Hz] NORMAL1/2, IDLE1/2 mode SLOW1/2 SLEEP1/2 mode R/W DV7CK = 0 DV7CK = 1 000 fc/2 11 fs/23 fs/23 001 fc/27 fc/27 – 010 fc/25 fc/25 – 011 fc/23 fc/23 – 100 fs fs fs 101 fc/2 fc/2 – 110 fc fc fc (Note 8)

111 TC3 pin input

TC3S TC3 start control 0: Operation stop and counter clear Operation start R/W TC3M TC3M operating mode select 000: 001: 010: 011: 1**: 8-bit timer/event counter mode 8-bit programmable divider output (PDO) mode 8-bit pulse width modulation (PWM) output mode 16-bit mode (Each mode is selectable with TC4M.) Reserved R/W

Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 9- Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the high-frequency warm-up mode.

1. 8-Bit TimerCounter (TC3, TC4)

The TimerCounter 4 is controlled by the TimerCounter 4 control register (TC4CR) and two 8-bit timer registers (TTREG4 and PWREG4). Note 1: Do not change the timer register (TTREG4) setting while the timer is running. Note 2: Do not change the timer register (PWREG4) setting in the operating mode except the 8-bit and 16-bit PWM modes while the timer is running. Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock [Hz] Note 2: Do not change the TC4M, TC4CK and TFF4 settings while the timer is running. Note 3: To stop the timer operation (TC4S= 1 → 0), do not change the TC4M, TC4CK and TFF4 settings. To start the timer operation (TC4S= 0 → 1), TC4M, TC4CK and TFF4 can be programmed. Note 4: When TC4M= 1** (upper byte in the 16-bit mode), the source clock becomes the TC4 overflow signal regardless of the TC3CK setting. Note 5: To use the TimerCounter in the 16-bit mode, select the operating mode by programming TC4M, where TC3CR<TC3 M> must be set to 011. TimerCounter 4 Timer Register TTREG4 (0019H) R/W 76543210 (Initial value: 1111 1111) PWREG4 (001BH) R/W 76543210 (Initial value: 1111 1111) TimerCounter 4 Control Register TC4CR (0017H) 76543210 TFF4 TC4CK TC4S TC4M (Initial value: 0000 0000) TFF4 Timer F/F4 control 0: Clear Set R/W TC4CK Operating clock selection [Hz] NORMAL1/2, IDLE1/2 mode SLOW1/2 SLEEP1/2 mode R/W DV7CK = 0 DV7CK = 1 000 fc/2 11 fs/23 fs/23 001 fc/27 fc/27 – 010 fc/25 fc/25 – 011 fc/23 fc/23 – 100 fs fs fs 101 fc/2 fc/2 – 110 fc fc –

111 TC4 pin input

TC4S TC4 start control 0: Operation stop and counter clear Operation start R/W TC4M TC4M operating mode select 000: 001: 010: 011: 100: 101: 110: 111: 8-bit timer/event counter mode 8-bit programmable divider output (PDO) mode 8-bit pulse width modulation (PWM) output mode Reserved 16-bit timer/event counter mode Warm-up counter mode 16-bit pulse width modulation (PWM) output mode 16-bit PPG mode R/W

Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC3CR<TC3CK>. Set the timer start control and timer F/F control by programming TC4S and TFF4, respectively. Note 7: The operating clock settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 9-1 and Table 9-2. Note 8: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 9- Note 1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on lower bit (TC3CK). Note 2: Ο : Available source clock Table 9-1 Operating Mode and Selectable Source Clock (NORMAL1/2 and IDLE1/2 Modes) Operating mode fc/211 or fs/23 fc/27 fc/25 fc/23 fs fc/2 fc TC3 pin input TC4 pin input 8 - b i t e v e n t c o u n t e r ––––––– Ο Ο 8-bit PWM ΟΟΟΟΟΟΟ –– 1 6 - b i t e v e n t c o u n t e r ––––––– Ο – 16-bit PWM ΟΟΟΟΟΟΟΟ – 16-bit PPG ΟΟΟΟ ––– Ο – Table 9-2 Operating Mode an d Selectable Source Clock (SLOW1/2 and SLEEP1/2 Modes) Operating mode fc/211 or fs/23 fc/27 fc/25 fc/23 fs fc/2 fc TC3 pin input TC4 pin input 8 - b i t e v e n t c o u n t e r ––––––– ΟΟ 1 6 - b i t e v e n t c o u n t e r ––––––– Ο – Note1: Note2: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on lower bit (TC3CK). Ο : Available source clock

1. 8-Bit TimerCounter (TC3, TC4)

Note: n = 3 to 4 Table 9-3 Constraints on Register Values Being Compared Operating mode Register Value 8-bit timer/event counter 1≤ (TTREGn) ≤255 8-bit PDO 1≤ (TTREGn) ≤255 8-bit PWM 2≤ (PWREGn) ≤254 16-bit timer/event counter 1 ≤ (TTREG4, 3) ≤65535 Warm-up counter 256 ≤ (TTREG4, 3) ≤65535 16-bit PWM 2 ≤ (PWREG4, 3) ≤65534 16-bit PPG 1≤ (PWREG4, 3) < (TTREG4, 3) ≤65535 and (PWREG4, 3) + 1 < (TTREG4, 3)

9.3 Function

The TimerCounter 3 and 4 have the 8-bit timer, 8-bit ev ent counter, 8-bit programmable divider output (PDO), 8- bit pulse width modulation (PWM) output modes. The Time rCounter 3 and 4 (TC3, 4) are cascadable to form a 16- bit timer. The 16-bit timer has the operat ing modes such as the 16-bit timer, 16-bit event counter, warm-up counter, 16-bit pulse width modulation (PWM) output and 16-bit programmable pulse generation (PPG) modes. 9.3.1 8-Bit Timer Mode (TC3 and 4) In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the timer register j (TTREGj) value is detected, an INTTCj interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Note 1: In the timer mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may output pulses. Note 2: In the timer mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift register configuration in the timer mode, the new value programmed in TTREGj is in effect immediately after the programming. Therefore, if TTREGi is changed while the timer is running, an expected operation may not be obtained. Note 3: j = 3, 4 Table 9-4 Source Clock for TimerCounter 3, 4 (Internal Clock) Source Clock Resolution Repeated Cycle NORMAL1/2, IDLE1/2 mode SLOW1/2, SLEEP1/2 mode fc = 16 MHz fs = 32.768 kHz fc = 16 MHz fs = 32.768 kHz DV7CK = 0 DV7CK = 1 fc/211 [Hz] fs/2 3 [Hz] fs/2 3 [Hz] 128 µs2 4 4 . 1 4 µs 32.6 ms 62.3 ms fc/27 fc/27 –8 µs – 2.0 ms – fc/25 fc/25 –2 µs – 510 µs– fc/23 fc/23 – 500 ns – 127.5 µs– Example :Setting the timer mode with source clock fc/27 Hz and generating an interrupt 80 µs later (TimerCounter4, fc = 16.0 MHz) LD (TTREG4), 0AH : Sets the timer register (80 µs÷27/fc = 0AH). DI SET (EIRH). 1 : Enables INTTC4 interrupt. EI LD (TC4CR), 00010000B : Sets the operating cock to fc/2 7, and 8-bit timer mode. LD (TC4CR), 00011000B : Starts TC4.

1. 8-Bit TimerCounter (TC3, TC4)

Figure 9-2 8-Bit Timer Mode Timing Chart (TC4) 9.3.2 8-Bit Event Counter Mode (TC3, 4) In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj pin. When a match between the up-counter and the TTREGj value is detected, an INTTCj interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counti ng at the falling edge of the input pulse to the TCj pin. Two machine cycles are required for the low- or high-level pulse input to the TCj pin. Therefore, a maximum freque ncy to be supplied is fc/2 4 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/2 4 Hz in the SLOW1/2 or SLEEP1/2 mode. Note 1: In the event counter mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may output pulses. Note 2: In the event counter mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift register configuration in the event counter mode, the new value programmed in TTREGj is in effect immediately after the programming. Therefore, if TTREGi is changed while the timer is running, an expected operation may not be obtained. Note 3: j = 3, 4 Figure 9-3 8-Bit Event Counter Mode Timing Chart (TC4) 9.3.3 8-Bit Programmable Divi der Output (PDO) Mode (TC3, 4) This mode is used to generate a pulse with a 50% duty cycle from the PDOj pin. In the PDO mode, the up-counter counts up using the internal clock. When a match between the up-counter and the TTREGj value is detected, the logic level output from the PDOj pin is switched to the opposite state and the up-counter is cleared. The INTTCj interrupt request is generated at the time. The logic state opposite to the timer F/Fj logic level is output from the PDOj pin. An arbitrary value can be set to the timer F/Fj by TCjCR<TFFj>. Upon reset, the timer F/Fj value is initialized to 0. To use the programmable divider output, set the output latch of the I/O port to 1. 1 2 3 n-1 n 0 1 n-1 n 20 12 0 Internal Source Clock Counter Match detect Counter clear Match detect Counter clear TC4CR<TC4S> TTREG4 INTTC4 interrupt request 10 2 n-1 n 0 1 2 0 Counter Match detect Counter clear n-1 n 20 1 Match detect Counter clear TC4CR<TC4S> TTREG4 INTTC4 interrupt request TC4 pin input

Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift register configuration in the programmable divider output mode, the new value programmed in TTREGj is in effect immediately after programming. Therefore, if TTREGi is changed while the timer is running, an expected operation may not be obtained. Note 2: When the timer is stopped during PDO output, the PDOj pin holds the output status when the timer is stopped. To change the output status, program TCjCR<TFFj> after the timer is stopped. Do not change the TCjCR<TFFj> setting upon stopping of the timer. Example: Fixing the PDOj pin to the high level when the TimerCounter is stopped CLR (TCjCR).3: Stops the timer. CLR (TCjCR).7: Sets the PDOj pin to the high level. Note 3: j = 3, 4 Example :Generating 1024 Hz pulse using TC4 (fc = 16.0 MHz) Setting port LD (TTREG4), 3DH : 1/1024÷27/fc÷2 = 3DH LD (TC4CR), 00010001B : Sets the operating clock to fc/27, and 8-bit PDO mode. LD (TC4CR), 00011001B : Starts TC4.

1. 8-Bit TimerCounter (TC3, TC4)

Figure 9-4 8-Bit PDO Mode Timing Chart (TC4) 120 n 0 n 0 n 0 n 01 2 2 1 2 1 2 31 0 Internal source clock Counter Match detect Match detect Match detect Match detect Held at the level when the timer is stopped Set F/F Write of "1" TC4CR<TC4S> TC4CR<TFF4> TTREG4 Timer F/F4 PDO4 pin INTTC4 interrupt request

9.3.4 8-Bit Pulse Wi dth Modulation (PWM) Output Mode (TC3, 4) This mode is used to generate a pulse-width modulated (PWM) signals with up to 8 bits of resolution. The up-counter counts up using the internal clock. When a match between the up-counter and the PWREGj value is detected, the logic level output from the timer F/Fj is switched to the opposite state. The counter continues counting. The logic level output from the timer F/Fj is switched to the opposite state again by the up-co unter overflow, and the counter is cleared. The INTTCj interrupt request is generated at this time. Since the initial value can be set to the timer F/Fj by TCjCR<TFFj>, positive and negative pulses can be gen- erated. Upon reset, the timer F/Fj is cleared to 0. (The logic level output from the PWMj pin is the opposite to the timer F/Fj logic level.) Since PWREGj in the PWM mode is serially connected to the shift register, the value set to PWREGj can be changed while the timer is running. The value set to PWREGj during a run of the timer is shifted by the INTTCj interrupt request and loaded into PWREGj. While the timer is stopped, the value is shifted immedi- ately after the programming of PWRE Gj. If executing the read instruction to PWREGj during PWM output, the value in the shift register is read, but not the value set in PWREGj. Therefore, after writing to PWREGj, the reading data of PWREGj is previous value until INTTCj is generated. For the pin used for PWM output, the output latch of the I/O port must be set to 1. Note 1: In the PWM mode, program the timer register PWREGj immediately after the INTTCj interrupt request is generated (normally in the INTTCj interrupt service routine.) If the programming of PWREGj and the inter- rupt request occur at the same time, an unstable value is shifted, that may result in generation of the pulse different from the programmed value until the next INTTCj interrupt request is generated. Note 2: When the timer is stopped during PWM output, the PWMj pin holds the output status when the timer is stopped. To change the output status, program TCjCR<TFFj> after the timer is stopped. Do not change the TCjCR<TFFj> upon stopping of the timer. Example: Fixing the PWMj pin to the high level when the TimerCounter is stopped CLR (TCjCR).3: Stops the timer. CLR (TCjCR).7: Sets the PWMj pin to the high level. Note 3: To enter the STOP mode during PWM output, stop the timer and then enter the STOP mode. If the STOP mode is entered without stopping the timer when fc, fc/2 or fs is selected as the source clock, a pulse is out- put from the PWMj pin during the warm-up period time after exiting the STOP mode. Note 4: j = 3, 4 Table 9-5 PWM Output Mode Source Clock Resolution Repeated Cycle NORMAL1/2, IDLE1/2 mode SLOW1/2, SLEEP1/2 mode fc = 16 MHz fs = 32.768 kHz fc = 16 MHz fs = 32.768 kHz DV7CK = 0 DV7CK = 1 fc/211 [Hz] fs/2 3 [Hz] fs/2 3 [Hz] 128 µs2 4 4 . 1 4 µs 32.8 ms 62.5 ms fc/27 fc/27 –8 µs– 2 . 0 5 m s – fc/25 fc/25 –2 µs – 512 µs– fc/23 fc/2 3 – 500 ns – 128 µs– fs fs fs 30.5 µs3 0 . 5 µs 7.81 ms 7.81 ms fc/2 fc/2 – 125 ns – 32 µs– fc fc – 62.5 ns – 16 µs–

1. 8-Bit TimerCounter (TC3, TC4)

Figure 9-5 8-Bit PWM Mode Timing Chart (TC4) 10 n n+1 FF 0 n n+1 FF 0 1 m m+1 FF 0 11 p Internal source clock Counter Write to PWREG4 Write to PWREG4 m p m pn?Shift registar Shift Shift Shift Shift Match detect Match detect One cycle period Match detect Match detect n m pn TC4CR<TC4S> TC4CR<TFF4> PWREG4 Timer F/F4 PWM4 pin INTTC4 interrupt request

9.3.5 16-Bit Timer Mode (TC3 and 4) In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 3 and 4 are cascad- able to form a 16-bit timer. When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the timer is started by setting TC4CR<TC4S> to 1, an INTTC4 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter continues counting. Pr ogram the upper byte and lower byte in this order in the timer register. (Programming only the upper or lower byte should not be attempted.) Note 1: In the timer mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj, and PPGj pins may output a pulse. Note 2: In the timer mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift register configuration in the timer mode, the new value programmed in TTREGj is in effect immediately after programming of TTREGj. Therefore, if TTREGj is changed while the timer is running, an expected operation may not be obtained. Note 3: j = 3, 4 Figure 9-6 16-Bit Timer Mode Timing Chart (TC3 and TC4) Table 9-6 Source Clock for 16-Bit Timer Mode Source Clock Resolution Repeated Cycle NORMAL1/2, IDLE1/2 mode SLOW1/2, SLEEP1/2 mode fc = 16 MHz fs = 32.768 kHz fc = 16 MHz fs = 32.768 kHz DV7CK = 0 DV7CK = 1 fc/211 fs/23 fs/23 128 µs2 4 4 . 1 4 µs 8.39 s 16 s fc/27 fc/27 –8 µs – 524.3 ms – fc/25 fc/25 –2 µs – 131.1 ms – fc/23 fc/2 3 – 500 ns – 32.8 ms – Example :Setting the timer mode with source clock fc/27 Hz, and generating an interrupt 300 ms later (fc = 16.0 MHz) LDW (TTREG3), 927CH : Sets the timer register (300 ms÷27/fc = 927CH). DI SET (EIRH). 1 : Enables INTTC4 interrupt. EI LD (TC3CR), 13H :Sets the operating cock to fc/2 7, and 16-bit timer mode (lower byte). LD (TC4CR), 04H : Sets the 16-bit timer mode (upper byte). LD (TC4CR), 0CH : Starts the timer. 10 2 3 mn-1 mn 0 1 mn-1 mn 20 12 0 Internal source clock Counter Match detect Counter clear Match detect Counter clear TC4CR<TC4S> TTREG3 (Lower byte) INTTC4 interrupt request TTREG4 (Upper byte)

1. 8-Bit TimerCounter (TC3, TC4)

9.3.6 16-Bit Event C ounter Mode (TC3 and 4) 9.3.7 16-Bit Pulse Width Modulatio n (PWM) Output Mode (TC3 and 4) This mode is used to generate a pulse-width modulated (PWM) signals with up to 16 bits of resolution. The TimerCounter 3 and 4 are cascadable to form the 16-bit PWM signal generator. The counter counts up using the internal clock or external clock. When a match between the up-counter and the timer register (PWREG3, PWREG4) value is detected, the logic level output from the timer F/F4 is switched to the opposite state. The counter continues counting. The logic level output from the timer F/F4 is switched to the opposite state again by the counter overflow, and the counter is cleared. The INTTC4 interrupt is generated at this time. Two machine cycles are required for the high- or low-level pulse input to the TC3 pin. Therefore, a maxi- mum frequency to be supplied is fc/2

4 Hz in the NORMAL1 or IDLE1 mode, and fs/2 4 to in the SLOW1/2 or

SLEEP1/2 mode. Since the initial value can be set to the timer F/F4 by TC4CR<TFF4>, positive and negative pulses can be generated. Upon reset, the timer F/F4 is cleared to 0. (The logic level output from the PWM4 pin is the opposite to the timer F/F4 logic level.) Since PWREG4 and 3 in the PWM mode are serially connected to the shift register, the values set to PWREG4 and 3 can be changed while the timer is runni ng. The values set to PWREG4 and 3 during a run of the timer are shifted by the INTTCj interrupt request and loaded into PWREG4 and 3. While the timer is stopped, the values are shifted i mmediately after the programming of PWREG4 and 3. Set the lower byte (PWREG3) and upper byte (PWREG3) in this order to program PWREG4 and 3. (Programming only the lower or upper byte of the register should not be attempted.) If executing the read instruction to PWREG4 and 3 during PWM output, the values set in the shift register is read, but not the values set in PWREG4 and 3. Therefore, after writing to the PWREG4 and 3, reading data of PWREG4 and 3 is previous value until INTTC4 is generated. For the pin used for PWM output, the output latch of the I/O port must be set to 1. Note 1: In the PWM mode, program the timer register PWREG4 and 3 immediately after the INTTC4 interrupt request is generated (normally in the INTTC4 interrupt service routine.) If the programming of PWREGj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the programmed value until the next INTTC4 interrupt request is generated. Note 2: When the timer is stopped during PWM output, the PWM4 pin holds the output status when the timer is stopped. To change the output status, program TC4CR<TFF4> after the timer is stopped. Do not program TC4CR<TFF4> upon stopping of the timer. Example: Fixing thePWM4 pin to the high level when the TimerCounter is stopped In the event counter mode, the up-counter counts up at the falling edge to the TC3 pin. The TimerCounter 3 and 4 are cascadable to form a 16-bit event counter. When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the timer is started by setting TC4CR<TC4S> to 1, an INTTC4 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter rest arts counting at the falling edge of the input pulse to the TC3 pin. Two machine cycles are required for the low- or high-level pulse input to the TC3 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode, and fs/24 in the SLOW1/2 or SLEEP1/2 mode. Program the lower by te (TTREG3), and upper byte (TTREG4) in this order in the timer register. (Programming only the upper or lower byte should not be attempted.) Note 1: Note 2: Note 3: In the event counter mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may output pulses. In the event counter mode, do not change the TTREGj setti ng while the timer is running. Since TTREGj is not in the shift register configuration in the event counter mode, the new value programmed in TTREGj is in effect imme- diately after the programming. Therefore, if TTREGj is changed while the timer is running, an expected operation may not be obtained. j = 3, 4

CLR (TC4CR).3: Stops the timer. CLR (TC4CR).7 : Sets the PWM4 pin to the high level. Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered with- out stopping of the timer when fc, fc/2 or fs is selected as the source clock, a pulse is output from the PWM4 pin during the warm-up period time after exiting the STOP mode. Table 9-7 16-Bit PWM Output Mode Source Clock Resolution Repeated Cycle NORMAL1/2, IDLE1/2 mode SLOW1/2, SLEEP1/2 mode fc = 16 MHz fs = 32.768 kHz fc = 16 MHz fs = 32.768 kHz DV7CK = 0 DV7CK = 1 fc/211 fs/23 [Hz] fs/2 3 [Hz] 128 µs2 4 4 . 1 4 µs 8.39 s 16 s fc/27 fc/27 –8 µs – 524.3 ms – fc/25 fc/25 –2 µs – 131.1 ms – fc/23 fc/2 3 – 500ns – 32.8 ms – fs fs fs 30.5 µs3 0 . 5 µs2 s 2 s fc/2 fc/2 – 125 ns – 8.2 ms – fc fc – 62.5 ns – 4.1 ms – Example :Generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 MHz) Setting ports LDW (PWREG3), 07D0H : Sets the pulse width. LD (TC3CR), 33H : Sets the operating clock to fc/23, and 16-bit PWM output mode (lower byte). LD (TC4CR), 056H : Sets TFF4 to the initial value 0, and 16-bit PWM signal generation mode (upper byte). LD (TC4CR), 05EH : Starts the timer.

1. 8-Bit TimerCounter (TC3, TC4)

Figure 9-7 16-Bit PWM Mode Timing Chart (TC3 and TC4) 10 an an+1 FFFF 0 an an+1 FFFF 0 1 bm bm+1 FFFF 0 bm cp b c 11 cp n a an Internal source clock 16-bit shift register Shift Shift Shift Shift Counter Match detect Match detect One cycle period Match detect Match detect an bm cpan m p TC4CR<TC4S> TC4CR<TFF4> PWREG3 (Lower byte) Timer F/F4 PWM4 pin INTTC4 interrupt request PWREG4 (Upper byte) Write to PWREG4 Write to PWREG4 Write to PWREG3 Write to PWREG3

9.3.8 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) This mode is used to generate pulses with up to 16- bits of resolution. The timer counter 3 and 4 are cascad- able to enter the 16-bit PPG mode. The counter counts up using the inte rnal clock or external clock. When a match between the up-counter and the timer register (PWREG3, PWREG4 ) value is detected, the logic level output from the timer F/F4 is switched to the opposite state. The counter continues counting. The logic level output from the timer F/F4 is switched to the opposite state again when a match betw een the up-counter and th e timer register (TTREG3, TTREG4) value is detected, and the counter is cleared. The INTTC4 interrupt is generated at this time. Since the initial value can be set to the timer F/F4 by TC4CR<TFF4>, positive and negative pulses can be generated. Upon reset, the timer F/F4 is cleared to 0. (The logic level output from the PPG4 pin is the opposite to the timer F/F4.) Set the lower byte and upper byte in this order to program the timer register. (TTREG3 → TTREG4, PWREG3 → PWREG4) (Programming only the upper or lower byte should not be attempted.) For PPG output, set the output latch of the I/O port to 1. Note 1: In the PPG mode, do not change the PWREGi and TTREGi settings while the timer is running. Since PWREGi and TTREGi are not in the shift register configuration in the PPG mode, the new values pro- grammed in PWREGi and TTREGi are in effect immediately after programming PWREGi and TTREGi. Therefore, if PWREGi and TTREGi are changed while the timer is running, an expected operation may not be obtained. Note 2: When the timer is stopped during PPG output, the PPG4 pin holds the output status when the timer is stopped. To change the output status, program TC4CR<TFF4> after the timer is stopped. Do not change TC4CR<TFF4> upon stopping of the timer. Example: Fixing the PPG4 pin to the high level when the TimerCounter is stopped CLR (TC4CR).3: Stops the timer CLR (TC4CR).7: Sets the PPG4 pin to the high level Note 3: i = 3, 4 Two machine cycles are required for the high- or low- level pulse input to the TC3 pin. Therefore, a maxi- mum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode, and fc/24 to in the SLOW1/2 or SLEEP1/2 mode. Example :Generating a pulse with 1-ms high-level width and a period of 16.385 ms (fc = 16.0 MHz) Setting ports LDW (PWREG3), 07D0H : Sets the pulse width. LDW (TTREG3), 8002H : Sets the cycle period. LD (TC3CR), 33H : Sets the operating clock to fc/23, and16-bit PPG mode (lower byte). LD (TC4CR), 057H : Sets TFF4 to the initial value 0, and 16-bit PPG mode (upper byte). LD (TC4CR), 05FH : Starts the timer.

1. 8-Bit TimerCounter (TC3, TC4)

Figure 9-8 16-Bit PPG Mode Timing Chart (TC3 and TC40) 10 mn mn+1 qr-1 mn qr-1 1 mn mn+1mn+10qr 0qr1 0 Internal source clock Counter Write of "0" Match detect Match detect Match detect mn mnmn Match detect Match detect ? n ? r Held at the level when the timer stops F/F clear TC4CR<TC4S> TC4CR<TFF4> PWREG3 (Lower byte) Timer F/F4 PPG4 pin INTTC4 interrupt request PWREG4 (Upper byte) TTREG3 (Lower byte) TTREG4 (Upper byte)

9.3.9 Warm-Up Counter Mode

In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. The timer counter 3 and 4 are cascadable to form a 16-bit TimerCouter. The warm-up counter mode has two types of mode; switching from the high-frequency to low-frequency, and vice-versa. Note 1: In the warm-up counter mode, fix TCiCR<TFFi> to 0. If not fixed, the PDOi, PWMi and PPGi pins may output pulses. Note 2: In the warm-up counter mode, only upper 8 bits of the timer register TTREG4 and 3 are used for match detection and lower 8 bits are not used. Note 3: i = 3, 4 (NORMAL1 → NORMAL2 → SLOW2 → SLOW1) In this mode, the warm-up period time from a stop of the low-frequency clock fs to oscillation stability is obtained. Before starting the timer, set SYSCR2<XTEN> to 1 to oscillate the low-frequency clock. When a match between the up-counter and the timer register (TTREG4, 3) value is detected after the timer is started by setting TC4CR<TC4S> to 1, the counter is cleared by generating the INTTC4 interrupt request. After stopping the timer in the INTTC4 inte rrupt service routine, set SYSCR2<SYSCK> to 1 to switch the system clock from the high-frequency to low-frequency, and then clear of SYSCR2<XTEN> to 0 to stop the high-frequency clock. Table 9-8 Setting Time of Low-Frequen cy Warm-Up Counter Mode (fs = 32.768 kHz) Maximum Time Setting (TTREG4, 3 = 0100H) Maximum Time Setting (TTREG4, 3 = FF00H) 7.81 ms 1.99 s Example :After checking low-frequency clock oscillation stability with TC4 and 3, switching to the SLOW1 mode SET (SYSCR2).6 : SYSCR2<XTEN> ← 1 LD (TC3CR), 43H : Sets TFF3=0, source clock fs, and 16-bit mode. LD (TC4CR), 05H : Sets TFF4=0, and warm-up counter mode. LD (TTREG3), 8000H : Sets the warm-up time. (The warm-up time depends on the oscillator characteristic.) DI : IMF ← 0 SET (EIRH). 1 : Enables the INTTC4. EI : IMF ← 1 SET (TC4CR).3 : Starts TC4 and 3. : : PINTTC4: CLR (TC4CR).3 : Stops TC4 and 3. SET (SYSCR2).5 : SYSCR2<SYSCK> ← 1 (Switches the system clock to the low-frequency clock.) CLR (SYSCR2).7 : SYSCR2<XEN> ← 0 (Stops the high-frequency clock.) RETI : : VINTTC4: DW PINTTC4 : INTTC4 vector table

1. 8-Bit TimerCounter (TC3, TC4)

(SLOW1 → SLOW2 → NORMAL2 → NORMAL1) In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation sta- bility is obtained. Before starting the timer, set SYSCR2<XEN> to 1 to oscillate the high-frequency clock. When a match between the up-counter and the timer register (TTREG4, 3) value is detected after the timer is started by setting TC4CR<TC4S> to 1, the counter is cleared by generating the INTTC4 interrupt request. After stopping the timer in the INTTC4 interrupt service routine, clear SYSCR2<SYSCK> to 0 to switch the system clock from the low-frequency to high-frequency, and then SYSCR2<XTEN> to 0 to stop the low-frequency clock. Table 9-9 Setting Time in High-Frequency Warm-Up Counter Mode Minimum time (TTREG4, 3 = 0100H) Maximum time (TTREG4, 3 = FF00H) 16 µs 4.08 ms Example :After checking high-frequency clock oscillation stability with TC4 and 3, switching to the NORMAL1 mode SET (SYSCR2).7 : SYSCR2<XEN> ← 1 LD (TC3CR), 63H : Sets TFF3=0, source clock fs, and 16-bit mode. LD (TC4CR), 05H : Sets TFF4=0, and warm-up counter mode. LD (TTREG3), 0F800H : Sets the warm-up time. (The warm-up time depends on the oscillator characteristic.) DI : IMF ← 0 SET (EIRH). 1 : Enables the INTTC4. EI : IMF ← 1 SET (TC4CR).3 : Starts the TC4 and 3. : : PINTTC4: CLR (TC4CR).3 : Stops the TC4 and 3. CLR (SYSCR2).5 : SYSCR2<SYSCK> ← 0 (Switches the system clock to the high-frequency clock.) CLR (SYSCR2).6 : SYSCR2<XTEN> ← 0 (Stops the low-frequency clock.) RETI : : VINTTC4: DW PINTTC4 : INTTC4 vector table

1. Synchronous Serial Interface (SIO) The serial interfaces connect to an external device via SI, SO, and SCK pins. When these pins are used as serial interface, the output latches for each port should be set to "1".

10.1 Configuration

Figure 10-1 Synchronous Serial Interface (SIO) interrupt Internal clock input To BUS Shift register on transmitter Shift register on receiver (Serial data output) Control circuit Shift clock Internal data bus Port (Note) (Serial data output) Port (Note) (Serial data input) Port (Note) Note: Set the register of port correctly for the port assigned as serial interface pins. For details, see the description of the input/output port control register. MSB/LSB selection SO pin SI pin SIOTDB SIORDB SCK pin INTSIO SIOCR1 SIOSR

1. Synchronous Serial Interface (SIO)

10.2 Control TMP86CH47AUG

10.2 Control

The SIO is controlled using the serial interface control regi ster (SIOCR1). The operating status of the serial inter- face can be inspected by reading the status register (SIOCR1). Note 1: When SIOCR1<SIOINH> is set to “1”, SIOCR1<SIOS>, SIOSR register, SIORDB register and SIOTDB register are initial- ized. Note 2: Transfer mode, direction of transfer and serial clock must be select during the transfer is stopping (when SIOSR<SIOF> "0"). Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care Serial Interface Control Register SIOCR1 (0026H) 76543210 SIOS SIOINH SIOM SIODIR SCK (Initial value: 0000 0000) SIOS Specify start/stop of transfer 0: Stop 1: Start R/W SIOINH Forcibly stops transfer (Note 1) 0: – 1: Forcibly stop (Automatically cleared to "0" after stopping) SIOM Selects transfer mode 00: Transmit mode 01: Receive mode 10: Transmit/receive mode 11: Reserved SIODIR Selects direction of transfer 0: MSB (Transfer beginning with bit7) 1: LSB (Transfer beginning with bit0) SCK Selects serial clock NORMAL1/2 or IDLE1/2 modes SLOW/SLEEP modeTBTCR <DV7CK> = "0" TBTCR <DV7CK> = "1" 000 fc/2 12 fs/24 fs/24 001 fc/28 fc/28 Reserved 010 fc/27 fc/27 Reserved 011 fc/26 fc/26 Reserved 100 fc/25 fc/25 Reserved 101 fc/24 fc/24 Reserved 110 fc/23 fc/23 Reserved

111 External clock (Input from SCK pin)

Note 1: The operation error flag (TXERR and RXERR) are not automatically cleared by stopping transfer with SIOCR1<SIOS> "0". Therefore, set these bits to "0" for clearing these error flag. Or set SIOCR1<SIOINH> to "1". Note 2: *: Don't care Note 1: SIOTDB is write only register. A bit manipulation should not be performed on the transmit buffer register using a read- modify-write instruction. Note 2: The SIOTDB should be written after checking SIOSR<TXF> "1". When SIOSR<TXF> is "0", the writing data can't be transferred to SIOTDB even if write instruction is executed to SIOTDB Note 3: *: Don't care Serial Interface Status Register SIOSR (0027H) 76543210 SIOF SEF TXF RXF TXERR RXERR (Initial value: 0010 00**) SIOF Serial transfer operation status monitor 0: Transfer finished 1: Transfer in progress Read only SEF Number of clocks monitor 0: 8 clocks 1: 1 to 7 clocks TXF Transmit buffer empty flag 0: Data exists in transmit buffer 1: No data exists in transmit buffer RXF Receive buffer full flag 0: No data exists in receive buffer 1: Data exists in receive buffer TXERR Transfer operation error flag Read 0: – (No error exist) 1: Transmit buffer under run occurs in an external clock mode Write 0: Clear the flag 1: – (A write of "1" to this bit is ignored) R/W RXERR Receive operation error flag Read 0: – (No error exist) 1: Receive buffer over run occurs in an external clock mode Write 0: Clear the flag 1: – (A write of "1" to this bit is ignored) Receive buffer register SIORDB (0028H)

76543210 R e a d o n l y

(Initial value: 0000 0000) Transmit buffer register SIOTDB (0028H)

76543210 W r i t e o n l y

1. Synchronous Serial Interface (SIO)

10.3 Function TMP86CH47AUG

10.3 Function

10.3.1 Serial clock

The serial clock can be selected by using SIOCR1<SCK>. When the serial clock is changed, the writing instruction to SIOCR1<SCK> should be executed wh ile the transfer is st opped (when SIOSR<SIOF> “0”) (1) Internal clock Setting the SIOCR1<SCK> to other than “111B” outputs the clock (shown in " Table 10-1 Serial Clock Rate (fc = 16 MHz, fs = 32.768kHz) ") as serial clock outputs from SCK pin. At the before beginning or finishing of a transfer, SCK pin is kept in high level. When writing (in the transmit mode) or reading (in the receive mode) data can not follow the serial clock rate, an automatic-wait function is executed to stop the serial clock automatically and hold the next shift operation until reading or writing is completed (shown in " Figure 10-2 Automatic-wait Function (Example of transmit mode) "). The maximum time from releasing the automatic-wait function by reading or writing a data is 1 cycle of the selected serial clock until the serial clock comes out from SCK pin. Figure 10-2 Automatic-wait Function (Example of transmit mode) Table 10-1 Serial Clock Rate (fc = 16 MHz, fs = 32.768kHz) NORMAL1/2, IDLE1/2 Mode SLOW1/2, SLEEP1/2 Mode Serial Clock Baud Rate SCK Serial Clock Baud Rate Serial Clock Baud Rate 000 fc/212 3.906 kbps fs/24 2048 bps fs/24 2048 bps 001 fc/28 62.5 kbps fc/28 62.5 kbps Reserved – 010 fc/27 125 kbps fc/27 125 kbps Reserved – 011 fc/26 250 kbps fc/26 250 kbps Reserved – 100 fc/25 500 kbps fc/25 500 kbps Reserved – 101 fc/24 1.00 Mbps fc/24 1.00 Mbps Reserved – 110 fc/23 2.00 Mbps fc/23 2.00 Mbps Reserved AB Automatically wait A1 B7 B6 B5 B4 B3A2A3A4A5A6A7 B2 B1 B0 SIOCR1<SIOS> SO pin SIOTDB Automatic wait is released by writing SIOTDB SCK pin output

(2) External clock When an external clock is selected by setting SIOCR1<SCK> to “111B”, the clock via the SCK pin from an external source is used as the serial clock. To ensure shift operation, the se rial clock pulse width must be 4/fc or more for both “H” and “L” levels. Figure 10-3 External Clock The leading edge is used to transmit data, and the trailing edge is used to receive data. (1) Leading edge shift Data is shifted on the leading edge of the serial clock (falling edge of the SCK pin input/output). (2) Trailing edge shift Data is shifted on the trailing edge of the serial clock (rising edge of the SCK pin input/output). Figure 10-4 Shift Edge tSCKL tSCKH tSCKL, tSCKH > 4/fc SCK pin Bit7 Shift out Bit5Bit6 Bit5Bit6Bit7 (a) Leading edge shift (Example of MSB transfer) (b) Trailing edge shift (Example of MSB transfer) Bit4 Bit4 Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 Bit0 SIOCR1<SIOS> SCK pin Shift register SO pin Shift register SCK pin SI pin SIOCR1<SIOS>

1. Synchronous Serial Interface (SIO)

10.3.2 Transfer bit direction

Transfer data direction can be selected by using SIO CR1<SIODIR>. The transfer da ta direction can't be set individually for transmit and receive operations. When the data direction is changed, the writing inst ruction to SIOCR1<SIODIR> should be executed while the transfer is stopped (when SIOCR1<SIOF>= “0”) Figure 10-5 Transfer Bit Direction (Example of transmit mode) (1) MSB transmit mode MSB transmit mode is selected by setting SIO CR1<SIODIR> to “0”, in which case the data is transferred sequentially beginning with the most significant bit (Bit7). (2) LSB transmit mode LSB transmit mode is selected by setting SIO CR1<SIODIR> to “1”, in which case the data is transferred sequentially beginning with the least significant bit (Bit0). (1) MSB receive mode MSB receive mode is selected by setting SIOCR1<SIODIR> to “0 ”, in which case the data is received sequentially beginning with the most significant bit (Bit7). (b) LSB transfer A A1 A2 (a) MSB transfer A3 A4 A5 A6 A7 Shift out A A6 A5 A4 A3 A2 A1 A0 Shift out SIOCR1<SIOS> SCK pin SIOTDB SO pin SIOCR1<SIOS> SCK pin SIOTDB SO pin

(2) LSB receive mode LSB receive mode is selected by setting SIO CR1<SIODIR> to “1”, in which case the data is received sequentially beginning with the least significant bit (Bit0). (1) MSB transmit/receive mode MSB transmit/receive m ode are selected by setting SIOCR1<S IODIR> to “0” in which case the data is transferred sequentially beginning with the most significant bit (Bit7) and the data is received sequentially beginning with the most significant (Bit7). (2) LSB transmit/receive mode LSB transmit/receive mode are se lected by setting SIO CR1<SIODIR> to “1”, in which case the data is transferred sequentially beginning with the least significant bit (Bit0) and the data is received sequentially beginning with the least significant (Bit0).

10.3.3 Transfer modes

Transmit, receive and transmit/receive mode are selected by using SIOCR1<SIOM>. Transmit mode is selected by writing “00B” to SIOCR1<SIOM>. (1) Starting the transmit operation Transmit mode is selected by se tting “00B” to SIOCR1<SIOM>. Serial clock is selected by using SIOCR1<SCK>. Transfer direction is selected by using SIOCR1<SIODIR>. When a transmit data is written to the transmit buffer register (SIOTDB), SIOSR<TXF> is cleared to “0”. After SIOCR1<SIOS> is set to “1”, SIOSR<SIOF> is set synchronously to “1” the falling edge of SCK pin. The data is transferred sequential ly starting from SO pin with the direction of the bit specified by SIOCR1<SIODIR>, synchronizing with the SCK pin's falling edge. SIOSR<SEF> is kept in high level, be tween the first clock falling edge of SCK pin and eighth clock falling edge. SIOSR<TXF> is set to “1” at the rising edge of pin after the data written to the SIOTDB is trans- ferred to shift register, then th e INTSIO interrupt request is generated, synchronizing with the next falling edge on SCK pin. Note 1: In internal clock operation, when SIOCR1<SIOS> is set to "1", transfer mode does not start without writing a transmit data to the transmit buffer register (SIOTDB). Note 2: In internal clock operation, when the SIOCR1<SIOS> is set to "1", SIOTDB is transferred to shift register after maximum 1-cycle of serial clock frequency, then a serial clock is output from SCK pin. Note 3: In external clock operation, when the falling edge is input from SCK pin after SIOCR1<SIOS> is set to "1", SIOTDB is transferred to shift register immediately.

1. Synchronous Serial Interface (SIO)

(2) During the transmit operation When data is written to SIOTDB, SIOSR<TXF> is cleared to “0”. In internal clock operation, in cas e a next transmit data is not wr itten to SIOTDB, the serial clock stops to “H” level by an automatic-wait function when all of the bit set in the SIOTDB has been transmitted. Automatic-wait function is released by writing a transmit data to SIOTDB. Then, trans- mit operation is restarted after maximum 1-cycle of serial clock. When the next data is written to the SIOTDB before termination of previous 8-bit data with SIOSR<TXF> “1”, the next data is continuously transferred after transmission of previous data. In external clock operation, after SIOSR<TXF> is set to “1”, the transmit data must be written to SIOTDB before the shift operation of the next data begins. If the transmit data is not written to SIOTDB, tr ansmit error occurs immediately after shift opera- tion is started. Then, INTSIO interrupt request is generated after SIOSR<TXERR> is set to “1”. (3) Stopping the transmit operation There are two ways for stopping transmits operation.

• The way of clearing SIOCR1<SIOS>. When SIOCR1<SIOS> is cleared to “0”, transmit operation is stopped after all transfer of the data is finished. When transmit operation is finished, SIOSR<SIOF> is cleared to “0” and SO pin is kept in high level. In external clock operation, SIOCR1<SIOS> must be cleared to “0” before SIOSR<SEF> is set to “1” by beginning next transfer.
• The way of setting SIOCR1<SIOINH>. Transmit operation is stopped immediately after SIOCR1<SIOINH> is set to “1”. In this case, SIOCR1<SIOS>, SIOSR register, SIORDB register and SIOTDB register are initial- ized. Figure 10-6 Example of Internal Clock and MSB Transmit Mode A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 C7 A7 B0 C6 C5 C4 C3 C2 C1 C0 A B C Automatic wait Start shift operation Start shift operation Start shift operation Writing transmit data B Writing transmit data A Writing transmit data C Clearing SIOS SIOCR1<SIOS> SIOSR<SIOF> SIOSR<SEF> SCK pin outout SO pin SIOSR<TXF> SIOTDB INTSIO interrupt request

1. Synchronous Serial Interface (SIO)

Figure 10-9 Example of Transmit Error Processingme The receive mode is selected by writing “01B” to SIOCR<SIOM>. (1) Starting the receive operation Receive mode is selected by setting “01” to SI OCR1<SIOM>. Serial clock is selected by using SIOCR1<SCK>. Transfer direction is selected by using SIOCR1<SIODIR>. After SIOCR1<SIOS> is set to “1”, SIOSR<SIOF> is set synchronously to “1” the falling edge of SCK pin. Synchronizing with the SCK pin's rising edge, the data is received sequentially from SI pin with the direction of the bit specified by SBIDIR<SIODIR>. SIOSR<SEF> is kept in high level, be tween the first clock falling edge of SCK pin and eighth clock falling edge. When 8-bit data is received, the data is transfer red to SIORDB from shift register. INTSIO inter- rupt request is generated and SIOSR<RXF> is set to “1” Note: In internal clock operation, when the SIOCR1<SIO S> is set to "1", the serial clock is generated from SCK pin after maximum 1-cycle of serial clock frequency. (2) During the receive operation The SIOSR<RXF> is cleared to “0” by reading a data from SIORDB. In the internal clock operation, the serial clock stops to “H” level by an automatic-wait function when the all of the 8-bit data ha s been received. Automatic-wait fu nction is released by reading a received data from SIORDB. Then, receive operation is restarted after maximum 1-cycle of serial clock. In external clock operation, after SIOSR<RXF> is set to “1”, the received data must be read from SIORDB, before the next data shift-in operation is finished. Writing transmit data B Writing transmit data A UnknownB A7 A6 A A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 Start shift operation Start shift operation Start shift operation SIOCR1<SIOS> SIOSR<SIOF> SIOSR<SEF> SCK pin SO pin SIOSR<TXF> SIOSR<TXERR> INTSIO interrupt request SIOTDB SIOCR1 <SIOINH>

If received data is not read ou t from SIORDB receive error occu rs immediately after shift opera- tion is finished. Then INTSIO interrupt request is generated after SIOSR<RXERR> is set to “1”. (3) Stopping the receive operation There are two ways for stopping the receive operation.

• The way of clearing SIOCR1<SIOS>. When SIOCR1<SIOS> is cleared to “0”, receive operation is stopped after all of the data is finished to receive. When receive operation is finished, SIOSR<SIOF> is cleared to “0”. In external clock operation, SIOCR1<SIOS> must be cleared to “0” before SIOSR<SEF> is set to “1” by starting the next shift operation.
• The way of setting SIOCR1<SIOINH>. Receive operation is stopped immediately after SIOCR1<SIOINH> is set to “1”. In this case, SIOCR1<SIOS>, SIOSR register, SIORDB register and SIOTDB register are initialized. Figure 10-10 Example of Internal Clock and MSB Receive Mode A6 A5 A4 A3 A2 A1 A0 A7 B7 B6 B5 B4 B3 B2 B1 C7 B0 C6 C5 C4 C3 C2 C1 C0 B A C Automatic wait Start shift operation Start shift operation Start shift operation Writing transmit data A Writing transmit data B Clearing SIOS Writing transmit data C SIOCR1<SIOS> SIOSR<SIOF> SIOSR<SEF> SCK pin SI pin SIOSR<RXF> INTSIO interrupt request SIORDB

1. Synchronous Serial Interface (SIO)

Figure 10-11 Example of External Clock and MSB Receive Mode (4) Receive error processing Receive errors occur on the following situation. To protect SIORDB and the shift register contents, the received data is ignored while the SIOSR<RXERR> is “1”.

• Shift operation is finished before reading ou t received data from SIORDB at SIOSR<RXF> is “1” in an external clock operation. If receive error occurs, set the SIOCR1<SIOS> to “0” for reading the data that received immediately before error occurence. And read the data from SIORDB. Data in shift register (at errors occur) can be read by reading the SIORDB again. When SIOSR<RXERR> is cleared to “0” after reading the received data, SIOSR<RXF> is cleared to “0”. After clearing SIOCR1<SIOS> to “0”, when 8-bit serial clock is input to SCK pin, receive operation is stopped. To restart the receive operation, confirm that SIOSR<SIOF> is cleared to “0”. If the receive error occurs, set the SIOCR1<SIOINH> to “1” for stopping the receive opera- tion immediately. In this case, SIOCR1<SIOS>, SIOSR register, SIORDB register and SIOTDB register are initialized. Writing transmit data C Writing transmit data B Writing transmit data A CB A7 A6 A A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0 Start shift operation Start shift operation Start shift operation Clearing SIOSReading received data SIOCR1<SIOS> SIOSR<SIOF> SIOSR<SEF> SCK pin SI pin SIOSR<RXF> INTSIO interrupt request SIORDB

Figure 10-12 Example of Receive Error Processing Note: If receive error is not corrected, an interrupt request does not generate after the error occurs. The transmit/receive mode are selected by writing “10” to SIOCR1<SIOM>. (1) Starting the transmit/receive operation Transmit/receive mode is selected by writing “10B” to SIOCR1<SIOM>. Serial clock is selected by using SIOCR1<SCK>. Transfer direction is selected by using SIOCR1<SIODIR>. When a transmit data is written to the transmit buffer register (SIOTDB), SIOSR<TXF> is cleared to “0”. After SIOCR1<SIOS> is set to “1”, SIOSR<SIOF> is set synchronously to the falling edge of SCK pin. The data is transferred sequential ly starting from SO pin with the direction of the bit specified by SIOCR1<SIODIR>, synchronizing with the SCK pin's falling edge. And receiving operation also starts with the direction of the bit specified by SIOCR1<SIODIR>, synchronizing with the SCK pin's rising edge. SIOSR<SEF> is kept in high level between the first clock falling edge of SCK pin and eighth clock falling edge. SIOSR<TXF> is set to “1 ” at the rising edge of SCK pin after the data written to the SIOTDB is transferred to shift register. When 8-bit data has been received, the receive d data is transferred to SIORDB from shift register, then the INTSIO interrupt request occurs, synchronizing with setting SIOSR<RXF> to “1”. Note 1: In internal clock operation, when the SIOCR1<SIOS> is set to "1", SIOTDB is transferred to shift register after maximum 1-cycle of serial clock frequency, then a serial clock is output from SCK pin. Note 2: In external clock operation, when the falling edge is input from SCK pin after SIOCR1<SIOS> is set to "1", SIOTDB is transferred to shift register immediately. When the rising edge is input from SCK pin, receive operation also starts. Writing transmit data B Writing transmit data A B A7 A6 A A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0 Start shift operation Start shift operation Start shift operation Write a "0" after reading the received data when a receive error occurs. SIOCR1<SIOS> SIOSR<SEF> SCK pin SIOSR<RXERR> INTSIO interrupt request SIORDB SI pin SIOSR<SIOF> SIOSR<RXF>

1. Synchronous Serial Interface (SIO)

(2) During the transmit/receive operation When data is written to SIOTDB , SIOSR<TXF> is cleared to “0” and when a data is read from SIORDB, SIOSR<RXF> is cleared to “0”. In internal clock operation, in case of the condition described below, the serial clock stops to “H” level by an automatic-wait function when all of the bit set in the data has been transmitted.

• Next transmit data is not wr itten to SIOTDB after reading a received data from SIORDB.
• Received data is not read from SIORDB afte r writing a next transmit data to SIOTDB.
• Neither SIOTDB nor SIORDB is accessed after transmission. The automatic wait function is released by writing the next transmit data to SIOTDB after reading the received data from SIORDB, or reading the re ceived data from SIORDB after writing the next data to SIOTDB. Then, transmit/receive operation is restarted after maximum 1 cycle of serial clock. In external clock operation, reading the received data from SIORDB and writing the next data to SIOTDB must be finished before the shift operation of the next data begins. If the transmit data is not written to SIOTDB afte r SIOSR<TXF> is set to “1”, transmit error occurs immediately after shift operation is started. When the transmit error occurred, SIOSR<TXERR> is set to “1”. If received data is not read ou t from SIORDB before next shift operation starts after setting SIOSR<RXF> to “1”, receive erro r occurs immediately after shift operation is finished. When the receive error has occurred, SIOSR<RXERR> is set to “1”. (3) Stopping the transmit/receive operation There are two ways for stopping the transmit/receive operation.
• The way of clearing SIOCR1<SIOS>. When SIOCR1<SIOS> is cleared to “0”, transmit/receive operation is stopped after all trans- fer of the data is finished. When transmit/receive operation is finished, SIOSR<SIOF> is cleared to “0” and SO pin is kept in high level. In external clock operation, SIOCR1<SIOS> must be cleared to “0” before SIOSR<SEF> is set to “1” by beginning next transfer.
• The way of setting SIOCR1<SIOINH>. Transmit/receive operation is stopped immediately after SIOCR1<SIOINH> is set to “1”. In this case, SIOCR1<SIOS>, SIOSR register, SIORDB register and SIOTDB register are ini- tialized.

Figure 10-13 Example of Internal Clock and MSB Transmit/Receive Mode A6 A5 A4 A3 A2 A1 A0 A7 B7 B6 B5 B4 B3 B2 B1 C7 B0 C6 C5 C4 C3 C2 C1 C0 C A B Automatic wait Automatic wait Start shift operation Start shift operation Start shift operation Writing transmit data A Writing transmit data B D6 D5 D4 D3 D2 D1 D0 D7 E7 E6 E5 E4 E3 E2 E1 F7 E0 F6 F5 F4 F3 F2 F1 F0 Clearing SIOS Writing transmit data C E D F Reading received data D Reading received data E Reading received data F SIOCR1<SIOS> SIOSR<SIOF> SIOSR<SEF> SCK pin output SO pin SI pin INTSIO interrupt request SIOSR<TXF> SIOSR<RXF> SIORDB SIOTDB

1. Synchronous Serial Interface (SIO)

Figure 10-14 Example of External Clock and MSB Transmit/Receive Mode (4) Transmit/receive error processing Transmit/receive errors occur on the following situatio n. Corrective action is different, which errors occur transmits or receives. (a) Transmit errors Transmit errors occur on the following situation.

• Shift operation starts before writing next transmit data to SIOTDB in external clock op- eration. If transmit errors occur during transmit operation, SIOSR<TXERR> is set to “1” imme- diately after starting shift operation. And INTSIO interrupt request is generated after all of the 8-bit data has been received. If shift operation starts before writing data to SIOTDB after SIOCR1<SIOS> is set to “1”, SIOSR<TXERR> is set immediately after starting shift operation. And INTSIO in- terrupt request is generated after all of the 8-bit data has been received. SO pin is kept in high level when SIOSR<TXERR> is set to “1”. When transmit error occurs, transmit operation must be forcibly stop by writing SIOCR1<SIOINH> to “1” after the received data is read from SIORDB. In this case, SIOCR1<SIOS>, SIOSR reg- ister, SIORDB register and SIOTDB register are initialized. Writing transmit data C Writing transmit data B Writing transmit data A CB A7 A6 A A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1 E0 F7 F6 F5 F4 F3 F2 F1 F0 Start shift operation Start shift operation Start shift operation Clearing SIOS Reading received data Reading received data F Reading received data E Reading received data D FED Writing transmit data SIOCR1<SIOS> SIOSR<SIOF> SIOSR<SEF> SCK pin output SO pin SI pin INTSIO interrupt request SIOSR<TXF> SIOSR<RXF> SIORDB SIOTDB

Figure 10-15 Example of Transmit/Receive (Transmit) Error Processing (b) Receive errors Receive errors occur on the following situatio n. To protect SIORDB and the shift register contents, the received data is ignored while the SIOSR<RXERR> is “1”.

• Shift operation is finished before read ing out received data from SIORDB at SIOSR<RXF> is “1” in an external clock operation. If receive error occurs, set the SIOCR1<SIOS> to “0” for reading the data that received immediately before error occurence. And read the data from SIORDB. Data in shift reg- ister (at errors occur) can be read by reading the SIORDB again. When SIOSR<RXERR> is cleared to “0” after reading the received data, SIOSR<RXF> is cleared to “0”. After clearing SIOCR1<SIOS> to “0”, when 8-bit serial clock is input to SCK pin, re- ceive operation is stopped. To restart the receive operation, confirm that SIOSR<SIOF> is cleared to “0”. If the received error occurs, set the SIOCR1<SIOINH> to “1” for stopping the receive operation immediately. In this case, SIOCR1<SIOS>, SIOSR register, SIORDB register and SIOTDB register are initialized. Writing transmit data B Writing transmit data A UnknownB A7 A6 A A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 D7 D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1 E0 F7 F6 F5 F4 F3 F2 F1 F0 Start shift operation Start shift operation Start shift operation Reading received data F Reading received data E Reading received data D FED SIOCR1<SIOS> SIOSR<SIOF> SIOSR<SEF> SCK pin output SO pin SI pin INTSIO interrupt request SIOSR<TXF> SIOSR<RXF> SIORDB SIOTDB SIOSR<TXERR> SIOCR1<SIOINH>

1. Synchronous Serial Interface (SIO)

Figure 10-16 Example of Transmit/Receive (Receive) Error Processing Note: If receive error is not corrected, an interrupt request does not generate after the error occurs. Figure 10-17 Hold Time of the End of Transmit/Receive Mode Writing transmit data C Writing transmit data B Writing transmit data A UnknownCB A7 A6 A A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 D7 D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1 E0 F7 F6 F5 F4 F3 F2 F1 F0 Start shift operation Start shift operation Start shift operation Reading received data E Reading received data D OOHED SIOCR1<SIOS> SIOSR<SIOF> SIOSR<SEF> SCK pin output SO pin SI pin INTSIO interrupt request SIOSR<TXF> SIOSR<RXF> SIORDB SIOTDB SIOCR1<SIOINH> SIOSR<RXERR> 4/fc 8/fc tSODH tSODH< < SCK pin SIOSR<SIOF> SO pin

1. Asynchronous Serial interface (UART )

11.1 Configuration

Figure 11-1 UART (Asynchronous Serial Interface) Counter Y A B C S S A B C D Y E F G H UART status register UART control register 2 UART control register 1 Transmit data buffer Receive data buffer fc/13 fc/26 fc/52 fc/104 fc/208 fc/416 fc/96 Stop bit Parity bit fc/2 fc/2 fc/2 Baud rate generator Transmit/receive clock 3 2 Noise rejection circuit M P X Transmit control circuit Shift register Shift register Receive control circuit MPX: Multiplexer UARTCR1 TDBUF RDBUF INTTXD INTRXD UARTSR UARTCR2 RXD TXD INTTC3

1. Asynchronous Serial interface (UART )

11.2 Control TMP86CH47AUG

11.2 Control

UART is controlled by the UART Control Registers (UARTCR1, UARTCR2). The operating status can be moni- tored using the UART status register (UARTSR). Note 1: When operations are disabled by setting TXE and RXE bit to “0”, the setting becomes valid when data transmit or receive complete. When the transmit data is stored in the transmit data buffer, the data are not transmitted. Even if data transmit is enabled, until new data are written to the transmit data buffer, the current data are not transmitted. Note 2: The transmit clock and the parity are common to transmit and receive. Note 3: UARTCR1<RXE> and UARTCR1<TXE> should be set to “0” before UARTCR1<BRG> is changed. Note: When UARTCR2<RXDNC> = “01”, pulses longer than 96/fc [s] are always regarded as signals; when UARTCR2<RXDNC> = “10”, longer than 192/fc [s]; and when UARTCR2<RXDNC> = “11”, longer than 384/fc [s]. UART Control Register1 UARTCR1 (0020H) 76543210 TXE RXE STBT EVEN PE BRG (Initial value: 0000 0000) TXE Transfer operation 0: Disable Enable Write only RXE Receive operation 0: Disable Enable STBT Transmit stop bit length 0: 1 bit 2 bits EVEN Even-numbered parity 0: Odd-numbered parity Even-numbered parity PE Parity addition 0: No parity Parity BRG Transmit clock select 000: 001: 010: 011: 100: 101: 110: 111: fc/13 [Hz] fc/26 fc/52 fc/104 fc/208 fc/416 TC3 ( Input INTTC3) fc/96 UART Control Register2 UARTCR2 (0021H) 7654321 0 RXDNC STOPBR (Initial value: **** *000) RXDNC Selection of RXD input noise rejectio time 00: 01: 10: 11: No noise rejection (Hysteresis input) Rejects pulses shorter than 31/fc [s] as noise Rejects pulses shorter than 63/fc [s] as noise Rejects pulses shorter than 127/fc [s] as noise Write only STOPBR Receive stop bit length 0: 1 bit 2 bits

Note: When an INTTXD is generated, TBEP flag is set to "1" automatically. UART Status Register UARTSR (0020H) 76543210 PERR FERR OERR RBFL TEND TBEP (Initial value: 0000 11**) PERR Parity error flag 0: No parity error Parity error Read only FERR Framing error flag 0: No framing error Framing error OERR Overrun error flag 0: No overrun error Overrun error RBFL Receive data buffer full flag 0: Receive data buffer empty Receive data buffer full TEND Transmit end flag 0: On transmitting Transmit end TBEP Transmit data buffer empty flag 0: Transmit data buffer full (Transmit data writing is finished) Transmit data buffer empty UART Receive Data Buffer RDBUF (0022H) (Initial value: 0000 0000) UART Transmit Data Buffer TDBUF (0022H) (Initial value: 0000 0000)

1. Asynchronous Serial interface (UART )

11.3 Transfer Data Format TMP86CH47AUG

11.3 Transfer Data Format

In UART, an one-bit start bit (Low level), stop bit (B it length selectable at high level, by UARTCR1<STBT>), and parity (Select parity in UARTCR1<PE>; even- or odd-numbered parity by UARTCR1<EVEN>) are added to the transfer data. The transfer data formats are shown as follows. Figure 11-2 Transfer Data Format Figure 11-3 Caution on Changing Transfer Data Format Note: In order to switch the transfer data format, perform transmit operations in the above Figure 11-3 sequence except for the initial setting. Start Bit 0 Bit 1 Bit 6 Bit 7 Stop 1 Start Bit 0 Bit 1 Bit 6 Bit 7 Stop 1 Stop 2 Start Bit 0 Bit 1 Bit 6 Bit 7 Parity Stop 1 Start Bit 0 Bit 1 Bit 6 Bit 7 Parity Stop 1 Stop 2 PE STBT Frame Length 123 89 1 0 1 1 1 2 Without parity / 1 STOP bit With parity / 1 STOP bit Without parity / 2 STOP bit With parity / 2 STOP bit

11.4 Transfer Rate

The baud rate of UART is set of UARTCR1<BRG>. The example of the baud rate are shown as follows. When TC3 is used as the UART transfer rate (when UARTCR1<BRG> = “110”), the transfer clock and transfer rate are determined as follows: Transfer clock [Hz] = TC3 source clock [Hz] / TTREG3 setting value Transfer Rate [baud] = Transfer clock [Hz] / 16

11.5 Data Sampling Method

The UART receiver keeps sampling input using the cloc k selected by UARTCR1<BRG> until a start bit is detected in RXD pin input. RT clock starts detecting “L” level of the RXD pin. Once a start bit is detected, the start bit, data bits, stop bi t(s), and parity bit are sampled at three times of RT7, RT8, and RT9 during one receiver clock interval (RT clock). (RT0 is the position where the bit supposedly starts.) Bit is determined according to majority rule (The data are the same twice or more out of three samplings). Figure 11-4 Data Sampling Method Table 11-1 Transfer Rate (Example) BRG Source Clock

16 MHz 8 MHz 4 MHz

000 76800 [baud] 38400 [baud] 19200 [baud] 001 38400 19200 9600 010 19200 9600 4800 011 9600 4800 2400 100 4800 2400 1200 101 2400 1200 600 RT0 1 2 3 4 5 6 7 8 910 11 1213 1415 0 1 2 3 4 5 6 7 8 9 1 0 1 1 Bit 0Start bit Bit 0Start bit (a) Without noise rejection circuit RT clock Internal receive data RT0 1 2 3 4 5 6 7 8 910 11 1213 1415 0 1 2 3 4 5 6 7 8 9 1 0 1 1 Bit 0Start bit Bit 0Start bit RT clock Internal receive data (b) With noise rejection circuit RXD pin RXD pin

1. Asynchronous Serial interface (UART )

11.6 STOP Bit Length TMP86CH47AUG

11.6 STOP Bit Length

Select a transmit stop bit length (1 bit or 2 bits) by UARTCR1<STBT>.

11.7 Parity

Set parity / no parity by UARTCR1<PE> and set parity type (Odd- or Even-numbered) by UARTCR1<EVEN>.

11.8 Transmit/Receive Operation

11.8.1 Data Transmit Operation

Set UARTCR1<TXE> to “1”. Read UARTSR to check UARTSR<TBEP> = “1”, then write data in TDBUF (Transmit data buffer). Writing data in TDBUF zero- clears UARTSR<TBEP>, transfers the data to the trans- mit shift register and the data are sequentially output from the TXD pin. The data output include a one-bit start bit, stop bits whose number is specified in UARTCR1<STBT> and a parity bit if pari ty addition is specified. Select the data transfer baud rate using UARTCR1<BRG >. When data transmit st arts, transmit buffer empty flag UARTSR<TBEP> is set to “1” and an INTTXD interrupt is generated. While UARTCR1<TXE> = “0” and from when “1” is written to UARTCR1<TXE> to when send data are written to TDBUF, the TXD pin is fixed at high level. When transmitting data, first read UARTSR, then write data in TDBUF. Otherwise, UARTSR<TBEP> is not zero-cleared and transmit does not start.

11.8.2 Data Receive Operation

Set UARTCR1<RXE> to “1”. When data are received vi a the RXD pin, the receive data are transferred to RDBUF (Receive data buffer). At this time, the data transmitted includes a start bit and stop bit(s) and a parity bit if parity addition is specified. When stop bit(s) are received, data only are extracted and transferred to RDBUF (Receive data buffer). Then the receive buffer full flag UA RTSR<RBFL> is set and an INTRXD interrupt is generated. Select the data transfer baud rate using UARTCR1<BRG>. If an overrun error (OERR) occurs when data are received, the da ta are not transferred to RDBUF (Receive data buffer) but discarded; data in the RDBUF are not affected. Note:When a receive operation is disabled by setting UA RTCR1<RXE> bit to “0”, the setting becomes valid when data receive is completed. However, if a framing error occurs in data receive, the receive-disabling setting may not become valid. If a framing error occurs, be sure to perform a re-receive operation.

11.9 Status Flag

11.9.1 Parity Error

When parity determined using the receive data bits diff ers from the received parity bit, the parity error flag UARTSR<PERR> is set to “1”. The UARTSR<PERR> is cleared to “0” when the RDBUF is read after read- ing the UARTSR. Figure 11-5 Generation of Parity Error

11.9.2 Framing Error

When “0” is sampled as the stop bit in the receive data, framing error flag UARTSR<FERR> is set to “1”. The UARTSR<FERR> is cleared to “0” when the RDBUF is read after reading the UARTSR. Figure 11-6 Generation of Framing Error

11.9.3 Overrun Error

When all bits in the next data are received while unread data are still in RDBUF, overrun error flag UARTSR<OERR> is set to “1”. In this case, the receive data is discarded; data in RDBUF are not affected. The UARTSR<OERR> is cleared to “0” when the RDBUF is read after reading the UARTSR. Parity Stop Shift register pxxxx0* 1pxxxx0xxxx0** RXD pin UARTSR<PERR> INTRXD interrupt After reading UARTSR then RDBUF clears PERR. Final bit Stop Shift register xxxx0* 0xxxx0xxx0** RXD pin UARTSR<FERR> INTRXD interrupt After reading UARTSR then RDBUF clears FERR.

1. Asynchronous Serial interface (UART )

11.9 Status Flag TMP86CH47AUG

Figure 11-7 Generation of Overrun Error Note:Receive operations are disabled until the overrun error flag UARTSR<OERR> is cleared.

11.9.4 Receive Data Buffer Full

Loading the received data in RDBUF sets receive data buffer full flag UARTSR<RBFL> to "1". The UARTSR<RBFL> is cleared to “0” when the RDBUF is read after reading the UARTSR. Figure 11-8 Generation of Receive Data Buffer Full Note:If the overrun error flag UARTSR<OERR> is set during the period between reading the UARTSR and reading the RDBUF, it cannot be cleared by only reading the RDBUF. Therefore, after reading the RDBUF, read the UARTSR again to check whether or not the overrun error flag which should have been cleared still remains set.

11.9.5 Transmit Data Buffer Empty

When no data is in the transmit buffer TDBUF, UARTSR<TBEP> is set to “1”, that is, when data in TDBUF are transferred to the transmit shif t register and data transmit star ts, transmit data buffer empty flag UARTSR<TBEP> is set to “1”. The UARTSR<TBEP> is cleared to “0” when the TDBUF is written after reading the UARTSR. Final bit Stop Shift register xxxx0* 1xxxx0 yyyy xxx0** RXD pin UARTSR<OERR> INTRXD interrupt After reading UARTSR then RDBUF clears OERR. RDBUF UARTSR<RBFL> Final bit Stop Shift register xxxx0* 1xxxx0 xxxxyyyy xxx0** RXD pin UARTSR<RBFL> INTRXD interrupt RDBUF After reading UARTSR then RDBUF clears RBFL.

Figure 11-9 Generation of Transmit Data Buffer Empty

11.9.6 Transmit End Flag

When data are transmitted and no data is in TDBUF (UARTSR<TBEP> = “1”), transmit end flag UARTSR<TEND> is set to “1”. The UARTSR<TEND> is cleared to “0” when the data transmit is stated after writing the TDBUF. Figure 11-10 Generation of Transmit End Flag and Transmit Data Buffer Empty Shift register Data write Data write zzzzxxxx yyyy Start Bit 0 Final bit Stop TDBUF TXD pin UARTSR<TBEP> INTTXD interrupt After reading UARTSR writing TDBUF clears TBEP. Stop Start 1yyyy0 Bit 0TXD pin UARTSR<TBEP> UARTSR<TEND> INTTXD interrupt Data write for TDBUF

1. Asynchronous Serial interface (UART )

1. 10-bit AD Converter (ADC) The TMP86CH47AUG have a 10-bit successive approximation type AD converter.

12.1 Configuration

The circuit configuration of the 10-bit AD converter is shown in Figure 12-1. It consists of control register ADCCR1 and ADCCR2 , converted value register ADCDR1 and ADCDR2, a DA converter, a sample-hold circuit, a comparator, and a successive comparison circuit. Note: Before using AD converter, set appropriate value to I/O port register conbining a analog input port. For details, see the sec- tion on "I/O ports". Figure 12-1 10-bit AD Converter 8AINDS ADRS R/2 R/2R ACKAMD IREFON AD conversion result register 1, 2AD converter control register 1, 2 ADBFEOCF INTADC SAIN n Successive approximate circuit ADCCR2 ADCDR1 ADCDR2ADCCR1 Sample hold circuit A S EN Shift clock DA converter Analog input multiplexer Y Reference voltage Analog comparator Control circuit AVSSVAREF AVDD AIN0 AIN7

1. 10-bit AD Converter (ADC)

12.2 Register configuration TMP86CH47AUG

12.2 Register configuration

The AD converter consists of the following four registers: 1. AD converter control register 1 (ADCCR1) This register selects the analog channels and operatio n mode (Software start or repeat) in which to per- form AD conversion and controls the AD converter as it starts operating. 2. AD converter control register 2 (ADCCR2) This register selects the AD conversion time and co ntrols the connection of the DA converter (Ladder resistor network). 3. AD converted value register 1 (ADCDR1) This register used to store the digital value fter being converted by the AD converter. 4. AD converted value register 2 (ADCDR2) This register monitors the operating status of the AD converter. Note 1: Select analog input channel during AD converter stops (ADCDR2<ADBF> = "0"). Note 2: When the analog input channel is all use disabling, the ADCCR1<AINDS> should be set to "1". Note 3: During conversion, Do not perform port output instruction to maintain a precision for all of the pins because analog input port use as general input port. And for port near to analog input, Do not input intense signaling of change. Note 4: The ADCCR1<ADRS> is automatically cleared to "0" after starting conversion. Note 5: Do not set ADCCR1<ADRS> newly again during AD conversion. Before setting ADCCR1<ADRS> newly again, check ADCDR2<EOCF> to see that the conversion is completed or wait until the interrupt signal (INTADC) is generated (e.g., interrupt handling routine). Note 6: After STOP or SLOW/SLEEP mode are started, AD converter control register1 (ADCCR1) is all initialized and no data can be written in this register. Therfore, to use AD converter again, set the ADCCR1 newly after returning to NORMAL1 or NORMAL2 mode. AD Converter Control Register 1 ADCCR1 (001CH) 76543210 ADRS AMD AINDS SAIN (Initial value: 0001 0000) ADRS AD conversion start 0: AD conversion start R/W AMD AD operating mode 00: 01: 10: 11: AD operation disable Software start mode Reserved Repeat mode AINDS Analog input control 0: Analog input enable Analog input disable SAIN Analog input channel select 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

Note 1: Always set bit0 in ADCCR2 to "0" and set bit4 in ADCCR2 to "1". Note 2: When a read instruction for ADCCR2, bit6 to 7 in ADCCR2 read in as undefined data. Note 3: After STOP or SLOW/SLEEP mode are started, AD converter control register2 (ADCCR2) is all initialized and no data can be written in this register. Therfore, to use AD converter again, set the ADCCR2 newly after returning to NORMAL1 or NORMAL2 mode. Note 1: Setting for "−" in the above table are inhibited. fc: High Frequency oscillation clock [Hz] Note 2: Set conversion time setting should be kept more than the following time by Analog reference voltage (VAREF) . AD Converter Control Register 2 ADCCR2 (001DH) 76543210 IREFON "1" ACK "0" (Initial value: **0* 000*) IREFON DA converter (Ladder resistor) connection control Connected only during AD conversion Always connected R/W ACK AD conversion time select (Refer to the following table about the con- version time) 000: 001: 010: 011: 100: 101: 110: 111: 39/fc Reserved 78/fc 156/fc 312/fc 624/fc 1248/fc Reserved Table 12-1 ACK setting and Conversion time Condition Conversion time 16 MHz 8 MHz 4 MHz 2 MHz 10 MHz 5 MHz 2.5 MHz ACK 000 39/fc - - - 19.5 µs - - 15.6 µs

001 Reserved

010 78/fc - - 19.5 µs 39.0 µs - 15.6 µs 31.2 µs 110 1248/fc 78.0 µs 156.0 µs - - 124.8 µs- -

111 Reserved

• VAREF = 4.5 to 5.5 V 15.6 µs and more - VAREF = 2.7 to 5.5 V 31.2 µs and more - VAREF = 1.8 to 5.5 V 124.8 µs and more AD Converted value Register 1 ADCDR1 (001FH) 76543210 AD09 AD08 AD07 AD06 AD05 AD04 AD03 AD02 (Initial value: 0000 0000) AD Converted value Register 2 ADCDR2 (001EH) 76543210 AD01 AD00 EOCF ADBF (Initial value: 0000 ****)

1. 10-bit AD Converter (ADC)

Note 1: The ADCDR2<EOCF> is cleared to "0" when reading the ADCDR1. Therfore, the AD conversion result should be read to ADCDR2 more first than ADCDR1. Note 2: The ADCDR2<ADBF> is set to "1" when AD conversion starts, and cleared to "0" when AD conversion finished. It also is cleared upon entering STOP mode or SLOW mode . Note 3: If a read instruction is executed for ADCDR2, read data of bit3 to bit0 are unstable. EOCF AD conversion end flag 0: Before or during conversion Conversion completed Read only ADBF AD conversion BUSY flag 0: During stop of AD conversion During AD conversion

12.3 Function

12.3.1 Software Start Mode

After setting ADCCR1<AMD> to “01” (software start mode), set ADCCR1<ADRS> to “1”. AD conver- sion of the voltage at the analog input pin specified by ADCCR1<SAIN> is thereby started. After completion of the AD conversion, the conversion result is stored in AD converted value registers (ADCDR1, ADCDR2) and at the same time ADCDR2<EOCF> is set to 1, the AD conversion finished inter- rupt (INTADC) is generated. ADRS is automatically cleared after AD conversion has started. Do not set ADCCR1<ADRS> newly again (Restart) during AD conversion. Before setting ADRS newly again, check ADCDR2 <EOCF> to see that the conversion is completed or wait until the interrupt signa l (INTADC) is generated (e.g., interrupt handling rou- tine). Figure 12-2 Software Start Mode

12.3.2 Repeat Mode

AD conversion of the voltage at the analog input pin specified by ADCCR1<SAIN> is performed repeat- edly. In this mode, AD conversion is star ted by setting ADCCR1<ADRS> to “1” after setting ADCCR1<AMD> to “11” (Repeat mode). After completion of the AD conversion, the conversion result is stored in AD converted value registers (ADCDR1, ADCDR2) and at the same time ADCDR2<EOCF> is set to 1, the AD conversion finished inter- rupt (INTADC) is generated. In repeat mode, each time one AD conversion is complete d, the next AD conversion is started. To stop AD conversion, set ADCCR1<AMD> to “00” (Disable mode) by writing 0s. The AD convert operation is stopped immediately. The converted value at this time is not stored in the AD converted value register. ADCDR1 status EOCF cleared by reading conversion result Conversion result read ADCDR2<EOCF> INTADC interrupt request ADCDR2<ADBF> ADCCR1<ADRS> 1st conversion result 2nd conversion resultIndeterminate AD conversion start AD conversion start ADCDR1 ADCDR2 Conversion result read Conversion result read Conversion result read

1. 10-bit AD Converter (ADC)

12.3 Function TMP86CH47AUG

12.3.3 Regi ster Setting

1. Set up the AD converter control register 1 (ADCCR1) as follows:

• Choose the channel to AD convert using AD input channel select (SAIN).
• Specify analog input enable fo r analog input control (AINDS).
• Specify AMD for the AD converter control operation mode (software or repeat mode). 2. Set up the AD converter control register 2 (ADCCR2) as follows:
• Set the AD conversion time using AD conversion time (ACK). For details on how to set the con- version time, refer to Figure 12-1 and AD converter control register 2.
• Choose IREFON for DA converter control. 3. After setting up (1) and (2) above, set AD conversion start (ADRS) of AD converter control register 1 (ADCCR1) to “1”. If software start mode has been selected, AD conversion starts immediately. 4. After an elapse of the specified AD conversion time, the AD converted value is stored in AD con- verted value register 1 (ADCDR1) and the AD conversion finished flag (EOCF) of AD converted value register 2 (ADCDR2) is set to “1”, upon which time AD conversion interrupt INTADC is gen- erated. 5. EOCF is cleared to “0” by a read of the conversion result. However, if reconverted before a register read, although EOCF is cleared the previous conversion result is retained until the next conversion is completed. ADCDR1,ADCDR2 EOCF cleared by reading conversion result Conversion result read ADCDR2<EOCF> INTADC interrupt request Conversion operation ADCCR1<ADRS> Indeterminate AD conversion start 1st conversion result AD convert operation suspended. Conversion result is not stored.2nd conversion result 3rd conversion result ADCDR1 ADCDR2 2nd conversion result 3rd conversion result1st conversion result Conversion result read Conversion result read Conversion result read Conversion result read Conversion result read

12.4 STOP/SLOW Modes during AD Conversion

When standby mode (STOP or SLOW mode) is entered forcibly during AD conversion, the AD convert operation is suspended and the AD converter is in itialized (ADCCR1 and ADCCR2 are initia lized to initial value). Also, the conversion result is indeterminate. (Conversion results up to the previous operation are cleared, so be sure to read the conversion results before entering standby mode (STO P or SLOW mode).) When restored from standby mode (STOP or SLOW mode), AD conversion is not automatically restarted, so it is necessa ry to restart AD conversion. Note that since the analog reference voltage is automatically disconnected, there is no possibility of current flowing into the analog reference voltage. Example :After selecting the conversion time 19.5 µs at 16 MHz and the analog input channel AIN3 pin, perform AD con- version once. After checking EOCF, read the converted value, store the lower 2 bits in address 0009EH nd store the upper 8 bits in address 0009FH in RAM. The operation mode is software start mode. : (port setting) : ;Set port register approrriately before setting AD converter registers. : : (Refer to section I/O port in details) LD (ADCCR1) , 00100011B ; Select AIN3 LD (ADCCR2) , 11011000B ;Select conversion time(312/fc) and operation mode SET (ADCCR1) . 7 ; ADRS = 1(AD conversion start) SLOOP : TEST (ADCDR2) . 5 ; EOCF= 1 ? JRS T, SLOOP LD A , (ADCDR2) ; Read result data LD (9EH) , A LD A , (ADCDR1) ; Read result data LD (9FH), A

1. 10-bit AD Converter (ADC)

12.5 Analog Input Voltage and AD Conversion Result TMP86CH47AUG

12.5 Analog Input Voltage and AD Conversion Result

The analog input voltage is corresponded to the 10-bit digital value converted by the AD as shown in Figure 12-4. Figure 12-4 Analog Input Voltage and AD Conversion Result (Typ.) 01H 02H 03H 3FDH 3FEH 3FFH 2 3 1021 1022 1023 1024 Analog input voltage 1024 AD conversion result VAREF AVSS

12.6 Precautions about AD Converter

12.6.1 Analog input pin voltage range

Make sure the analog input pins (AIN0 to AIN7) are used at voltages within V AREF to A VSS. If any volt- age outside this range is applied to one of the analog input pins, the converted value on that pin becomes uncer- tain. The other analog input pins also are affected by that.

12.6.2 Analog input shared pins

The analog input pins (AIN0 to AIN7) are shared w ith input/output ports. When using any of the analog inputs to execute AD conversion, do not execute input/output instructions for all other ports. This is necessary to prevent the accuracy of AD conversion from degrading. Not only these analog input shared pins, some other pins may also be affected by noise arising from input/output to and from adjacent pins.

12.6.3 Noise Countermeasure

The internal equivalent circuit of the analog input pins is shown in Figure 12-5. The higher the output impedance of the analog input source, more easily they are susceptible to noise. Therefore, make sure the out- put impedance of the signal source in your design is 5 kΩ or less. Toshiba also recommends attaching a capac- itor external to the chip. Figure 12-5 Analog Input Equivalent Circuit and Example of Input Pin Processing DA converter AINi Analog comparatorInternal resistance Permissible signal source impedance Internal capacitance 5 kΩ (typ) C = 12 pF (typ.) 5 kΩ (max) Note) i = 7 to 0

1. 10-bit AD Converter (ADC)

12.6 Precautions about AD Converter TMP86CH47AUG

1. Key-on Wakeup (KWU) In the TMP86CH47AUG, the STOP mode is released by not only P20( INT5/STOP) pin but also four (STOP2 to STOP5) pins. When the STOP mode is released by STOP2 to STOP5 pins, the STOP pin needs to be used. In details, refer to the following section " 13.2 Control ".

13.1 Configuration

Figure 13-1 Key-on Wakeup Circuit

13.2 Control

STOP2 to STOP5 pins can controlled by Key-on Wakeup C ontrol Register (STOPCR). It can be configured as enable/disable in 1-bit unit. When thos e pins are used for STOP mode releas e, configure corresponding I/O pins to input mode by I/O port register beforehand.

13.3 Function

Stop mode can be entered by setting up the System Control Register (SYSCR1), and can be exited by detecting the "L" level on STOP2 to STOP5 pins, which are enabled by STOPCR, for releasing STOP mode (Note1). Key-on Wakeup Control Register S T O P C R 7654 3 2 1 0 (0031H) STOP5 STOP4 STOP3 STOP2 (Initial value: 0000 ****) STOP5 STOP mode released by STOP5 0:Disable 1:Enable Write only STOP4 STOP mode released by STOP4 0:Disable 1:Enable Write only STOP3 STOP mode released by STOP3 0:Disable 1:Enable Write only STOP2 STOP mode released by STOP2 0:Disable 1:Enable Write only STOPCR INT5 STOPSTOP mode release signal (1: Release) (0031H) STOP2 STOP3 STOP4 STOP5 STOP2 STOP3 STOP4 STOP5

1. Key-on Wakeup (KWU)

13.3 Function TMP86CH47AUG

Also, each level of the STOP2 to STOP5 pins can be co nfirmed by reading correspondi ng I/O port data register, check all STOP2 to STOP5 pins "H" that is enabled by STOPCR before the STOP mode is startd (Note2,3). Note 1: When the STOP mode released by the edge release mode (SYSCR1<RELM> = “0”), inhibit input from STOP2 to STOP5 pins by Key-on Wakeup Control Register (STOPCR) or must be set "H" level into STOP2 to STOP5 pins that are available input during STOP mode. Note 2: When the STOP pin input is high or STOP2 to STOP5 pins inputwhich is enabled by STOPCR is low, executing an instruction which starts STOP mode will not place in STOP mode but instead will immediately start the release sequence (Warm up). Note 3: The input circuit of Key-on Wakeup input and Port input is separatedÅAso each input voltage threshold value is diffrent. Therefore, a value comes from port input before STOP mode start may be diffrent from a value which is detected by Key-on Wakeup input (Figure 13-2). Note 4: STOP pin doesn’t have the control register such as STOPCR, so when STOP mode is released by STOP2 to STOP5 pins, STOP pin also should be used as STOP mode release function. Note 5: In STOP mode, Key-on Wakeup pin which is enabled as input mode (for releasing STOP mode) by Key-on Wakeup Control Register (STOPCR) may genarate the penetration current, so the said pin must be disabled AD conversion input (analog voltage input). Note 6: When the STOP mode is released by STOP2 to STOP5 pins, the level of STOP pin should hold "L" level (Figure 13-3). Figure 13-2 Key-on Wakeup Input and Port Input Figure 13-3 Priority of STOP pin and STOP2 to STOP5 pins Table 13-1 Release level (edge) of STOP mode Pin name Release level (edge) SYSCR1<RELM>="1" (Note2) SYSCR1<RELM>="0" STOP "H" level Rising edge STOP2 "L" level Don’t use (Note1) STOP3 "L" level Don’t use (Note1) STOP4 "L" level Don’t use (Note1) STOP5 "L" level Don’t use (Note1) Port input External pin Key-on wakeup input STOP pin a) STOP Release STOP modeSTOP mode STOP pin "L" Release STOP modeSTOP mode In case of STOP2 to STOP5 STOP2 pin

1. Input/Output Circuitry

14.1 Control Pins

The input/output circuitries of the TMP86CH47AUG control pins are shown below. Note: The TEST pin of the TMP86PM47/PH47 does not have a pull-down resistor and protect diode (D1). Fix the TEST pin at low- level. Control Pin I/O Input/Output Circuitry Remarks XIN XOUT Input Output Resonator connecting pins (high-frequency) Rf = 1.2 MΩ (typ.) RO = 1.5 kΩ (typ.) XTIN XTOUT Input Output Resonator connecting pins (low-frequency) R f = 6 MΩ (typ.) RO = 220 kΩ (typ.) RESET I/O Hysteresis input Pull-up resistor RIN = 220 kΩ (typ.) R = 1 kΩ (typ.) TEST Input Pull-down resistor RIN = 70 kΩ (typ.) R = 1 kΩ (typ.) fc Rf RO Osc. enable XIN XOUT VDDVDD fs Rf RO Osc. enable XTIN XTEN XTOUT VDDVDD /K52 /K49/K4E/K52 /K56/K44/K44 /K41/K64/K64/K72/K65/K73/K73 /K74/K72/K61/K70 /K72/K65/K73/K65/K74 /K57 /K61/K74/K63/K68/K64/K6F/K67 /K74/K69/K6D/K65/K72 /K72/K65/K73/K65/K74 /K53/K79/K73/K74/K65/K6D /K63/K6C/K6F/K63/K6B /K72/K65/K73/K65/K74 VDD RIN R

1. Input/Output Circuitry

14.2 Input/Output Ports TMP86CH47AUG

14.2 Input/Output Ports

Port I/O Input/Output Circuitry Remarks P0 I/O Sink open drain output High current output Hysteresis input R = 100 Ω (typ.) P1 I/O Tri-state I/O Hysteresis input R = 100 Ω (typ.) P2 I/O Sink open drain output High current output Hysteresis input R = 100 Ω (typ.) P3 I/O Tri-state I/O R = 100 Ω (typ.) P4 I/O Tri-state I/O High current output (Nch) R = 100 Ω (typ.) /K49/K6E/K69/K74/K69/K61/K6C /K22/K48/K69/K67/K68/K2D/K5A/K22 /K49/K6E/K70/K75/K74 /K66/K72/K6F/K6D /K3 /K6F/K75/K74/K70/K75/K74 /K6C/K61/K74/K63/K68 /K44/K61/K74/K61 /K6F/K75/K74/K70/K75/K74 /K50/K69/K6E /K69/K6E/K70/K75/K74 /K56/K44/K44 /K52 /K49/K6E/K69/K74/K69/K61/K6C /K22/K48/K69/K67/K68/K2D/K5A/K22 /K44/K69/K73/K61/K62/K6C/K65 /K56/K44/K44 /K52 /K44/K61/K74/K61 /K6F/K75/K74/K70/K75/K74 /K50/K69/K6E /K69/K6E/K70/K75/K74 /K49/K6E/K69/K74/K69/K61/K6C /K22/K48/K69/K67/K68/K2D/K5A/K22 /K49/K6E/K70/K75/K74 /K66/K72/K6F/K6D/K3 /K6F/K75/K74/K70/K75/K74 /K6C/K61/K74/K63/K68 /K44/K61/K74/K61 /K6F/K75/K74/K70/K75/K74 /K50/K69/K6E /K69/K6E/K70/K75/K74 /K56/K44/K44 /K52 /K49/K6E/K69/K74/K69/K61/K6C /K22/K48/K69/K67/K68/K2D/K5A/K22 /K44/K69/K73/K61/K62/K6C/K65 /K56/K44/K44 /K52 /K44/K61/K74/K61 /K6F/K75/K74/K70/K75/K74 /K50/K69/K6E /K69/K6E/K70/K75/K74 /K49/K6E/K69/K74/K69/K61/K6C /K22/K48/K69/K67/K68/K2D/K5A/K22 /K44/K69/K73/K61/K62/K6C/K65 /K56/K44/K44 /K52 /K44/K61/K74/K61 /K6F/K75/K74/K70/K75/K74 /K50/K69/K6E /K69/K6E/K70/K75/K74

1. Electrical Characteristics

15.1 Absolute Maximum Ratings

The absolute maximum ratings are rated values, which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causi ng it to catch fire or explode resul ting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. (VSS = 0 V) Parameter Symbol Pins Ratings Unit Supply voltage VDD −0.3 to 6.5 VInput voltage VIN −0.3 to VDD + 0.3 Output voltage VOUT −0.3 to VDD + 0.3 Output current (Per 1 pin) IOUT1 P1, P3, P4 port −1.8 mA IOUT2 P1, P3 port 3.2 IOUT3 P0, P2, P4 port 30 Output current (Total) Σ IOUT2 P1, P3 port 60 Σ IOUT3 P0, P2, P4 port 80 Power dissipation [Topr = 85°C] PD 250 mW Soldering temperature (Time) Tsld 260 (10 s) °CStorage temperature Tstg −55 to 125 Operating temperature Topr −40 to 85

1. Electrical Characteristics

15.2 Recommended Operating Condition TMP86CH47AUG

15.2 Recommended Op erating Condition

The recommended operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. If the device is us ed under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified AC/DC values etc.), malfunction may occur. Thus, when designing products which include this device, ensure that the recommended operating conditions for the device are always adhered to. Note 1: When the supply voltage is VDD=1.8 to 2.0V, the operating tempreture is Topr= -20 to 85 °C. (VSS = 0 V, Topr = −40 to 85°C) Parameter Symbol Pins Condition Min Max Unit Supply voltage VDD fc = 16 MHz NORMAL1, 2 mode 4.5 5.5 V IDLE0, 1, 2 mode fc = 8 MHz NORMAL1, 2 mode 2.7 IDLE0, 1, 2 mode fc =

4.2 MHz

NORMAL1, 2 mode 1.8 (Note1) IDLE0, 1, 2 mode fs = 32.768 kHz SLOW mode SLEEP mode STOP mode Input high level VIH1 Except hysteresis input VDD ≥ 4.5 V VDD × 0.70 VDDVIH2 Hysteresis input VDD × 0.75 VIH3 VDD < 4.5 V V DD × 0.90 Input low level VIL1 Except hysteresis input VDD ≥ 4.5 V VDD × 0.30 VIL2 Hysteresis input VDD × 0.25 VIL3 VDD < 4.5 V V DD × 0.10 Clock frequency fc XIN, XOUT VDD = 1.8 V to 5.5 V 1.0 4.2 MHzVDD = 2.7 V to 5.5 V 8.0 VDD = 4.5 V to 5.5 V 16.0 fs XTIN, XTOUT 30.0 34.0 kHz

15.3 DC Characteristics

Note 1: Typical values show those at Topr = 25°C, VDD = 5 V Note 2: Input current (IIN1, IIN3); The current through pull-up or pull-down resistor is not included. Note 3: IDD does not include IREF current. Note 4: The supply currents in SLOW2 and SLEEP2 modes are the same as those in IDLE0, IDLE1, and IDLE2 modes. (VSS = 0 V, Topr = −40 to 85°C) Parameter Symbol Pins Condition Min Typ. Max Unit Hysteresis voltage VHS Hysteresis input – 0.9 – V Input current IIN1 TEST VDD = 5.5 V, VIN = 5.5 V/0 V –– ±2 µAIIN2 Sink open drain, Tri-state port IIN3 RESET, STOP Input resistance RIN1 TEST pull-down – 70 – kΩ RIN2 RESET pull-up 100 220 450 Output leakage current ILO1 Sink open drain VDD = 5.5 V, VOUT = 5.5 V ––2 µA ILO2 Tri-state port VDD = 5.5 V, VOUT = 5.5 V/0 V –– ±2 Output high voltage VOH Tri-state port VDD = 4.5 V, VOH = -0.7 mA 4.1 – – V Output low voltage VOL Except XOUT, P0, P4, P2 port VDD = 4.5 V, VOL = 1.6 mA –– 0 . 4 Output low current IOL High current port (P0, P2, P4 port) V DD = 4.5 V, VOL = 1.0 V –2 0– m A Supply current in NORMAL1, 2 mode I DD VDD = 5.5 V VIN = 5.3/0.2 V fc = 16 MHz fs = 32.768 kHz –7 . 59 mA Supply current in IDLE0, 1, 2 mode –5 . 5 6 . 5 Supply current in SLOW1 mode V DD = 3.0 V VIN = 2.8 V/0.2 V fs = 32.768 kHz –8 2 0 µA Supply current in SLEEP1 mode –5 1 5 Supply current in SLEEP0 mode –4 1 3 Supply current in STOP mode V DD = 5.5 V VIN = 5.3 V/0.2 V –0 . 5 1 0

1. Electrical Characteristics

15.4 AD Conversion Characteristics TMP86CH47AUG

15.4 AD Conversi on Characteristics

Note 1: The total error includes all errors except a quantization error, and is defined as a maximum deviation from the ideal con- version line. Note 2: Conversion time is different in recommended value by power supply voltage. About conversion time, please refer to “Register Configuration”. Note 3: Please use input voltage to AIN input Pin in limit of VAREF − VSS. When voltage of range outside is input, conversion value becomes unsettled and gives affect to other channel conversion value. Note 4: Analog reference voltage range: ∆VAREF = VAREF − VSS Note 5: When AD is used with VDD < 2.7 V, the guaranteed temperature range varies with the operating voltage. (VSS = 0.0 V, 4.5 V ≤ VDD ≤ 5.5 V, Topr = −40 to 85°C) Parameter Symbol Condition Min Typ. Max Unit Analog reference voltage VAREF AVDD − 1.0 – AVDD V Power supply voltage of analog control cir- cuit AVDD VDD Analog reference voltage range (Note 4) ∆VAREF 3.5 – – Analog input voltage VAIN VSS – VAREF Power supply current of analog reference voltage I REF VDD = AVDD = VAREF = 5.5 V VSS = AVSS = 0.0 V –0 . 6 1 . 0 m A Non linearity error VDD = AVDD = 5.0 V VSS = AVSS = 0.0 V VAREF = 5.0 V –– ±2 LSB Zero point error –– ±2 Full scale error –– ±2 Total error –– ±2 (VSS = 0.0 V, 2.7 V ≤ VDD < 4.5 V, Topr = −40 to 85°C) Parameter Symbol Condition Min Typ. Max Unit Analog reference voltage VAREF AVDD − 1.0 – AVDD V Power supply voltage of analog control cir- cuit A VDD VDD Analog reference voltage range (Note 4) ∆VAREF 2.5 – – Analog input voltage VAIN VSS – VAREF Power supply current of analog reference voltage I REF VDD = AVDD = VAREF = 4.5 V VSS = AVSS = 0.0 V –0 . 5 0 . 8 m A Non linearity error VDD = AVDD = 2.7 V VSS = AVSS = 0.0 V VAREF = 2.7 V –– ±2 LSB Zero point error –– ±2 Full scale error –– ±2 Total error –– ±2 (VSS = 0.0 V, 2.0 V ≤ VDD < 2.7 V, Topr = −40 to 85°C) (Note 5) (VSS = 0.0 V, 1.8 V ≤ VDD < 2.0 V, Topr = −10 to 85°C) (Note 5) Parameter Symbol Condition Min Typ. Max Unit Analog reference voltage VAREF AVDD − 0.9 – AVDD V Power supply voltage of analog control cir- cuit A VDD VDD Analog reference voltage range (Note 4) ∆VAREF Analog input voltage VAIN VSS – VAREF Power supply current of analog reference voltage I REF VDD = AVDD = VAREF = 2.7 V VSS = AVSS = 0.0 V –0 . 3 0 . 5 m A Non linearity error VDD = AVDD = 1.8 V VSS = AVSS = 0.0 V VAREF = 1.8 V –– ±4 LSB Zero point error –– ±4 Full scale error –– ±4 Total error –– ±4

15.5 AC Characteristics

Note 1: When the supply voltage is VDD=1.8 to 2.0V, the operating tempreture is Topr= -20 to 85 °C. (VSS = 0 V, VDD = 4.5 to 5.5 V, Topr = −40 to 85°C) Parameter Symbol Condition Min Typ. Max Unit Machine cycle time tcy NORMAL1, 2 mode 0.25 – 4 µs IDLE0, 1, 2 mode SLOW1, 2 mode 117.6 – 133.3 SLEEP0, 1, 2 mode High level clock pulse width tWCH For external clock operation (XIN input) fc = 16 MHz –3 1 . 2 5–n s Low level clock pulse width t WCL High level clock pulse width tWSH For external clock operation (XTIN input) fs = 32.768 kHz –1 5 . 2 6– µs Low level clock pulse width t WSL (VSS = 0 V, VDD = 2.7 to 4.5 V, Topr = −40 to 85°C) Parameter Symbol Condition Min Typ. Max Unit Machine cycle time tcy NORMAL1, 2 mode 0.5 – 4 µs IDLE0, 1, 2 mode SLOW1, 2 mode 117.6 – 133.3 SLEEP0, 1, 2 mode High level clock pulse width tWCH For external clock operation (XIN input) fc = 8 MHz – 62.5 – ns Low level clock pulse width tWCL High level clock pulse width tWSH For external clock operation (XTIN input) fs = 32.768 kHz –1 5 . 2 6– µs Low level clock pulse width t WSL (VSS = 0 V, VDD = 1.8 to 2.7 V, Topr = −40 to 85°C) Parameter Symbol Condition Min Typ. Max Unit Machine cycle time tcy NORMAL1, 2 mode 0.95 – 4 µs IDLE0, 1, 2 mode SLOW1, 2 mode 117.6 – 133.3 SLEEP0, 1, 2 mode High level clock pulse width tWCH For external clock operation (XIN input) fc = 4.2 MHz –1 1 9 . 0 5– n s Low level clock pulse width tWCL High level clock pulse width tWSH For external clock operation (XTIN input) fs = 32.768 kHz –1 5 . 2 6– µs Low level clock pulse width t WSL

1. Electrical Characteristics

15.6 Recommended Oscillating Conditions TMP86CH47AUG

15.6 Recommended Osc illating Conditions

Note 1: A quartz resonator can be used for high-frequency oscillation only when VDD is 2.7 V or above. If VDD is below 2.7 V, use a ceramic resonator. Note 2: To ensure stable oscillation, the resonator position, load capacitance, etc. must be appropriate. Because these factors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the device will actually be mounted. Note 3: For the resonators to be used with Toshiba microcontrollers, we recommend ceramic resonators manufactured by Murata Manufacturing Co., Ltd. For details, please visit the website of Murata at the following URL: http://www.murata.com

15.7 Handling Precaution

• The solderability test conditions for lead-free produc ts (indicated by the suffix G in product name) are shown below. 1. When using the Sn-37Pb solder bath Solder bath temperature = 230 °C Dipping time = 5 seconds Number of times = once R-type flux used 2. When using the Sn-3.0Ag-0.5Cu solder bath Solder bath temperature = 245 °C Dipping time = 5 seconds Number of times = once R-type flux used Note: The pass criteron of the above test is as follows: Solderability rate until forming ≥ 95 % - When using the device (oscillator) in places exposed to high electric fields such as cathode-ray tubes, we recommend electrically shielding the package in order to maintain normal operating condition. /K28/K32/K29 /K4C/K6F/K77/K2D/K66/K72/K65/K71/K75/K65/K6E/K63/K79 /K4F/K73/K63/K69/K6C/K6C/K61/K74/K69/K6F/K6E/K28/K31/K29 /K48/K69/K67/K68/K2D/K66/K72/K65/K71/K75/K65/K6E/K63/K79 /K4F/K73/K63/K69/K6C/K6C/K61/K74/K69/K6F/K6E /K58/K49/K4E /K58/K4F/K55/K54 /K43 /K32/K43 /K31 /K58/K54/K49/K4E /K58/K54 /K4F/K55/K54 /K43 /K32/K43 /K31

1. Package Dimensions 0.37 12.0 0.2 10.0 0.2 12.0 0.2 10.0 0.2 0.6 0.15 0.25 0.145 0.055 0.1 1.6MAX 0.05 1.4 0.05 0.08 0.07 0.2 0.8 1.0TYP LQFP44-P-1010-0.80B Rev 01 Unit: mm

1. Package Dimensions TMP86CH47AUG

This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/C (LSI). Toshiba provides a variety of development tools a nd basic software to enable efficient software development. These development tools have specifications that support advances in microcomputer hardware (LSI) and can be used extensively. Both the hardware and software are supported continuously with version updates. The recent advances in CMOS LSI production technology have be en phenomenal and microcomputer systems for LSI design are constantly being improved. The products described in this document may also be revised in the future. Be sure to check the latest specifications before using. Toshiba is developing highly integrated, high-perfo rmance microcomputers using advanced MOS production technology and especially well proven CMOS technology. We are prepared to meet the requests for custom packaging for a variety of application areas. We are confident that our products can satisfy your application needs now and in the future.