TMP82C51A

TMP82C51A TOSHIBA | Alldatasheet

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TMP82C51AP-2 / TMP82C51AP-10 TMP82C51AM-2 / TMP82C51AM-10 PROGRAMMABLE COMMUNICATION INTERFACE 1. GENERAL DESCRIPTION The TMP82C51A is the industry standard Universal Synchronous/Asynchronous Receiver/Transmitter (USART) that is fabricated using C-MOS silicon gate technology. The 82C51A is mainly used for 8-bit microcomputer extention system, which require serial data communications. The TMP82C51AP-2/TMP82C51AP-10 is packaged in the 28 pin standard Dual Inline Package. The TMP82C51AM-2/TMP82C51AM-10 is packaged in the 28 pin Small Out Line Package.

FEATURES

@ Synchronous: 5-8 Bit Characters Internal or External Character Synchronization Single or Double Character Synchronization (Inrternal) Automatic Sync Character(s) Insertion @ Asynchronous: 5-8 Bit Characters Clock Rate -1, 16 or 64 Times Transfer Rate Break Character Generation 1, 1.5 or 2 stop Bits False Start Bit Detection Automatic Break Detect and Handling @ TransferRate TMP82C51A-2 TMP82C51A-10 DC-104K bps DC-300K bps @ Full-Duplex, Double-Buffered, Transmitter and Receiver e Error DetectionParity, Overrun and Framing. @ Single +5V Supply: 5V +10% MPU85-42

1. PIN CONNECTIONS (DIP, SOP) D2 1 2810 Dy D3 02 2710 Do RxD O13 266 Vee GND (4 2510 Rx Da 5 24 DIR Ds C6 230 RTS De C7 221 DSR D7 8 21) RESET Tc 9 2019 CLK WR (110 191 TxD sq 181 TxEMPTY c/D 12 170 CTS RO O13 16 SYNDET/BD RxRDY 1] 14 151 TxRDY osoae9 3. BLOCK DIAGRAM RECEIVE DATA (Ps) ot | | sc ¢ f BUFFER Da ae Ds TRANSMIT DATA CONTROL | TxC De BUFFER COMMAND DATA T (Ps) RESET RxRDY CLK RECEIVE 4 SYNDET/BD READ/WRITE contre |, Rxt — CONTROL cD | ! RD d LOGIC | cs 7G _ MODEM as va CONTROL fp DTR Vee b DSR GND INTERNAL DATA BUS, osoaes MPU85-43

1. PIN NAMES AND PIN DESCRIPTIONS

4.1 INTERFACE SIGNALS TO CPU (MAIN SYSTEM)

® DO-D7 (Input/Output) This 3-state, bidirectional, 8-bit buffer is used to interface with the system Data Bus. Data is transmitted or received through the buffer upon execution of Input or Output Instructions of the CPU. Control Words, Command Words and Status Information are also transferred through the Data Bus Buffer. e WR (Input) A “low” level signal on this input informs the 82C51A that the CPU is Writing Data or Control Words to the 82C51A. e RD Unput) A “low” level signal on this input informs the 82C51A that the CPU is Reading Data or Status Information from the 82C51A. e CS (Input) A “low” level signal on this input selects the 82C51A. No reading or writing operation will occur unless the device is selected. When CS is “high” the Data Bus is in the floating state and RD and WR have no effect on the chip. ® C/D (Input) This input signal, in conjuction with the WR and RD inputs, informs the 82C51A that the word on the Data Bus is either a Data Bus Character, Control Word or Status Information. A “high” level signal means Control or Status, a “low” level signal means Data. cD RD WR OS 0 0 1 0 82C51A Receive DATA Buffer — DATA Bus 0 1 0 i 82C51A Transmit DATA Buffer < DATA Bus 1 0 1 0 82C51A Status DATA Buffer — DATA Bus x 1 1 0 DATA Bus is in floating state. x x x 1 DATA Bus is in floating state. © CLK (Input) The CLK input is used to generate internal device timing. No external input or output referenced to CLK, but the frequency of CLK must be greater than 30 times the Receiver or Transmitter Data Bit Rates (RxC or TxC) in Synchronous Operation, and greater than 4.5 times the Receiver Data Bit Rates (RxC or Trransmiter, TxC) in Asynchronous operation. eee MPU85-44

@ RESET (Input) A “high” level signal on this input forces the 82C51A into an “Idle” mode. The device will remain “Idle” until a new set of Control Words is written into the 82C51A to program its functional definition. Minimum RESET pulse width is 6 ty.

4.2 MODEM CONTROL SIGNALS

e DSR (input) The DSR input signal is a general purpose, 1-bit inverting input port. Its condition can be tested by the CPU using a Status Read Operation. The DSR input is normally used to test MODEM conditions such as Data Set Ready signal. © DTR (Output) The DTR output signal is a general purpose, 1-bit inverting output port. It can be set “low” by programming the appropriate bit in the Command Instruction Words. The DTR output signal is normally used for MODEM control such as Data Terminal Ready or Rate Select signal. e@ RTS (Output) The RTS output signal is a general purpose, 1-bit inverting output port. It can be set “low” by pogramming the appropriate bit in the Command Instruction Word. The RTS output signal is normally used for MODEM control such as Request to Send signal. © CTS (Input) A “low” level signal on this input enables the 82C51A to transmit serial data, if the Tx Enable Bit in the Command Byte is set to a “one” (TxEN=1). If either a Tx Enable off (TxEN=0) or CTS off (CTS=1) condition occurs while the Tx is in operaion, the Tx will transmit all the data in the USART, written prior to Tx Disable Command before shutting down. 4.3. TRANSMIT CONTROL SIGNALS e TxC (Input) The transmitter Clock controls the rate at which the character is to be transmitted. In the Synchronous Transmission Mode, the Transfer Rate (1x) is equal to the TxC frequency. In Asynchronous Transmission Mode the transfer rate is a fraction of the actual TxC ferquency. A portion of the Mode Instruction selects this factor; it can be 1, 1/16 or 1/64 the TxC. MPU85-45

For Example: If Transfer Rate equals 110 bps, TxC=110Hz = (1x) TxC =1.76kHz (16x) TxC = 7.04 Hz (64x) The falling edge of TxC shifts the serial data out of the 82C51A. ® TxD (Output) This line is used to transmit serial data. Serial output data on TxD is changed from parallel data to serial data in accordance with the TxD line will be held in the marking state (‘1’ level) immediately on one of the followings. + Master Reset + Tx Disable (TxEN=0) + CTS signal is high (CTS=1) + TxEMPTY signal is high (TxEMPTY = 1) © TxRDY (Output) This output informs the CPU that the transmitter is ready to accept a Data Character. The TxRDY output pin can be used as an interrupt to the system, since it is masked by Tx Disable (TxEN=0), or, for polled Operation, the CPU can check TxRDY using a Status Read Operation, TxRDY is automatically reset by the trailing edge of WR when a Data Character is loaded from the CPU. The TxRDY pin output status (TxRDY (pin)) is different from the TxRDY status bit status register (TxRDY (status bit)) as follows. TxRDY (status bit) = (Transmit Data Buffer Empty) TxRDY (pin) = (Transmit Data Buffer Empty) AND (CTS=0) AND (TxEN =1) © TxEMPTY (Output) The TxEMPTY output will go “high” when the 82C51A has no characters to send. It resets upon receiving a character from the CPU if the transmitter is enabled. In Synchronous Mode, a “high” level signal on this output indicates that a Character has not been loaded and the SYNC Character or Characters are about to be or are being transmitted automatically as “fillers”. TxEMPTY does not go “low” when the SYNC characters are being shifted out. MPU85-46

4.4 RECEIVE CONTROL SIGNALS

© RxC (Input) The Receiver Clock controls the rate at which the character is to be received. In Synchronous Mode, the Transfer Rate (1x) is equal to the actual frequency of RxC. In Asynchronous Mode, the Transfer Rate is a fraction of the actual RxC frequency. A portion of the Mode Instruction selects this factor; 1, 1/16 or 1/64 the RxC. For Example: If Transfere Rate equals 2400 bps, RxC =2.4kHz (1x) RxC = 38.4kHz (16x) RxC = 153.6kHz (64x) Data is sampled into the 82C51A on the rising edge of RxC. ® RxD (Input) This line is used to receive the serial data. Serial input data on this line is changed to parallel data in accordance with the format specified by the Control Words, and then transfered to the Receive Data Buffer. @ RxRDY (Output) This output indicates that the 82C51A contains a Data Character that is ready to be input to the CPU. RxRDY can be connected to the interrupt structure of the CPU, or, for Polled Operation, the CPU can check the condition of RxRDY using Status Read Operation. Rx Enable off both masks and holds RxRDY in the Reset Condition. © SYNDET/BD (Input/Output) This pin is used for SYNDET in Synchronous Mode and may used as either input or output, programmable through the Control Word. It is reset to output mode “low” upon RESET. When used as an Output (Internal Syne Mode), the SYNDET pin will go “high” to indicate that the 82C51A has located the SYNC Character in the Receive Mode. If the 82C51A is programmed to use Double Sync Characters then SYDET will go “high” in the middle of the last bit of the second SYNC Character. SYNDET is automatically reset upon a Status Read Operation. When used as an Input (External Sync Mode), a positive going signal will cause the 82C51A to start assembling Data Characters on the rising edge of the next RxC. eee MPU85-47

In Asynchronous Mode this pin is used BD. This output will go “high” whenever the receiver remains “low” through two consecutive Stop Bit Sequences (including the Start Bits, Data Bits, and parity bits). Break Detect may also be read as a Status Bit. It is reset only upon a Master Chip Reset or Rx Data returning to a “one” state.

4.5 POWER SUPPLY

@ VCC (Power) +5 Volt supply © GND (Power)

0 Volt supply

1. ELECTRICAL CHARACTERISTICS

5.4 MAXIMUM RATINGS

Power Supply Voltage (with respectto GND) | —0.5Vto7.0V Input Voltage (with respect to GND) =0.5Vto Vec +0.5 Vout Output Voltage (with respect to GND) =0.5V to Vec +0.5 Po Power Dissipation 250mWw Soldering Temperature (10 sec) Storage Temperature | 65°C to 150°C Operating Temperature = 40°C to 85°C Gs0%09 5.2 D.C CHARACTERS Topr= —40°C to +85°C, VCC = + 5V + 10%, GND = OV, Unless otherwise noted. Re featiometegs [es [Vor __[OutputLow Voltage | 10L=2.2mA Vou Output High Voltage |IOH = — 400pA Von2 Output High Voltage |IOH= — 100nA Vee = 0.8 [ -_| - Output Leak Current | 0.45V= VOUTS VCC - | - | +10 Ji input teak Current 0.45VS VOUTS Vcc - | -_| +10 Power Supply Current | tcye = 200ns , oe 1.2 5.0 mA (AP-2/AM-2, 5MHz)__| Vin = 4.8V/0.2V cer Power Supply Current |tcyc=125ns 2.0 70.0 mA (AP-8/AM-8, 8MHz) Vin =4.8V/0.2V Power Supply Current |tcyc = 100ns 25 15 mA {AP-10/AM-10, 10MHz) | Vin = 4.8V/0.2V STOP All Clocks \\cc2 ondbe eregen Vee =5V, CS =1 0.5 10.0 | pa Y Vin = 4.8V/0.2V 50489 MPU85-49

5.3 AC CHARACTERISTICS

Topr= — 40°C to 85°C, VCC =5V + 10%, GND =OV, Unless otherwise noted.

5.3.1 Bus Read Cycle Timing Note 1)

| CS, C/D Set-up {Mt [Time for RO Pe f el -| ” t CS, C/D Hold ns RA | Time for RD Data Delay Time CL = 150pF | aed 140 | - | "RO | for RD Note 2) Note 3) ° too | ns 230589

5.3.2 Bus Write Cycle Timing (Note 1)

| Test AP-2/AM-2 | AP-10/AM-10 ; symbol Parameter Units | Conditions | Min. Max. | + GS, c/D Set-up | aw ° - |e] - | " t CS, C/D Hold i nS WA |Time for WR Data Set-up Time ‘ow awe] fw | = fe | "s t Data Hold Time _ ns WO | for WR Recovery Time Between Nowe) Fst = |e] = fos] 230589 MPU85-50

5.3.3 Other Timings

fiye [Clock Period ove 5,6) | 200) = 7100 | - [7] ClockHigh LevelWaith [a0] - a0] = | ws | Clock tow Level Wait [so [a0 | Clock ise, Fal Time [= ae = 0 J cae tDTx Edge of TxC ~~ [Transmitter input oa | Dc | 300 | fTx Clock Frequency 528 khz tTPH | Clock Low Level | 16x, 64x, 7 1 teyc Transmitter input] txBaudRate | 75 Das tTPL | Clock High Level | 16x, 64x, 3 = | tee Width Baud Rate Receiverinput | ixBaudRate| DC | 104 | DC | 300 tex | clock Frequency bie ReceiverInput | IxBaudRate| 12 | - [| 12 | - ‘| 1RPH — | Clock High Level | 16x, 64x, 7 teyc Receiver Input ixBaudRate{ 15 [| - | 1s | — tRPH — | Clock Low Level | 16x, 64x, 3 3 = | tye tTxRDY Center of Last Bit tTxRDY_ | TxRDY Clear Delay Time from 400 | 150 | ns Ea senoegeatn | a freer [emeacreee | | | | ® tRxRDY Center of Last Bit tRxRDY [TxRDY Clear Delay Time from 750 | ns ita [esinocaeorme™ "| | | from Rising Edge of RxC fs [ramen | | TL Falling Edge of RxC tTx TxEMPTY Delay Time from 20 20 | teyc Siew [emmeararae | | | | TS Edge of WR (TxEN, DTRRTS) MPU85-51

Notes: 1) AC Test Condition: Output measuring points VOH=2.2V, VOL=0.8V Input supply level VIH=2.4V, VIL=0.45V 2) Assumes that Address is valid before the falling edge RD. 3) CL means load capacitance. 4) This recovery time is defind only for Mode Intialization. Write Data is allowed only when TxRDY =1. Recovery Time between Writes for Asynchronous Mode is 8 teye and for Synchronous Mode is 16 tcyc. 5) The TxC and RxC frequencies have the following limitations with respect to CLK: For 1x Transfer Rate, fT’ or fRx <1 (30 teye) For 16x and 64x Transfer Rate, fTx or fRx= 1 (4.5 teyc) 6) Minimum Reset Pulse Width is 6 teye. System Clock must running during Reset. 7) Status up data can have a maximum delay of 28 clock periods from the event affecting the status, MPU85-52

1. OUTLINE DRAWING

7.1 DIP

Unit: mm Fa 28 15 fi _ ‘ dé “ ian i al | | ¢ 6 \\ } -3 2 | 3? aa - 4 1 4 oS 37.00.2 S$ [ TI 52 oo ofo Tae a aaa rH H) “| he —— a 4.99TYP 270289 Note : Lead pitch is 2.54mm and to lerance is + 0.25mm against theoretical center of each lead that is obtained on the basis of No.1 and No.28 leads. MPU85-58

7.2. SOP SOP28-P-450 Unit: mm 18.540.2 ween onan LOMA j— 3] ¢ z a} @ s eo! = 2 1 i 14 1.0TYP 0.43401 1.27 s od a Lexy eo F bk 1.020.2 Note: Package Width and Length do not include Mold Protrusions, Allowable Mold Protrusion is 0.15mm. MPU85-59

. PROGRAMMABLE COMMUNICATION INTERFACE TMP8251AP 1. GENERAL DESCRIPTION The TMP8251AP is the industry standard Universal Synchronous/Asynchoronous Receiver/Transmitter (USART) that is fabricated using N-channel silicon gate MOS technology. The TMP8251A is mainly used for 8-bit microcomputer extension systems, which require serial data communications. The TMP82514P is packaged in the 28pin standard Dual Inline package. e Synchoronous: 5-8 Bit Characters Internal or External Character Synchronization Single or Double Character Synchronization (Internal) Automatic Sync Insertion e Asynchronous: 5-8 Bit Characters Clock Rate - 1, 16 or 64 Times Transfer Rate Break Character Generation 1, 1.5, or 2 Stop Bits False Start Bit Detection Automatic Break Detect and Handling e Transfer Rate DC to 64K bps (Synchronous) DC to 19.6K bps (Asynchronous) e Full-Duplex, Double-Buffered, Transmitter and Receiver e Error DetectionParity, Overrun and Framing e Single +5V Supply @ Compatible with Intel’s 8251A/S2657 ee MPU85-60

1. PIN CONNECTIONS (TOP VIEW) D2 1 281 Dy D3 G2 271) Do RxD 03 26 vec GND 4 2510 Rx Dg 5 2410 DIR Ds G6 2319 RTS De G7 227 DSR 07 8 211 RESET Txt 49 20) CLK WR C10 1910 TxD cs qi 18) TxEMPTY cD O12 170 Gs RD O13 161] SYNDET/BD RxRDY [14 15 TxRDY asoass 3. BLOCK DIAGRAM RECEIVE DATA TRANSMIT BUFFER BUFFER —1> TxD Do | (Ps) | D } STATUS DATA BUFFER D3 _ TRANSMIT TxRDY Da | re t TxEMPTY Ds | TRANSMIT DATA CONTROL Tx De BUFFER COMMAND DATA. f KJ RECEIVE BUFFER RxD (Pes) ij 1_ otk READ/ WRITE - +} Barve - SYNDET/ED _ CONTROL | CONTROL RxC cD | — RD qd LOGIC we d _ MODEM ian ars KM i CONTROL [| DIR vec Po Ber GND INTERNAL DATA BUS a os0as9 MPU85-61

1. PIN NAMES AND PIN DESCRIPTIONS

4.1 INTERFACE SIGNALS TO MPU (MAIN SYSTEM)

e Do~Dz7 (Input/Output) This 3-state bidirectional, 8-bit buffer is used to interface the 8251A to the system Data Bus. Data is transmitted or received through the buffer upon execution of Input or Output Instructions of the MPU. Control Words, Command Words and Status Information are also transffered through the Data Bus Buffer. e = =WR (Input) A “low” level signal on this input informs the 8251A that the MPU is Writing Data or Control Words to the 8251A. © RD (Input) A “low” level signal on this input informs the 8251A that the MPU is Reading Data or Status Information from the 8251A. e = CS (Input) A “low” level signal on this input selects the 8251A. No reading or writing operation will occur unless the device is selected. When CS is “high” the Data Bus is in the floating state and RD and WR have no effect on the chips. e = C/D (Input) This input signal, in conjunction with the WR and RD inputs, informs the 8251A that the word on the Data Bus is either a Data Character, Control Word or Status Information. A “high” level signal means Control or Status, a “low” level signal means Data. co RD WR SSS 0 0 1 0 8251A Recieve DATA Buffer — Data Bus 0 1 0 () 8251A Transmit DATA Buffer < Data Bus 1 0 1 0 8251A Status DATA Buffer — Data Bus 1 1 0 0 8251A Command DATA Buffer — Data Bus x 1 1 0 DATA Busis in floating state x x x 1 4 eee MPU85-62

© CLK (Input) The CLK input is used to generate internal device timing. No external input or output is referenced to CLK, but the frequency of CLK must be greater than 30 times the Receiver or Transmitter Data Bit Rates (RxC or TxC) in Synchronous Operation, and greater than 4.5 times the Receiver Data Bit Rated (RxC) in Asynchronous Operation. © RESET (Input) A “high” level signal on this input forces the 8251A into an “Idle” mode. The device will remain at “Idel” untill a new set of Control Words is written into the 8251A to program its functional definition. Minimum RESET pulse width is 6 tey. . DSR (Input) The DSR input signal is a general purpose, 1-bit inverting input port. Its condition can be tested by the MPU using a Status Read Operation. The DSR input is normlaly used to test MODEM conditions such as Data Set Ready signal. e DTR (Output) The DTR output signal is a general purpose, 1-bit inverting output port. It can be set “low” by programming the appropriate bit in the Command Instsruction Word. The DTR output signal is normally used for MODEM control such as Data Terminal Ready or Rate Select signal. e RTS (Output) | The RTS output signal is a general purpose, 1-bit inverting output port. It can be set “low” by programming the appropriate bit in the Command Instruction Word. The RTS output signal is normally used for MODEM control such as Request to Send signal. e CTS (Input) A “low” level signal on this input enables the 8251A to transmit serial data, if the Tx Enable Bit in the Command Byte is set to a “one” (TxEN=1). If either a Tx Enable off (TxEN=0) or CTS off (CTS=1) condition occurs while the Tx is in operation, the Tx will transmit all the data in the USART, written prior to Tx Disable Command before shutting down. MPU85-63

4.3. TRANSMIT CONTROL SIGNALS e TxC (Input) The Transmitter Clock Controls the rate at which the character is to be transmitted. In the Synchronous Transmission Mode, the transfer rate (1x) is equal to the TxC frequency. In Asynchronous Transmission Mode, the transfer rate is a fraction of the actual TxC frequency. A poriton of the Mode Instruction selects this factor; it can be 1, 1/16 or 1/gq the TxC. For Example: If transfer rate equals 110 bps, TxC=110 Hz (1x) TxC=1.76 KHz (16x) TxC=7.04 KHz (64x) The falling edge of TxC shifts the serial data out of the 8251A. e TxD (Output) This line is used to transmit the serial data. Serial output data on TxD is changed from paralled data to serial data in accordancae with the format specified by the Control Words. TxD line will be held in the marking state (‘1’ level) immediately on one of the following.s ° Master Reset ° Tx Disable (TxEN=0) ° CTS signal is high (CTS=1) ° TxEMPTY signal is high (TxEMPTY = 1) e TxRDY (Output) This output informs the MPU that the transmitter is ready to accept a Data Character. The TxRDY output pin can be used as an interrupt to the system, since it is masked by Tx Disable (TxEN =0), or, for polled Operation, the MPU can check TxRDY using a Status Read Operaiton. TxRDY is automatically reset by the trailing edge of WR when a Data Character is loaded from the MPU. The Tx RDY pin output status (Tx RDY (pin)) is different from the TxRDY status bit status (TxRDY (status bit)) as follows. TXRDY (status bit )=(Transmit Data Buffer Empty) TxRDY (pin) =(Transmit Data Buffer Empty) -(CTS=0) - (TxEN=1) ® TxEMPTY (Output) The TxEMPTY output will go “high” when the 8251A has no characters to send. It resets upon receiving as character from the MPU if the transmitter is enabled. eee MPU85-64

In Synchronous Mode, a*high” level signal on this output indicates that a Character has not been loaded and the SYNC Character or Characters are about to be or are being transmitted automatically as “fillers”. Tx EMPTY does not go “low” when the SYNC characters are being shifted out.

4.4 RECEIVE CONTROL SIGNLAS

e = RxC (Input) The Receiver Clock controls the rate at which the character is to be received. In Synchronous Mode, the Transfer Rate (1x) is equal to the actual frequency of RxC. In Asynchronous Mode, the Transfer Rate is a fraction of the actual RxG frequency. A portion of the Mode Instruciton selects this factor; 1, lhe or gg the RxC. For Example: if Transfer Rate equals 2400 bps, RxC=2.4 KHz (1x) RxC =38.4 KHz (16x) RxC = 153.6 KHz (64x) Data is sampled into the 8251A on the rising edge of RxC. e RxD (Input) This line is used to receive the serial data. Serial input data on this line is changed to parallel data in accordance with the format specified by the Control Words, and then transfered to the Receive Data Buffer. e RxRDY (Output) This output indicates that the 8251A contains a Data Character that is ready to be input to the MPU. RxRDY can be connected to the interrupt structure of the MPU, or, for Polled Operation, the MPU can check the condition of RxRDY using a Status Ready Operaiton. Rx Enable off both masks and holds RxRDY in the Reset Condition. eee MPU85-65

e SYNDET/BD (Input/Output) This pin is used for SYNDET in Synchronous Mode and may be used as eigher input or ourput, programmable through the Contorl Word. It is reset to output mode “low” upon RESET. When used as an Output (Internal Syne Mode}, the SYNDET pin will go “high” to indicate that the 8251A is programmed to use SYNC Character in the Receive Mode. If the 8251A is programmed to use Double Sync Characters then SYNDET will go “high” in the middle of the last bit of the second SYNC Character. SYNDET is automatically reset upon a Status Read Operation. When used as an Input (External Syne Mode), a positive going signal will cause the 8251A to start assembling Data Characters on the rising edge of the next RxC. In Asynchronous Mode this pin is used for BD. This output will go “high” whenever the receiver remains “low” through two consecutive Stop Bit Sequences (including the Start Bits, Data Bits, and Parity Bits). Break Detect may also be read as a Status Bit. It is reset only upon a Master Chip Reset or Rx Data returning to a “one” state. But, if the Rx data returns to a “one” State during the last bit of the next character after the Break, Break detect does not always reset. @ = Voc (Power) +5 Volt supply e GND (Power)

1. ELECTRICAL CHARACTERISTICS

5.1 MAXIMUM RATINGS

Power Supply Voltage (with respect to GND) | -0.5V to 7.0V Input Voltage (with respect to GND) Vout Output Voltage (with respect to GND) | Po _| Power Dissipation (Ta=70°C) Tsotder | Soldering Temperature (10 sec) | 260°C 50889 5.2 D.C. CHARACTERISTICS Topr = 0°C to 70°C, Vcc = 5V 5%, GND = OV, Unless otherwise noted. Inputlow Vohage | [05] - |os[v | Output High Voltage | Ion = —400na 24a] - [| -[v] [ep] [ec [rowersupsycurent_[atoupuwarashe] — | = | 100 | ma | 050489 5.3. A.C CHARACTERISTICS Topr = 0°C to 70°C, Vec = 5V + 5%, GND = OV, Unless otherwise noted. CS, C/D Set-up Time for RD 50 [me [Rruewam io | Data Delay Time for RD Note2) | C,=150pF Note3) - | - | 250 | ns | fe feesseree fp ‘50889 MPU85-67

5.3.2 Bus Write Cycle Timing Note 1)

5.3.3 Other Timing

SYMBOL PARAMETER Typ. | MAX. ] UNIT tye Clock PeriodNote 5), 6) [ 320] - | 1350 ty Clock High Level Width [ 140 | - |tye-90| ns | TxD Delay Time from Falling Edge of | torx —= - 1 Bs THC 1x,64x BaudRate | oc | - | 64 | fx Transmitter Input [76x Baud Rate oc | - | 310 | khz Clock Frequency 64xBaudRate | oc | - | 615 Transmitter input | tx Baud Rate fai -f - | t Clock High Level Transmitter Input | 1x Baud Rate [ isf - | - tree Clock Low Level teye Width 64xBaudRate | 3|{ - | - | ixBaudRate | pc | — | fax Transmitter input 76 ax BaudRate | DC | - | 310 | Clock Frequency Transmitter input | 1x Baud Rate [az{- | - | ‘tReH Clock High Level teye Transmitter Input | 1x Baud Rate | i[- | - | tet Clock Low Level teyc TxRDY Pin Delay Time from Center of 3 | toc [Note7 | teye TROY | Last Bit | TxRDY Clear Delay Time from Trailing t trxRDY CLEAR Edge of WR cyc | Note7 tesaoy | RARDY Pin Delay Time from Center of 24 | toe |Note7 is Last Bit RxRDY Clear Delay Time from Leading tRxRDY CLEAR Edge of RD teye | Note 7 I aya TI 7 | Internal SYNDET Delaya Time from - na | toe | Note7 | Rising Edge of RxC External SYNDET Set-Up Time fore tes _ | 16 teye | Note 7 Falling Edge of RxC | TxEMPTY Delay Time fromCenterof | trxeMPTY Last Bit 20 teye | Note? Control Delay Time from Rising Edge of WR (TxEN, BTR, RTS) 050489 MPU85-69

Note: 1) ACTest Conditions: Output measuring Point Vou=2.0V, VoL=0.8V Input supply level Vin=2.4V, Vi.=0.45V 2) Assumes that Address is valid before the falling edge of RD. 3) Cymeans load capacitance. 4) This recovery time is defined only for Mode Intialization. Write Data is allowed only when TxRDY =1. Recovery Time between Writes for Asynchronous Mode is 8 tcy and for Synchronous Mode is 16 tey. 5) TheTxC and RxC frequencies have the following limitations with respect to CLK: For 1x Transfer Rate, fry or fyx= 1/ (30tcy) For 16x and 64x Transfer Rate, fry or frxS 1/ (4.5tcy) 6) Minimum Reset Pulse Width is 6 tey. System Clock must be running during Reset. 7) Status up data can have a maximum delay of 28 clock periods from the event affecting the status. MPU85-70

cs | \\ TxEMPTY | j TxRDY 7 7 ¥ (PIN) er oo A) Ye | fy eo SH eee 8 " WR \\ NN | TxD ay A Ae F a4 ma pet . WY sdrdonabortarh J NOEECCCOCECEC MARKING DATA DATA SYNC SYNC_—=s«DATA = «DATA = MARKING BREAK = MARKING DATA — SYNCCHARAt STATE CHARA! CHARAT CHARA) CHARA2 CHARA3 CHARAG STATE STATE CHARAS SYNC CHARAZ EXAMPLE FORMAT 5 BIT CHARACTER WITH PARITY 2 SYNC CHARACTERS. 05049 Figure 6.8 Transmitter Control and Flag Timing (SYNC Mode) MPU85-74

‘SYN DET 4 7 | (sTatusam { wo LT i A WW WERHRXE ae L[ wrer[ | [Tt Dayat _ sTarus sratus__ |i status DATAD RD uy 4 4 RxD sce j os lam Ill en SYNC SYNC |) DATA DATA DATA SYNC SYNC |] pata ata cHaRat CHARA? | HaRal y CHARA? , CHARA? y CHARA! , CHARAZ HARAY | CHARA CHAR ASSY BEGINS | AxC y Y i SET SYNDET i EXIT HUNT MODE. SYNDET SETSYNDET (STATUS AIT) (STATYS BIT) EXAMPLE FORMAT: 5 BIT CHARACTER WITH PARITY 2 SYNC CHARACTERS. 0489 Figure 6.9 Receiver Controla nd Flag Timing (SYNC Mode) | MPU85-75

1. OUTLINE DRAWING (Dual Inline Package) DIP28-P-600 Unit : mm Fa 28 15 s ~ } ° is ¢ E 3s ty 1 14 3 37.020.2 $f | | 23 a

4 ARR j iH nalanaalat S14),

i f z ° 1.99TYP Note Lead pitch is 2.54m and to lerance is +25mm against theoretical center of each lead that is obtained on the basis of No.1 and No.28 leads. MPU85-77