Interface

TMP82C255AN

Toshiba Semiconductor

CMOS PROGRAMMABLE PERIHERAL INTERFACE

Manufacturer: Toshiba Semiconductor

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TOSHIBA TMP82C255A/TMP82C265B CMOS PROGRAMMABLE PERIPHERALINTERFACE —7-52-33-53 TMP82C255AN-2 / TMP82C265BF-2 TMP82C255AN-10 / TMP82C265BF-10 1. GENERAL DESCRIPTION AND FEATURES ‘The TMP82C255A/TMP82C265B is a CMOS high speed programmable input/output interface with six 8-bit I/O ports. The function is almost equivalent to TMP82C55A X 2. The TMP82C265B has the function that ports state are selectable immediately after reset by hardware either in input state or output state. The TMP82C255A has not this function. The TMP82C255A/TMP82C265B is fabricated using Toshiba’s CMOS Silicon Gate Technology. (1) 48 programmable I/O terminals (8 bit x 6 ports) | (2) The ports of TMP82C265B are capable to set to output after reset by hardware. (3) High Speed Version (TRD=100ns MAX : TMP82C255AN-10/TMP82C265BF-10) (4) Low power consumption 3mA. Typ. 10uA. MAX. (@5V stand-by) (5) ‘Three operation modes (Mode 0, Mode 1, Mode 2) (6) Bit set/reset capability (PCg9 to PCg7, PC to PC17) (7) All ports are capable of driving darlington transistors (8) Extended operating temperature : — 40°C to +85°C (9) Two packages TMP82C265BF 80 PIN Mini Flat Package MPU85-204

TOSHIBA TMP82C255A/TMP82C265B 2. PIN CONNECTIONS (TOP VIEW) TMP82C255AN-2/TMP82C255AN-10 z 2 é z a | 5 rr Oh s3sieu SSssssssurersnrrens f£¢ $8 caaeaeese ee eeee Sessa eee us OHO NAAN Aono ANNAN AAO AAA SESS SRRRBRARHAGRLGSS SV ISI SE IRARRAAR T Nee wonmosr neg BEh S2RaNRSRANRAaas CUDUUU UCU UU U UU ODO OU UUU ooo Sssssace@cssssosareesecr ene nensen P88 £ 0 PSSST IGS LEE EE EaB OSE GETS St z g z g TMP82C265BF-2/TMP82C265BF-10 aR <essseespetécs ONG On NAO NAA gaensusenreaehee SSRRRRSRARRSSSSS ncChi Oo 64,5 NC A, G2 63/51 D2 Ag 3 623 PCo7 4 61 NC PCog 5 60/1 Dg Ne Cle soo PCos 7 58E De PCo9 SD 56 |=] PBo7 PCo, 10 5551 PBog Pests sain NC 12 53 [51 PBos PCo3 3 52 Pps ncCh}i4 STI NC PAy7 Chis 50/71 PB93 Pare li6 mat ParsCl17 4855 Pp, nc Chie 47 PBo9 Pa l19 asEune PA;3 [420 45 Vcc pasa iste Pay Choe “ae PAyg 323 42> Pais Ne} 24 atFane RERARIHARSBBRASS CUUTUUOOUUUooooo Bas SSSI SSE osoms MPU85-205

TOSHIBA TMP82C255A/TMP82C265B 3. BLOCK DIAGRAM TMP82C255A OT z He) < inlie | i jee 2/2 NTViee : + SE 5 | g i 128 2hylyal | H 68 Gle ks a H 5 ed ) zZ H = TV le | 2 i et ! ke (ve)\\s8 23 2} Neve a2 5 ce 24 Slelpzinh. 2 2 NT |e= Z 3 ¢ ne | isi) & — as & ° << Ei Ww 2 H 8 i 8 2 EVENS i q H ke " lag <1 ey ak 7 iL /s3 <|S NTE - y Se 5 i 6 oo H OZ ce} U ' ° 1 z=£oO 4 Ee le | fe} 1 ° 1 < « : a 1 jo | 5 H i g i ; & 8 ' i g i : 3 | et S qa + a « la 2 5 9 cr Ko | ERODE Fi leg 2|/oN Ed ! SE 5 ' i o2 oto H A ZS & H Le i 8 Ne MPU85-206

TOSHIBA TMP82C255A/TMP82C265B TMP82C265B ooo 3 iS rayne 158 g|SNTVE yu i SE 5 i s : |2é2 gfelt i: 188 Jv Sle Kio) bs H IS g H a NTVE oO H H i @|rin|tes 2 kg t g 3g H 25 als ey ee i |S se ire Fe 1 (26 Sleolpinhe. & | 188 8/2 bg é Kk) ° |B Kua gg 2 ' oO a a H a a INT |e 3 i s i a} fo e < ee | rr i ask) 6 K7 ae Zz pyprr tonne nne| Z prea nnnnnnnancneccccncg, ie 19 < Exh 4 ia g 52 8 rolag <|S K 7 Pes al + Se aja Hi ja a ¥ Hi 26 2 1 a GO H oz fe} H a fe} H ae) e\\y LN ts 8 q 2 H O° Ol kz 3 : B oe < 2 : & INTY <q Z i i < ! i i o H H a = t { Z g i inthe E-—4 2 leg 2/5 Nive rd H Se 3 H al i |32 glean e ; 188 8/2 he i 8 ge H 9 NVR MPU85-207

TOSHIBA TMP82C255A/TMP82C265B 4. PIN NAMES AND PIN FUNCTIONS

7 Number | Input/Output

Pin Name | ean 3-state v0 3-state bidirectional 8-bit data bus. Used for data transfer with D7~Do astate | MPU. Also, used for transfer of control words to this device and status information from this device. PAg7~Paoo | @ | vo There are two 3-state 8-bit /O Port named PAO and PA1. Operation 3ettate | ode and input/output configuration are defined by software. Port PAi7~PAio | 2 | A contains the output latch buffer and input latch. | Pe07~Pe00 | 8 | vo There are two 3-state 8-bit /O Port named PBO and P81. Operation 3.state | Mode and input/output configuration are defined by software. Port PBy7~PBio 8 Acontains the output latch buffer and input latch. There are two 3-state 8-bit /O Port named PCO and PC1. Operation PCo7~PCog | 8 mode and input/output configuration are defined by software. Port vo can be divided into two 4-bit ports by the mode control and also, 3-state | used as the control signal for Port A and Port B. In this case, each 3 PCy7~PC49 bits of PCo9 to PCo2 and PCi9 to PC2 are used for Port B control and each 5 bits of PCo3 to PCo7 and PC}3 to PC17 for Port A control. Fas 1 Chip select input. When the terminal CSO is at “L" level, data transfer between BLOCK-0 and MPU is possible. And when the Input | terminal CS7 is at “L” level, data transfer between BLOCK-1 and a MPU is possible. At “H” level, the data bus is placed in the high cst impedance state and control from the processor is ignored. Ao, A Used for selecting Port A, 8, C and the control registers. Normally, ot this terminal is connected to low order 2 bits of the address bus. Read signal. Only the TMP82C265B has this terminal. When this : Input | terminal is at "L” level, data or status information in this device is transferred to MPU _ Write signal. Only the TMP82C2658 has this terminal. When this wR 1 Input | terminal is at “L” level, data or control word is written into this device from MPU. READ/WRITE signal. Only TMP82C255A has this terminal. When the terminal C30 or CST is at “L" level, if this terminal is at “H" level, RW 1 data or status information in this device is transferred to MPU. If this terminal is at “L" level, data or contro! word is written into this device from MPU. Only the TMP82C265B has these terminals. When SELo or SEL is a SElo “H" level, the ports are set to input state after reset, when it is a "L" Input level, the ports are set to output state after reset. if the terminals is P at “L" level, the function is only capable to set to output state in SEL mode 0. BLOCK-0 ports of block diagram is controled by SELo. BLOCK-1 ports of block diagram is controled by SEL}. When this terminal is at “H" level, all internal registeres including the control register are cleared, and the function turn out input RESET input __ [State in mode 0 for the TMP82C55A and TMP82C2658 with SELo or P SEL; “H" level. THe function turn out output state in mode 0 for the TMP82C265B with SELo or SEL; “L" level. Each BLOCK of TMP82C265B is capable to set to different mode by SELo and SELy 26009" MPU85-208

a TOSHIBA TMP82C255A/TMP82C265B TOSHIBA TPB 2c 255A/TIMPBZC?ESE Number | Input/Output [enone [amie [Smee | nn wv L_vss [1 [Powersupaly [6no os04e9 a MPU85-209

TOSHIBA (UC/UP) SHE D MM@ 9097249 0023045 ITT mMTOS3 TOSHIBA TMP82C255A/TMP82C265B 5. DESCRIPTION OF BASIC OPERATION

5.1 TMP82C255A FUNCTIONS AND FEATURES

‘The TMP82C256A is a programmable peripheral interface consisting of Block-0 and Block-1 each of which has 3 sets, total 6 sets of 8-bit ports (PAO, PBO, PCO, PA1, PB1 and PC1) each of which has 2 built-in control registers. Block-0 and Block-1 have the independent chip select input terminals CSO and CSi, respectivery. Data buses D7-Dg, address input terminals Ay and Ag, RESET input terminals, and R/W terminal are commonly used by Block-0 and Block-1. Read and Write functions are controlled by one R/W terminal and therefore, RD and WR signals and address must be synthesized and connected to the R/W, CS0 and CST terminals. ‘Total 24 ports input/output terminals each of Block-0 and Block-1 are divided into 12- bit group A and Group B. Group A consist of upper 4 bits of Ports A and Port C, while Group B consists of lower 4 bits of Port B and Port C. Each group is programmable independently by control word from MPU. Three operation modes are available; Mode 0, Mode 1 and Mode 2. In mode 0, it is programmable to use 28-bit input/output ports as | the input or output port independently. In Mode 1, the input/output ports are divided , into group A and Group B. In each group, 8 bits are used for the input or output port and the remaining 4 bits are used as the control signal. Mode 2 is applicable only to Group A and 12 bits are used for 8-bit two-way bus and 5-bit control signal. Further, when port C is used as the output port, any bit of port C can be set/reset. There are two control registers; one is used for mode setting and the other is used for bit seting/resetting. The control register cannot be read. Further, when the reset input becomes “H” level, the input/output internal registers are all reset and all the input/output terminals are placed in Mode 0 and input Mode (high impedance state). MPU85-210

a TOSHIBA (UC/UP) S4E D mM 9097249 0023046 036 MMTOS3 TOSHIBA TMP82C255A/TMP82C265B CBAC SAVTIMPB 262658 TMPZ84CO0A TMP82C255A Ao Ao a Ai PAK 7) "2 dress PT f-D 0 CO PBO om) Pco =) inne 5 _ a CST ES PAI k=» TORQ RD _ {> PBI =) RESET [>° RESET > —— a >, ny rs | Do Do 00489 Figure 5.1 Connecting example of TMPZ84CO0A and TMP82C255A In case of the TMP82C255, the read operation is controlled by the terminals CS0 or CSI when the R/W terminals is at “H” level and therefore, there is no AC electrical characteristics for rise and fall of the RD terminal but anf fall of the CSO or TSI terminal are controlled. ‘The write opertion is controlled by the terminal CSO or CSI when the R/W is at “L” level. Further, the maximum control of the setup time TWC of the OS0 or CSI for fall of RUW terminal and the hold time Twc of the CS0 or CST for the rise of B/W terminal is added. This is because the CSO or CSI terminal controls the read operation when the RWis at “H” level. eee MPU85-211

14097249 002304? 172 MMTOS3 TOSHIBA (UC/UP) S4yE D mm 9097249 0023047 T?e TOSHIBA TMP82C255A/TMP82C265B

5.2 TMP82C255A BASIC OPERATION

Basic operation of the TMP82C255A for BLOCK-0. PCO are as shown in Table 5.1. Table 5.1. Basic Operation for Block-0 of the TMP82C255A x 1 x | x | x | Settoall ports (six ports) input state in mode 0. Ports terminals are in High Impedance state. o} o | 0] 1 | 4 | DataBus << PBO o} o | 1] 0 | 14 | DataBus < Pco o | o | 0] 0 | 0 | PAo © DataBus o | o | 0] 1 | 0 | PBo © Data Bus o} 0 1 | 0 | 0 | Pco < DataBus o} o 1 | 1 | 0 | Control register for BLOCK-0 <~ Data Bus o} o 1 | 1 | 1 | Inhibition of combination 1 oO x x x Non active 050089 Basic Operation for BLOCK-1 of the TMP82C255A is equal to the one shown in Table 5.1. BLOCK-1 is selected when CS1=0. 5.3. TMP82C265B FUNCTION AND FEATURES The TMP82C265B can be set to general mode when the terminal SELp or SEL; is fixed at “II” level and to the output mode when it is fixed at “L” level. | In the general mode, the 'MP82C265B has the functions similar to those of the TMP82C55A but for the WR and RD functions, the independent RD and WR terminals are provided as in the former TMP82C255A unlike R/W 1 terminal in the TMP82C255A. Therefore, the TMP82C265B operates when connected in the same connecting method as before. In the output mode, all ports of the TMP82C265B are set in “L” output state in mode 0 after reset. Further, even when the write operation is made in any mode, the ports are set in output state in mode 0, and “L” level signals are output from the ports.

5.4 TMP82C265B BASIC OPERATION

Basic operation of the TMP82C265B in the general mode (the terminal SELo-SELy is “L” level) is equal to that of the TMP82C255A. Basic operation for BLOCK-0 of the TMP82C265B in the output only mode (SELg: “L” level) is as shown in Table 5.2. MPU85-212

S4uE D MM 9097249 0023048 909 MATOS3 TOSHIBA (UC/UP) TOSHIBA TMP82C255A/TMP82C265B Table 5.2 Output Mode Basic Operation for Block-0 of the TMP82C265B [Beef emo [neser [or [A [eo [RO [WR] ——Funcion—_———~d Set to PAO, PBO and PCO ports “L” level output state 0 x 1 x x x x x in mode 0 PAO, PBO and PCO ports "L” level output state in OPO] O | TPP] 1] 1 | © | pode oset command x 0 0 0 1 1 1 0 Bit set/reset control pay 0 0 x 0 oO 1 Oo PAO < Data Bus a t) oO x 0 1 1 oO PBO < Data Bus Aa 0 0 x 1 0 1 i} PCO < Data Bus Alo 0 x 0 0 0 1 | DataBus << PAO (Read the terminal state) Aa oO o x 0 1 it) 1 Data Bus © PBO (Read internal output latch) Aa oO 0 x 1 o 1) 1 Data Bus <_PCO (Read internal output latch) 050489 4: The output only mode is maintained when SEL. is either in “I.” or “H” level if set to the output state. However, if the RESET terminal is set to “H” level or mode is written when SELo is at “H” level, the output mode is changed to the general mode. Basic operation of the TMP82C265B for Block-1 is equal to that shown in Table 5.2 but the control is made by the terminal SEL, and CSI. ee MPU85-213

“TOSHIBA (UC/UP) 54E ) Mm 9097249 0023049 845 MMTOS3 TOSHIBA TMP82C255A/TMP82C265B 6. DETAILED OPERATIONAL DESCRIPTION The operation of the TMP82C255A and TMP82C265B in the general made is described in detail. Further, the operation is described for Block-0. Block-1 has the same functions as those of Block-0 and therefore, it is omitted. ‘The operation of the TMP82C265B in the output mode is considered to be a special case of the description for the general mode provided below, in which the TMP82C265B has been set in the output state in mode 0 from immediately after reset irrespective of command input and therefore, the description is omitted here.

6.1 MODE SELECTION

There are three basic modes of operation that can be selected by control words. Mode 0 - Basic I/O (Group A, Group B) Mode 1 - Strobe input/Strobe output (Group A, Group B) Mode 2 - Two-way bus(Port A only) . Operation modes for Group A and Group B can be independently defined by the control word from the MPU. If D7 is set to “L” in writing a control word into the PPI, on ) operation mode is selected, while of D7= “0” , the set/reset function for Port C is selected. a MPU85-214

“TOSHIBA (UC/UP) SHE D M™@ 9097249 0023050 Sb? M@TOS3 TOSHIBA TMP82C255A/TMP82C265B

6.1.1 Control Word to Define Operation Mode

Figure 6.1 shows the control words to define operation mode of the TMP82C255A/ TMP82C265B. Control Word [1 [eeu A consi [crop canvai | Lor | os [os | o« | os | o2 | oT oo | Input/output selection of low order 4 bits of Port C ‘0’ = Output ‘'sInput Input/output selection of Port B ‘0’ = Output "V's Input Mode selection of Group B ‘0’ =Mode 0 "V's Mode 1 Input/foutput selection of high order 4 bits of Port C ‘O's Output ‘"sInput Input/output selection of PortA ‘0 = Output ‘'=Input Mode Selection Group A ‘0'=Mode 0 Ds Ds 0 0 = Modeod = Designati 0 1 = Mode1 1= Designation of mode set flag ‘ xn Mode? x: Don'tcare osoas9 Figure 6.1 Control Word for Mode Selection MPU85-215

“TOSHIBA (UC/UP) SE D M@ 9097249 0023051 473 METOS3 TOSHIBA TMP82C255A/TMP82C265B

6.1.2 Port C Bit Set/Reset Control Word

Any bit of 8 bits of Port C can be set/reset by Port C bit set/reset contro! word. Figure 6.2 shows the Port C bit set/reset control word. Control Word Lor | os [os [o« [es [o | o [bo | . Bit setreset selection Don't care "QO" = Reset "1" = Set Bit set/reset flag [ Pcoo “0 = Active [Lo Jo | o | Poo [9 [0 [a | Pecos] | o | + | 0 | Poo] [o [1 {1 | Pcos| Bit selection [+ [0 | o | Poe | [0 [4 | Pos] [a [0 | coe | [1 [+ [recor 50289 Figure 6.2 Control Word for Bit Set/Reset

6.2 OPERATION MODES

6.2.1 Mode 0 (Basic I/O)

This functional configuration is used for simple input or output operations. No ‘handshaking’ is required and data is simply written to or read from a specified part. Output data to the ports from MPU are latched out but input data from the ports are not latched. In Mode 0, 24 I/O terminals are divided into four groups of Port A (8 bits) , Port B (8 bits) , high order 4 bits of Port C and low order 4 bits of Port C. Each port can be programmed to be input or output. The configuration of each port are determined according to the contents of Bit 4 (D4) , 3 (Dg) , 1 (Dj) and 0 (Do) of the control word for mode selection. The I/O configuration of each port in Mode 0 are shown in Table 6.2. MPU85-216

TOSHIBA (UC/UP) S4YE D MM 9097249 0023052 33T METOS3 TOSHIBA TMP82C255A/TMP82C265B Table 6.2 Port definition in Mode 0 oO 0 0 Qo Out Out Out Out oO Oo 0 1 Out Out Out dn oO oO 1 0 Out Out In Out oO 0 1 1 Out Out In In 0 1 oO 0 Out In Out Out oO 1 0 1 Out In Out In oO 1 1 oO Out In In Out oO 1 1 1 Out In In In 1 oO 0 0 In Out Out Out

1 Oo 0 1 In Out Out In

1 0 1 ) In Out In Out 1 oO 1 1 In Out In In 1 1 0 0 In In Out Out 1 1 0 1 in In Out In 1 1 1 0 In In In Out 1 1 1 1 In In In In sone

6.2.2 Mode 1 (Strobe /0)

In Mode 1, input/output of port data is performed in conjunction with the srtobe signals or ‘handshaking’ signals, Port C is used to control Port A or Port B. ‘The basic operatings in Mode 1 are as follows: © =~ Mode 1 can be set for two groups of Group A and Group B. © — Each group consist of 8-bit data port and 4-bit control/data port. © — The 8-bit data port can be set as input or output port. © — Thecontrol/data port is used as control or status of the 8-bit data port. (1) When used as the input port in Mode 1 : © — STB (Strobe Input) At “O” , input data is loaded in the internal input latch in the port. In this case, a control signal from MPU is not concerned and data is input from the port any time. This data is not read out on the data bus unless MPU executes an input instruction. ¢ IBF (Input Buffer Full F/F Output) When data is loaded in the internal input latch from the port, this output is set to “1”. IBF is set (“1”) by STB input being reset and is reset (“O”) by the rising edge of RD input. MPU85-217

TOSHIBA (UC/UP) SHE D M™ 9097249 0023053 27b mETOS3 TOSHIBA TMP82C255A/TMP82C265B ¢ _ INTR (Interrupt Request Output) Used for the interrupt process of data loaded in the internal input latch. When STB input is at “0” if INTE (INTE flag) in the PPI is in the enabled state (“1”) , IBF is set to “1”. INTR is set to “1” immediately after the rising edge of this STB input and reset to “0” by the falling edge of RD input. ‘The INTE flags of Group A and Group B are controlled as follows: INTEA - Control by bit set/reset of PCoq INTEB - Control by bit set/reset of PCo2 (2) When used as the output port in Mode 1: ¢ © OBF (Output Buffer Full F/F Output) ‘This is a flag which shows that MPU has written data into a specified port. OBF is set to becomes “0” at the rising edge of WR signal and is set to “1” at the falling edge of ACK (Acknowledge input) signal. e ACK (Acknowledge Input) ACK signal is sent to the PP1 as a response from a peripheral device that received data from the port. ¢ — INTR (aterrupt Request Output) When a peripheral device received data from MPU, INTR is set to “1” and the interrupt is requested to MPU. If ACK signal is received when INTE flag is in the enable state, OBF is set to “1” and INTR signal becomes “1” immediately after the rising edge of ACK signal. Further, INTR is reset at the falling edge of WR signal when data is written into the PPI by MPU. The INTE flags of Group A and Group B are controlled as follows: INTEA - Control by bit set/reset of PCog INTEB - Control by bit set/reset of PCy2 MPU85-218

"TOSHIBA (UC/UP) SHE D M@ 9097249 0023054 102 METOS3 TOSHIBA TMP82C255A/TMP82C265B MODE 1 (PORTA) controLworo PAor~ Poa jo Oy 05 Ds Ds 03 2 D1 Do | fe egal STOR [1 To[s]s fuof Tx Te] | p= APcos}-> wea se Wt Po6, PCor _ U INTRA =| Oeouirut Ad or 1 = INPUT PCo6~ PCoa 1/0 MODE 1 (PORT B) INTR: t contRot woRo 8) ~ P89 Jer? D / 7~ Pg or

07 Bg 05 Dy 05 02 D1 Oo |THE Gb SE

EUEIEIEIET CORES be rs ORT (a) (a wed fecgg}—> INTRE w osotes Figure 6.3 Example of Strobe Input in Mode 1 MODE 1 (PORTA) CONTROL WORD PAg7 ~ PAgg |e Dy Dg Ds D4 Ds Ds Ds Do [Pcug| > O8FR (Lo Jo [vol x [xT] ear we PCoq, PC {Pcq3}-—> INTRA onF Seton weed Lea ORF ) |

12 INPUT Poe ~ PCa eB 0 _

MODE 1 (PORT 8) | CONTROL WORD PBo7 ~ PBoo b> 8 INTR Dy Dg Ds Dy D3 Dz Dy Do one EEESEIEAEI NES) elle ack® ——pogp outur__X_ w—vd [_)fecag} > intra sous Figure 6.4 Example of Strobe Output in Mode 1 MPU85-219

TOSHIBA (UC/UP) SHE D M@ 9097249 0023055 045 METOS3 TOSHIBA TMP82C255A/TMP82C265B PAo7~ Pago | Pho ~ PAgy oe Wi—~d PCoy |» OBFA, Rd PCog —STER CONTROL WORD PCog |< ACKA CONTROL WORD PCos (BFA, Dy Dg Ds Dg Dy Dz Oy Dp PCs» INTRA DD Ds Dg D3 Dz Di Do PCo3 [> INTRA EE Cots [i fof fo [x] PCo4~ PCgs 1/0 C97 ~ PC og > 1/0 Poa Pos a a PCo6, Poy Boy ~ PB fo | t= Inpur RO—> PCop [x —ST8B 1 INPUT |= WR—>d Poy }-» OBFB | Poy F> 18FB PC a2 ACRE . Cag | INTRE Poo INTRB PORT A- (STROBE OUTPUT) PORT A- (STROBE INPUT) PORT B - (STROBE INPUT) PORT B - (STROBE OUTPUT) osoaee Figure 6.5 Example of Port A Qutput, Figure 6.6 Example of Port A Input port B Input in Mode 7 Port B Output in Mode 1

6.2.3 Mode 2 (Strobed Bidirectional Bus I/O)

In this mode, Port A is used as 8 bits bidirectional bus for data transfer with a peripheral device. This mode is applicable only to Group A, which consists of an 8-bit bidirectional bus (Port A 8-bit) and 5-bit control signals (high order 5 bits of Port C). The bidirectional bus (Port A ) has both the internal input and output registers. When group A is set in Mode 2, Group B can be set independently. There are 5 control signals as follows when Group A is used in Mode 2. . OBF (Output buffer Full F/F Output) When MPU writes data into of Port A, OBF is set to “0” to inform a peripheral device that the PPI is ready to output data. However, Port A is kept in the floating (high impedance) state until ACK input signal is received. ¢ KCK (Acknowledge Input) When ACK signal is set to “0”, the data of the 3-state output buffer of Port A is send out. If ACK signal is at “1”, Port A is in the high impedance state. © STB (Strobe Input) When STB input is set to “0”, the data from peripheral devices are held in the input latch. When the active RD signal is input into the PPI, the latched input data are output on the system data bus (D7-Do). MPU85-220

pe erggaug mneanca ACA MMTOCR *OSHIBA (UC/UP) SE D MM@ 9097249 0023058 858 METOS3 TOSHIBA TMP82C255A/TMP82C265B

6.2.4 Precautions for use in Mode 1 and 2

When used in Mode 1 and 2, bits which are not used as control or status in Port C can be used as follow. Ifporgrammed as the input, they are accessed by normal Port C read. Ifporgrammed as the output, high order bits of Port C (PCo7-PCo4) are accessed using the bit set/reset function. As to low order bits of Port C (PCo3-PCop), in additions to access by the bit set/reset function, 3 bits only can be accessed by normal writing.

6.3 READING PORT C STATUS

When Port C is used as the control port, that is, when Port C is used in Mode 1 or Mode 2, the status information of the control word can be read out by a normal read operation of Port C. Table 6.3 Status Word Format of Port C Pome Toff [=[ofapale| MPU85-223

. - re a OSHIBA (UC/UP) SHE D MM@ 9097249 0023059 794 MMTOS3 TOSHIBA TMP82C255A/TMP82C265B 7. ELECTRICAL CHARACTERISTICS

7.1 ABSOLUTE MAXIMUM RATINGS

7.2 DC ELECTRICAL CHARACTERISTICS

TOSHIBA (UC/UP) SHE D MM@ 9097249 0023060 40b METOS3 TOSHIBA TMP82C255A/TMP82C265B 7.3. CAPACITANCE TA=25°C, Vec=Vss=0V fae] [mom Dom [oe fom P| is ee oxo (*): All terminals except that to be measured should be earthed.

7.4 AC ELECTRICAL CHARACTERISTICS (1/2)

TA= ~40°C to +85°C, Voc = 5V + 10%, Vss = 0V symbol parameter Unit me —_ | min. [ max | ain. " [oem [RB pukewas vr = | mo] | oe | Delay from RD fall to decided data output | — [140] = | 100[ ns | [tor _| Time from RD rise to data bus floating | o[ ao] of ao] ns | [aie tonics tonee Roa _| an] — [wo] — [oe | two _[Busdata holding time for WR rise [20] - | 2| = | os | twa _ | Delay from WR rise to decided data output [| = | 350] = | 350] ns | tes |Port data set-up time for STB rise [20] - |: 20] — | ns | | tao __[Delat from ACK fall to decided data output Delay | — | 300| — | 300] ns | Time from ACK rise up to port ‘ko | Port in Mode 2) floating 25] 250 250 ‘won [Delay from WR rise to OBF Tal = [eo [= [0 | RektanwowFree | =| a0] = fmf | caoHes MPU85-225

TOSHIBA (UC/UP) manana. e - 54E D ao Mm 9097249 oo23061 342 METOS3 TOSHIBA ‘TMP82C255A/TMP82C265B AC ELECTRICAL CHARACTERISTICS (2/2) symbol Parameter - Unit a [rosy rom Actrietonrran [| s00f — | 00 | tat [Delay from ACK rise to INTR rise | 350] — | 350] ns a [aso — [0 | tac _ [Address set-up time for C50, GSI fall [| o| - | o| — | os Delay from C50, Giifalltodecideddataoutput_ | — | 140] — | 100[ ns | ‘ore [Time from€50, GSirse todata busfloating | | 40 | 0] a0] Tew _ |@0, Giset-up time for R/W fall | | o| Twe _ | C50, GSI holding time for RAV rise | =| so] — | so] ns | tic _| Port data set-up time for CSO, CSI fall [of —| of —| os | [ie fPorsetehouing unetores6,csss | of — [0] | m | [es fRsetputewan ao — mo] — [| 050889 Note 1: A-2_ : TMP82C255AN-2, TMP82C265BF-2 A-10 ; TMP82C255AN-10, TMP82C265BF-10 Note 2: Following AC specifications of TMP82C255A are applied to the logical AND timing between R/W terminal and CS0 or CSi terminal. Two 050009 Note 3: ACMeasuring Point Input Voltage Vyy=2.4V, Vi.=0.45V Output Voltage Vor =2.2V, Vo =0.8V CL=150pF. MPU85-226

TOSHIBA (UC/UP) SHE D MM 9097249 0023062 289 METOS3 TOSHIBA TMP82C255A/TMP82C265B 8.1. TMP82C255A TIMING DIAGRAM (1) MODE 0 INPUT OPERATION RAW) tec CSO, CST t ty INPUT t t Au Ao te tore MODE 0 OUTPUT OPERATION ts RW tew t CSO, CST - . tww or tcc R/W and 7 (C50 or C51) ==" D7~Do a a a At, Ao ee a ourPuT | twa ‘sos Figure 8.1. TMP82C255A Timing diagram (1) MPU85-227

TOSHIBA (UC/UP) SSE) mm g - > mm 40 97249 0023063 115 mTOS3 TOSHIBA TMP82C255A/TMP82C265B MODE 1 INPUT OPERATION te: tes INPUT PORT DATA __ go STB tsip. IBF tsit tor top INTR v og CSO, CST RIM MODE 1 OUTPUT OPERATION t t wo ce ow we — ns R/W t twos tarr INTR = OUTPUT PORT DATA 4 tas OBF RE a : Figure 8.1. TMP82C255A Timing diagram (2) MPU85-228

TOSHIBA (UC/UP) S4E D MM 9097249 0023064 051 MNTOS3 TOSHIBA TIMP82C255A/TMP82C265B MODE 2 BIDIRECTION OPERATION tyyy RW snr, INTR ro | a twos taos | | tak AK t _ {$$ 318 tsa \\BF + ton | teow twe, sO, CST tec 50089 Figure 8.1 TMP82C255A Timing diagram (3) MPU85-229

TOSHIBA CUC/UP) SHE D M@ 9097249 0023065 T98 mmTOS3 TOSHIBA TMP82C255A/TMP82C265B

8.2 TMP82C265B TIMING DIAGRAM (1)

Csi, Cs0 At Ao Dy~D9 ---- een ee ---- tro t MODE 0 OUTPUT OPERATION t wR — WR Dr~Do ee At, Ao ourrur [>*X twa Figure 8.2 TMP82C265B Timing diagram (1) MPU85-230

TOSHIBA (UC/UP) SHE D MM 59097249 0023066 924 mETOS3 TOSHIBA TMP82C255A/TMP82C265B MODE 1 INPUT OPERATION tes t INPUT PORT DATA tst = jo STB tsip IBF tsir «tk ti INTR i eg RD a MODE 1 OUTPUT OPERATION _ pj WR K. two, t tar INTR OUTPUT PORT DATA twe ‘taos OBF Ne ir Figure 8.2 TMP82C265B Timing diagram (2) MPU85-231

TOSHIBA (UC/UP) SHE D MM 9097249 0023067 860 MMTOS3 TOSHIBA TMP82C255A/TMP82C265B MODE 2 BIDIRECTION OPERATION tw WR tsit, INTR ooo ‘wos; taos. tak =" ye ACK 4 af PERIPHERAL = ----{___}---+----- : tsr St canEEEEET pa STB x. j tsip IBF i+-———— So RD 4 Figure 8.2. TMP82C265B Timing diagram (3) MPU85-232

TOSHIBA (UC/UP) SHE D MM 9097249 0023068 777 METOS3 TOSHIBA TMP82C255A/TMP82C265B 9. OUTLINE DRAWINGS SDIP64-P-750 = Unit : mm | ad he —— q p = i b —— q h — i b — 4 q h SS q h =—! q h q bi

5 SS q b

—j o i b — Fa q i => Pa q b a 3 q b E =) is q f §S q p 2S i b a q b => i b EI a q hi i q b Sj i b = i b —> q b —= q b SS i - SS sq pe | T 2892 |__mat02 || g.simin 30203 0.25 “th or~15° e028 Note: Each lead pitch is 1.78mm, All leads are located within 0,25mm of their trve longitudical position with respect to No.1 and No.64 leads. MPU85-233

TOSHIBA (UC/UP) S4E D MM 9097249 0023069 433 miTos3 TOSHIBA TMP82C255A/TMP82C265B QFP80-P-1420B Unit : mm 23.8203 20.0+0.2 64 a HAA ARAARAARAAARRBARAAARL = HAHAHA AE ee Ss ”O”~”:CSCS a0 Co 25 TTT TTT TTT TTT OOOO AOU OO OOOO OO Oooo HUOUUEUOUDOUDOUDOUO OULD 1 2a [os] _srsgnegncan (000 sot Hl 170880 MPU85-234

Product Information

TMP82C255AN specifications and overview.

Summary

CMOS PROGRAMMABLE PERIHERAL INTERFACE

Description

CMOS PROGRAMMABLE PERIHERAL INTERFACE

Source title TMP82C255AN Datasheet(PDF) - Toshiba Semiconductor

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