TMP8251AP

TMP8251AP TOSHIBA | Alldatasheet

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PROGRAMMABLE COMMUNICATION INTERFACE TMP8251AP 1. GENERAL DESCRIPTION The TMP8251AP is the industry standard Universal Synrnronons/Asynchoronous Receiver/Transmitter (USART) that is fabricated using N-channel silicon gate MOS technclogy. The TMP&2514 is mainly used for &-bit microcomputer extension systems, which require serial data communications. The TMP82514P is packaged in the 28pin standard Dual Inline package.

FEATURES

® = Synchoronous: 5-8 Bit Characters Internal or External Character Synchronization Single or Double Charaeter Synchronization (Internal) Automatic Sync Insertion ° Asynehrongus: 5-8 Bit Characters Clock Rate ~ 1, 16 or 64 Times Transfer Rate Break Character Generation 1,11, or 2 Stop Bits Palse Start Bit Detection Automstic Break Detect and IIandling e Tranufer Rate DC te 64K bps (Synchronous) TDC to 19.6K bps (Asynchronous) . Full-Duplex, Double-Ruffered, Transmitter and Reeejver ¢ Error DetectionParity, Overrun and Framiog ¢ = Single +5¥ Supply . Compatible with Intel's 8251A/S2657 MPU8S-41

1. PIN CONNECTIONS (TOP VIEW) put Sto b3 G2 27 Ro RxD G3 26 = vee ono 4 25 [5 axc m 5 24 Dr 2s G8 23 RTs De C? 2p osm by C8 2110 RESET me a9 200 © WE 10 WE TxD 3 4u 18 TxEMPTY eB 412 wh os RD 33 16 SYNDET:BD RRDY C1 1S TARDY 3. BLOCK DIAGRAM . ‘a secawipsta’ YT L_) ~2ANSPAMT vat BUFFER BLTFER TxD Dy + t a PS} b A= Satusnaa 4 a BUFFER Leet Os - inansnart 27 TARDY Dy rm Tal MPTY Ds IKANS WIT DATA CONTROL — Tre dg <1 SUFFER . Dy wee |< — ! j | corrmane BAe —V ls meceveurer |] + . Pest RESET + p> BeRDY CuK RIAD: WRF —) RECEIVE os SYNDET/ED CONTRO CONTROL > (RHC a = teste | Wr a) —_! RIS m 2 Mose ~ i — I— CIS vec : . 7 SR GND INTERNAL L. DATA BUS Mpuss-62

1. PIN NAMES AND PIN DESCRIPTIONS 4.: INTERFACE SIGNALS TO VIPU (MAIN SYSTEM) » 19~D¢9 inpr-vOueput] This 3-state bidirectional, 4-bit buffer is used to interface the 82514 to tae system Dava Bus. Data is Lransmilted or received through the buffer upon exécuLion of Input or Ourput Insuruclions of the MPU. Ccontrol Words, Command Words and Status Information are also transfered through the Data Bus Buffer. @ | WR inpet) A “iow” level signal on this input inZerms the 82514 that the MPU is Writing Data or Control Words to the 82514, ° RD iInpu:} A “low” iovel signal on this input informs the 8251A that che MPU js Reading Data or Status Information from the 82514. =e = CSilnput) A “lox” level signal on <kis input selects the 8252A. No reading or writing operation wil! occur unless the device is sclected. When 5 is “high” the Data Bus is in the floating state and RD and WR have oo effeet on the chigs. * GD inpar)s This ixput signal, in conjunction with the WR and RD inputs, infurme the $2514 Lhat lhe word un Lhe Data Bus is #ither a Data Characler, Contre! Word or Status Information. A “high” level signal means Control or Status, a “low” level signal means Data. cB RD WR cs f I 1 fl 82514 Recieve DATS Buller Nata Bus a 7 o q 82514 Transmit DATA Butter — Daca Bus . 0 1 a BZSTA Status DAIA Buffer >Data Bus 5 1 i Q 82514 Command DATA Buffer< - Data Bus x 1 1 a BAMA Basis in floating state. x x x 1 ‘ MPU85-63

¢ CLK (Input) The CLK input is used to generate internal device timing. No external input or output is referenced lo CLK, but the frequency of CLK must be greater than 30 times tke Receiver oy Transmitter Data Bit Rates (RaC or Tx) in Synchronous Operation, and greater than 4.5 limes the Receiver Duta Bil Rated (RxC) in Asynchronous Operation. ° RESET (Input) A “high” level sigaal on this imput forces tne 826A into an “Idle” mode, The device will remain at "Idel” untill a new set of Control Words is written into the 82514 to program its functional definition. Mirimum RESET pulse width is 6 tcy. 4.2 MODEM CONTROL SIGNALS. « DER dnput) The DSR input signal is a generat purpose, I-bit inverting input port. Its condition can be tested by the MPU using a Status Read Operation. The DSR input is normlaly used lo test MODEM eondizions such as Data Set Ready signal. ° DTR(Outputt The DTR output signal is a general purpose, 1-bil inverting autpet port. It can be sct “low” by programming the appropriate bit in the Command Instsruczion Word. The DTR output signa! is normally used for MODEM control such as Data Terminal Ready or Rate Select signal. e = RTS (Output; . ‘The TEES output signal is a gcncral purpose, 1 bit inverting output port. It can be set “low” by programming the appropriate bit in the Command Instruction Word. The RTS ouput signal is normally used for MODEM control such an Request to Send signal. e = CTS tinput) A “low” level signal on this input erables the 8251A to transmit serial data, if the Tx Enable Bit in the Command Byte is set 10 a “one” (TxEN=1}. Ifeither a Tx Enable off (TxEN=0) or CTS off (CTS=1) condition occurs while Lhe Ta is in operation, the Tx will transmit al. the data in the USART, written prior to Tx Disable Command before shutting down. MPU85-64

4.3. TRANSMIT CONTROL SIGNALS © = TxCdinput} The Transmitter Clock Coutrals the rate at which the character is to be ‘ransmitted. In tae Synchronous Transmission Made, the trans‘er rate (1x) is equal to the TxC frequency. In Asynchronous Transmission Mode, the transfer rale is a fraction of the actnal TxC frequency. A poriton of the Mode Instruction selects this factar, it can be 1, 1/yg or Ligg the TxG. For Example: If transfer rate equals 110 bps, TxC=110 H2(x) Tx = 1.76 KHz (16x) TxC = 7.04 KTlz (64x) The falling edge of TxC shifts the serial data out of the 82514, * TxD (Output) This line is used to transmit the serial data. Serial output data on TxD is changed from paralled data to seria” data in accordancae with the format specified by the Control Words. TxD line will be held in the marking state (‘1° Level}-immediately on one of the followings + Master Reset ° Tx Disable (TxEN =0) * CTSsignalishigh(CTS=1) © TxEMPTY signal ig high (TxEMPTY=1) ° TxRDY {Output} This output informs the MPU that tke transmitter is ready to accept a Data Character. The TxRDY au‘put pin can be used as an interrupt to the sysvem, since itis masked by Tx Disable (xEN =D}, or, for polled Opera:ion, the MPU can check TxRDY using a Status Read Operaiton. TxRDY is automatically reset hy the trailing edge of WR when a Data Character is loaded from the MPU. Tae Tx RDY pin output status (Tx RTDY (pin}) is different from the TxRDY status bit status (TxRDY (status biti) as follows. TARDY (status bit }=(Transmit Data Buffer Empty} TxRDY (pin} «(Tranamit Data Bufler Empty) - (CTS=0) : iTxEN=1} e TxEMPTY (Oulput) The [x2MPTY output will go “high” when the 8251A has na characters to send. It resets wpon receiving as character [rom the MPU if the transmitter is enabled. MPUBS-65

Ir Synchronous Mode, a*high” level signal on this output indicates that a Character has rot been loaded and the SYNC Character or Characters are absut to he or are being transmitted automatically as “filers”. Tx EMPTY does not z0 “low” when the SYNC characters arc being shifted out. 4A RECEIVE CONTROL SIGNLAS . RxC (laput) The Receiver Clock controls the rate at which the character is to be received. In Synchronous Mode, the Transfer Rate (1x} is equal te the actual frequency of ExC, In Asynchronons Mode, the Transfer Rave is a fraction of the actual RC frequency. A portion of the Mode Instruciton selects this factar; 1, 1/1g¢ or lg4 the RxC. For Example: if Transfer Rate equals 2400 bps, RaC=2.4 KHz (ix) Rx =38.4 KHz (16x) RxC = 153.6 KHz (64x) Dats is sampled into the 32514 on the rising edge of RxC. ® RxD input} This line is used ta receive the serial data. Serial input date on this line is changed to parallel data in accordance with the format specified hy the Control Words, and then transfered 10 the Receive Data Buffer. ® RxRDY (Output) ‘This output indicates that the 8251A contains a Data Character that is ready to be input to the MPU. RxRDY can be connected to the interrupt struccure of the MPU, or, for Polled Operation, the MPU can check the condition of RaRDY using « Status Ready Operaiton. Bx Enable off both masks and holds RxKUY in the Reset Candition. MPUBS-66

e SYNDET/BD {{nput/Output) This pun is used for SYNDET in Synchronous Mode and may be used as eigher input or onrput, programmable through the Contorl Word. It is reset to output. mode “low” upon RESET. When used az an Output (Internal Syne Mode), the SYNDEY pin will go “high” to indicate that the 8251A is programmed to use SYNC Character in the Receive Mode. If the 82514 is programmed to use Double Syne Characters then SYNDET will go “high” in the midéle of the last bit of the second SYNC Character. SYNDET is automatically reset upon a Status Read Operation, When used as an Input (Exteroul Syne Model, a positive going signal will cause the 8251A to start assembling Data Characters on the rining edge of the next RxC. In Azynchronqus Mode this pin is used for BD. This output will go “high” whenever the receiver remains “low” througa two cuasecutive Stap Rit Sequences {including the Start Bits, Date Bits, and Parity Bits), Break Detect may also be read as a Stams Bit. It is reset only upon a Master Chip Reset cr Rx Data returning toa “one” state. But, if the Rx date returns to a “onc” State during the last 9it of the next character afler the Break, Break detect does not always reset.

4.5 POWER SUPPLY

« Yec (Power) +5 Volt supply . GND :Power)

0 Volt supply

1. ELECTRICAL CHARACTERISTICS 5.1. MAXIMUM RATINGS Vee | Power Supply Voltage (with respect tc GND) | -0.5v to 7.0¥ Vin | Input Voltage with respect to GND) =O 8Vt0 7.04 Vour | Output Valtage (with respect 20 GND} =0.5¥ 10 7.0¥ Po Power Dissipation (Ta = 70°C) | Ww Tsalder | Soldering Temperature (10 sec} | 260°C Teta. : Storage Temperate - 55°C to 150°C Top: _| Operating Temperature OC to 70°C 52 D.C, CHARACTERISTICS Topr = 0°C to 70°C, Vec = 5V + 5%, GND = OV, Unless atherwise noted. Prec rw [ recon [| [oe Vu Input Low Voltage -05] - | 08 ‘n__ Inputle . Vin___| Input High Voltage 22] - | vec Output low Valiage | 1o.=2.2mA - | - [oa] v Output Hign Vo tage lon = — AUC aA ral - - v lon | GutpurteakCurrent [oasvevour=ver | - | - | #10! nA he input wak Currert | O4SVE Vine Vee - FL | sto pa [tcc | Powersupply Current | allOuiputs=“High” | - , — | 109 | ma

5.3 AC CHARACTERISTICS

Topr = 0°C to 76°C, Ver = SV t5%, GND SOV, Unless otherwise noted.

5.3.1 Bus Read Cycle Tim'ng — Note 11

| tar | 6S, GiB Setup Time for RU ; sol - | - | «| | tea__| 65. CDHold Time far RO sol thr RD Pulse Width to Data Delay Time forRD wie | Ci=150pF \\ote2! : ¢S, CD Set-up “ime for FO [10 | MPUs5-68

5.3.2 Bus Write Cycle Timing Note 1)

twa | C5, GiB Hots Teme for OR [ep pe | tw _ | WH Pose wich ; “a50[ — 1 [ms | tow _| Data Set Up Time for wR so] - | - | ns | two | Data Hold Time for WH re ee sy__| RecavaryTime aetweenwwares fume | 6] = |= I tae | . MPUBS-69

5.3.3 Other Timing

SYMEGL PARAMETER Typ. Max. | UNIT tye Clock Periadhote 5), 6) [320 [= 30 [ns | tu Clock High Leve! Width 140 f — “ye-90 | ns | in Clock Low Leve Width ; wl] - | - Clack Rise anc Fall Time | - | [20 | TxD Delay Tire from Falling fdge of 1 lors Txt . ~~] 1x, 6% BaudRate | oc | - | 64 fa i Tranemitter Input 16x Baud Rate pe | ~ | Clock Frequency FT aud Rate . Trensmiteae Input | 14 Baul Rate - ; tTPH Glock High Level 75 Gas Baud Rate - or | Transmitter mpat_| 1x Baud Rate | - [| - |. low Level | = eye tre | Flock Low Level | ax Baud Rate aj - | - |* 1x Baud Rate * 0¢ 64 fre Transmitter Input [78 eax Saud Rave Ot. 310 | kaz lock Fr y - Transmitter Input | 1xBaud Rate vi - | tRPH | Cieck High Level Tove ‘Width 64x Baud Rate 1| -_| Transmortter Input 1x 3aud Rate 15 [ - | ter. Clock bow Leve | ——— teye ‘Width 64x Baud Rate 3 . TxRDY Psn Delay Time from Center of i §rxRov . j- | - tox | Note 7 Last Bil _ Io. TeRDY Clear Delay Time from Trai ing | a ot = 7B | tye | mote? ‘tRaRDY CLEAR Edge of WR _ | ; ~ RaXDY Pin DelayTime from Center of : | i ARDY Pin DelayTime from a ~ os aa | tye | Note? Last Bit A _ RxaDY Clear Jelay Time from Leading ‘ — - | es 6 tee [ Note? tRaRDY CAR kdge of AD i sf Inte‘nal S¥YNDET Delaya Time from: . Note? — fey ts Rising Edge of Sat a4 Exc I SYNE Set-Up Time fore tes meena) ere ~ tye | Note 7 Falling Edge of Rac . TxEMP “Y Desay Time from Center of x . tee | Note 7 tTeEWPTY Last Bit A © "T contro Delay Time from Rising Edge & Note? we of WR {TxEN, DIR, R2$) ter TAR, CTS Set-Up Time tor RD oe ee ee ce Mpuas-70

Rote: 1) ACTestCond:tiuns: QutputmeasuringPoint Von=2.0V. VoL=O.8¥ Input supply level Viu=2.4¥, Vir=0.45V 2) Assumes that Address is valid before the falling ede of RD. 4) Cy, means load capacitance 4) This recovery time is def-ned only fur Mare Intisliaatior:, Write Data is alluwed uly when TxRDY=1, Recovery Time between Writes for Asynchronous Mode is 8 tey and for Synchronous Mode is 16 icy. 5) The TxC and RxC frequencies have the fulluwing limitations with respec; to CLK; For 1x ‘Transfer Rate, fr, or fyx = 1 (30tey) For 16x and 64x ‘Lransfer Rate, fp, or Igy 1/ (4.ftey) 6) Minimure Heset Pulse Width is 6 tey. System Clock must be running during Keset. 7) Status op dala car have a maximum delay of 28 ¢lock periods from the ovent alfecting the stars. MPUBS:71

— twee “ 4 ts Kee DATA BUS DON'! CARE DATA FLOATING {INPUT DATA) Dara STABIE Law st twa ci ‘ | fay Figure 6.4 Write Data Cycle (MPU—8251A) RxRDY ‘treRDY CLEAR ox tar : RD i] . tap ul [wor +

7 ATA FLOATING

DATA BUS DATA FLOATING ae ae DATA FLOATING (OUTPUT DATA) taR tre tar tra rad Figure 6,5 Read Data Cycle (8251A—MPU) MPU85-73

i. ey ee xEMPTY | | TaRDY iPM) ow Ay be a fy | WA DA py peeatar J prnecras | bur perce TS Zong Lraganw SVR DATAS i “0 M 4 H a ADAPARORRASAASSSSSCORACANI I IACC CEE CS! BESCRAR IROL MARKING CIA DATA SYNC SYC DATA ATA MARKING © REBK —-M@PKING DATA SYNC CHARAT ‘STATE CHAE) THAjat TeaRS' rrahay CHAReT CuetAe —STSTE STe"E CARAS. SwwtcHana? EXANPLE 7DRMAT: —§ BIT CHARACTER WITH PARITY 2 SYNC CHARACTERS Figure 6.8 Transm:tter Control and “lag Timing (SYNC Mode} MPUBS-75

SYMDET INTERNAL SYNC “TT cae AL a re noi a oes "mi TT <B ee i= rr a Gt [UE Winn ne PF nes a aL Tete Hh Us BaTAs | STapUS L t Rone had CEEESSISERCLEDSEO DAIS ICCORCKOSOISOLORECCCOOSTICERSRRC ROC OSALCE CETL OU EA Sim Sync |) ogra DATA. DATA. SYNCS DATA DATA HAMAD Ora? Lelovama” , CHARAD | CHARAT 5 CHARI, Cmanas HARAY , CHaRe? we SNL Ti seroncerisenen — geareson) EXAMPLE FORMAT; = 5 BIT CHARACTER WITH PARITY 2 SYNC CHARACTERS. . Figure 6.9 Receiver Controla nd Flag Timing (SYNC Mode) MPUa5-76

TxR2¥ t F GTATLS! r i i (PIN) RDATA\\ WR DATA Peo To ow PRY A Py ee peed WWRTEN i I fae ee } ‘

0 SS E-LALRGCRREPPLSRORSOGEP® WEEE he sp

SKANPLEFDAMAT: 7.8" CHAMACTER & 2 STOP BITS Rote! TxHDy WIN) = UU rwmual Date Buller 's exopty)-(TxXEN = 13: (CTS—0i TARDY (STATUS KIT} — Cresta Date Buffer is empty? Figure 6.10 Transmitter Contral and Flag Timing (SYNC Made) B3 Pinth ed DATA2 ssrerusem 4 Lost iy tReRDY : I RxKOY { BDATAI \\ aa | 1 co pS Oey SE | ee Fa " pea Oa i fxd —— WEE GRRRBE =" LA0RRGR RGR SiPRRER GE DATA DATA DATAS SOLTS ASH PAT? EXAMPLE FORMAT: 7 BIT CHARACIER K 2 SIUF IIS, Figure 6.11 Receiver Control and Flag Timing (ASYNC Mode) MPU8S-77

1. OUTLINE DRAWING (Dual Inline Package} DIP28-P-600 Unit: mm ‘ 37,020.2 ES Ne LR AI TE A ss 8 H | lato. 520.19 . . ae bg sate see err crea SDE) Nota: Lead pitgh is 2.542 and to Jerance is +25-om ageinat theoretical center of exch lead that is ebtained on the basis of No.1 and No.Z8 leads, eee | . MPUBS-78 |