TMP8155 TOSHIBA | Alldatasheet
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256 BYTE STATIC RAM WITH I/O PORTS AND TIMER
- GENERAL DESCRIPTION The TMP8155/8156P-2 are RAM including I/O ports and counter/timer on one chip for using in the TLCS-85A microcomputer system. The RAM portion is designed with 2K bit static memory cells organized as 256 x 8. The 14 bit programmable counter/timer is the down counter. It provides either a square wave terminal count pulse for the MPU system depending on timer mode. The I/O portion consists of 2 programmable 8 bit I/O ports and 1 programmable 6 bit VO port. The programmble I/O ports can be operated by BASIC MODE and STROBE MODE. 2. FEATURES . Single +5V Power supply . Access Time: 330 ns . Internal Address Latch e 2 Programmable 8 bit I/O Ports and 1 Programmable 6 bit I/O Port . 256 x 8 bit RAM e Programmable 14 bit Binary Counter/Timer e Multiplexed Address/Data Bus e Chip Enable Active High (TMP8156P-2) or Low (TMP8155P-2) e 40 pin DIP MPU85-26
$$ SSSsSsSSSssSSSsSSsSsesesesesee er 5. PIN NAMES AND PIN DESCRIPTION e@ RESET (INPUT) The Reset signal is a pulse provided by TMP8085A to initialize the system. Input high on this line resets the chip and initializes the internal three I/O ports to input mode. The width of RESET pulse should typically be two clock cycles of TMP8085A. @ ~~ AD 9~7 (INPUT/OUTPUT, 3-STATE) These are 3-state Address/Data lines that interface with the MPU lower 8-bit Address/Data Bus. The 8-bit address can be applied to the memory section or the 1/O section depending on the polarity of the IO/M input signal. 8-bit data is either written into or read from the TMP8155/8156 depending on the status of WR or RD input signal. @ = CEORCE (INPUT) Chip Enable : On the TMP8155P-2, this pin is CE and is Active Low. On The TMP8156P-2, this pin is CE and is Active High. e RD (INPUT) Input low on this line with the Chip Enable active enables the ADg~7 buffers. If IO/M pin is low, the RAM content will be read out from the ADo~7 bus. Otherwise the content of the selected I/O port or command/status register will be read out from the ADg~7 bus. e = =WR(INPUT) Input low on this line with the active CE/CE causes the data on the ADg~7 lines to be written to the RAM or I/O ports and command/status register depending on the polarity of IO/M. e ALE (INPUT) Address Latch Enable : This control signal latches both the data on the ADy~7 lines and the state of the Chip Enable and IO/M into the chip at the falling edge of ALE. e = I0/M (INPUT) 10/Memory Select : This line selects the memory if low and selects the I/O or command/status register if high. e@ = PAg~7 (INPUT/OUTPUT, 3-STATE) These 8 pins are general purpose I/O pins. The in/out direction is selected by programming the Command Register. SSS MPU85-28
e@ = =PBo~7 UNPUT/OUTPUT, 3-STATE) These 8 pins are general purpose I/O pins. The in/out direction is selected by programming the Command Register. @ = =PC9~5 INPUT/OUTPUT, 3-STATE) These 6 pins can function as either input port, output port, or as control signal for PA and PB. Programming is done through the Command Register. When PC g~5 are used as control signals, they are defined as the following : PCO-AINTR (Port A Interrupt) PC1- A BF (Port A Buffer Full) PC2- A STB (Port A Strobe) PC3 - B INTR (Port B Interrupt) PC4-B BF (Port B Buffer Full) PC5 - B STB (Port B Strobe) ° TIMER IN (INPUT) This is the input to the counter-timer. e = TIMEROUT (OUTPUT) This pin is the timer output. This output can be either a square wave or a pulse depending on the timer mode. ° VCC (Power) +5 volt supply e VSS (Power) Ground Reference | MPU85-29
- FUNCTIONAL DESCRIPTION
6.1 PROGRAMMING THE COMMAND REGISTER
The command register consists of either latches. Four bits (0-3) define the mode of the ports, two bits (4-5) enable or disable the interrupt from port C when is acts as control port, and the last two bits (6-7) are for the timer. The command register contents can be altered at any time by using the I/O address XXXX000 during a WRITE operation. The functions of each bit of the command register is shown in Figure 6.1 Note that the command register is a write-only register and can not be read. x = Don'tcare AD7__AD6_ ADS ADS ADS AD2_—AD1_—ADDO. oye t=Logic "1 COMMAN 0=Logic “0” recister | [M2 | Ti [| IEA PC2 Pct | | PA DEFINE PAg.7 4 = INPUT DEFINE PBo.7 t 1 = OUTPUT | 00= MODE 1 01=MODE 3 10=MODE4 ENABLE PORTA INTERRUPT O= ENABLE i ENABLE PORTS | |= DISABLE INTERRUPT [ 00=NOP- DO NOT AFFECT COUNTER | OPERATION | 01 = STOP - NOP iF TIMER HAS NOT STARTED; STOP COUNTING IF THE TIMER IS RUNNING 10 = STOP AFTER TC - STOP IMMEDIATELY AFTER PRESENT TC IS REACHED (NOP TIMER COMMAND: iF TIMER HAS NOT STARTED 11 = START - LOAD MODE AND COUNT LENGTH AND START IMMEDIATELY AFTER LOADING (iF TIMER IS NOT PRESENTLY RUNNING). IF TIMER IS RUNNING, START IMMEDIATELY AFTER PRESENT TC IS REACHED. 50489 Figure 6.1 Command Register Bit Assignment ee MPU85-30
6.2 READING THE STATUS REGISTER
The status register consists of seven latches, one for each bit ; six (0-5) for the status of the ports and one (6) for the status of the timer. The status of the timer and the I/O section can be polled by reading the Status Register (Address XXXX000). Status word format is shown in Figure 6.2. AD7 ADs ADs ADa_ ADs, AD? ~— AD) ~—ADo commanol\\_ TIMER iNTE BF INTR INTE | BF INTR REGISTER ~~. B 8 B A lA A PORT A INTERRUPT REQUEST i PORT A BUFFER FULL/ EMPTY. | (INPUT / OUTPUT) PORT A INTERRUPT ENABLE | PORT B INTERRUPT REQUEST PORT B BUFFER FULL / EMPTY (INPUT / OUTPUT) PORT B INTERRUPT ENABLE TIMER INTERRUPT (THIS BIT IS LATCHED HIGH WHEN TERMINAL COUNT IS REACHED, AND IS RESET TO LOW UPON READING OF THE C/S REGISTER AND BY HARDWARE RESET) 050489 Figure 6.2 Status Register Bit Assignment MPU85-31
6.3. VOSECTION e COMMANDSSTATUS REGISTER (C/S) — Both registers have the same address XXXXX000. When the C/S registers are selected during WRITE operation, a command is written into the C/S Register. The contents of this register are not accessible through the pins. When the C/S is selected during a READ operation, the status information of the I/O ports and the timer becomes available on the ADpo~7 lines. e PA Register — This register can be programmed to be either input or output ports depending on the status of the contents of the C/S Register. Also depending on the command, this port can operate in either the basic mode or the strobed mode (See timing diagram). The I/O pins assigned in relation to this register are PAg.7. The address of this register is XXXXX001. e —-~PB Register — This register functions the same as PA Register. The I/O pins assigned are PBo.7. The address of this register is XXXXX010. e PC Register — This register has the address XXXXXO11 and contains only 6-bits. The 6-bits can be programmed to be either input ports, output ports or as control signals for PA and PB by properly programming the ADg and ADs bits of the C/S Register. When PCp.5 is used as a control port, 3-bits are assigned for Port A and 3 for Port B. The first bit is an interrupt that the TMP8155/8156 issues. The second is an output signal indicating whether the buffer is full or empty, and the third is an input pin to accept a strobe for the strobed input mode. See Table 6.2. When the port C is programmed to either MODE 3 or MODE 4, the control signals for PA and PB are initialized as follows : 050489 MPU85-32
To summarize, the register’s address assignments are shown in Table 6.1. Table 6.1 I/O Port Addressing Scheme 1/O ADDRESS SELECTION NO. OF BITS [x[x[x|x[x[ ©] 0] 0) intemal | command’ status Register rs [x |x [x] x][x foo]: | PAo.7 General Purpose I/O Port A | 8 [x[x{x|x][x]oj}a fo! PBo.7 General Purpose |/0 Port B | 8 [x [xx [xp xo [a [a] er | GeneralPurpose sO Portorconver | 6 | Defebebe bch ToL | Trsrenierativortinercount | | 050489 Table 6.2 Port Control Assignment PCO | InputPort | Output Port AINTR (Port A Interrupt) AINTR (Port A interrupt) PCI InputPort | Output Port ABE (Port A Buffer Full) A BF (Port A Buffer Full) PC2 Input Port Output Port ASTB (Port A strobe) ASTB (Port A strobe) PC3_ | InputPort | Output Port Output Port B INTR (Port B Interrupt) PC4 | InputPort | Output Port Output Port B BF (Port B Buffer Full) Pcs Input Port Output Port Output Port B STB (Port B strobe) 050089 eee MPU85-33
6.4 TIMER SECTION
The timer is a 14-bit down-counter that counts the ‘timer input’ pulses and provides either a square wave or pulse when terminal count (TC) is reached. The timer has I/O address XXXXX100 for the low order byte of the register and the I/O address XXXXX101 for the high order of the register. To program the timer, the COUNT LENGTH REGISTER is loaded first, one byte at a time, by selecting the timer addresses. Bits 0-13 will specify the length of the next count and bits 14-15 will specify the timer output mode. The value loaded into the count length register can have any value from 2H through 3FFFH in bits 0-13. Lm | m [ ts [te [ti [to | ts | te J Lo TIMER MODE MSB OF COUNT LENGTH LSB OF COUNT LENGTH 050489 Figure 6.3 Timer Format There are four timer modes which are defined by M2 and M1. M2 Mi 0 Q ——— Put out low during second half of count. 0 1 ——— Continuous square wave; The period of the square-wave equals the count length programmed with automatic reload at terminal count. 1 0 ———— Single pulse upon TC being reached. 1 1 ———— Continuous pulses. Note: In case of an odd-numbered count, the first half-cycle of the square-wave output, which is high, is one count longer than the second (low) half-cycle as shown in Figure 6.3. MPU85-34
Is |@|sjetsjsleis [ao fs| TIMER IN | M2 M1 00 a ee o a ee es Oe oe 1 0 es a A L_ d wid wll osoaea Figure 6.3 Asymmetrical Square-Wave Output resulting from Count 5 Bits 6-7 ([M2 and TM1) of command register contents are used to start and stop the counter. There are four commands to choose from; TM2 TMI 0 0 NOP : Do not affect counter operation. 0 1 STOP: NOP if timer has not started; stop counting if the timer is running. 1 0 STOP AFTER TC : Stop immediately after present TC is reached. a (NOP if timer has not started) 1 1 START : Load mode and count length and start immediately after loading (if timer is not presently running). If timer is running, start the new mode and count length immediately after present TC is reached. Note that while the counter is counting, a new count and mode can be loaded into the count length registers. Before the new count and mode will be used by the counter, a START command should be issued to the counter. This applies even though only the change of the count is required in the previous (same) mode. The counter in the TMP8155/8156 is not initialized to any particular mode or count when hardware RESET occurs, but RESET does stop the counting. Therefore a START command must be issued via the C/S register, because counting cannot begin following RESET. eee MPU85-35
Note that the timer circuit on the TMP8155/8156 chip is designed to be a square-wave timer, not an event counter. To achieve this, it counts down by two twice in completing one cycle. Thus, its registers do not contain values directly representing the number of TIMER IN pulses received. Counter value ‘1’ can’t be loaded as the initial value into the count register because the timer operates as its terminal count value is 10 (binary). After the timer has started counting down, the values residing in the count registers can be used to calculate the actual number of TIMER IN pulses required to complete the timer cycle if desired. To obtain the remaining count, the following operations should be done in order: 1. Stop the count. 2. Read in the 16-bit value from the count length registers. 3. Reset the upper two mode bits. 4, Reset the carry and rotate right one position all 16 bits through carry. 5. Ifcarry is set, add 1/2 of the full original count (1/2 full count—! if full count is odd.) Note: When the initial count value is odd and the third count pulse has not come yet, it will be unknown whether one or two counts has occurred. Regardless of this, the TMP8155/8156 always counts out the right number of pulses in generating the TIMEROUT waveforms. MPU85-36
eee P8155 /8 156, 7. ELECTRICAL CHARACTERISTICS
7.1 ABSOLUTE MAXIMUM RATINGS
[ro [rowerusinaion ft Pw 930089 7.2 D.C. CHARACTERISTICS TA =0°C to + 70°C, Voc = +5V 45% [vi [eputtowvanage [~~ os | ae | [vw [inputichvoroge [zo |veewos pv [von Jouputtighvakage owe 00a | 24 | - | v fu nwutietage |vwaveewoov | - | 20 | aa | [io [tout teatage cuvent|0a5vsVoursver | - | #0 | va [icc veesvoaiycurent [| =| 00) ma] po Fee ew [Tele] I lic (CE) 8155 Vin = Vcc to OV. +100 pA 8156 -100 pA 030889 MPU85-37
7.3 A.C. CHARACTERISTICS TA =0°C to + 70°C, Vec = + 5V 45% [tar [Addressto latch sewptime | 50 | [ns Lis —astres tid tmesigrines ——} 30-1] [tue [Latch to READ /WRITE Control [a0 [= [ne | txo [Valid Date out Delay rom READ Control [— | 740 [ns | [tao [Address StableTo Data Out valid | — | 330 | ms | [uc [eaten Enabiewigth TO |e | | teor [Data Bus FloatatterReAD ———+| 0 | 80 | s_| [sci __[READ/WARITE Control Latch Enable [10 | — | ne | [icc [READ/WRITE Controiwidts | -300 [= [re [ tow [Data intowRITESewup Time | 100.) = | ns_| [two _[DatainHoldTimeaferware | O | = | ms | | tay [Recovery Time etween Contra [700 | — [ns | [tex _[PortinputSewup Time ——~|—so f = ne | [iss __[Stobewieth SS [| | trae [READ tobufferempty | (| 300 |e | tror[StobetonTrore Y= | 300 | s_| [ tnss_[PorSetupTimetoswobe «| 20 | — | as | [ins [PortHoid Time afterstobe «| “TOO | — | ns | | tsee [Sober Buffertmpty | | 300 | as [twee fwRiTetoBufferrul «| (| 300 | ns [tw [wrtetointRo Tf 300 | [i [TMERINtoTIMEROUTLow «| — | 300 | ve | [tn [TIMER-INtoTIMEROUTHigh «iT — | 300 [ns | | teoe _[DataBus Enable from READ Control | 10) — | ns_| [uu [TIMERINTowTime aT | [te [TIMERINHigh time) 0 oe | tere [CKGderenod «200 [= | [ete [eiKRiseandralttime | | 80 | [ie EAI ancoing TH? T= Lo 730509 Notes: 1. Test conditions CL=150pF 2. Timing defining signal voltage are ; Output High level =2V, Low level =0.8V MPU85-38
- OUTLINE DRAWING (40Pins Plastic Package) DIP40-P-600 Unit: mm 40 2t vi SSS ° = Py om] [eS 38 - ge i 20 3 50.7402 wa ee “Pa WUT ooo nnn oy thm it) ) 2 ° —— 5-13 = * 1.22TYP y4201 lessor grey 3 2.54 270289 Note: Each lead pitch is 2.54mm, and all the leads are located within +0.25mm from their theoritical positions with respect to No. 1 and No. 40 leads. Sanne MPU85-41