TMP8039PI-6

TMP8049PI-6 TOSHIBA | Alldatasheet

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TECHNICAL DATA TMP8049PI-6, TMP8039PI-6 8-BIT SINGLE-CHIP MICROCOMPUTER GENERAL DESCRIPTION The TMP8049PI-6, from here on referred to as the TMP8049, is a single chip microcomputer fabricated in N-channel Silicon Gate MOS technology which provides internal 8-bit parallel architecture. The following basic architectural functions of a computer have been included in a single chip; an 8-bit CPU, 128 x 8 RAM data memory, 2K x 8 ROM program memory, 27 I/O lines and an 8-bit timer/event counter. The TMP8049 is particularly efficient as a controller. If has extensive bit handing capability as well as facilities for both binary and BCD arithmetic. The TMP8039PI is the equivalent of a TMP8049 without ROM program memory on chip. By using this device with external EPROM or RAM, software debugging becomes easy.

FEATURES

+ 2.5 uS Instruction Cycle + 128 x 8 RAM + All instruction 1 or 2 cycles - 27 1/0 lines . Over 99 instructions; 70% single byte . Interval Timer/Event Counter + Easy expandable memory and 1/0 + Single level interrupt + 2K x 8 masked ROM + Single 5V supply 40°C to +85°C Operation PIN CONNECTIONS (Top View) To qh 40b vec (45v) xTALL G2 39 11 XTAL2 G3 385 P27 RESET G4 37B P26 53 ds 36B Pos nT 6 35B Pay Fa G7 34 P}7 RD ds 33D Pig SER go 32B Pys wR G10 31B Pi, ALE Gi 306) P13 pBo G2 29P Pho DB; G33 28D Pi; pBy G14 27D Pio pp 35 26B Vyp(4sv) DB, G16 251 PROG Bs G17 24B Po vB, G8 23 Poo DB7 G19 22D Poy covy¥ss 420 21P P59 —733—

TECHNICAL DATA TMP8049PI-6, TMP8039PI-6 BLOCK DIAGRAM DBo~DB7 ProcPi PagrP27 Port O Port 1 Port 2 Buffer Buffer Buffer ist

7 Ty of | (} ay f} 4

Oscillation ny T Dotpue Output 2 : uepal utp utpu IK x 8 (reogran Area) Cireuie an ccumo=] [Tenpo-] [— RAM Adres I Fli : ator | frary Reg} [7285 Enstruc} | PSH) | eeeister J ‘ion Re-| [| aM ik gister/ \\ccunul a: Timer 64 « B tor Latc Decoder Flag In Fl | carry Bit Test Conditional Jump Circuit: To oT) RT Control and Timing Circuit XTAL, XTAL; RESET INT EA 53. ALE PSEN AD WR proc v rj y 7 y 4 J Note 1) The lower order 4 bits of port 2 output latch are 3? ees ee 2 snen Bb ae used also for input/output 32 43823 8 F Begg § a3 operations with the 1/0 25 822 $2 @ ec 8 3 Bre naa $4 8 S$2o8 Ss expander. a5 a3 F FRET 4 FE B g £ sho gh" s F CE g 27 erg gs g Note 2) The output latch of port 0 ° ae ee Es is also used for address output. —734—

TECHNICAL DATA TMP6049PI-6, TMP8039PI-6 PIN NAMES AND PIN DESCRIPTION VSS (Power Supply) Circuit GND potential VDD (Power Supply) +5V during operation Low power standby pin for TMP8049 RAM VCC (Main Power Supply) +5V during operation PROG(Output) Output strobe for the TMP8243P 1/0 expander P10-P17 (Input/Output) Port 1 8-bit quasi -bidirectional port (Internal Pullup=50k2). P20-P27 (Input/Output) Port 2 8-bit quasi-bidirectional port (Internal Pullup=50k®). P20-P23 Contain the four high order program counter bits during an external program memory fetch and serve as a 4-bit I/O expander bus for the TM?8243P. DBO-DB7 (Input/Output, 3 State) True bidirectional port which can be written or read synchronously using the RD, WR strobes. The port can also be statically latched. Contains the 8 low order program counter bits during an external progran memory fetch, and receives the addressed instruction under the control of PSEN. Also contains the address and data during an_external RAM data store instruction, under control of ALE, RD, and WR. TO (Input /Output) Input pin testable using the conditional transfer instructions JTO and JNIO. TO can be designated as a clock output using ENTO CLK instruction. Tl (Input) Input pin testable using the JT1 and JNT] instruction. Can be designated the event counter input using the timer/STRT CNT instruction. INT (Input) External interrupt input. Initiates an interrupt if interrupt is, enabled. Interrupt is disabled after a reset. Also testable with conditional jump instruction. (Active Low) RD (Output) Output strobe activated during a Bus read. Can be used to enable data onto the Bus from an external device. Used as a Read Strobe to External Data Memory (Active Low). WR (Output) Output strobe during a Bus write (Active Low) Used as a Write Strobe to External Data Memory. —735—

TECHNICAL DATA TMP8049PI-6, TMPBO39PI-6 RESET (Input) Active Low signal which is used to initialize the Processor. Also used during Power down. ALE (Output) Address Latch Enable. This signal occurs once during each cycle and is useful as a clock output. The negative edge of ALE strobes address into external data and program memory. PSEN (Output) Program Store Enable. This output occurs only during a fetch to external program memory (Active Low). SS (Input) Single step input can be used in conjunction with ALE to "single step" processor through each instruction when SS is low the CPU is placed into await state after it has completed the instruction being excuted. EA (Input) External Access input which forces all program memory fetches to reference external memory. Useful for emulation and debug and essential for testing and program verification. (Active High). XTAL 1 (Input) One side of crystal input for internal oscillator. Also input for extern- al source. XTAL 2 (Input) Other side of crystal input. FUNCTIONAL DESCRIPTION 1. System Configuration The following system functions of the TMP8049 are described in detail. (1) Program Memory (6) Stack (Stack Pointer) (2) Data Memory (7) Flag 0, Flag 1 (3) 1/0 Port (8) Program Status Word (PSW) (4) Timer /Counter (9) Reset (5S) Interrupt Control Circuit (10) Oscillator Circuit (1) Program Memory The maximum memory that can be directly addressed by the TMP8049 is 4096 bytes. The first 2048 bytes from location 0 through 2047 can be internal resident mask ROM. The rest of the 2048 bytes of addressable memory are external to the chip. The TMP8039 has no internal resident memory; all memory must be external. —736—

TECHNICAL DATA TMP8049PI-6, TMP8039PI-6 There are three locations in Program Memory of special importance. Aderess 4095, | | Memory Bank 1 2048 5}

2087 LLZZZZ/ 7

2087 Yillde

y Internal R Menory Bank 0 ALLL Wh AZ Z| Program Memory Area + Location 0 Activating the Reset line of the processor causes the first instruc- tion to be fetched from Location 0. + Location 3 Activating the interrupt line of the processor (if interrupt enabled) causes a jump to subroutine defined by address held in Location 3. + Location 7 A timer/counter interrupt resulting from a timer/counter overflow (if enabled) causes a jump to a subroutine defined by address held in Location 7. . Program address 0-2047 and 2048-4095 are called memory banks 0 and 1 respectively switching of memory banks is achieved by changing the most significant bit of the program counter (PC) during execution of an unconditional jump instruction or call instruction executed after using SEL MBO or SEL MB. Reset operation automatically selects Bank 0. (2) Data Memory + Resident Data Memory (volatile RAM) is organized as 128 words by 8-bits wide. «The first 8 locations (0 -7) of the memory array are designated as working registers and are directly addressable by several instructions. By executing a Register Bank switch instruction (SEL RB1) locations 24 - 31 are designated as the working registers in place of 0 ~ 7. —737—-

TECHNICAL DATA TMP8049PI-6, TMP8039PI-6 Address 127 Data Memory 31[Resister Bank 1

24 RB]

8 Level Stack

8 C yte)

7{Resister Bank 0 oO RBO Internal Data Memory Area + RAM locations 8 - 23 serve a dual role in that they contain the program counter stack which is a stack 2 bytes wide by 8 levels deep. These locations store returning addresses from subroutines. If the level of subroutine nesting is less than the permitted 8, you free up 2 bytes of RAM for general use for every level of nesting not utilized. + ALL 128 locations are indirectly addressable through either of two RAM Pointer Registers which reside at RO and RI of the Register array. + The T8049 architecture allows extension of the Data Memory to 256 words. (3) Input /Output Ports + The TMP8049 has 27 1/0 lines which can be used for either input or output. These I/O lines are grouped into 3 ports each having 8 bidirectional lines and 3 "test" inputs which can alter program sequences when tested by con- ditional jump instructions. + Ports 1 and 2 are each 8-bits wide and have identical characteristics. Data written to these ports is statically latched and remains unchanged ustil rewritten. As input ports these lines are non-latching, i.e., inputs must be present until read by an input instruction. + All lines of Ports 1 and 2 are called quasi-bidirectional because of a special output circuit structure (illustrated in Figure 1). Each line is continously pulled to a +5V level through a high impedance resistive device (50k2 ) which is sufficient to provide the source current for a TTL high level yet can be pulled low by a standard TTL gate thus allowing the same pin to be used for both input and output. In order to speed up the "0" to "1" transition a low impedance device (5k ) is switched in momentarily whenever a "1" is written to line. When a "0" is written to line a low impedance device overcomes the pullup and provides TTL current sinking capability. —738—

TECHNICAL DATA TMP6O49PI-6, TMP8039PI-6 ANL, ORL 2 +5V 45 Internal Bus’ D i {) Si Detype 7] 50k2 1/0 pins Flip-Flop Lyortl or 2 aK a Write Pulse Inter Buffer IN Figel Input/Output Circuit of Port 1, Port 2 - Reset initializes all lines to a high impedance "1" state. + When external data memory area is not addressed during excution of an internal program, Port 0 (DBO - DB7) becomes a true bidirectional port (bus) with associated input and output strobes. If bidirectional feature not needed Bus can serve as either a statically latched output port or 4 non-latched input port. However, 1/0 lines of this port cannot be intermixed. + As a static port data is written and latched using the OUTL instruction and inputted using the INS instruction these two commands generate pulses on the corresponding RD and WR strobe lines. . As a bidirectional port the MOVX instructions are used to read and write the port which generate the RD and WR strobes. + When not being written or read, the Bus lines are in a high impedance state. (4)Timer /Event Counter . The 8-bit binary up counter can use either of the following frequency inputs (1) Internal clock (1/480 of OSC frequency) seteeeeeeees Timer mode —739—

TECHNICAL DATA TMPGO49PI-6, TMPBO3OPI-6 (2) External input clock form Tl terminal (minimum cycle time 3 x ALE cycle) seeeeeaeesees Event Counter mode The counter is presettable and readable with two MOV instructions which transfer the content of the accumulator to the counter and vice versa, The counter content is not affected by a Reset and is initialized solely by the MOVT, A instruction. The counter is stopped by a Reset or STOP TCNT instruction and remains stopped until started by START T instruction or as an event counter by a START CNT. Once started the counter will increment to its maximum count (FF) and overflow to Zero continuing its count until stopped by a STOP TCNT instruction or RESET. The increment from maximum count to Zero (overflow) results in the setting of an overflow flag and the generation of an interrupt request. When interrupt acknowledged a subroutine call to Location 7 will be initiated. Location 7 should store the starting address of the timer or counter service routine. The state of the overflow flag is testable with the conditional JUMP (JTF). The flag is reset by excuting a JTF or by RESET. Figure 2 illustrates the concept of the timer circuit. Timer Overflow Flag 1/32 ip- XTAL/15— Flip-Flop Pre-scaler Cleared on Stert Timer F Ins on srer t JTF Inst ructior o 8-Bit Timer/ STOP TCXTO Counter STRI CNT Timer Interrupt Request Flip-Flop dee Detector Read/Write Enable a [ Timer Interrupt Enable Fig.2 Concept of Timer Circuit —740—

TECHNICAL DATA TMP6049PI-6, TMP8O39PI-6 mF s Conditional Jump Logic Instruction Timer Flog F+F Timer Overflow SO s a Timer Interrupt Overflow ein Reset RETR PEE] | Instrucz|y Zo = | tion nee Ts) pin} ) | Inter- | | Font iid i__rxternal inter ALE [> mk OG ij CLK |rupt Recognized oii q TH b pent Last eycle i Timer interrupt of Instruction ii Recognized i! cL EXT sey Ii Instruction JS 2 _CfES TTT sg er | | Et Instruction} i Execution ef Inter= aed bE | rupt Call Instruction zE4 Reet REEL REEa Reset _# vis a! ee ced DIS TCNTL netruction Instruction Fig.3 Concept of Interrupt Control Circuit (5) Interrupt Control Circuit . There are two distinct types of Interrupts in the TMP8049. (1) External Interrupt from the INT terminal (2) Timer Interrupt caused by timer overflow -741—

TECHNICAL DATA TMP8O49PI-6, TMP6039PI-6 The interrupt system is single level in that once an interrupt is detected all further interrupt requests are ignored until execution of an RETR (which should occur at the end of an interrupt service routine) reenables the interrupt input logic. . An interrupt sequence is initiated by applying a low level "0" to the INT pin. INT is level triggered and active low which allows "Wire Oring" of several interrupt sources. The interrupt level is sampled every machine cycle during ALE and when detected causes a "jump to subroutine” at Loca~ tion 3. As in any call to subroutine, the Program Counter and Program Status Word are saved in the stack. » When an overflow occurs in the internal timer/event counter an interrupt request is generated which is reserviced as outlined in previous paragraph except that a jump to Location 7 is used instead of 3. If INT and times overflow occur simultaneously then external request INT takes precedence. + If an extra external interrupt is needed in addition to INT this can be achieved by enabling the counter interrupt, loading FFH in the counter (one less than the terminal count), and enabling the event counter mode. A "I" to "0" transition on Tl will cause an interrupt vector to Location 7. + The interrupt service routine pointed to be addresses in Location 3 or 7 must reside in memory between 0 and 2047, i,e., Bank 0. Figure 3 illustrates the concept of the interrupt control circuit. (6) Stack (stack Pointer) + An interrupt or Call to subroutine causes the contents of the program counter to be stored in one of the 8 register pairs of the Program Counter Stack. The pair to be used is determined by a 3-bit stack pointer which is part of the Program Status Words (PSW explained in section (8)). Data RAM locations, 8 through 23 are available as stack registers and are used to store the program counter and 4-bits of PSW as shown in the figure. + The stack pointer when initialized points to RAM location 8 and 9. The first subroutine jump or interrupt results in the program counter contents being transferred to Locations 8 and 9. Then the stack pointer is incre- mented by one to point to Locations 10 and 11. Eight levels of subroutine are obviously possible. + At the end of a subroutine signalled by a RET or RETR causes the stack pointer to be decremented by one and the contents of the resulting pair to be transferred to the Program Counter. —742—

TECHNICAL DATA TMP6049PI-6, TMP8039PI-6 6 2 5 19 4 7 3 15 2 13 T rey 1 ! i 10 Psh | PCBS of are | 9 PCA 7 1 PCO 8 Stack RAM Pointer . Address (7) Flag 0, Flag 1, oF). Fl) + The TMP8049 has two flags FO and Fl which are used for conditional jump. These flags can be set, reset and tested with the conditional jump instruction JFO. + FO is a part of the program status word (?SW) and is saved in the stack area when a subroutine is called. (8) Program Status Word (PSW) . An 8-bit status word which can be loaded to and from the accumlator exists called the Program Status Word (PSW). The PSW is read by a MOV A, PSW and written to by a MOV PSW, A. The information available in the PSW is shown in the diagram below. —743—

TECHNICAL DATA TMP8O49PI-6, TMP8039PI-6 Stack Pointer ic jac _IFo [Bs ii_{s2 [si fso0_| MSB od LSB itt Saved in stack area Spare ("1" during Read) at the time of Sub- routine Call. Bits 0 - 2 : Stack Pointer Bits(S0, Sl, $2) Bit 3 : Not used ("1" level when read.) Bit 4 : Working Register Bank Switch Bit (Bs) 0 = Bank 0 1 = Bank 1 Bit 5 : Flag 0 (FO) Bit 6 : Auxiliary Carry (AC) carry bit generated ty an ADD instruction and used by the decimal adjust instruction DA, A (AC) Bit 7 : Carry (C) flag which indicates that the previous operation has resulted in the accumulator. (c) (9) Reset + The reset input provides a means for initialization of the processor. This Schmitt trigger input has an internal pullup registor which in combination with an external lyF capacitor provides an internal reset pulse sufficient length to guarantee that all internal logic is initialized. RESET 1yF T —744—

TECHNICAL DATA TMP6O49PI-6, TMP8039PI-6 If the pulse is generated externally the reset pin must be held at ground (<0.5V) for at least 50mS after the power supply is within tolerance. « Reset performs the following functions within the chip: (i) Sets PC to Zero. (ii) Sets Stack Pointer to Zero. (iii) Selects Register Bank 0. (iv) Selects Memory Bank 0. (vy) Sets BUS (DBO - DB 7) to high impedance state. (Except when EA = 5V) (vi) Sets Ports 1 and 2 to input mode. (vii) Disables interrupts (timer and external). (viii) Stops Timer. (ix) Clears Timer Flag. (x) Clears FO and Fl. (xi) Disables clock output from TO. (10) Oseillater Circuit . TMPS049 can be operated by the external clock input in addition to erystal oscillator as shown below. +5V 470: - 2ff xpat 1 2): XTAL 2 ror fi : loa TIL Gate a 3p xTaL 2 4702 3 xTaL 2 hoor . 35¥ : PT 2. Basic Operation and Timing The following basic operations and timing are explained (1) Instruction Cycle (2) External Memory Access Timing (3) Interface with 1/0 Expander TMP8243P (4) Interaal Program Verify (Read) Timing (5) Single Step Operation Timing (6) Low Power Stand-by Mode —745—

TECHNICAL DATA TMP8049PI-6, TMP8039PI-6 () Instruction Cycle + The instructions of TMP8049 are executed in one or two machine cycles, and one machine cycle contents of five states. + Fig.4 illustrates its relationship with the clock input to @U. + 62 clock shown in Fig.4 is derived to outside by ENTO CLK instruction. + ALE can be also used as the clock to indicate the machine cycle as well as giving the external address latch timing. (2) External Memory Access Timing (i) Program Memory Access + THP8049 programs are excuted in the following three modes. (1) Execution of internal program oniy. (2) Execution of both external and internal programs. (3) Execution of external program only. The external program memory is accessed (instructions are fetched) avtomatically when the internal ROM address is exceeded in mode (2) and from initial start address 0 in mode (3). + In the external program mesory access operation, the following will occur + The contents of the 12-bit program counter will be output on BUS(D3O - DB7) and the lower 4~bits of Port 2. + Address Latch Enable (ALE) will indicate the time at which address is valid. The trailing edge of ALE is used to latch the address externally. + Program Store Enable (PSEN) indicates that an external instruction fetch is in progress and serves to enable the external memory device. + BUS (DBO - DB7) reverts to Input mode and the processor accepts its 8-bit contents as an Instruction Word. + Figure 5 illustrates the timing. (ii) Access of External Data Memory + In the extended data memory access operation during READ/WRITE cycle the following occurs + The contents of RO RI is output onto BUS (DBO ~ DB7). + ALE indciates address is valid. The trailing edge of ALE is used to latch the address externally. + A read RD or write WR pulse on the corresponding output pins indicates the type of data memory access in progress. Output data valid at_trail- ing edge of WR and input data must be valid at trailing edge of RD. + Data (8-bits) is transferred over BUS. —746—

TECHNICAL DATA TMP6049PI-6, TMP8039PI-6 (6mHz) a (2MHz) Generated internally ¢2 ] Instruction! Decode Execution | Execution | Execution Fetch | | i | i i | i |

1 State 1 Cycle i

(400kHz J Fig.4 Instruction Cycle Timing Instruction Instruction ALE | | P| | r 4 | Fig. 5 Timing of External Program Memory Access —747—

TECHNICAL DATA TMP8049PI-6, TMP8039PI-6 Program Address Data Address Program Address ‘ \\ \\ | Inst rver ior | Inpufourpur Data Instructor Suggest we have diagrams ALE oe ne ALE ED — We re a Fig. 6 Timing of Accessing External Data Memory —748-—

TECHNICAL DATA TMP8O49PI-6, TMP8O39PI-6 . Figure 6 illustrates the timing of accessing the external data memory during execution of external program. . (3) Interface with 1/0 Expander (TMP8243P) | The TMP8O49 1/0 can be easily expanded using the TMP8243 1/0 Expander. THis device uses only the lower half 4-bits of Port 2 for commuication with the TMP8049. The TMP8243 contains four 4-bit I/O ports which serve we extensicns of one chip 1/0 and are addressed as Ports (4-7). all Communication takes place over the lower half of port 2 (P20 - P23) with timing provided by an output pulse on the PROG pin. Each transfer consists ct two 4-bit nibbles the first containing the "OP Code" and port address and the second containing the actual 4-bits of data. 4120 EA OY nour ef dnt Trput of internal —_—— Thput of internal 720, P22 Input of Internal ROM Address Rot address Fig.7 Timing of Reading Internal Program Memory sv sv 10K | ss Bo RON sy , sv—tn % 9 53 10K 74 ro, 0 ALE Fig.8 (a) Single Step Circuit —749—

TECHNICAL DATA TMP8049PI-6, TMP8039PI-6 Reading of Internal Program Memory + The processor is placed in the READ mode by applying +12V to the EA pin and OV to the “RESET pin, The address of the location to be read is then applied to BUS and the low order 2~bits of Port 2. The address is latched by a 0 to 1 transition on RESET and the high level causes the contents of program memory location addressed to appear on the eight lines of BUS. + Figure 7 illustrates the timing diagram for this operation. (5) Single Step Operation. + A single step feature useful for debug can be implemented by utilizing a circuit shown in Figure 8 (a) combined with the SS pin and ALE pin, + A D-type flip flop with set and reset is used to generate SS. In the run mode SS is held high by keeping the flip flop set. To enter single step, set is removed allowing ALE to bring SS low via reset input. The next instruction is started by clocking a "1" into the FF which will not appear on SS unless ALE is high removing reset. In response to SS going high the processor begins an instruction fetch which brings ALE low resetting FF and causing the processor to again enter the stopped state. + The timing diagram in this case is as shown in Figure 8 (b). (EA = 5V). (6) Lower Power Stand-by Mode. + The Lower TMP8049 has been organized to allow power to be removed from all but the volatile, 128 x 8 date RAM array. In power down mode the contents of data RAM can be maintained while drawing typically 10 - 15% of normal operating power requirements. + VCC serves as the 5V supply for tie bulk of the TMP8049 while the VDD supplies only the RAM array. In standby mode VCC is reduced to OV but VDD is kept at SV. Applying a low level to reset inhibits any access to the RaM by the processor and guarantees that RAM cannot be inadvertently altered as power is removed from VCC. eS \\ Instruction Input instruction DBO - DB7 Address (PC) »__)———_ Adéress (p+) P20~ P23 Address (PC) x X Address (PC#1) Port 20-23 Data Fig.8(b) Single Step Operation Timing —750—

TECHNICAL DATA TMP8O49PI-6, TMP8039PI-6 INSTRUCTION ACCUMULATOR INSTRUCTION { . |__Instruction Code i] . i] 1 1 Flag! j_Nsemonic (D7 [pelp5ipaipsib2iDipo; _ Operation [Bytes | Cycles) ~cTac} [ADD A,Rr Pot al al of at rf rl ri (ay<-(a)+ (Rr) rd 1 Tol ol . i Pid tt lot to tre 0-7 | | Iorot |ADD A,@Rr { Of Lf 1! Of Of Of Of riCads-(A)#CQRr)) | 1 i 2 Jol ol \\ 1b} di tt to to tre 0,1 ! | itl |ADD A,#Data { 0! O| O| O| Of Of 1} 1) (A)<-(A)+Data 2 | 2 Joloi JADDC A,Rr {Of Vf dt ab af et el rl (ad<-(ade(Rr)+(c) | rf 1 | of of | hoiot ft tot to to tee 0-7 | | Iolod jappc A,@Rr =| Of 1] 1] Af Of Of Of el (ay<-(ad#C(Rr))# | 1 ft 2 | of of \\ Ptr ds tb bot ley i ! fore \\ Pdot yoy to to to terso,a | | iotot |ADDC A,#Data | 0] 0! Of 1] O| Of] Pf 1) (A)<-(A)+Datat(c) | 2 | 2 | of of i [d7{d6{d5|d4{d3|d2/d1 [dol ! 1 Pobod [ANL A,Rr | ol i] Of Li li ri rl ri(A)<-(A) and (Rr) | 2 $b ft -} =} I fboiot to t tot ters 0-7 ! | I otot [ANL A,@Rr | Ol 1f Of 1} OF Of Of ri(Ad<-(Adand ((Rr))! 2 | 1 ft -t-l . | Plot oi t ft tof tre 0,1 i 1 iohot |ANL A,#Data | 0! 1] 0! 1] 0] Of 2} 11 CA)<-(A) and Data | 2 | 2 jf -i -i JORL A,Rr | oO] 1{ Of Of BL rf} rl rl (ad<-(A) or (Rr) | ob Fo ob di =i | Prti ttt r= 0-7 1 | tat JORL A,@Rr 1 Ol Lf Of Of Of Of O} r!(A)<-(A) or ((Rr))| 2} 2 [-t-l i boa foi do do to tr 0,2 ! I Pood | {d7id6id5/d4/43/d2/d1|d0! I t Poiod [XRL A, Rr Fab dl Of Ql Ql rf rf r'(ay<-(A) EoR (Rr) | 2 job Eh =I ! ott ot ft tot lo tre 0-7 | J Iolot IXRL A,@Rr {lf 1} Of 2] Of Of Of ri (ad<-Ca) EoRC(RE))! 1 | 1 fj -l -t | fob bt} i to tot tre 0,2 i | Prot IxRL A,#Data | 1! 1! 0! 1] Of Of 1) 1/(A)<-(A) BOR Data ! 2 | 2 | =I -! \\INc A 10 Of O| AI Of 1] LI 1) (Ad<-Caded bob fod f-te-t |DEC A 1 01 Of Of Of Of 1} LI Al CAd<-Ca)-1 for tod f-l-t [CLR A [| Of Of 1] Of Of 1] If 11 CAd<-0 ford od t-te [CPL A {Of Of 1] 1] Of LI 1] 11 CAd<-NoF (A) fordob t-t-t IDA A | Of df Of 1! 0) Lt QI ilDecimal Adjust !o or | 2 Jolt | {tot tot | tL [Accumutator I i Potod [SWAP A { Of LE O} Of Of If LI 11(A-7)->(A0-3) ee ee ee Oe ed | | ( < 1 | Ioiot | | es | ! foto —751—

TECHNICAL DATA TMP8049PI-6, TMP8039PI-6 struc Code i i... 1 Flag! ! Mnemonic ALG Operation [Bytes cycles) Ere IRL A Fal ab il oF of ai iy 1 Can+i)<-(an) 1 | | horeot dt tee ins 0-6 i tot ! Pb ot fo tot tf ttaoy<-¢a7) i Paid |RLC A A) aU! a! 1i OF 1} at a] Cansi)<=(an) Porth oro tele | fotor to io oy f tas 0-6 1 iol i | foot i 1 (C)<=(A7) 1 | | fir ty td ((A0)<-(C) | it IRR A PO} V2) 1) Of a} di 1} CAn)<-Cant1) hoa lye = 1 ee | [n= 0-6 | i yd : Pe} tb bid | (a7)<-(a0) ! 1 IRRC A Of 1] 1! GO! Of 11 1! 2) (an)<-Cans1) fou Loistie- i ft}ot tototod [n= 0-6 | od | bob a7) <- (0) H : it Tnput /Output Tastruction _ - T_Instruction Code H H T j_ Mnemonic 157 ]/pelbS'DAID DI IDITDO| _ Operation [Bytes icycles|Etaé: [IN A,Pp 1 Of 0; Of Of 1} OL PI Pi (Ad<-(Pp) a | Tif ft ft ft i t bPe 2,2 | 1oiot fOUTL Pp,A | 0] Of A! 1) 1! OF Bs P (Pp)<=Ca) Porto 2 f-pet 1 It ! 1 P= 1,2 | ol ANL Pp,#Data 1) 0! 0 1} 1) 0; Pi P! (Pp)<-(Pp)and Data! 2 2 ste | \\d7id6}d5/d4}d3id2!dlido' P= 1, 2 i to \\ORL Pp,#Data | 1} 0] 0 Ol 1) 0; Pi P;(Pp)<-(Pp)or Data} 2 5 2 |=) = i 1d7/d6/d5!d4/d3]d2idl{d0! P= 1, 2 | ‘4 LINS A,BUS 0} 0} O Of 1) 0. 0, O (a)<-CBuS) fo 2 |= JOUTL BUS, A 9: 0) 0! 0! 0} O! 1} 0} (BUS)<-(a) hoa 2 fet- 'ANL BUS,#Data! 1] 9/ O| 1] 1) Of 0} O}(BUS)<-(BUS) and | 2 2 -b- | 47,6! d5/d4!d3'd2\\dl)d0! Data | Poiod jORL BUS,#Data! 1| O] O! O| i] Of Of Of (BUS)<-(BYS) or t 2 2 ele | id7$d6{d5!d4/d3!d2/d1id0|Data | tod iMOVD A,Pp [| O! 0} Of Of Lf 1] PI PI(AO-3)<-(Pp) boa 2 nie t bob ob ob ob EL ttas-7)<-0 1 ' fod | Ht tot to to | ot tepe4a-7 i tot {MOVD Pp,A f Of Of 1} EL Li Qi Pi Pi@p)<-(ao-3) fon 2 biel | Pobod ot of to | of tepea-7 | hod {ANLD Pp,A 11) 9] 0; 1] 1! 3] Pi PI<Pp)<-(Ppand | 1 2 tele | ee [Pe4-7 | tot {ORLD Pp,A {1} Gl Ol oO] 1} 1] Pl Pi(Pp)<-(Ppdor(a0-3)} 1 2 1 -b- 1 (ee ee ee [pse4-7 i 1 —752—

TECHNICAL DATA TMP8049PI-6, TMP8O39PI-6 Register Instruction i ; Instruction Code : i T Fla; |_Mnemonic ip7ipeiDSib4D3iD2iDITDO| _OPeFAtion jsytes Cycles \\~crag| | Inc Rr To; of} Of al il rl rf ri (Rr)<-- (Rr) 41 1 ToT f= | botod ft to to bt bt tre 0-7 | 1rd | INC ¢Rr 10 Of Of 2) Of Of Of riC(Rr))<-C(Rr))+1 1 1 Yop -f-! t ee [r= 0,1 | Pobol | DEC Rr A} 2] Of Of Uf rl rl rl (Rr)<--(Rr)-1 hoa 1oy-t-! \\ titi tt iitrs 0-7 i l ta Branch Instruction |" Mnemonic | _ Instruction Code Operation Bytes 1Cycles| Flag! 1 | D71D61D5 {D4 1D3[D2/D11DO! i ! \\ciaci \\JMP Address |al0/a9]a8! O1 0) 1] O| O:(PCO-7)<=-(a0-7) | 2 F 2 THT =i ! }ot tot tod ft | | (eei.)<--par 1 ! ort JIMPP GA | df Of 1) al Of OF Af A} (PcO-7)<--C(A)) EEE 2 The! {DINZ Rr, Poa} di dl Of 1f ri rf ri (Rr)<--(Rr)-1 [2 4 2 f-t-h |Address 1 a?\\a6|a5|aé}a3/a2lalla0lif Rr not 0 ! ! ido I fob Fd tt tbl (ec0-7)<--(a0-7) | folot lac Address | 1] 1] 1] Lf Of 1} Qf O!(PCO-7)<--(a0-7) | 2 | 2 Fal =t | i }ot odo tol i ft fife | | ili i | a7 a6} a5|aé|a3!a2jaljad| (Pc) = (PC)+2 i H it 1 bof bt tot to to t lit ce 0 | ! it |JNC Address | 1] 1] 2] Of O! Li 1f O/(PCO-7)<-(a0-7) | 2 | 2 Eat \\ a7! a6!a5ias|a3‘a2ial adiif C= 0 i ' it i Poe br di ia £ E(RC)<-- (PC) +2. i | it i : horol od fot fit ch i ! it {JZ Address | 1/ 1] 0] O! Of 1) 11 Ol(PCO-7)<--(a0-7) | 2 | 2 Fah at | | a7ja6laS}a4ja3ja2!aljadlif (A) = 0 | | f 1 1 a ee he ! i ti | Plott ij lif (A) .NEQ.O | ! i oiod 3NZ Address | 1] Of OL 11 O! 1] 1} Of @CO-7)<--(a0-7) | 2 | 2 I -t = | | a7|a6la5|adla3la2/alladlif (A) .NEQ.O t 1 | 1 ! Poy yo fob bob Lb eee)<--(pe)+2 1 i : i ! i fopototo | lif (A) = 0 4 i Pit jJTO Address | 0] O| 1] 1] Of 1) 1{ 0] @CO-7)<--(a0-7) | 2} 2 mie! \\ | a?JablaSjasia3/a2ialla0lif TO = 1 | | Pit ! fob tod tot tb @ed<--@e)+2 i i io i foto} tot tf fit tos 0 | ! it IJNTO Address! 0! O/ 1! Of O| 1{ 1] O{(@CO-7)<--(a0-7) | 2 | 2 teri - ! | a7|a6la5!a4/a3la2ialla0lif To = 0 t | i | | | Poy bot ot fb L b@ey<--(@e)+2 { | tr oiot i fof to toto tot ft tif Tord { | tolot \\JT1 Address | 0] 1] Of 1/ Of 11 1] Of(PcO-7)<--(a0-7) | 2 | 2 1-1 -! ! { a7la6la5{a4la3la2lall/a0jif Tl = 1 1 l roll | i { tot tot tt | @e<--(e)+2 | | bil | fot to tot ot tt lit ti = 0 | i tid JINTL Address] 0] 1| O| O| Of 1 1| O{(PCO-7)<--(a0-7) | 2 | 2 I=) -t | | a7\\a6la5/asla3!a2lalla0lif TL = 0 | ! Pt ! fot tot tot bb [@eed<--(rey+2 1 | ttt l [es ee eS a i | tit —753—

TECHNICAL DATA TMP6049PI-6, TMP8O39PI-6 |" Mnemonic | Instruction Code Operation |Bytes |Cycles|_Flag| | \\"D71DeTD51D41D31D21DI1DO! | | iclac! |JFO Address | I] Of IT 1] OT if iT 0) @00-7)<——tad-7) | 2 1! | | a?ja6la5|a4]a3la2jallaOlif FO = 1 t ! trot | | Soh tol bod bt t@ep<--@eye2 i ! oto i | fot to tof | |) lit ro = 0 ! foil ISFl Address | 0! 1! 1 11 Oj 1} 1] ol (Pco-7)<--(a0-7) | 2 | 2 | =] -! | | a7la6la5|a4la3!a2\\aljaQlif Fl = 1 i t horot } 1 bolo} fo fo dt) t@eo<--@wey+2 ! folot | toot fof of tf | jif Fh =o 1 I hoi d |STF Address | 0! O| O| 1! Of 11 1] 0! (PCO-7)<--(a0-7) | 2 | 2 | =) i | | a7la6la5{a4/a3]a2l/aljaO|if TF = 1 ! | 1oiod i fot ot ot tot tL) b@eds--(ey+2 I | 1s t of tot ot | dd lit tee 0 i I folot LINI Address | 1] 0! O} Of Of 11 1] Ol (PCO-7)<--(a0-7) | 2 | 2 j =| =| | | a7la6laS|aé|a3/a2lal]aOlif INT = 0 ! ! Iolot | Fob fo bot db th t@eey<--@ede2 ! i oud | Pot tf tb td tit int ea I { Poyod |3Bb Address | b2/b1/bO] 1) 0! O| 1] O{(PCO-7)<--(a0-7) | 2 | 2 | -| -] | | a?la6la5ja4la3/a2/alla0|if Bb = 1 ! [ Iolod | fot ot bot i tt @ed<-ed+2 ! t Poiod | Pol to tot to bod lit pb =o t 1 foi | Fold tot to $d t@=0-7) I i Iobog [CALL Address|al0|a9/a8| 1| 0! 1] Of 0!((sP))<-- [2 1 2 [-t-! | | a7la6la5!a4|a3!a2/al|a0] (PC), (PsW4-7) | ! Hott | | fof ot tof td l¢sp)<--(sp y+ 1 | Poiot H ! hob of fo} 4 4 | (Pc8-10)<--(a8-10) | ! oft { I foto ' tof ff |(eco-7)<--(a0-7) | | hobod ! Pot tod tot tt t@eii)<--psr ! I Iolod | RET | Af Of Of oO} Of oO} 1) 11¢SP)<--(sP)=2 !oato2t 4 4 | For ot toy ttf t@ed<-csp)) 1 | iit | RETR | 1! 0] Of 2} of Of 1) 41 (sP)<——-(sP)-1 foro} 2d 4 | Pot fo bob bot b t@ey<--Cspy) ! 1 Pobod | bot ee swg-7<--CCsP)) | i foot Flag Manipulation Instruction | Mnemonic |___Instruction Code [Operation IBytes |Cycles! Flag! } |_b7[D61D5'D41D3/D2/D11D0} I [ |_cTacl (CLR Cc {iT of or if oral it it¢ey<== 0 Pr Pr or=} } cpl c 1 2] Of 11 Of Of 1} 1} 11 ¢c)<--Nor¢c) fo oa J oa fol-t | CLR Fo | 1) Of O1 Of oj 11 Of 1}¢FO)<-- 9 bod fod [=f = | CPL FO | 1} Of Of 1} Of 1] Oo} 1) (FO)<--NoT(FO) fob | ot | -t-i { CLR FL | 2} Ol 11 0} of if of 1iCe1)<-- 0 ford oa [-f-t |_c@pL Fl {ij ol ti at of 4) Of 2) (F1)<--NoT(FL) fo | i =} —754—

TECHNICAL DATA TMPGO49PI-6, TMP8039PI-6 Data Transfer Instruction a_i |” Mnemonic |__ Instruction Code | Operation [Bytes |Cyclesi Flag! 1 | "D7 [De1D5 [D4 Tp31D21D11D0! i I i*cTac! \\NOV A, Rr! Ll 1) Qf Q1 UT rl ef ef Cay<-~ (Rr) 1 1 1-1 -! t Pbod bt tol to ters o-7 | | | -l-1 Imov a, @Rr | Tf Li al af 0! O} Of ri (ay<-~ C(Rr)) fob tod -1-1 | | 1 ee i | rotot [Mov A, #Data) 0] 0] 1) 0/ 0} O| 1h 1/(A)<--Data io2 to 2 -i-l i | 471d6\\d5\\d4{d3/d2/d1!40] ! | trot Mov Rr, A} 1 Of 2! Ol Li el xl r{(Rr)<--(A) fo oy tod tale ' horde tt bt tot bee 0-7 I t Iolot jMoverr,A | -L1 OL 2! Of 0} Of OF ri ((Rr))<-CA) 1 ya [-h-l ! i ee ee 1 | oto [Mov Rr,#Data] 1) Of 1! 1) Qi ri rl ri (Rr)<--Data bo2 4 2 t-t-l | | d7|d6!d5id4|d3)d2idild0| r= 0-7 1 \\ rat |Mov@rr,#Data! 1! 0! 1! 1] 0} Of O| £1 ((Rr))<--Data i o2 1 2 te-t-t | | a7ja6ja5la4ja3la2jalla0| r = 0, 1 ! ! totot IMov a,psw | 1] 1! Of Of O} II 1] 1) (a)<~- (PSW) forpo ot t-tei IMov psw, A | il 1{ Of 1! Of Ti 1] 1f(esw)<--Ca) oa toa i-t-l (xcH A, Rr | 0] Of 1] O1 2f ri rt r!(A)-->(Rr) for toa t-t-l 1 [ee ee ee | i rut | Poy tr td bt dot ters on7 I i fil IxXcH A,@Rr | ol 0! 1! of of of Oj} r!(A)-->((Rr)) boat oa d-t-! | fort Pore - ! ! oat porrd | | bofoder : 0, 1 1 | iid ixcnD A,@Rr | 0! OF 2] 1{ 0} O] O} ri(ad-3)-->((RrO-3))| 1 1 ot {-f =i \\ i fe ee <-- | | ttt | | Pied bob tb tes o,k | | robod Imovx A,@Rr | 1! Ol O| O} O| Of Of rl (Ad<--C(Rr)) toa} 2 t-te | Poy tb dt tb tes 0d 1 i botot iMovx @rr,A | 1] 0] Of 1] Of Of Of r|((Rr))<--(A) io 2 fo 2 t-t-t I | Piet td tos tee o,t ! I iotot jMove a, @A | 1! Ol 1] 0} Of Of If 1{(eco-7)<-~CA) Por to 2 te-b-l | | Lot or ob od tt $tay<-= (Rey) | | tit | hod EE Lb EL 1 (ee8-any<--001) | ' Iolot | | Od D2 | i Lit —755—

TECHNICAL DATA TMP8049PI-6, TMP8039PI-6 Timer /Counter Instruction | Mnemonic /|__ Instruction Code T TBytes |Cycles| Flag! ! | D7{D6;D51D4{D31D2'DI IDO! i ! CIAC! |MOVA,T Y Of YO; Of Of OT) OT (aye) TT T=! -1 iMOv T,A | 0) 1] 1) 0! 6} O! 1) 0) (T)<-~Ca) rs ee es (sTRt T ' Of 1! OF 1! Ol 1) O| Licounting is oe ee ' 14 1 i | Istarted in the | | | 1} oft | | ttimer mode i i \\STRT CNT i} Of 1] 0; O! O' 1) 0, 2/ Counting is ee ee | | Prot | [started in the | Hy i \\ i} fo tot tt 1 levent counter ee re | | Iolo ba | |mode t i itd {STOP TCNT i 0; 1] 11 Oj O; 1| OF LiStop both time oe vie t | hotolod { | |accumulation and | i 1 ! 1 of fo to tf $f) levent counting I | ! ! EN TCNT) | O] Of 1] 0! Of 3) O} LiTimer interrupe | 2 | 1 i ale 1 i !oyoto gs | lis enabled 1 i i DIS TCNT! | O| O} 1! 1) O 2) Oj Litimer interrupe { 1 ! 2 f=! =! \\ lis disabled : ! : Control Instruction | Mnemonic | Instruction Code | Operation [Bytes {Cycles! Flag! ! LD7[D61DS |D4"D3_D2.D1 DO} | ! eae EN T 00, 6, 0 0, 1, 0 1 External interrupt, 1, ro pofoaorad ‘is enabled : DIS I {| 0! Of 1! 0: 1) O! L-External interrupt) 1 bie =! 1 boiot tot ot | fis disabled | t i ) SEL RBO =| 1/1] 0! “| Ol 11 0} 1! (BS)<-- 0 Io4 |} rin =! | SEL RBI i i} 1] 0; EI Of Lf OF 1] (BS)<-- 1 foal Py =} ! SEL MBO =| 1! 11 2! Of Of 1} Of 11 (DBF)<-- 0 foal bie - | SEL MBL fod} Ql dl di Of d} 0} 1! @BF)<-- 1 re 1i- -! | ENTO CLK! Oj 1) 1/ 1) O| 1] Of 1/70 is enabled to | 1 | li- -! { i | Jact as the clock } 1 Hi 1 i t boy to tf ft foutput | ' ! ! i_NoP {_0| 0! O| 0! O! 0} 0} O1No operation boat Lis =} —756—

TECHNICAL DATA TMP8049PI-6, TMPBO39PI-6 \\TMPSOL9PT/B039PI1: INDUSTRIAL SPECIFICATION | ABSOLUTE MAXIMUM RATTINGS \\“symBou | ITEM RATTING | {WDD [VDD Supply Voltage (with respect to GND (VSS)) [-0.5V to + 7v_ 1 ivec [VCC Supply Voltage (with respect to GND (VSS)) T=0.5¥ to + Vi VINA {input Voltage (Except EA) =0.5V to + 7V | VINB___|Tnput Voltage (Only EA) =0,5V to + 13V_| pp iPower Dissipation (Ta = 70°C) _ 1.5 7 FSOLDER Soldering Temperature (Soldering Time 10 sec) 260°C 1 ITSTG (Storage Temperature =35C to 150°C | TOPR [Operating Temperature {-40"C to 85°C | DC CHARACTERISTICS TA=-40°C to 85°C!, VCC#VDD=+5V210%, VSS=O0V, Unless Otherwise Noted. |_SYMBOL ! PARAMETER TTEST CONDITIONS [MIN (TYP. {MAX. UNIT] iVIL [Input Low Voltage T {0.51 - 7 O77) Vv | ! [Except XTAL1,XTAL2, RESET) 1 i i i } ' |VILT [Input Low Voltage | 057-1 0.6 V1 1 | (XTAL] ,XTAL2, RESET) i \\ i I | {VIR Tinput High Voltage i 12.27) - [veclv | i | xcept XTAL],¥TAL2, RESET) { ! i ! $ I {VERT [Input High Voltage ! 13.8: - fveci vj i (STALL NTAL2, RESET) ! i i i 1 \\YOLTOutput Low Voltage (BUS) FC 0 | |WOLT TOutput_Low Voltage TTOL = 1.6 mA =P 0.451 VI | [(RD, WR, PSEN, ALE) i ! i i i i (VoL2 [Output Low Voltage (PROG) [tou = 0.8 mA T= = 0-457 | |VOL3 Output Low Voltage | TOL = 1.2 mA - [= [0.45f vi 1 \\(For other output pins) i | { i i | \\VOH [Output High Voltage (BUS) | 10H _=-280uA P2.4j)- i -ivii \\vonl — |Output_High Voltage | TOR =-80uA P24t- [ =-Tvii t [(RD, WR, PSEN, ALE) { { ! i i | \\VOH2 [Output High Voltage TOH =-30uA T2.47- | -Tv i \\ | (For other output pins) | ! i i | 1 1 _ 1 en en | {ILI [Input Leak Current (T1, INT) lvss ¢ VIN ¢ vec | - | - | #10] HA! | i 4 - i 1 i 1 i \\TLYT input Leak Current TWSS+0.45<Vingvec] - 1 - [-700T ua | \\TLo Output Leak Current (BUS, TO) [VSS+O.45<vINcvoC! - 1 = | #107 ua | | | (igh impedance condition) ! . i | ! l ! {TDD VOD Supply Current I == 507 ma |Ipp+TCClTotat Supply Current I ee —757—

TECHNICAL DATA TMP8O49PI-6, TMP8039PI-6 AC CHARACTERISTICS {Ta=-40°C to 85°C], VCC=VvDD=+5V10%, VSS=0V, Unless Otherwise Noted. |_SYMBOLT PARAMETER [TEST CONDITIONS [MIN.|TYP./MAX.]UNIT| [tLL JALE Pulse Width T | 2007 - T= ns | ELE TALE Pulse Wide 0} 2007 = ns ItAL JAddress Setup Time (ALE) i] T1207 == ns | (ELA TaAddress Hold time (ALE) Hi go, = = ns | | ] T T ! [rec |Control Pulse Width(PSEN,RD,WR) | | 400! - |} - J ns | | T | {row |Data Setup Time (WR) t 1420! - | - ns! i _ T | | ewD. |Data Hold Time (WR) i | 80; - |- | ns} |tcy [Cycle Time | V2.5) = 15.07 us! | 1 —_ Tt i {RD |Data Input Read Time (PSEN, RD) | fo =} - 1 400! ns} | i _ T t i T I] | | raw laddress Setup Time (WR) i | 230) = t= fons | \\raD Address Setup Time (Data Input)! T= T= T6007 ns! \\ T _ — 1 TT | ltaFc lAddress Float Time (RD, PSEN) | | -40| =} = tons | fAFC__lAddress Float Time (RD, PSEN) | | -401 - f= It ns {rca [Internal between Control Pulse | [ lol= T=" Tas} ! Vand ALE | i ! 1 1 ! ig@e !Port Control Setup Tine (PROG)) SSE | IxPC_ "Port Control Hold Time (PROG) 65; > - ns _| i2C__Port Control Holé Time (PROG) 65) = = ns !tPR [Port 2 Input Data Set Time = l=. 860) ns | t { (PROG) i i | i I l teDP. {Output Data Setup Time (PROG) | [230] = T= Tons! | ePD. [Output Data Hold Time (PROG) |} { 25) = f= tas} \\ePF [Port 2 Input Data Hold Time T for = 7 1601 ns! I | PROG) i i H ! ! {PP [PROG Pulse Width i | 920) = | = J ns | [tPL [Port 2 1/0 Data Setup Time H 3001 = T= ns | [LP [Port 2 1/0 Data Hold Time i [i20f = f= Fons’) Hip __lPort 2 1/0 Data Hold Time 0 j_ 0 207 == ns” Note :tC¥=2.5us, Control Output: CL=80pF, BUS Output: CL=]150pF, PORT20-23: CL=80pF. —758—

Tos TECHNICAL DATA TMP8049PI-6, TMP8039PI-6 TIMING WAVEFORM A. Instruction Fetch from External Program Memory toy TLL . ALE , ‘ | | LARC CA Ha SER Toa N My, ae MM, a hadrons cy ERS Instruction B. keed from External Data Memory tec fa wD f tarc FDR sus WR KIL Kp C. Write into External Data Memory ae ff \\ SF NL tec We 7 twp ws KR XK == KD —759—

TECHNICAL DATA ‘TMP8O49PI-6, TMP8039PI-6 D. Timing of Port 2 during Expander Instruction Execution TYPICAL CHARACTERISTICS ALE / \\ f i! A tor | hPL tpp tpp PORT20 (Output Data) Port {20-23 | | PR tpr PORT20 Data | PO (Input Data) Port 20-23 tep_, | fc Input Data Data PROG t * Input Enabled State TYPICKL CHSRECTERISTICS 1) BUS! Igy - Vor 3) BUS, Pl, P2: Joy - Vor [|| TARDS°C = — | gan2sec a i a ee = Nf el ee | 0 ee ob 4 . 0 2 4 Yow (v) Yo. 0 2) Pl, P2:Ton -Von 500) TT vonevecesv

2 LF tt tacasee

= 401 | | 1 BE Cy TT tT 0 a es ps a 0 2 4 Vou (v) —760—

TECHNICAL DATA TMPGO49PI-6, TMPGO39PI-6 PROGRAM TAPE FORMAT TMP8049 programs are delivered in the form of paper tape with the following format and it is required to attach the tape list. The format of paper tape is same as the Intel type object tape (hexadecimal tape output by Intel MDS system, PROMPT 48 Development Tool, etc.) ()) Tape Format rit | reaser, 50 "NULL" characters oF more Comments |-+--- Comment (Record ark ":" is not included) Option [Oot ]-.--- Record Mark [J Record Length (2 hexadecimal digits) FF | sting acorese (henadcisad tebe — "00" .... Normal Record — sess Normal Recor |] | Record type (2 Digits) von" .... End of File Record Deta [——| | creck sum (2 hexadecimal digits) Dummy characters (RUBOUT, BLANK) before and after "(CR)(LF)" are [ =) } optional. TX Jreater 50 "NULL" characters or more (2) Example of Tape List TOSHIBA MICRO COMPUTER TLCS-48 :100000000665C7D79 CF 50F 3F951 FEDSSA8FF16E570 :1000100088884DDE67D31F SDBABA6DF 292F 11 3F5C1 :100020004FF 1 FBSDFFDAA96A99 CF 7DF94A346B7 C09 :10003000197352F729F12F79AA9C057C5B851EED77 :1003CO005DFDB5E556A67277F61A51 C631 CF9FOE8O :1003D000BD2F 6F 20E8BB1977E3FBSADIF41 FDAA7E2 :1003E000B53D42E0EC3254 6025B7308CDD52063D1D :1003F000B4BE9E9E 345861 38060B20VC372BF 60BD6 :00000001FF —761—

TECHNICAL DATA TMPG049PI-6, TMPB039PI-6 OUTLINE DRAWING Unit in om 46 21 x lcd BS I 20 é | 2 ol z ptezesoen a FAA AAA AAA ; q TT | i o2sto! = 1.44015 O15? Note: 1. This dimension is measured at the center of bending point of leads. 2. Each lead pitch is 2,.54um, and all the leads are located within 20.25mm from their theoritical positions with respect to No.l and No.40 leads. —762—