TMP62681

TMP62681 TOSHIBA | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 78

Technical content

a . TOSHIBA TMP68681/2681 T-75-37- OS 1. INTRODUCTION ‘The TMP68681 dual universal asynchronous receiver/transmitter (DUAR) is part of the TLCS-68000 Family of peripherals and directly interfaces to the TMP68000 processor via an asynchronous bus structure. The TMP68681 consists of eight major sections internal control logic, timing logic, interrupt control logic, a bidirectional 8-bit data bus buffer, two independent communication channels (A and B), a 6-bit parallel input port, and an 8-bit parallel output port. The TMP2681 dual asynchronous receiver/transmitter (DUART) is functionally equivalent to the TMP68681 with some minor differences. The description of the ‘TMP68681 applies to the TMP2681 except for the areas described in the Appendix found at the back of this document. Figure 1.1 illustrates the basic block diagram of the TMP68681 and should be referred to during the discussion of its features which include the following: e TLCS-68000 Bus Compatible @ — Two Independent Full-Duplex Asynchronous Receiver/Transmitter Channels e. Maximum Data Transfer: 1X ~— 1MB/second 16 — 125 kB/second ¢ Quadruple-Buffered Receiver Data Registers e —Double-Buffered Transmitter Data Registers @ Independently Programmable Baud Rate for Each Receiver and Transmitter Selectable From: 18 Fixed Rates: 50 to 38.4k Baud One User Defined Rate Derived from a Programmable Timer/Counter External 1X Clock or 16 X Clock © Programmable Data Format: Five to Eight Data Bits plus Parity Odd, Even, No Parity, or Force Parity One, One and One-Half, or Two Stop Bits Programmable in One-Sixteenth Bit Increments @ Programmable Channel Modes: Normal (Full Duplex) Automatic Echo Local Loopback Remote Loopback DUART-1

w_—_ o— Internal Control Logic keset -——— RS1~RS4 XMCLK xe Processor « Selectors External Interface 2 Interface s 2 Character || _ oo-07 a interruy ‘Character “ ~t | = ve PLE mo a Figure 1.1 Block Diagram DUART-2

L TOSHIBA TMP68681/2681 © Automatic Wake-up Mode for Multidrop Applications © — Multi-Function 6-bit Input Port Can Serve as Clock or Control Inputs Change-of-State Detection on Four Inputs Features (Coninued) . Multi-Function 8-bit Output Port Individual Bit Set/Reset Capability Outputs can be Programmed to be Status/Interrupt Signals . Multi-Function 16-bit Programmable Counter/Timer © Versatile Interrupt System Single Interrupt Output with Eight Maskable Interrupting Conditions Interrupt Vector Output on Interrupt Acknowledge Output Port can be Configured to Provide a Total of Up to Six Separate Wire- ORable Interrupt Outputs © Parity, Framing, and Overrun Error Detection e = False-State Bit Detection e — Line-Break Detection and Generation . © Detects Break Which Originates in the Middle of a Character © — Start-End Break Interrupt/Status ° On-Chip Crystal Oscillator © TTL Compatible © Single +5 V Power Supply

1.1 INTERNAL CONTROL LOGIC

The internal control logic receives operation commands from the central processing unit (CPU) and generates appropriate signals to the internal sections to control device operation. It allows the registers within the DUART to be accessed and various commands to be performed by decoding the four register-select lines (RS1 through RS4). Besides the four register-select lines, there are three other inputs to the internal control logic from the CPU: read/write (R/W), which allows read and write transfers between the CPU and DUART via the data bus buffer; chip select (CS), which is the DUART chip select; and reset (RESET), which is used to initialize or reset the DUART. Output from the internal control logic is the data transfer acknowledge (DTACK) signal which is asserted during read, write, or interrupt acknowledge cycles. DTACK indicates to the CPU that data has been latched on a CPU write cycle or that valid data is present on the data bus during a CPU read cycle or interrupt acknowledge ([ACK) cycle. DUART-3

1.2 TIMING LOGIC

The timing logic consists of a crystal oscillator, a baud-rate generator (BRG), a programmable 16-bit counter/timer (C/T), and four clock selectors. The crystal oscillator operates directly from a 3.6864 MHz crystal connected across the X1/CLK and X2 inputs or from an external clock of the appropriate frequency connected to X1/CLK. The clock serves as the basic timing reference for the baud-rate generator, the counter/timer, and other internal circuits. A clock signal, within the limits given in SECTION 5 ELECTRICAL SPECIFICATIONS, must always be supplied to the DUART. The baud-rate generator operates from the oscillator or external clock input and is capable of generating 18 commonly used data communication baud rates ranging from 50 to 38.4k by producing internal clock outputs at 16 times the actual baud rate. ‘The counter/timer can be used in the timer mode to produce a 16X clock for any other baud rate by counting down the crystal clock or external clock. Other baud rates may also be derived by connecting 16 X or 1X clocks to certain input port pins which have alternate functions as receiver or transmitter clock inputs. The four clock selectors allow the independent selection, for each receiver and transmitter, of any of these baud rates. The 16-bit counter/timer (C/T) included within the DUART and timing logic can be programmed to use one of several timing sources as its input. The output of the counter/timer is available to the internal clock selectors and can also be programmed to | be a parallel output at OP3. In the timer mode, the counter/timer acts as a programmable divider and can be used to generate a square-wave output at OP3. In the counter mode, the contents of the counter/timer can be read by the CPU and it can be stopped and started under program control. The counter counts down the number of pulses stored in the concatenation of the counter/timer upper register and counter/timer lower register and produces an interrupt. This is a system oriented feature which may be used to keep track of timeouts when implementing various application protocols.

1.38 INTERRUPT CONTROL LOGIC

The following registers are associated with the interrupt control logic: interrupt mask register (IMR), interrupt status register (ISR), auxiliary control register (ACR), and interrupt vector register (IVR). Refer to SECTION 4 PROGRAMMING AND REGISTER DESCRIPTION for a more complete description of these registers. A single active-low interrupt output (IRQ) is provided which can be used to notify the processor that any of eight internal events has occurred. These eight events are described in the discussion of the interrupt status register (ISR) in SECTION 4 PROGRAMMING AND REGISTER DESCRIPTION. DUART-4

a TOSHIBA TMP68681/2681 The interrupt mask register (IMR) can be programmed to select only certain conditions which cause IRQ to be asserted while the interrupt status register (ISR) can be read by the CPU to determine all currently active interrupting conditions. When an active-low interrupt acknowledge signal (ACK) from the processor is asserted while the DUART has an interrupt pending, the DUART will place the contents of the interrupt vector register (IVR) (i.e., the interrupt vector) on the data bus and assert the data transfer acknowledge signal (DTACK). In addition, the DUART offers the ability to program the parallel outputs OP3 through OP7 to provide discrete interrupt outputs for the transmitters, the receivers, and the counter/timer.

14 DATABUS BUFFER

‘The data bus buffer provides the interface between the external and internal data buses. It is controlled by the internal control logic to allow read and write data transfer operations to take place between the controlling CPU and DUART by way of the eight parallel data lines (D0 ~ D7),

1.5 COMMUNICATION CHANNELS A ANDB

Each communication channel comprises a full-duplex asynchronous receiver/transmitter (UART). The operating frequency for each receiver and each transmitter can be selected independently from the baud-rate generator, the counter/timer, or from an external clock. ‘The transmitter accepts parallel data from the CPU, converts it to a serial bit stream, inserts the appropriate start, stop, and optional parity bits, and outputs a composite serial stream of data on the TxD output pin. The receiver accepts serial data on the RxD pin, converts this serial input to parallel format, checks for a start bit, stop bit, parity bit (if any), or break condition, and transfers an assembled character to the CPU during read operations.

1.6 INPUT PORT

The inputs to this unlatched 6-bit port (IPO ~ IP5) can be read by the CPU by performing a read operation. High or low inputs to the input port result in the CPU reading a logic one or logic zero, respectively; that is, there is no inversion of the logic level. Since the input port is a 6-bit port, performing a read operation will result in D7 being read as a logic one and D6 reflecting the logic level of IACK. Besides general- purpose inputs, the inputs to this port can be individually assigned specific auxiliary functions serving the communication channels. DUART-5

TOSHIBA (UC/UP) S4E D m@ 9097249 0024163 793 T TOSHIBA TMP68681/2681 Four change-of-state detectors, also provided within the input port, are associated with inputs IPO, IP1, IPS, and IP3. A high-to-low or low-to-high transition of these inputs lasting longer than 25 to 30 microseconds (best-to-worst case times) will set the corresponding bit in the input port change register (IPCR). The bits are cleared when the register is read by the CPU. Also, the DUART can be programmed so any particular change of state can generate an interrupt to the CPU. The DUART recognizes a level change on an input pin internally only after it has sampled the new level on the pin for two successive pulses of the sampling clock. The sampling clock is 38.4 MHz and is derived from one of the baud-rate generator taps. The resulting sampling period is slightly more than 25 microseconds (this assumes that the clock input is 3.6864 MHz). Subsequently, if the level change occurs on or just before a sampling pulse, it will be recognized internally after 25 microseconds. However, if the level change occurs just. after a sampling pulse, it will be sampled the first time after 25 microseconds. Thus, in this case the level change will not be recognized internally until 50 microseconds after the level change took place on the pin.

1.7 OUTPUT PORT

This 8-bit multi-purpose output port can be used as a general-purpose output port. Associated with the output port is an output port register (OPR). All bits of the output port register can be individually set and reset. A bit is set by performing a write operation at the appropriate address with the accompanying data specifying the bits to be set (one equals set and zero equals no change). Similarly, a bitis reset by performing a write operation at another address with the accompanying data specifying the bits to be reset (one equal reset and zero equals no change). ‘The output port register stores data that is to be output at the output port pins. Unlike the input port, if a particular bit of the output port register is set to a logic one or logic zero the output pin will be at a low or high level, respectively. Thus, a logic inversion takes place internal to the DUART with respect to this register. The outputs are complements of the data contained in the output port register. More information on the address location of the output port register and setting and resetting bits of this register can be found in Table 4.1 and in SECTION 4 PROGRAMMING AND REGISTER DESCRIPTION. Besides general-purpose outputs, the putputs can be individually assigned specific auxiliary functions serving the communication channels. The assignment is accomplished by appropriately programming the channel A and B mode registers (MR1A, MR1B, MR2A, and MR2B) and the output port configuration register (OPCR). More information on the mode registers and output port configuration register can be found in SECTION 4 PROGRAMMING AND REGISTER DESCRIPTION. DUART-6

—Fosnia cucvup) SSCS WED 972NG OOAHIEN Get mMTOSS. TOSHIBA TMP68681/2681 2. SIGNAL DESCRIPTION This section contains a brief description of the input and output signals. Each signal is explained in a brief paragraph about its function with reference (if applicable) to other sections which give greater detail on its use. Table 2.1 provides a quick reference in determining a signal’s pin number, its use as an input or output, whether it is active high or low, and the section in which more information can be found about its operation. Note: The terms assertion and negation will be used extensively. This is done to avoid confusion when dealing with a mixture of “active low” and “active high” signals. The term assert or assertion is used to indicate that a signal is active or true, independent of whether that level is represented by a high or low voltage. The term negate or negation is used to indicate that a signal is inactive or false. Table 2.1 Signal Summary (1/2) a es Ssatmaoraamraea bare [ af ef a a OO lpseee | as | to | 2] eoawete | aw | 8 |p gow] 26 | fst tensterncnowieige | Brae | 9 | Output] tow | a7 | feobwrseecsesone [asa | 6 [nm] Wh | aa | easersteceuson2 | asa | > | mmo | woh | a0 a fen osasa7———-~or [apo er sdrecionaronw auras | 08 [22 [inpwvowtut| woh | 29 | sresonstouwowens | 05 | 18 |npuvowint| nh | 2a | sreionsoowowore | on | 23 _|rpwvowint| woh | aa | Bidirectional-Data Bus Bit 3 [03 | 17 _[inputioutput| High | 29 | [sdrecinatontsomons | 01 | 16 |pwvowiput| won| 29 | * Requires a pullup registor. DUART-7

TOSHIBA (UC/UP) SYED MM 9097245 0024165 bb MMTOS3: TOSHIBA TMP68681/2681 Table 2.1 Signal Summary (2/2) a= ES SE PetesrSannantace'’ | | [howowon| ion | 29 | ChannelATransmitterSerialData | TA | 30 | Output | - | 212 | Channel A Receiver Serial Data | roa | 31 | input | - | 213 | ChannelB Transmitter SerialData_ | txoa | 11 | Output | - | 214 | cans ecerstbaw [moe | —W0 [ ww [= a | tenn [ws | 8 |r P= | tenn |e] |= | | patents | | ef | oteuez | va [ae re [= Pataca tats] oie T= stevia [err [ue [=f a foateouote [one | 2 fone | La | teouats [ons | one |= a | sis ovpine | ore | ar owe Lar tetoupas [ors | | one [=| a | Peaivouputa | ons | ae ov [= a | faitovwurs [ort [ovat Psttoveuo | oro | 29 [our ** May require a pullup resistor, depending upon its programmed function. DUART-8

TOSHIBA (UC/ Mm 5097205 Hnou oe UP) SUE D M@@ 9097249 Oo24iEE 7Te MITOS3 TOSHIBA TMP68681/2681 40pin DIP (TOP VIEW) Rs1 H1@ 40f1 Vee 3 2 39) 1P4 Rs2 13 38[] Ips ra 37) TACK Rs3 15 36 12 nsa (16 ash & to 7 aap) RESET nw fe a3fl x2 DTACK 19 32fl xweuk Rx08 f} 10 311 RxDA 1x08 11 30{] TxOA opt 12 29{1 oP0 op3 113 2efl op2 ops 14 27H op4 op7 15 261 oP6 pt dis 250 po b3 417 2afi 02 bs dis 23) 04 b7 dis 220 06 No (120 2p TRG Figure 2.1 Pin Assignments

21 Vee AND GND

Power is supplied to the DUART using these two signals. Voc is power (+5 volts) and GND is the ground connection.

2.2 CRYSTAL INPUT OR EXTERNAL CLOCK (X1/CLK)

This input is one of two connections to a crystal (see 2.8 CRYSTAL INPUT (X2)) or a connection to an external clock. A crystal or a clock, within the specified limits, must be supplied at all times (see SECTION 5 ELECTRICAL SPECIFICATIONS). If a crystal is used, a capacitor of approximately 10 to 15 picofarads should be connected from this pin to ground.

2.3 CRYSTAL INPUT (X2)

This input is an additional connection to a crystal (see 2.2 CRYSTAL INPUT OR EXTERNAL CLOCK (X1/CLK). If an eternal TTL-level clock is used, this pin should be tied to ground. If a crystal is used, a capacitor of approximately 0 to 5 picofarads should be connected from this pin to ground. DUART-9

| TOSHIBA (UC/UP) S4E D MM 9097249 OO241b7 639 MTOS3 TOSHIBA TMP68681/2681

24 RESET (RESET)

‘The DUART can be reset by asserting the RESET signal or by programming the appropriate command register. A hardware reset, assertion of RESET, clears status registers A and B (SRA and SRB), the interrupt mask register (IMR), the interrupt status register (ISR), the output port register (OPR), and the output port configuration register (OPCR). RESET initializes the interrupt vector register (IVR) to OF yg, places | parallel outputs OPO through OP3 in the high state, places the counter/timer in timer mode, and places channels A and B in the inactive state with the channel A transmitter serial-data output (TxDA) and channel B transmitter serial-data output (TxDB) in the mark (high) state. Software resets are not as encompassing and are achieved by appropriately programming the channel A and/or B command registers. Reset commands can be programmed through the command register to reset the receiver, transmitter, error status, or break-change interrupts for each channel. Refer to SECTION 4 PROGRAMMING AND REGISTER DESCRIPTION for further information.

2.5 CHIP SELECT (CS)

This active low input signal, when low, enables data transfers between the CPU and DUART on the data lines (D0 ~ D7). These data transfers are controlled by read/write (RAW) and the register-select inputs (RS1 ~ RS4). When chip select is high the D0 ~ D7 data lines are placed in the high-impedance state.

2.6 READ/WRITE (R/W)

When high, this input indicates a read cycle, and when low, it indicates a write cycle. A cycle is intiated by assertion of the chip-select input.

2.7 DATA TRANSFER ACKNOWLEDGE (DTACK)

This three-state active low open-drain output is asserted in read, write, or interrupt acknowledge (TACK) cycles to indicate the proper transfer of data between the CPU and DUART.

2.8 REGISTER-SELECT BUS (RSI ~ RS4)

The register-select bus lines during read/write operations select the DUART internal registers, ports, or commands.

2.9 DATABUS(D0~ D7

‘These bidirectional three-state data lines are used to transfer commands, data, and status between the CPU and DUART. D0 is the least-significant bit. DUART-10

TOSHIBA (UC/UP) SHE D M@@ 9097249 OO241b8 575 METOSZ TOSHIBA TMP68681/2681

2.10 INTERRUPT REQUEST (IRQ)

This active low, open-drain output signals the CPU that one or more of the eight maskable interrupting conditions are true.

2.11 INTERRUPT ACKNOWLEDGE (TACK:

This active low input indicates an interrupt acknowledge cycle. If there is an interrupt pending (IRQ asserted) and this pin asserted, the DUART responds by placing the interrupt vector on the data bus and then asserting DIACK. If these is not an interrupt pending (IRQ negated), the DUART ignores the status of this pin.

2.12 CHANNEL A TRANSMITTER SERIAL-DATA OUTPUT (TxDA,

‘This signal is the transmitter serial-data output for channel A. The least-significant bit is transmitted first. This output is held high (mark condition) when the transmitter is disabled, idle, or operating in the local loopback mode. (Mark is high and space is low.) Data is shifted out this pin on the falling edge of the programmed clock source.

2.13 CHANNEL A RECEIVER SERIAL-DATA INPUT (RxDA)

‘This signal is the receiver serial-data input for channel A. The least-significant bit is received first. Data on this pin is sampled on the rising edge of the programmed clock source.

2.14 CHANNEL B TRANSMITTER SERIAL-DATA OUTPUT (TxDB;

This signal is the transmitter serial-data output for channel B. The least-significant bit is transmitted first. This output is held high (mark condition) when the transmitter is disabled, idle, or operating in the local loopback mode. Data is shifted out this pin on the falling edge of the programmed clock source.

2.15 CHANNEL B RECEIVER SERIAL-DATA INPUT (RxDB)

This signal is the receiver serial-data input for channel B. The least-significant bit is received first. Data on this pin is sampled on the rising edge of the programmed clock source.

2.16 PARALLEL INPUTS (IPO ~ IP5:

Each of the parallel inputs (IP0 ~ IP5) can be used as general-purpose inputs. However, each one has an alternate function(s) which is described in the following paragraphs.

2.16.1 IPO

This input can be used as the channel A clear-to-send active low input (CTSA). A change-of-state detector is also associated with this input. DUART-11

TOSHIBA (UC/UP) SHE D MM 9097249 9024349 401 METOS3 TOSHIBA TMP68681/2681

2.16.2 IPL

This input can be used as the channel B clear-to-send active low input (CTSB). A change-of-state detector is also associated with this input.

2.16.3 IP2

‘This input can be used as the channel B receiver external clock input (RxCB), or the counter/timer external clock input. When this input is used as the external clock by the receiver, the received data is sampled on the rising edge of the clock. A change-of-state detector is also associated with this input.

2.16.4 IP3

This input can be used as the channel A transmitter external clock input (TxCA). When this input is used as the external clock by the transmitter, the transmitted data is clocked on the falling edge of the clock. A change-of-state detector is also associated with this input.

2.16.5 IP4

‘This input can be used as the channel A receiver external clock input (RxCA). When this input is used as the external clock by the receiver, the received data is sampled on the rising edge of the clock.

2.16.6 IP5

‘This input can be used as the cahannel B transmitter external clock (IxCB). When. this input is used as the external clock by the transmitter, the transmitted data is clocked on the falling edge of the clock.

2.17 PARALLEL OUTPUTS (OP0 ~ OP7;

Each of the parallel outputs can be used as general-purpose outputs. However, each one has an alternate function(s) which is described in the following paragraphs.

2.17.1 OPO

‘This output can be used as the cannel A active low request-to-send (RTSA) output. When used for this function, it is automatically negated and reasserted by either the receiver or transmitter.

217.2 OPL

This output can be used as the cahnnel B active low request-to-send (RTSB) output. When used for this function, it is negated and reasserted automatically by either the receiver or transmitter. DUART-12

TOSHIBA (UC/UP) S4E D M@@ 9097249 0024170 123 METOS3 TOSHIBA TMP68681/2681

2.17.8 OP2

This output can be used as the channel A transmitter 1 X-clock or 16 X-clock output, or the channel A receiver 1 X-clock output. :

2.17.4 OP3

‘This output can be used as the open-drain active low counter-ready output, the open- drain timer output, the cannel B transmitter 1 X-clock output, or the channel B receiver 1X-clock output.

2.17.5 OP4

This output can be used as the channel A open-drain active-low receiver-ready or buffer-full interrupt outputs (RxRDYA/FFULLA) by appropriately programming bit 6 of mode register 1A.

2.17.6 OP5

‘This output can be used as the channel B open-drain active low receiver-ready or buffer-full interrupt outputs (RxRDYB/FFULLB) by appropriately programming bit 6 of mode register 1B.

2.17.7 OP6

‘This output can be used as the channel A open-drain active low transmitter-ready interrupt output (TxRDYA) by appropriately programming bit 6 of the output port configuration register.

2.17.8 OPT

This output can be used as the channel B open-drain active low transmitter-ready interrupt output (TxRDYB) by appropriately programming bit 7 of the output port configuration register. DUART-13

TOSHIBA (UC/UP) SHE D MM 9097249 0024171 ObT MITOS3. TOSHIBA TMP68681/2681 3. OPERATION This section describes the operation of the transmitter, receiver, and operating modes of the TMP68681 DUART.

3.1 TRANSMITTER

‘The channel A and B transmitters are enabled for data transmission through their respective command registers (refer to SECTION 4 PROGRAMMING AND REGISTER DESCRIPTION). The DUART signals the CPU it is ready to accept a character by setting the transmitter-ready bit in the channel's status register. This condition can be programmed to generate an interrupt request on the IRQ output, an interrupt request for channel A’s transmitter on parallel output OP6, or for channel B’s transmitter on parallel output OP7. When a character is loaded into the transmit buffer (TB), the above conditions for the respective channel are negated. Data is transferred from the transmit holding register to the transmit shift register when it is idle or has completed transmission of the previous character. The transmitter-ready conditions are then asserted again providing one full character time of buffering. Characters cannot be loaded into the transmit buffer while the transmitter is disabled. . The transmitter converts the parallel data from the CPU to a serial bit stream on the transmitter serial-data output pin. It automatically sends a start bit followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits. The least-significant bit is sent first. Data is shifted out the transmit serial data output pin on the falling edge of the programmed clock source. Following the tansmission of the stop bits, if a new character is not available in the tansmit holding register the transmitter serial-data output remains high and the transmitter- empty bit in the status register (SRA and SRB) will be set to a one. Transmission resumes and the transmitter-empty bit is cleared when the CPU loads a new character into the transmit buffer (TBA or TBB). If the transmitter is sent a disable command, it will continue operating until the character in the transmit shift register is completely sent out. The transmitter can be reset through a software command (refer to 2.4 RESET (RESET). If it is reset, operation ceases immediately and must be enabled through the command register before resuming operation. The transmitter can also be forced to send a continuous low condition by issuing a send-break command. If clear-to-send (CTS) operation is enabled, the CTS input (alternate function of IPO or IP1) must be low in order for the character to be transmitted. If it goes high in the middle of a transmission, the character in the shift register is transmitted and TxD then remains in the marking state until CTS again goes low. The state of CTS is ignored by the transmitter when it is to send a break. The transmitter can be programmed to automatically negate the request-to-send (RTS) output (alternate function of OPO and OP1) upon completion of a message transmission. DUART-14

“TOSHIBA (UC/UP) S4E D mm 9097249 ao24172 TT mTOS3 TOSHIBA TMP68681/2681 Note that if the transmitter is programmed to operate in this manner, the RTS output must be manually asserted before a message is to be transmitted. In applications where the transmitter is disabled after transmission is complete, and if appropriately programmed, the RTS output will be negated one bit time after the character in the transmit shift register is completely transmitted.

3.2 RECEIVER

The channel A and B receivers are enabled for data reception through the respective channel’s command register. The channel's receiver looks for a high-to-low (mark-to- space) transition of the start bit on the receiver serial-data input pin. If a transition is detected, the state of the receiver serial-data input pin is sampled each 16X clock for seven and one-half clocks (16X-clock mode) or at the next rising edge of the bit time clock (1 X-clock mode). If the receiver serial data is sampled high, the start bit is invalid and the search for a valid start bit begins again. If receiver serial data is still low, a valid start bit is assumed and the receiver continues to sample the input at one bit time intervals (at the theoretical center of the bit) until the proper number of data bits and the parity bit (if any) have been assembled and one stop bit has been detected. Data on the receiver serial data input pin is sampled on the rising edge of the programmed clock source. During this process the least-significant bit is received first. The data is then transferred to a receive holding register (RHR) and the receiver-ready bit in the status register (SRA or SRB) is set to a one (see Figure 4.1). This condition can be programmed to generate an interrupt request on the IRQ output, an interrupt request for channel A’s receiver on parallel output OP4, or an interrupt request for channel B’s receiver on parallel output OP5. If the character length is less than eight bits, the most-significant unused bits in the receive holding register (RHR) are set to zero. After the stop bit is detected, the receiver will immediately look for the next start bit. However, if a non-zero character was received without a stop bit (framing error) and receiver serial data remains low for one-half of the bit period after the stop bit was sampled, the receiver operates as if a new start bit transition has been detected. ‘The parity error, framing error, overrun error, and received-break conditions (if any) set error and break flags in the status register at the received character boundary and are valid only when the receiver-ready bit (RxRDY) in the status register is set. If a break condition is detected (receiver serial data is low for the entire character including the stop bit), a character consisting of all zeros will be loaded into a receive holding register (RHR) and the received-break bit and the receiver-ready bit in the status register (SRA and SRB) will be set to a one, The receiver serial-data input must return to a high condition for at least one-half bit time before a search for the next start bit begins. DUART-15

TOSHIBA (UC/UP) SHE D Mm@ 9097249 0024173 932 METOS3- TOSHIBA TMP68681/2681 The receiver can detect the beginning of a break in the middle of a character so long as the break persists until at least the next character time. When the break begins in the middle of a character, the receiver will place the damaged character in the receiver FIFO and set the corresponding framing error and receiver-ready status bits. Then, so long as the break persists until the next character time, the receiver will place an all- zeros character in the receiver FIFO and set the corresponding received-break and receiver-ready status bits. A first-in first-out (FIFO) stack is used in each channel's receive buffer logic and consists of three receive holding registers. The receiver bufer (RBA or RBB) is composed of the FIFO and a receive shift register connected to the receiver serial-data input. Data is assembled in the shift register and loaded into the top-most empty receive holding register position of the FIFO. Thus, data flowing from the receiver to the CPU is quadruply buffered. The receiver-ready bit in the status register (SRA or SRB) is set whenever one or more characters are available to be read. A read of the receiver buffer produces an output of data from the top of the FIFO stack. After the read cycle, the data at the top of the FIFO stack and its associated status bits are “popped” and new data can be added at the bottom of the stack by the receive shift register. The FIFO-full status bit set if all three stack positions are filled with data. Either the receiver-ready or the FIFO-full status bits can be selected to cause an interrupt. In addition to the data byte, three status bits (parity error, framing error, and received break) are appended to each data character in the FIFO (overrun is not). By programming the error-mode control bit in the channel’s mode register, status can be provided for “character” or “block” modes. In the “character” mode, status provided in the status register (SRA or SRB) is given on a character-by-character basis and thus applies only to the character at the top of the FIFO. In the “block” mode, the status provided in the status register for the parity error, framing error, and received-break conditions is the logical OR of these respective bits for all characters coming to the top of the FIFO stack since the last reset error command was issued. That is, beginnig at the last reset error command issued, a continuous logical-OR function of corresponding status bits is produced in the status register as each character comes to the top of the FIFO stack. ‘The block mode is useful in applications reguiring the exchange of blocks of information where the software overhead of checking each character’s error flags cannot be tolerated. In this mode, entire messages can be received and only data integrity check is performed at the end of each message. Although data reception in this manner has speed advantages, there are also disadvantages. Since each character is not individually checked for error conditions by the software, if an error occurs within a message the error will not be recognized until the final check is performed. Also, there is no indication of which character(s) is in error within the message. DUART-16

—_— TOSHIBA (UC/UP) SHE D MM 9097245 0024174 879 MTOS3 TOSHIBA TMP68681/2681 In either mode, reading the status register (SR) does not affect the FIFO. The FIFO is “popped” only when the receive buffer (RBA or RBB) is read. Therefore, the status register (SRA or SRB) should be read prior to reading the FIFO. If all three of the FIFO’s receive holding registers are full when a new character is received, that character is held in the receive shift register until a FIFO position is available. If an additional character is received while this state exists, the contents of the FIFO are not affected. But, the character previously in the shift register is lost and the overrun-error status bit will be set upon receipt of the start bit of the new overrunning character. ‘To support control flow capability, a receiver can automatically negate and reassert the request-to-send (RTS) output. If programmed to operate in this mode, the request-to- send output (alternate function of parallel outputs OPO and OP1) will automatically be negated by the receiver when a valid start bit is received and the FIFO stack is full. When a FIFO position becomes available, the request-to-send output will be reasserted automatically by the receiver. By connecting the request-to-send output to the clear-to- send (CTS) input of a transmitting device, overrun errors can be prevented in the receiver. Note that the RTS output must be manually asserted the first time. Thereafter the receiver will control the RTS output. If the FIFO stack contains characters and the receiver is then disabled, the characters in the stack can still be read but no additional characters can be received until the receiver is again enabled. If the receiver is reset, the FIFO stack and all of the receiver status bits, the corresponding output prots, and the interrupt request are reset. No additional characters can be received until the receiver is again enabled.

8.8 LOOPING MODES

Besides the normal operation mode, in which the receiver and transmitter operate independently, each DUART channel can be configured to operate in various looping modes which are useful for local and remote system diagnostic functions. These modes are described in the following paragraphs with further information available in SECTION 4 PROGRAMMING AND REGISTER DESCRIPTION.

8.8.1 Automatic-Echo Mode

In this mode, the channel automatically retransmits the received data on a bit-by-bit basis. The local CPU-to-receiver communication continues normally but the CPU-to- transmitter link is disabled.

3.8.2 Local-Loopback Mode

In this mode, the transmitter output is internally connected to the receiver input. This mode is useful for testing the operation of a local DUART channel. By sending data to the transmitter and checking that the data assembled by the receiver is the same data SSeS DUART-17

TOSHIBA (UC/UP) SYE D MM 9097249 0024175 705 METOS3 TOSHIBA TMP68681/2681 that was sent, correct channel operation can be assured. In this mode the CPU-to- transmitter and CPU-to-receiver communications continue normally.

3.3.3 Remote-Loopback Mode

In this mode, the channel automatically retransmits the received data on a bit-by-bit basis. The local CPU-to-receiver link is disabled. This mode is useful in testing the receiver and transmitter operation of a remote channel. For this mode the remote channel must have its receiver enabled.

3.4 MULTIDROP MODE

‘The channel can be programmed to operate in a wake-up mode used for multidrop or multiprocessor applications. This mode is selected by setting bits three and four in mode register one (MR1). In this mode of operation, a master station’s channel, connected to several slave stations (a maximum of 256 unique slave stations), transmits an address character followed by a block of data characters targeted for one of the slave stations. In this mode, the channel receivers within the slave stations are disabled. Even though the channel receivers within the slave stations may be disabled, they continuously monitor the data stream sent out from the master station. When any address character in the data stream is deteced by the slave station’s channel receivers, each receiver notifies its respective CPU by setting receiver ready (RxRDY) and generating an interrupt if programmed to do so. Each slave station CPU then compares the received address to its station address and enables its receiver if it wishes to receive the subsequent data characters or block of data from the master station. Slave stations which are not addressed continue monitoring the data stream for the next address character. The end of a previous block of data and the start of another block of data is flagged by an address character. After receiving a block of data, the slave station’s CPU may disable the channel receiver and initiate the process again. A transmitted character from the master station consists of a start bit, the programmed number of data bits, an address/data (A/D) bit flag, and the programmed number of stop bits. The address/data bit identifies to the slave station’s channel whether the character should be interpreted as an address character or a data character. The character is interpreted as an address character if the A/D bit is set to a one or interpreted as a data character if it is set to a zero. The polarity of the transmitted address/data bit is selected by programming bit two in mode register one (MR1) to a one for an address character and to a zero for data characters, The mode register should be programmed prior to enabling the transmitter and loading the corresponding data bits into the transmit buffer (TBA or TBB). In the multidrop mode, the receiver continuously monitors the received data stream regardless of whether it is enabled or disabled. If the receiver is disabled, it sets the receiver ready status bit and loads the character into the FIFO receive holding register stack provided the received address/data bit is a one (address tag). DUART-18

—Fosnipa cuc/uP)——~*~«S ESC 7249 OOOH HL TOS TOSHIBA TMP68681/2681 The received character is discarded if the received address/data bit is a zero (data tag). If the receiver is enabled, all received characters are transferred to the CPU by way of the receive holding register stack during read operations. In either case, the data bits are loaded into the data portion of the FIFO stack while the address/data bit is loaded into the status portion of the FIFO stack normally used for parity error (status register bit five). Framing error, overrun error, and break-detection operate normally regardless of whether the receiver is enabled or disabled. Note, the address/data bit takes the place of the parity bit and parity is neither calculated nor checked for characters in this mode. Nevertheless, messages in this mode can still contain error detection and correction information. One way to provide error detection, if 8-bit characters are not required, would be to use software to calculate parity and append it to 5-, 6-, or 7-bit characters. Another way to provide error detection for the entire message would be to use cyclic redundancy checks, or Hamming codes similar to those used in synchronous protocols, perform the check in software, and append the check character(s) to the end of the message.

3.5 COUNTER/TIMER

The 16-bit counter/timer can operate in a counter mode or a timer mode. In either mode, the counter/timer input (clock source) can be programmed to come from several sources and the counter/timer output can be programmed to appear on output port pin OP8. The value (preload value) stored in the concatenation of the counter/timer upper register (CTUR) and the counter/timer lower register (CTLR) can be from $0002 ~ $FFFF and changed at any time. In the counter mode, the counter/timer can be started and stopped by the CPU. Thus, this mode allows the counter/timer to be used as a system stopwatch, a real-time single interrupt generator, or a device watchdog. In the timer mode, the counter/timer runs continuously and cannot be started or stopped by the CPU. Instead, the CPU only resets the counter/timer, Thus, this mode allows the counter/timer to be used as a programmable clock source for channels A and B, periodic interrupt generator, or a variable duty cycle square-wave generator. Upon power-up and after reset, the counter/timer operates in timer mode.

3.5.1 Counter Mode

In the counter mode, the counter/timer counts down from the preload value using the programmed counter clock source. The counter clock source can be either the channel A transmitter clock, the channel B transmitter clock, the external clock on the X1/CLK pin divided by sixteen, or an external clock on the input port pin IP2. The CPU can start and stop the counter and can read the count value (CUR : CLR). When a read at the start counter command address is performed, the counter initializes itself with the preload value and begins a countdown sequence. Upon reaching $0000 (terminal count), the counter sets the counter/timer-ready bit in the interrupt status register (ISR [3]), rolls over from $0000 to $FFFF, and continues counting. SSSSSSSSsseessesSSSSsSsSSSSSSsS DUART-19

TOSHIBA (UC/UP) S4E D mM@ 9097249 0024177 588 METOS3 TOSHIBA TMP68681/2681 ‘The counter can be programmed to generate an interrupt request for this condition on the IRQ output pin OP3. If the preload value is changed by the CPU, the counter will not recongnize the new value until it receives the next start counter command (and must reinitialize itself). When a read at the stop counter command address is performed, the counter stops the countdown sequence and clears ISR [3]. The count value should only be read while the counter is stipped. This is because only one of the count registers (either CUR or CLR) can be read at a time and if the counter is running, a decrement of CLR that requires a borrow form the CUR could take place between the two reads. ~

3.5.2 Timer Mode

In the timer mode, the counter/timer generates a square-wave output derived from the programmed timer input (clock source). The timer clock source can be the external clock on the X1/CLK input pin divided by one or sixteen, or it can be an external input on input port pin IP2 divided by one or sixteen. The square wave generated by the timer has a period of 2X (preload value) x (period of clock source), is available as a clock source for both communications channels, and can be programmed to appear on output pin OP3. The timer runs continuously and cannot be started or stopped by the CPU. Because the timer cannot be stopped, the count value (CUR : CLR) should not be read. When a read at the start counter command address is performed, the timer terminates the current countdown sequence, inverts its output, reinitializes itself with the preload value, and begings a new countdown sequence. Upon reaching $0000 (terminal count), the timer inverts its output, reinitializes itself with the preload value, and repeats the countdown sequence. After reaching terminal count this time, the timer sets the counter/timer-ready bit in the interrupt status register (ISR [8]), inverts its output, reinitializes itself with the preload value, and begins a new countdown sequence. The timer can be programmed to generate an interrupt request for this condition on the IRQ output. If the preload value is changed by the CPU, the timer will not recognize the new value until it reaches the next terminal count (and must reinitialize itself). This feature is very useful when generating variable duty cycle square waves. When a read at the stop counter command address is performed, the timer clears ISR [3] but does not stop. Because in timer mode the counter/timer runs continuously, it should be completely configured (preload value loaded and start counter command issued) before programming the timer output to appear on OP3. DUART-20

TOSHIBA (UC/UP) SHE D MM 9097249 0024178 414 MBTOS3 TOSHIBA . TMP68681/2681 4, PROGRAMMING AND REGISTER DESCRIPTION This section contains a brief discussion on programming certain registers of the DUART with a detailed description of each register and its function.

41 PROGRAMMING

The operation of the DUART is progrmmed by writing control words into the appropriate registers. Operational feedback is provided by way of the status registers which can be read by the CPU. The DUART register address and address-triggered commands are described in Table 4.1. Figure 4.1 (located on foldout page at the end of this document) illustrates a block diagram of the DUART from a programming standpoint and details the register configuration for each block. Table 4.1 and Figure 4.1 should be referred to during the discussion of the programming features of the DUART. The locations marked “do not access” should never be read during normal operation. They are used by the factory for test purposes. Table 4.1 Register Addressing and Address - Triggered Commands falafel [wenn ind [ele [o[e fimatamn ———_waininny [uomoawa on [Te [e [sumtin ow [aoasaecnaira ea | [ee [ [© foonsscnr eames | On Le [To |e fnentorcunniaie wen atnveowasiar wo | [To fiwrnsonsnaie craton [Tr [ene cram tem [cnertaw pei [TTT fone consteane ea [omrineionrtsie eu | oe 2 oo oo Oe

1 Input Port (Unlatched) Output Port Configuration

PLT [e[ ferreneore Parmenter oe | PTET [> froreonecomae ag RS oe TeNinlgird eiblr and poutie indetee hommes oc reeetias ar meee. Reading tis eaten wil ary ++ SUES triggered commands, DUART-21

7 >) mm 9097249 0024179 350 MITOS3 TOSHIBA (UC/UP) SUE TOSHIBA . TMP68681/2681 Table 4.2 is provided to illustrate the various input port pin functions. More detailed information can be obtained from Table 4.5 and 4.2 REGISTER DESCRIPTION. ‘Table 4.2 Programming of Input Functions [cewarnpow [ont owes [orto __ounon___[oveut [ove | Detector External Counter ACR [6:4]* = 000 1X Clock input External Timer ACR [6:4]* = 100 16X Clock Input External Timer ACR (6:4]* = 101 1X Clock input fea [emma | iY dd Fe A EC A OC Note: Default refers to the function the input port pins perform when not used in one of the other modes. Only those functions which show the register programming are available for use. * In these modes, because IP2 is used for the counter/timer-clock input, it is not available for use as the channel B receiver-clock input. DUART-22

TOSHIBA (UC/UP) SHE D Ml 9097249 0024180 072 mMTOS] TOSHIBA TMP68681/2681 Table 4.3 is provided to illustrate the various output port pin functions. More detailed information can be obtained from Table 4.5 and 4.2 REGISTER DESCRIPTION. Table 4.3 Programming of Output Port Functions a a fe [se ee ss Purpose ‘MR28(5)=0 | MR2A[5]=0 eee eli eb Output ACR IG] = 1* ee a [cmt [PP overie [ Ee GG Cc femora | forse | frmore_fovamew [PP i i = i = ek a a a CC A Ge a Note: Only those funetions which show the register programming are available for use. * Pin requires a pullup resistor if used for this function. DUART-23

TOSHIBA (UC/UP) Sue D mm 9097249 024181 TOF METOS3 TOSHIBA TMP68681/2681 Table 4.4 is provided to illustrate the various clock sources which may be selected for the counter and timer. More detailed information can be obtained from Table 4.5 and 4.2 REGISTER DESCRIPTION. Table 4.4 Selection of Clock Sources for the Counter and Timer Modes [=o [=i] | External InputviainputPortPin2(Ip2)____—[_—00__—| External inputvia input PortPin 2 (ra) [oo itil Ar Port Pin 2 (122) aa i | ae ee | XAICLK and X2 Inputs XA/CLK and X2 Inputs a XVCLK Input Pin Note: Only those functios which show the register programming are available for use Care should be exercised if the contens of a register is changed during receiver/transmitter operation since certain changes may cause undesired results. For example, changing the number of bit-per-character while the transmitter is active may cause the transmission of an incorrect character. The contents of the mode registers (MR), the clock-select register (CSR), the output port configuration register (OPCR), and bit 7 of the auxiliary control register (ACR [7]) should only be changed after the receiver(s) and transmitter(s) have been issued software Rx and Tx reset commands. Similarly, certain changes to the auxiliary control register (ACR bits six through four) should only be made while the counter/timer (C/T) is not used (i.e, stopped if in counter mode, output and/or interrupt masked timer mode). Mode registers one and two of each channel are accessed via independent auxiliary pointers. The pointer is set to channel A mode register one (MR1A) and channel B mode register one (MR1B) by RESET or by issuing a “reset pointer” command via the corresponding command register. Any read or write of the mode register while the pointer is at MR1A or MR1B switches the pointer to channel A mode'register (MR2A) or channel B mode register two (MR2B). The pointer then remains at MR2A or MR2B. So, subsequent accesses will address MR2A or MR2B, unless the pointer is reset to MR1A or MRI1B as described above. Mode, command, clock-select, and status registers are duplicated for each channel to provide total independent operation and control. Refer to Table 4.5 for descriptions of the register and input and output port bits. DUART-24

TOSHIBA (UC/UP) SHE D MM 9097249 0024142 945 mETOS3 TOSHIBA TMP68681/2681 Table4.5 Register Bit Formats (1/6) CHANNEL A MODE REGISTER 1 (MR1A) AND CHANNEL B MODE REGISTER 1 (MR1B) Bit Bité Bits Bita Bit Bitz it ft With Parity O= Even ~---120dd O=Disabled | 0=RxRDY | 0=Char | 00= With Parity Force Parity 0025

1 Enabled 1=FFULL | 1=Block | O1= Force Parity 0=LOW 0156

10= NoParity a 1SHIGH 1057 f= Multidrop ‘Multidrop Mode Wa8 Mode* 0= Data t= Address * ‘Tho parity bit is used as the address/data bit in multidrop mode. CHANNEL A MODE REGISTER 2 (MR2A) AND CHANNEL B MODE REGISTER 2 (MR28) Bit7Z Bit. Bits ita sits sit2 git! Bito Ir 0=Disabled 0= Disabled 00= Normal 1 =Enabled 1=Enabled a pits seit 01= Automatic Echo Character Character 10= Local (2) 0000= 0.563 1.063 Loopback (1) Ooo1= — 0.625 4.125 11= Remote Q) 0010 0.688 1.188 Loopback @) 0011= 0.750 1.250 (4) 0100= 0.813 1.313 () 0101= 0.875 1375 Note: Ifan external 1X clock is used for the (@) 0110= 0.938 1438 transmitter, MR2 bit 3=0 selects one stop @ O1tt= — 1.000 411500 bitand MR2 bit 3=1 solects two stop bits (@) 1000= 1863 11563 tobe transmitted. (9) 1001= 1.625 1.625 (8) 101t= 1.750 1.750 (Q t100= 1,813, 1.813 (2) 1140= 1,938 1.938 () 1111= 2.000 2.000 DUART-25

TOSHIBA (UC/UP) Su— D M@@ 9097249 0024143 641 METOS3 TOSHIBA TMP68681/2681 Table 4.5 Register Bit Formats (2/6) CLOCK-SELECT REGISTER A (CSRA) Bit? Bit Bi ‘Bit4 Bit3 Bit2 Bitt Bito —Baud Rate Baud Rate _ Set 1 Set 2 Set Set2 0000 50 La 0000 50 75 ooo1 110 110 ooo1 110 110 0010 134.5 134.5 0010 134.5 134.5 oo11 200 150 oo11 200 150 0100 300 300 0100 300 300 0101 600 600 0101 600 600 1000 2400 2400 1000 2400 2400 1o1t 9600 9600 1011 9600 9600

1101 Timer Timer 1101 Timer Timer

clock except when CSRA seven 16X except when CSRA bits through four equal 1111. three zero equal 1111, CLOCK-SELECT REGISTER B (CSRB) ‘Bité Bits Bit Bit3 Bit2 it 1 | Baud Rate I —Baud Rate ACRBit7= ACR Bit 7=1 ACR Bit7=0 ACRBit7=1 ooo1 110 110 0001 110 110 0010 134.5, 134.5 0010 134.5 134.5 o101 600 600 o10t 600 600 o110 1200 1200 o110 1200 1200 ord 1050 2000 Orit 1050 2000 1001 4800 4800 1001 4800 4800 1010 7200 1800 1010 7200 1800 1011 9600 9600 1001 9600 9600 1100 38.4K 19.2K 1100 38.4K 19.2K

1109 Timer Timer 1101 Timer Timer

Note: Receiver clock is always a 16x Note: Transmiter clock is always a clock except when CSRB bits 16X except when CSRB bits seven through four equal 1111, throe zero equal 1111. DUART-26

TOSHIBA (UC/UP) SHE D MM 9097249 0024184 718 METOS3 TOSHIBA TMP68681/2681 Table 4.5 Register Bit Formats (8/6) CHANNEL A COMMAND REGISTER (CRA) AND CHANNEL B COMMAND REGISTER (CRB) Bit itt sits pita Bit3 big rt # 0 x 000 NoCommand 00 No Action, Stays in 00 NoAction, Staysin

001 Reset MR Pointer toMR1 Present Mode Present Mode

010 Reset Receiver 01 Transmitter 01 Receiver Enabled

011 Reset Transmitter Enabled 10 Receiver Disabled

100 Reset Errot Status 10 Transmitter 11 Don’t Use,

101 Reset Channel's Break- Disabled Indeterminated

Change Interrupt 14 Don't Use,

110 Start Break Indeterminated

111 Stop Break

• Bitseven is not used and may be set to either zero or one, CHANNEL A STATUS REGISTER (SRA) AND CHANNEL B STATUS REGISTER (SRB) Received Framing Pariaty ‘Overrun xem TeRDY FFULL RxRDY Bread Error Error Error Bit7* Bité* aits* Bite ita Bitz ait ito O=No O=No O=No 0=No o=No | o=No | o=No | 0=No t=Yes 1=Yes 1=Yes i= Yes teves | 1=ves | 1=Yes | t=Yes * ‘Those status bits are appended to the corresponding data charactor in the receive FIFO and are valid only when the RxRDY bit set. A read of the status register provides these bits (seven through five) from the top of the FIFO together with bits four through zero. These bits are cleared by a reset error status command. In character mode, they are discarded when the corresponding data character is read from the FIFO, OUTPUT PORT CONFIGURATION REGISTER (OPCR) [om [ow [oom Tom [om | om | O=OPR [7] 0=OPR (6) O= OPR[S) O= OPR [4] 00 = OPR([3} 00 = OPR[2] taTeRoye | t=TxROYA | i= RxRDYe/ | t= RxROYA’ | 01 = CT Output* 01 = TxCA (X16) FFULLB FFULLA } 10 = TxCB(X1) 10 = TxCA(K1) 11 = RxCB(X1) 14 = RxCA (XI) * IF OP3 is to be used for the timer output, the counter/timer should be programmed for timer (ACR [6]=1), the counter/timer preload registers (CTUR and CTLR) initialized, and the start counter command issued before setting OPCR (3:2)=01. Note: OP1 and OPO can be used as transmitter and receiver RTS control lines by appropriately programming the mode registers (MRI [7] for the receiver RxRTX, and MR2 [5] for the transmitter TxRTS). OP1 is used for channel B's RTS control line and OPO for channel A's RTS control line. When OPI and OPO are not used for RTS control, they may be used as general-purpose outputs. (See Table 4.3.) DUART-27

TOSHIBA (UC/UP) BYE D mm an4720q Gran; = moo 249 0024185 654 mTOS3 TOSHIBA TMP68681/2681 Table 4.5 Register Bit Formats (4/6) OUTPUT PORT REGISTER (OPR) [om [om [ow [ow [om [om [on [om AUXILIARY CONTROL REGISTER (ACR) Select® Mode and Source 1P3 IRQ 1p2 IRQ 1 TRO ipo TRG Bit7Z Bi Bits Bit4 Bit Bit2 Bit Bito Mode Clock Source O=Seti 000 Counter External (IP2)** 0= Disabled |0= Disabled |0= Disabled |0= Disabled j=Set2 001 Counter TxCA- 1X Clock of Channel A i= Enabled | 1= Enabled |1= Enabled | 1= Enabled ‘Transmitter

010 Counter TxCB- 1X Clock of Channel B

‘Transmitter

011 Counter Crystal or External

‘Clock (X1/CLK) Divided by 16

100 Timer External (IP2)** * *

101 Timer External (IP2)

Divided by 16****

110 Timer Crystal or External

‘Clock (X V/CLK) 111° Timer Crystal or External Clock (X1/CLK) Divided by 16 Should only be afterd while the counter/timer is not in use (i.e, stopped if in counter mode, output and/or interrupt masked if in timer mode). * Delta is equivalent to change-of-state. wee In tees modes, because IP2 is used for the counter/timer clock input, it is not available for use as the channel B DUART-28

TOSHIBA (UC/UP) S4E D MM 9097249 00241486 S50 METOS3 TOSHIBA TMP68681/2681 ‘Tabel 4.5 Register Bit Formats (5/6) INPUT PORT CHANGE REGISTER (IPCR) Detected | Detected | Detected | Detected | ‘eve! tel bevel ‘evel 1P3 Pz Pt IPO Bit? Bit 6 Bits Bita Bita Bit2 Bit Bito 0=No | 0=No | O=No | O=No | O=Low | o=Low | O=Low | O=Low 1=Yes 1=Yes 1=Yes 1=Yes 1=High 1=High 1=High 1=High *Delta is equivalent to change-oF-state, INTERRUPT STATUS REGISTER (ISR) Input Counter/ Delta | RxRDYB/ ; Delta | RxRDYA/ Port BreakB | FFULLB TXRDYB | Timer Breaka | FeuiLa | T*ROYA change Ready Bit7 Bité Bit 5 pita Bits Bit2 itt Bito O=No | O=No | O=No | O=No | O=No | O=No | G=No | O=No i=Yes | i=Yes | 1=Yes | t=Yes | 1=Yes | 1=Yes | 1=Yes | 1=Yes INTERRUPT MASK REGISTER (IMR) Input Counter/ Port pees | ere | txOvB | Timter | gee, | ROU | txrova Change ho TRS TRO Ready ao Te IRQ Le] RO a Bit7 Bit6 Bits Bita Bita Bit2 sit Bito 0=Masked | 0= Masked | 0 = Masked | 0 = Masked | 0 = Masked | 0 = Masked | 0 = Masked | 0 = Masked t=Pass | t=Pass |t=Pass | t=Pass |1=Pass | tePass | 1=Pass | 1=Pass DUART-29

TOSHIBA (UC/UP) SHE D MM 9097249 0024187? 427 METOS3 TOSHIBA TMP68681/2681 Tabel4.5 Register Bit Formats (6/6) COUNTER/TIMER UPPER REGISTER (CTUR) COUNTER/TIMER LOWER REGISTER (CTLR) INTERRUPT VECTOR REGISTER (IVR) INPUT PORT [[=Tata[e[eTale] [ser [aeons [ee [ae [|] * Bit seven has no external pin, Upon reading the input port, bit seven will always be read as a one, ¥* Bit six has no external pin. Upon reading the input port, bit six will reflect the current logic level of ACK. OUTPUT PORT fe [=[=[=[m[w[@=|| Bitz Bite Bits Bita Bit3 Bit2 Bit1 BitO opR(7]_| OPRi6) | OPRI5] | OPR{4] | OPRI3] | OpRi2) | OPRIt] | OPRIO} DUART-30

HIBA (UC/UP) SHE D M@ 9097249 0024188 343 M@TOS3 TOSHIBA TMP68681/2681

42 REGISTER DESCRIPTION

‘The following paragraphs provide a detailed description of each register and its function.

4.2.1 Channel A Mode Registerl (MR1A)

The channel A mode register one (MRIA) is accessed when the channel A mode register pointer points to MR1. The pointer is set to MR1 by RESET or by a “set pointer” command applied via control register A. After reading or writing MR1A, the pointer will point to channel A mode register two (MR2A).

4.2.11 CHANNEL A RECEIVER REQUEST-TO-SEND CONTROL — MR1A [7]

This bit controls the negation of the channel A request-to-send (RTSA) parallel output (OPO) by the receiver. This output is normally asserted by setting OPR [0] and negated by clearing OPR [0]. MR1A [7]=1 causes RTSA to be negated upon receipt of a valid start bit if the channel A FIFO is full. RTSA will be reasserted when an empty FIFO position is available. This feature can be used for flow control to prevent overrun in the receiver by using the RTSA output signal to control the clear-to-sent CTS input of the transmitting device. 4.2.1.2: CHANNEL A RECEIVER-INTERRUPT SELECT-MRIA [6] ‘This bit selects either the channel A receiver-ready status (RxRDY) or the channel A FIFO full status (FFULL) to be used for CPU interrupts. It also causes the selected bit to be output on the parallel output OP4 if OP4 is programmed as an interrupt output via the output port configuration register (OPCR).

4.2.1.8 CHANNEL A ERROR MODE SELECT — MR1A[5]

This bit selects the operating mode of the three FIFOed status bit (framing error (FE), parity error (PE), and received break (RB)) for channel A. In the “character” mode, status provided in the status register is given on a character-by-character basis and applies only to the character at the top of the FIFO. In the “block” mode, the status provided in the status register for these bits is the accumulation (logical OR) of the status for all characters coming to the top of the FIFO since the last reset error status command for channel A was issued.

4.2.14 CHANNEL A PARITY MODE SELECT — MRI1A [4:3]

If “with parity” or “force parity” is selected, a parity bit is added to the transmitted character and the receiver performs a parity check on incoming data. MRIA [4:3]=11 selects channel A to operate in the multidrop mode described in 3.4 MULTIDROP MODE. DUART-31

TOSHIBA (UC/UP) S4E D mm 9097249 0024289 2TT METOS3 TOSHIBA TMP68681/2681

4.2.1.5 CHANNEL A PARITY TYPE SELECT-MRIA [2]

‘The bit selects the parity type (odd or even) if the “with parity” mode is programmed by MRI1A [4:3], and the polarity of the forced parity bit if the “force parity” mode is programmed. It has no effect if the “no parity” mode is programmed. In the multidroup mode, it configures the transmitter for address character transmission or data character transmission.

4.2.1.6 CHANNEL A BITS-PER-CHARACTERSELECT — MRI1A [1:0]

This field selects the number of data bits per character to be transmitted and received, The character length does not include the start, parity, and stop bits. 4.2.2. Channel A Mode Register 2 (MR2A) ‘The channel A mode register two (MR2A) is accessed when the channel A mode register pointer pints to mode register two (MR2A), which occurs after any access to channel A mode register one (MR1A). Accesses to MR2A do not change the pointer. 4.2.2.1. CHANNEL A MODE SELECT-MR2A [7:6] Each channel of DUART can operate in one of four modes:normal, automatic echo, : local loopback, or remote loopback. MR2A [7:6]=00 is the normal mode, with the transmitter and receiver operating independently. MR2A [7:6]=01 places the channel in the automatic-echo mode, which automatically retransmits the received data. The following conditions are true while in the automatic-echo mode: 1. Received data is reclocked and retransmitted on the channel A transmitter serial-data output. 2. The receive clock is used for the transmitter. 3. The receiver must be enabled, but the transmitter need not be enabled. 4. The channel A transmitter ready and transmitter empty status bits are inactive. 5. The received parity is checked, but is not recalculated for transmission, i.e, the transmitted parity bit is as received. 6. Character framing is checked, but the stop bits are retransmitted as received. 7. A received break is echoed as received until the next valid start bit is detected. 8. CPU-to-receiver communication continues normally, but the CPU-to- transmitter link is disabled. DUART-32

a TOSHIBA (UC/UP) S4E D MM 9097249 002414590 TLL METOS3 TOSHIBA TMP68681/2681 Two diagnostic modes can also be configured. MR2A [7:6]=10selects the first of these, the local-loopback mode. In this mode: 1, The transmitter output is internally connected to the receiver input. 2, The transmit clock is used for the receiver. 3. Thechannel A transmitter serial-data output is held high. 4, The channel A receiver serial-data input is ignored. 5. The transmitter must be enabled, but the receiver need not be enabled. 6. CPU-to-transmitter and receiver communication continue normally. The second diagnostic mode is the remote-loopback mode, selected by MR2A (7:6]=11. In this mode: 1. Received data is reclocked and retransmitted on the channel A transmitter serial-data output. 2, The receive clock is used for the transmitter. 3, Received data cannot be read by the local CPU, and the error status conditions are inactive. 4. The received parity is not checked and is not recalculated for transmission; i.e, the transmitted parity bitis as received. 5. Thereceiver must be enabled. 6. Character framing is not checked, and the stop bits are retransmitted as received. 7. Areceived break is echoed as received until the next valid start bitis detected. Switching between modes should only be done while the channel is disabled. ‘This is because the selected mode will be activated immediately upon mode selection, even if this occurs in the middle of a received or transmitted character. Similarly, if a mode is deselected, the device will switch out of the mode immediately. An exception to this is switching out of automatic-echo or remote-loopback modes. If the deselection of these modes occurs just after the receiver has sampled the stop bit (indicated in automatic echo by assertion of receiver ready), and the transmitter is enabled, the transmitter will remain in automatic-echo mode until the entire stop bit has been retransmitted. eee DUART-33

“TOSHIBA (UC/UP) SHE D MM@ 9097249 0024391 958 METOS3 TOSHIBA TMP68681/2681 4.2.2.2. CHANNEL A TRANSMITTER REQUEST-TO-SEND CONTROL — MR2A [5] This bit controls the negation of the channel A transmitter request-to-send (RTSA) paralled output (OPO) by the transmitter. This output is normally asserted by setting OPR [0] and negated by clearing OPR [0]. In applications where the transmitter is disabled after transmission is complete, programming MR2A [5]=1 causes OPR [0] to be cleared automatically one bit time after the characters in the channel A transmit shift register and in the transmit holding register, if any, are completely transmitted, including the programmed number of stop bits. This feature can be used to automatically terminate the transmission of a message as follows: 1. Program the DUART for the automatic-reset mode: MR2A [5]=1. 2. Enable the transmitter. 8. Assert channel A transmitter request-to-send control: OPR[0]=1. 4. Send the message, 5. Disabel the transmitter after the transmitter-ready bit becomes asserted (SRA [2]=1. 6. The last character will be transmitted and OPR [0] will be cleared one bit tiem after the last stop bit, causing the channel A transmitter request-to-send control to be negated.

4.2.2.8 CHANNEL A CLEAR-TO-SEND CONTROL — MR2A[4]

If this bit is zero, channel A clear-to-send control (CTSA)has no effect on the transmitter. If this bit is a one, the transmitter checks the state of CTSA (IPO) each time it is ready to send a character. If IPO is asserted (low), the character is transmitted. If it is negated (high), the channel A transmitter serial-data output remains in the marking state and the transmission is delayed until CTSA goes low. Changes in the CTSA while acharacter is being transmitted do not affect the transmission of that character.

4.2.2.4 CHANNEL A STOP BIT LENGTH SELECT-MR2A [38:0]

This field programs the length of the stop bit appended to the transmitted character. Stop bit lengths of nine-sexteenths-to-one and one and nine-sexteenths-to-two (1 9/162) bits, in increments of one-sixteenth bit, can be programmed for character lengths of six, seven, and eight bits. For a character length of five bits, one and one-sixteenth-to-two (1 1/162) stop bits can be programmed in increments of one-sexteenth bit. The receiver, in all cases, only checks for a “mark” condition at the center of the first stop bit position (one bit time after the last data bit, or after the parity bit if parity is enabled). If an external 1X clock is used for the transmitter, MR2A [3]=0 selects one stop bit and MR2A [3]=1 selects two stop bits to be transmitted. DUART-34

TOSHIBA (UC/UP) S4E D MM 9097249 0024192 894 MTOS3 TOSHIBA TMP68681/2681

4.2.3 Channel B Mode Register 1 (MR1B)

The channel B mode register one (MRIB) is accessed when the channel B mode register pointer points to mode register one (MR1). The pointer is set to MR1 by RESET or by a “set pointer” command applied by way of the channel B command register. After reading or writing MR1B, the pointer will point to the channel B mode register two (MR2B). The bit definitions for this register are identical to the bit definitions for MR1A, except that all control actions apply to the channel B receiver and transmitter and their corresponding inputs and outputs.

4.2.4 Channel B Mode Register 2 (MR2B)

The channel B mode register two (MR2B) is accessed when the channel B mode register pointer points to mode register two (MR2), which occurs after any access to channel B mode register one (MR1B). Accesses to MR2B do not change the pointer. The bit definitions for this register are identical to the bit definitions for MR2A, except that all control actions apply to the channel B receiver and transmitter and their corresponding input and outputs.

4.2.5 Channel A Clock-Select Register (CSRA)

The following paragraphs provide a detailed description of the channel A clock-select register.

4.2.5.1 CHANNEL A RECEIVER CLOCK-SELECT — CSRA [7:4]

This field selects the baud-rate clock for the channel A receiver form a set of baud rates. There are two sets of baud rates dependent upon bit seven of the auxiliary control register. These sets, with their respective baud rates, are shown in Table 4.5. Set one is selected if ACR [7]=0 and set two is selected if ACR[7]=1. The receiver clock is always 16 times the baud rate given in the table except for CSRA [7:4]=1111, when an external 1X clock is used. When CSRA [7:5]=111, the external clock connected to parallel input IP4 is used by the receiver.

4.2.5.2 CHANNEL A TRANSMITTER CLOCK SELECT — CSRA [3:0]

This field selects the baud-rate clock for the channel A transmitter from a set of baud rates. As with the receiver clock, there are two sets of baud rates dependent upon bit seven of the auxiliary control register. These sets, with their respective baud rates, are shown in Table 4.5. The transmitter clock is always 16 times the baud rate given in the table except for CSRA [3:0]=1111, when an external 1X clock is used. When CSRA [8:1] =111, the external clcok connected to parallel input IP3 is used by the transmitter. DUART-35

TOSHIBA (UC/UP) nee SUE ~ D mm 9097249 9024193 220 METOS3 TOSHIBA TMP68681/2681

4.2.6 Channel B Clock-Select Register (CSRB)

‘The follwing paragraphs provide a detailed description of the channel B clock-select register. 4.2.6.1. CHANNEL B RECEIVER CLOCK SELECT — CSRB [7:4] This field selects the baud-rate clcok for the channel B transmitter from a set of baud rates. There are two sets of baud rates dependent upon bit seven of the auxiliary control register. These sets, with their respective baud rates, are shown in Table 4.5. Set one is selected if ACR [7]=0 and set two is selected if ACR [7]=1. The receiver clock is always 16 times the baud rate given in the table except for CSRB [7:4]=1111, when an external 1X clock is used. When CSRB [7:5]=111, the external clock connected to parallel input TP2 is used by the receiver. 4.2.6.2. CHANNEL B TRANSMITTER CLOCK SELECT — CSRB [3:0] ‘The field selects the baud-rate clock for the channel B transmitter from a set of baud | rates. As with the receiver clock, there are two sets of baud rates dependent upon bit seven of the auxilary control register. These sets, with their respective baud rates, are shown in Table 4.5. The transmitter clock is always 16 times the baud rate given in the table except of CSRB [3:0]=111, when an external 1X clock is used. When CSRB [8:1] =111, the external clock connected to parallel input IP5 is used by the transmitter.

4.2.7 Channel A Command Register (CRA)

The channel A command register (CRA) is a register used to supply commands to channel A. Multiple commands can be specified in a single write to CRA as long as the commands are non-conflicting; e.g, the “enable transmitter” and “reset transmitter” commands cannot be specified in a single command word.

4.2.7.1 CRA[7]

This bit is not used and may be set to either zero or one. DUART-36

a TOSHIBA (UC/UP) SHE D M@ 9097249 0024194 bb? METOSS TOSHIBA TMP68681/2681 4.2.7.2. CHANNEL A MISCELLANEOUS COMMANDS — CRA [6:4] ‘The encoded value of this field may be used to specify a single command as follows: CRA [6:4] Command 000 Nocommand. . 001 Reset Mode Register Pointer. This command causes the channel A mode register pointer to point to mode register one. 010 Reset Receiver. This command resets the channel A receiver. The receiver is immediately disabled, the RxRDY and FFULL bits in the SRA are cleared, and the RxFIFO pointer is reinitialized. All other registers are unaltered. This command should be used in lieu of the receiver disable command whenever the receiver configuration is to be changed, as it places the receiver in a guaranteed known state. 011 Reset Transmitter. This command resets the channel A transmitter. The transmitter is immediately disabled and the TxRDY and TxEMT bits in the SRA are cleared. All other registers are unaltered. This command should be ~ used in lieu of the transmitter disable command whenever the transmitter configuration is to be changed, as it places the receiver in a guaranteed known state. 100 Reset Error Status. This command clears the channel A received break (RB), parity error (PE), framing error (FE), and overrun error (OE) flags in the status register (SRA [7:4]). This command is used in the character mode to clear OE status (RB, PE, and FE bits will also be cleared) and is used in the block mode to clear all error status flags after a block of data has been received. 101 Reset Channel A Break Change Interrupt. This command causes the channel A break detect change bit in the interrupt status register (ISR [2]) to be cleared to zero. 110 Strat Break. This command forces the channel A transmitter serial-data output (TxDA) low (spacing). If the transmitter is empty, the start of the break condition will be delayed up to two bit times. If the transmitter is active, the break begins when transmission of the character is completed. Ifa character is in the transmit holding register, the start of the break will be delayed until that character or any others loaded subsequently are transmitted. The transmitter must be enabled for this command to be accepted. The state of the OTS input is ignored for this command. DUART-37

TOSHIBA (UC/UP) S4E D M@@ 9097249 GoOe2415S5 S5T3 METOS3 TOSHIBA TMP68681/2681 111 Stop Break. The channel A transmitter serial-data output (TxDA) line will go high (marking) within two bit times. TxDA will remain high for one bit time before the next character, if any, is transmitted.

4.2.7.3 CHANNEL A TRANSMITTER COMMANDS — CRA [8:2]

The encoded value of this field specifies commands for the transmitter as follows: CRA [8:2] Command 00 No action is taken. The transmitter stays in its present mode. If the transmitter was enabled it remains enabled, if disabled it remains disabled. OL Enable Transmitter. This command enables operation of the channel A transmitter. ‘The transmitter-ready status bit will be asserted.

10 Disable Transmitter, This command terminates transmitter operation and

resets the transmitter-ready and transmitter-empty status bits. However, if a character is being transmitted when the transmitter is disabled, the transmission of the character is completed before assuming the inactive state. | il Do not use. The result of this is indeterminate. ) 4.2.74 CHANNEL A RECEIVER COMMANDS — CRA [1:0] The encoded value of this field specifies commands for the receiver as follows: CRA [1:0] Command 00 No action is taken. The receiver stays in its present mode. If the receiver was enabled it remains enabled, if disabled it remains disabled. 01 Enable Receiver. This command enables operation of the channel A receiver. If the DUART is not in the multidrop mode, this command also forces the receiver into the search-for-start bit state. 10 Disable Receiver. This command terminates operation of the receiver immediately-a character being received will be lost. The command has no effect on the receiver status bits or any other control register. If the DUART has been programmed to operate in the local loopback or multidrop mode, the receiver operates even if it is disabled. Refer to SECTION 8 OPERATION for further information. ll Do not use. The result of this is indeterminate. DUART-38

TOSHIBA (UC/UP) SHE D MM 9097249 02419 43T MM TOS3 TOSHIBA TMP68681/2681

4.2.8 Channel B Command Register (CRB)

‘The channel B command register (CRB) is a register used to supply commands to channel B. Multiple commands can be specified in a single write to CRB as long as the commands are nonconflicting; e.g., the “enable transmitter” and “reset transmitter” command cannot be specified in a single command word. ‘The bit definitions for this register are identical to the bit definitions for channel A command register, except that all control actions apply to the channel B receiver and transmitter and their corresponding inputs and outputs.

4.2.9 Channel A Status Register (SRA)

‘The following paragraphs provide a detailed description of the channel A status register.

4.2.9.1 CHANNEL A RECEIVED BREAK-SRA [7]

‘This bit indicates an all zero character of the programmed length has been received without a stop bit. This bit is valid only when the RxRDY bit is set (SRA [0]=1). Only a single FIFO position is occupied when a break is received;further entries to the FIFO are inhibited until the channel A receiver serial-data input line returns to the marking state for at least one-half a bit time (two successive edges of the internal or external X Iclock). When this bit becomes set, the channel A “change in break” bit in the interrupt status register (ISR [2)) is also set. Additionally, ISR [2] is set when the end of break condition, as defined above, is detected. ‘The break detect circuitry can detect breaks that originate in the middle of a received character. However, if a break begins in the middle of a character it must persist until at least the end of the next character time in order for it to be detected. 4.2.9.2. CHANNEL A FRAMING ERROR — SRA [6] ‘This bit, when sot, indicates that a stop bit was not detected when the corresponding data character in the FIFO was received. The stop bit check is made in the middle of the first stop bit position, This bit is valid only when the RxRDY bit is set (SRA [0]=1).

4.2.9.8 CHANNEL A PARITY ERROR — SRA [5]

This bit becomes set when the “with parity” or “force parity” mode is programmed by mode register one and the correspondign character in the FIO is received with incorrect parity. In the multidrop mode the parity error bit position is used to store the received address/data bit. This bit is valid only when the RxRDY bit is set (SRA (0]=1). DUART-39

TOSHIBA (UC/UP) SHE D MM 9097249 0024197 376 METOS3 TOSHIBA TMP68681/2681

4.2.9.4 CHANNEL A OVERRUN ERROR — SRA [4]

This bit when set, indicates one or more characters in the received data stream have been lost. It becomes set upon receipt of a new character when the FIFO is full and a character is already in the receive shift register waiting for an empty FIFO position. When this occurs, the character in the receive shift register (and its break detect, parity error, and framing error status, if any) is lost. This bit is cleared by a reset error status command,

4.2.9.5 CHANNEL A TRANSMITTEREMPTY — SRA [3]

‘This bit will be set when the channel A transmitter underruns; i.e., both the transmit holding register and the transmit shift register are empty. It is set after transmission of the last stop bit of a character if no character is in the transmit holding register awaition transmission. It is cleared when the transmit holding register is loaded by the CPU or when the transmitter is disabled.

4.2.9.6 CHANNEL A TRANSMITTER READY — SRA [2]

This bit, when set, indicates that the transmit holding register is empty and ready to be loaded with a character. Transmitter ready is set when the character is transferred to the transmit shift register. This bit is cleared when the transmit holding register is loaded by the CPU. Transmitter ready is also cleared when the transmitter is disabled and is set when the transmitter is first enabled; i.e., characters loaded into the transmit holding register while the transmitter is disabled will not be transmitted.

4.2.9.7 CHANNEL A FIFO FULL — SRA [1]

This bit is set when a character is transferred from the receive shift register to the receiver FIFO and the transfer causes the FIFO to become full; i.e., all three FIFO holding register positions are occupied. It is cleared when the CPU reads the receiver buffer. Ifa character is waiting in the receive shift register because the FIFO is full, the channel A FIFO full status bit will not be cleared when the CPU reads the receiver buffer.

4.2.9.8 CHANNEL A RECEIVER READY — SRA [0]

This bit indicates that a character has been received and is waiting in the FIFO to be read by the CPU. It is set when the character is transferred from the receive shift register to the FIFO and cleared when the CPU reads the receiver buffer, providing there are no more characters still in the FIFO after this read.

4.2.10 Channel B Status Register (SRB)

The bit definitions for this register are identical to the bit definitions for the channel A status register, except the status applies to the channel B receiver and transmitter and their corresponding inputs and outputs. DUART-40

ee _ TOSHIBA (UC/UP) S4E D M@ 9097249 0024198 202 METOS3 TOSHIBA TMP68681/2681

4.2.11 Output Port Configuration Register (OPCR)

This register individually configures each bit of the 8-bit parallel output port for general purpose use or an auxiliary function serving the communication channels. 4,2.11.10P7 OUTPUT SELECT — OPCR[7] ‘This bit programs the parallel output OP7 to provide either the complement of OPR [7] or the channel B transmitter interrupt output, which is the complement of the channel B transmitter ready status bit. When configured for the channel B transmitter interrupt, OP7 acts as an open-collector output and is not masked by the contents of the interrupt mask register.

4.2.11.2 OP6 OUTPUT SELECT — OPCR[6]

This bit programs the parallel output OP6 to provide either the complement of OPR [6] or the channel A transmitter interrupt output, which is the complement of the channel A transmitter ready status bit. When configured for the channel A transmitter interrupt, OP6 acts as an open-collector output and is not masked by the contents of the interrupt mask register.

4.2.11.3 OP5 OUTPUT SELECT — OPCR[5)

This bit programs the parallel output OPS to provide either the complement of OPR [5] or the channel B receiver interrupt output, which is the complement of ISR [5]. When configured for the channel B receiver interrupt, OP5 acts as an opencollector output and is not masked by the contents of the interrupt mask register. 4.2.11.40P4 OUTPUT SELECT — OPCR[4] This bit programs the parallel output OP4 to provide either the complement of OPR [4] or the channel A receiver interrupt output, which is the complement of ISR [1]. When configured for the channel A receiver interrupt, OP4 acts as an opencollector output and is not masked by the contents of the interrupt mask register. DUART-41

TOSHIBA (UC/UP) SHE D M@ 9097249 0024199 149 MTOS3 TOSHIBA TMP68681/2681

4.2.11.5 OP3 OUTPUT SELECT — OPCR[3:2]

This field programs the parallel output OPS to provide one of the following: OPCR [3:2] OP3 Function 00 In this configuration OP3 becomes the complement of OPR [3]. 01 In this configuration OP3 provides the counter/timer output. OP3 acts as an opencollector output and is not masked by the contents of the interrupt mask register. In the timer mode, this output is a square wave at the programmed frequency. In the counter mode, the output remains high until terminal count is reached, at which time it goes low. The output returns to the high state when the counter is stopped by a stop counter command. Because the counter/timer, while in timer mode, cannot be stopped, if the counter/timer is to operate in timer mode and its output is programmed to appear on OP3, OPCR [8:2] should be cleared until the counter/timer has been programmed for the desired operation.

10 In this configuration OP3 becomes the 1 clock for the channel B transmitter,

which is the clock that shifts the transmitted data. If data is not being transmitted, a freerunning 1X clock is output. i Tn this configuration OP3 becomes the 1X clock for the channel B receiver, which is the clock that samples the received data. If data is not being received, a free-running 1X clock is output.

4.2.11.6 OP2 OUTPUT SELECT-OPCR [1:0]

This field programs the parallel output OP2 to provide one of the following: OPCR (1:0) OP2 Function 00 In this configuration OP2 becomes the complement of OPR [2].

01 In this configuration OP2 becomes the 16X clock for the channel A

transmitter. This is the clock selected by CSRA [3:0] and will be a 1X clock if CSRA [8:0] =1111.

10 In this configuration OP2 becomes the 1X clock for the channel A

transmitter, which is the clock that shifts the transmitted data. A free running 1X clock is always output in this mode.

11 In this configuration OP2 becomes the 1X clock for the channel A receiver,

which is the clock that samples the received data. A free running 1X clock is always output in this mode. DUART-42

STOSHIBA (UC/UP) SHE D MM 9097249 0024200 790 METOS3 TOSHIBA TMP68681/2681

4.2.12 Output Port Register-OPR [7:0]

‘These bits contain the complement of the logic levels output at the output port pins [OP0-OP7]. Bits of this register are set by performing a bit set command during a write cycle, with data specifying the bits to be set (one equals set, zero equal no change). Bits of this register are cleared by performing a bit reset command during a write cycle, with data specifying the bits to be cleared (one equals reset, zero equals no change).

4.2.13 Auxiliary Control Register (ACR)

‘The following paragraphs provide a detailed description of the auxiliary control register (ACR).

4.2.13.1 BAUD-RATE GENERATOR SET SELECLT — ACR{[7]

This bit selects one of the two sets of baud rates that can be generated by the baud- rate generator: The selected set of rates available for use by the channel A and B receivers and transmitters are described under 4.2.5 Channel A Clock-Select Register (CSRA) and 4.2.6 Channel B Clock-Select Register (CSRB). Baud-rate generator characteristics are given in Table 4.6. Table 4.6 Baud-Rate Generator Characteristics Crystal or Clock=3.6864 MHz Nominal Actual 16X Clock Error Nominal Actual 16X Clock Error Rate (Baud) (kHz) (Percent) Rate (Baud) (kHz) (Percent) 50 08 0 1200 19.2 0 75 1.2 0 1800 28.8 0 100 1.759 - 0.069 2000 32.056 0.175 134.5 2.153 0.059 2400 38.4 0 150 2.4 0 4800 76.8 t) 200 3.2 Cy) 7200 115.2 0 300 48 0 9600 153.6 0 600 9.6 0 19.2k 307.2 0 1050 16.756 0.260 38.4k 614.4 0 Note: Duty cycle of 16X clocks is 50% +19.

4.2.13.2 COUNTER/TIMER MODE AND CLOCK SURCE SELECT — ACR [6:4]

This field seleclts the operating mode of the counter/-timer and its clock source as shown in Table 4.4. DUART-43

—e —— oe 3 TOSHIBA (UC/UP) SHE D MM 9097249 o024201 be? METOS]' TOSHIBA TMP6868 1/2681

4.2.13.3 IP3, IP2, IP1, AND IPO CHANGE-OF-STATE INTERRUPT ENABLE — ACR([3:0]

This field seleclts which bits of the input port change register can cause the input change bit in the interrupt status register (ISR [7]) to be set. Ifa bit of ACR [3:0] is set to the “enabled” state (set to one) and interrupt mask register bit seven in set (IMR [7]=1) to enable input port change interrupts, then the setting of the corresponding bit in the input port change register by an external transition on that input pin will result in ISR [7] being set and an interrupt output generated. If a bit of ACRC [3:0] is in the “disabled” state (cleared to zero), the setting of that bit in the input port change register has no effect on ISR [7].

4.2.14 Input Port Change Register (IPCR)

‘The following paragraphs provide a detailed description of the input port change register. 4,2,14,1IP3, IP2, IP1, AND IPO CHANGE OF STATE — IPCR[7:4] These bits are set when a change-of- state, a high-to-low or low-to-high transition, lasting longer than 25-50 microseconds, occurs at their respective input pins. They are cleared when the input port change register is read by the CPU. A read of the input port change register also clears ISR [7], the input change bit in the interrupt status register. The setting of these bits can be programmed by the auxiliary control register to generate an interrupt to the CPU. 4,2.14.2 IP3, IP2, IP1, AND IPO CURRENT STATE — IPCR[3:0] These bits provide the current state of their respective inputs, The information is unlatched and reflects the state of the input pins at the time the input port change register is read.

4.2.15 Interrupt Status Register (ISR)

This register provides the status of all potential interrupt sources. The contents of this register are masked by the interrupt mask register. If a bit in the interrupt status register is a one and the corresponding bit in the interrupt mask register is also a one, the IRQ output will be asserted. If the correspondigng bit in the interrupt mask register is a zero, the state of the bit in the interrupt status register has no effect on the IRQ output. Note that the interrupt mask register does not mask the reading of the interrupt status register — the true status will be provided regardless of the contents of the intrrupt mask register. The contents of this register are initialized to 0016 when the DUART is reset. DUART-44

a _ TOSHIBA (UC/UP) S4uE D m@ 9097249 OOe4e02 S63 METOSS TOSHIBA TMP68681/2681 4,2.15.1 INPUT PORT CHANGE STATUS — ISR[7] This bit is a one when a change of state has occurred at the IPO, IP1, 1P2, or IP3 inputs and that event has been selected to cause an interrupt by the programming of ACR [3:0]. This bit is cleared when the CPU reads the input port change register. 4,2.15.2 CHANNEL B CHANGE IN BREAK — ISR[6] This bit, when set, indicates that the channel B receiver has detected the beginning or the end of a received break. It is reset when the CPU issues a channel B reset break change interrupt command. 4.2.15. CHANNEL B RECEIVER READY OR FIFO FULL — ISR[5] The function of this bit is programmed by MRIB [6]. If programmed as receiver ready, it indicates that a character has been received in channel B and is waiting in the receiver buffer FIFO to be read by the CPU. It is set when the character is transferred from the receive shift register to the FIFO and cleared when the CPU reads the receiver buffer. If after this read there are more characters still in the FIFO, the bit will be set again after the FIFO is “popped”. If programmed as FIFO full, it is set when a character is transferred from the receive shift register to the FIFO and the transfer causes the channel B FIFO to become full; i.e., all three FIFO positions are occupied. It is cleared when the CPU reads the receiver buffer. If a character is waiting in the receive shift register because the FIFO is full, the bit will be set again when the waiting character is Joaded into the FIFO. . 4,2.15.4 CHANNEL B TRANSMITTER READY — ISR[4] This bit is a duplicate of channel B transmitter ready (SRB [2]).

4.2.15.5 COUNTER/TIMER READY — ISR[3]

In the counter mode, this bit is set when the counter reaches terminal count and is cleared when the counter is stopped by a stop counter command. In the timer mode, this bit is set once each cycle of the generated square wave (every other time that the counter/timer reaches terminal count). The bit is cleared by a stop counter command. The command, however, does not stop the counter/timer (see 3.5 COUNTER/TIMER). 4,2.15.6 CHANNEL A CHANGE IN BREAK — ISR[2} This bit, when set, indicates that the channel A receiver has detected the beginning or the end of a received break. It is cleared when the CPU issues a channel A reset break change interrupt command. DUART-45

TOSHIBA (UC/UP) S4E D MM 9097249 0024203 4TT METOS3 TOSHIBA TMP68681/2681

4.2.15.7 CHANNEL A RECEIVER READY OR FIFO FULL — ISR[1]

The function of this bit is programmed by MRIA [6]. If programmed as receiver ready, it indicates that a character has been received in channel A and is waiting in the receiver buffer FIFO to be read by the CPU. It is set when the character is transferred from the receive shift register to the FIFO and cleared when the CPU reads the receiver buffer. If after tis read there are more characters still in the FIFO, the bit will be set again after the FIFO is “popped”. If programmed as FIFO full, it is set when a character is transferred from the receive shift register to the FIFO and the transfer causes the channel A FIFO to become full; i.e., all three FIFO positions are occupied. It is cleared when the CPU reads the receiver buffer. If a character is waiting in the receive shift register because the FIFO is full, the bit will be set again when the waiting character is loaded into the FIFO.

4.2.15.8 CHANNEL A TRANSMITTER READY ~- ISR[0]

This bit is a duplicate of channel A transmitter ready (SRA [2)]).

4.2.16 Interrupt Mask Register (IMR)

: This register is used to select which bits in the interrupt status register can cause an interrupt output. If a bit in the interrupt status register is a one and the corresponding bit in the interrupt mask register is also a one, the IRQ output will be asserted. If the corresponding bit in the interrupt mask register is a zero, the state of the bit in the interrupt status register has no effect on the IRQ output. Note that the intrerrupt mask register does not mask the programmable interrupt outputs OP7 ~ OP3 nor the reading of the interrupt status register.

4.2.17 Count Registers (CUR and CLR)

The count upper register (CUR) and count register (CLR) hold the most-significant byte and the least-significant byte of the current value in the counter/timer, respectively. These registers should only be read when the counter/timer is in counter mode and the counter is stopped. See 3.5 COUNTER/TIMER for further information.

4.2.18 Counter/Timer Preload Registers (CTUR and CTLR)

‘The counter/timer upper register (CTUR) and counter/timer lower register (CTLR) hold the eight most-significant bits and eight least-significant bits, respectively, of the preload value to be used by the counter/timer in either the counter or timer modes of. operation, The minimum value which may be loaded into the concatenation of CTUR with CTLR is 000216. Note that CTUR and CTLR are write-only registers and cannot be read by the CPU. . DUART-46

TOSHIBA (UC/UP) SE D MM 9097249 0024204 336 METOS3 TOSHIBA TMP68681/2681

4.2.19 Interrupt Vector Register (IVR)

‘This register contains the interrupt vector. When the DUART responds to a valid interrupt acknowledge (IACK) cycle the contents of this register are placed on the data bus. Upon reset, this register will contain OF16, which is the TMP68000 exception vector assignment for uninitialized interrupt vectors. DUART-47

TOSHIBA (UC/UP) ~~ sue > Mm 9097249 GO24205 272 METOSS TOSHIBA TMP68681/2681 5, ELECTRICAL SPECIFICATIONS This section contains electrical specifications and associated timing information for the TMP68681.

5.1 ABSOLUTE MAXIMUM RATINGS

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high- impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or Vg). DUART-48,

“JOSHIBA (UC/UP) SHE DOM 9097249 OO242O6 109 MNTOSS TOSHIBA TMP68681/2681

5.2 DC ELECTRICAL CHARACTERISTICS

(Vcc =5.0V 5%, GND =0V, Ta =0°C~70°C) Input High Voltage, Except X1/CLK Va [ 20 [= [= fv] Input High Voltage, X1/CLK ES Output High Veltage. Except Open-Collector Outputs [vm | a] - | - | Vv Output Low Voltage (lo = 2.4mA) [vo | - | - | 04 | 7 ee a a Peepers Pw fet | Po | [owersuppiycurene ee [||| [coactonce Wn <Bv.Fa=25e Fatih | Gn [=| | 5 | oF XI/CLK Low Input Current xa mA Vin=0,x2 Grounded -40} -20 pe] as] ™ | Vin = Vcc, X2_ Grounded 1.0 1.0 Vin=Vec, X2_ Floated i) 16.0 i Vin =0,X1/CLK Floated Petters PTT eT | Vin =Vee, XVCLK Floated DUART-49

TOSHIBA (UC/UP) SUE D MM 9097249 0024207 O45 METOS3 TOSHIBA TMP68681/2681

5.8 ACELECTRICAL CHARACTERISTICS

(Vcc = 5.0V + 5%, GND = OV, Tz = 0°C~70°C, See Note 1) Receiver Clock Frequency (RxC) 16X Clock fax 2.0 MHz 1X Clock 1.0 Transmitter Clock Frequency (TxC) 16X Clock fix 2.0 MHz 1X Clock 1.0 : Note1: All voltage measurements are referenced to ground (GND). For testing, all inputsignals except XI/CLK swing between 0.4 volt and 2.4 volts with a maximum transition time of 20 nanoseconds. For X1/CLK, this swing is between 0.4 volt and 4.4 volts. All time measurements are referenced at input and output voltages of 0.8 volt and 2.0 volts as appropriate. Test conditions for outputs: C1,=150 picofarads, Ry,=750 ohm to Veo. 2: ‘To use the standard baud rates selected by the clock-select register given in Table 4.5, the XI/CLK frequency shold be set to 8.6864 MHz or a 3.6864 MHz crystal should be connected across pins X1/CLK and X2.

5.4 ACELECTRICAL CHARACTERISTICS ~ RESET TIMING

(See Figure 5.1 and Note 1) Note1: All voltage measurements are referenced to ground (GND). For testing, all input signals swing between 0,4 volt and 2.4 volts with a maximum transition time of 20 nanoseconds. All time measurements are referenced at input and output voltages of 0.8 volt and 2.0 volts as appropriate. Test conditions for non-interrupt outputs: C=150 picofarads, RL =750 ohms to Voc. Test conditions for interrupt outputs: Cy=50 picofarads, Ry=27 kilohms to Voc. RESET tres . Figure 5.1 RESET Timing DUART-50

TOSHIBA (UC/UP) S4E D MM 9097249 0024208 T4l METOS3 TOSHIBA TMP68681/2681

5.5 ACELECTRICAL CHARACTERISTECS — READ CYCLE BUS TIMING

(See Figure 5.2 and Note 1) symbot | win [mex [ vnit_] GS Setup Time to XI/CLK High (See Note 2) [tse [| 9 [ - | os | C$ Pulse Width Asserted (See Note 3) [tem | 205 | - | ns _| DTACK Asserted from X1/CLK High [ton | - | 12s | ns GS Negated from DTACK Asserted (See Note 3) [tso [| 2 [| - | as RS1~RS4 Hold Time from CS Negated [ten | 0 | - | os | Data Bus Floating from CS Negated [tor [| - [10 | as | DTACK Negated from C5 Negated [ton | -_| 100 ns DTACK Hi-2 from CS Negated [ toar | - | 125 ns G Pulse Width Negated [tcswn | 90 | - | os Note1: All voltage measurements are referenced to ground (GND). For testing, all input signals except XI/CLK swing between 0.4 volt and 2.4 volts with a maximum transition time of 20 nonoseconds. For X1/CLK, this swing is between 0.4 volt and 4.4 volts. All time measurements are referenced at input and output voltages of 0.8 volt and 2.0 volts as appropriate, ‘Test conditions for non-interrupt outputs: C1,=150 picofarads, Ry,=750 ohms to Voc. Test conditions for interrupt outputs: C,=50 picofarads, Ry,=27 kilohms to Voc. 2: This specification is made only to insure DTACK is asserted with respect to the rising edge of X1/CLK as shown in Figure 5.2, not to guarantee operation of the part, If the setup time is violated, DTACK may be asserted as shown, or may be asserted one clock cycle later. 3: ‘The tcsp specification is made only to insure that DTACK will be asserted. If CS is negated before DTACK is asserted, DTACK may not be asserted, ee DUART-51

TOSHIBA (UC/UP) SE D M@@ 9097249 0024209 914 METOS3 TOSHIBA TMP68681/2681 tesc >| XVCLK ‘ass test nsimnse, WI | RAW | |< teswi J test —] | lod | ey a ony Paes | Do~D7 es a ) tes DTACK * (Sand IAUK should be asserted simultaneously. Po tock =] fs toatl Figure 5.2 Read Cycle Bus Timing DUART-52

TOSHIBA (UC/UP) S4E D MM 9097249 0024210 &3T METOS] TOSHIBA TMP68681/2681

5.6 ELECTRICAL CHARACTERISTICS — WRITE CYCLE BUS TIMING

(See Figure 6.3 and Note 1)

5 Setup Time to X1/CLK High (See Note 2) [tse [ 9% | - | os |

RS1~RS4 Setup Time to CS Asserted | rss | 10 | RW Setup Time to CS Asserted [ews | 0 | Pulse Width Asserted (See Note 3 and 4) [tem | 205 | - | ns | Data Setup Time to X1/CLK High (See Note 4) [twos | 10 | - | os | Data Setup Time to CS Negated (See Note 4) | toses | 100 | - | os | DTACK Asserted from X1/CLK High [tow | - | 125 | ns | CS Negated from DTACK Asserted (See Note 3) [iso | 2 | - | ns | RS1~RS4 Hold Time from CS Negated [sn | oo | - | os | DTACK Negated from CS Negated [toan | - | 100 | TACK Hi-2 from GS Negated [toar | - | 125 |

5 Pulse Width Negated (See Note 5) [tw | 90 | - | ns _|

Note 1: Allvoltage measurements are referenced to ground (GND). For testing, all input signals except XU/CLK swing between 0.4 volt and 2.4 volts with a maximum transition time of 20 nanoseconds. For X1/CLK, this swing is between 0,4 volt and 4,4 volts, All time measurements are referenced at input and output voltages of 0.8 volt and 2.0 volts as appropriate. Test conditions for non-interrupt outputs: C1,=160 picofarads, Ry.=750 ohms to Voc. Test conditions for interrupt outputs: C=50 picofarads, Ry,=27 kilohms to Veo. 2: This specification is made only to insure DTACK is asserted with respect to the rising edge of X1/CLK as shown in Figure 6.2, not to guarantee operation of the part. If the setup time is violated, DTACK may be asserted as shown, or may be asserted one clock cycle later. 8: The tcgp specification is made only to insure that DTACK will be asserted, If GS is negated before DTACK is asserted, DTACK may not be asserted, 4 :During write eycles, data is latched on either the asserting edge of DTAOK or the negating edge of CS, whichever occurs first. IF CS is negated within one clock eycle after OS has been recognized (i.e, first rising edge of XU/CLK where CS is asserted), then DTACK may not be generated. In this case, data will be latched on the negating edge of CS. ‘Thus, tps can be ignored but togcs must be observed. 5: Consecutive write operations to the same command register (CRA or CRB) require at least three transitions of XI/CLK between write cycles. Typically, a processor is incapable of accessing the same command register a second time prior to three transitions on the XUCLK pin, DUART-53

TOSHIBA (UC/UP) SHE D MM 9097249 OOe4e211 S7b MMETOS]: TOSHIBA TMP68681/2681 tesc >| XM/CLK — trss >| tas RS1~RS4 Ok RAW cs 00~D7 a — tos teso DTACK J<— toar * Sand [ACK should not be assserted simultaneously. Figure 5.3 Write Cycle Bus Timing DUART-54

TOSHIBA (UC/UP) SHE D M™@ 9097249 OO24212 402 METOS] TOSHIBA TMP68681/2681

5.7 ACELECTRICAL CHARACTERISTICS — INTERRUPT CYCLE BUS TIMING*

(See Figure 5.4 and Note 1) TACK Setup Time to X1/CLK High (See Note 2) [sc [| 90 | - [| os | TACK Pulse Width Asserted (See Note 3) tam | 205 | - | ns | Data Valid from IACK Asserted too | - | 175 [ns | TACK Negated from DTACK Asserted (See Note 3) [tso [| o | - | as | Data Bus Floating from IACK Negated [tor | - | 100 | ns | * During IACK cycles, the status of the R/W line is ignored, Note1: All voltage measurements are referenced to ground (GND). For testing, all input signals except XI/CLK swing between 0.4 volt and 2.4 volts with a maximum transition time of 20 nanoseconds. For XI/CLK, this swing is between 0.4 volt and 4.4 volts. All time measurements are referenced at input and output voltages of 0.8 volt and 2.0 volts as appropriate, ‘Test conditions for non-interrupt outputs: Cr=160 picofarads, R=750 ohms to Vcc. Test conditions for interrupt outputs: Cy,=50 picofarads, Ry,=27 kilohms to Voc. 2: 'This specification is made only to insure DTACK is asserted with respect to the rising edge of X1/CLK as shown in Figure 6.2, not to guarantee operation of the part. If the setup time is violated, DTACK may be asserted as shown, or may be asserted one clock cycle later. 3: The tosp specification is made only to insure that DTACK will be asserted. If CS is negated before DTACK is asserted, DTACK may not be asserted. [* tese >| XICLK RQ JACK Dr Sep ES bo~p7 a a ee) cso DTACK toer == toan >| <——. tpaT * Sand IACK should not be assserted simultaneously. Figure 5.4 Interrupt Cycle Bus Timing DUART-55

sy SuE D MM 9097249 0024213 349 METOSS TOSHIBA (UC/UP) TOSHIBA TMP68681/2681

5.8 ACELECTRICAL CHARACTERISTICS — PORT TIMING

(See Figure 5.5 and Note 1) Port input Setup Time to GS Asserted [we | ° |] - | | Port input Hold Time from CS Negated mm |e | - [| Port Output Valid from CS Negated tp [ - | 40 | ns | Note: All voltage measurements are referenced to ground (GND). For testing, all input signals except X1/CLK swing between 0.4 volt and 2,4 volts with a maximum transition time of 20 nanoseconds. For X1/CLK, this swing is between 0.4 volt and 4,4 folts. All time measurements are referenced at input and output voltages of 0.8 volt and 2.0 volts as appropriate. Test conditions for non-interrupt outputs: Cy,=150 picofarads, Ry,=750 ohms to Voc. Test conditions for interrupt outputs: Cy, =50 picofarads, Ry, =27 kilohms to Vcc. —>| Fetes teH IPO~IPS OP0~OP7 Old Data New Data * CS and IACK should not be assserted simultaneously. Figure 5.5 Port Timing DUART-56

TOSHIBA (UC/UP) SuE D Mm 9097249 GOe4214 285 METOS3 TOSHIBA TMP68684/2681

5.9 ACELECTRICAL CHARACTERISTICS — INTERRUPT RESET TIMING

(See Figure 5.6 and Note 1) TRQ Negated or OP3~OP7 High from CS Negated When Used as Interrupts From: Read RB (RxRDY/FFULL Interrupt) - 300 Write TB (TxRDY Interrupt) - 300 Reset Command (Delta Break Interrupt) - 300 Stop CT Command (Counter Interrupt) - 300 Read IPCR (Input Port Change Interrupt) - 300 Write IMR (Clear-of-Interrupt Mask Bit) - 300 Note: All voltage measurements are referenced to ground (GND). For testing, all input signals except XI/CLK swing between 0:4 volt and 2.4 volts with a maximum transiiton time of 20 nanoseconds, For X1/CLK, this swing is between 0.4 volt and 4,4 volts. All time measurements are referenced at input and output voltages of 0.8 volt and 2.0 volts as appropriate. Test conditions for non-interrupt outputs: C1,=150 picofarads, RL=750 ohms to Vcc. Test conditions for interrupt outputs: C1,=60 picofarads, Ry,=27 kilohms to Vcc. ite sey (Read or Write Cycle) t Interrupt Output? * CS and TACK should not be asserted simultaneously. ** IRQ or OP3~OP7 when used as interrupt outputs. Figure 5.6 Interrupt Reset Timing DUART-57

TOSHIBA (UC/UP) SHE D MM 9097249 0024215 111 MMTOS3 TOSHIBA TMP68681/2681

5.10 ACELECTRICAL CHARACTERISTICS — CLOCK TIMING

(See Figure 5.7 and Note 1) Counter/Timer Clock High orLow Time [tere [100 | Recerive Clock (RxC) High or Low Time [tm | 220 | - | as | Transmit Clock (TxC) High or Low Time [tx | 20 [| - | os | Note: All voltage measurements are referenced to ground (GND). For testing, all input signals except X1/CLK swing between 0.4 volt and 2.4 volts with a maximum transition time of 20 nanoseconds. For XI/CLK, this swing is between 0.4 volt and 4.4 volts. All time measurements are referenced at input and output voltages of 0.8 volt and 2.0 volts as appropriate. Test conditions for non-interrupt outputs: Cy,=1650 picofarads, Ry, 750 ohms TO Vcc. Test conditions for interrupt outputs: Cy,=50 picofarads, Ry,=27 kilohms to Vcc. Driving From Crystal: Driving From External TTL-Level Source: +5v Series Resonant Crystal C1 10~15 pF + IRA SE ef) C2: O~ 5 pF + STRAY<S pF) 470 teux->| Jotcax tare: tere: [>e tee >} fe tio XWVCLK xveuk tix tx a . Open ct eu FS jesse [tects | SY |rrsasen RC = TxC ~@ Wee ht! 7 x2 t x2 * ‘Typically 3.6864 MHz Note; Board layout should be such that the crystal and capacitor(s) are as close as possible to the pins of the DUART to minimize stray capacitance. Also, crystal series resistance should be less than 180 ohms, Figure 5.7 Clock Timing DUART-58

TOSHIBA (UC/UP) SHE D MM 9097249 OO24216 O58 METOS3 TOSHIBA TMP68681/2681

5.11 ACELECTRICAL CHARACTERISTICS — TRANSMITTER TIMING

(See Figure 5.8 and Note 1) Note: All voltage measurements are referenced to ground (GND). For testing, all input signals except XI/CLK swing between 0.4 volt and 2.4 volts with a maximum transition time of 20 nanoseconds. For X1/CLK, this swing is between 0.4 volt and 4.4 volts. All time measurements are referenced at input and output voltalges of 0.8 volt and 2.0 volts as appropriate. Test conditions for non-interrupt outputs: CL =150 picofarads, R= 750 ohms to Vcc. ‘Test conditions for interrupt outputs: C1,=50 picofarads, Ri,=27 kilohms to Voc. 1Bit Time (Tor 16 Clocks) Txe (input) ‘trxD TxD tres Txe (1x Output) Figure 6.8 Transmit Timing

5.12 AC ELECTRICAL CHARACTERISTICS — RECEIVER TIMING

(See Figure 5.9 and Note 1) RxC Data Hold Time from Rx High [eww [20 f= fone | Note: All voltage measurements are referenced to ground (GND). For testing, all input signals except X1/CLK swing between 0.4 volt and 2.4 volts with a maximum transition time of 20 nanoseconds. For X1/CLK, this swing is between 0.4 volt and 4,4 volts, All time measurements are referenced at input and output voltalges of 0.8 volt and 2.0 volts as appropriate. Test conditions for non-interrupt outputs: Ci,=160 picofarads, Ry,=750 ohms to Voc. Test conditions for interrupt outputs: C1=60 picofarads, Ry, =27 kilohms to Voc. RxC (x1 Input) t t RxD ’ K Figure 5.9 Receive Timing DUART-59

TOSHIBA (UC/UP) SUE D mm 9097249 024217 TI4 MMTOS3 TOSHIBA TMP68681/2681 TxD [ory fet fa TA. Loe Loe Transmitter Hy H Enabled H TxRDY b, L , Y L Ph (SR2) | DTACK? | 4 4 j (Write) ot D2 D3. Start D4 Stop osWwill | D6 __ 4 Break Break NotBe H CTs2 Transmitted | (IP0) 7 (oPo) oPR{o]=1 Cm (ol=1 Note1: If GS is negated within one clock cycle after CS is recognized, DYACK will not be asserted. In this case the negation of CS will cause the transitions. 2; ‘Timing shown for MR2 (4)=1. 3: Timing shown for MR2(5)=1. Figure 5.10 Transmitter Timing DUART-60

TOSHIBA (UC/UP) S4E D MM 9097249 O024218 920 METOS3 TOSHIBA TMP68681/2681 RxD [oii] [o2]} [oa}7]_[os} 4 [os] [os | H H i D6, D7, D8 Receiver H H Ht Will Be Lost ° Enabled ' H Hy RxRDY (SRO) FFULL s (SR1) RRRDY/ : AL) A, FFULL Wi (opa)t DTACK2 t § (| (Read) Status Data ; D1 : Status|Status Status ps Data |Data Data + will ‘ba Ba “Ba | Be ! Lost, Overrun H (SR4) H Reset By __ H Command RTS3 (OP0) OPR (0}=1 Note1: Shown for OPCR (4)=1 and MR1(6)=0. 2: If CS is negated within one clock cycle after OS is recognized, DTACK will not be asserted, In this case the negation of OS will cause the transitions. 3: ‘Timing shown for MR1 (7)=1. Figure 5.11 Receiver Timing DUART-61

TOSHIBA (UC/UP) SHE D MM 9097249 0024219 667 METOS3 TOSHIBA TMP68681/2681 AD wy _MasterStation wo TxD PRT Lfooid aaa Transmitter Enabled H H TeRDY t i (SR2) DTACK! (Write) MRI (igl= 11 ADD DO MRi[2])=1 ADD MR} (2) =1 1 wart (220 2 Peripheral Station AID A/D AID AID AID ) RxD [it LAL feo id ALE Receiver H : + Enabled i RxRDY (SRO) | DTACKi MR [4:3] = 11 ADD1 Status Status Data Data | Eo) ‘ADD2 Note: If GS is negated within one clock cycle after OS is recognized, DTACK will not be asserted, In this case the negation of CS will cause the transitions. Figure 5.12 Wake-Up Mode Timing DUART-62

“TOSHIBA (UC/UP) SHE D M@ 9097249 OO24ee0 589 METOSS TOSHIBA TMP68681 /2681 6. MECHANICAL DATA This section contains package dimensions for the TMP68681/2681.

6.1 PACKAGE DIMENSIONS

AASSAALAAASAAAAAAAAA 7 Unit: mm ‘0 3 a EEE 1 24 [8 | 13.72] 14.22 | PVT VV VVVVVYVT TTT TV TY ‘ « [ep tarl t33| tt IO YUOV IRAE Ce cara alle TT eiee VS] few Lu | ol 1s a [x osit 02] DUART-63

| TOSHIBA (UC/UP) SHE D M@@ 9097249 OOe24e22e1 415 METOS3 TOSHIBA TMP68681/2681 APPENDIX TMP2681 The TMP2681 dual asynchronous receiver/transmitters (DUARTs) are functionally equivalent to the TMP68681 with some minor differences. The description of the TMP68681 applies to the TMP2681 except for the areas described below. A.1 INTRODUCTION Unlike the TMP68681 which has an TLCS-68000 bus interface, the TMP2681 have a general purpose interface which may be used with both synchronous and asynchronous microprocessors. This devices have a multipurpose 7-bit input port and a multipurpose 8-bit output port. These ports can be used as general purpose I/O ports or can be assigned specific functions (such as inputs or status/interrupt outputs) under program control. A block diagram for the TMP2681 is given in Figure A.1. | The TMP2681 differ in that the TMP2681 is available in a 40-pin dual-in-line package is available in a 28-pin dual-in-line package. This option is given to satisfy system requirements. A.L.LINTERNAL CONTROL LOGIC The internal control logic receives operation commands from the central processing unit (CPU) and generates appropriate signals to the internal sections to control device operation. It contains address decoding and read and write circuits to permit communications with the microprocessor via the data bus buffer. A.1.2INTERRUPT CONTROL LOGIC A single active-low interrupt output (IRQ) is provided which is activated upon the occurrence of any of eight internal events. Associated with th einterrupt system are the interrupt mask register (IMR) and the interrupt status register (ISR). The IMR may be programmed to select only certain conditions to cause IRQ to be asserted. The ISR can be read by the CPU to determine all currently active interrupting conditions. In addition, the DUARTs offer the ability to program the parallel outputs OP3 through OP7 to provide discrete interrupt outputs for the transmitters, the receivers, and the counter/timer. DUART-64

TOSHIBA (UC/UP) SUE D MM 9097249 D024222 351 MMTOS3 TOSHIBA TMP68681/2681 R ve c—>| Internal Control Logic RESET —— RSI~RS4 xuctK Crystal x2 Baud Rate: . Processor « Selector External Interface 3 Interface 2 yaracter || pee 00~07 & | | TQ a we | LE | _ Figure A.l TMP2681 Block Diagram DUART-65

TOSHIBA (UC/UP) SHE D MM 9097249 0024223 298 METOS3 TOSHIBA TMP68681/2681 A.1.3INPUT PORT The inputs to the unlatched 7-bit port (IPO ~ IP6) can be read by the CPU by performing a read operation. A high input results in a logic one while a low input results in a logic zero. D7 will always be read as a logic one. The pins of this port can also serve as auxiliary inputs to certain portions of the DUART logic. Four change-of-state detectors, also provided within the input port, are associated with inputs IPO, IP1, IP2, and IP3. A high-to-low or low-to-high transition of these inputs lasting longer than 25 to 50 microseconds (best-to-worst case times) will set the corresponding bit in the input port change register (IPCR). The bits are cleared when the register is read by the CPU. Also, the DUART can be programmed so any particular change of state can generate an interrupt to the CPU. A.2 SIGNAL DESCRIPTION Table A.1, like that for the TMP68681 found in Section 2, Signal Description, provides a quick reference in determining a signal’s pin number, its use as an input or output, whether it is active high or low, and the section in which more information can be found about its operation. Note that the signal description given for the TMP68681 | applies to the TMP2681 except for the areas described in this appendix. (40Pin DIP TOP VIEW) asi die 401) Vee

3 G2 39) ira

Rsz 3 36) ips Pia 37H) 16 R305 36 [) IP2 Ra 6 35S po 7 34f] RESET wis 33] x2 Rqo 321 Xt/CLK RxDB [] 10 31f] RxDA TxbB 4] 11 300) TxDA ont diz 291 opo ora 13 28) op2 cops (114 27) ops oP7 15 261 oP6 oi 016 25{1 DO 03 017 2a) 02 os die 23) 04 o7 19 22H 06 GNo 20 2ip TRO Figure A.2 TMP2681 Pin Assignments DUART-66

T03 (UC/UP) 9097249 go2uesu Vee TOSHIBA SHED M@™ 9097249 oOa4224 124 MOTOS] TOSHIBA TMP68681/2681 A.2,1RESET (RESET) When active high, this input clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OPO~OP7 in the high state, stops the counter/timer, and puts channel A and B in the inactive state with the TxDA and TxDB outputs in the mark (high) state. A.2.2CHIP SELECT (CS) This active low signal, when low, enables data transfers between the CPU and DUARY on the date lines (D0 ~ D7). These data transfers are controlled by write (W), read (R), and the register-select inputs (RS1 ~ RS4). When chip enable is high, the DO through D7 data line are placed in the high-impedance state. A.2.3WRITE STROBE (W) When this signal and chip enable are low, the contents of the data bus are loaded into the addressed register. The transfer occurs on the rising edge of the signal. A.2.4READ STROBE (R) When this signal and chip enable are low, the contents of the addressed register are pressented on the data bus. The read cycle begins on the falling edge of the signal. A.2.5 PARALLEL INPUT 6 (IP6) ‘This signal can be used as a general purpose input or a channel B receiver external clock input (RxCB). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. Table A.1_ TMP2681 Signal Summary (1/2) [sess nt ee] | [rowersuppiy(+sy) [ee [a0 [input [High [ot | [oround | co Tt [inp | tow a | leostnpsoréenaiGear [xc || pe [ = | a | lemme |e | | = | lainseea Yt] tow fa 2 | Jwrtestobe | Sw Lt | input [tow [a2 | Jreadswobe | RL | input [tow [a 2a | fsoersencourone [ase || | wah | a | [Reaistersetecteussits | rss || input | High | 28 | ast [it [mot [igh 28 | DUART-67

TOSHIBA (UC/UP) SHE D MM 9097249 0024225 Ob0 METOS3 TOSHIBA TMP68681/2681 Table A.1_ TMP2681 Signal Summary (2/2) [osname finer inne nvwows] Si [rs fiiecoaroanensi7 | or | [ream] ah [29 | Breconarove sate [os | 2] wnwvowt] igh | 29 | irecionsonauens | os | 1p] gh | 39 ieconarovasusane [pe | 28 _[npwouut] wah | 20 | iteinstoxis wane | or | 7p] igh | 39 isinsoniosoacz | on | apie] igh [39 ecioa:onsawani | ov | «wot nh [99 | Bidirectional-Data Bus Bit 0 | vo | 25 |inpuvoutput| High | 29 | cine Anni Siibow—| aoe | 30 | owt] [aa | ChannelAReceiverSerialData_ | RxDA | 31 | input | - | 2.13 | Channel B Transmitter Serial Data mos | 11 [| output | - | 2aa | Channel 8 Receiver Serial Data pee ff owe ff i a a print ar281 Oni) [we | 99] put] = 6 | Foraetnpts cuPasevonin | wef? — input [= a6] Fersetinpu ciara oni) | 2 | 36] pot [= [a2 | Pratap rr Onb)—[ Wr | — «| moe [= 20 | Frtetnpocorne268 oni) —[ PO | 7 | rot [= 208] Parselounut treason] —| —oFr | 15 | ouput | = a | feroeroupueotrassionn) | ore [26 | owpur® [= fara | ere oupuescvaeat Oni) —[ OPS | —1a_| ower [Para] araeroupueaaPasev oni) —| —oPe [a7 oupue= | = 27a] stat oupueacaasstonny [ore 1a | ownur™ [= 275] Forteroupueacnea@st Onn) | ore —| 26 [out | = Pe festetoupett | or [| out [= [20777 [ratefovputa | “or | | oapee =| * Requires a pullup resistor. ** May require a pullup resistor depending upon its programmed function, A.2,6PARALLEL INPUT 2 (IP2) This signal can be used as a general purpose input or a counter/timer external clock input. DUART-68

TOSHIBA CUC/UP) S4E D MM 9097249 0024226 TT? MTOS3 TOSHIBA TMP68681/2681 A.3 PROGRAMMING AND REGISTER DESCRIPTION Table A.2 describes the register addresses and address-triggered commands for the ‘TMP2681. The detailed description of each register and its function, given for the TMP68681 in Section 4 Programming and Register Description, applies to the TMP2681. Table A.2 TMP2681 Register Addressing and Address - Triggered Commands fe fele[ eee ed [efele[e [mmanen oman [ncaa a a fefels[e orcs omen | fe fef[ ewan waa [rata ec fe [fe [fonts frre oa [To [enna arenas tem [ewnerine vase run [=P [erin creators ean [cnrineiow tae | [ee fe fieenanwe nisin [aici emanan_ | a [efi [oenencar femme | 2 oe Input Port (Unlatched) Output Port Register i ce Se capa LoD T HT sncsoercnmnaes erm * This address location is used for factory testing of the DUARTs and should not be read. Reading this location will result in undesired effects and possible incorrect transmission or reception of characters, Reigster contents may also be changed, ** Address Triggered commands, DUART-69

TOSHIBA (UC/UP) > S4uE Dm” 939 MTORs 9097249 ooey227 933 METOS3 TOSHIBA ‘TMP68681/2681 A.4 ELECTRICAL SPECIFICATIONS This section contains electrical specifications and associated timing information for the TMP2681. A.4.1ABSOLUTE MAXIMUM RATINGS A.4.2DC ELECTRICAL CHARACTERISTICS (Vcc =5.0V £5%, GND =0V, Ta=0°C~70°C) a input VoFage a ‘Output High Voltage, Except Open-Collector Outputs . (low= ~ 400 pA) Vou M ‘Output Low Voltage (lo. = 2.4mA) [vo | - | 0.4 fputteskage curentWineotoved |__| = 10 | v0 Data Bus Hi-Z Leakage Current (Vout =0 to Veo) tie =70 10 A Open-Collector Output Leakage Current - Creates loc 10 10 pA [PowerSupaiycurent | ee == [0 ma] [coactance Winesvfanec fama | Ge [= [= [8 | oF XT/CLK Low Input Currnet xi mA Vin=0,X2 Grounded -40 Vin=0,X2 Floated -3.0 XIV/CLK High Input Current IaH mA Vin=Vec,X2 Grounded 0.2 1.0 Vin =Vcc, X2__ Floated 35 10.0

2 Low Input Current beat 30 BA

Vin=0,X1/CLK Floated X2__ High Input Current ea +30 Vin=Vec, XV/CLK Floated DUART-70

TOSHIBA (UC/UP) SHE D MM 9097249 OO24228 &87T METOS3 TOSHIBA TMP68681/2681 A.4.3AC ELECTRICAL CHARACTERISTICS. (Veo=5.0V £5%, GND =0V, Ta=0°C~70°C, See Note 1) ee eountetinercodegueny (ee [0 | 40 | me | Receiver Clock Frequency (RxC) 16X Clock frx 2.0 MHz 1X Clock 1.0 ‘Transmitter Clock Frequency (TxC) 16X Clock ftx 2.0 MHz 1X Clock 1.0 * Touse the standard baud rates selected by the clock-select register given in Table 4-6, the XW/CLK frequency should be set at 3.6864 MHz. A.4.4AC ELECTRICAL CHARACTERISTICS — RESET TIMING (See Figure A.2) [characterise | symbot | tin [mex unie_] feserrmewan i rs Pe) | RESET ‘tres >| Figure A.2 RESET Timing DUART-71

TOSHIBA (UC/UP) S4E D M@™@ 9097249 GOe24229 70b METOS3 TOSHIBA TMP68681/2681 A.4.5AC ELECTRICAL CHARACTERISTICS — BUT TIMING (See Figure A.3) RS1~RS4 Setup Time to R, W Asserted [tess | 10 | - | ns | RS1~RS4 Hold Time from R, W Negated [ts | oo | - | os | [ES Hold Time from R, W Negated ta [| 0 | - | os | R, W Pulse Width Asserted tew | 205 | - | ns | Data Bus Floating after R Negated [wr | - | wo | os | Data Setup Time before W Negated [tos | wo | - | os | Data Hold Time after R or W Negated | ton | 10 | High Time Between Reads and/or Writes* [tewo | 200 | * IfCS is used as the “strobing” input, this parameter defines theminimum high time between one CS and the next. CS and R (W) are ANDed internally. Subsequently, the signal asserted last initiates the cycle and the signal negated first terminates the cycle, R must be negated for trwp to guarantee that any status register changes are valid, Consecutive write operations to the same command register require at last three edges of the X1 clock between writes. Typically, a processor is incapable | of accessing the same command register a second time prior to three transitions on the X1/CLK pin. RSI~RS4 if % cs = — ~ R f_tor ee 0-07 i [ valid} Read) loat__| XNotValid X | Valid Float tewo Ww f |<+B5, tou rand Se (Write) valid Figure A.3 Bus Timing DUART-72

TOSHIBA (UC/UP) SHE D MM 9097249 0024230 428 mETOSR TOSHIBA TMP68681/2681 A.4.6AC ELECTRICAL CHARACTERISTICS — PORT TIMING (See Figure A.4) [ance ne [| | fonnpasaupTnewRawenes fw fe | - |» | Porinuthourineton®Neged tw |e f= | | por ovtuivaidtomWnegsed | w» |e [wo | m| R “eke IPO~IP6 Ww Tt OPp0o~OP7 Old Data New Data Figure A.4 Port Timing DUART-73

TOSHIBA (UC/UP) SHE D MM 9097249 0024231 364 METOS3 TOSHIBA TMP68681/2681 A.4.7AC ELECTRICAL CHARACTERISTICS — INTERRUPT TIMING (See Figure A.5) TRQ Negated or OP3~OP7 High for R or W Negated When tr Used as Interrupts From: Read RHR (RXRDY/FFULL Interrupt) 300 ns Write THR (TXRDY Interrupt) 300 ns Reset Command (Delta Break Interrupt) 300 ns Stop C/T Command (Counter Interrupt) 300 ns Read IPCR (Inpur Port Change Interrupt) 300 ns Write IMR (Clear-of-Interrupt Mask Bit) 300 ns RorW \\ | tir or 0Pp3~0P7 Figure A. Interrupt Timing A.4.8AC ELECTRICAL CHARACTERISTICS — CLOCK TIMING (See Figure A.6 and Note 1) a Soba XI1/CLK High or Low Time wo | - | os Counter/Timer Clock High or Low Time oo | - | os Recerive Clock (RxC) High or Low Time [tm | 220 | - | ns | Transmit Clock (TxC) High or Low Time [tx | 220 | - | ns | Note: All voltage measurements are referenced to ground (GND), For testing, all input signals exept XI/CLK swing between 0.4 volt and 2.4 volts with a maximum transtion time of 20 nanoseconds. For XI/CLK, this swing is between 0.4 volt and 4.4 volts. All time measurements are referenced at input and output voltages of 0.8 volt and 2,0 volts as appropriate. ‘Test condition for non-interrupt outputs: C1,=160 picofarads, Ri =750 ohms to Veo. ‘Test conditions for interrupt outputs: Cy,=50 picofarads, R,=27 kilohms to Veo. DUART-74

oe SeeSeeeeseSeSesessesesesFeFeSeeeF “TOSHIBA (UC/UP) SHE D MM 9097249 O024232 2TO METOS3 TOSHIBA TMP68681/2681 Driving From Crystal Driving From External TTL-Level Source: +5V Seriess Resonant Crystal Ci 10~15 pF + (STRAY <5 pF) 2: 0~ 5 pF (STRAY<S pF) 470 tax} feta ‘tere: tere: {> © tox te XWVCLK XWCLK tix tx ax |, Open. llector + cen oS J rwerees [tes SY | reaa6st RxC > Tre = 0 iV 470 x2 sf x2 * ‘Typically 3.6864 MHz Note: Board layout should be such that the crystal and capacitor(s) are as close as possible to the pins of the DUART to minimize stray capacitance Also, crystal series resistance should be less than 180 ohms. Figure A.6 Clock Timing A.4.9AC ELECTRICAL CHARACTERISTICS — TRANSMITTER TIMING (See Figure A.7 and Notel) Note: All voltage measurements are referenced to ground (GND). For testing, all input signals except XI/CLK swing between 0.4 volt and 2.4 volts with a maximum transition time of 20 nanoseconds. For XI/CLK, this swing is between 0.4 volt and 4.4 volts. All time measurements are referenced at input and output voltages of 0.8 volt and 2.0 volts as appropriate, ‘Test conditions for non-interrupt outputs: C1,=150 picofarads, R= 760 ohms to Voc. Test conditions for interrupt outputs: C1,=60 picofarads, Ry =27kilohms to Voc. 1Bit Time (1 or 16 Clocks) (input) tx TxD tres TxC (1x Output) Figure A.7 Transmit Timing DUART-75

TOSHIBA (UC/UP). 7 SHE D MM 9097249 0024233 137 METOS3 TOSHIBA TMP68681/2681 A4,10 AC ELECTRICAL CHARACTERISTICS — RECEIVER TIMING (See Figure A.8) ae J [Rxcbatasetuptimetonschigh | teas | 2a | | | [xc DataHold TimefromaxcHigh | teas | 200 «| | ors Rx (x1 Input) ee RxD x \\X Figure A.8 Receive Timing on) DoT Afel RS LETT Lon Transmiter_ A jf \\ | Craad (SR2) im D1 02 3 Start D4 Stop osWill | D6 __ : bras Bee Rowse, CTS*1 Transmitted | (IPO) + RTS*2 ‘ A (oP0) OPR [0] = 1 OPR [OJ =1 Figure A.9 Transmitter Timing DUART-76

TOSHIBA (UC/UP) SHE D M@@ 9097249 0024234 073 METOS3 TOSHIBA TMP68681/2681 RxD [oi Ti] H [oaJi]|_[osT 4 [os] [os | H i Hi 06, D7, D8 i Will Be Lost Receiver H i i Enabled : ' it RxRDY aN (SRO) FFULL he PaRDY/ r | HHS FFULI (OPS) *2 Edad x 5 ; Anrine Status Hl Status Status Status Data ; Data_, |Daty Data Bi H D2 Be {Dswill 'Be Overrun iLost (SRA) { Reset By H Command RTS*1 {oP0) OPR fo}=1 Figure A.10 Receiver Timing DUART-77

TOSHIBA (UC/UP) SHE D MM 9097249 0024235 TOT mmTOS3 TOSHIBA TMP68681/2681 Master Station wo ~~ No Transmitter Enabled (SR2) w Receiver Enabled _ __| LH RxRDY (SRO) Rw Figure A.11 Wake-Up Mode Timing . DUART-78