TMP102A UMW | Alldatasheet
Document overview
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Technical content
Features
- Product number: UMW TMP102AIDRLRS、UMW TMP102AIDRLRD
- Temperaturerange: -55°C ~ +150°C
- Temperatureaccuracy: ±0.5°C (-40°C ~ +125°C)
- Package: 6-Pin SOT563 (UMW TMP102AIDRLRS) 6-Pin DFNWB (UMW TMP102AIDRLRD)
- Supplyvoltagerange: 1.4V ~ 5.5V
- Lowquiescentcurrent: Normaloperation:≤10μA (4Hz) Shutdownmode:≤1μA
- Resolution: 12bits, 0.0625°C
- Digitaloutput: SMBusTM and I2C interface compatibility
Applications
- Portableandbattery-powered applications
- Power-supply temperaturemonitoring
- Computer peripheral thermalprotection
- Notebook computers
- Batterymanagement
- Officemachines
- Thermostatcontrols
- Electromechanicaldevicetemperatures
- Generaltemperaturemeasurements: –Industrialcontrols TMP102A UMW Rwww.umw-ic.com 1 UTD Semiconductor Co.,Limited
Figure 1. UMW TMP102A Internal
Description
The digital temperature sensor with high-accuracy,low-power, and NTC/PTC thermis- tor replacements. It can be used for extended tempe- rature measurement in communication, computer, consumer electronics, environmental, industrial and instrumentation applications. The UMW TMP102A provides ≤ ± 0.5°C temperature accuracy with good temperature linearity over the normal operating range of -40°C to +125°C. The UMW TMP102A can provide extended temperature measurement mode, extending the temperature measurement rangefrom-55°C to+150°C. The rated working voltage range of the UMW TMP102A is 1.4V~5.5V, and the maximum quiescent current in the entire working rage is 10µA (temperature measurement frequency 4Hz). The on-chip 12-bit ADC offers resolutions down to 0.0625°C. The adopts SOT563 / DFNWB package of 1.6mm × 1.6mm, is compatible with SMBus and I2C interface, and allows up to four de- vices on one bus. The device also features an SMBusalertfunction.www.umw-ic.com 2 UTD Semiconductor Co.,Limited TMP102A UMW R UMW TMP102A is a UMW TMP102A
PinConfigurationandFunctions PinFunctions PIN NO. NAME 1 SCL Serialclock.Open-drainoutput,requiresapull-upresistor. 2 GND Ground. 3 ALERT Overtemperaturealert.Open-drainoutput,requiresapull-upresistor. 4 ADD0 Addressselect.ConnecttoV+,GND,SCLorSDA. 5 V+ Supplyvoltage,1.4Vto5.5V. 6 SDA Serialdatainput.Open-drainoutput,requiresapull-upresistor. Specifications AbsoluteMaximumRatings Over operating free-air temperature range (unless otherwise noted). Stresses beyond those listed under Absolute Maximum Ratings maycausepermanentdamagetothedevice. MIN MAX UNIT Supply Voltage, V+ 6 V Voltage at SCL, SDA, and ADD0 -0.5 6 V Voltage at ALERT -0.5 ((V+)+0.3) and ≤5.5 V Operating Temperature -55 160 °C Junction Temperature 150 °C Storage Temperature -60 150 °Cwww.umw-ic.com 3 UTD Semiconductor Co.,Limited TMP102A UMW R
Figure 2. UMW TMP102A Internal ESD
ElectricalcharacteristicsofdevicesatTA =+25℃ andV+=1 .4Vto3 .6V(unlessotherwisenoted) PARAMETER TESTCONDITONS MIN TYP MAX UNIT Operating Temperature Range -40 125 °C Extendedmode -55 150 °C Accuracy (Temperature Error) DC Power Supply Sensitivity -40°Cto+125°C 0.0625 ±0.25 °C/V Resolution 0.0625 °C 12 bits Conversion Time 26 35 ms Conversion Modes CR1=0,CR0=0 0.25 conv/s CR1=0,CR0=1 1 CR1=1,CR0=0(default) 4 CR1=1,CR0=1 8 Timeout Time 30 40 ms Communication Frequency Fastmode 0.001 0.4 MHz High-speedmode 0.001 2.75 Power Supply Voltage 1.4 3.3 5.5 V Average Quiescent Current, IQ Serialbusinactive,CR1=1,CR0=0(default) 7 10 μASerialbusactive,SCLfrequency=400kHz 15 Serialbusactive,SCLfrequency=2.75MHz 85 Shutdown Current, ISD Serialbusinactive 0.5 1 μASerialbusactive,SCLfrequency=400kHz 10 Serialbusactive,SCLfrequency=2.75MHz 80 www.umw-ic.com 5 UTD Semiconductor Co.,Limited TMP102A UMW R
Figure 3.Schematic DiagramofContinuousConversionDetailed The default working mode of UMW TMP102A is continuous conversion mode, and the typical conversion time is 26ms. During continuous conversion mode, the ADC performs continuous temperature conversions andstores each results to thetemperature register,overwritingthe result from theprevious conversion. The conversion rate bits, CR1 and CR0, configure the UMW TMP102A for conversion rates of 0.25Hz, 1Hz,4Hz, or 8Hz. The conversion rate can be changed by configuring CR1 and CR0, the UMW TMP102A makes a conversion and then powers down and waits for the appropriate delay set by CR1 and CR0, as shown in Figure 3. Table 1lists the settings for CR1 and CR0. Table1. Conversion Rate Settings CR1 CR0 CONVERSION RATE 0 0 0.25Hz 0 1 1Hz 1 0 4Hz（default） 1 1 8Hz ExtendedMode The temperature measurement range of UMW TMP102A is -40°C to +125°C in normal temperature measurement mode. By setting the EM bit in the configuration register to1, the UMW TMP102A can enter the extended temperature measurement mode. Extended mode (EM = 1) allows measurement of temperatures above 128°C by configuring the temperature register and the temperature limit registers for 13-bit data format. The read-only temperature register in UMW TMP102A uses two bytes to store the temperaturewww.umw-ic.com 6 UTD Semiconductor Co.,Limited TMP102A UMW R
temperature information of the LSB is not required. Table 2. 12-bit Temperature Data Format in Normal Temperature Measurement Mode
–0.25 1 111111111100 1FFC –25 1 11100111 0000 1E70 –55 1 1100 1001 0000 1C90 ShutdownMode Shutdown mode of the UMW TMP102A device allows the user to conserve power by shutting down all device circuitry except the serial interface, thereby reducing the current of the UMW TMP102A to less than0.5µA (typical value). Shutdown mode is initiated when the SD bit in the configuration register is set to 1; after configuring the registers in this way, the UMW TMP102AI will shut down after completing the current conversion. To exit shutdown mode, write SD bit to 0, the UMW TMP102A will re-enter continuous conversion mode. One-ShotMode The UMW TMP102A features a one-shot mode. When the UMW TMP102A is in shutdownmode, writing 1 to the OS bit starts a single temperature conversion. During the conversion, the OS bit reads 0. The UMW TMP102AI returns to the shutdown state at the completion of the single conversion, the OS bit reads 1. This feature is usefulfor reducing power consumption when continuous temperature monitoring is not required. Since the UMW TMP102A only needs 26ms for a single temperature measurement (typical value), it can achieve a higher conversion rate through this mode. When using one-shot mode, 30 or more conversions per second are possible. ALERT The UMW TMP102A has a temperature alarm function, by writing theTM bit in the configurationregister as 0 or 1, the UMW TMP102A can beconfigured as comparator mode or interrupt mode to achieve differentalarm functions Figure 4 Status oftheALERTPin inDifferentModeswww.umw-ic.com 8 UTD Semiconductor Co.,Limited TMP102A UMW R
comparison mode (TM=0), when the number of times the temperature measurement result continuously equalsorexceeds thetemperature upper limitregister valueTHIGH reaches thevalue defined bytheF1/F0 bitsinthe configuration register (as shown in Table 4), theALERT pin will be activated. TheALERT pin will remain active until the number of times the temperature measurement result is continuously lower than the temperature lower limit register valueTLOW reaches the value defined by F1/F0. In interrupt mode (TM=1), theALERTpin will be activated when the temperature measurement result equals or exceeds THIGH continuously for a number of times to the value defined by F1/F0 (as shown in Table 4). TheALERT pin remains active until it is cleared by one of three events: a read of any register, a successful SMBus alert response, or a shutdown command. After the ALERT pin is cleared, the device starts to compare temperature readings with the TLOW. The ALERT pin becomes active again only when the temperature drops below TLOW for a consecutive number of conversions as set by F1/F0 bits. TheALERT pin remains active until cleared by any of the same three clearing events. The user can also reset the UMW TMP102A to clear the ALERT pin state byusing the global response reset command (General Call). This operation also resets other internal registers in theUMW TMP102A and returns the device to compare mode (TM=0). Table 4 shows the specific configuration of the F1/F0 bits. Table4. Number ofOver-Temperature Required toActivate theALERT Pin F1 F0 REQUIRED NUMBER (TIMES) 0 0 1 (Default) 0 1 2 1 0 4 1 1 6 The polarity bit (POL) inthe configuration register allows theuser to adjust thepolarity oftheALERTpin output. If the POL bit is set to 0 (default), the ALERT pin becomes active low. When POL bit is set to 1, the ALERT pin becomes active high.The above situations are shown in Figure 4.www.umw-ic.com 9 UTD Semiconductor Co.,Limited TMP102A UMW R
The UMW TMP102A is compatible with SMBus and I2C interfaces. In the SUMBus protocol, the device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. To address a specific device, a START condition is initiated, indicated by pulling the dataline(SDA)fromahigh-tolow-logic levelwhentheSCLpinishigh.Allslaves onthebusreceivethe8-bits slave address on the rising edge of the clock, and the last bit indicates whether a read or write operation is intended. During the ninth clock pulse, the addressed slave generates an acknowledge and pulls the SDApin low to respond tothemaster.Adatatransferistheninitiatedandsentovereightclockpulsesfollowed byanacknowledgebit.When all data are transferred, the master generate a STOP signal to end the communication by pulling SDA from low to high when SCLis high. During the data transfer, the SDApin must remain stable when the SCLpin is high because any change in the SDApin when the SCLpin is high is interpreted as aSTARTor STOPsignal. SerialBusAddress To communicate with the UMW TMP102A, the master must first address slave devices through an address byte. The address byte has seven address bits and a read-write (R/W) bit that indicates the intent of executing a read or write operation.The UMW TMP102A features an address pin to allow up to four devices to be addressed on a single bus. Table 5 shows the connection mode of the ADD0 pins corresponding to each slave address. Table5.Address Pin and SlaveAddresses DEVICE TWO-WIREADDRESS ADD0 PIN CONNECTION
1001000 GND
1001010 SDA
1001011 SCL
WritingandReadingOperationwww.umw-ic.com 10 UTD Semiconductor Co.,Limited TMP102A UMW R
Figure5. Two-wireWriteCommandTiming DiagramF igure6.Two-wireReadCommand TimingDiagram When writing data to the UMW TMP102A, after the slave address byte is sent, accessing a particular register on the UMW TMP102A is accomplished by writing the appropriate value to the pointer register. Every writeoperationtotheUMW TMP102Arequiresavalueforthepointerregister. When reading from the UMW TMP102A device, after the slave address byte is sent, the corresponding pointer register byte also needs to be sent. Unlike the write operation, if the user need to repeatedly read data from thesameregister,itisnotrequiredtosendthepointerregisterbyteseparatelyeachtime,thelastvaluestoredinthe www.umw-ic.com 11 UTD Semiconductor Co.,Limited TMP102A UMW R
Figure7.SMBusAlertTimingDiagram pointer register will be read by the device automatically; to change the register pointer for a read operation, a new value must be written to the pointer register. The action is accomplished by issuing a slave-address byte with the R/W bit low,followed by the pointer register byte.The master can then generate a STARTcondition and send the slaveaddressbytewith the R/W bit hightoinitiatethereadcommand. Register bytes are sent with the MSB first, followed by the LSB. Figure 5 and Figure 6 show schematic diagramsoftheabovereadandwriteoperations. SMBusAlertFunction The UMW TMP102A supports the SMBus alert function. When the UMW TMP102A operates in interrupt mode (TM=1), the master can send out and SMBus ALERT command (19h) to the bus. If the ALERT pin is active, the device acknowledges the SMBus ALERT command and responds by returning the slave address. The eighth bit (LSB) of the slave address byte indicates if the alert condition is caused by the temperature exceeding THIGH or falling below TLOW. This bit is equal to POL if the temperature is greater than or equal to THIGH; this bit is equaltoPOLifthetemperature islessthanTLOW. If multiple devices on the bus respond to the SMBus ALERT command, the bus will return the lowest two-wire address. The UMW TMP102A ALERT pin becomes inactive at the completion of the SMBus ALERT command; the ALERT pin of the UMW TMP102A that does not return an address will remain active. Sending the SMBus ALERT command again can continue to clear the ALERT pin of the UMW TMP102Awith thecurrentlowestaddress.TheaboveprocessisdetailedinFigure7.General CallReset TheUMW TMP102Aresponds tothetwo-wire generalcalladdress00h.Thedeviceacknowledges thegeneral call address and responds to commands in the second byte. If the second byte is 06h, the UMW www.umw-ic.com 12 UTD Semiconductor Co.,Limited TMP102A UMW R
resets the internal registers to the power-up reset values, and aborts the current temperature conversion. If the second byte is other value, theUMW TMP102A willnot respond. High-SpeedMode For the two-wire bus to operate at frequencies above 400kHz, the host device must issue a High-Speed mode host code (0000 1xxxb) as the first byte after a START condition to switch the bus to high-speed operation. The UMW TMP102A device does not acknowledge this byte, but it does switch the input filters on the SDA and SCL and the output filters on the SDA to operate in High-Speed mode, allowing the bus to transmit data at frequencies up to 2.75MHz. After the High-Speed mode host code is issued, the host transmits a two-wire device address to initiate a data transfer operation. The bus continues to operate in High-Speed mode until a STOP condition occurs on the bus. Upon receiving the STOP condition, the UMW TMP102A switches the input and outputfiltersbacktofast-mode operation. Time-OutFunction The UMW TMP102A resets the serial interface if SCL is held low for 30ms (typical) between a START and STOPcondition, theUMW TMP102A releases the SDA bus and waits for a STARTcondition. Toavoid activating theTime-Outfunction,acommunication speedofatleast1kHz must bemaintained.R egisterDescriptions PointerRegister Figure 8 shows the internal register structure of the UMW TMP102A device. The 8-bit Pointer Register of the device is used to address a given data register. The Pointer Register uses the two LSBs (see Table 6) to identify which of the data registers must respond to a read or write command. The power-up reset value of P1/P0 is '00'.Bydefault, theUMW TMP102Areadsthetemperature onpower-up.www.umw-ic.com 13 UTD Semiconductor Co.,Limited TMP102A UMW R
- Internal Register Structure Table6 lists the pointer address of the registers available in the UMW TMP102A device. During a write command, bytes P2 through P7 must always be 0. Table6.PointerAddress P1 P0 REGISTER 0 0 TemperatureRegister(ReadOnly) 0 1 ConfigurationRegister(Read/Write) 1 0 TLOW Register(Read/Write) 1 1 THIGH Register(Read/Write) www.umw-ic.com 14 UTD Semiconductor Co.,Limited TMP102A UMW R
Table7.PointerRegisterByte P7 P6 P5 P4 P3 P2 P1 P0 0 0 0 0 0 0 RegisterBitsT emperatureRegister The Temperature Register of the UMW TMP102A device is configured as a 12-bit or 13-bit read-only register(settingtheEMbitto0or1)thatstorestheoutputofthemostrecentconversion.Twobytesmust bereadto obtain data and are listed in Table8 and Table9. Byte 1 is the most significant byte (MSB), followed by byte 2, the leastsignificantbyte(LSB).TheT11~T0bits(T12~T0bitsinextendedmode)areusedtoindicatetemperature.Byte 2doesnothavetobereadifthatinformationisnotneeded.TheD0bitofbyte2inthetemperatureregisterindicates whether the device is in normal mode (D0=0) or extended mode (D0=1) at this time, which can be used to distinguish theformat ofthetwotemperature registerdata. Table8.Byte1ofTemperatureRegister BYTE D7 D6 D5 D4 D3 D2 D1 D0 T11 T10 T9 T8 T7 T6 T5 T4 Table 9.Byte 2ofTemperatureRegister BYTE D7 D6 D5 D4 D3 D2 D1 D0 T3 T2 T1 T0 0 0 0 0 emperatureLimitRegister The temperature limits are stored in the THIGH and TLOW registers in the same format as the temperature result, and can be configured as 12-bit or 13-bit according to the value of the EM bit. Table10 and Table11list the format for the THIGH and TLOW registers, the configuration in extended mode is in brackets. The power-up reset values for THIGH andTLOW are: THIGH =+80℃；TLOW =+75℃ Table10.Byte1and2ofTHIGH Register BYTE D7 D6 D5 D4 D3 D2 D1 D0 H11 H10 H9 H8 H7 H6 H5 H4 2 H3 H2 H1 H0 0 0 0 0www.umw-ic.com 15 UTD Semiconductor Co.,Limited TMP102A UMW R
_ _ Table 11.Byte 1and2ofTLOW Register BYTE D7 D6 D5 D4 D3 D2 D1 D0 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 0 0 0 0 onfigurationRegister TheConfigurationRegisterisa16-bitread/writeregisterusedtostorebitsthatcontroltheoperationalmodesof the temperature sensor. Read/write operations are performed MSB first. Table12 and Table13 list the format and power-upandresetvaluesoftheconfiguration register. Table 12.Configuration RegisterHigh Byte BIT FIELD DEFAULT DESCRIPTION
7 OS（R） 0
One-Shot and Conversion Completion Flag 1 = Temperature not converting 0 = Temperature is converting
6 R1（R） 1 Set to 11 on Power-up
Temperature measurement resolution is 12bits5 R0（R） 1
4 F1（R/W） 0
Flag Bit for the Number of Over-Temperature Required to Activate the ALERT Pin 00 = 1 time（ Default） 01 = 2 times 10 = 4 times 11 = 6 times
3 F0（R/W） 0
2 POL（R/W） 0
1 = ALERT pin is high when activated 0 = ALERT pin is low when activated
1 TM（R/W） 0
Device Working Mode Flag Bit 1 = Interrupt mode 0 = Comparator mode
0 SD（R/W） 0
1 = Shutdown mode 0 = Continuous conversion modewww.umw-ic.com 16 UTD Semiconductor Co.,Limited TMP102A UMW R
Table 13.Configuration RegisterLowByte BIT FIELD DEFAULT DESCRIPTION
7 CR1（R/W） 1
Continuous Conversion Rate Flag 00 =0.25Hz 01 =1Hz 10 =4Hz(Default) 11 =8Hz
6 CR0（R/W） 0
5 AL（R） 1
Alarm Function Fag Bit in Compare Mode When the POL bit equals 0, the AL bit reads as 1 until the temperature equals or exceeds THIGH for the programmed number of consecutive faults, causing the ALbittoreadas0.TheALbitcontinuestoreadas0until the temperature falls below TLOW for the programmed numberofconsecutivefaults,whenitagainreadsas1.If POL=1, the behavior of the AL bit is the opposite of the above. ThestatusoftheTMbitdoesnotaffectthestatusof theALbit.
4 EM（R/W） 0
1 = Extendedmode 0 =Normalmode 3 0 0 / 2 0 0 / 1 0 0 / 0 0 0 / www.umw-ic.com 17 UTD Semiconductor Co.,Limited TMP102A UMW R
Ordering information
Order code Package Baseqty Deliverymode UMW TMP102AIDRLR SOT-563 4000 Tape and reelwww.umw-ic.com 19 UTD Semiconductor Co.,Limited TMP102A UMW R