TMM41464 | DigiCamel IC Datasheet

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TMM41464AP TOSHIBA | Alldatasheet

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ss.s96worDxearr DyNAMICRAM —TNIMI41464AP/AT/AZ-10, TMIM41464AP/AT/AZ-12 N-CHANNEL SILICON GATE MOS TMM41464AP/AT/AZ-15

DESCRIPTION

The TMM41464AP/AT/AZ is N-channel dynamic AT/AZ to be package in a standard 18 pin plastic DIP, 18 RAM organized 65,536 words by 4 bit. The TMM41464 pin PLCC and 20 pin ZIP. The package size provides high AP/AT/AZ utilizes TOSHIBA’s N-channel/Silicon gate system bit densities and is compatible with widely avail- process technology as well as advanced circuit techniques able automated testing and insertion equipment. System to provide wide operating margins, both internally and oriented features include single power supply of 5V + to the system user. 10% tolerance, direct interfacing capability with high Multiplexed address inputs permit the TMM41464AP/ performance logic familes such as schottky TTL.

FEATURES

@ 65,536 words by 4 bit organization @ Lower Power: @ Fast access time and cycle time 440mW MAX. Operating (TMM41464AP/AT/AZ-10) 396mW MAX. Operating (TMM41464AP/AT/AZ-12) [ DEVICE tac 358mW MAX. Operating (TMM41464AP/AT/AZ-15) TMMA1464AP/AT/AZ10 | 100ns | 50ns_| 190ns | 28mW MAX. Standby [TMMAi464AP/AT/AZ12 | 120ns | 60ns © Output unlatched at cycle end allows two-dimensional TMMA1464AP/AT/AZ-15 | 150ns_| 75ns | 260ns chip selection @ Read-Modify-Write, RAS only refresh, Hidden refresh, © Singl f 1 i Itin V, eac rite, | soe supply of 5V + 10% with a built-in Ves CAS before RAS refresh, and Page Mode capability © All inputs and outputs TTL compatible PIN CONNECTION @ 256 refresh cycles/4ms @ Package 'TMM41464AP TMM41464AT ‘TMM41464AZ Plastic DIP TMM41464AP_ Plastic Leaded Chip Carrier : TMM41464AT x q: ish vss = vos ex Plastic ZIP TMM41464AZ vor 2 17h vos Saas oa SSE] AS yo2 3 16P CAS ares) DEfetad Ys WAITE da ish yos. B axe 02 Bats vor BLOCK DIAGRAM RAS ds 1abao Yor d spcas 1-465] WRITE

5 WRITed- hyo RAS[a}

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TMM41464AP/AT/AZ-10, TMM41464AP/AT/AZ-12 ABSOLUTE MAXIMUM RATINGS TEM ~ | sympou RATING _ UNITS NOTES _ Input and Output Voltage Vin. Vout -1~7 Pawer Supply Voltage ~ : Veo -1~7 Operating Temperature ~ a Topr o~70 1 Storage Temperature 1 tetg 85 ~ 150 % Soldering Temperatures Time 1 Tsovoer 260-10 °Crsec Power Dissipation Po 1 W Short Circuit Output Current lout 60 mA RECOMMENDED DC OPERATING CONDITIONS (Ta = 0 ~ 70°C) SYMBOL PARAMETER MIN. TYP, MAX. units _|_NoTes DC ELECTRICAL CHARACTERISTICS (Vcc = 5V # 10%, Ta=0~ 70°C) SYMBOL PARAMETER, - MAX, | UNITS [NOTES | OPERATING CURRENT Twa ra6aar/at/az 10) — | 80 | | tees ‘Average Power Suoply Operating Current “rumaraeaar/atiazi2| ~~ 72] mA | 3,4 LL _| (RAS, CAS Cycling: tac = tac MIN.) Tumarasaap/atiazis{ — | 66 _| | STANDBY CURRENT ~~ | 'eca Power Supply Standby Current - ) 5 mA (RAS = CAS = Vin) . - . _ i _ | RAS ONLY REFRESH CURRENT_ TMMA1464AP/AT/AZ10 | — 70 | tees ‘Average Power Supply Current, RAS Only Refresh Modd TMMA1a04AP/AT/AZI2| = | 62] mA | 3 (RAS Cycling, CAS = Vins: tac® tacMIN.) [Twmarasaar/ariazis | [88 | | PAGE MODE CURRENT [Twinarasaap/ar/az10[ ~ |_60_ | | leca | Average Power Supply Current, Page Mode TMM 1464AP/ATIAZ 12. 55 | mA | 3.4 | __[LHRAS = Viv, CAS Cycling: tec= tec MIN.) TMMa1464AP/AT/AZ-15 50 | CAS BEFORE RAS REFRESH CURRENT TMM41464AP/AT/AZ-10 Average Power Supply Current, CAS Before RAS 4 ee Mode __ ae 7 | (RAS, CAS Cycling, CAS Before FAS: tac= tac MIN.) | TMMAIS64AP/AT/A215 | INPUT LEAKAGE CURRENT ~ a Tuy | Input Leakage Current, any input -10 BA (OV < Vin $6.5Y, All Other Pins Not Unter Test = OV) low OUTPUT LEAKAGE CURRENT BA (Dour is disabled, OV < Vour< + 5.5V) OUTPUT LEVEL | vi 4 - v OH | Output "H™ Level Voltage (lour=—5mA) 2 i OUTPUT LEVEL ~~ Ve - 4 v oF Output "L” Level Voltage (lour= 4.2mA) . | . — A386 —

TWM41464AP/AT/AZ-10, TMM41464AP/AT/AZ-12 TMM41464AP/AT/AZ-15 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC ‘OPERATING CONDITIONS| (Vee = BV + 10%, Ta = 0~ 70°C) (Notes 5, 6, 7) - | | Teananaaary [Twa anne! TMMA1464AP/ SYMBOL PARAMETER AT/AZ-10 AT/AZ-12_ AT/AZ-15__) UNITS JNOTES | MIN. | MAX. | min. [ MAX. tre Random Read or Write Cycle Time [190 | - | 220 | - | 260 | —_ ns |_| truw | Read-Modify Write Cycle Time [ 260 | — fh 3907 P= 355 ns | tec Page Mode Cycle Time. jo | — q20 | = | 145 = a tRAC ‘Access Time from RAS _ = 00 = “120 et tet esis Tie from CAS ee Oe TOFF Output Buffer Turn-off Delay — Fo | 380 0] 35 | 0 { 40] ms [i | eT Franson Time Rise and Fat) |S pw | | | Se | mL ow [7 tas | AS Fold Time et = pep- pst fs, | vest | CAS Hol Time ce cas) CAS Pulse Width 86 [1000060 {ToooE] 7 [10.600] | op tas rrecwgetine = ee TO CAS Precharge Time. Row Address Set-Up Time 0 of; - 0 pte +— Row Address Hold Time __ 10 we | — [18 ps |_| Column Address Set-Up Time _ _ on —or- ) o/- [ss {| Carn Adres Hoid Time | 2 a Column Address Hold Time Reference — RCH to CAS +— Bead Gomvnand Hold Time Reference 10 iw | - 20 [- [= [2 | Write Command Hold Time 30 se wer Wire Command Hold Time Reference 20 os | - | 120 j-f= | | Tee Write Commando PAS md Tine | 0) = | asf ae T= mw TT Te [aie Commando CAS Ld Tine [30] = te = fe [= [| ee iat istetn ta Tine Reeencavo PAS [eo [=o [= [a0 [= Te TT et —brerenpeice eT et — Tare Command Up Tine = | = oR fs PERS ioWATTE Dsiny SSS LL oO | ao | [RAST RATE Dey ta [= fo 9 ss eo —oraces time Pe es —_A37 — _

TMM41464AP/AT/AZ-10, TMM41464AP/AT/AZ-12 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) To TviM41464aP/ | TMM41464AP/ | TMM414644P/ 7] SYMBOL PARAMETER ATIAZ-10 ATIAZ.12 AT/AZ-15__| UNITS |NOTES} es ee MIN, [ MAX. | MIN, MIN. | MAX. | toed GE to Data Delay [2 30 = 40] — ns Output Buffer Turn-Off Delay Time a ~ i toez ‘rom OE : o| 0) | 9 | 0] # toen OE command Hoid Time 2 | - ao { - 40} — ns CAS Hold Time for CAS Before RAS rs a | | tena | Rtresh | 30 - | 30] - 30 - ns | ee a _ CAS Set-Up Time for CAS Betore RAS |, Refresm - tReC 1 CAS Precharge to CAS Active Time - of - 0 0 piece) eer ee - — | CAS Precharge Time for CAS Before RAS | T tcer | Counter Test | | - aan a 36 s | tnon OF Command Hold Time a CAPACITANCE (Vcc = 5V # 10%, f= IMHz, Ta= 0 ~ 70°C) “SYMBOL __ PARAMETER SSSS*wYSCSiMIN, =| MAX. [UNITS cn | Input Capacitance (AO ~ A7) —_ 5 C12 | Input Capacitance (RAS, CAS, WRITE, OE) a a pF 12__{_Input Capacitance { Lh Co, T Input/Output Capacitance (1/01 ~ 1/04) — 7 . ABB

TMM41464AP/AT/AZ-10, TMM41464AP/AT/AZ-12 TMM41464AP/AT/AZ-15 NOTES: 1. Stresses greater than those listed under “Absolute Maximum Ratings’ may cause permanent damage to the device. 2. All voltage are referenced to Vss. 3. ‘eer, lees. lees, lees depend on cycle rate. 5. An initial pause of 200us is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS Before RAS initializa- tion cycles instead of 8 RAS cycles are required, 6. AC measurements assume ty = 5 ns. 7. Vin (min.) and Vi, (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between Vin and Vit. 8. Assumes that taco < taco (max.). If taco is greater than the maximum recommended value shown in this table, trac will increase by the amount that taco exceeds the value shown. 9. Assumes that taco > trep (max). 10. Measured with a load equivalent to 2 TTL loads and 100 pF. 11. tore (max.) and toez (max.) define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 12. Either tacy or tay must be satisfied for a read cycle. a reference point only: If taco is greater than the specified taco (max.) limit, then access time is controlled exclusively by tcac. 14, These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in read-write or read-modify-write cycles. 15. twes, tewo and tawp are not restrictive operating parameters. They are included in the data sheet as elec- trical characteristics only. If twcs > twes (min.), the cycle is an early write cycle and the input/output pin will remain open circuits (high impedance) throughout the entire cycle; !f towo > tcwo (min.) and trwo > tawo (min.), the cycle is a read-write cycle or read-modify-write cycle and the data out will contain data read from the selected cell: If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate, — A39 —

TMM41464AP/AT/AZ-10, TMM41464AP/AT/AZ-12 TMM41464AP/AT/AZ-15 ° T_T @ WRITE vets cany WRITE) Don's care a = TM a ts _— Aero i {vai nata-tn } “Weswaae

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TMM41464AP/AT/AZ-10, TMM41464AP/AT/AZ-12 TMM41464AP/AT/AZ-15 © RAS ONLY REFRESH CYCLE vit — - Notes: WRITE, OE=Don't Care (ZZven's care © CAS BEFORE RAS REFRESH CYCLE viL— te Yo~yoe aT ) = Note: WRITE, OE, AO~A7=Don't Care — A43 — ; : —

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TMM41464AP/AT/AZ-10, TMM41464AP/AT/AZ-12 TMM41464AP/AT/AZ-15 a me fen ————- eam MY, am @ READ CYCLE [fl om 2 we I) WE eM a @ WRITE CYCLE tes com: | ™ a eee = 1 TT

TMM41464AP/AT/AZ-10, TMM41464AP/AT/AZ-12 TMM41464AP/AT/AZ-15

APPLICATION INFORMATION

The 16 address bits required to decode 1 of the satisfied. 65,536 cell locations within the TMM41464AP/AT/ The outputs become valid after the access time has AZ are multiplexed onto the 8 address inputs and elapsed and remains valid which CAS and OE are tow. latched into the on-chip address latches by externally CAS or OE going high returns it to a high impedance applying two negative going T1'' level clocks. state. In an early-write cycle, the outputs are always The first clock, the Row Address Strobe (RAS), in the high-impedance state. In a delayed-write or latches the 8 row address bits into the chip. The read-modify-write cycle, the outputs will follow the second clock, the Column Address Strobe (CAS), sequence for the read cycle. subsequently latches the 8 column address bits into The O€ controls the impedance of the output the chip. Each of these signals, RAS, and CAS, buffers. In the logic high position the buffers will triggers a sequence of events which are controlled by remain in a high impedance state. different delayed internal clocks. When the OE input is brought to a logic low level, The two clock chains are linked together logically the output buffer are enabled. Both CAS and OE in such a way that the address multiplexing operation can control the output. Thus in a read operation, is done outside of the critical path timing sequence either OE or CAS returning high forces the outputs for read data access. The later events in the CAS into the high impedance state. clock sequence are inhibited until the occurrence of a delayed signal derived from the RAS clock chain. RAS ONLY REFRESH This ‘gated CAS" feature allows the CAS clock to be Refresh of the dynamic cell matrix is accomplish- externally activated as soon as the Row Address Hold ed by performing a memory cycle at each of the Time specification (tax) has been satisfied and the 256 row address (Ag ~ Az) within each 4 milli- address inputs have been changed from Row address second time interval. Although any normal memory to Column address information. cycle will perform the refresh operation, this function is most easily accomplished with “RAS-only” cycles, Data Inputs RAS only refresh results in a substantial reduction Data is written during a write or read-modify-write in operating power. This reduction in power is cycle. reflected in the Ioc3 specification. The falling edge of CAS or WRITE strobes data into the on-chip data latches. In an early-write cycle, CAS BEFORE RAS REFRESH WRITE is brought low prior to CAS and the data is CAS before RAS refreshing available on the strobed in by CAS with setup and hold times re- TMM41464AP/AT/AZ offers an alternate refresh method. ferenced to this signal. In delayed write or read- \\f CAS is held on low for the specified period (tcsr) modify-write cycle, CAS will already be low, thus the before RAS goes to low, on chip refresh control data will be strobed in by WRITE with setup and clock generators and the refresh address counter are hold times referenced to this signal. enabled, and an internal refresh operation takes place. In delayed or read-modify-write, OE must be high After the refresh operation is performed, the refresh to bring the output buffer to high impedance prior address counter is automatically incremented in to impressing data on the 1/0 lines. preparation for the next CAS before RAS refresh operation. Data Outputs The three-state output buffers provide direct TTL PAGE MODE compatibility with a fan-out of two standard TTL The ‘Page-Mode" feature of the TMM41464AP/ loads. Data-out is the same polarity as data-in. The AT/AZ allows for successive memory operations at outputs are in the high-impedance state until CAS multiple column locations of the same row address is brought low. In a read cycle the outputs go active with increased speed without an increase in power. after the access time interval trac and toea are This is done by strobing the row address into the : — A46 —

TMM41464AP/AT/AZ-10, TMM41464AP/AT/AZ-12 TMM41464AP/AT/AZ-15 chip and maintaining the RAS signal at a logic 0 HIDDEN REFRESH throughout all successive memory cycles in which the An optional feature of the TMM41464AP/AT/AZ row address is common. This “Page Mode’ of is that refresh cycles may be performed while main- operation will not dissipate the power associated with taining valid data at the output pin. This is referred to the negative going edge of RAS. Also, the time re- as Hidden Refresh. Hidden Refresh is performed by quired for strobing in a new address is eliminated, holding CAS at Vi__and taking RAS high and after a thereby decreasing the access and cycle times specified precharge period (t,9), executing a CAS before RAS refresh cycle. (see Figure below) MEMORY CYCLE PEFFESH CYCLE REFRESH CYCLE mT SVS VY This feature allows a refresh cycle to be “hidden” write mode. among data cycles without affecting the data avail- @ Select one certain column address and read “0” ability. out and write ‘'1” in each cell by performing CAS BEFORE RAS REFRESH COUNTER TEST CAS BEFORE RAS REFRESH COUNTER TEST (READ-WRITE CYCLE). Repeat this operation The internal refresh operation of TMM41464AP/ 256 times. AT/AZ can be tested by CAS BEFORE RAS RE- © Check “1” out of 256 bits at normal read mode, FRESH COUNTER TEST. This cycle performs which was written at (2), READ/MRITE operation taking the internal counter (4) Using the same column as (2), read ‘1 out and address as row address and the input address as write "0" in each cell performing CAS BEFORE column address. "RAS REFRESH COUNTER TEST. Repeat this The test is performed after a minimum of 8 CAS operation 256 times. before RAS cycles as initialization cycles. The test (©) Check “0” out of 256 bits at normal read mode, procedure is as follows. which was written at @). © Perform the above (1) to ©) to the complement @ Write “0” into all the memory celis at normal data. — A47 —

TMM41464AP/AT/AZ-10, TMM41464AP/AT/AZ-12 TMM41464AP/AT/AZ-15 OUTLINE DRAWINGS © Plastic DIP Unit in om le 17 16 15 14 13 12 11 10 Fi R10 3 l.o2 3 4 5 67 6 9 228MAK. 7624025 MOM aaeiaee cu {—¥— ozst eh. 8] 3 [['ossors 3 7s2~e8 Note: Each lead pitch is 2.54mm. All leads are located within 0.25mm of their true longitudinal position with respect to No. 1 and No. 18 leads. All dimensions are in millimeters. Note: Toshiba does not assume any responsibility for use of any circuitry described; no circuit patent licenses are implied, and Toshiba reserves the right, at any time without notice, to change said circuitry. — A48 —

TMM41464AP/AT/AZ-10, TMM41464AP/AT/AZ-12 TMM41464AP/AT/AZ-15 @ Plastic ZIP Unit in mm Ty OW 7 ° : I ETOTN HUTT TAN oe 2 3 6 8 2 “a 16 «16 2 ae — A4o — _ ee

TMM41464AP/AT/AZ-10, TMM41464AP/AT/AZ-12 TMM41464AP/AT/AZ-15 @ Plastic LCC Unit in om a : INDEX DOT " o Fy q H 3 q 0 ° <—Ssoaooo TwoEx_conuER LLese~cor é =) = ss = ; — A50 —

Product Information

TMM41464 specifications and overview.

Summary

SILICON MONOLITHIC N-CHANNEL SILICON GATE MOS

Description

SILICON MONOLITHIC N-CHANNEL SILICON GATE MOS

Source title TMM41464 Datasheet(PDF) - Toshiba Semiconductor

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