TMM2018AP TOSHIBA | Alldatasheet

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Technical content

TMM2018AP-25, TMM2018AP-35, TMM2018AP-45

DESCRIPTION

‘The TMM2018AP is a 16,384 bits high speed and low power static random access memory organized as 2,048 words by 8 bits and operates from a single 5V supply. Toshiba's high performance device technology provides both high speed and low power features with a maximum access time of 25ns/35ns/45ns and maximum operating current cof 150mA/135mA/135mA. When CS goes high, the device is deselected and placed in a low power standby mode in which maximum standby current is 20mA. Thus the TMM2018AP is most suitable for use in cache memory and high speed storage. The TNM2018AP is offered in a 24 pin standard plastic package with 0.3 inch width for high density assembly. The TNM2018AP is fabricated with ion implanted N channel silicon gate MOS technology for high performance and high reliability. FEATURES} + Single 5V power supply + Fast access time + Fully static operation tacc™25ns: 'TMM2018AP~25, + All inputs and outputs: Directly TTL compatible tacc=35ns: TMM2018AP-35 + Power down feature: CS=V1y tacc=45ns: TMM2018AP-45 + Output buffer control: OE + Low power dissipation + Three state outputs Igc=150mA: TMM2018AP-25 + Inputs protected: All inputs protection against Igc#135mA: TMN2018AP-35 static charge. T¢c=135mA: TMM2018AP-45 + Package: 24 pin standard plastic package, 0.3 inch ag P Igp-20mA width. PIN CONNECTION BLOCK DIAGRAR] arg. 2OVco os neq 2 zspre sao —— Y asd s zapine OTE g ——? Yoo q bar pe 8 gs & apoE scope] 8 uewonr | ——o oun x26 S ispaio mores & CELL ARRAY agd7 > isbee soot et 8 (ager 6x8) moge & wpe moot * voids & ishi07 eS 1fadio isp170s mi |_| rosqun 1B 10s 110 b > D 30 — eS s Eee aes ez TGS PIN NAMES| ose iS rere: = AO~A10 | Address Inputs 17080 . WH wy = vores [pe EB) oS 1/01 ~1/08} Data Input/Output 180 Ht ttt = = os Chip Select Taput i a [d& _| output Enable Input gos [enn [erouna mete — pa

[vec [over Supply Woltsge | ar Soldering Temperature - Time 260 + 10 [oor [.c. ouepot Oorsene 90. er D.C. RECOMMENDED OPERATING CONDITIONS Vin Input High Voltage [2.0 | = | vocri.o | ee Power Supply Voltage * Pulse Width: 10ns, DC: -0.5V (MIN.) D.C. CHARACTERISTICS (Ta=0~ 70°C, Vec=5vs10%) [sou [pawerce | conrnvone [win [aks [OT] Von Output High Voltage Ton=-4.0mA _ Output Leakage Current Vour=0 ~ Vcc, CS=Vr4 | - [#1.0[ ua | oo [=f so Operating Current CSV tat » | Standby Current ” CS=Vin aay [ Iser_| Peak Power-on Current CS=Vcc, Voc=0 15.5 [ - | 40 | CAPACITANCE* (Ta=25°C, f=14Hz) [semeor [_rataweren erat [a] * Note: This parameter is periodically sampled and is not 100% tested. — F4 —

TMM201GAP-25, TRE2OIGAPS5, TMM2Z018AP-45 A.C. CHARACTERISTICS (Ta=0 ~ 70°C, Vec=5Vt10%) Read Cycle toe | ovepar Frable to ourpue vata | - | as[ = | a [= | 20 | [tara | chip Selection to Outpet into | of - | e[ = [ol = | High-Z [ teu | chip Selection to Power Up Time 0 | o | - | [ - | Chip Ds oY i P De Write Cycle [wan [aux [ ows [ wae, [evs [ MAK, | Lig [tae wor tine i | | oe P= Po A.C. TEST CONDITIONS Input and Output Timing S108 Fig.l OUTPUT LOAD ps

TMM2016AP-25, TMM2018A2-35, TMM2018AP-45 TIMING WAVEFORMS. READ CYCLE 1. (WE=Vyy, CS=Vz,) tre face ‘on: _ pov OE ‘op as | a ae READ CYCLE 2. (RE=Vyy, OE=V11) Fas] N a tke ——— nd touz CURKENT Isp WRITE CYCLE 1. . ‘we .; tow _ _ bral = WO WAU tw a LoLZ. tps tpn bin [bara tn sranue Dp _ 6

TMM201SAP-25, TMM2O1SAP-35, TMMZ2018AP-45 WRITE CYCLE 2. two nea. iF TAS. - el we DouT lps | UDH Dan par in erase Note: 1. In read cycle 2, all addresses are valid prior to or coincident with CS transition low. 2. The operating temperature (Ta) is guaranteed with transverse air flow exceeding 400 linear feet per minute. pe

TMM2018AP-25, TMM2G1SAP-25, THM201SAP4S OUTLINE DRAWINGS Unit in mm 2 13 i T y Soomax 26240.28 3; WURU RA OIs) = i h 5 | i ‘ " 2644 025 2th llossois sano letter 1ez015 Note: Each lead pitch is 2.54mm. All leads are located within 0.25mm of their longitudinal position with respect to No.1 and No.24 leads. — Fe —