TMC7300

TMC7300 TRINAMIC | Alldatasheet

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Technical content

POWER DRIVER FOR DC MOTORS INTEGRATED CIRCUITS TRINAMIC Motion Control GmbH & Co. KG Hamburg, Germany TMC7300 Datasheet FEATURES AND BENEFITS Voltage Range 2V (1.8V) … 11V DC Battery Operation min. 2 AA / NiMh cells, or 1-2 Li-Ion cells 1 / 2 DC motors up to 2A / 2.4A with velocity & torque control Direct Bridge control for solenoids, relays, lamps, motors… Single Wire UART for two-motor torque and velocity control Standby <50nA typ. current draw Low RDSon LS 170mΩ & HS 170mΩ (typ.) Parallel Option for single DC motor Motor Load Feedback available Full Protection & Diagnostics Tiny of QFN 3*3 with 20 pins

APPLICATIONS

IOT & Handheld devices Battery operated motors 4-Channel Relay- and LED driving Printers, POS Toys Office and home automation CCTV, Security HVAC Mobile medical devices

DESCRIPTION

Working from a single or dual Li-Ion cell or dual or more AA batteries the TMC7300 is optimally suited for battery operated equipment. Its two full-bridges allow either control of two DC motors, PWM -control of LEDs, or protected st andalone peripheral driving, using a polarity sig nal per half - bridge. Operate up to two DC motors via simple UART control for direction, velocity and torque. Integrated power -MOSFETs with internal charge -pump for best -in-class RDSon even at low supply volt age, handle motor current up to 1.2A per motor continuously, or the double current in parallel connection . Together with a tiny standby current, this guarantees a long battery life . Protection and diag nostic features support robust and reliable operation. This advanced driver ensures efficient and relia ble operation for cost - effective and highly competitive solutions. Low Voltage Driver for One or Two DC Motors up to 2A (2.4A) peak – UART based Control for Torque and Velocity. 4 Half Bridge Peripheral Driver Option. BLOCK DIAGRAM

TMC7300 DATASHEET (Rev. 1.01 / 2019-NOV-06) 2 www.trinamic.com APPLICATION EXAMPLES: SIMPLE SOLUTIONS – HIGHLY EFFECTIVE The TMC 7300 scores with a high power density using integrated power MOSFETs and a complete integrated DC motor contr ol logic, to control velocity and limit torque, or for torque controlled operation. It covers a wide spectrum of applications from battery systems to embedded applications with up to 2A (2.4A) current per motor. Extensive support enables rapid design cycles and fast time-to- market with highly competitive products. M OA1 OA2 TMC7300 UART CPUHigh-Level Interface UART INTERFACE FOR CONTROL OF 2 DC MOTORS MOB1 OB2 M OA1 OA2 TMC7300 UART CPUHigh-Level Interface UART INTERFACE FOR CONTROL OF 1 DC MOTOR (UP TO 2.4A) OB1 OB2 M OA1 OA2 OB1 OB2

4 HALF BRIDGE PERIPHERAL DRIVERS

A1, A2, B1, B2, HS TMC7300ERROR nSTANDBY, EN Current Sense RLED ORDER CODES Order code PN Description Size [mm2] TMC7300-LA 00-0191 Low voltage DC motor driver 3 x 3 TMC7300-LA-T 00-0191T -T denotes tape on reel packing of devices TMC7300-BOB 40-0186 Break out Board with TMC7300 20 x 25 TMC7300-EVAL 40-0187 Evaluation board for TMC7300 85 x 55 ESELSBRÜCKE 40-0098 Connector board fitting to Landungsbrücke 61 x 38 LANDUNGSBRÜCKE 40-0167 Baseboard for TMC 7300-EVAL and further evaluation boards 85 x 55 The TMC7300 acts a peripheral driver for a low -voltage application. It drives resistive loads, like a LED, or inductive loads like motors or solenoids. It offers up to 2A peak output current while adding protection features. A CPU operates the driver via its UART interface. It configures mo tor direction and velocity as well as current limit, and accesses diag nostic information via the UART interface. The TMC7300 takes care for voltage and current regulation and overcurrent protection. With single motor operation, output current is increased and power dissipation is reduced. The TM C7300-EVAL is part of TRINAMICs universal evaluation board system which provides a convenient handling of the hardware as well as a user-friendly software tool for evaluation. The TMC7300 evaluation board system consists of three parts: STARTRAMPE (base board), Eselsbrücke (connector board with test points), and TMC7300-EVAL.

TMC7300 DATASHEET (Rev. 1.01 / 2019-NOV-06) 3 www.trinamic.com Table of Contents 2.1 PACKAGE OUTLINE TMC7300 (UART MODE) . 7 2.4 SIGNAL DESCRIPTIONS / HALFBRIDGE MODE .. 8

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1 Principles of Operation

The TMC7300 low voltage motor driver is intended for battery-operated, space- and standby-power- critical driver applications. It is optimized for DC motor control, as well as control of other magnetic actuators or lamp and LED driving. Optionally the driver supplies four protected half -bridges for direct control by four input signals. A highly efficient power stage , boosted by an internal charge pump for best in-class RDSon resistance, provides high motor current from a tiny package even at low supply voltages. With this, dual AA batteries can be drained down to typic ally 2.0V (voltage must not drop below 1.8V, provide sufficient supply buffer capacitors). The TMC7300 requires just a few control pins on its tiny package , as full control is possible via UART interface. Protection and diag nostic features support robust and reliable operation. A simple -to-use 8 bit UART interface opens up more tuning and control options. Industries’ most advanced low voltage motor driver family upgrades designs to efficient and reliable operation for cost -effective and highly competitive solutions. 1n-100n 10V EN GND DIE PAD Full Bridge A Full Bridge B +VM VS OA1 OA2 OB1 OB2 Current regulator BRB BRA RSA Use low inductivity SMD type for RSA and RSB RSB 100n VCP driver enable (disable prior to configuration!) DC motor PWM 100n 1.8VOUT Place near IC with short path to die pad Connect directly to GND plane Connect directly to GND plane VIO/ NSTDBY TMC7300 1.8V Voltage regulator Internal charge pump 1.8V to 5V I/O voltage / standby 100n Programmable Diagnostic Output Configuration Interface AD0 AD1 ENUART DIAG UART Address Configuration (GND or VIO) Driver error UART B. Dwersteg, © TRINAMIC 2016 UART interface + Register Block UART interface Standby detector Optional external capacitor BRA BRBMODE STANDBY STANDBY CLK oscillator 500k M M 10µ Or low ESR 100µF electrolytic / depending on supply resistance and motor current Figure 1.1 TMC7300 basic application block diagram for two DC motors MODES OF OPERATION: OPTION 1: DC-Motor Driver with Full Diagnostics and Control This mode allows operation of two DC motors, or a single motor with double current. Options (label UART): + Full control over motor velocity and direction by setting PWM voltage for each motor + Control motor torque limit for both motors, by setting a common current limit + Use current limit to safely avoid battery overload during acceleration or when motor is blocked + Detailed diagnostics and thermal management + Passive braking and freewheeling for flexible, lowest power stop modes UART

TMC7300 DATASHEET (Rev. 1.01 / 2019-NOV-06) 5 www.trinamic.com Access to multiple driver ICs is possible u sing 4 different address settings or via an analog multiplexer IC. M OA1 OA2 TMC7300 UART CPUHigh-Level Interface UART INTERFACE FOR CONTROL OF 1 DC MOTOR (UP TO 2.4A) OB1 OB2 M OA1 OA2 TMC7300 UART CPUHigh-Level Interface UART INTERFACE FOR CONTROL OF 2 DC MOTORS MOB1 OB2 Figure 1.2 UART controlled single or Dual DC motor driver OPTION 2: 4 Half Bridge Peripheral Driver This mode uses the power stage to drive inductive or resistive loads. A single-shunt measurement can be realized, using the bridge foot point connections to add a sense resistor. The TMC7300 protects the power stage against overload. An external microcontroller cont rols each half bridge using a single input / optionally a common high-side PWM. M OA1 OA2 OB1 OB2 A1, A2, B1, B2, HS TMC7300ERROR nSTANDBY, EN Current Sense RLED Figure 1.3 Peripheral Power Driver

1.1 Control Interfaces

The TMC7300 supports both, discrete control lines for basic operation and a UART based single wire interface with CRC checking.

1.1.1 UART Interface

The single wire interface allows unidirectional operation (for parameter setting only), or bi -directional operation for full control and diagnostics. It can be driven by any standard microcontroller UART or even by bit banging in software. Baud rates from 9600 Baud to 500k Baud may be used. No baud rate configuration is required , as the TMC 7300 automatically adapts to the masters’ baud rate . The frame format is identical to the intelligent TRINAMIC controller & driver ICs TMC51XX and TMC22XX. A CRC checksum allows data transmission over longer distance. For fixed initialization sequences, store the data including CRC into the µC, thus consuming only a few 10 0 bytes of code for a full initialization. CRC may be ignored during read access, if not desired. This makes CRC use an optional feature! The IC has a fixed address selected by 2 pins . Multiple drivers can be programmed in parallel by tying UART

TMC7300 DATASHEET (Rev. 1.01 / 2019-NOV-06) 6 www.trinamic.com together all interface pins, in case no read access is required. An optional addressing can be provide d by analog multiplexers, like 74HC4066. From a software point of view the TMC 7300 is a peripheral with a number of control and status registers. Most of them can eithe r be written only or are read only. Some of the registers allow both , read and write access. In case read-modify-write access is desired for a write only register, a shadow register can be realized in master software.

1.2 Moving and Controlling the Motor

1.2.1 PWM control

The motor is operated by an internal PWM generator. The PWM acts like a dedicated voltage source for the motor. E.g. a 50% duty cycle will let the motor turn like with 50% of the supply voltage. A negated duty cycle will turn the motor in the oppos ite direction. This way, direction and velocity can be controlled like with a programmable power source. By slowly increasing / decreasing the duty cycle, the motor can be softly accelerated and decelerated.

1.2.2 Internal Current Limiter

When a DC -motor is me chanical loaded, its current increases. Therefore, a current limit allows limitation of motor torque. At the same time, the power source, e.g. a dual AA battery with a certain internal resistance is protected against voltage drop due to overload. This feat ure especially is helpful when moving the motor to a mechanical obstacle. The action of the current limiter can be read back via the interface.

1.3 Mechanical Load Sensing

When a DC -motor is mechanical loaded, its current increases. Therefore, a current limi t allows limitation of motor torque. The TMC7300 reports back, when this load limit is achieved. This feature especially is helpful when moving the motor to a mechanical obstacle.

1.4 Protection and Diagnostics

By adapting the sense resistor to the desired ma ximum current, a sensitive protection of the respective half bridge is reached. In case the voltage drop across the sense resistor plus internal Power MOSFET exceeds roughly 1V, the power stage become s disabled and the error is reported via the interface, or via the DIAG output. UART UART

TMC7300 DATASHEET (Rev. 1.01 / 2019-NOV-06) 7 www.trinamic.com

2 Pin Assignments

The TMC7300 comes in a tiny package in order to fit miniaturized devices. For the ease of use, pinning is shown separately for all four function-modes.

2.1 Package Outline TMC7300 (UART mode)

© B. Dwersteg, TRINAMIC OB2 BRB OA1 OB1 1.8VOUT MODE VS BRA OA2 EN ENUART B1_AD0 PWM_UART TMC7300 (DC motor) VIO/NSTDBY VCP GND 12345 109876 1514131211 1617181920 DIAG B2_AD1 PAD Figure 2.1 TMC7300 Pinning Top View Stepper Driver – QFN20, 3x3mm², 0.4mm pitch

2.2 Signal Descriptions / UART mode

VCP 2 Charge pump voltage. Optionally t ie to VS using 1nF to 100nF capacitor. May be left unconnected in stepper mode. A1 3 DI A1 input not used in UART mode (tie to GND or VCC_IO) A2 4 DI A2 input not used in UART mode (tie to GND or VCC_IO) B1_AD0 5 DI Selection of UART Address 0…3 (AD0=LSB, AD1=MSB) B2_AD1 6 DI EN 7 DI Enable input. The power stage becomes switched off (all motor outputs floating) when this pin becomes driven to a low level. Also used to clear error flags. ENUART 8 DI Mode selection input. ENUART, MODE: 01: 4 Halfbridge 10: UART enabled (CLK, TST input in factory test mode) MODE 9 DI PWM_UART 10 DIO UART Input/Output. VIO/NSTDBY 11 1.8V to 5V IO supply voltage for all digital pins. IC goes to standby mode and resets, when this pin is pulled to GND. DIAG 12 DO Diagnostic output. Hi gh level upon driver error or stall . Reset by EN=low. 1.8VOUT 13 Output of internal 1.8V regulator. Attach 100nF ceramic capacitor to GND near to pin for best performance. Provide the shortest possible loop to the GND pad. GND 14 GND. Connect to GND plane near pin. OB2 15 DC motor 2 output 2 BRB 16 Sense resistor connection for coil B or DC motor 2 . Place sense resistor to GND near pin. OB1 17 DC motor 2 output 1

TMC7300 DATASHEET (Rev. 1.01 / 2019-NOV-06) 8 www.trinamic.com Pin Number Type Function VS 18 Motor supply voltage. Provide filtering capacity >10µF near pin with shortest possible loop to GND pad. OA1 19 DC motor 1 output 2 BRA 20 Sense resistor connection for coil A or DC motor 1 . Place sense resistor to GND near pin. Exposed die pad - Connect the exposed die pad to a GND plane. Provide as many as possible vias for heat transfer to GND plane.

2.3 Package Outline / Halfbridge mode

© B. Dwersteg, TRINAMIC OB2 1.8VOUTTMC7300 (4 Halfbridge) VIO/NSTDBY VCP GND 12345 109876 1514131211 1617181920 MODE EN ENUART PWM BRB OA1 OB1 VS BRA OA2 DIAG PAD Figure 2.2 TMC7300 Pinning Top View Stepper Driver – QFN20, 3x3mm², 0.4mm pitch

2.4 Signal Descriptions / Halfbridge mode

Charge pump voltage. Optionally t ie to VS using 1nF to 100nF capacitor. May be left unconnected if maximum 2 pins change at a time. A1 3 DI Bridge A output 1 polarity A2 4 DI Bridge A output 2 polarity B1 5 DI Bridge B output 1 polarity B2 6 DI Bridge B output 2 polarity EN 7 DI Enable input. The power stage becomes switched off (all motor outputs floating) when this pin becomes driven to a low level. Also used to release driver after fault shutdown. ENUART 8 DI tie to GND MODE 9 DI tie to VIO PWM 10 DI Common PWM for high -side drivers. Tie high to enable high -side drivers as controlled by A and B inputs. Influences high -side driver, only. VIO/NSTDBY 11 1.8V to 5V IO supply voltage for all digital pins. IC goes to standby mode and resets, when this pin is pulled to GND. DIAG 12 DO Diagnostic output. High level upon driver error. Reset by EN=low. 1.8VOUT 13 Output of internal 1.8V regulator. Attach 100nF ceramic capacitor to GND near to pin for best performance. Provide the shortest possible loop to the GND pad.

TMC7300 DATASHEET (Rev. 1.01 / 2019-NOV-06) 9 www.trinamic.com Pin Number Type Function GND 14 GND. Connect to GND plane near pin. OB2 15 Bridge B output 2 BRB 16 Foot point of bridge B. Connect to GND directly, or via a sense resistor, if external current measurement is desired. OB1 17 Bridge B output 1 VS 18 Bridge supply voltage. Provide filtering capacity >10µF near pin with shortest possible loop to GND pad. OA1 19 Bridge A output 1 BRA 20 Foot point of bridge A. Conne ct to GND directly, or via a sense resistor. Exposed die pad - Connect the exposed die pad to a GND plane. Provide as many as possible vias for heat transfer to GND plane.

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3 Sample Circuits

The sample circuits show the connection of external compone nts in different operation and supply modes. The connection of the bus interface and further digital signals is left out for clarity. The TMC7300 is configured for different application modes by two pins, as well as by set tings available via the UART interface.

3.1 DC Motor Operation

+VM VS OA1 OA2 OB1 OB2 Current regulator BRB BRA RSA Use low inductivity SMD type for RSA and RSB RSB 100n VCP driver enable (disable prior to configuration!) DC motor PWM 100n 1.8VOUT Place near IC with short path to die pad Connect directly to GND plane Connect directly to GND plane VIO/ NSTDBY TMC7300 1.8V Voltage regulator Internal charge pump 1.8V to 5V I/O voltage / standby 100n Programmable Diagnostic Output Configuration Interface AD0 AD1 ENUART DIAG UART Address Configuration (GND or VIO) Driver error UART B. Dwersteg, © TRINAMIC 2016 UART interface + Register Block UART interface Standby detector Optional external capacitor BRA BRBMODE STANDBY STANDBY CLK oscillator 500k M M 10µ Or low ESR 100µF electrolytic / depending on supply resistance and motor current Figure 3.1 Operation of two DC-Motors for 1.8V to 11V supply The standard application circuit uses a minimum set of additional components to operate one or two DC motors. Each one sense resistor set s the motor current limit. See chapter 7 to choose the right sense resistor value. Take care to keep power supply ripple due to chopper operation at a few 100mV, max., especially whe n low voltage operation is desired. Use ceramic, or low ESR capacitors for filtering the power supply . The capacitors need to cope with the current ripple c aused by chopper operation. A minimum capacity of 100µF electrolytic, or a 10µF ceramic capacitor near the driver is recommended to keep ripple low. Actual demand will depend on the internal power supply resistance and the desired motor current. VCC_IO can be supplied from a separate supply , e.g. a 3.3V regulator , or be driven by a microcontroller port pin. AD0 and AD1 set the UART address. Ensure, that the EN pin is driven by the microcontroller in order to disable the motor prior to initialization! Apply a pulldown resistor for EN to keep it low during power-up. Basic layout and component hints Place sense resistors and all filter capacitors as close as possible to the related IC pins. Use a solid common GND for all GND connections, also for sense resistor GND. Connect 1.8VOUT filtering capacitor directly to 1.8VOUT and the GND pin. See layout hints for more details. Low ESR electrolytic capacitors are recommended for VS filtering unless supply resistance is very low. Attention Power up with EN -pin low. Set GCONF.pwm_direct prior to enabling the driver via EN -pin. Otherwise the motor will run directly after power-up.

TMC7300 DATASHEET (Rev. 1.01 / 2019-NOV-06) 11 www.trinamic.com 1n-100n 10V EN GND DIE PAD Full Bridge A Full Bridge B +VM VS OA1 OA2 OB1 OB2 Current regulator BRB BRA Use low inductivity SMD type for RSRS 100n VCP driver enable (disable prior to configuration!) DC motor PWM 100n 1.8VOUT Place near IC with short path to die pad Connect directly to GND plane VIO/ NSTDBY TMC7300 1.8V Voltage regulator Internal charge pump 1.8V to 5V I/O voltage / standby 100n Programmable Diagnostic Output Configuration Interface AD0 AD1 ENUART DIAG UART Address Configuration (GND or VIO) Driver error UART B. Dwersteg, © TRINAMIC 2016 UART interface + Register Block UART interface Standby detector BRA BRBMODE STANDBY STANDBY CLK oscillator 500k M 10µ Or low ESR 100µF electrolytic / depending on supply resistance and motor current Figure 3.2 Operation of a single DC-Motor (double current) A single DC -motor can be ope rated at double current (up to 2.4A), by paralleling both power -stages. Before operating the motor, the IC has to be switched to parallel mode, because default setting will cause a short circuit between the bridges and a high current flow, which will trigger overcurrent protection. Therefore e nsure, that the EN pin is driven by the microcontroller in order to disable the motor prior to initialization . Apply a pulldown resistor for EN additionally to ensure power-up with a low level. Attention For parallel operation , power up with EN -pin low. S et GCONF.par_mode in order to force identical drive signals prior to enabling the driver via EN-pin. In this mode, a capacitor is required on pin VCP.

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3.2 Halfbridge Driver Mode

Halfbridge driver mode offers four separate half-bridges to individually drive and control resistive and inductive loads, like LEDs, solenoids, etc. In case a current measurement is desired, each two halfbridges allow adding a foot point shunt resistor. Keep voltage drop in this resistor to maximum 400mV for normal operation. A common high -side PWM input allows switch ing off all high -side drivers at the same time. I t does not influence drivers, where the low -side is on. If more than two drivers are switched at the same time, a capacitor on p in VCP is recommended. The diagnostic output signals any overcurrent or overtemperature condition. The driver automatically restarts after power -up, or after cycling VIO_NSTDBY pin. 1n-100n 10V EN GND DIE PAD Full Bridge A Full Bridge B +VM VS OA1 OA2 OB1 OB2 BBM logic BRB BRA 100n VCP opt. driver enable 100n 1.8VOUT Place near IC with short path to die pad Connect directly to GND plane or via sense resistor VIO/ NSTDBY TMC7300 1.8V Voltage regulator Internal charge pump 1.8V to 5V I/O voltage / standby 100n Diagnostic Output DIAG Individual output polarity control Driver error B. Dwersteg, © TRINAMIC 2016 Standby detector Optional external capacitor +VIO STANDBY STANDBY 500k MODE ENUART PWMCommon PWM for High-Side Inductive or resistive loads between each two pins, to GND or to VM Inductive or resistive loads between each two pins, to GND or to VM Connect directly to GND plane or via sense resistor +VIO 10µ Or low ESR 100µF electrolytic / depending on supply resistance and motor current Figure 3.3 Halfbridge Driver Mode

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3.3 Highly Efficient Driver

The TMC7300 in tegrates a highly efficient power stage, offering low RDSon even at low supply voltages, due to its internal charge pump. This enables high motor current drive c apability and low power dissipation for battery powered applications. Figure 3.4 RDSon Variation over Supply Voltage When operating at a high motor current, the driver power dissipation due to MOSFET swi tch on - resistance significantly heats up the driver. This power dissipation will significantly heat up the PCB cooling infrastructure, if operated at an increased duty cycle. This in turn leads to a further increase of driver temperature. An increase of te mperature by about 100°C increases MOSFET resistance by roughly 50%. This is a typical behavior of MOSFET switches. Therefore, under high duty cycle, high load conditions, thermal characteristics have to be carefully taken into account, especially when increased environment temperatures are to be supported. Refer the thermal characteristics and the layout hints for more information. As a thumb rule, thermal properties of the PCB design become critical for the tiny QFN 3mm x 3mm package at or above 0.8A mean motor current for increased periods of time. For currents above 0.8A, a 4 -layer PCB layout with 5 via contact of the die attach pad to the GND plane is required. Keep in mind that resistive power dissipation raises with the square of the motor current. On the other hand, this means that a small reduction of motor current significantly saves heat dissipation and energy. Pay special attention to good thermal properties of your PCB layout, when going for 0.8A mean current or more. 0,00 50,00 100,00 150,00 200,00 250,00 300,00 350,00 400,00 RDSon vs. VS RDSon (LS) [mOhm] RDSon(HS) [mOhm]

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3.4 Low Power Standby

Battery powered applications, as well as mains powered applications conforming to EU energy saving regulations, often require a standby mode, where the power -supply remains on. Current consumption in this mode must be minimized. Control near zero p ower TMC7300 standby operation by switching off the I/O supply voltage on VIO_NSTDBY pin. At the same time make sure, that no digital input pin is at a high level. An input level above VIO_NSTDBY would hinder pulling down VIO_NSTDBY, due to the ESD protection diodes in each digital I/O pin. These diodes clamp each input to a level between GND and the IO supply voltage VIO_NSTDBY. Therefore, stop the motor first, and allow sufficient time for the motor to come to a standstill, pull the enable input EN low, a nd also all other input pins, to switch off the motor completely before switching off VIO voltage. All dri ver registers are reset to their power-up defaults after leaving standby mode. See Figure 3.5. readydriver power updriver standbymoving PWM ramp down motor stopped driver disable +IMAX -IMAX EN VIO_NSTDBY Actual Power Draw <1µA 5mA Operation Motor Current (example) Limit by IRUN 3mA +VIO +VIO up to 0.5ms Inputs Phase of Operation 0% duty cycle Software controlled ramp Motor driver disabled Low current standby Ready to move, send UART configuration before Enable Motion stop Figure 3.5 Switching to Standby and Back On

3.5 Very low I/O voltage operation

In ca ses, where an I /O voltage of 1.8V (or even lower , due to tolerance ) is to be used, the VIO undervoltage threshold level might be too high, to safely release the TMC7300 from reset state. A simple way to av oid the need for an add itional I/O voltage regulator (e.g. 2 V type), is to use the internal 1.8V regulator to self-supply the TMC7300 VIO pin. In order to allow power-up, the voltage on pin at VIO/NSTDBY has to be forced to min. 1. 4V. In order to go back to low power standby, pull it down to less than 0.6V. A PNP transistor gives a low resistive switch to supply VIO. 100n 1.8VOUT VIO/ NSTDBY 1.8V Voltage regulator 100n Standby detector STANDBY STANDBY 500k Control Signals Digital I/O µC powered with 1.8V +-10% I/O voltage Standby 470R Powerup BC858B Figure 3.6 Additional Circuit for I/O voltage <1.80V

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4 UART Single Wire Interface

The UART single wire interface allows control of the TMC7300 with any microcontroller UART. It shares transmit and receive line like an RS485 based interface. Data transmission is secured using a cyclic redundancy check, so that increased interface distances (e.g. over cables between two PCBs) can be bridged withou t danger of wrong or missed commands even in the event of electro -magnetic disturbance. The automatic baud rate detection makes this interface easy to use.

4.1 Datagram Structure

4.1.1 Write Access

UART WRITE ACCESS DATAGRAM STRUCTURE each byte is LSB…MSB, highest byte transmitted first 0 … 63 sync + reserved 8 bit slave address RW + 7 bit register addr. 32 bit data CRC 0…7 8…15 16…23 24…55 56…63 1 0 1 0 Reserved (don’t cares but included in CRC) SLAVEADDR=(MS2, MS1) register address 1 data bytes 3, 2, 1, 0 (high to low byte) CRC A sync nibble precedes each transmission to and from the TMC 7300 and is embedded into the first transmitted byte, followed by an addressing byte (0 to 3, selected by pins MS1 (LSB) and MS2 for TMC7300). Each transmission allows a synchronization of the internal baud rate divider to the master clock. The actual baud rate is adapted and variations of the internal c lock frequency are compensated. Thus, the baud rate can be freely chosen within the valid range. Each transmitted byte starts with a start bit (logic 0, low level on UART pin) and ends with a stop bit (logic 1, high level on UART pin). The bit time is calc ulated by measuring the time from the beginning of start bit (1 to 0 transition) to the end of the sync frame (1 to 0 transition from bit 2 to bit 3 ). All data is transmitted byte wise. The 32 bit data words are transmitted with the highest byte first. A minimum baud rate of 9000 baud is permissible, assuming maximum clock frequency (worst case for low baud rate). Maximum baud rate is fCLK/16 due to the required stability of the baud clock. The slave address SLAVEADDR is selected by MS1 (bit 0) and MS2 (b it 1) in the range 0 to 3 . Bit 7 of the register address identifies a Read (0) or a Write (1) access. Example: Address 0x10 is changed to 0x90 for a write access. The communication becomes reset if a pause time of longer than 63 bit times between the star t bits of two successive bytes occurs. This timing is based on the last correctly received datagram. In this case, the transmission needs to be restarted after a failure recovery time of minimum 12 bit times of bus idle time. This scheme allows the master to reset communication in case of transmission errors. Any pulse on an idle data line below 16 clock cycles will be treated as a glitch and leads to a timeout of 12 bit times, for which the data line must be idle. Other errors like wrong CRC are also treat ed the same way. This allows a safe re -synchronization of the transmission after any error conditions. Remark, that due to this mechanism an abrupt reduction of the baud rate to less than 15 percent of the previous value is not possible. Each accepted wri te datagram becomes acknowledged by the receiver by in crementing an internal cyclic datagram counter (8 bit). Reading out the datagram counter allows the master to check the success of an initialization sequence or single write accesses. Read accesses do n ot modify the counter. The UART line must be logic high during idle state. UART

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4.1.2 Read Access

UART READ ACCESS REQUEST DATAGRAM STRUCTURE each byte is LSB…MSB, highest byte transmitted first sync + reserved 8 bit slave address RW + 7 bit register address CRC 1 0 1 0 Reserved (don’t cares but included in CRC) SLAVEADDR=(MS2,MS1) register address 0 CRC The read access request datagram structure is identical to the write access datagram structur e, but uses a lower number of user bits. Its function is the addressing of the slave and the transmission of the desired register address for the read access. The TMC 2300 responds with the same baud rate as the master uses for the read request. In order t o ensure a clean bus transition from the master to the slave, the TMC 2300 does not immediately send the reply to a read access, but it uses a programmable delay time afte r which the first reply byte becomes sent following a read request. This delay time ca n be set in multiples of eight bit times using SENDDELAY time setting (default=8 bit times) according to the needs of the master. UART READ ACCESS REPLY DATAGRAM STRUCTURE each byte is LSB…MSB, highest byte transmitted first sync + reserved 8 bit master address RW + 7 bit register addr. 32 bit data CRC 0…7 8…15 16…23 24…55 56…63 1 0 1 0 reserved (0) 0xFF register address 0 data bytes 3, 2, 1, 0 (high to low byte) CRC The read response is se nt to the master using address code %1111 1111. The transmitter becomes switched inactive four bit times after the last bit is sent. Address %11111111 is reserved for read access replies going to the master. Hint Find an example for generating read and write datagrams in the TMC2300 calculation sheet.

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4.2 CRC Calculation

An 8 bit CRC polynomial is us ed for checking both read and write access. It allows detection of up to eight single bit errors. The CRC8 -ATM polynomial with an initial value of zero is applied LSB to MSB, including the sync - and addressing byte. The sync nibble is assumed to always be correct. The TMC7300 responds only t o correctly transmitted datagrams containing its own slave address. It increases its datagram counter for each correctly received write access datagram. 𝐶𝑅𝐶 = 𝑥8 +𝑥2 +𝑥1 +𝑥0 SERIAL CALCULATION EXAMPLE CRC = (CRC << 1) OR (CRC.7 XOR CRC.1 XOR CRC.0 XOR [new incoming bit]) C-CODE EXAMPLE FOR CRC CALCULATION void swuart_calcCRC(UCHAR* datagram, UCHAR datagramLength) int i,j; UCHAR* crc = datagram + (datagramLength-1); // CRC located in last byte of message UCHAR currentByte; *crc = 0; for (i=0; i<(datagramLength-1); i++) { // Execute for all bytes of a message currentByte = datagram[i]; // Retrieve a byte to be sent from Array for (j=0; j<8; j++) { if ((*crc >> 7) ^ (currentByte&0x01)) // update CRC based result of XOR operation *crc = (*crc << 1) ^ 0x07; else *crc = (*crc << 1); currentByte = currentByte >> 1; } // for CRC bit } // for message byte

4.3 UART Signals

The UART interface on the TMC7300 uses a single bi-direction pin: UART INTERFACE SIGNAL UART Non-inverted data input and output. I/O with Schmitt Trigger and VCC_IO level. AD0 IC UART address bit 0 (LSB) AD1 IC UART address bit 1 The IC checks PDN_UART for correctly received datagrams with its own address continuously. It adapts to the baud rate based on the sync nibble, as described before. In case of a read access, it switches on its output drivers and sends its response using th e same baud rate. The output becomes switched off four bit times after transfer of the last stop bit. Master CPU (µC with UART) Slave #1 different address (R/W access) UART TXD RXD Master CPU (µC with UART) Slave #1 same address (write only access) UART TXD Slave #2 same address (write only access) UART Slave #2 different address (R/W access) UART AD1 AD0 AD1 AD0 +VCCIO Figure 4.1 Attaching the TMC7300 to a microcontroller UART

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4.4 Addressing Multiple Slaves

If read access is not used, and all slaves are to be programmed with the same initialization values, no addressing is required. All slaves can be programmed in parallel like a single device (Figure 4.1.). ADDRESSING MULTIPLE SLAVES As the TMC7300 uses has a limited number of UART addresses, in principle only up to four ICs can be accessed per UART interface channel. Adding analog switches allows separated access to individual ICs. This scheme is similar to an SPI bus with individual slave select lines (Figure 4.2). Master CPU (µC with UART) Slave UART Slave Slave TXD RXD +VIO 22k SWO ¼ 74HC4066Select#1Port pin Port pin Port pin UART+VIO 22k SWO ¼ 74HC4066 UART+VIO 22k SWO ¼ 74HC4066 Select#2 Select#3 74HC1G125 Optional buffer for transmission over long lines or many slaves. Port pin Figure 4.2 Addressing multiple TMC7300 via single wire interface using analog switches PROCEED AS FOLLOWS TO CONTROL MULTIPLE SLAVES: - Set the UART to 8 bits, no parity. Select a baud rate safely within the valid range. At 250kBaud, a write access transmission requires 320µs (=8 Bytes * (8+2) bits * 4µs). - Before starting an access, activate the select pin going to the analog switch by setting it high. All other slaves select lines shall be off, unless a broadcast is desired. - When using the optional buffer, set TMC 7300 transmission send delay to an appropriate value allowing the µC to switch off the buffer before receiving reply data. - To start a transmission, activate the TXD line buffer by setting the control pin low. - When sending a read access request, switch off the buffer after transmission of the last stop bit is finished. - Take into account, that all transmitted data also is received by the RXD input.

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5 Register Map

This chapter gives an overview of the complete register set. Some of the registers bundling a number of single bits are detailed in extra tables. The functional practical application of the settings is detailed in dedicated chapters. Note - Reset default: All registers become reset to 0 upon power up, unless otherwise noted. - Add 0x80 to the address Addr for write accesses! NOTATION OF HEXADECIMAL AND BINARY NUMBERS 0x precedes a hexadecimal number, e.g. 0x04 % precedes a multi-bit binary number, e.g. %100 NOTATION OF R/W FIELD R Read only W Write only R/W Read- and writable register R+C Clear upon read OVERVIEW REGISTER MAPPING REGISTER DESCRIPTION General Configuration Registers These registers contain - global configuration - global status flags - interface configuration Chopper Register Set This register set offers registers for - chopper settings, e.g. frequency - passive braking and freewheeling options - driver diagnostics - driver enable / disable Motor Control Registers Register set for actual control of motor operation UART

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5.1 General Registers

GENERAL CONFIGURATION REGISTERS (0X00…0X0F) R/W Addr n Register Description / bit names RW 0x00 10 GCONF Bit GCONF – Global configuration flags

0 PWM_direct (Reset default=0)

0: Do not use this mode. 1: Normal DC-motor operation Attention: Do not enable driver prior to setting this flag. Motors 1 would start running. 1 extcap (Reset default=0) 0: Operation without external capacitor on VCP. 1: External capacitor available. No switching delays. 2 par_mode (Reset default=0) 0: normal operation (dual motor) 1: Single DC-motor operation: P arallel operation for single motor. B ridge OA1 and OB1, OA2 and OB2 output identical signals . Control is by bridge A, only. Externally bridge the outputs and the sense resistor connection. Attention: Do not enable driver prior to setting this flag, if outputs are bridged! 3 reserved / set to 0 4 reserved / set to 0 5 reserved / set to 0 6 reserved / set to 0 7 test_mode 0: Normal operation 1: Enable analog test output on pin DIR IHOLD[1..0] selects the function of DIR: 0…1: T120, DAC Attention: Not for user, set to 0 for normal operation! WC 0x01 3 GSTAT Bit GSTAT – Global status flags (Re-Write with ‘1’ bit to clear respective flags) 0 reset 1: Indicates that the IC has been reset since the last read access to GSTAT. All registers have been cleared to reset values. 1 drv_err 1: Indicates, that the driver has been shut down due to overtemperature or short circuit detection since the last read access. Read DRV_STATUS for details. The flag can only be cleared when all error conditions are cleared. 2 u3v5 1: Actual state of the supply voltage comparator. A high value means that the voltage sinks below 3.5V. This flag is not latched and thus does not need to be cleared. R 0x02 8 IFCNT Interface transmission counter. This register becomes incremented with each successful UART int erface write access. Read out to check the serial transmission for lost data. Read accesses do not change the content. The counter wraps around from 255 to 0. W 0x03 4 SLAVECONF Bit SLAVECONF

TMC7300 DATASHEET (Rev. 1.01 / 2019-NOV-06) 21 www.trinamic.com GENERAL CONFIGURATION REGISTERS (0X00…0X0F) R/W Addr n Register Description / bit names 11..8 SENDDELAY for read access (time until reply is sent): 0, 1: 8 bit times 2, 3: 3*8 bit times 4, 5: 5*8 bit times 6, 7: 7*8 bit times 8, 9: 9*8 bit times 10, 11: 11*8 bit times 12, 13: 13*8 bit times 14, 15: 15*8 bit times R 0x06 IOIN Bit INPUT (Reads the state of all input pins available)

0 EN (1=enable driver)

1 NSTDBY (0=standby, 1=enable)

2 AD0

3 AD1

4 DIAG

5 1: UART interface on

6 UART input

7 MODE input

0: UART controlled operation 8 A2 9 A1

10 COMP_A1A2

1: during LS passive braking: A1 voltage > A2 voltage

11 COMP_B1B2

1: during LS passive braking: B1 voltage > B2 voltage 31.. VERSION: 0x40=first version of the IC Identical numbers mean full digital compatibility.

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5.2 Motor Control

MOTOR CONTROL REGISTER SET (0X10…0X1F) R/W Addr n Register Description / bit names W 0x10 CURRENT_ LIMIT Bit CURRENT_LIMIT – Driver current control 0 motorrun (Reset default=1) 1: Normal motor operation 0: Enable freewheeling options. The motor becomes stopped in case fre ewheeling or passive braking is selected (PWM_CONF). 12..8 IRUN (Reset default=31) Run current limit for both motors Set a lower value to limit motor torque . Each full bridge current is individually cycle by cycle limited by IRUN setting. When current limiting is not active, OLA resp. OLB become set. Hint: Choose sense resistors in a way, that normal IRUN is 16 to 31 for best performance. W 0x22 PWM_AB Bit PWM_DIRECT – Driver current control 8..0 PWM_A, signed: Bridge A PWM duty cycle 24..16 PWM_B, signed: Bridge B PWM duty cycle

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5.3 Chopper Control Registers

CHOPPER CONTROL REGISTER SET (0X6C…0X7F) R/W Addr n Register Description / bit names Range [Unit] RW 0x6C 32 CHOPCONF Chopper and driver configuration See separate table! Reset default= 0x13008001 R 0x6F 32 DRV_ STATUS Driver status flags and current level read back See separate table! RW 0x70 22 PWMCONF StealthChop PWM chopper configuration See separate table! Reset default= 0xC40D1024

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5.3.1 CHOPCONF – Chopper Configuration

0X6C: CHOPCONF – CHOPPER CONFIGURATION Bit Name Function Comment 31 diss2vs Low side short protection disable 0: Short protection low side is on 1: Short protection low side is disabled 30 diss2g short to GND protection disable 0: Short to GND protection is on 1: Short to GND protection is disabled 29 - reserved set to 0 or leave unmodified 23 - reserved set to 0 or leave unmodified 16 tbl1 TBL blank time select %00 … %11: Set current comparator blank time to 16, 24, 32 or 40 clocks Hint: %00 or %01 is recommended for most applications (Default: %01) 15 tbl0 14 - reserved set to 0 0 enabledrv driver enable 1: Enable driver (Default: 1, enable)

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5.3.2 PWMCONF – Voltage PWM Mode StealthChop

0X70: PWMCONF – VOLTAGE MODE PWM STEALTHCHOP Bit Name Function Comment 31 - reserved set to 0 or leave unmodified 23 - reserved set to 0 22 - reserved set to 0 21 freewheel1 Allows different standstill modes Stand still option when motor current setting is zero (I_HOLD=0). %00: Normal operation (always selected with motorrun=1) %01: Freewheeling %10: Coil shorted using LS drivers (passive braking) %11: Coil shorted using HS drivers (passive braking) 20 freewheel0 19 - reserved set to 0 or leave unmodified 18 - reserved set to 0 or leave unmodified 17 pwm_freq1 PWM frequency selection %00: fPWM=2/1024 fCLK %01: fPWM=2/683 fCLK %10: fPWM=2/512 fCLK %11: fPWM=2/410 fCLK 16 pwm_freq0 15 - reserved set to 0 or leave unmodified 7 - reserved set to 0 or leave unmodified

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5.3.3 DRV_STATUS – Driver Status Flags

0X6F: DRV_STATUS – DRIVER STATUS FLAGS AND CURRENT LEVEL READ BACK Bit Name Function Comment 31.. - 0 Ignore these bits 9 t150 150°C comparator 1: Temperature threshold is exceeded, driver is off 8 t120 120°C comparator 1: Temperature prewarning threshold is exceeded 7 lib load indicator phase B 1: Current for motor cannot be reached. 0: Respective motor goes into current / torque limit Hint: This is just an informative flag. The driver takes no action upon it. False detection may occur in fast motion and standstill. Check during slow motion, only. 6 lia load indicator phase A 5 s2vsb low side short indicator phase B 1: Short on low-side MOSFET detected on bridge A or B. The driver becomes disabled. The flags stay active, until the driver is disabled by software ( enabledrv=0) or by the ENN input. 4 s2vsa low side short indicator phase A 3 s2gb short to ground indicator phase B 1: Short to GND detected on bridge A or B. The driver becomes disabled. The flags stay active, until the driver is disabled by software ( enabledrv=0) or by the ENN input. 2 s2ga short to ground indicator phase A 1 ot overtemperature flag 1: The overtemperature limit has been reached. Drivers become disabled until otpw is also cleared due to cooling down of the IC. The overtemperature flag is common for both bridges. 0 otpw overtemperature pre- warning flag 1: The o vertemperature pre -warning threshold is exceeded. The overtemperature pre -warning flag is common for both bridges.

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6 Chopper Options

In order to match the motor voltage or current to a certain level, the effective PWM voltage becomes scaled depending on the settings IRUN and PWM_A respectively PWM_B. Current limit takes over, in case the motor current exceeds the limit as programmed by IRUN. This way, torque is limited as desired, as well as current draw from the battery. Reaching the current limit can be used as informative event: check lia resp. lib flags. The Chopper PWM frequency can be chosen in four steps in order to adapt the chopper frequency to the motor inductance . It balances low current ripple vs. increased dynamic power dissipation at higher frequency. CHOICE OF PWM FREQUENCY Clock frequency fCLK PWM_FREQ=%00 fPWM=2/1024 fCLK PWM_FREQ=%01 fPWM=2/683 fCLK (default) PWM_FREQ=%10 fPWM=2/512 fCLK PWM_FREQ=%11 fPWM=2/410 fCLK Table 6.1 Choice of PWM frequency – green / light green: recommended

6.1 Load Indicator Flags

lia and lib indicate, if the original duty cycle is driven, or if current regulation limits the PWM duty cycle. When read back as active , the original duty cycle is driven. A cleared flag results from current limiting, e.g. when the motor is blocked, highly loaded, or still accelerating.

6.2 Freewheeling and Passive Braking

The chopper unit provides different options for motor standstill. These options can be enabled by setting CURRENT_LIMIT.motorrun to zero , and choosing the desired option using via FREEWHEEL setting. The PWM and current regulator become disabled in freewheeling and coil sh ort modes. This way, either freewheeling, or passive braking ca n be realized. Passive braking is an effective eddy current motor braking, which consumes a minimum of energy, because no active current is driven into the coils. PARAMETERS RELATED TO CHOPPER Parameter Description Setting Comment PWM_FREQ PWM frequen cy selection. Use the lowest setting giving good results. The frequency measured at each of the chopper outputs is half of the effective chopper frequency fPWM. 0 fPWM=2/1024 fCLK 1 fPWM=2/683 fCLK 2 fPWM=2/512 fCLK 3 fPWM=2/410 fCLK FREEWHEEL Stand still option for both motors, when motorrun flag is cleared (motorrun=0). The freewheeling option makes the motor easy movable, while coil short options realize a passive braking.

0 Normal operation

1 Freewheeling

2 Coil short via LS drivers

3 Coil short cia HS drivers

enabledrv General enable for the motor driver 0 Driver off, all outputs hi-Z

1 Driver enabled

TBL Comparator blank time. This time needs to safely cover the switching event and the duration of the ringing on the sense resis tor. Choose a setting of 1 or 2 for typical applications . For high er capacitive loads, 3 may be required. 0 16 tCLK 1 24 tCLK 2 32 tCLK 3 40 tCLK UART

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7 Selecting Sense Resistors

Set the desired maximum motor current by selecting an appropriate value f or the sense resistor. The following table shows the RMS current values which can be reached using standard resistors and motor types fitting without additional motor current scaling . Additional 15mΩ PCB resistance are included in the calculation. CHOICE OF RSENSE AND RESULTING MAX. MOTOR CURRENT RSENSE [Ω] current limit [A] IRUN=31 1.50 0.21 1.20 0.26 1.00 0.31 0.82 0.38 0.75 0.41 0.68 0.45 0.50 0.60 470m 0.63 390m 0.75 330m 0.87 270m 1.03 220m 1.23 180m 1.44 150m 1.67 120m 1.97 100m 2.24 (single motor, parallel operation) 82m 2.56 (single motor, parallel operation) *) At high currents, duty cycle restriction for motion might apply, due to heat up of IC and board. Sense resistors should be carefully selected. The full motor current fl ows through the sense resistors. Due to chopper operation the sense resistors see pulsed current from the MOSFET bridges. Therefore, a low-inductance type such as film or composition re sistors is required to prevent voltage spikes causing ringing on the se nse voltage inputs leading to unstable measurement results. A lso, a low- inductance, low-resistance PCB layout is essential. Any common GND path for the two sense resistors must be avoid ed, because this would lead to coupling between the two current sense s ignals. A massive ground plane is best. Please also refer to layout considerations in chapter 14. The sense resistor needs to be able to conduct the peak motor coil current in motor standstill conditions, unless standby power i s reduced. Under normal conditions, the sense resistor conducts less than the coil RMS current, because no current flows through the sense resistor during the slow decay phases of the chopper. A 0.25W type is sufficient for most applications up to 800mA RMS. Attention Be sure to use a symmetrical sense resistor layout and short and straight sense resistor traces of identical length. Well matching sense resistors ensure best performance. A compact layout with massive ground plane is best to avoid parasitic resistance effects.

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7.1 Motor Torque Limit

Select the sense resistor s to deliver enough current for the motor at full current scale. This is the default current scaling (IRUN = 31). IRUN allows for scaling of the limit from 1/32 to 32/32: MOTOR CURRENT CALCULATION WITH UART CONTROL OPTION: 𝐼𝑀𝐴𝑋 = 𝐼𝑅𝑈𝑁 +1 32 ∗ 𝑉𝐹𝑆 𝑅𝑆𝐸𝑁𝑆𝐸 +30𝑚Ω VFS is the full-scale voltage (please refer to electrical characteristics, VSRT). Typical value is 325mV. PARAMETERS FOR MOTOR CURRENT CONTROL Parameter Description Setting Comment IRUN Current limit scale when motor is running. 0 … 31 scaling factor

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8 Driver Diagnostic Flags

The TMC7300 drivers supply a complete set of diagnostic and protection capabilities, like short to GND protection, short to VS protection and undervoltage detection. A detection of current limit condition allows testing if a motor coil connection is interrupted. See the DRV_STATUS table for details.

8.1 Temperature Measurement

The driver integrates a two-level temperature sensor (pre -warning and therm al shutdown) for diagnostics and for protection of the IC against excess heat . Heat is mainly generated by the motor driver stages. Most critical situations, where the driver MOSFETs could be overheated, are avoided by the short to GND protection. For many applications, the overtemperature pre -warning will indicate an abnormal operation situation and can be used to initiate u ser warning or power reduction measures like motor current reduction. The thermal shutdown is just an emergency measure and temperatur e rising to the shutdown level should be prevented by design. TEMPERATURE THRESHOLDS Temperature Level Comment 150°C This value is relatively safe to switch off the driver stage before the IC can be destroyed by overheating. On a large PCB, the powe r MOSFETs reach roughly 150°C peak temperature when the temperature detector is triggered with this setting. 120°C Temperature level for pre -warning. In most applications, reaching this level is a sign for abnormal heat accumulati on. The overtemperature pre-warning threshold of 120°C gives lots of headroom to react to high driver temperature, e.g. by reducing motor current, or increasing waiting-time in between of two motions. Attention Overtemperature protection cannot in all cases avoid thermal destr uction of the IC. In case the rated output current is exceed, excess heat generation can quickly heat up the driver before the overtemperature sensor can react. This is due to a delay in heat conduction over the IC die. After triggering the overtemperature sensor (ot flag), the driver remains switched off until the system temperature falls below the pre -warning level ( otpw) to avoid continuou s heating to the shutdown level.

8.2 Short Protection

The TMC7300 power stages are protected against a short circuit c ondition by an additional measure - ment of the current flowing through each of the power stage MOSFETs. This is important, as most short circuit conditions result from a motor cable insulation defect, e.g. when touching the conducting parts connected to the system ground. The short detection is protected against spurious triggering, e.g. by ESD discharges, by retrying three times before switching off the motor. Once a short conditio n is safely detected, both driver bridges become switched off, and the s2ga or s2gb flag, respectively s2vsa or s2vsb becomes set. In order to restart the motor, disabl e and re - enable the driver. Note, that short protection cannot protect the system and th e power stages for all possible short events, as a short event is rather un defined and a complex network of external components may be involved. Therefore, short circuits should basically be avoided.

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8.3 Diagnostic Output

The diagnostic output DIAG provide s error status information , especially when using the drive r in stand-alone mo de. An active DIAG output shows that the driver cannot work normally. Figure 8.1 shows the signals controlling the output. DIAG Power-on reset Short circuit (s2vs, s2g) over temperature (ot)S R Q drv_err Power stage disable (e.g. pin EN, STANDBY) Overtemperature (ot) Figure 8.1 DIAG output

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9 Quick Configuration Guide

This guide is meant as a practical tool to come to a first configuration . Do a minimum set of measurements and decisions for tuning the driver to fit the application. PWM setup Set I_RUN as desired for motor torque limit from 0 up to 31. Set motorrun=1 Set initial PWM duty cycle in PWM_A and PWM_B and enable motor using EN pin. Operate motor using PWM_A, PWM_B, I_RUN, and motorrun Check hardware setup and motor max. current Start with motor disabled upon power -up (EN=low) Configure GCONF to operate one or two motors: GCONF.PWM_direct =1 Single motor in parallel config? N For parallel operation with a single motor, set GCONF.par_mode = 1 Y Passive braking desired? N Set PWM_CONF.freewheel to %10 for braking when motorrun=0 Y Figure 9.1 Configuration and Motor operation Hint Use the evaluation board to explore settings and to generate the required configuration datagrams. UART

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10 External Reset

The chip is loaded with default values during power on via its internal pow er-on reset. In order to reset the chip to power on defaults, any of the supply voltages monitored by internal reset circuitry (VS or VCC_IO) must be cycled. It is easiest and safest to cycle VCC_IO in order to completely reset the chip. Also, current cons umed from VCC_IO is low and therefore it has simple driving requirements. Due to the input protection diodes not allowing the digital inputs to rise above VCC_IO level, all inputs must be driven low during this reset operation. When this is not possible, a n input protection resistor may be used to limit current flowing into the related inputs.

11 Clock Oscillator

The clock is the timing reference for all functions: the chopper frequency, the blank time, the standstill power down timing , and the internal step pulse generator etc. The on -chip clock oscillator is not calibrated, but relatively temperature -stable. The internal clock frequency is roughly 12MHz. When the internal pulse generator is used, and increased precision is desired, measure the internal freq uency by doing a test -motion (with motor disabled) and adapt the pulse frequency to the actual value of the frequency. Store the calibration value into the microcontroller’s EEPROM for the application.

TMC7300 DATASHEET (Rev. 1.01 / 2019-NOV-06) 34 www.trinamic.com The maximum ratings may n ot be exceeded under any circumstances. Operating the circuit at or near more than one maximum rating at a time for extended periods shall be avoided by application design. Parameter Symbol Min Max Unit Supply voltage operating with inductive load *) VVS -0.5 11.2 V Supply and bridge voltage max. *) VVMAX 13 V I/O supply voltage VVIO -0.5 5.5 V digital supply voltage V1V8OUT -0.5 1.95 V Logic input voltage VI -0.5 VVIO+0.5 V MODE input voltage (Do not exceed both, VCC_IO and 5VOUT by more than 10%, as this enables a test mode) VVREF -0.5 6 V Maximum current to / from digital pins and analog low voltage I/Os IIO +/-10 mA 1.8V regulator output current (internal plus external load) I5VOUT 20 mA Power bridge repetitive output current IOx 2.0 A Maximum VS current (both bridges operating) IVS 2.8 A Maximum BRx current IOx 2.0 A Junction temperature TJ -50 150 °C Storage temperature TSTG -55 150 °C ESD-Protection for handling (Human body model, HBM) VESD 1.5 kV *) Stray inductivity of GND and VS connections will lead to ringing of the supply voltage when driving an inductive load. This ringing results from the fast switching slopes of the driver outputs in combination with reverse recovery of the body diodes of the output driver MOSFETs. Even small trace inductivities as well as stray inductivity of sense resistors can easily generate a few volts of ringing leading to temporary voltage overshoot . This should be considered when working near the maximum voltage.

13.1 Operational Range

Parameter Symbol Conditions Min Max Unit Junction temperature TJ -40 125 °C Supply voltage VVS 2 11 V Supply & IO voltage battery empty limit VVS 1.8 V I/O supply voltage VVIO 2 5.25 V Mean current per full bridge output for continuous operation (value for design guideline) IRMS VVS<2.1V 0.6 A VVS≥2.1V 0.8 VVS≥2.2V 1.0 RMS motor current per fullbridge, duty cycle limited operation IRMS VVS≥2.5V 1.2 A Peak output current per fullbridge output IOx 1.7 A Sum of output current (VS supply pin current) IVS 2.4 A

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13.2 DC and Timing Characteristics

DC characteristics contain the spread of values guaranteed within the specified supply voltage range unless otherwise specified. Typical values represent the average value of all p arts measured at +25°C. Temperature variation also causes stray to some values. A device with typical values will not leave Min/Max range within the full temperature range. Power supply current DC-Characteristics VVS = 8.0V, VVIO=3.3V Parameter Symbol Conditions Min Typ Max Unit Total supply current, driver disabled IVS disable via UART 4 8 mA disable via EN=0 1.5 3 mA Total supply current, operating, IVS IVS default chopper, no load 7 12 mA IO supply current operating IVIO no load on outputs, inputs at VIO or GND 60 200 µA Total supply current, low-power standby, IVS IVS VVIO < 0.2V 0.03 1 µA Motor driver section DC- and Timing-Characteristics VVS = 8.0V, VVIO=3.3V Parameter Symbol Conditions Min Typ Max Unit RDSON lowside MOSFET RONL measure at 100mA, 25°C, VVS ≥ 3.2V 0.17 0.25 Ω RDSON highside MOSFET RONH measure at 100mA, 25°C, VVS ≥ 3.2V 0.17 0.25 Ω slope, rising tSLPRISE value for reference 20 ns slope, falling tSLPFALL value for reference 7 ns Current sourcing, driver off IOIDLE OXX pulled to GND 6 13 30 µA Recommended / max. VS power- up slope to >5V VSRAMP Hint: Normally satisfied due to ext. capacitor on VS. <0.33 rcd.

1 V/µS

Charge pump DC-Characteristics Parameter Symbol Conditions Min Typ Max Unit Charge pump output voltage (mean) VVCP-VVS VVS ≥ 3.5V 4.2 5.1 5.7 V Linear regulator DC-Characteristics VVS = 8.0V, VVIO=3.3V Parameter Symbol Conditions Min Typ Max Unit Output voltage V5VOUT I1V8OUT = 0mA TJ = 25°C 1.65 1.8 1.95 V Clock oscillator and input Timing-Characteristics Parameter Symbol Conditions Min Typ Max Unit Clock oscillator frequency fCLKOSC tJ=-50°C 11.7 MHz fCLKOSC tJ= 25°C 9 12.0 15 MHz fCLKOSC tJ=150°C 12.1 MHz

TMC7300 DATASHEET (Rev. 1.01 / 2019-NOV-06) 36 www.trinamic.com Detector levels DC-Characteristics VVS = 8.0V, VVIO=3.3V Parameter Symbol Conditions Min Typ Max Unit VVS undervoltage threshold for RESET VUV_VS VVS rising 1.8 2.1 V VVS falling 1.5 1.7 1.85 V VVIO undervoltage threshold for RESET VUV_VIO VVIO rising 1.8 1.9 V VVIO falling 1.5 1.7 VVIO low power standby input voltage VUV_VIOHYST 0.4 V Worst case power-up delay time VVS = 2.0V, VVIO=2.0V 500 µs Short to GND detector threshold (VVS - VOx) VOS2G VVS ≥ 3.5V required for operation 0.5 0.8 V Short to VS detector threshold (VOx) VOS2G 1.0 1.2 1.6 V Short detector delay (high side / low side switch on to short detected) tS2G 1 µs Overtemperature prewarning 120°C tOTPW Temperature rising 100 120 140 °C Overtemperature shutdown 150°C tOT150 Temperature rising 135 150 170 °C 3.5V Detector Threshold U3V5 VVS3V5 VS falling 3.15 3.5 V 3.5V Detector Threshold U3V5 VVS3V5 VS rising 3.7 4.1 V COMPA1A2, COMPB1B2 Offset Voltage VCABOFS Lowside MOSFETs ON +-10 mV Sense resistor voltage levels DC-Characteristics fCLK=16MHz Parameter Symbol Conditions Min Typ Max Unit Sense input peak threshold voltage (low sensitivity) VSRT csactual=31 CUR_A/B=248 Hyst.=0; IBRxy=0 325 mV Sense input tolerance / motor current full scale tolerance ICOIL -5 +5 % Internal resistance from pin BRxy to internal sense comparator (additional to sense resistor) RBRxy 30 mΩ Digital pins DC-Characteristics Parameter Symbol Conditions Min Typ Max Unit Input voltage low level VINLO -0.3 0.3 VVIO V Input voltage high level VINHI 0.7 VVIO VVIO+0.3 V Input Schmitt trigger hysteresis VINHYST VVIO=3.3V 0.12 VVIO V Output voltage low level VOUTLO IOUTLO = 2mA, VVIO=3.3V 0.2 V Output voltage high level VOUTHI IOUTHI = -2mA, VVIO=3.3V VVIO-0.2 V Input leakage current IILEAK -1 1 µA Digital pin capacitance C 3.5 pF

TMC7300 DATASHEET (Rev. 1.01 / 2019-NOV-06) 37 www.trinamic.com

13.3 Thermal Characteristics

The following table shall give an idea on the thermal resistance of the package. The thermal resistance for a four -layer board will provide a good idea on a typical application. Actual thermal characteristics will depend on the PCB layout, PCB type and PCB size. The thermal resistance will benefit from thicker CU (inner) layers for spreading heat horizontally within the PCB. Also, air flow will reduce thermal resistance. A thermal resistance of 40K/W for a typical board means, that the package is capable of continuously dissipating 1W at an ambient temperature of 85°C with the die temperature staying below /at 125°C. Note, that a thermally optimized layout is required. Parameter Symbol Conditions Typ Unit Typical power dissipation PD 1A RMS in two motors (or single motor with 2A RMS in parallel circuit), 35kHz chopper, 11V, 60°C peak surface of package 1 W Typical power dissipation PD 0.7A RMS in two motors (or single motor with 1.4A RMS in parallel circuit), sinewave, 35kHz chopper, 11V, 45°C peak surface of package 0.5 W Thermal resistance junction to ambient on a multilayer board RTMJA Dual signal and two internal power plane board (2s2p) as defined in JEDEC EIA JESD51-5 and JESD51-7 (FR4, 35µm CU, 70mm x 133mm, d=1.5mm)

40 K/W

Thermal resistance junction to case RTJC Junction to heat slug of package 7 K/W Table 13.1 Thermal characteristics Note A spread-sheet for calculating power dissipation is available on www.trinamic.com.

TMC7300 DATASHEET (Rev. 1.01 / 2019-NOV-06) 38 www.trinamic.com

14 Layout Considerations

14.1 Exposed Die Pad

The TMC7300 uses its die attach pad to dissipate heat from the drivers and the linear regulator to the board. For best electrical and thermal performance, use a reasonable amount of solid, thermally conducting vias between the die attach pad and the ground pla ne. The printed circuit board should have a solid ground plane spreading heat into the board and providing for a stable GND reference.

14.2 Wiring GND

All signals of the TMC7300 are referenced to their respective GND. Directly connect all GND pins under the device to a common ground area (GND and die attach pad). The GND plane right below the die attach pad should be treated as a virtual star point. For thermal reasons, the PCB top layer shall be connected to a large PCB GND plane spreading heat within the PCB. Attention Especially the sense resistors are susceptible to GND differences and GND ripple voltage. No current other than the sense resistor current should flow on their connections to GND and to the TMC 7300. Optimally place them close to the IC, with one or more vias to the GND plane for each sense resistor. The two sense resistors should not share a common ground connection trace or vias, as also PCB traces have a certain resistance.

14.3 Supply Filtering

The 1.8VOUT output voltage ceramic filtering capaci tor (100 nF recommended) should be placed as close as possible to the 1.8VOUT pin, with its GND return going directly to the die pad or the nearest GND pin. This ground connection shall not be shared with other loads or additional vias to the GND plane. Use as short and as thick connections as possible. The motor supply pins VS should be decoupled with a ceramic, or a ceramic plus a n electrolytic capacitor (47 μF or larger is recommended , depending on the motor coil current ). Place the capacitors close to the device. Take into account that the switching motor coil outputs have a high dV/dt. Thus, capacitive stray into high resistive signals can occur, if the motor traces are near other traces over longer distances.

TMC7300 DATASHEET (Rev. 1.01 / 2019-NOV-06) 39 www.trinamic.com

14.4 Layout Example

Placement (Excerpt) Top Layout (Excerpt, showing die pad vias) The complete schematics and layout data for all evaluation boards are available on the TRINAMIC website.

TMC7300 DATASHEET (Rev. 1.01 / 2019-NOV-06) 40 www.trinamic.com

15.1 Dimensional Drawings QFN20

Attention: Drawings not to scale. Figure 15.1 Dimensional drawings QFN20

TMC7300 DATASHEET (Rev. 1.01 / 2019-NOV-06) 41 www.trinamic.com Parameter [mm] Ref Min Nom Max total thickness A 0.8 0.85 0.9 stand off A1 0 0.035 0.05 mold thickness A2 0.65 0.67 lead frame thickness A3 0.203 Lead width b 0.15 0.2 0.25 body size X D 3.0 body size Y E 3.0 lead pitch e 0.4 exposed die pad size X J 1.6 1.7 1.8 exposed die pad size Y K 1.6 1.7 1.8 lead length L 0.35 0.4 0.45 package edge tolerance aaa 0.1 mold flatness bbb 0.1 coplanarity ccc 0.08 lead offset ddd 0.1 exposed pad offset eee 0.1

15.2 Package Codes

Type Package Temperature range Code & marking TMC7300-LA QFN20 (RoHS) -40°C ... +125°C (TMC logo) 7300

TMC7300 DATASHEET (Rev. 1.01 / 2019-NOV-06) 42 www.trinamic.com

16 Designed for Sustainability

Sustainable growth is one of the most important and urgent challenges today. We at Trinam ic try to contribute by designing highly efficient IC products, to minimize energy consumption, ensure best customer experience and long -term satisfaction by smooth and silent run, while minimizing the demand for external resources, e.g. for power supply, cooli ng infrastructure, reduced motor size and magnet material by intelligent control interfaces and advanced algorithms. Please help and design efficient and durable products made for a sustainable world.

17 Table of Figures

TMC7300 DATASHEET (Rev. 1.01 / 2019-NOV-06) 43 www.trinamic.com Version Date Author BD= Bernhard Dwersteg V0.9 2019-Jun-24 BD Edited electrical data based on prototype measurements, first version of datasheet V0.91 2019-Jul-18 BD Added RDSon measurement of power stage V1.00 2019-Aug-02 BD Minor changes V1.01 2019-Nov-06 BD Minor wording, added chapter on sustainability, added chapter on low I/O voltage operation Table 18.1 Document Revisions

19 References

[TMC7300-EVAL] TMC7300 Evaluation board: Manuals, software and PCB data available on www.trinamic.com