TLS850D0TEV50

TLS850D0TE INFINEON | Alldatasheet

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Low Dropout Linear Voltage Regulator TLS850D0TE TLS850D0TEV50 TLS850D0TEV33 Linear Voltage Regulator Automotive Power Data Sheet Rev. 1.0, 2016-10-07

Data Sheet 2 Rev. 1.0, 2016-10-07 TLS850D0TE Table of Contents Table of Contents

Data Sheet 3 Rev. 1.0, 2016-10-07 Low Dropout Linear Voltage Regulator TLS850D0TE 1O v e r v i e w

Features

Wide Input Voltage Range from 3.0 V to 40 V
Fixed Output Voltage 5 V or 3.3 V
Output Voltage Precision ≤ ±2 %
Output Current Capability up to 500 mA
Ultra Low Current Consumption typ. 40 µA
Very Low Dropout Voltage typ. 70 mV @100 mA
Stable with Ceramic Output Capacitor of 1 µF
Delayed Reset at Power-On: 16.5 ms
Enable, Undervoltage Rese t, Overtemperature Shutdown
Output Current Limitation
Wide Temperature Range
Green Product (RoHS compliant)
AEC Qualified Figure 1 PG-TO252-5

Data Sheet 4 Rev. 1.0, 2016-10-07 Functional Description The TLS850D0TE is a high performance very low dropout linear voltage regulator for 5 V (TLS850D0V50) or 3.3 V (TLS850D0V33) supply in a PG-TO252-5 package. With an input voltage range of 3 V to 40 V and very low quiescent of only 40 µA, these regulators are perfectly suitable for automotive or any other supply systems connected to the battery permanently. The TLS850D0TE provides an output voltage accuracy of 2 % and a maximum output current up to 500 mA. The new loop concept combines fast regulation and very good stability while requiring only one small ceramic capacitor of 1 µF at the output. At cu rrents below 100 mA the device will ha ve a very low typical dropout voltage of only 70 mV (for 5 V device) and 80 mV (for 3.3 V device). The operating range starts already at input voltages of only 3 V (extended operating range). This makes the TLS850D0TE also suitable to supply automotive systems that need to operate during cranking condition. The device can be switched on and off by the Enable feature as described in Chapter 5.5. The output voltage is supervised by the Reset feature, including Undervoltage Reset and delayed Reset at Power- On, more details can be found in Chapter 5.7. Internal protection features like output current limitation and overtemperature shutdown are implemented to protect the device against immediate damage due to failu res like output short circuit to GND, over-current and over-temperatures. Choosing External Components An input capacitor CI is recommended to compensate line influences. The output capacitor CQ is necessary for the stability of the regulating circuit. TLS850D0TE is designed to be also stable with low ESR ceramic capacitors. Type Package Marking TLS850D0TEV50 PG-TO252-5 850D0V50 TLS850D0TEV33 PG-TO252-5 850D0V33

Data Sheet 5 Rev. 1.0, 2016-10-07

2 Block Diagram

Figure 2 Block Diagram TLS850D0TEV50 and TLS850D0TEV33 Bandgap Reference GND QI Temperature Shutdown EN Enable Reset RO Current Limitation

Data Sheet 6 Rev. 1.0, 2016-10-07 TLS850D0TE Pin Configuration

3 Pin Configuration

3.1 Pin Assignment TLS850D 0TEV50 and TLS850D0TEV33

Figure 3 Pin Configuration

3.2 Pin Definitions and Functi ons TLS850D0TEV50 and TLS850D0TEV33

It is recommended to place a small ceramic capacitor (e.g. 100 nF) to GND, close to the IC terminals, in order to compensate line influences. See also Chapter 6.2.1 2E N Enable (integrated pull-down resistor) Enable the IC with high level input signal; Disable the IC with low level input signal; 3G N D Ground 4R O Reset Output (intergrated pull-up resistor to Q) Open collector output; Leave open if the reset function is not needed 5Q Output Voltage Connect output capacitor CQ to GND close to the IC’s terminals, respecting the values specified for its capacitance and ESR in “Functional Range” on Page 8 Heat Slug GND Heat Slug Connect to GND Connect to heatsink area; I EN RO GND Q

General Product Characteristics Data Sheet 7 Rev. 1.0, 2016-10-07

4 General Product Characteristics

4.1 Absolute Maximum Ratings

Note: 1. Stresses above the ones listed here may cause perma nent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection func tions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Table 1 Absolute Maximum Ratings 1) Tj = -40 °C to +150 °C; all voltages with respect to ground (unless otherwise specified) 1) Not subject to production test, specified by design. Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Input I, Enable EN Voltage VI, VEN -0.3 – 45 V – P_4.1.1 Output Q, Reset Output RO Voltage VQ, VRO -0.3 – 7 V – P_4.1.3 Temperatures Junction Temperature Storage Temperature Tstg -55 – 150 °C – P_4.1.8 ESD Absorption ESD Susceptibility to GND VESD -2 – 2 kV 2) HBM 2) ESD susceptibility, HBM accordin g to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF) P_4.1.9 ESD Susceptibility to GND VESD -500 – 500 V 3) CDM 3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101 P_4.1.10 ESD Susceptibility Pin 1, 5 (corner pins) to GND VESD1,5 -750 – 750 V 3) CDM P_4.1.13

Data Sheet 8 Rev. 1.0, 2016-10-07 TLS850D0TE General Product Characteristics

4.2 Functional Range

Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the Electrical Characteristics table. Table 2 Functional Range Tj = -40 °C to +150 °C; all voltages with respect to ground (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Input Voltage Range VI VQ,nom + Vdr –4 0 V 1) – 1) Output current is limited internaly an d depends on the input voltage, see Electrical Characteristics for more details. P_4.2.1 Extended Input Voltage Range VI,ext 3.0 – 40 V 2) – 2) When VI is between VI,ext,min and VQ,nom + Vdr, VQ = VI - Vdr. When VI is below VI,ext,min, VQ can drop down to 0 V. P_4.2.3 Enable Voltage Range VEN 0– 4 0 V – P_4.2.5 Output Capacitor’s Requirements for Stability CQ 1– – µ F 3)4) – 3) Not subject to production test, specified by design. 4) The minimum output capacitance requ irement is applicable for a worst case capacitance tolerance of 30% P_4.2.6 ESR ESR(CQ) –– 1 0 0 Ω 3) – P_4.2.7 Junction Temperature Tj -40 – 150 °C – P_4.2.9

General Product Characteristics Data Sheet 9 Rev. 1.0, 2016-10-07

4.3 Thermal Resistance

Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Table 3 Thermal Resistance Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Junction to Case RthJC –3 – K / W 1) – 1) Not subject to production test, specified by design P_4.3.11 Junction to Ambient RthJA –2 6 – K / W 1)2) 2s2p board 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. P_4.3.12 Junction to Ambient RthJA –1 0 9 – K / W 1)3) 1s0p board, footprint only 3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product (Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu). P_4.3.13 Junction to Ambient RthJA –5 1 – K / W 1)3) 1s0p board, 300 mm2 heatsink area on PCB P_4.3.14 Junction to Ambient RthJA –4 0 – K / W 1)3) 1s0p board, 600 mm2 heatsink area on PCB P_4.3.15

Data Sheet 10 Rev. 1.0, 2016-10-07 TLS850D0TE Block Description and Electrical Characteristics

5 Block Description and El ectrical Characteristics

5.1 Voltage Regulation

The output voltage VQ is divided by a resistor network. This fracti onal voltage is compared to an internal voltage reference and the pass transistor is driven accordingly. The control loop stability depen ds on the output capacitor CQ, the load current, the chip temperature and the internal circuit design. To ensure stable operation, the output capacitor’s capacitance and its equivalent series resistor (ESR) requirements given in “Functional Range” on Page 8 have to be maintained. For details, also see the typical performance graph “Output Capacitor Series Resistor ESR(CQ) versus Output Current IQ” on Page 15. As the output capacitor also has to buffer load st eps, it should be sized according to the application’s needs. An input capacitor CI is recommended to compensate line influences. In order to block influences like pulses and HF distortion at input side, an additional reverse polarity protection diode and a combination of several capacitors for filtering should be used. Connect the capacitors close to the component’s terminals. In order to prevent overshoots during start-up, a smooth ramp up function is implemented. This ensures almost no output voltage overshoots during start-up, mostly independent from load and output capacitance. Whenever the load current exceeds the specified limit, e.g. in case of a short circuit, the output current is limited and the output voltage decreases. The overtemperature shutdown circuit prevents the IC from immediate destruction under fault conditions (e.g. output continuously short-circuit) by switching off the power stage. After the chip has cooled down, the regulator restarts. This leads to an oscillatory behavior of the output volt age until the fault is re moved. However, junction temperatures above 150 °C are outside the maximum ratings and therefore significantly reduce the IC’s lifetime. Figure 4 Voltage Regulation Figure 5 Output Voltage vs. Input Voltage LOAD Supply CI Regulated Output VoltageIQII Bandgap Reference GND QI Temperature Shutdown EN Enable Reset RO C ESR CQ VI VQ Current Limitation V t VQ,nom VI Vdr VQVI,ext,min

Block Description and Electrical Characteristics Data Sheet 11 Rev. 1.0, 2016-10-07 Table 4 Electrical Characteristics Voltage Regulator 5 V version Tj = -40 °C to +150 °C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified) Typical values are given at Tj = 25 °C Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Output Voltage Precision VQ 4.9 5.0 5.1 V 0.05 mA < IQ <5 0 0m A

5.95 V < VI <2 8V

P_5.1.3 Output Voltage Precision VQ 4.9 5.0 5.1 V 0.05 mA < IQ <2 0 0m A

5.44 V < VI <4 0V

P_5.1.4 Output Voltage Start-up slew rate dVQ/dt 3.0 7.5 18 V/ms V I >1 8V / m s CQ =1µ F 0.5 V < VQ <4 . 5V P_5.1.7 Output Current Limitation IQ,max 501 650 1100 mA 0 V < VQ <4 . 8V P_5.1.9 Load Regulation steady-state ∆VQ,load -20 -1.5 5 mV IQ = 0.05 mA to 500 mA VI = 6 V P_5.1.11 Line Regulation steady-state ∆VQ,line -20 0 20 mV VI = 8 V to 32 V IQ =5m A P_5.1.13 Dropout Voltage Vdr = VI - VQ Vdr – 175 425 mV 1) IQ = 250 mA 1) Measured when the output voltage VQ has dropped 100 mV from the nominal value obtained at VI = 13.5V P_5.1.16 Dropout Voltage Vdr = VI - VQ Vdr –7 0 1 7 0 m V 1) IQ =1 0 0m A P_5.1.17 Power Supply Ripple Rejection PSRR –5 9 – d B 2) fripple = 100 Hz Vripple = 0.5 Vpp 2) Not subject to production test, specified by design P_5.1.18 Overtemperature Shutdown Threshold Tj,sd 151 – 200 °C 2) Tj increasing P_5.1.19 Overtemperature Shutdown Threshold Hysteresis Tj,sdh –1 5 – K 2) Tj decreasing P_5.1.20

Data Sheet 12 Rev. 1.0, 2016-10-07 TLS850D0TE Block Description and Electrical Characteristics Table 5 Electrical Characteristics Voltage Regulator 3.3 V version Tj = -40 °C to +150 °C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified) Typical values are given at Tj = 25 °C Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Output Voltage Precision VQ 3.23 3.3 3.37 V 0.05 mA < IQ <5 0 0m A

4.23 V < VI <2 8V

P_5.1.23 Output Voltage Precision VQ 3.23 3.3 3.37 V 0.05 mA < IQ <2 0 0m A

3.72 V < VI <4 0V

P_5.1.24 Output Voltage Start-up slew rate dVQ/dt 3.0 7.5 18 V/ms V I >1 8V / m s CQ =1µ F 0.33 V < VQ <2 . 9 7V P_5.1.27 Output Current Limitation IQ,max 501 650 1100 mA 0 V < VQ <3 . 1V P_5.1.29 Load Regulation steady-state ∆VQ,load -20 -1.5 5 mV IQ = 0.05 mA to 500 mA VI =6V P_5.1.31 Line Regulation steady-state ∆VQ,line -15 0 15 mV VI = 8 V to 32 V IQ =5m A P_5.1.33 Dropout Voltage Vdr = VI - VQ Vdr – 200 430 mV 1) IQ = 250 mA 1) Measured when the output voltage VQ has dropped 100 mV from the nominal value obtained at VI = 13.5V P_5.1.36 Dropout Voltage Vdr = VI - VQ Vdr –8 0 1 7 5 m V 1) IQ =1 0 0m A P_5.1.37 Power Supply Ripple Rejection PSRR –6 3 – d B 2) fripple = 100 Hz Vripple = 0.5 Vpp 2) Not subject to production test, specified by design P_5.1.38 Overtemperature Shutdown Threshold Tj,sd 151 – 200 °C 2) Tj increasing P_5.1.39 Overtemperature Shutdown Threshold Hysteresis Tj,sdh –1 5 – K 2) Tj decreasing P_5.1.40

Block Description and Electrical Characteristics Data Sheet 13 Rev. 1.0, 2016-10-07

5.2 Typical Performance Characteristics Voltage Regulator

Typical Performance Characteristics Output Voltage VQ versus Junction Temperature Tj (3.3 V version) Output Voltage VQ versus Junction Temperature Tj (5 V version) Dropout Voltage Vdr versus Junction Temperature Tj (3.3 V version) Dropout Voltage Vdr versus Junction Temperature Tj (5 V version) 0 50 100 150 3.1 3.15 3.2 3.25 3.3 3.35 3.4 3.45 3.5 Tj [°C] VQ [V] IQ = 100mA 0 50 100 150 4.8 4.85 4.9 4.95 5.05 5.1 5.15 Tj [°C] VQ [V] IQ = 100mA −40 0 50 100 150 100 150 200 250 300 350 Tj [°C] Vdr [mV] VQ = 3.3 V IQ = 100 mA IQ = 250 mA −40 0 50 100 150 100 150 200 250 300 350 Tj [°C] Vdr [mV] IQ = 100 mA IQ = 250 mA

Data Sheet 14 Rev. 1.0, 2016-10-07 TLS850D0TE Block Description and Electrical Characteristics Load Regulation ∆VQ,load versus Output Current Change IQ Line Regulation ∆VQ,line versus Input Voltage VI Output Voltage VQ versus Input Voltage VI (3.3 V version) Output Voltage VQ versus Input Voltage VI (5 V version) 0 100 200 300 400 500 −20 −18 −16 −14 −12 −10 IQ [mA] ΔVQ,load [mV] Tj = −40 oC Tj = 25 oC Tj = 150 oC VI = 6 V 10 15 20 25 30 VI [V] ΔVQ,line [mV] IQ = 5 mA Tj = −40 oC Tj = 25 oC Tj = 150 oC 0 1 2 3 4 5 6 0.5 1.5 2.5 3.5 VI [V] VQ [V] Tj = −40 °C Tj = 25 °C Tj = 150 °C IQ = 100 mA 0 1 2 3 4 5 6 VI [V] VQ [V] Tj = −40 °C Tj = 25 °C Tj = 150 °C IQ = 100 mA

Block Description and Electrical Characteristics Data Sheet 15 Rev. 1.0, 2016-10-07 Power Supply Ripple Rejection PSRR versus ripple frequency f Output Capacitor Series Resistor ESR(CQ) versus Output Current IQ Maximum Output Current IQ versus Input Voltage VI Dropout Voltage Vdr versus Output Current IQ VQ = 3.3 V VQ = 5 V f [kHz] PSRR [dB] IQ = 10 mA CQ = 1 μF Vripple = 0.5 Vpp Tj = 25 oC Tj = 25 oC 0.05 1 10 100 500 IQ [mA] ESR(CQ) [Ω] CQ = 1 μF Stable Region Unstable Region 0 10 20 30 40 200 400 600 800 1000 1200 VI [V] IQ,max [mA] Tj = −40 oC Tj = 25 oC Tj = 150 oC VQ = 0 V 0 100 200 300 400 500 100 150 200 250 300 350 400 450 500 IQ [mA] Vdr [mV] Tj = 25 oC VQ = 3.3 V VQ = 5 V

Data Sheet 16 Rev. 1.0, 2016-10-07 TLS850D0TE Block Description and Electrical Characteristics

5.3 Current Consumption

Table 6 Electrical Characteristics Current Consumption Tj = -40 °C to +150 °C, VI = 13.5 V (unless otherwise specified) Typical values are given at Tj = 25 °C Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Current Consumption Iq = II Iq,off –1 . 3 5µ A VEN =0V ; Tj <1 0 5° C P_5.3.1 Current Consumption Iq = II Iq,off –– 8µ A VEN =0 . 4V ; Tj < 125 °C P_5.3.3 Current Consumption Iq = II - IQ Iq –4 0 5 2 µ A IQ =0 . 0 5m A Tj =2 5° C P_5.3.4 Current Consumption Iq = II - IQ Iq –6 2 7 7 µ A IQ =0 . 0 5m A Tj <1 2 5° C P_5.3.7 Current Consumption Iq = II - IQ Iq –6 2 8 2 µ A 1) IQ = 500 mA Tj <1 2 5° C 1) Not subject to production test, specified by design P_5.3.11

Block Description and Electrical Characteristics Data Sheet 17 Rev. 1.0, 2016-10-07

5.4 Typical Performance Charac teristics Current Consumption

Typical Performance Characteristics Current Consumption Iq versus Output Current IQ Current Consumption Iq versus Input Voltage VI 0 100 200 300 400 500 100 IQ [mA] Iq [μA] Tj = 25 oC 5 10 15 20 25 30 35 40 100 120 140 160 180 200 VI [V] Iq [uA] Tj = −40 °C Tj = 25 °C Tj = 150 °C VEN = 5 V IQ = 50 uA

Data Sheet 18 Rev. 1.0, 2016-10-07 TLS850D0TE Block Description and Electrical Characteristics

5.5 Enable

The TLS850D0TE can be switched on and off by the Enable feature: Connect a HIGH level as specified below (e.g. the battery voltage) to pin EN to enable the devi ce; connect a LOW level as specified below (e.g. GND) to shut it down. The enable has a built in hysteresis to avoid toggling between ON/OFF st ate, if signals with slow slopes are applied to the EN input. Table 7 Electrical Characteristics Enable Tj = -40 °C to +150 °C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified) Typical values are given at Tj = 25 °C Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. High Level Input Voltage VEN,H 2––V VQ settled P_5.5.1 Low Level Input Voltage VEN,L ––0 . 8 V VQ ≤ 0.1 V P_5.5.2 Enable Threshold Hysteresis VEN,Hy 1 0 0 ––m V – P_5.5.3 High Level Input Current IEN,H ––3 . 5 µ A VEN =3 . 3V P_5.5.4 High Level Input Current IEN,H ––2 2 µ A VEN ≤ 18 V P_5.5.6

Block Description and Electrical Characteristics Data Sheet 19 Rev. 1.0, 2016-10-07

5.6 Typical Performance Characteristics Enable

Typical Performance Characteristics Input Current IIN versus Input Voltage VIN (condition: VEN = 0 V) Enabled Input Current IEN versus Enabled Input Voltage VEN Output Voltage VQ versus time (EN switched ON, 5 V version) Output Voltage VQ versus time (EN switched ON, 3.3 V version) 0 10 20 30 40 VIN [V] IIN [uA] Tj = −40 °C Tj = 25 °C Tj = 150 °C VEN = 0V 0 10 20 30 40 VEN [V] IEN [uA] Tj = −40 °C Tj = 25 °C Tj = 150 °C 0 500 1000 1500 20000 t [us] VQ, VEN [V] Tj = −40 °C Tj = 25 °C Tj = 150 °C VEN IQ = 100 mA 0 500 1000 1500 20000 t [us] VQ, VEN [V] Tj = −40 °C Tj = 25 °C Tj = 150 °C VEN IQ = 100 mA

Data Sheet 20 Rev. 1.0, 2016-10-07 TLS850D0TE Block Description and Electrical Characteristics

5.7 Reset

The TLS850D0TE’s output voltage is supervised by the Reset feature, including Undervoltage Reset and delayed Reset at Power-On. The Undervoltage Reset function sets the pin RO to LOW, in case VQ is falling for any re ason below the Reset Threshold VRT,low. When the regulator is powered on, the pin RO is held at LOW for the duration of the Power-On Reset Delay Time trd. Figure 6 Block Diagram Reset Circuit Reset Delay Time The Reset Delay Time trd is fix defined according to Table 8. Power-On Reset Delay Time The power-on reset delay time is defined by the parameter t rd and allows a microcontroller and oscillator to start up. This delay time is the time period from exceeding the upper reset switching threshold VRT,high until the reset is released by switching the reset output “RO” from “LOW” to “HIGH”. Undervoltage Reset Delay Time Unlike the power-on reset delay time, the undervoltage reset delay time is defined by the parameter t rd and considers an output undervoltage event where the output voltage VQ trigger the VRT,low threshold. Reset Blanking Time The reset blanking time trr,blank avoids that short undervoltage spikes trigger an unwanted reset “low” signal. Table 8 Reset DelayTime Reset delay timing trd fix 16.5 ms GND QISupply ROControl Reset optional CQ VDD Micro- Controller GND RRO,int IRO Timer S R Q OR Reference

Block Description and Electrical Characteristics Data Sheet 21 Rev. 1.0, 2016-10-07 Reset Reaction Time In case the output voltage of the regulator drops below the output undervoltage lower reset threshold VRT,low, the reset output “RO” is set to low, after the delay of the internal reset reaction time trr,int. The reset blanking time trr,blank is part of the reset reaction time trr,int. Reset Output “RO” The reset output “RO” is an open collector output with an integrated pull-up resistor. In case a lower-ohmic “RO” signal is desired, an external pull-up resistor can be connected to the output “Q”. Since the maximum “RO” sink current is limited, the mi nimum value of the option al external resistor “ RRO,ext” is given in Table “Reset Output RO” on Page 22. Reset Output “RO” Low for VQ ≥ 1V In case of an undervoltage reset condit ion reset output “RO” is held “low” for VQ ≥ 1 V, even if the input “I” is not supplied and the voltage VI drops below 1 V. This is achieved by su pplying the reset circuit from the output capacitor. Figure 7 Typical Timing Diagram Reset VI t VQ t VRT,low VRT,hi gh VRO t VRO,low 1 V trr,inttrd Thermal Shutdown Input Voltage Dip trr,inttrd trd t < trr,blank Under- voltage Spike at output Over- load VRH trr,int trd

Data Sheet 22 Rev. 1.0, 2016-10-07 TLS850D0TE Block Description and Electrical Characteristics Table 9 Electrical Characteristics Reset Tj = -40 °C to +150 °C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified) Typical values are given at Tj = 25 °C Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Output Undervoltage Reset 5V Version only Output Undervoltage Reset Upper Switching Threshold Output Undervoltage Reset Lower Switching Threshold - Default Output Undervoltage Reset Switching Hysteresis VRT,hy 60 100 – mV – P_5.7.3 Output Undervoltage Reset Headroom VQ - VRT VRH 200 400 – mV – P_5.7.4 Output Undervoltage Reset 3V3 Version only Output Undervoltage Reset Upper Switching Threshold Output Undervoltage Reset Lower Switching Threshold - Default Output Undervoltage Reset Switching Hysteresis VRT,hy 60 100 – mV – P_5.7.7 Output Undervoltage Reset Headroom VQ - VRT VRH 100 250 – mV – P_5.7.8 Reset Output RO Reset Output Low Voltage VRO,low –0 . 2 0 . 4 V 1 V ≤ VQ ≤ VRT; RRO ≥ 5.1 kΩ P_5.7.40 Reset Output Internal Pull-Up Resistor RRO,int 13 20 36 k Ω internally connected to Q P_5.7.41 Reset Output External Pull-up Resistor to VQ RRO,ext 5.1 – – k Ω 1V ≤ VQ ≤ VRT ; VRO ≤ 0.4 V P_5.7.42 Reset Delay Timing Reset blanking time t rr,blank –6–µ s 1) for VQ,nom =3 . 3V 1) Not subject to production test, specified by design. P_5.7.22 Reset blanking time t rr,blank –7–µ s 2) for VQ,nom =5V 2) Not subject to production test, specified by design. P_5.7.46 Internal Reset Reaction Time trr,int –72 0 µ s f o r VQ,nom =3 . 3V P_5.7.23 Internal Reset Reaction Time trr,int –1 0 3 3 µ s f o r VQ,nom =5V P_5.7.36

Block Description and Electrical Characteristics Data Sheet 23 Rev. 1.0, 2016-10-07

5.8 Typical Performance Characteristics Reset

Typical Performance Characteristics Undervoltage Reset Threshold VRT versus Junction Temperature Tj (3.3 V version) Undervoltage Reset Threshold VRT versus Junction Temperature Tj (5 V version) Power On Reset Delay Time trd versus Junction Temperature Tj Internal Reset Reaction Time trr,int versus Junction Temperature Tj 0 50 100 150 2.5 2.6 2.7 2.8 2.9 3.1 3.2 3.3 3.4 3.5 Tj [°C] VRT [V] VRT, high VRT, low IQ = 1 mA VQ = 3.3 V 0 50 100 150 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 Tj [°C] VRT [V] VRT, high VRT, low IQ = 1 mA VQ = 5 V −40 0 50 100 150 Tj [°C] trd [ms] 0 50 100 150 Tj [°C] trr,int [us] VQ = 3.3 V VQ = 5 V

Data Sheet 24 Rev. 1.0, 2016-10-07 TLS850D0TE

Application Information

6 Application Information

6.1 Application Diagram

Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. Figure 8 Application Diagram Note: This is a very simplified example of an application circuit. The function must be verified in the real application.

6.2 Selection of External Components

6.2.1 Input Pin

The typical input circuitry for a linear voltage regulator is shown in the application diagram above. A ceramic capacitor at the input, in the range of 100 nF to 470 nF, is recommended to filter out the high frequency disturbances imposed by the line e.g. ISO pulses 3a/b. This capacitor must be placed very close to the input pin of the linear voltage regulator on the PCB. An aluminum electrolytic capacitor in the range of 10 µF to 470 µF is recommended as an input buffer to smooth out high energy pulses, such as ISO pulse 2a. This capacitor should be placed close to the input pin of the linear voltage regulator on the PCB. An overvoltage suppressor diode can be used to furthe r suppress any high voltag e beyond the maximum rating of the linear voltage regulator and protect the device against any damage due to over-voltage. The external components at the input are not mandatory for the operation of the voltage regulator, but they are recommended in case of possible external disturbances.

6.2.2 Output Pin

An output capacitor is mandatory for the stability of linear voltage regulators. The requirement to the output capacitor is given in “Functional Range” on Page 8 . The graph “Output Capacitor Series Resistor ESR(CQ) versus Output Current IQ” on Page 15 shows the stable operation range of the device. CQ Load e. g. Micro Controller XC22xx GND Regulated Output VoltageSupply 100nF47µF CI1CI2 <45V DI2 1µ F DI1 Bandgap Reference GND QI Temperature Shutdown EN Enable Reset RO Current Limitation e.g. Ignition

Data Sheet 25 Rev. 1.0, 2016-10-07 TLS850D0TE is designed to be also stable with low ESR capacitors. According to the automotive requirements, ceramic capacitors with X5R or X7R dielectrics are recommended. The output capacitor should be placed as close as possible to the regulat or’s output and GND pins and on the same side of the PCB as the regulator itself. In case of rapid transients of input voltage or load current, the capacitance should be dimensioned in accordance and verified in the real application that the output stability requirements are fulfilled.

6.3 Thermal Considerations

Knowing the input voltage, the output voltage and the load profile of the application, the total power dissipation can be calculated: PD =( VI - VQ)× IQ + VI × Iq (1) with

PD: continuous power dissipation
VI : input voltage
VQ: output voltage
IQ: output current
Iq: quiescent current The maximum acceptable thermal resistance RthJA can then be calculated: RthJA,max =( Tj,max - Ta )/ PD (2) with
Tj,max: maximum allowed junction temperature
Ta: ambient temperature Based on the above calculation the proper PCB type and the necessary heat sink area can be determined with reference to the specification in “Thermal Resistance” on Page 9. Example Application conditions: VI = 13.5 V VQ = 5 V IQ = 175 mA Ta = 85 °C Calculation of RthJA,max: PD =( VI – VQ)× IQ + VI × Iq ( VI × Iq can be neglected because of very low Iq) =( 1 3 . 5V–5V )×1 7 5m A =1 . 4 8 7W RthJA,max =( Tj,max – Ta)/ PD

Data Sheet 26 Rev. 1.0, 2016-10-07 TLS850D0TE As a result, the PCB design must ensure a thermal resistance RthJA lower than 43.71 K/W. According to “Thermal Resistance” on Page 9, at least 600 mm2 heatsink area is needed on the FR4 1s0p PCB, or the FR4 2s2p board can be used to ensure a proper cooling for the TLS850D0TE in package.

6.4 Reverse Polarity Protection

TLS850D0TE is not self protected against reverse polarity faults and must be protected by external components against negative supply voltage. An external reverse polarity diode is ne eded. The absolute maximum ratings of the device as specified in “Absolute Maximum Ratings” on Page 7 must be kept.

6.5 Further Application Information

For further information you may contact http://www.infineon.com/

Data Sheet 27 Rev. 1.0, 2016-10-07

7 Package Outlines

Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). 1) Includes mold flashes on each side. 4.56

0.25 M A

6.5 5.7 MAX. ±0.1 per side 0.15 MAX. -0.26.22 ±0.59.98 (4.24) 1 A 1.14 5 x 0.6 ±0.150.8 ±0.1 +0.15 -0.05 0.1 B -0.04 +0.08 0...0.15 0.51 MIN. 0.5 B 2.3 -0.10 0.5 +0.05 -0.04 +0.08(5) -0.010.9 +0.20 B All metal surfaces tin plated, except area of cut. For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Dimensions in mm

Data Sheet 28 Rev. 1.0, 2016-10-07 TLS850D0TE

Revision History

8 Revision History

1.0 2016-10-07 Data Sheet - Initial version

Trademarks of Infineon Technologies AG AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolMOS™, CoolSET™, CORE CONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HI TFET™, HybridPACK™, I²RF™, ISOF ACE™, IsoPACK™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™, POWERCODE™, PR IMARION™, PrimePACK™, PrimeSTACK ™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SPOC™, SOLID FLASH™, TEMPFET™, th inQ!™, TRENCHSTOP™, TriCore™. Other Trademarks Advance Design System™ (ADS) of Agilent Tech nologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ o f ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR developm ent partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Co mmission Electrotechnique Internationale. IrDA™ of Infrared Dat a Association Corporation. ISO™ of INTERNATIONAL ORGANIZA TION FOR STANDARDIZATION. MATLAB™ of MathWo rks, Inc. MAXIM™ of Maxim Integrated Prod ucts, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., Om niVision™ of OmniVision Te chnologies, Inc. Openwave™ Openwave TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADI UM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2011-11-11 Edition 2016-10-07 Published by Infineon Technologies AG

81726 Munich, Germany

© 2016 Infineon Technologies AG. All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non- infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.infineon.com

Summary

Low Dropout Linear Voltage Regulator Rev. 1.0, 2016-10-07

Description