TLS820F3ELV33

TLS820F3ELV33 INFINEON | Alldatasheet

Document overview

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• PDF pages: 42

Technical content

Features

• Output voltage 3.3 V ±2%
• Current capability 200 mA
• Input voltage range from 3 V to 42 V
• Stable with 1 µF ceramic output capacitor
• Ultra low current consumption: typically 26 µA
• Very low drop out voltage: typically 100 mV at 100 mA
• Watchdog circuit for monitoring a microprocessor
• Watchdog inhibit
• Output voltage supervision by reset circuit: – Programmable undervoltage reset threshold: minimum 2.5 V – Programmable delay time
• Separate outputs for reset and watchdog
• E n a b l e
• Output current limitation
• Overtemperature shutdown
• Green Product (RoHS compliant) Potential applications
• Automotive general ECUs
• Telematics systems
• ADAS cameras and radar systems
• Navigation systems
• Body control modules Product validation Qualified for automotive applications. Product validation according to AEC-Q100.

Datasheet 2 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset

Description

The OPTIREG™ linear TLS820F3ELV33 is a high performance low drop out fixed output voltage regulator in a PG-SSOP-14 package. With an input voltage range of 3 V to 42 V and very low quiescent current of only 26 µA, these regulators are perfectly suitab le for automotive systems or othe r supply systems connected to the battery permanently. The TLS820F3ELV33 provides an output voltage accuracy of ±2% and a maximum output current of 200 mA. The loop concept combines fast regu lation and very good stability whil e requiring only one small ceramic capacitor of 1 µF at the output. The operating range star ts already at an input voltage of only 3 V (extended operating range). This makes the TL S820F3ELV33 also suitable to supply automotive systems that need to operate during cranking condition. The device can be switched on and off via Enable. The Reset supervises the output voltage, including unde rvoltage reset, delay reset at power-on and an adjustable lower reset threshold. An integrated Watchdog circuit with adjustable timing monitors the microcontroller’s operation. A shared external delay capacitor sets both reset timing and watchdog timing. Internal protection features such as output cu rrent limitation and overtemperature shutdown are implemented to protect the device against immediate dama ge due to failures such as output short circuit to GND, overcurrent and overtemperature. Type Package Marking TLS820F3ELV33 PG-SSOP-14 820F3V33

Datasheet 3 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Table of contents

Datasheet 4 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block diagram

1 Block diagram

D Reset & Watchdog Generator

Datasheet 5 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Pin configuration

2 Pin configuration

2.1 Pin assignment

Figure 2 Pin assignment PG-SSOP-14

2.2 Pin definitions and functions

It is recommended to connect a small ceramic capacitor from this pin to GND, close to the pins, in order to compensate line influences. 2n . c . Not connected Leave this pin open or connect it to GND. 3E N Enable input “High” signal enables the IC. “Low” signal disables the IC. This pin has an integrated pull-down resistor. 4n . c . Not connected Leave this pin open or connect it to GND. 5W I N H Watchdog inhibit input “Low” activates the watchdog function. “High” deactivates the watchdog function. This pin has an integrated pull-down resistor. 6W I Watchdog input Serve watchdog with trigger input signal (usable for microcontroller monitoring). This pin has an integrated pull-down resistor. 7G N D Ground 8D Delay input Connect an external capacitor from this pin to GND to set reset timing and watchdog timing. If no capacitor is placed, then disable the watchdog. Exposed Pad I WI n.c. WINH Q n.c. GND n.c. WO RO RADJ n.c. D SSOP-14 EN

Datasheet 6 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Pin configuration 9R A D J Reset threshold adjustment Connect this pin to GND to use the default reset threshold. Connect this pin to an external voltage divider to set a reset threshold other than the default value. If the reset function is not needed, then connect this pin to Q. 10 n. c. Not connected Leave this pin open or connect it to GND.

11 RO Reset output

This pin has an integrated pull-up resistor to Q. If the reset function is not needed, then leave this pin open.

12 WO Watchdog output

This pin has an integrated pull-up resistor to Q. If the watchdog function is not needed, then leave this pin open. 13 n.c. Not connected Leave this pin open or connect it to GND.

14 Q Regulator output

Connect the output capacitor C Q from this pin to GND close to the pin, respecting the values specified for its capacitance and ESR in Functional range. Pad – Exposed pad Connect the exposed pad to a heatsink area. Connect the exposed pad to GND. Pin Symbol Function

Datasheet 7 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset General product characteristics

3 General product characteristics

3.1 Absolute maximum ratings

1. Stresses above the ones listed he re may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection functions are designed to preven t IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. 3. Latchup robustness: class II according to AEC - Q100-04. Table 1 Absolute maximum ratings 1) Tj = -40°C to 150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) 1) Not subject to production test, specified by design. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Voltage rating Input voltage I VI -0.3 – 45 V – P_3.1.1 Enable voltage EN VEN -0.3 – 45 V – P_3.1.2 Output voltage Q VQ -0.3 – 7 V – P_3.1.3 Reset output RO VRO -0.3 – 7 V – P_3.1.4 Delay voltage D VD -0.3 – 7 V – P_3.1.5 Reset threshold RADJ VRADJ -0.3 – 7 V – P_3.1.6 Watchdog input WI VWI -0.3 – 7 V – P_3.1.7 Watchdog output WO VWO -0.3 – 7 V – P_3.1.8 Watchdog inhibit WINH VWINH -0.3 – 7 V – P_3.1.9 Temperature Junction temperature Tj -40 – 150 °C – P_3.1.10 Storage temperature Tstg -55 – 150 °C – P_3.1.11 ESD robustness ESD robustness to GND VESD,HBM -2 – 2 kV 2) HBM all pins 2) Human body model (HBM) robust ness according to AEC-Q100-002. P_3.1.12 ESD robustness to GND VESD, CDM -500 – 500 V 3) CDM all pins except 1, 7, 8, 14 3) Charged device model (CDM) robustness according to AEC-Q 100-011 Rev-D; voltage level refers to test condition (TC) mentioned in the standard. P_3.1.13 ESD robustness pins 1, 7, 8, 14 to GND VESD,CDM -750 – 750 V 3) CDM P_3.1.14

Datasheet 8 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset General product characteristics

3.2 Functional range

Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. Table 2 Functional range Tj = -40°C to 150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Input voltage range VI VQ,nom + Vdr –4 2 V 1) 1) See the values of output voltage VQ and drop out voltage Vdr, in Voltage regulator. P_3.2.1 Extended input voltage range VI(ext) 3–4 2 V 2) 2) The output voltage VQ follows the input voltage, but is outside the specified range, see Voltage regulator. P_3.2.2 Enable voltage range VEN 0–4 2 V – P_3.2.3 Junction temperature Tj -40 – 150 °C – P_3.2.4 Output capacitance for stable operation CQ 1–– µ F 3)4) 3) The minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%. 4) Not subject to production test, specified by design. P_3.2.5 ESR of output capacitor ESRCQ –– 2 0 Ω 4)5) 5) Relevant ESR value at f = 10 kHz. P_3.2.6

Datasheet 9 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset General product characteristics

3.3 Thermal resistance

Note: This thermal data was generated in accord ance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Table 3 Thermal resistance Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Junction to case RthJC –1 4 – K / W 1) 1) Not subject to production test, specified by design. P_3.3.1 Junction to ambient RthJA – 132 – K/W 1)2) Footprint only 2) Specified RthJA value is according to JEDEC JESD51-3 at natural convection on FR4 1s0p board; The Product (chip and package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 inner copper layer (1 × 70 µm Cu). P_3.3.2 Junction to ambient RthJA –6 7 – K / W 1)2) 300 mm2 heatsink area on PCB P_3.3.3 Junction to ambient RthJA –5 7 – K / W 1)2) 600 mm2 heatsink area on PCB P_3.3.4 Junction to ambient RthJA –4 8 – K / W 1)3) 2s2p PCB 3) Specified RthJA value is according to JEDEC JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (chip and package) was simulated on a 76.2 × 114.3 × 1.5 mm3 b o a r d w i t h 2 i n n e r c o p p e r l a y e r s ( 2×7 0µ m C u , 2×3 5µ m C u ) . Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. P_3.3.5

Datasheet 10 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics

4 Block description and electrical characteristics

4.1 Voltage regulator

A resistor network divides the output voltage VQ. The device compares this frac tional voltage to an internal voltage reference and drives the pass transistor accordingly. The control loop stability depends on the following factors:

• Output capacitor
• L o a d c u r r e n t I Q
• Chip temperature Tj
• Internal circuit design Output capacitor To ensure stable operation, the capacitance of the output capacitor CQ and its equivalent series resistorESRCQ requirements must be maintained, see Functional range. The output capacitor must be sized according to the requirements of the application, for example to buffer steps in the load current IQ. Input capacitors, reverse polarity protection diode An input capacitor CI is recommended to compensate line influe nces. In order to block influences, such as pulses and high frequency distortion at the input, use a reverse polarity protection diode and a combination of several capacitors. Connect the capacitors close to the component’s terminals. Smooth ramp-up In order to prevent overshoot duri ng startup, a smooth ramp-up function is implemented. This ensures a reduced output voltage overshoot during startup, mostly independent from load and output capacitor. Output current limitation Due to a short circuit or overload co ndition the load current can exceed th e specified limit. In this case the device limits the output current and the output voltage decreases. Overtemperature shutdown The overtemperature shutdown circuit prevents the device from imme diate destruction in case of a fault condition, for example due to a permanent short circuit at the output. In such a condition the overtemperature shutdown circuit switches off the device. After the device cools down, the regulator restarts. This leads to an oscillatory behavior of the output voltage VQ. However, any junction temperature above 150°C is outside the maximum ratings and therefore significantly reduces the lifetime of the device.

Datasheet 11 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics Figure 3 Functional block diag ram voltage regulator circuit Figure 4 Output voltage versus input voltage

4.1.1 Electrical characteristics voltage regulator

Table 4 Electrical characte ristics voltage regulator VI = 13.5 V; Tj = -40°C to 150°C; all voltages with respect to ground, direction of currents as shown in Figure 3 (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Output voltage accuracy VQ 3.23 3.3 3.37 V 50 µA ≤IQ ≤100 mA; VQ,nom + Vdr ≤VI ≤42 V P_4.1.3 Output voltage accuracy VQ 3.23 3.3 3.37 V 50 µA ≤IQ ≤200 mA; VQ,nom + Vdr ≤VI ≤28 V P_4.1.4 Output voltage accuracy VQ 3.23 3.3 3.43 V IQ ≤50 µA; VQ,nom + Vdr ≤VI ≤42 V P_4.1.6 Output voltage startup slew rate ∆VQ/∆t 7–7 0 V / m s ∆VI/∆t = 50 V/ms; CQ = 1 µF; 0.33 V ≤ VQ ≤ 2.97 V P_4.1.11 Load regulation steady state ∆VQ,load –15 -5 5 mV IQ = 0.05 mA to 200 mA; VI = 6.5 V P_4.1.12 Line regulation steady state ∆VQ,line –5 1 10 mV VI = 8 V to 32 V; IQ = 5 mA P_4.1.14 Power supply ripple rejection PSRR –6 4 – d B 2) fripple = 100 Hz; Vripple = 0.5 Vpp; IQ=10 mA P_4.1.16 Prim ary Refere nce GND QI Temperature Shutdown Current Limitation CQ ESRCQ LO AD CIVI VQ IQII Supply Regulat ed Output Voltage EN Enable V t Diagram_Output-InputVoltage.svg VQ,nom VI Vdr VQ dVQ dt Iload CQ dVQ dt ≈ IQ,max - Iload CQ ≈VI(ext),min

Datasheet 12 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics Dropout voltage Vdr = VI - VQ Vdr – 110 250 mV 1) IQ = 100 mA P_4.1.19 Dropout voltage Vdr = VI - VQ Vdr – 220 500 mV 1) IQ = 200 mA P_4.1.20 Output current limitation IQ,max 201 350 550 mA 0 V ≤VQ ≤ VQ,nom-0 . 1V P_4.1.25 Overtemperature shutdown threshold Tj,sd 151 175 200 °C 2) Tj increasing P_4.1.27 Overtemperature shutdown threshold hysteresis Tj,sdh –1 5 – K 2) Tj decreasing P_4.1.28 1) Measured when the output voltage VQ has dropped 100 mV from its nominal value obtained at VI = 13.5 V. 2) Not subject to production test, specified by design. Table 4 Electrical characte ristics voltage regulator (cont’d) VI = 13.5 V; Tj = -40°C to 150°C; all voltages with respect to ground, direction of currents as shown in Figure 3 (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 13 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics

4.1.2 Typical performance characteristics voltage regulator

Output current limitation IQmax versus input voltage VI Dropout voltage Vdr versus junction temperature Tj Dropout voltage Vdr versus output current IQ

Datasheet 14 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics Output voltage VQ versus output current IQ Output voltage VQ versus input voltage VI Line regulation ∆VQ,line versus input voltage change VI Load regulation ∆VQ,load versus output current change IQ

Datasheet 15 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics Power supply ripple rejection PSRR versus frequency f

Datasheet 16 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics

4.2 Current consumption

Table 5 Electrical characte ristics current consumption VI = 13.5 V, Tj = -40°C to 150°C; all voltages with respect to ground; direction of currents see Figure 5 (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Current consumption Iq = II Iq,off –– 1 µ A VEN = 0 V; Tj ≤105°C P_4.2.1 Current consumption Iq = II Iq,off –– 2 µ A VEN= 0 V; Tj ≤125°C P_4.2.2 Current consumption Iq = II Iq,off –– 2 µ A VEN= 0.4 V; Tj ≤125°C P_4.2.3 Current consumption Iq = II - IQ Iq –2 3 3 5 µ A IQ =5 0µ A ; Tj = 25°C; watchdog disabled P_4.2.4 Current consumption Iq = II - IQ Iq –2 6 4 3 µ A IQ = 50 µA; Tj ≤125°C; watchdog disabled P_4.2.5 Current consumption Iq = II - IQ Iq –2 9 5 1 µ A IQ = 50 µA; Tj ≤150°C; watchdog disabled P_4.2.6 Current consumption Iq = II - IQ Iq –2 6 3 9 µ A IQ =5 0µ A ; Tj = 25°C; watchdog enabled P_4.2.7 Current consumption Iq = II - IQ Iq –3 0 4 7 µ A IQ =5 0µ A ; Tj ≤125°C; watchdog enabled P_4.2.8 Current consumption Iq = II - IQ Iq –3 3 5 5 µ A IQ =5 0µ A ; Tj ≤150°C; watchdog enabled P_4.2.9 Current consumption Iq = II - IQ Iq –3 3 5 5 µ A 1) IQ = 200 mA ; Tj ≤125°C; watchdog enabled 1) Not subject to production test, specified by design. P_4.2.10

Datasheet 17 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics Figure 5 Parameter definition GND QI CQ LOAD Supply CI Regulated Output VoltageIQII VQ VI Iq Voltage Regulator

Datasheet 18 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics

4.2.1 Typical performance characteristics current consumption

Current consumption Iq versus junction temperature Tj Current consumption Iq versus output current IQ Current consumption Iq,off versus junction temperature Tj Current consumption Iq versus input voltage VI

Datasheet 19 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics Current consumption Iq,off versus input voltage VI

Datasheet 20 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics

4.3 Enable

The device can be switched on and off via the EN input:

• “High”, for example battery voltage, enables the device
• “Low”, for example GND, disables the device The enable function has a built in hy steresis to avoid toggling between on-state and off-state when signals with slow slopes are applied to the EN input. Table 6 Electrical characteristics enable VI = 13.5 V, Tj = -40°C to 150°C, all voltages with respect to ground (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Enable “high” input voltage VEN,H 2– – V VQ settled P_4.3.1 Enable “low” input voltage VEN,L –– 0 . 8 V VQ ≤0.1 V P_4.3.2 Enable threshold hysteresis VEN,Hy 90 – – mV – P_4.3.3 Enable “high” input current IEN,H –– 1 µ A VEN =3 . 3V P_4.3.4 Enable “high” input current IEN,H –– 6 µ A VEN ≤18 V P_4.3.5 Enable internal pull-down resistor REN 2.8 10 20 M Ω – P_4.3.6

Datasheet 21 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics

4.3.1 Typical performance characteristics enable

Current consumption IEN versus input voltage VEN Output voltage VQ versus time t

Datasheet 22 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics

4.4 Reset

The reset function monitors the output voltage VQ. It allows a connected system or microcontroller to react to an imminent loss of power. To meet the requirements of the application, some reset related parameters can be adjusted by measures described below. Output undervoltage reset event If VQ drops below the output undervoltage reset lower switching threshold VRT,low, then the device detects an output undervoltage event and sets the reset output pi n RO to “low”. This signal can be used to reset a microcontroller, which is supplied by VQ. Reset reaction time If the output voltage of the regulator drops below th e output undervoltage reset lower switching threshold VRT,low, then the delay capacitor CD discharges with th e discharge current IDR,dsch. As soon as the delay capacitor’s voltage VD reaches the lower delay switching threshold VDR,lo, then the device sets the reset output RO to “low”. The time from VQ dropping below VRT,low and the transition of the reset output RO to “low” is the total reset reaction time trr,total. The total reset reaction time trr,total is related to the delay capacitor discharge time trr,d and the internal reaction time trr,int: trr,total = trr,int + trr,d (4.1) with

• trr,total: Total reset reaction time
• trr,int: Internal reset reaction time, see Internal reset reaction time
• trr,d: Delay capacitor discharge time. For CD = 10 nF see value specified in Delay capacitor discharge time. If the output voltage drop lasts shorter than the reset blanking time trr,blank, then the delay capacitor does not discharge and the device does not set the reset outp ut RO to “low”. The rese t blanking time prevents unintentional microcontroller rese t due to very short distortion of the output voltage, see Timing diagram reset.

Datasheet 23 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics Power-on reset delay time Before startup of the regulator or after an undervoltage reset event, the delay capacitor CD discharges. If the output voltage of the regulator exceeds the output undervoltage reset upper switching threshold VRT,hi, then this triggers the charging cycle of CD. CD is charged with the delay capacitor charge current ID,ch. If VD reaches the higher delay switching threshold VDR,hi, then the device sets the reset ou tput RO to “high”. The time from VQ exceeding VRT,hi until the device sets the reset output RO to “high” is the power-on reset delay time td,PWR-ON. The power-on reset delay time allows a microcontroller to start up properly before the reset output RO is released to “high”. The power-on reset delay time td,PWR-ON can be configured with the capacitance of the delay capacitor CD connected to pin D. If a power-on reset delay time td,PWR-ON different from the value for CD =1 0n F i s r e q u i r e d , t h e n t h e n e c e s s a r y delay capacitor’s value can be derived from the specified value given in Reset delay timing by: CD =1 0n F× td,PWR-ON / td,PWR-ON,10nF (4.2) with

• td,PWR-ON: Desired power-on reset delay time
• td,PWR-ON,10nF: Power-on reset delay time, see Power-on reset delay time
• CD: Delay capacitor required The formula is valid for CD ≥1 nF. For precise timing calculations also consider the delay capacitor’s tolerance. Reset output RO The reset output RO is an open collector output with an integrated pull-up resistor. If a lower-ohmic RO signal is desired, then connect an external pull-up resistor to the output Q. Since the maximum RO sink current is limited, the minimum optional external resistor RRO,ext is specified in Reset output, external pull-up resistor to Q. Reset output RO “low” for VQ ≥1V If an undervoltage reset condition occurs, then the device keeps the reset output RO “low” for VQ ≥1 V, even if the input voltage VI is 0 V. This is achieved by supplying the reset circuit from the output capacitor. Primary and secondary voltage reference There are two voltage references implemen ted in the reset circuit to provide the VRADJ,th signal. The input of the device supplies the primary voltage reference, wh ile the output of the devi ce supplies the secondary voltage reference. If EN is “low”, then the device disables the primary bandgap along with the power stage. As a consequence, the primary bandgap voltage drops below the secondary bandgap voltage reference, whereas the secondary bandgap then defines V RADJ,th. This ensures that the device pe rforms a controlled reset of the output on being disabled. Due to internal filtering and buffering, switching from the primary voltage reference to the secondary voltage reference occurs with some delay. The EN slope and the speed of the output voltage ramp down determine this delay.

Datasheet 24 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics Figure 6 Timing diagram reset VI t VQ t VRT,l ow VRT,high VRO t VRO,low 1 V trr,total Thermal Shutdown Input Voltage Dip trr,total t < trr,blank Under- voltage Spike at output Over- load VD t trr,total td,power-on trr,total VDR,low VDW,high VDR,high VDW,hold td,power-on td,power-on td,power-on td,power-on td,power-on trr,total trr,total td,power-on td,power-on

Datasheet 25 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics Reset adjust function An external voltage divider ( RADJ1, RADJ2) connected to RADJ can adjust the undervoltage reset switching threshold to the application’s needs. To select the default threshold, connect the RADJ pin to GND. For reset adjustment range, see Reset adjustment range. For dimensioning the voltage divider, consider the additional current flowing through the resistors. With a voltage divider connected to RADJ, the output undervoltage reset lower switching threshold VRT,low,new is calculated as follows (neglecting the reset adjust pin current IRADJ): VRT,low,new = VRADJ,th ×( RADJ,1 + RADJ,2)/ RADJ,2 (4.3) with

• VRT,low,new: Desired reset switching threshold
• RADJ,1, RADJ,2: Resistors of the external voltage divider, see Figure 7
• VRADJ,th: Reset adjust switching threshold, see Reset adjust switching threshold Figure 7 Functional block diagram reset

4.4.1 Electrical characteristics reset

Table 7 Electrical characteristics reset VI = 13.5 V, Tj = -40°C to 150°C; all voltages with respect to ground; direction of currents see Figure 7 (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Output undervoltage reset comparator default values (Pin RADJ = GND) Output undervoltage reset lower switching threshold VRT,low 2.97 3.03 3.10 V VEN ≥ 2.0 V; VQ decreasing; RADJ connected to GND; V RT,low ≤VI ≤42 V P_4.4.5 GND Q I RO RADJ Control D VRA DJ,th Int. Supply VDS T,high Secondary Reference ID,charge IRD,disch arg e QR S RRO VDS T,low CD RADJ,1 RADJ,2 CQ optional optional Microcontroller VDD Reset GND IRO IRA DJ Supply Primary Reference EN OR

Datasheet 26 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics Output undervoltage reset upper switching threshold VRT,high 3.03 3.10 3.17 V VEN ≥ 2.0 V; VQ increasing; RADJ connected to GND; VRT,high ≤VI ≤42 V P_4.4.7 Output undervoltage reset switching hysteresis VRT,hy 20 66 132 mV VI within operating range; RADJ connected to GND V EN ≥ 2.0 V P_4.4.11 Reset threshold adjustment Reset adjust switching threshold Reset adjustment range VRT,range 2.5 – 2.9 V 1) P_4.4.15 Reset output RO Reset output “low” voltage VRO,low –0 . 2 0 . 4 V 1 V ≤VQ ≤ VRT; RRO,ext ≥6.2 kΩ P_4.4.16 Reset output, external pull-up resistor to Q RRO,ext 6.2 – – k Ω 1V ≤VQ ≤VRT; VRO ≤0.4 V P_4.4.17 Reset output, internal pull-up resistor RRO,int 10 20 35 k Ω Internally connected to Q P_4.4.18 Reset delay timing Upper delay switching threshold VDR,high –0 . 9 – V – P_4.4.19 Lower delay switching threshold VDR,low –0 . 6 – V – P_4.4.20 Delay capacitor charge current ID,ch –1 . 6 – µ A VD = 1.2 V P_4.4.21 Delay capacitor reset discharge current IDR,dsch – 180 – mA VD = 1.2 V P_4.4.22 Power-on reset delay time td,PWR- ON,10nF 36 9 m s 2) Calculated value; CD = 10 nF; CD discharged to 0 V P_4.4.23 Internal reset reaction time trr,int 38 4 0 µ s CD = 0 nF, VQ = 2.64 V; VWINH,high ≤ VWINH P_4.4.25 Delay capacitor discharge time trr,d,10nF –0 . 2 0 . 3 µ s 2) CD = 10 nF P_4.4.26 Table 7 Electrical characteristics reset (cont’d) VI = 13.5 V, Tj = -40°C to 150°C; all voltages with respect to ground; direction of currents see Figure 7 (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 27 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics Total reset reaction time trr,total,10nF – 10 41 µs Calculated value: trr,d,10nF + trr,int; CD = 10 nF P_4.4.27 Reset blanking time trr,blank –3 – µ s 3) P_4.4.28 1) If the reset switching threshold is modified, then the related parameters VRT,hi, VRT,hy are changed directly proportional. 2) For programming a different dela y and reset reaction time, see Reset. 3) Not subject to production test, specified by design. Table 7 Electrical characteristics reset (cont’d) VI = 13.5 V, Tj = -40°C to 150°C; all voltages with respect to ground; direction of currents see Figure 7 (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 28 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics

4.4.2 Typical performance characteristics reset

Undervoltage reset lower switching threshold VRT,lo versus junction temperature Tj Power-on reset delay time td,PWR-ON versus delay capacitor CD Power-on reset delay time td,PWR-ON versus junction temperature Tj Internal reset reaction time trr,int versus junction temperature Tj

Datasheet 29 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics Total reset reaction time trr,total versus junction temperature Tj

Datasheet 30 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics

4.5 Watchdog

The device offers a watchdog with inhibit featur e and programmable watchdog timing. The watchdog function monitors a microcontroller to detect time base d failures. If the device detects a missing rising edge at the WI pin, then it sets the watchdog output to “low” after a defined time. An external delay capacitor CD is used to configure the timing. For details on how th e WI signal can comply with watchdog timing, see Timing diagram watchdog. The watchdog output WO is separated from the reset output RO. Therefore, the watchdog output can be used as an interrupt signal for the microcontroller independently from the reset signal. It is possible to interconnect WO pin and RO pin in order to establish a wired OR function with a dominant “low” signal. Figure 8 Functional block diagram watchdog Watchdog inhibit input WINH The watchdog inhibit input WINH enables or disables the watchdog function. A “high” signal at WINH disables the watchdog. When disabled, the capacitor at the D pin is charged to the watchdog deactivation hold voltage VDW,hold. The signal applied to WINH must comply with the values in Watchdog inhibit WINH. Watchdog output WO The watchdog output WO is an open collector output with an integrated pull-up resistor. If a lower-ohmic WO signal is desired, then connect an external pull-up resistor to the output Q. Since the maximum WO sink current is limited, the minimum external resistor value RWO,ext is specified in Watchdog output external pull- up resistor. GND QI WO WI Control D Int. Supply VDW,high ID,charge IWD,disch arg e Q R S RWO CD CQ optional Microcontroller VDD Reset GND IWO Supply I/O Rising Edge detect WINH Q R S Q OR VDW,low AND RWI RWINH

Datasheet 31 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics Watchdog input WI A positive edge at the watchdog input WI triggers the watchdog. Because of the integrated high pass filter, the amplitude and slope of the signal at WI pin must comply with the values in Watchdog input WI. For details on the test pulse applied, see Figure 9. Figure 9 Test pulses watchdog input WI Watchdog timing If the watchdog is enabled and the device does not de tect a rising edge at the WI pin, then the delay capacitor CD is continuously charged and discharged between VDW,low and VDW,high, see Functional block diagram watchdog. The WO pin goes “low” for tWD,lo when the delay capacitor voltageVD discharges to VDW,low. Due to the cyclic nature of this behavior, this pattern repeats with the watchdog period tWD,p. If the device detects a rising edge at the WI pin during the CD discharge cycle, then a new charge cycle starts. To prevent the device from setting WO to “low”, a risi ng edge on the WI pin must occur within the watchdog trigger time tWI,tr. For timing details see Timing diagram watchdog. If a watchdog trigger time tWI,tr different from the one for CD = 10 nF is required, then the delay capacitor’s value can be derived from the value in Watchdog timing by: CD =1 0n F× tWI,tr / tWI,tr,10nF (4.4) The watchdog output “low” time tWD,lo and the watchdog period tWD,p equate to: tWD,lo = tWD,lo,10nF × CD /1 0n F (4.5) tWD,p = tWI,tr + tWD,lo (4.6) The formula applies for CD ≥1 nF. For precise timing calculations consider the delay capacitor’s tolerance. VWI t VWI,low VWI,high tWI,ph dVWI / dt tWI,pl

Datasheet 32 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics Figure 10 Timing diagram watchdog VWI t VWI,low VWI,high VWO t VWO,low tWD,low tWI,tr VDW,low VDW,high t VD tWD,low tWD,p tWI,p1/fWINo positive VWI edge dVWI / dt outside spec VWINH,high t VDW,hold tWINH,ph VWINH,low

Datasheet 33 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics

4.5.1 Electrical characteristics watchdog

Table 8 Electrical char acteristics watchdog VI = 13.5 V, Tj = -40°C to 150°C; all voltages with respect to ground, direction of currents see Figure 8 (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Watchdog inhibit WINH Watchdog inhibit “low” signal valid VWINH,low ––0 . 8 V – P_4.5.1 Watchdog inhibit “high” signal valid VWINH,high 2––V – P_4.5.2 Watchdog inhibit “high” level input current IWINH,high ––3 . 5 µ A VWINH = 3.3 V P_4.5.3 Watchdog inhibit “high” signal pulse length tWINH,ph –2 . 5 –m s CD = 10 nF; VWINH ≥VWINH.high P_4.5.5 Watchdog inhibit internal pull- down resistor Watchdog input WI Watchdog input “low” signal valid VWI,low ––0 . 8 V 1) P_4.5.7 Watchdog input “high” signal valid VWI,high 2––V 1) P_4.5.8 Watchdog input “low” signal pulse length tWI,pl 1––µ s 1) VWI ≤VWI,low P_4.5.9 Watchdog input “high” signal pulse length tWI,ph 1––µ s 1) VWI ≥VWI,high P_4.5.10 Watchdog input “high” level input current IWI,H ––3 . 5 µ A VWI =3 . 3V P_4.5.11 Watchdog input signal slew rate ∆VWI/∆t 1––V / µ s 1) VWI,low ≤VWI ≤VWI,high P_4.5.12 Watchdog input internal pull- down resistor Watchdog output WO Watchdog output “low” voltage VWO,low –0 . 2 0 . 4 V VQ ≥2.5 V; RWO ≥ 6.2 kΩ P_4.5.14 Watchdog output external pull- up resistor RWO,ext 6 . 2 ––k Ω VQ ≥2.5 V; VWO ≤0.4 V P_4.5.15 Watchdog output internal pull- up resistor RWO,int 10 20 35 k Ω – P_4.5.16 Watchdog timing Delay capacitor charge current ID –1 . 6 –µ A VD = 1.2 V P_4.5.17

Datasheet 34 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics Delay capacitor deactivation charge current IDW,ch,deact –1 . 6 –µ A VD = 1.2 V P_4.5.18 Delay capacitor watchdog discharge current IDW,disch –0 . 5 –µ A VD = 1.2 V P_4.5.19 Upper watchdog timing threshold VDW,high –1 . 4 5 –V – P_4.5.20 Lower watchdog timing threshold VDW,low –0 . 9 –V – P_4.5.21 Upper delay watchdog deactivated hold voltage VDW,deact –1 . 5 –V VWINH ≥VWINH.high P_4.5.22 Watchdog trigger time tWI,tr,10nF 3 . 5 1 32 1m s 2) Calculated value; CD = 10 nF P_4.5.23 Watchdog output “low” time tWD,lo,10nF 1 . 5 46m s 2) Calculated value; CD = 10 nF P_4.5.24 Watchdog period tWD,p,10nF 5 1 72 7m s 2) Calculated value; tWI,tr,10nF + tWD,lo,10nF; CD = 10 nF P_4.5.25 1) For details on the test pulse applied, see Figure 9. 2) For programming the watchdog timing, see Watchdog. Table 8 Electrical char acteristics watchdog (cont’d) VI = 13.5 V, Tj = -40°C to 150°C; all voltages with respect to ground, direction of currents see Figure 8 (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 35 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics

4.5.2 Typical performance characteristics watchdog

Watchdog trigger time tWI,tr versus delay capacitor CD Watchdog trigger time tWI,tr versus junction temperature Tj Watchdog inhibit high signal pulse length tWINH,ph versus junction temperature Tj Watchdog output “low” time tWD,lo versus junction temperature Tj

Datasheet 36 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset Block description and electrical characteristics Watchdog output “low” time tWD,lo versus delay capacitor CD

Datasheet 37 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset

Application information

5 Application information

Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device.

5.1 Application diagram

Figure 11 Application diagram

5.2 Selection of external components

5.2.1 Input pin

Figure 11 shows the typical input circuitry for a linear volt age regulator. A ceramic capacitor at the input, in the range of 100 nF to 470 nF, is recommended to filter out high frequency disturbances imposed by the line, such as ISO pulses 3a/b. The capacitor must be placed very close to the input pin of the linear voltage regulator on the PCB. An aluminum electrolytic capacitor in the range of 10 µF to 470 µF is recommended as an input buffer to smooth out high energy pulses, such as ISO pulse 2a. This capacitor should be placed close to the input pin of the linear voltage regulator on the PCB. An overvoltage suppressor diode can be used to further suppress any voltage exceeding the maximum rating of the linear voltage regulator and protect the device against damage due to overvoltage. The external components at the input are not mandator y for the operation of the voltage regulator, but they are recommended in case of possible external disturbances.

5.2.2 Output pin

An output capacitor is mandatory for the stability of a linear voltage regulator. The requirement to the output capacitor is given in Functional range. The device is designed to be stable with extremely low ESR capacitors. According to automotive requirements, ceramic capacitors with X5R or X7R dielectrics are recommended. The output capacitor should be placed as close as poss ible to the regulator’s output and to GND pins and on the same side of the PCB as the regulator itself. Primary Reference GND QI Temperature Shutdown EN Enable RO RADJ WINH WO Current Limitation WI D Reset & Watchdog Generator CQ=1 µF Microcontroller GND CD CI1 10 0nF CI2 10 µF DI2 <42V Regulated output voltageSu pp ly DI1 e.g. Ignition

Datasheet 38 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset I n c a s e o f r a p i d t r a n s i e n t s o f i nput voltage or load curr ent, the capacitance sh ould be dimensioned in accordance and verified in the real application to fulfill the output stability requirements.

5.3 Thermal considerations

Knowing the input voltage, the output voltage and th e load profile of the application, the total power dissipation can be calculated: PD =( VI - VQ)× IQ + VI × Iq (5.1) with

• PD: continuous power dissipation
• VI: input voltage
• VQ: output voltage
• IQ: output current
• Iq: quiescent current The maximum acceptable thermal resistance RthJA can then be calculated: RthJA,max =( Tj,max - Ta)/ PD (5.2) with
• Tj,max: maximum allowed junction temperature
• Ta: ambient temperature Based on the above calculation the proper PCB type and the necessary heat sink area can be determined with reference to the specification in Thermal resistance. Example Application conditions: VI = 13.5 V VQ = 3.3 V IQ = 50 mA Ta = 85°C Calculation of RthJA,max: PD =( VI - VQ)× IQ + VI × Iq =( 1 3 . 5V-3 . 3V )×5 0m A+1 3 . 5V×3 3µ A = 0.510 W + 0.000446 W = 0.510446 W RthJA,max =( Tj,max - Ta)/ PD As a result, the PCB design must ensure a thermal resistance RthJA lower than 127.33 K/W. According to Thermal resistance, at least 300 mm2 heatsink area is needed on the FR4 1s0p PCB, or the FR4 2s2p board can be used.

5.4 Reverse polarity protection

The device must be protected from reverse polarity by external components. An external reverse polarity diode is required. The Absolute maximum ratings of the device must be maintained.

Datasheet 39 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset

5.5 Further application information

• Please contact Infineon for information on pin behavior assessment
• Existing application note
• For further information you may contact https://www.infineon.com

Datasheet 40 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset

Package information

6 Package information

Figure 12 PG-SSOP-14 1) Green Product (RoHS compliant) To meet the world-wide customer requirements for en vironmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e. Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Further information on packages https://www.infineon.com/packages 1) Dimensions in mm 14 8 1 7 814 The drawing is in compliance with ISO 128-30, Projection Method 1 [ ] All dimensions are in units mm 4.9±0.1 0.25±0.05 0.65 6 x 0.65 = 3.9 2.65±0.2 3±0.2 6±0.2 Index Marking 0.05±0.05 Stand off 1) 3.9±0.1 0.19 +0.06 0.00 0.64±0.25 (1.45) 1.7Max. 8° Max. 0.35 x 0.45° 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Lead width can be 0.61 max. in dambar area Bottom View

Datasheet 41 Rev. 1.1 2023-10-16 OPTIREG™ linear TLS820F3ELV33 Low dropout linear voltage regulator with watchdog and reset

Revision history

7 Revision history

1.1 2023-10-16 Editorial changes an d update to latest template 1.0 2022-02-22 Datasheet created

All referenced product or service names and trademarks are the property of their respective owners. Edition 2023-10-16 Published by Infineon Technologies AG

81726 Munich, Germany

© 2023 Infineon Technologies AG. All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com Document reference Z8F69559393 IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer's comp liance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer's products and any use of the product of Infineon Technologies in customer's applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer's technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.