TLS810C1EJV33_15 INFINEON | Alldatasheet
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Technical content
Rev. 1.0, 2015-02-11 TLS810C1EJV33 Ultra Low Quiescent Current Linear Voltage Regulator
TLS810C1EJV33 PG-DSO-8 EP 810C1V33 Data Sheet 2 Rev. 1.0, 2015-02-11 Ultra Low Quiescent Current Linear Voltage Regulator TLS810C1 TLS810C1EJV33 1O v e r v i e w
Features
- Ultra Low Quiescent Current of 8.5 µA
- Wide Input Voltage Range of 2.75 V to 42 V
- Output Current Capacity up to 100 mA
- Low Drop Out Voltage of typ. 250 mV @ 100 mA
- Reset
- Output Current Limit Protection
- Overtemperature Shutdown
- Available in PG-DSO-8 EP package
- Wide Temperature Range
- Green Product (RoHS compliant)
- AEC Qualified
Description
The TLS810C1 is a linear voltage regulator featuring wide input voltage range, low drop out voltage and ultra low quiescent current. With an input voltage range of 2.75 V to 42 V and ultra lo w quiescent of only 8.5 µA, the regulators are perfectly suitable for automotive or any other supply systems connected permanently to the battery. The TLS810C1EJV33 is the fixed 3.3 V output version with an accuracy of 2 % and output current capability up to 100 mA. The new regulation concept implemente d in TLS810C1 combines fast regulation and very good stability while requiring only a small ceramic capacitor of 1 μF at the output. The tracking region starts already at input voltages of 2.75 V (extended operating range). This makes the TLS810C1 also suitable to supply automotive systems that need to operate during cranking condition. Internal protection features like output current limitation and overtemperature shutdown are implemented to protect the device against immediate damage due to failu res like output short circuit to GND, over-current and over-temperature. The output voltage is supervised by the Reset feature, including undervoltage reset and delayed reset release at power-on.
Data Sheet 3 Rev. 1.0, 2015-02-11 Choosing External Components An input capacitor CI is recommended to compensate line influences. The output capacitor CQ is necessary for the stability of the regulating circui t. Stability is guara nteed at values CQ ≥ 1 µF and an ESR ≤ 100 Ω within the whole operating range.
Data Sheet 4 Rev. 1.0, 2015-02-11
2 Block Diagram
Figure 1 Block Diagram TLS810C1 Bandgap Reference GND QI Temperature Shutdown Reset RO D Current Limitation
Data Sheet 5 Rev. 1.0, 2015-02-11
3 Pin Configuration
3.1 Pin Assignment in PG-DSO-8 EP Package
Figure 2 Pin Configuration TLS810C1 in PG-DSO-8 EP package
3.2 Pin Definitions and Functi ons in PG-DSO-8 EP Package
It is recommended to place a small ceramic capacitor (e.g. 100 nF) to GND, close to the IC terminals, in order to compensate line influences. 2N . C . Not connected 3N . C . Not connected 4G N D Ground 5D Reset Delay Timing Connect a ceramic capacitor to GND for adjusting the reset delay time. Leave open if the reset function is not needed. 6R O Reset Output Integrated pull-up resistor. Open collector output. Leave open if the reset function is not needed. 7N . C . Not connected Q N.C. RO I N.C. N.C. GND D
Data Sheet 6 Rev. 1.0, 2015-02-11 8Q Output Connect an output capacitor CQ to GND close to the IC’s terminals, respecting the values specified for its capacitance and ESR in Table 2 “Functional Range” on Page 8. Pad – Exposed Pad Connect to heatsink area. Connect to GND. Pin Symbol Function
General Product Characteristics Data Sheet 7 Rev. 1.0, 2015-02-11
4 General Product Characteristics
4.1 Absolute Maximum Ratings
- Stresses above the ones listed here may cause perma nent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection func tions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Table 1 Absolute Maximum Ratings 1) Tj = -40 °C to +150 °C; all voltages with respect to ground (unless otherwise specified) 1) Not subject to production te sting, specified by design. Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Voltage Input Voltage VI -0.3 – 45 V – P_4.1.1 Voltage Output Q Voltage VQ -0.3 – 7 V – P_4.1.2 Reset Output RO, Reset Delay D Voltage VRO, VD -0.3 – 7 V – P_4.1.3 Temperatures Junction Temperature Tj -40 – 150 °C – P_4.1.4 Storage Temperature Tstg -55 – 150 °C – P_4.1.5 ESD Absorption ESD Absorption VESD,HBM - 2 –2k V H B M 2) 2) ESD HBM Test according to AEC-Q100-002 - JESD22-A114 (1.5kOhm, 100pF) P_4.1.6 ESD Absorption VESD,CDM -750 – 750 V CDM 3) at all pins 3) ESD CDM Test according to ESDA STM5.3.1 P_4.1.7
General Product Characteristics Data Sheet 8 Rev. 1.0, 2015-02-11
4.2 Functional Range
Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the Electrical Characteristics table.
4.3 Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Table 2 Functional Range Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Input Voltage Range VI VQ,nom + Vdr –4 2 V – 1) 1) Output current is limited internally and depends on the in put voltage, see Electrical Characteristics for more details. P_4.2.1 Extended Input Voltage Range VI,ext 2.75 – 42 V – 2) 2) When VI is between VI,ext.min and VQ,nom + Vdr, VQ = VI - Vdr. When VI is below VI,ext,min, VQ can drop down to 0 V. P_4.2.2 Output Capacitor CQ 1 – – µF – 3) 3) The minimum output capacitance requ irement is applicable for a worst case capacitance tolerance of 30%. P_4.2.3 Output Capacitor’s ESR ESR( CQ)– – 1 0 0 Ω –4) 4) Relevant ESR value at f = 10 kHz. P_4.2.4 Junction temperature Tj -40 – 150 °C – P_4.2.5 Table 3 Thermal Resistance Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Package Version PG-DSO-8 EP Junction to Case1) 1) Not subject to production test, specified by design RthJC – 19 – K/W – P_4.3.1 Junction to Ambient1) RthJA – 51 – K/W 2s2p board 2) 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. P_4.3.2 Junction to Ambient1) RthJA – 167 – K/W 1s0p board, footprint only3) 3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product (Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu). P_4.3.3 Junction to Ambient1) RthJA – 71 – K/W 1s0p board, 300 mm 2 heatsink area on PCB3) P_4.3.4 Junction to Ambient1) RthJA – 60 – K/W 1s0p board, 600 mm 2 heatsink area on PCB3) P_4.3.5
Block Description and Electrical Characteristics Data Sheet 9 Rev. 1.0, 2015-02-11
5 Block Description and El ectrical Characteristics
5.1 Voltage Regulation
The output voltage VQ is divided by a resistor network. This fracti onal voltage is compared to an internal voltage reference and the pass transistor is driven accordingly. The control loop stability depen ds on the output capacitor CQ, the load current, the chip temperature and the internal circuit design. To ensure stable operation, the output capacitor’s capacitance and its equivalent series resistor ESR requirements given in “Functional Range” on Page 8 have to be maintained. For details see the typical performance graph Output Capacitor Series Resistor ESR(CQ) versus Output Current IQ. Since the output capacitor is used to buffer load steps, it should be sized according to the application’s needs. An input capacitor CI is not required for stability, but is re commended to compensate line fluctuations. An additional reverse polarity protection diode and a combination of several capacitors for filtering should be used, in case the input is connected directly to the battery line. Connect the capacitors close to the regulator terminals. In order to prevent overshoots during start-up, a smooth ramping up function is implemented. This ensures almost no overshoots during start-up, mostly independent from load and output capacitance. Whenever the load current exceeds the specified limit, e.g. in case of a short circuit, the output current is limited and the output voltage decreases. The overtemperature shutdown circuit prevents the IC from immediate destruction under fault conditions (e.g. output continuously short-circuit) by switching off the power stage. After the chip has cooled down, the regulator restarts. This oscillatory th ermal behaviour causes the junction temp erature to exceed the maximum rating of 150°C and can significantly reduce the IC’s lifetime. Figure 3 Block Diagram Voltage Regulation Bandgap Reference GND QI Temperature Shutdown Current Limitation Regulated Output VoltageIQ VQCQ Supply VI LOAD C ESR CI II
Block Description and Electrical Characteristics Data Sheet 10 Rev. 1.0, 2015-02-11 Table 4 Electrical Characteristics Tj = -40 °C to +150 °C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified). Typical values are given at Tj = 25 °C, VI = 13.5 V. Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Output Voltage Precision VQ 3.23 3.30 3.37 V 50 µA ≤ IQ ≤ 100 mA, 4V ≤ VI ≤ 28 V P_5.1.2 Output Voltage Precision VQ 3.23 3.30 3.37 V 50 µA ≤ IQ ≤ 50 mA, 4V ≤ VI ≤ 42 V P_5.1.3 Output Current Limitation IQ,lim 110 190 260 mA 0 V ≤ VQ ≤ VQ,nom - 0.1 V P_5.1.4 Line Regulation steady-state ΔVQ,line –12 0 m V IQ = 1m A , 6V ≤ VI ≤ 32 V P_5.1.6 Load Regulation steady-state ΔVQ,load -20 -1 – mV VI = 6 V, 50 µA ≤ IQ ≤ 100 mA P_5.1.7 Dropout Voltage1) Vdr = VI - VQ 1) measured when the output voltage VQ has dropped 100 mV from the nominal value obtained at VI = 13.5V Vdr – 250 650 mV IQ = 100 mA P_5.1.11 Ripple Rejection2) 2) not subject to production test, specified by design PSRR –6 0 – d B IQ =5 0m A , fripple = 100 Hz, Vripple = 0.5 Vp-p P_5.1.12 Overtemperature Shutdown Threshold Tj,sd 151 175 – °C Tj increasing P_5.1.13 Overtemperature Shutdown Threshold Hysteresis Tj,sdh –1 0 – K Tj decreasing P_5.1.14
Block Description and Electrical Characteristics Data Sheet 11 Rev. 1.0, 2015-02-11
5.2 Typical Performance Characteristics Voltage Regulation
Typical Performance Characteristics Output Voltage VQ versus Junction Temperature Tj Output Current IQ versus Input Voltage VI Dropout Voltage Vdr versus Junction Temperature Tj Dropout Voltage Vdr versus Output Current IQ 0 50 100 150 3.1 3.15 3.2 3.25 3.3 3.35 3.4 3.45 3.5 Tj [°C] VQ [V] VI = 13.5 V IQ = 50 mA 0 10 20 30 40 100 150 200 250 300 VI [V] IQmax [mA] Tj = −40 °C Tj = 25 °C Tj = 150 °C 0 50 100 150 100 150 200 250 300 350 400 Tj [°C] Vdr [mV] IQ = 10 mA IQ = 50 mA IQ = 100 mA 0 20 40 60 80 100 100 150 200 250 300 350 400 IQ [mA] Vdr [mV] Tj = −40 °C Tj = 25 °C Tj = 150 °C
Block Description and Electrical Characteristics Data Sheet 12 Rev. 1.0, 2015-02-11 Load Regulation ∆VQ,load versus Output Current IQ Load Regulation ∆VQ,line versus Input Voltage VI Output Voltage VQ versus Input Voltage VI Power Supply Ripple Rejection PSRR versus Ripple Frequency fr 0 20 40 60 80 100 −10 IQ [mA] dVload [mV] VI = 6 V Tj = −40 °C Tj = 25 °C Tj = 150 °C 10 15 20 25 30 35 40 −10 VI [V] dVline [mV] IQ = 1 mA Tj = −40 °C Tj = 25 °C Tj = 150 °C 0 1 2 3 4 5 0.5 1.5 2.5 3.5 VI [V] VQ [V] IQ = 50 mA Tj = 25 °C f [kHz] PSRR [dB] IQ = 10 mA CQ = 1 μF VI = 13.5 V Vripple = 0.5 Vpp Tj = 25 °C
Block Description and Electrical Characteristics Data Sheet 13 Rev. 1.0, 2015-02-11 Output Capacitor Series Resistor ESR(CQ) versus Output Current IQ 0 20 40 60 80 100 IQ [mA] ESR(CQ) [Ω] CQ = 1 μF VI = 3...28 V Stable Region Unstable Region
Block Description and Electrical Characteristics Data Sheet 14 Rev. 1.0, 2015-02-11
5.3 Current Consumption
Table 5 Electrical Characteristics Current Consumption Tj = -40 °C to +150 °C, VI = 13.5 V (unless otherwise specified). Typical values are given at Tj = 25 °C, VI = 13.5 V. Parameter Symbol Values Unit No te / Test Condition Number Min. Typ. Max. Current Consumption Iq = II - IQ Iq – 8.5 10.5 µA IQ = 50 µA, Tj = 25 °C P_5.3.1 Current Consumption Iq = II - IQ Iq –1 1 1 4 µ A IQ = 50 µA, Tj < 105 °C P_5.3.2 Current Consumption Iq = II - IQ Iq –1 1 . 5 1 5 µ A IQ = 50 µA, Tj < 125 °C P_5.3.3 Current Consumption Iq = II - IQ Iq –1 1 . 5 1 5 µ A IQ= 100 mA, Tj < 125 °C P_5.3.4
Block Description and Electrical Characteristics Data Sheet 15 Rev. 1.0, 2015-02-11
5.4 Typical Performance Charac teristics Current Consumption
Typical Performance Characteristics Current Consumption Iq versus Output Current IQ Current Consumption Iq versus Input Voltage VI Current Consumption Iq versus Junction Temperature Tj 0 20 40 60 80 100 IQ [mA] Iq [μA] VI = 13.5 V Tj = −40 °C Tj = 25 °C Tj = 105 °C Tj = 125 °C 10 15 20 25 30 35 40 VI [V] Iq [μA] IQ = 50 μA Tj = −40 °C Tj = 25 °C Tj = 105 °C Tj = 125 °C 0 50 100 150 Tj [°C] Iq [μA] VI = 13.5 V IQ = 50 μA
Block Description and Electrical Characteristics Data Sheet 16 Rev. 1.0, 2015-02-11
5.5 Reset Function
The reset function provides several features: Output Undervoltage Reset An output undervoltage condition is indicated by setting the Reset Output RO to “low”. This signal might be used to reset a microcontroller during low supply voltage. Power-On Reset Delay Time The power-on reset delay time trd allows a microcontoller and oscillator to start up. This delay time is the time frame from exceeding the reset switching thresholdVRT until the reset is released by switching the reset output “RO” from “low” to “high”. The power-on reset delay time trd is defined by an external delay capacitor CD connected to pin D charged by the delay capacitor charge current ID,ch starting from VD =0V . If the application needs a power-on reset delay time trd different from the value given in Table 6, the delay capacitor’s value can be derived from the specified value and the desired power-on delay time: (5.1) with
- CD: capacitance of the delay capacitor to be chosen
- trd,new: desired power-on reset delay time
- trd: power-on reset delay time specified in this datasheet For a precise calculation also take the delay capacitor’s tolerance into consideration. Reset Reaction Time The reset reaction time avoids that short undervoltage spikes trigger an unwanted reset “low” signal. The reset reaction rime trr considers the internal reaction time trr,int and the discharge time trr,d defined by the external delay capacitor CD (see typical performance graph for details). Hence, the total reset reaction time becomes: (5.2) with
- trr: reset reaction time
- trr,int: internal reset reaction time
- trr,d: reset discharge Optional Reset Output Pull-Up Resistor RRO,ext The Reset Output RO is an open collector output with an integrated pull-up resistor. If needed, an external pull-up resistor to the output Q can be added. In Table 6 a minimum value for the external resistor RRO,ext is given. CD = trd,new 100 nFtrd x trr = +trr,int trr,d
Block Description and Electrical Characteristics Data Sheet 17 Rev. 1.0, 2015-02-11 Figure 4 Block Diagram Reset Function GND QISupply RO VDST Int. Supply ID, ch ID, d ch VRADJ ,th Control D CD Reset optional CQ VDD Micro- Controller GND RRO IRO RRO ,ext
Block Description and Electrical Characteristics Data Sheet 18 Rev. 1.0, 2015-02-11 Figure 5 Timing Diagram Reset Table 6 Electrical Characteristics Reset Tj = -40 °C to +150 °C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified). Typical values are given at Tj = 25 °C, VI = 13.5 V. Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Output Undervoltage Reset Output Undervoltage Reset Upper Switching Threshold Output Undervoltage Reset Lower Switching Threshold Reset Output RO Reset Output Low Voltage VRO,low 00 . 2 0 . 4 V 1 V ≤ VQ ≤ VRT; RRO >4 . 7kΩ P_5.5.4 VI t VQ t VRT,high VRO TimingD iagram_R eset.vsd t VRO,low 1 V trr,totaltrd Thermal Shutdown Input Voltage Dip trr,totaltrd trd t < trr,total trd Under- voltage Spike at output Over- load trr, total VDRL VDU t VD VRT,low
Block Description and Electrical Characteristics Data Sheet 19 Rev. 1.0, 2015-02-11 Reset Output Internal Pull-Up Resistor RRO,int 13 20 36 k Ω internally connected to Q P_5.5.5 Reset Output External Pull-up Resistor to VQ RRO,ext 4.7 – – k Ω 1V ≤ VQ ≤ VRT; VRO ≤ 0.4 V P_5.5.6 Reset Delay Timing Power On Reset Delay Time trd 17 25 37 ms CD = 100 nF Calculated value P_5.5.8 Upper Delay Switching Threshold VDU – 0.9 – V – P_5.5.9 Lower Delay Switching Threshold VDL – 0.6 – V – P_5.5.10 Delay Capacitor Charge Current ID,ch –3 . 6 –µ A VD = 1 V P_5.5.11 Delay Capacitor Discharge Current ID,dch – 250 – mA VD = 1 V P_5.5.12 Delay Capacitor Discharge Time trr,d –24µ s CD = 100 nF Calculated value P_5.5.13 Internal Reset Reaction Time1) trr,int –81 4 µ s CD = 0 nF P_5.5.14 Reset Reaction Time trr,total –1 0 1 8 µ s CD = 100 nF Calculated value P_5.5.15 1) Parameter not subject to produ ction test; specified by design. Table 6 Electrical Characteristics Reset Tj = -40 °C to +150 °C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified). Typical values are given at Tj = 25 °C, VI = 13.5 V. Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.
Block Description and Electrical Characteristics Data Sheet 20 Rev. 1.0, 2015-02-11
5.6 Typical Performance Characteristics Reset
Typical Performance Characteristics Undervoltage Reset Threshold VRT versus Junction Temperature Tj Power On Reset Delay Time trd versus Junction Temperature Tj Internal Reset Reaction Time trr,int versus Junction Temperature Tj 0 50 100 150 2.9 2.95 3.05 3.1 3.15 3.2 3.25 3.3 Tj [°C] VRT [V] VRT high VRT low 0 50 100 150 Tj [°C] trd [ms] CD = 100 nF 0 50 100 150 Tj [°C] trr,int [μs]
Application Information
Data Sheet 21 Rev. 1.0, 2015-02-11
6 Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device.
6.1 Application Diagram
Figure 6 Application Diagram TLS810C1
6.2 Selection of External Components
6.2.1 Input Pin
The typical input circuitry for a linear voltage regulator is shown in the application diagram above. A ceramic capacitor at the input, in the range of 100 nF to 470 nF, is recommended to filter out the high frequency disturbances imposed by the line e.g. ISO pulses 3a/b. This capacitor must be placed very close to the input pin of the linear voltage regulator on the PCB. An aluminum electrolytic capacitor in the range of 10 µF to 470 µF is recommended as an input buffer to smooth out high energy pulses, such as ISO pulse 2a. This capacitor should be placed close to the input pin of the linear voltage regulator on the PCB. An overvoltage suppressor diode can be used to furthe r suppress any high voltag e beyond the maximum rating of the linear voltage regulator and protect the device against any damage due to over-voltage. The external components at the input are not mandatory for the operation of the voltage regulator, but they are recommended in case of possible external disturbances.
6.2.2 Output Pin
An output capacitor is mandatory for the stability of linear voltage regulators. TLS810C1 QI RO D Regulated Output VoltageIQ CQ 1μF CD 100nF Supply 100nF10μF CI1CI2 <45V DI2 II GND Load (e.g. Micro Controller) GND (optional) RRO DI1
Data Sheet 22 Rev. 1.0, 2015-02-11 The requirement to the output capacitor is given in “Functional Range” on Page 8 . The graph “Output Capacitor Series Resistor ESR(CQ) versus Output Current IQ” on Page 13 shows the stable operation range of the device. TLS810C1 is designed to be stable with extremely low ESR capacitors. According to the automotive environment, ceramic capacitors with X5R or X7R dielectrics are recommended. The output capacitor should be placed as close as possible to the regulat or’s output and GND pins and on the same side of the PCB as the regulator itself. In case of rapid transients of input voltage or load current, the capacitance should be dimensioned in accordance and verified in the real application that the output stability requirements are fulfilled.
6.3 Thermal Considerations
Knowing the input voltage, the output voltage and the load profile of the application, the total power dissipation can be calculated: (6.1) with
- PD: continuous power dissipation
- VI: input voltage
- VQ: output voltage
- IQ: output current
- Iq: quiescent current The maximum acceptable thermal resistance RthJA can then be calculated: (6.2) with
- Tj,max: maximum allowed junction temperature
- Ta: ambient temperature Based on the above calculation the proper PCB type and the necessary heat sink area can be determined with reference to the specification in “Thermal Resistance” on Page 8. Example Application conditions: VI = 13.5 V VQ = 3.3 V IQ = 80 mA Ta = 105 °C Calculation of RthJA,max: PD =( VI – VQ) x IQ + VI x Iq = (13.5 V – 3.3 V) x 80 mA + 13.5 V x 0.015 mA = 0.816 W PD VI VQ–() IQ VI Iq×+×= RthJA max, Tjm a x, Ta– PD
Data Sheet 23 Rev. 1.0, 2015-02-11 RthJA,max =( Tj,max – Ta) / PD = 55.15 K/W As a result, the PCB design must ensure a thermal resistance RthJA lower than 55.15 K/W. According to “Thermal Resistance” on Page 8, only the FR4 2s2p board can be used.
6.4 Reverse Polarity Protection
TLS810C1 is not self protected against reverse polarity faults. To protect the device against negative supply voltage, an external reverse polarity diode is needed, as shown in Figure 6. The absolute maximum ratings of the device as specified in “Absolute Maximum Ratings” on Page 7 must be kept.
6.5 Further Application Information
- For further information you may contact http://www.infineon.com/
Data Sheet 24 Rev. 1.0, 2015-02-11
7 Package Outlines
Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). 8 5 8x0.41±0.09 2) M0.2 DC A-B 1.27 C Stand Off -0.10.1 (1.45) 1.7 MAX. 0.08 Seating Plane C A B 3) JEDEC reference MS-012 variation BA 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Dambar protrusion shall be maximum 0.1 mm total in excess of lead width Bottom View ±0.23 ±0.22.65 0.2±0.2 D 6 M D 8x 0.64±0.25 3.9±0.11) 0.1 0.35 x 45° CD2 x +0.06 0.19 8° MAX. Index Marking For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Dimensions in mm
Revision History
Data Sheet 25 Rev. 1.0, 2015-02-11
8 Revision History
1.0 2015-02-11 Data Sheet - Initial Version
81726 Munich, Germany
© 2015 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.