TLS805B1LDV INFINEON | Alldatasheet

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Ultra Low Quiescent Current Linear Voltage Regulator TLS805B1 TLS805B1SJV TLS805B1LDV Linear Voltage Regulator Automotive Power Data Sheet Rev. 1.2, 2016-01-11

Data Sheet 2 Rev. 1.2, 2016-01-11

1 Overview

Features

  • Ultra Low Quiescent Current of 5 µA
  • Wide Input Voltage Range of 2.75 V to 42 V
  • Output Current Capacity up to 50 mA
  • Off Mode Current Less than 1 µA
  • Low Drop Out Voltage of typ. 100 mV @ 50 mA
  • Output Current Limit Protection
  • Overtemperature Shutdown
  • E n a b l e
  • Available in PG-DSO-8 Package
  • Available in PG-TSON-10 Package
  • Wide Temperature Range
  • Green Product (RoHS Compliant)
  • AEC Qualified Figure 1 PG-DSO-8 Figure 2 PG-TSON-10 Type Package Marking TLS805B1SJV PG-DSO-8 805B1V TLS805B1LDV PG-TSON-10 805B1V

Data Sheet 3 Rev. 1.2, 2016-01-11 TLS805B1SJ/LDV Overview

Description

The TLS805B1 is a linear voltage regulator featuring wide input voltage range, low drop out voltage and ultra low quiescent current. With an input voltage range of 2.75 V to 42 V and ultra low quiescent of only 5 µA, the regulator is perfectly suitable for automotive or any other supply systems connected permanently to the battery. The TLS805B1SJ/LDV is the adjustable output version with an accuracy of 2 % and output current capability up to 50 mA. The new regulation concept implemented in TLS805B1 combines fast regulation and very good stability while requiring only a small ceramic capacitor of 1 μF at the output. The tracking region starts already at input voltages of 2.75 V (extended operating range). This makes the TLS805B1 also suitable to supply automotive systems that need to operate during cranking condition. Internal protection features like output current li mitation and overtemperature shutdown are implemented to protect the device against immediate damage due to failures like output short circuit to GND, over-current and over-temperature. The device can be switched on and off by the Enable fe ature. When the device is switched off, the current consumption is typically less than 1 µA. Choosing External Components An input capacitor CI is recommended to compensate line influences. The output capacitor CQ is necessary for the stability of the regulating circuit. Stability is guaranteed at values CQ≥ 1µ F a n d a n E S R ≤ 100 Ω within the whole operating range.

Data Sheet 4 Rev. 1.2 2016-01-11 TLS805B1SJ/LDV Block Diagram

2 Block Diagram

Figure 3 Block Diagram TLS805B1 Bandgap Reference GND QI Temperature Shutdown EN Enable Current Limitation ADJ

Data Sheet 5 Rev. 1.2 2016-01-11 TLS805B1SJ/LDV Pin Configuration

3 Pin Configuration

3.1 Pin Assignment in PG-DSO-8 Package

Figure 4 Pin Configuration TLS805B1 in PG-DSO-8 package

3.2 Pin Definitions and Functions in PG-DSO-8 Package

It is recommended to place a small ceramic capacitor (e.g. 100 nF) to GND, close to the IC terminals, in order to compensate line influences. 2N . C . Not connected 3E N Enable Integrated pull-down resistor. Enable the IC with high level input signal. Disable the IC with low level input signal. 4G N D Ground 5N . C . Not connected 6N . C . Not connected 7A D J Voltage Adjustment Connect an external voltage divider to determine the output voltage. 8Q Output Connect an output capacitor CQ to GND close to the IC’s terminals, respecting the values specified for its capacitance and ESR in Table 2 “Functional Range” on Page 9. Q ADJ N.C. I N.C. EN GND N.C.

Data Sheet 6 Rev. 1.2 2016-01-11 TLS805B1SJ/LDV Pin Configuration

3.3 Pin Assignment in PG-TSON-10 Package

Figure 5 Pin Configuration TLS805B1 in PG-TSON-10 package

3.4 Pin Definitions and Functions in PG-TSON-10 Package

It is recommended to place a small ceramic capacitor (e.g. 100 nF) to GND, close to the IC terminals, in order to compensate line influences. 2N . C . Not connected 3E N Enable Integrated pull-down resistor. Enable the IC with high level input signal. Disable the IC with low level input signal. 4N . C . Not connected 5G N D Ground 6N . C . Not connected 7N . C . Not connected 8A D J Voltage Adjustment Connect an external voltage devider to determine the output voltage. The pin is left not connected for fixed output voltage version. 9Q Output Connect an output capacitor CQ to GND close to the IC’s terminals, respecting the values specified for its capacitance and ESR in Table 2 “Functional Range” on Page 9. I N.C. N.C. EN GND ADJ N.C. TSON-10 N.C. Q N.C.4

Data Sheet 7 Rev. 1.2 2016-01-11 TLS805B1SJ/LDV Pin Configuration 10 N.C. Not connected Pad – Exposed Pad Connect to heatsink area. Connect to GND. Pin Symbol Function

Data Sheet 8 Rev. 1.2 2016-01-11 TLS805B1SJ/LDV General Product Characteristics

4 General Product Characteristics

4.1 Absolute Maximum Ratings

  1. Stresses above the ones listed he re may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection functions are designed to preven t IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Table 1 Absolute Maximum Ratings 1) Tj = -40 °C to +150 °C; all voltages with respect to ground (unless otherwise specified) 1) Not subject to production testing, specified by design. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Voltage Input I, Enable EN Voltage VI, VEN -0.3 – 45 V – P_4.1.1 Voltage Output Q Voltage V Voltage Adjustment ADJ Voltage VADJ -0.3 – 7 V – P_4.1.3 Temperatures Junction Temperature Tj -40 – 150 °C – P_4.1.4 Storage Temperature Tstg -55 – 150 °C – P_4.1.5 ESD Absorption ESD Susceptibility to GND VESD,HBM -2 – 2 kV HBM 2) 2) ESD susceptibility, HBM accordin g to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF) P_4.1.6 ESD Susceptibility to GND VESD,CDM -750 – 750 V CDM 3) at all pins 3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101 P_4.1.7

Data Sheet 9 Rev. 1.2 2016-01-11 TLS805B1SJ/LDV General Product Characteristics

4.2 Functional Range

Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the Electrical Characteristics table. Table 2 Functional Range Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Input Voltage Range VI VQ,nom+Vdr –4 2 V – 1) 1) Output current is limited internally and depends on the in put voltage, see Electrical Characteristics for more details. P_4.2.1 Extended Input Voltage Range VI,ext 2.75 – 42 V – 2) 2) When VI is between VI,ext.min and VQ,nom + Vdr, VQ = VI - Vdr. When VI is below VI,ext,min, VQ can drop down to 0 V. P_4.2.2 Output Capacitor CQ 1– – µ F – 3)4) 3) The minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%. P_4.2.3 Output Capacitor’s ESR ESR( CQ) – – 100 Ω –4) 4) Not subject to production testing, specified by design. P_4.2.4 Junction temperature Tj -40 – 150 °C – P_4.2.5

Data Sheet 10 Rev. 1.2 2016-01-11 TLS805B1SJ/LDV General Product Characteristics

4.3 Thermal Resistance

Note: This thermal data was generated in accordance wi th JEDEC JESD51 standards. For more information, go to www.jedec.org. Table 3 Thermal Resistance TLS805B1 in PG-DSO-8 Package Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Package Version PG-DSO-8 Junction to Case1) 1) Not subject to production test, specified by design RthJC – 40 – K/W – P_4.3.1 Junction to Ambient1) RthJA – 114 – K/W 2s2p board 2) 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. P_4.3.2 Junction to Ambient1) RthJA – 172 – K/W 1s0p board, footprint only3) 3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product (Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu). P_4.3.3 Junction to Ambient1) RthJA – 139 – K/W 1s0p board, 300 mm 2 heatsink area on PCB3) P_4.3.4 Junction to Ambient1) RthJA – 133 – K/W 1s0p board, 600 mm 2 heatsink area on PCB3) P_4.3.5 Table 4 Thermal Resistance TLS805B1 in PG-TSON-10 Package Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Package Version PG-DSO-8 Junction to Case1) 1) Not subject to production test, specified by design RthJC – 13 – K/W – P_4.3.6 Junction to Ambient1) RthJA –6 0 –K / W 2 s 2 p b o a r d 2) 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. P_4.3.7 Junction to Ambient1) RthJA – 188 – K/W 1s0p board, footprint only3) 3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product (Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu). P_4.3.8 Junction to Ambient1) RthJA – 77 – K/W 1s0p board, 300 mm 2 heatsink area on PCB3) P_4.3.9 Junction to Ambient1) RthJA – 65 – K/W 1s0p board, 600 mm 2 heatsink area on PCB3) P_4.3.10

Data Sheet 11 Rev. 1.2 2016-01-11 TLS805B1SJ/LDV Block Description and Electrical Characteristics

5 Block Description and Electrical Characteristics

5.1 Voltage Regulation

The output voltage VQ is divided by a resistor network. This fractional voltage is compared to an internal voltage reference and the pass transistor is driven accordingly. The control loop stability depends on the output capacitor CQ, the load current, the chip temperature and the internal circuit structure. To ensure stable operatio n, the output capacitor’s capacitance and its equivalent series resistor ESR requirements given in “Functional Range” on Page 9 have to be maintained. For details see the typical pe rformance graph Output Capacitor Series Resistor ESR(C Q) versus Output Current I Q. Since the output capacitor is used to buffer load steps, it should be sized according to the application’s needs. An input capacitor CI is not required for stability, but is reco mmended to compensate line fluctuations. An additional reverse polarity protection diode and a comb ination of several capacito rs for filtering should be used, in case the input is connected directly to the battery line. Connect the capacitors close to the regulator terminals. In order to prevent overshoots during start-up, a smoot h ramping up function is implemented. This ensures almost no overshoots during start-up, mostly independent from load and output capacitance. Whenever the load current ex ceeds the specified limit, e. g. in case of a short circuit, the output current is limited and the output voltage decreases. The overtemperature shutdown circui t prevents the IC from immediate destruction under fault conditions (e.g. output continuously short-circuit) by switching off the power stage. After the chip has cooled down, the regulator restarts. This oscillator y thermal behaviour causes the junc tion temperature to exceed the maximum rating of 150°C and can significantly reduce the IC’s lifetime. Figure 6 Block Diagram Voltage Regulation Bandgap Reference GND QI Temperature Shutdown Current Limitation ADJ Regulated Output VoltageIQ VQ CQ Supply VI LOAD C ESR CI II

Data Sheet 12 Rev. 1.2 2016-01-11 TLS805B1SJ/LDV Block Description and Electrical Characteristics Table 5 Electrical Characteristics Tj = -40 °C to +150 °C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified). Typical values are given at Tj = 25 °C, VI = 13.5 V. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Output Voltage Precision1) 1) Referring to the device tolerance only, the tolerance of th e resistor divider can cause additional deviation. Parameter is tested with the ADJ pin directly connected to the output pin Q. ΔVQ -2 – 2 % 50 µA ≤ IQ ≤ 50 mA, VQ+ Vdr ≤ VI ≤ 28 V, VI ≥ 3V , R2 ≤ 250 kΩ P_5.1.1 Output Voltage Precision ΔVQ -2 – 2 % 50 µA ≤ IQ ≤ 25 mA, VQ+ Vdr ≤ VI ≤ 42 V, VI ≥ 3V , R2 ≤ 250 kΩ P_5.1.2 Output Current Limitation IQ,lim 51 85 120 mA 0 V ≤ VQ ≤ VQ,nom - 0.1 V P_5.1.3 Line Regulation steady-state ΔVQ,line –12 0 m V IQ = 1 mA, 6 V ≤ VI ≤ 32 V P_5.1.4 Load Regulation steady-state ΔVQ,load -20 -1 – mV VI = 6 V, 50 µA ≤ IQ ≤ 50 mA P_5.1.5 Dropout Voltage2) Vdr = VI - VQ 2) Measured when the output voltage VQ has dropped 100 mV from the nominal value obtained at VI = 13.5V Vdr – 100 300 mV IQ =5 0m A , VI = 5.4 V P_5.1.6 Output Voltage Adjustable Range VQ,Range 1.2 – VI - Vdr V VI < 42 V P_5.1.8 Ripple Rejection3) 3) Not subject to production test, specified by design PSRR –6 0 – d B IQ =5 0m A , VQ =1 . 2V , fripple = 100 Hz, Vripple = 0.5 Vp-p P_5.1.9 Overtemperature Shutdown Threshold3) Tj,sd 151 175 – °C Tj increasing P_5.1.10 Overtemperature Shutdown Threshold Hysteresis3) Tj,sdh –1 0 – K Tj decreasing P_5.1.11

Data Sheet 13 Rev. 1.2 2016-01-11 TLS805B1SJ/LDV Block Description and Electrical Characteristics

5.2 Typical Performance Characteristics Voltage Regulation

Typical Performance Characteristics Output Voltage VQ versus Junction Temperature Tj Output Current IQ versus Input Voltage VI Dropout Voltage Vdr versus Junction Temperature Tj Dropout Voltage Vdr versus Output Current IQ 0 50 100 150 1.15 1.16 1.17 1.18 1.19 1.2 1.21 1.22 1.23 1.24 Tj [°C] VQ [V] VI = 13.5 V IQ = 25 mA VQ,nom = 1.2 V 0 10 20 30 40 100 120 VI [V] IQmax [mA] Tj = −40 °C Tj = 25 °C Tj = 150 °C 0 50 100 150 100 120 140 160 180 200 Tj [°C] Vdr [mV] IQ = 10 mA IQ = 25 mA IQ = 50 mA 0 10 20 30 40 50 100 120 140 160 180 200 IQ [mA] Vdr [mV] Tj = −40 °C Tj = 25 °C Tj = 150 °C

Data Sheet 14 Rev. 1.2 2016-01-11 TLS805B1SJ/LDV Block Description and Electrical Characteristics Load Regulation ΔVQ,load versus Output Current IQ Line Regulation ΔVQ,line versus Input Voltage VI Output Voltage VQ versus Input Voltage VI Power Supply Ripple Rejection PSRR versus Ripple Frequency fr 0 10 20 30 40 50 −10 IQ [mA] dVload [mV] Tj = −40 °C Tj = 25 °C Tj = 150 °C 10 15 20 25 30 35 40 VI [V] dVline [mV] IQ = 1 mA VQ,nom = 1.2 V Tj = −40 °C Tj = 25 °C Tj = 150 °C 0 1 2 3 4 5 6 VI [V] VQ [V] VQ,nom = 5 V IQ = 50 mA Tj = 25 °C f [kHz] PSRR [dB] IQ = 10 mA CQ = 1 μF VI = 13.5 V VQ,nom = 1.2 V Vripple = 0.5 Vpp Tj = 25 °C

Data Sheet 15 Rev. 1.2 2016-01-11 TLS805B1SJ/LDV Block Description and Electrical Characteristics Output Capacitor Series Resistor ESR(CQ) versus Output Current IQ 0 10 20 30 40 50 IQ [mA] ESR(CQ) [Ω] CQ = 1 μF VI = 3...28 V Stable Region Unstable Region

Data Sheet 16 Rev. 1.2 2016-01-11 TLS805B1SJ/LDV Block Description and Electrical Characteristics

5.3 Current Consumption

Table 6 Electrical Characteristics Current Consumption Tj = -40 °C to +150 °C, VI = 13.5 V (unless otherwise specified). Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Current Consumption Iq = II Iq,off ––1µ A VEN ≤ 0.4 V, Tj < 105 °C P_5.3.1 Current Consumption Iq = II - IQ Iq –57 . 5 µ A IQ = 50 µA, Tj = 25 °C P_5.3.2 Current Consumption Iq = II - IQ Iq –61 0 µ A IQ = 50 µA, Tj < 105 °C P_5.3.3 Current Consumption Iq = II - IQ Iq –6 . 5 1 1 µ A IQ = 50 µA, Tj < 125 °C P_5.3.4 Current Consumption Iq = II - IQ Iq –6 . 5 1 1 µ A IQ= 50 mA, Tj < 125 °C P_5.3.5

Data Sheet 17 Rev. 1.2 2016-01-11 TLS805B1SJ/LDV Block Description and Electrical Characteristics

5.4 Typical Performance Characteristics Current Consumption

Typical Performance Characteristics Current Consumption Iq versus Output Current IQ Current Consumption Iq versus Input Voltage VI Current Consumption Iq versus Junction Temperature Tj Current Consumption in OFF mode Iq,off versus Junction Temperature Tj 0 10 20 30 40 50 IQ [mA] Iq [μA] VI = 13.5 V Tj = −40 °C Tj = 25 °C Tj = 105 °C Tj = 125 °C 10 15 20 25 30 35 40 VI [V] Iq [μA] IQ = 50 μA Tj = −40 °C Tj = 25 °C Tj = 105 °C Tj = 125 °C 0 50 100 150 Tj [°C] Iq [μA] VI = 13.5 V IQ = 50 μA 0 50 100 150 0.5 1.5 2.5 3.5 Tj [°C] Iq,off [μA] VI = 13.5 V VEN ≤ 0.4 V

Data Sheet 18 Rev. 1.2 2016-01-11 TLS805B1SJ/LDV Block Description and Electrical Characteristics

5.5 Enable

The device can be switched on and off by the Enable feature. Connect a HIGH level as specified below (e.g. the battery voltage) to pin EN to enable the device; connect a LOW level as specified below (e.g. GND) to switch it off. The Enable function has a build-in hysteresis to avoid toggling between ON/OFF state, if signals with slow slopes are appiled to the EN input. Table 7 Electrical Characteristics Enable Tj = -40 °C to +150 °C, VI = 13.5 V, all voltages with respect to ground (unless otherwise specified). Typical values are given at Tj = 25 °C, VI = 13.5 V. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Enable High Level Input Voltage VEN,H 2–– V VQ settled P_5.5.1 Enable Low Level Input Voltage VEN,L ––0 . 8 V VQ ≤ 0.1 V P_5.5.2 Enable High Level Input Current IEN,H ––4µ A VEN = 5 V P_5.5.3 Enable Internal Pull-down Resistor REN 1.25 2 3.5 M Ω –P _ 5 . 5 . 4

Data Sheet 19 Rev. 1.2 2016-01-11 TLS805B1SJ/LDV Block Description and Electrical Characteristics

5.6 Typical Performance Characteristics Enable

Typical Performance Characteristics Enable Input Current IEN versus Enable Input Voltage VEN 0 10 20 30 40 VEN [V] IEN [μA] Tj = −40 °C Tj = 25 °C Tj = 150 °C

Data Sheet 20 Rev. 1.2 2016-01-11 TLS805B1SJ/LDV

Application Information

6 Application Information

Note: The following information is given as a hint for th e implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device.

6.1 Application Diagram

Figure 7 Application Diagram

6.2 Selection of External Components

6.2.1 Input Pin

The typical input circuitry for a linear voltage regulator is shown in the application diagram above. A ceramic capacitor at the input, in the range of 100 nF to 470 nF, is recommended to filter out the high frequency disturbances imposed by the line e.g. ISO pulses 3a/b. This capacitor must be placed very close to the input pin of the linear voltage regulator on the PCB. An aluminum electrolytic capacitor in the range of 10 µF to 470 µF is recommended as an input buffer to smooth out high energy pulses, such as ISO pulse 2a. This capacitor should be placed close to the input pin of the linear voltage regulator on the PCB. An overvoltage suppressor diode can be used to further suppress any high voltage beyond the maximum rating of the linear voltage regulator and protect the device against any damage due to over-voltage. The external components at the input are not mandator y for the operation of the voltage regulator, but they are recommended in case of possible external disturbances. TLS805B1 QI EN ADJ Regulated Output VoltageIQ CQ 1μF Supply 100nF10μF CI1CI2 <45V DI2 II GND e.g. Ignition Load (e.g. Micro Controller) GND DI1

Data Sheet 21 Rev. 1.2 2016-01-11 TLS805B1SJ/LDV

6.2.2 Output Pin

An output capacitor is mandatory for the stability of linear voltage regulators. The requirement to the outp ut capacitor is given in “Functional Range” on Page 9 . The graph “Output Capacitor Series Resistor ESR(CQ) versus Output Current IQ” on Page 15 shows the stable operation range of the device. TLS805B1 is designed to be stable with extremel y low ESR capacitors. According to the automotive environment, ceramic capacitors with X5R or X7R dielectrics are recommended. The output capacitor should be placed as close as possible to the regulator’s output and GND pins and on the same side of the PCB as the regulator itself. I n c a s e o f r a p i d t r a n s i e n t s o f i nput voltage or load curr ent, the capacitance sh ould be dimensioned in accordance and verified in the real application that the output stability requirements are fulfilled.

6.3 Output Voltage Adjust

The output voltage of TLS805B1SJ/LDV can be adjusted between 1.2 V and VI - Vdr by an external resistor divider, connected to the adjust pin ADJ, as shown in Figure 7. The pin ADJ is connected to the error amplifier comparing the voltage at th is pin with the internal reference voltage of typically 1.2 V. The output voltage can be easily calculated, neglecting the current flowing into the ADJ pin: (6.1) with

  • Vref: internal reference voltage, typically 1.2V
  • R1: resistor between regulator output Q and adjust pin ADJ
  • R2: resistor between adjust pin ADJ and GND The bigger the resistors R1 and R2, the less the current flowing through the resistor divider. However, using too big resistors makes the current flowing into the ADJ pin non-negligible. In oder to neglect the current flowing into the ADJ pin, the values of R1 and R2 should be selected fulfilling the criteria R2 ≤ 250 kΩ. To set the output voltage to 1.2 V, the adjust pin ADJ should be directly connected to the output pin Q. Take into consideration that an additional error to the output voltage tolerance may be introduced by the accuracy of the resistors R1 and R2.

6.4 Thermal Considerations

Knowing the input voltage, the output voltage and th e load profile of the application, the total power dissipation can be calculated: (6.2) with

  • PD: continuous power dissipation
  • VI: input voltage
  • VQ: output voltage VQ R1 R2+ PD VI VQ–() IQ VI Iq×+×=

Data Sheet 22 Rev. 1.2 2016-01-11 TLS805B1SJ/LDV

  • IQ: output current
  • Iq: quiescent current The maximum acceptable thermal resistance RthJA can then be calculated: (6.3) with
  • Tj,max: maximum allowed junction temperature
  • Ta: ambient temperature Based on the above calculation the proper PCB type and the necessary heat sink area can be determined with reference to the specification in “Thermal Resistance” on Page 10. Example Application conditions: VI = 13.5 V VQ = 5 V IQ = 35 mA Ta = 105 °C Calculation of RthJA,max: PD =( VI – VQ) x IQ + VI x Iq = (13.5V – 5V) x 35 mA + 13.5 V x 0.0115 mA = 0.2975 W RthJA,max=( Tj,max – Ta) / PD = 151.2 K/W As a result, the PCB design must ensure a thermal resistance RthJA lower than 151.2 K/W. According to “Thermal Resistance” on Page 10, for both TLS805B1SJV and TLS805B1LDV at least 300 mm² heatsink area is needed on the FR4 1s0p PCB, or the FR4 2s2p board can be used.

6.5 Reverse Polarity Protection

TLS805B1 is not self protected agains t reverse polarity faults. To prot ect the device against negative supply voltage, an external reverse polarity diode is needed, as shown in Figure 7. The absolute maximum ratings of the device as specified in “Absolute Maximum Ratings” on Page 8 must be kept.

6.6 Further Application Information

  • For further information you may contact http://www.infineon.com/ RthJA max, Tjm a x, Ta– PD

Data Sheet 23 Rev. 1.2 2016-01-11 TLS805B1SJ/LDV Package Outlines

7 Package Outlines

0.35 x 45° 1)-0.24 C +0.06 0.19 0.64 ±0.26 ±0.25 0.2 8xM C 1.27 +0.10.41

0.2 M A

-0.06 SEATING PLANE B Index Marking 8 5 5-0.2 1) A 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Lead width can be 0.61 max. in dambar area 1.75 MAX. (1.45) ±0.070.175 B0.1 8° MAX.

Data Sheet 24 Rev. 1.2 2016-01-11 TLS805B1SJ/LDV Package Outlines Figure 9 PG-TSON-10 Green Product (RoHS compliant) To meet the world-wide customer requirements for en vironmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Pin 1 Marking Pin 1 Marking PG-TSON-10-2-PO V02 ±0.10.2 ±0.10.25 ±0.10.55 0.96 ±0.1 2.58±0.1 0 +0.05 ±0.1 ±0.1 0.25 0.5 ±0.13.3 ±0.13.3 ±0.1 1±0.1 0.71±0.1 1.63±0.1 1.48±0.1 Z 0.05 0.07 MIN. Z (4:1) For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Dimensions in mm

Data Sheet 25 Rev. 1.2 2016-01-11 TLS805B1SJ/LDV

Revision History

8 Revision History

1.2 2016-01-11 New variant TLS805B1LD V in PG-TSON-10 package added. 1.1 2015-11-02 - Functional range of the Enable input voltage defined. - Document style updated. - Typical performance graph Load Regulation updated. - Editorial changes. 1.0 2015-02-05 Datasheet - Initial Version

Trademarks of Infineon Technologies AG AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolMOS™, CoolSET™, CORE CONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HI TFET™, HybridPACK™, I²RF™, ISOF ACE™, IsoPACK™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™, POWERCODE™, PR IMARION™, PrimePACK™, PrimeSTACK ™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SPOC™, SOLID FLASH™, TEMPFET™, th inQ!™, TRENCHSTOP™, TriCore™. Other Trademarks Advance Design System™ (ADS) of Agilent Tech nologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ o f ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR developm ent partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Co mmission Electrotechnique Internationale. IrDA™ of Infrared Dat a Association Corporation. ISO™ of INTERNATIONAL ORGANIZA TION FOR STANDARDIZATION. MATLAB™ of MathWo rks, Inc. MAXIM™ of Maxim Integrated Prod ucts, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., Om niVision™ of OmniVision Te chnologies, Inc. Openwave™ Openwave TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADI UM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2011-11-11 Edition 2016-01-11 Published by Infineon Technologies AG

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