TLS208D1 INFINEON | Alldatasheet
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Technical content
Rev. 1.0, 2015-02-26 TLS208D1 Linear Voltage Post Regulator TLS208D1EJV TLS208D1EJV33 TLS208D1LDV TLS208D1LDV33
Data Sheet 2 Rev. 1.0, 2015-02-26 TLS208D1 Table of Contents
TLS208D1EJV PG-DSO-8 (Exposed Pad) 208D1V TLS208D1EJV33 PG-DSO-8 (Exposed Pad) 208D1V33 TLS208D1LDV PG-TSON10 208DV TLS208D1LDV33 PG-TSON10 208DV33 PG-DSO-8 (Exposed Pad) PG-TSON10 Data Sheet 3 Rev. 1.0, 2015-02-26 Linear Voltage Post Regulator TLS208D1 1O v e r v i e w
Features
- 3.3 V Fixed and Adjustable Output Voltage from 0.8 V to 5.25 V
- Output Voltage Accuracy of ± 2%
- Static Output Currents up to 800 mA
- Enable Functionality
- Undervoltage Reset with Power-On Reset Delay
- Adjustable Reset Threshold
- Extended Input Voltage Operat ing Range of 2.7 V to 18 V
- Low Dropout Voltage: typ. 400mV at 400mA
- Very Low Current Consumption: typ. 90 µA
- Very High PSRR: typ. 62dB at 10kHz
- Output Current Limitation
- Overtemperature Shutdown
- Wide Temperature Range From -40 °C up to 150 °C
- Suitable for Use in Automotive Electronics as Post Regulator
- Green Product (RoHS compliant)
- AEC Qualified
Description
The TLS208D1 is a monolithic integrated linear voltage post regulator. The IC regulates an input voltage VI in the range of 2.7 V ≤ VI ≤ 18 V to an adjustable output voltage of 0.8 V to 5.25 V or to a fixed output voltage with a precision of ±2 %. The TLS208D1 is especially designed for applications with a permanent connection to preregulators like DCDC converters. The device is ava ilable in the small surface mounted PG-DSO-8 (Exposed Pad) package. In addition to the enabl e functionality, the feature set includes a reset with an adjustable reset threshold. This threshold can be modified by an external resistor divider. The device is designed for the harsh environment of automotive applications. Therefore it is protected against ov erload, short circuit and overtemperature conditions by the implemented outpu t current limitation and the overtemperature shutdown circuit. The TLS208D1 can be also used in all other applications requiring a stabilized voltage of 0.8 V to 5.25 V. The input capacitor CI is recommended for compensating line influences. The output capacitor CQ is necessary for the stability of the regulating circuit. St ability is guaranteed at values specified in “Functional Range” on Page 8 within the whole operating temperature range.
Data Sheet 4 Rev. 1.0, 2015-02-26 TLS208D1 Block Diagram
2 Block Diagram
Figure 1 Block Diagram Adjustable Version (e.g. TLS208D1EJV) Figure 2 Block Diagram Fixed Voltage Version (e.g. TLS208D1EJV33) Bandgap Reference Current Limitation Driver Internal Supply Reset Control Temperature Shutdown I EN GND RADJ RO ADJ Q Bandgap Reference Current Limitation Temperature Shutdown Driver Internal Supply Reset Control I EN GND RO RADJ FB Q
Data Sheet 5 Rev. 1.0, 2015-02-26
3 Pin Configuration
3.1 Pin Assignment PG-DSO-8 (Exposed Pad)
Figure 3 Pin Configuration Package PG-DSO-8 (Exposed Pad)
3.2 Pin Definitions and Functi ons PG-DSO-8 (Exposed Pad)
1I Input. IC supply. For compensating line influences, a capacitor of 220 nF close to the IC pins is recommended. 2N . C Not Connected. 3G N D Ground Reference. Connect this pin low ohmic to GND. 4E N Enable. A low signal disables the IC. A high signal switches it on. Connect to the input I, if the enable functionality is not required. 5R O Reset Output The open collector output can be connected to a microcontroller using a external pull up resistor. If the functionality is not required, the pin can be left open. 6R A D J Reset Adjust. For reset threshold adjustment connect to a voltage divider from output Q to GND. (“Description Reset Function” on Page 20) 7A D J FB Adjust. (Only Adjustable Version TLS208D1EJV) The reference voltage can be connected to the output pin directly or by a voltage divider for higher output voltages (see application information). Feedback. (Only Fixed Voltage Versions e.g. TLS208D1EJV33) The Feedback pin has to be connected to the output voltage. 8Q Output. Block to GND with a capacitor close to the IC terminals, respecting capacitance and ESR requirements given in the table “Functional Range” on Page 8. Pad EP Exposed Pad. Connect to PCB heat sink area and GND. Q ADJ/FB RADJ IN N.C. GND EN RO
Data Sheet 6 Rev. 1.0, 2015-02-26 TLS208D1 Pin Configuration
3.3 Pin Assignment PG-TSON10
Figure 4 Pin Configuration Package PG-TSON10
3.4 Pin Definitions an d Functions PG-TSON10
1I Input. IC supply. For compensating line influences, a capacitor of 220 nF close to the IC pins is recommended. 2N . C Not Connected. 3G N D Ground Reference. Connect this pin low ohmic to GND. 4N . C Not Connected. 5E N Enable. A low signal disables the IC. A high signal switches it on. Connect to the input I, if the enable functionality is not required. 6R O Reset Output The open collector output can be connected to a microcontroller using a external pull up resistor. If the functionality is not required, the pin can be left open. 7N . C Not Connected. 8R A D J Reset Adjust. For reset threshold adjustment connect to a voltage divider from output Q to GND. (“Description Reset Function” on Page 20) 9A D J FB Adjust. (Only Adjustable Version TLS208D1LDV) The reference voltage can be connected to the output pin directly or by a voltage divider for higher output voltages (see application information). Feedback. (Only Fixed Voltage Versions e.g. TLS208D1LDV33) The Feedback pin has to be connected to the output voltage. 10 Q Output. Block to GND with a capacitor close to the IC terminals, respecting capacitance and ESR requirements given in the table “Functional Range” on Page 8. Pad EP Exposed Pad. Connect to PCB heat sink area and GND. I Q N.C. GND N.C. EN N.C. RO RADJ ADJ/FB PG-TSON10
General Product Characteristics Data Sheet 7 Rev. 1.0, 2015-02-26
4 General Product Characteristics
4.1 Absolute Maximum Ratings
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1. Integrated protection func tions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Table 1 Absolute Maximum Ratings 1) Tj = -40 °C to +150 °C; all voltages with respect to ground, (unless otherwise specified) 1) not subject to production test, specified by design Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Input I Voltage VI -0.3 – 20 V – P_4.1.1 Output Q Voltage Adjust ADJ Voltage VADJ -0.3 – 5.5 V – P_4.1.3 Feedback FB Voltage VFB -0.3 – 5.5 V – P_4.1.4 Enable EN Voltage VEN -0.3 – 20 V – P_4.1.5 Reset Output Voltage Reset Adjust Voltage VRADJ -0.3 – 5.5 V – P_4.1.7 Temperature Junction temperature Tj -40 – 150 °C – P_4.1.8 Storage temperature Tstg -50 – 150 °C – P_4.1.9 ESD Susceptibility ESD Absorption VESD,HBM -2 – 2 kV Human Body Model (HBM) 2) 2) ESD susceptibility, HBM accordin g to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF) P_4.1.10 ESD Absorption VESD,CDM -750 – 750 V Charge Device Model (CDM) 3) P_4.1.11
Data Sheet 8 Rev. 1.0, 2015-02-26 TLS208D1 General Product Characteristics
4.2 Functional Range
Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the Electrical Characteristics table.
4.3 Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Table 2 Functional Range Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Input voltage VI 2.7 – 18 V – P_4.2.1 Output Capacitor Requirements for Stability CQ 1––µ F 1)– 1) The minimum output capacitance requ irement is applicable for a worst case capacitance tolerance of 30% P_4.2.2 Output Capacitor Requirements for Stability ESR(CQ) – – 10 Ω 2) 2) relevant ESR value at f =1 0k H z P_4.2.3 Junction temperature Tj -40 – 150 °C – P_4.2.4 Table 3 Thermal Resistance Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. PG-DSO-8 (Exposed Pad) Junction to Ambient 1) Not subject to production test, specified by design. RthJA – 42 – K/W 2s2p board 2) 2) Specified RthJA value is according to JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layer (2 x 70µm Cu, 2 x 35µm Cu). Where applicable a thermal via array under the exposed pad contacted to the first inner copper layer. P_4.3.1 Junction to Ambient RthJA – 150 – K/W Footprint only 3) 3) Package mounted on PCB FR4; 80 x 80 x 1.5 mm; 35 µm Cu, 5 µm Sn; horizontal position; zero airflow. P_4.3.2 Junction to Ambient RthJA –6 6 –K / W 3 0 0 m m 2 PCB heatsink area 3) P_4.3.3 Junction to Ambient RthJA –5 5 –K / W 6 0 0 m m 2 PCB heatsink area 3) P_4.3.4 Junction to Case RthJC – 9.5 – K/W P_4.3.5 PG-TSON10 Junction to Ambient 1) RthJA – 57 – K/W 2s2p board 2) P_4.3.6 Junction to Ambient RthJA – 176 – K/W Footprint only 3) P_4.3.7 Junction to Ambient RthJA –7 0 –K / W 3 0 0 m m 2 PCB heatsink area 3) P_4.3.8 Junction to Ambient RthJA –5 9 –K / W 6 0 0 m m 2 PCB heatsink area 3) P_4.3.9 Junction to Case RthJC –9–K / W P_4.3.10
Data Sheet 9 Rev. 1.0, 2015-02-26
5 Voltage Regulator
5.1 Description Voltage Regulator
The output voltage VQ is controlled as follows: it is divided by the re sistor divider. This fraction is then compared to an internal reference and drives the pass transistor accordingly. By connecting the ADJ pin directly to th e output Q the device will regulate to it s reference voltage. In this case a minimum load resistance of less than 300 kΩ needs to be ensured for stability reasons. The control loop stability depends on the output capacitor CQ, the load current, the chip temperature and the circuit design. To ensure stable operation, the requirements fo r output capacitance and eq uivalent series resistance ESR, given in the “Functional Range” on Page 8, have to be maintained. For details see also the typical stability graph of ESR versus load current on Page 17. As the output capacitor also has to buffer load steps it should be sized according to the needs of the application. An input capacitor CI of at least 220 nF is recommended to compensate line influences. Connect the capacitors close to the terminals of the component. In case the load current is above the specified limit, e.g. in case of a short circuit, the output current limitation limits the current. The output voltage is therefore decreasing at the same time. The overtemperature shutdown circuit prevents the IC from immediate destruction under fault conditions (e.g. output continuously short-circuited) by switching off the power stage. After the chip has cooled down, the regulator restarts. This leads to an oscillatory behavior of the output volt age until the fault is re moved. However, junction temperatures above 150 °C are outside the maximum ratings and therefore significantly reduce the IC’s lifetime. Figure 5 Block Diagram Voltage Re gulator Circuit (Fixed Voltage Variant e.g. TLS208D1EJV33) Figure 6 Block Diagram Voltage Regu lator Circuit (Adjustable Voltage Variant e.g. TLS208D1EJV) Bandgap Reference Current Limitation Temperature Shutdown LOAD Supply CI Regulated Output VoltageIQII Driver VI VQ C ESR CQ FB Q GND I Bandgap Reference Current Limitation Temperature Shutdown LOAD Supply CI Regulated Output VoltageIQII Driver VI VQ C ESR CQ Q GND I ADJ
Data Sheet 10 Rev. 1.0, 2015-02-26 TLS208D1 Voltage Regulator
5.2 Electrical Character istics Voltage Regulator
Table 4 Electrical Characteristics VI = VQ,nom + 1 V and VI > 2.7 V; Tj = -40 °C to +150 °C; all voltages with respect to ground (unless otherwise specified) Parameter Symbol Values Unit No te / Test Condition Number Min. Typ. Max. Characteristic Adjustable Output Voltage (TLS208D1EJV, TLS208D1LDV) Reference Voltage Vref –0 . 8 –V P_5.2.1 Output Voltage 1) TLS208D1EJV TLS208D1LDV VQ -1% VQ,nom +1% V IQ =1 0 0m A; Tj = 25 °C P_5.2.2 Output Voltage 1) TLS208D1EJV TLS208D1LDV VQ -2% VQ,nom +2% V IQ =1 0 0m A; P_5.2.3 Adjustable Voltage Range 2) TLS208D1EJV TLS208D1LDV Load Regulation TLS208D1EJV TLS208D1LDV ∆VQ,load /VQ,nom –51 0 m V / V IQ = 100 mA to 1 mA ; VI ≥ VQ,nom + Vdr,max +1 0 0m V 3) 4) P_5.2.5 Load Regulation TLS208D1EJV TLS208D1LDV ∆VQ,load /VQ,nom -10 -5 – mV/V IQ = 100 mA to 800 mA ; VI ≥ VQ,nom + Vdr,max +1 0 0m V and VI ≥ 3.8 V 3) 4) P_5.2.6 Line Regulation TLS208D1EJV TLS208D1LDV VQ,line /VQ,nom) /∆VI – 0.01 0.2 %/V VI =( VQ,nom +1V )t o 1 0V; VI ≥ 2.7 V ; IQ =1m A 4) P_5.2.7 Characteristic Fixed Output Voltage (TLS208D1EJV33, TLS208D1LDV33) Output Voltage TLS208D1EJV33 TLS208D1LDV33 VQ 3.267 3.3 3.333 V IQ =1 0 0m A; Tj = 25 °C P_5.2.8 Output Voltage TLS208D1EJV33 TLS208D1LDV33 Load Regulation TLS208D1EJV33 TLS208D1LDV33 ∆VQ,load –1 6 3 3 m V IQ = 100 mA to 1 mA ; VI ≥ 4.4 V 3) P_5.2.10 Load Regulation TLS208D1EJV33 TLS208D1LDV33 VQ,load -33 -16 – mV IQ = 100 mA to 800 mA ; VI ≥ 4.4 V 3) P_5.2.11 Line Regulation TLS208D1EJV33 TLS208D1LDV33 Dropoutvoltage Characteristic
Data Sheet 11 Rev. 1.0, 2015-02-26 Power Supply Ripple Rejection 2) PSRR –6 2 –d B ff = 10 kHz ; IQ = 200 mA ; Tj =2 5° C ; Vin = VQ +1 . 5V and Vin ≥ 3.2 V ; ∆VI =1 Vpp ; CQ = 1 µF(Ceramic Capacitor) P_5.2.20 Protection Features Output Current Limitation IQ 801 1150 1350 mA 0 V ≤ VQ ≤ 0.9 * VQ,nom P_5.2.21 Overtemperature Shutdown Threshold 2) Tj,sd 151 175 200 °C Tj increasing P_5.2.22 Overtemperature Shutdown Hysteresis 2) Tj,sd,Hyst –1 5 –° C Tj decreasing P_5.2.23 Adjust Pin Characteristic (TLS208D1EJV) Adjust Pin Pull Up Current 7) IADJ ––5 0 0 n A – P_5.2.24 1) Referring to the device tolerance only, the tolerance of the resistor divider can cause additional deviation. Parameter is tested with ADJ-Pin directly connected to the output Q. 2) This parameter is not subject to production test, specified by design 3) The input voltage condition is intended to ensure that the device is out of the drop condition. 4) Tested with ADJ-Pin directly connected to the output Q. 5) Dropout voltage is defined as the diffe rence between input and output voltage when the output voltage decreases 100 mV from output voltage measured at VI = VQ,nom + Vdr,max + 100 mV. 6) The dropout voltage might be limited to the minimum input voltage as defined in P_4.2.1 on Page 8 7) ADJ pin pull up current flows out of the ADJ pin. Table 4 Electrical Characteristics VI = VQ,nom + 1 V and VI > 2.7 V; Tj = -40 °C to +150 °C; all voltages with respect to ground (unless otherwise specified) (cont’d) Parameter Symbol Values Unit No te / Test Condition Number Min. Typ. Max.
Data Sheet 12 Rev. 1.0, 2015-02-26 TLS208D1 Voltage Regulator
5.3 Typical Performance Characteristics Voltage Regulator
VEN = 5 V (unless otherwise noted) Typical Performance Characteristics Output Voltage VQ vs. Input Voltage VI (Line Regulation) Output Voltage VQ vs. Load Current IQ (Load Regulation) Output Voltage VQ vs. Junction Temperature Tj Power Up Timing VQ 4 6 8 10 12 14 16 18 3.27 3.28 3.29 3.3 3.31 3.32 3.33 VI [V] VQ [V] Tj = −40 °C Tj = 25 °C Tj = 125 °C Tj = 150 °C 0 200 400 600 800 3.25 3.26 3.27 3.28 3.29 3.3 3.31 3.32 3.33 3.34 3.35 IQ [mA] VQ [V] VI = 4.3 V Tj = −40 °C Tj = 25 °C Tj = 125 °C Tj = 150 °C −50 0 50 100 150 3.27 3.28 3.29 3.3 3.31 3.32 3.33 Tj [°C] VQ [V] VI = 4.3V ; VQ,nom = 3.3V IQ = 1 mA IQ = 100 mA IQ = 400 mA IQ = 800 mA 0 100 200 300 400 500 0.5 1.5 2.5 3.5 4.5 t [µs] V [V] VQ,nom = 3.3V IQ = 100mA VEN VQ
Data Sheet 13 Rev. 1.0, 2015-02-26 Dropout Voltage Vdr vs. Load Current IQ (VQ,nom =3 . 3 V ) Dropout Voltage Vdr vs. Output Voltage VQ (IQ =4 0 0m A ) Dropout Voltage Vdr vs. Output Voltage VQ (IQ =8 0 0m A ) Adjust Pin Current IADJ vs. Junction Temperature Tj 0 200 400 600 800 100 200 300 400 500 600 700 800 900 IQ [mA] Vdr [mV] VQnom = 3.3 V Tj = −40 °C Tj = 25 °C Tj = 125 °C Tj = 150 °C 1 2 3 4 5 200 400 600 800 1000 1200 VQ [V] Vdr [mV] Tj = −40 °C Tj = 25 °C Tj = 125 °C Tj = 150 °C 1 2 3 4 5 200 400 600 800 1000 1200 1400 1600 1800 VQ [V] Vdr [mV] Tj = −40 °C Tj = 25 °C Tj = 125 °C Tj = 150 °C −50 0 50 100 150 100 150 200 250 300 Tj [°C] IADJ [nA]
Data Sheet 14 Rev. 1.0, 2015-02-26 TLS208D1 Voltage Regulator PSRR vs. Frequency TLS208D1xxV33 PSRR vs. Frequency TLS208D1xxV (adjusted to VQ,nom =3 . 3V ) Noise Graph TLS208D1xxV (adjusted to VQ,nom =3 . 3V ) Output Capacitor Series Resistance ESR(CQ) vs. Output Current IQ (CQ =1 μF) 10 100 1k 10k 100k 1M f [Hz] PSRR [dB] IL = 200 mA VI = 5 V Tj = 25 °C CQ = 1 µF Ceramic . 10 100 1k 10k 100k 1M f [Hz] PSRR [dB] IL = 200 mA VI = 5 V VQ,nom = 3.3 V Tj = 25 °C CQ = 1 µF Ceramic CBYP = 1 nF Ceramic . without CBYP CBYP = 1 nF 10 100 1k 10k 100k 1M 0.01 0.1 f [Hz] Noise [µV/sqrt(Hz)] IL = 200 mA VI = 5 V VQ,nom = 3.3 V Tj = 25 °C CQ = 1 µF Ceramic 0 200 400 600 800 IQ [mA] ESR(CQ) [Ω] CQ = 1 µF Min ESR is equal to built−in ESR of Cap. . Max ESR Min ESR
Data Sheet 15 Rev. 1.0, 2015-02-26 Dynamic Load Response TLS208D1xxV33 (10mA to 200mA) Dynamic Load Response TLS208D1xxV33 (10mA to 400mA) Dynamic Load Response TLS208D1xxV (adjusted to VQ,nom = 3.3 V) (10mA to 200mA) Dynamic Load Response TLS208D1xxV (adjusted to VQ,nom = 3.3 V) (10mA to 400mA)
Data Sheet 16 Rev. 1.0, 2015-02-26 TLS208D1 Voltage Regulator Dynamic Load Response TLS208D1xxV (adjusted to VQ,nom = 0.8 V) (10mA to 100mA)
Data Sheet 17 Rev. 1.0, 2015-02-26
6 Current Consumption
6.1 Description Current Consumption
The Current Consumption of the device is characterizing the current the device needs to operate. The Quiescent Current is describing the Current Consumption in a very low load condition (e.g. the supplied microcontroller is in sleep mode). The TLS208D1 has an Enable functionality to shutdown the device, in case it is not needed. During shutdown the device has a very low Current Consumpt ion. The Current Consumption of the device can be determined by measuring the Current flowing out of the GND Pin and defined as the delta between II and (IQ+IEN). Figure 7 Parameter Definition Current Consumption
6.2 Electrical Characteris tics Current Consumption
Table 5 Electrical Characteristics VI = VQ,nom + 1 V and VI > 2.7 V ; Tj = -40 °C to +150 °C , VRADJ ≥ 1.3 V; all voltages with respect to ground (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Quiescent Current Iq = II – IQ Iq –9 0 1 7 0 µ A IQ =1 0µ A P_6.2.1 Current Consumption Iq = II – IQ Iq – 200 250 µA I Q =5 0m A P_6.2.2 Quiescent Current in Shutdown Iq,off –0 . 0 1 6 µ A V I =5V ; VEN =0V ; Tj ≤ 125 °C ; VQ =0V P_6.2.3 GND QI CurrentConsumption _Block.vsd LOADCI IQII EN VI VQ Iq+IEN VEN TLS208D1 C ESR CQ IEN
Data Sheet 18 Rev. 1.0, 2015-02-26 TLS208D1 Current Consumption
6.3 Typical Performance Charac teristics Current Consumption
VEN= 5 V (unless otherwise noted) Quiescent Current Iq vs. Input Voltage VI Quiescent Current Iq vs. Junction Temperature Tj Current Consumption Iq vs. Load Current IQ Quiescent Current in Shutdown Iq,off vs. Junction Temperature Tj 4 6 8 10 12 14 16 18 100 120 140 160 180 200 VI [V] Iq [µA] Tj = 25 [°C] IQ = 10 µA IQ = 10 mA IQ = 100 mA −50 0 50 100 150 100 150 200 250 300 Tj [°C] Iq [µA] VI = 4.3 V IQ = 10 µA IQ = 10 mA IQ = 50 mA IQ = 400 mA 0 100 200 300 400 100 150 200 250 300 IQ [mA] Iq [µA] VI = 4.3 V Tj = −40 °C Tj = 25 °C Tj = 125 °C Tj = 150 °C −50 0 50 100 150 100 120 140 160 180 200 Tj [°C] Iq,off [nA] VEN = 0 V VI = 4.3 V VI = 10 V VI = 14 V
Data Sheet 19 Rev. 1.0, 2015-02-26
7 Enable Function
7.1 Description Enable Function
The TLS208D1 can be turned on or turned off by the EN Input. The parameter VEN is the voltage provided to the EN Pin as shown in Figure 7 “Parameter Definition Current Consumption” on Page 17. With voltage levels lower than VEN,Lo applied to the EN Input the device will be turned off. Du ring this state the device is in shutdown with a very low current consumption Iq,off. Changing the voltage at the EN Input from VEN,Lo to VEN,Hi will trigger the start-up of the device. For voltages higher than VEN,Hi the device will re gulate the output voltage to the nominal value as described in Chapter 5 Voltage Regulator.
7.2 Electrical Character istics Enable Function
7.3 Typical Performance Char acteristics Enable Function
Table 6 Electrical Characteristics VI = VQ,nom + 1 V and VI > 2.7 V ; Tj = -40 °C to +150 °C ; all voltages with respect to ground (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Enable High Voltage Level VEN,Hi 2– – V VQ,on ≥ 0.95 VQ,nom P_7.2.1 Enable Low Voltage Level VEN,Lo –– 0 . 4 V VQ,off ≤ 200 mV P_7.2.2 Enable Pin Current 1) 1) Enable pin current flows into the EN pin. IEN –4 5 µ A VEN = 5V P_7.2.3 Enable Thresholds VEN vs. Junction Temperature Tj Enable Pin Current VEN vs. Junction Temperature Tj −50 0 50 100 1500.8 1.2 1.4 1.6 1.8 Tj [°C] VEN,th [V] VEN increasing (Off−to−On) VEN decreasing (On−to−Off) −50 0 50 100 150 0.5 1.5 2.5 3.5 4.5 Tj [°C] IEN [µA] VEN = 5 V .
Data Sheet 20 Rev. 1.0, 2015-02-26 TLS208D1 Reset Function
8 Reset Function
8.1 Description Reset Function
The TLS208D1’s output voltage is supervised by the Reset feature, including Undervoltage Reset, delayed Reset at Power-On and an adjustable Reset Threshold. Furthermore there is an input voltage monitor implemented that is contributing to the reset function. The Undervoltage Reset sets the pin RO to LOW, in case VQ is falling for any reason below the Reset Threshold VRT,low. When the regulator is powered on, the pin RO is held at LOW for the duration of the Power-On Reset Delay Time trd. Figure 8 Block Diagram Reset Circuit Reset Adjust Function The undervoltage reset switching threshold can be adjuste d according to the application’s needs by connecting an external voltage divider (RADJ,1, RADJ,2) at pin “RADJ”. In case you are using a device with a fixed output voltage, you can select the default undervoltage reset threshold given in parameter by connecting the pin “RADJ” directly to GND. By connecting the pin “RADJ” to the output Q the reset threshold is set to the minimum, which corresponds to the specified parameter VRADJ. When dimensioning the voltage divider, take into consideration that there will be an additional current constantly flowing through the resistors. With a voltage divider connected, the reset switching threshold VRT,new is calculated as follows (neglecting the Reset Adjust Pin Current IRADJ): (1)
- VRT,new: Desired undervoltage reset switching threshold.
- RADJ,1, RADJ,2: Resistors of the external voltage divider, see Figure 8. GND QI OR Supply ROVRT,int RADJ Control Reset optionaloptional CQ VDD Micro- Controller GND RADJ,1 RADJ,2 RRO IRO IRADJ RRO,ext Power On Reset Delay trd in out trd Internal Reset Threshold only for fixed variants VRADJ VIn-RT
Data Sheet 21 Rev. 1.0, 2015-02-26
8.2 Electrical Character istics Reset Function
Table 7 Electrical Characteristics VI = VQ,nom + 1 V and VI > 2.7 V ; Tj = -40 °C to +150 °C ; all voltages with respect to ground (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Fixed Reset Threshold (TLS208D1EJV33 only) Output Undervoltage Reset Threshold (default) only TLS208D1EJV33 and TLS208D1LDV33 VRT,def 2.87 2.97 3.07 V VRADJ =0 V
1.355 V ≤ VRT
P_8.2.1 Output Undervoltage Reset Hysteresis VRT,hyst 33 66 99 mV P_8.2.2 Adjustable Reset Threshold Reset Adjust Lower Switching Threshold TLS208D1EJV33 TLS208D1LDV33 om P_8.2.3 Reset Adjust Lower Switching Threshold TLS208D1EJV33 TLS208D1LDV33 m P_8.2.4 Reset Adjust Lower Switching Threshold TLS208D1EJV TLS208D1LDV m P_8.2.5 Reset Adjust Switching Threshold Hysteresis 1) 1) This parameter is not subject to production test, specified by design VRADJ,hyst –2 5 – m V P_8.2.6 Reset Adjust Pull-down Current IRADJ –– 1 µ A P_8.2.7 Input Voltage Monitor Input Reset Threshold Hysteresis 1) VIn-RT,Hyst –6 0 – m V VI increasing P_8.2.9 Reset Timing Characteristic Power On Reset Delay Time trd 61 0 1 4 m s P_8.2.10 Internal Reset Reaction Time trr,int –– 1 0 µ s P_8.2.11 Reset Output Characteristic Reset Pin Leakage IRO,leak –– 1 µ A VRO = VQ,nom P_8.2.12 Reset Output Low Voltage VRO,Low –– 0 . 4 V RRO,ext =5k Ω ; 1V ≤ VQ ≤ VQ,nom P_8.2.13 Reset Output external Pull-up Resistor to Q RRO,ext 5– – k Ω VRO ≤ 0.4 V ; 1V ≤ VQ ≤ VQ,nom P_8.2.14
Data Sheet 22 Rev. 1.0, 2015-02-26 TLS208D1 Reset Function
8.3 Typical Performance Ch aracteristics Reset Function
VEN = 5 V (unless otherwise noted) Adjustable Reset Threshold Voltage VRADJ vs. Junction Temperature Tj RADJ Input Current IRADJ vs. Junction Temperature Tj Input Voltage Reset Threshold VIN-RT vs. Junction Temperature Tj Internal Reset Threshold Voltage VRT vs. Junction Temperature Tj (TLS208D1xxV33) −50 0 50 100 150 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 Tj [°C] VRADJ,th [V] VQ increasing VQ decreasing −50 0 50 100 150 100 120 140 160 180 200 Tj [°C] IRADJ [nA] −50 0 50 100 150 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 Tj [°C] VIN−RT [V] VI increasing VI decreasing −50 0 50 100 1502.85 2.9 2.95 3.05 3.1 3.15 Tj [°C] VRT [V] VQ increasing VQ decreasing
Data Sheet 23 Rev. 1.0, 2015-02-26 Reset Delay Time trd vs. Junction Temperature Tj −50 0 50 100 150 8.5 9.5 10.5 11.5 Tj [°C] trd [ms]
Data Sheet 24 Rev. 1.0, 2015-02-26 TLS208D1
Application Information
9 Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device.
9.1 Adjustable Version - TLS208D1xxV
Figure 9 Application Diagram Adjust able Version (e.g. TLS208D1LDV) Note: This is a very simplified example of an application circuit. The function must be verified in the real application. The resistor divider for a specific output voltage can be calculated according to Equation (2). The current IADJ, which flows into the ADJ-Pin, can be neglected, if Equation (3) is observed. VADJ is typically 0.8 V. (2) (3) The output capacitor should be sized according to the application needs in terms of load and line variations. Examples for loadsteps are given as typical performance graphs at Page 15. An optional capacitor CBYP can be placed in parallel to R1 to improve the PSRR, noise and loadstep response of this adjustable regulator. The capacitance depends strongly on the used resistance. Using Equation (4) a feasible capacitance value can be determined, the final capacitance is to be evaluated according to the applications need. (4) TLS208D1 is designed to work with ceramic output caps, but allows also the usage of other capacitors according to the allowed ESR range defined in the Functional Range. Furthermore there is a typ. performance graph on the stability of the device at Page 14. The adjustable voltage variants have an adjustable reset threshold can be adjusted individually by connecting a resistor divider (RADJ,1 & RADJ2) between the Q and RADJ. For the calculation of the resistor values please refer to Equation (1) in Chapter 8.1. There is no default internal reset threshold for the adjustable variants. In case the device is used to ge nerate output voltages lower than the VRADJ threshold, the reset function cannot be used to supervise the own output voltage. In this case it is recommended to connect the RADJ pin to a voltage higher than VRADJ (e.g. VI or VEN) in order to avoid additional current consumption due to the reset condition. VI I 220nF EN TLS208D1LDV From µC GND LOAD Regulated Output VoltageQ To µC Reset RO ADJ RADJ R1 RADJ,1 R2 RADJ,2 ESR C CQ Cin optional RRO,ext CBYP
Data Sheet 25 Rev. 1.0, 2015-02-26
9.2 Fixed Voltage Version - TLS208D1xxV33
Figure 10 Application Diagram Fixed Vo ltage Version (e.g. TLS208D1LDV33) Note: This is a very simplified example of an application circuit. The function must be verified in the real application. For the fixed voltage variants of the TLS208D1 the feedbac k pin FB must be connect ed to the output voltage to be regulated. This connection is mandatory to ensure proper regulation. The output capacitor should be sized according to the application needs in terms of load and line variations. Examples for loadsteps are given as typical performance graphs at Page 15. TLS208D1 is designed to work with ceramic output caps, but allows also the usage of other capacitors according to the allowed ESR range defined in the Functional Range. Furthermore there is a typ. performance graph on the stability of the device at Page 14. The fixed voltage variants have an default internal reset threshold (P_8.2.1) which can be used by connecting the RADJ pin to GND. Furthermore the reset threshold can be adjusted to lower values than the internal reset threshold by connecting a resistor divider (RRADJ,1 & RRADJ2) between the Q and RADJ. For the calculation of the resistor values please refer to Equation (1) in Chapter 8.1. VI I 220nF EN TLS208D1LDV33 From µC GND LOAD Regulated Output VoltageQ To µC Reset RO RADJ RADJ,1 RADJ,2 ESR C CQ Cin optional RRO,ext FB
Data Sheet 26 Rev. 1.0, 2015-02-26 TLS208D1 Package Outlines
10.1 Package Outlines PG -DSO-8 (Exposed Pad)
Figure 11 PG-DSO-8 (Exposed Pad) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). PG-DSO-8-27-PO V01 8x0.41±0.09 2) M0.2 DC A-B 1.27 C Stand Off -0.10.1 (1.45) 1.7 MAX. 0.08 Seating Plane C A B 3) JEDEC reference MS-012 variation BA 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Dambar protrusion shall be maximum 0.1 mm total in excess of lead width Bottom View ±0.23 ±0.22.65 0.2±0.2 D 6 M D 8x 0.64±0.25 3.9±0.11) 0.1 0.35 x 45˚ CD2 x +0.06 0.1 8˚ MAX. Index Marking For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Dimensions in mm
Data Sheet 27 Rev. 1.0, 2015-02-26
10.2 Package Outlines PG-TSON10
Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Pin 1 Marking Pin 1 Marking ±0.10.2 ±0.10.25 ±0.10.55 0.96 ±0.1 2.58±0.1 0 +0.05 ±0.1 ±0.1 0.25 0.5 ±0.13.3 ±0.13.3 ±0.1 1±0.1 0.71±0.1 1.63±0.1 1.48±0.1 Z 0.05 0.07 MIN. Z (4:1) For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Dimensions in mm
Data Sheet 28 Rev. 1.0, 2015-02-26 TLS208D1
Revision History
1.0 2015-02-26 Initial Data Sheet.
81726 Munich, Germany
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