TLIU04C1

TLIU04C1 AGERE | Alldatasheet

Document overview

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Technical content

Features

■ Selectable microprocessor or direct logic control modes. ■ Quad T1/E1 line interface. ■ Hardware and software reset options. ■ 3-state outputs. ■ 0.35 µm CMOS technology. ■ Compliant with: AT&T CB119 (10/79) Bellcore TR-54016 (89) TR-TSY -000170 (10/97) TR-TSY -000009 (5/86) GR-499-CORE (12/95) GR-253-CORE (12/95) ANSI T1.102 (93) T1.231 (93) T1.403 (95) ITU-T G.703 (88) G.704 (91) G.706 (91) G.732 (88) G.735-9 (88) G.775 (11/94) G.823-4 (3/93) G.826 (11/93) I.431 (3/93) ETSI TBR 12 (12/93) TBR 13 (1/96) ■ –40 °C to +85 °C operating temperature range. ■ Fine-pitch (12.5 mil) surface-mount package, 144-pin TQFP . ■ T ransmitter includes transmit encoder (B8ZS or HDB3), pulse shaping, and line driver. ■ Five pulse equalization settings for template com- pliance at DSX cross connect. ■ Receive includes equalization, digital clock and data recovery (immune to false lock), and receive decoder (B8ZS or HDB3). ■ CEPT/E1 interference immunity as required by G.703. ■ T ransmit jitter <0.02 UI. ■ Receive generated jitter <0.05 UI. ■ Jitter attenuator selectable for use in transmit or receive path. Jitter attenuation characteristics are data pattern independent. ■ For use with 100 Ω DS1 twisted-pair, 120 Ω E1 twisted-pair, and 75 Ω E1 coaxial cable. ■ Common part available for transmit/receive transformers. ■ Analog LOS alarm for signals less than –18 dB for greater than 1 ms or 10 bit symbol periods to 255 bit symbol periods (selectable). ■ Digital LOS alarm for 100 zeros (DS1) or 255 zeros (CEPT). ■ Diagnostic loopback modes. ■ Low power consumption.

Applications

■ T1/E1 network performance monitoring ■ SONET/SDH multiplexers ■ Asynchronous multiplexers (M13) ■ Digital access cross connects (DACs) ■ Channel banks ■ Digital radio base stations, remote wireless mod- ules ■ PBX interface

Advance Data Sheet, Rev. 2 TLIU04C1 Quad T1/E1 Line Interface April 1999 2 Lucent T echnologies Inc. Table of Contents Contents Page

Advance Data Sheet, Rev. 2 April 1999 TLIU04C1 Quad T1/E1 Line Interface 3Lucent Technologies Inc. Table of Contents (continued) Contents Page

Advance Data Sheet, Rev. 2 TLIU04C1 Quad T1/E1 Line Interface April 1999 4 Lucent T echnologies Inc. Table of Contents (continued) Contents Page

Advance Data Sheet, Rev. 2 TLIU04C1 Quad T1/E1 Line Interface April 1999 8 Lucent T echnologies Inc.

Description

The TLIU04C1 is a quad line interface containing four line transmit and receive channels for use in both North American (T1/DS1) and European (E1/CEPT) applica- tions. The line interface unit has the same functions as the Lucent T7698. The device can operate in either of two modes, chosen by the logic state of a control pin. A direct logic control mode provides the ability to define the architecture, ini- tiate loopbacks, and monitor alarms without connecting to a microprocessor by setting the logic levels on con- trol pins. The microprocessor mode uses a parallel microprocessor interface to allow the user to configure the device. The interface is compatible with many com- mercially available microprocessors. The block dia- grams of the microprocessor and direct logic modes are shown in Figure 2 and Figure 25, respectively. The block diagram of the line interface unit is shown in Figure 3 on page 19 (it is repeated as Figure 26). The line receiver performs clock and data recovery using a fully integrated digital phase-locked loop. This digital implementation prevents false lock conditions that are common when recovering sparse data patterns with analog phase-locked loops. Equalization circuitry in the receiver provides a high level of interference immunity. As an option, the raw sliced data (no retiming) can be output on the receive data pins. T ransmit equalization is implemented with low-impedance output drivers that provide shaped waveforms to the transformer, guaranteeing template conformance. The quad device will interface to the digi- tal cross connect (DSX) at lengths of up to 655 ft. for DS1 operation or to line impedances of 75 Ω or 120 Ω for CEPT operation. A selectable jitter attenuator may be placed in the receive signal path for low-bandwidth line-synchronous applications, or it may be placed in the transmit path for multiplexer applications where DS1/CEPT signals are demultiplexed from higher rate signals. The jitter atten- uator will perform the clock smoothing required on the resulting demultiplexed gapped clock. Microprocessor Mode Overview The TLIU04C1 device has the ability to operate in either a microprocessor mode or a direct logic control mode. The CMODE pin is used to determine the oper- ating mode. T o configure the device for microprocessor mode, the CMODE pin is pulled high. The device is equipped with a microprocessor interface that can operate with most commercially available microprocessors. Inputs MPMUX and MPMODE (pins 108 and 110) are used to configure this interface into one of four possible modes, as shown in T able 3. The MPMUX setting selects either a multiplexed 8-bit address/data bus (AD[7:0]) or a demultiplexed 4-bit address bus (A[3:0]) and an 8-bit data bus (AD[7:0]). The MPMODE setting selects the associated set of control signals required to access a set of registers within the device. When the microprocessor interface is configured to operate in the multiplexed address/data bus modes (MPMUX = 1), the user has access to an internal chip select function that allows the microprocessor to selec- tively read/write a specific TLIU04C1 in a multiple TLIU04C1 environment (see the Internal Chip Select Function section, page 16). The microprocessor interface can operate at speeds up to 16.384 MHz in interrupt-driven or polled mode with- out requiring any wait-states. For microprocessors operating at greater than 16.384 MHz, the RDY_DTACK output is used to introduce wait-states in the read/write cycles. In the interrupt-driven mode, one or more device alarms will assert the active-high INT output (pin 114) once per alarm activation. After the microprocessor reads the alarm status registers, the INT output will deassert. In the polled mode, however, the micropro- cessor monitors the various device alarm status by periodically reading the alarm status registers without the use of INT . A variety of LIU mask controls are avail- able for control of the INT pin.

Figure 1. TLIU04C1 Microprocessor Mode Pin Diagram

108 MPMUX

10 Lucent T echnologies Inc. Table 1. Pin Descriptions internal pull-ups or pull-downs is 50 kΩ , unless otherwise specified. or a primary line rate clock for XCLK (CLKS = 1). GND X[1—4] P Ground Reference for Line Drivers. ± 5% power supply on these pins. GND A[1—4] P Ground Reference for Analog Circuitry. (CDR = 0), this signal is the raw sliced negative data of the front end. indicate the occurrence of a bipolar violation in the received data.

Table 1. Pin Descriptions (continued) internal pull-ups or pull-downs is 50 kΩ , unless otherwise specified. this signal is the raw sliced positive data of the front end. mode (CDR = 1: register 5, bit 0), this signal is the received NRZ data. this signal is the transmit positive NRZ data from the terminal equipment. signal is the transmit NRZ data from the terminal equipment. 50 ppm) clock signal from the terminal equipment. and a combined read/write control. microprocessor interface to accept multiplexed address and data signals. demultiplexed (separate) address and data signals. microprocessor to initiate a write cycle. microprocessor to initiate a read cycle.

12 Lucent T echnologies Inc. internal pull-ups or pull-downs is 50 kΩ , unless otherwise specified. high to low, the address bus inputs are latched into the internal registers. high to low, the address bus inputs are latched into the internal registers. 100 kΩ pull-up is on this pin.

115 RDY_DT ACK

condition when CS (pin 113) is high. D P Ground Reference for Microprocessor Interface and Digital Circuitry. TLIU04C1 device requires a 5 V ± 5% power supply on these pins. jitter attenuation. This clock must be ungapped and free of jitter. tolerances must be ±20 ppm. An internal 100 kΩ pull-up is on this pin.

internal pull-ups or pull-downs is 50 kΩ , unless otherwise specified. controlled by the ICTMODE bit (register 4, bit 3). lower 4 bits (AD[3:0]) are used for the internal register addresses. A[3:0] must be externally tied low. 4.096 MHz for CEPT operation) to 16.384 MHz are supported.

14 Lucent T echnologies Inc. TTIP and TRING at the line interface. height falls below –18 dB, the ALOS pin is asserted high, and remains high until the signal rises above –14 dB. page 30). When a coding violations occurs, the BPV pin is asserted high. Table 2. System Interface Pin Mapping Table 3. Microprocessor Configuration Modes

the same set of pins in all modes. Table 4. MODE [1—4] Microprocessor Pin Definitions

111 RD _R/W R/W Input — Read/Write

112 ALE_AS AS Input — Address Strobe

113 CS CS Input Active-Low Chip Select

114 INT INT Output Active-High Interrupt

106 MPCLK MPCLK Input — Microprocessor Clock

111 RD _R/W RD Input Active-Low Read

112 ALE_AS ALE Input — Address Latch Enable

115 RDY_DT ACK RDY Output Active-High Ready

16 Lucent T echnologies Inc. outputs are required to be synchronous to MPCLK. Otherwise, the MPCLK pin must be connected to ground. selectively read or write a specific TLIU04C1 device in a system of up to eight devices on the microprocessor bus. microprocessor read/write request. The I/O timing specifications for the microprocessor interface are given on page 53. Table 5. Microprocessor Input Clock Specifications

T able 6 shows the register bank architecture. A numerical suffix appended to the bit name identifies the channel number. Bits shown in parentheses indicate the state forced during a reset condition. All registers must be configured by the user before the device can operate as required for the particular application. Table 6. LIU Register Bank

18 Lucent T echnologies Inc. Figure 2. TLIU04C1 Block Diagram, CMODE = 1 (Microprocessor Mode)

interfaces is shown. Pin names that apply to all four channels are followed by the designation [1—4]. Figure 3. Block Diagram of the Quad Line Interface Unit (Single Channel)

20 Lucent T echnologies Inc. XCLK, depending on the state of CLKS (pin 117). depending on the CDR and CODE configurations. Delay Values section, page 42). dent of input ones density on the line interface. register 5 (JAR, ACM, LOSSD) are ignored. CODE[1—4] bits for the respective channels. Note:Encoding and decoding are not independent. selects B8ZS/HDB3 encoding in the transmitter. Table 7. Register Map for CODE Bits on the RDA T A and BPV pins, respectively.

Advance Data Sheet, Rev. 2 April 1999 TLIU04C1 Quad T1/E1 Line Interface 21Lucent Technologies Inc. Microprocessor Mode (continued) Receiver Configuration Modes (continued) Alternate Logic Mode (ALM) The alternate logic mode (ALM) control bit (register 5, bit 5) selects the receive and transmit data polarity (i.e., active-high vs. active-low). If ALM = 0, the receiver cir- cuitry (and transmit input) assumes the data to be active-low polarity. If ALM = 1, the receiver circuitry (and transmit input) assumes the data to be active-high polarity. The ALM control is used in conjunction with the ACM control (register 5, bit 6) to determine the receive data retiming mode. Alternate Clock Mode (ACM) The alternate clock mode (ACM) control bit (register 5, bit 6) selects the positive or negative clock edge of the receive clock (RCLK) for receive data retiming. The ACM control is used in conjunction with ALM (register 5, bit 5) control to determine the receive data retiming modes. If ACM = 1, the receive data is retimed on the positive edge of the receive clock. If ACM = 0, the receive data is retimed on the negative edge of the receive clock. Note that this control does not affect the timing relationship for the transmitter inputs. See Figure 23 on page 59. RLIU Alarms Analog Loss of Signal (ALOS) Alarm. An analog sig- nal detector monitors the receive signal amplitude and reports its status in the analog loss of signal alarm bits in registers 0 and 1. Analog loss of signal is indicated (ALOS = 1) if the amplitude at the RRING and RTIP inputs drops more than approximately 18 dB below the nominal signal amplitude. The ALOS alarm condition will clear when the receive signal amplitude returns to greater than 14 dB below normal. In this way, the ALOS circuitry provides 4 dB of hysteresis to prevent alarm chattering. The ALOS alarm status bit will latch the alarm and remain set until being cleared by a read (clear on read). Upon the transition from ALOS = 0 to ALOS = 1, a microprocessor interrupt will be generated if the corresponding ALOS interrupt mask bit (MALOS; registers 2 and 3, bits 0 and 4), the channel mask bit (MASK; registers 6—9, bit 1), or the global mask bit (GMASK; register 4, bit 0) is not set. The time required to detect ALOS is selectable. When ALTIMER = 0 (register 12, bit 0), ALOS is declared between 1 ms and 2.6 ms after losing signal as required by I.431(3/93) and ETS-300-233 (5/94). If ALTIMER = 1, ALOS is declared between 10 and 255 bit symbol periods after losing signal as required by G.775 (11/95). The timing is derived from the XCLK clock. The detection time is independent of signal amplitude before the loss condition occurs. Normally, ALTIMER = 1 would be used only in CEPT mode since no T1/DS1 standards require this mode. In T1/DS1 mode, this bit should normally be zero. The behavior of the receiver LIU outputs under ALOS conditions is dependent on the loss shutdown control bit (LOSSD; register 5, bit 7) in conjunction with the receive alarm indication select control bit (RCVAIS; register 12, bit 1) as described in the Loss Shutdown (LOSSD) and Receiver AIS (RCVAIS) section on page 22. Digital Loss of Signal (DLOS) Alarm. A digital loss of signal (DLOS) detector guarantees the received signal quality as defined in the appropriate ANSI, Bellcore, and ITU standards. The digital loss of signal alarms are reported in the alarm status registers 0 and 1. During DS1 operation, digital loss of signal (DLOS = 1) is indi- cated if 100 or more consecutive zeros occur in the receive data stream. The DLOS condition is deacti- vated when the average ones density of at least 12.5% is received in 100 contiguous pulse positions. The DLOS alarm status bit will latch the alarm and remain set until being cleared by a read (clear on read). The LOSSTD control bit (register 4, bit 2) selects the con- formance protocols for the DLOS alarm indication per T able 8. Setting LOSSTD = 1 adds an additional con- straint that there are less than 15 consecutive zeros in the DS1 data stream before DLOS is deactivated.

22 Lucent T echnologies Inc. During CEPT operation, DLOS is indicated when 255 or more consecutive zeros occur in the receive data stream. pulse positions. LOSSTD has no effect in CEPT mode. bit 1) or the global mask bit (GMASK; register 4, bit 0) is not set. If LOSSD = 0 and RCVAIS = 0, the RND, RPD, and RCLK outputs will be unaffected by the DLOS alarm condition. forced to their inactive state (dependent on ALM state) and the RCLK free runs (based on XCLK frequency). quency, and the RCLK free runs. independent of LOSSD and RCVAIS settings. The LOSSD and RCVAIS behavior is summarized in Table 9. Table 8. Digital Loss of Signal Standard Select Table 9. LOSSD and RCVAIS Control Configurations (Not Valid During Loopback Modes)

1 X ALOS 0 if ALM = 1, 1 if ALM = 0 Free Runs

1 X DLOS 0 if ALM = 1, 1 if ALM = 0 Free Runs

24 Lucent T echnologies Inc. Figure 4. DS1/T1 Receiver Jitter Accommodation Without Jitter Attenuator

Figure 5. DS1/T1 Receiver Jitter Transfer Without Jitter Attenuator

Figure 6. CEPT/E1 Receiver Jitter Accommodation Without Jitter Attenuator

28 Lucent T echnologies Inc. Figure 7. CEPT/E1 Receiver Jitter Transfer Without Jitter Attenuator

Encoding (CODE) section, page 30). Table 12. Equalizer/Rate Control

• In DS1 mode, the distance to the DSX for 22 gauge PIC (ABAM) cable is specified. Use the maximum cable loss figures for other cable types.

In CEPT mode, equalization is specified for coaxial or twisted-pair cable. used in CEPT 120 Ω applications. attenuator is not selected, JA T = 0), is typically 5 nsp-p and will not exceed 0.02 UIp-p.

101 C E P T

111 N o t U s e d — — —

30 Lucent T echnologies Inc. CODE[1—4] bits for the respective channels. Note:Encoding and decoding are not independent. ter selects B8ZS/HDB3 decoding in the receiver. Table 13. Register Map for CODE Bits appearing on TTIP and TRING at the line interface. of clock from the pulse-width controller. clock is lost and no data can be driven onto the line. impedance state when this alarm condition is active. functional links and protect the device from damage.

transmitter is powered up in its normal operating mode. cleared by a read (clear on read). state or functionality of the signal path. not set and the GMASK bit (register 4, bit 0) is not set. Figure 8. DSX-1 Isolated Pulse Template Table 14. DSX-1 Pulse Template Corner Points

32 Lucent T echnologies Inc. During DS1 operation, the TTIP and TRING pins will perform as specified in Table 15.

1. In accordance with the line circuitry described (see Line Circuitry on page 50).
2. Measured in a 2 kHz band around the specified frequency.
3. Using Lucent transformer 2795B and components in Table 30.
4. Below the power at 772 kHz.

Table 15. DS1 Transmitter Specifications

1.544 MHz

34 Lucent T echnologies Inc. During CEPT operation, the transmitter tip/ring (TTIP/TRING pins) will perform as specified in T able 16. quency to within the transmit line rate specification. The jitter attenuator will smooth the gapped clock. jitter attenuator of this device outputs a maximum of 0.05 UIp-p intrinsic jitter. Table 16. CEPT Transmitter Specifications

• In accordance with the line circuitry described (see Line Circuitry on page 50), measured at the transformer secondary.

† Using Lucent transformer 2795D or 2795C and components in T able 30.

Advance Data Sheet, Rev. 2 April 1999 TLIU04C1 Quad T1/E1 Line Interface 35Lucent Technologies Inc. Microprocessor Mode (continued) Jitter Attenuator (continued) Jitter Transfer Function The jitter transfer function describes the amount of jitter that is transferred from the input to the output over a range of frequencies. The jitter attenuator exhibits a single-pole roll-off (20 dB/decade) jitter transfer characteristic that has no peaking and a nominal filter corner frequency (3 dB bandwidth) of less than 4 Hz for DS1 operation and approximately 10 Hz for CEPT operation. Optionally, a lower bandwidth of approximately 1.25 Hz can be selected in CEPT operation by setting JABW0 = 1 (register 12, bit 5) for systems desiring compliance with ETSI-TBR12/13 jitter attenuation requirements. When configured to meet ETSI-TBR12/13, the clock connected to the XCLK input must be ±20 ppm. For a given frequency, different jitter amplitudes will cause a slight variation in attenuation because of finite quantization effects. Jitter amplitudes of less than approximately 0.2 UI will have greater attenua- tion than the single-pole roll-off characteristic. The jitter transfer curve is independent of data patterns. T ypical jitter transfer curves of the jitter attenuator are given in Figure 11 and Figure 13. Jitter Accommodation The minimum jitter accommodation of the jitter attenuator occurs when the XCLK frequency and the input clock’s long-term average frequency are at their extreme frequency tolerances. When the jitter attenuator is used in the LIU transmit path, the minimum accommodation is 28 UIp-p at the highest jitter frequency of 15 kHz. T ypical receiver jitter accommodation curves including the jitter attenuator in the LIU receive path are given in Figure 10 and Figure 12. When the jitter attenuator is placed in the data path, a difference between the XCLK/16 frequency and the incoming line rate for receive applications, or the TCLK rate for transmit applications, will result in degraded low- frequency jitter accommodation performance. The peak-to-peak jitter accommodation (JAp-p) for frequencies from above the corner frequency of the jitter attenuator (fc) to approximately 100 Hz is given by the following equation: where: f data = 1.544 MHz for DS1 or 2.048 MHz for CEPT; for JABW0 = 0, fc = 3.8 Hz for DS1 or 10 Hz for CEPT, and for JABW0 = 1, fc = 1.25 Hz for CEPT; Δf xclk = XCLK tolerance in ppm; Δfdata = data tolerance in ppm. Note that for lower corner frequencies, the jitter accommodation is more sensitive to clock tolerance than for higher corner frequencies. When JABW0 = 1 and the jitter attenuator is used in the receive data path, the tolerance on XCLK should be tightened to ±20 ppm in order to meet the jitter accommodation requirements of TBR12/13 as given in G.823 for line data rates of ±50 ppm. JAp-p 64 2f xclkΔΔ fdata–() fdata 2πfc  UI=

Advance Data Sheet, Rev. 2 TLIU04C1 Quad T1/E1 Line Interface April 1999 36 Lucent T echnologies Inc. Microprocessor Mode (continued) Jitter Attenuator (continued) Jitter Attenuator Enable The jitter attenuator is selected using the JAR and JA T bits (register 5, bits 1 and 2) of the microprocessor interface. These control bits are global and affect all four channels unless a given channel is in the power- down mode (PWRDN = 1). Because there is only one attenuator function in the device, selection must be made between either the transmit or receive path. If both JA T and JAR are activated at the same time, the jitter attenuator will be disabled. Note that the power consumption increases slightly on a per-channel basis when the jitter attenuator is active. If jitter attenuation is selected, a valid XCLK (pin 46) signal must be available. Jitter Attenuator Receive Path Enable (JAR) When the jitter attenuator receive bit is set (JAR = 1), the attenuator is enabled in the receive data path between the clock/data recovery and the decoder (see Figure 3 on page 19). Under this condition, the jitter characteristics of the jitter attenuator apply for the receiver. The receive path will then exhibit the jitter characteristics shown in Figure 10 through Figure 13. If CDR = 0 (register 5, bit 0), the JAR bit is ignored because clock recovery will be disabled. Jitter Attenuator Transmit Path Enable (JAT) When the jitter attenuator transmit bit is set (JA T = 1), the attenuator is enabled in the transmit data path between the encoder and the pulse-width controller/ pulse equalizer (see Figure 3 on page 19). Under this condition, the jitter characteristics of the jitter attenuator apply for the transmitter. When JA T = 0, the encoder outputs bypass the disabled attenuator and directly enter the pulse-width controller/pulse equalizer. The transmit path will then pass all jitter from TCLK to line interface outputs TTIP/TRING.

Figure 10. DS1/T1 Receiver Jitter Accommodation with Jitter Attenuator

38 Lucent T echnologies Inc. Figure 11. DS1/T1 Jitter Transfer of the Jitter Attenuator

Figure 12. CEPT/E1 Receiver Jitter Accommodation with Jitter Attenuator

40 Lucent T echnologies Inc. Figure 13. CEPT/E1 Jitter Transfer of the Jitter Attenuator

3 and 4) as shown in T able 17. The locations of these loopbacks are illustrated in Figure 3 on page 19. Table 17. Loopback Control system and not the all-ones signal. † T ransmit AIS request is ignored. A full local loopback (FLLOOP) connects the transmit line driver input to the receiver analog front-end circuitry. DLOS monitors the looped data. transmit data, and XAIS inputs are ignored. Valid receive output data continues to be sent to the system interface. This loopback mode is very useful for isolating failures between systems. behavior of the LOTC and TDM alarms upon activation and deactivation of RLOOP . is enabled or disabled. The AIS signal can be transmitted without any effect on the looped signal.

Advance Data Sheet, Rev. 2 TLIU04C1 Quad T1/E1 Line Interface April 1999 42 Lucent T echnologies Inc. Microprocessor Mode (continued) Powerdown (PWRDN) Each line interface channel has an independent power- down mode controlled by PWRDN (registers 6—9, bit 0). This provides power savings for systems that use backup channels. If PWRDN = 1, the corresponding channel will be in a standby mode, consuming only a small amount of power. It is recommended that the alarm registers for the corresponding channel be masked with MASK = 1 (registers 6—9, bit 1) during powerdown mode. If a line interface channel in power- down mode needs to be placed into service, the chan- nel should be turned on (PWRDN = 0) approximately 5 ms before data is applied. Reset (RESET, SWRESET) The device provides both a hardware reset (RESET ; pin 44) and a software reset (SWRESET; register 4, bit 1) that are functionally equivalent. INT (pin 114) is also cleared. The writable microprocessor interface registers are not affected by reset, with the exception of bits in register 4 (see the Global Control Registers (0100, 0101) section). During a reset condition, data transmission will be interrupted. The reset condition is initiated by setting RESET = 0 or SWRESET = 1 for a minimum of 10 µs. After releasing the reset control (RESET = 1 or SWRESET = 0), the device will stay in the reset condition for approximately 2.7 ms to ensure stabilization of the PLL. After leaving the reset condition (with RESET = 1 or SWRESET = 0), the bits in register 4 will be reset and may need to be restored. Loss of XCLK Reference Clock (LOXC) The LOXC output (pin 45) is active when the XCLK ref- erence clock (pin 46) is absent. The LOXC flag is asserted a maximum of 16 µs after XCLK disappears, and deasserts immediately after detecting the first clock edge of XCLK. During the LOXC alarm condition, the clock recovery and jitter attenuator functions are automatically dis- abled. Therefore, if CDR = 1 and/or JAR = 1, the RCLK, RPD, RND, and DLOS outputs will be unknown. If CDR = 0, there will be no effect on the receiver. If the jitter attenuator is enabled in the transmit path (JA T = 1) dur- ing this alarm condition, then a Loss of T ransmit Clock alarm, LOTC = 1, will also be indicated. In-Circuit Testing and Driver High-Imped- ance State (ICT) The function of the ICT input (pin 43) is determined by the ICTMODE bit (register 4, bit 3). If ICTMODE = 0 and ICT is activated (ICT = 0), then all output buffers (TTIP , TRING, RCLK, RPD, RND, LOXC, RDY_DTACK , INT , AD[7:0]) are placed in a high-impedance state. For in-circuit testing, the RESET pin can be used to activate ICTMODE = 0 without having to write the bit. If ICTMODE = 1 and ICT = 0, then only the TTIP and TRING outputs of all channels will be placed in a high- impedance state. The TTIP and TRING outputs have a limiting high-impedance capability of approximately 8k Ω . LIU Delay Values The transmit coder has 5 UI delay whether it is in the path or not and whether it is B8ZS or HDB3. Its delay is only removed when in single-rail mode. The remainder of the transmit path has 4.6 UI delay. The receive decoder has 5 UI delay whether it is in the path or not and whether it is B8ZS or HDB3. Its delay is only removed when in single-rail mode or CDR = 0. The AFE (equalizer plus slicer) delay is nearly 0 UI delay. The jitter attenuator delay is nominally 33 UI but can be 2 UI—64 UI depending on the state. The DPLL used for timing recovery has 8 UI delay.

or mark on the positive or negative rail and a 0 with no pulse on either rails. This scheme is shown in Table 18. Table 18. AMI Encoding pulses, and no more than 15 zeros may be transmitted consecutively. Table 19. DS1 B8ZS Encoding The line code used for CEPT is described in ITU Rec. G.703 Section 6.1 as high-density bipolar of order 3 (HDB3). bipolar violations. An example is shown in T able 20. Table 20. ITU HDB3 Coding and DCPAT Binary Coding

44 Lucent T echnologies Inc. reserved). Register 13 is an index register which must contain the value 00 to access the other 15 LIU registers. other registers are read/write. Registers 2 and 3 contain the individual mask bits for the alarms in registers 0 and 1. Registers 4 and 5 are designated as the global control registers used to set up the functions for all four channels. ation. The following sections describe these registers in detail. the bit to remain set. These are read-only registers. *The numerical suffix identifies the channel number. Table 21. Alarm Registers 0, 4 ALOS[1—2] Analog loss of signal alarm for channels 1 and 2. 1, 5 DLOS[1—2] Digital loss of signal alarm for channels 1 and 2. 2, 6 TDM[1—2] Transmit driver monitor alarm for channels 1 and 2. 3, 7 LOTC[1—2] Loss of transmit clock alarm for channels 1 and 2. 0, 4 ALOS[3—4] Analog loss of signal alarm for channels 3 and 4. 1, 5 DLOS[3—4] Digital loss of signal alarm for channels 3 and 4. 2, 6 TDM[3—4] Transmit driver monitor alarm for channels 3 and 4. 3, 7 LOTC[3—4] Loss of transmit clock alarm for channels 3 and 4.

*The numerical suffix identifies the channel number. active-high. These are read/write registers. Table 22. Alarm Mask Registers 0, 4 MALOS[1—2] Mask analog loss of signal alarm for channels 1 and 2. 1, 5 MDLOS[1—2] Mask digital loss of signal alarm for channels 1 and 2. 2, 6 MTDM[1—2] Mask transmit driver monitor alarm for channels 1 and 2. 3, 7 MLOTC[1—2] Mask loss of transmit clock alarm for channels 1 and 2. 0, 4 MALOS[3—4] Mask analog loss of signal alarm for channels 3 and 4. 1, 5 MDLOS[3—4] Mask digital loss of signal alarm for channels 3 and 4. 2, 6 MTDM[3—4] Mask transmit driver monitor alarm for channels 3 and 4. 3, 7 MLOTC[3—4] Mask loss of transmit clock alarm for channels 3 and 4. Table 23. Global Control Register (0100)

0 GMASK The GMASK bit globally masks all the channel alarms when GMASK = 1, pre-

venting all the receiver and transmitter alarms from generating an interrupt. GMASK = 1 after a device reset. for device initialization through the microprocessor interface.

2 LOSSTD The LOSSTD bit selects the conformance protocol for the DLOS receiver

3 ICTMODE The ICTMODE bit changes the function of the ICT

high-impedance state. HIGHZ [1—4] = 1 after a device reset.

46 Lucent T echnologies Inc. PWRDN[1—4], MASK[1—4], and XAIS[1—4] bits are active-high. These are read/write registers. Control bits for zero substitution coding for channels 1—4 are listed in Table 26 and T able 27.

• A numerical suffix identifies the channel number.

† Channel suffix not shown in the description. Table 24. Global Control Register (0101) 0 CDR The CDR bit is used to enable and disable the clock/data recovery function.

1 JAR The JAR is used to enable and disable the jitter attenuator function in the

JAR or the JA T control bit can be set, but not both.

2 JA T The JA T is used to enable and disable the jitter attenuator function in the trans-

the JAR control bit should be set, but not both. used in conjunction with the DUAL bit and is valid only for single-rail operation. 4 DUAL The DUAL bit is used to select single or dual-rail mode of operation. mit and receive data retiming modes.

6 ACM The ACM bit selects the positive or negative edge of the receive clock (RCLK

determine the transmit and receive data retiming modes.

7 LOSSD The LOSSD bit selects the shutdown function for the digital loss of signal alarm

Table 25. Channel Configuration Registers (0110—1001) 0 PWRDN[1—4] The PWRDN bit powers down a channel when not used. 1 MASK[1—4] The MASK bit masks all interrupts for the channel.

2 XAIS[1—4] The XAIS bit enables transmission of an all-ones signal to the line inter-

The LOOPB and LOOP A bits select the channel loopback modes.

Advance Data Sheet, Rev. 2 April 1999 TLIU04C1 Quad T1/E1 Line Interface 47Lucent Technologies Inc. Microprocessor Mode (continued) Registers (continued) Channel Configuration and Control Registers (0110—1001, 1011, 1100) (continued) * A numerical suffix identifies the channel number. Table 26. Channel Configuration Register (1011)

• A numerical suffix identifies the channel number.

Channel Configuration Register (11) 0—3 — Reserved. Write to 0.

4 CODE4 The CODE4 bit selects B8ZS/HDB3 encoding (transmit) and decoding

(receive) in channel 4. 5 — Reserved. Write to 0.

6 CODE3 The CODE3 bit selects B8ZS/HDB3 encoding (transmit) and decoding

(receive) in channel 3. 7 — Reserved. Write to 0. Table 27. Control Register (1100) selects 1 ms—2.6 ms. ALTIMER = 1 selects 10 bit—255 bit periods.

1 RCVAIS The RCVAIS bit selects the shutdown function for the receiver during analog loss of

signal alarm (ALOS). RCVAIS operates in conjunction with the LOSSD bit. 2 PFLALM The PFLALM prevents the DLOS alarm from occurring during FLLOOP activation. 5 JABW0 The JABW0 bit selects the lower bandwidth jitter attenuator option in CEPT mode.

6 CODE2 The CODE2 bit selects B8ZS/HDB3 encoding (transmit) and decoding (receive) in

7 CODE1 The CODE1 bit selects B8ZS/HDB3 encoding (transmit) and decoding (receive) in

48 Lucent T echnologies Inc. must not be derived from any recovered line clock (i.e., from RCLK or any synthesized frequency of RCLK). for the device by CLKS (pin 117) and CLKM (pin 116). synthesizer operates in CEPT mode (2.048 MHz). The CLKM pin is ignored when CLKS = 0. Table 28. XCLK (16x, CLKS = 0) Timing Specifications meet the jitter accommodation requirements of TBR12/13 as given in G.823 for line data rates of ±50 ppm. specifications of 1.544 MHz ± 32 ppm for DS1 (T1) or 2.048 MHz ± 50 ppm for CEPT (E1).

specifications for XCLK using a primary rate reference clock are defined in Table 29. Table 29. XCLK (1x, CLKS = 1) Timing Specifications meet the jitter accommodation requirements of TBR12/13 as given in G.823 for line data rates of ±50 ppm. specifications of 1.544 MHz ± 32 ppm for DS1 (T1) or 2.048 MHz ± 50 ppm for CEPT (E1). bit 5 (RESTART) = 1) does not impact the clock synthesizer circuit.

50 Lucent T echnologies Inc. T able 30, based on the specific application. Figure 14. Line Termination Circuitry Table 30. Termination Components by Application Resistor tolerances are ±1%. T ransformer turns ratio tolerances are ±2%.

1. Use Lucent 2795B transformer.
2. For CEPT 75 Ω applications, Option 1 is recommended over Option 2 for lower device power dissipation. Option 2 increases power dissipa-
3. Use Lucent 2795D transformer.
4. Use Lucent 2795C transformer.
5. A ±5% tolerance is allowed for the transmit load termination, RL.

ings for extended periods can adversely affect device reliability. Table 31. Absolute Maximum Ratings using these circuit parameters. Table 32. ESD Threshold Voltage Table 33. Recommended Operating Conditions

Advance Data Sheet, Rev. 2 TLIU04C1 Quad T1/E1 Line Interface April 1999 52 Lucent T echnologies Inc. Microprocessor Mode (continued) Power Requirements The majority of the power used by the TLIU04C1 device is used by the line drivers. Therefore, the power is very dependent on data pattern and signal amplitude. The signal amplitude is a function of the transmit equalization in DS1 mode. When configured for greater cable loss, the signal amplitude is greater at the output drivers, and thus uses more power. For this reason, the power specification of T able 34 are given for various conditions. The typical specification is for a quasi-random signal and the maximum specification is for a mark (all ones) pattern. The power also varies somewhat for DS1 versus CEPT , so figures are given for both. Table 34. Power Consumption minus the power dissipated in the line. Table 35. Power Dissipation

Electrical Characteristics

DS1 with Max Eq. TBD TBD mW Parameter Power Unit Typ Max CEPT TBD TBD mW DS1 TBD TBD mW DS1 with Max Eq. TBD TBD mW Table 36. Logic Interface Characteristics sink no more than 20 µA. The device uses TTL input and output buffers; all buffers are CMOS-compatible.

The I/O timing specifications for the microprocessor interface are given in T able 37 and shown in Figures 15—22. cycle time is 200 ns for all device configurations. The read and write timing diagrams for all four microprocessor interface modes are shown in Figures 15—22. Table 37. Microprocessor Interface I/O Timing Specifications

54 Lucent T echnologies Inc. Table 37. Microprocessor Interface I/O Timing Specifications (continued) The read and write timing diagrams for all four microprocessor interface modes are shown in Figures 15—22.

Advance Data Sheet, Rev. 2 TLIU04C1 Quad T1/E1 Line Interface April 1999 60 Lucent T echnologies Inc. Direct Logic Control Mode Overview The TLIU04C1 device has the ability to operate in either a microprocessor mode or a direct logic control mode. The CMODE pin is used to determine the operating mode. To configure the device for direct logic control mode, the CMODE pin is pulled low. The device is equipped with direct logic control of the line interface configuration and options so that connection to a microprocessor is not required. Control of the various functions is accomplished by providing a logic high or low at the control pins. Functions such as E1/T1 modes, equalizer settings, diagnostic loopbacks, test modes, system interface timing and polarity, and standards compliance options are controlled in this manner. Alarm conditions are also indicated by output levels directly on device pins. Device Overview The TLIU04C1 is a four-channel device. The LIUs convert bipolar line data pulses into logic level terminal data, with options for timing for jitter attenuation, equalization, zero bit coding, loopbacks, and other functions.

Figure 24. TLIU04C1 Direct Logic Control Mode Pin Diagram

108 PWRDN4

62 Lucent T echnologies Inc. Table 39. Pin Descriptions internal pull-ups or pull-downs is 50 kΩ , unless otherwise specified. (CLKS = 0) or a primary line rate clock for XCLK (CLKS = 1). X[1—4] P 8 Ground Reference for Line Drivers. 5 V ± 5% power supply on these pins. GND A[1—4] P 4 Ground Reference for Analog Circuitry. (2.048 MHz ± 50 ppm) clock signal from the terminal equipment. dual = 1, this pin is used as the transmit data positive rail. the transmit data negative rail. line data. The duty cycle of RCLK is 50% ± 5%.

Table 39. Pin Descriptions (continued) internal pull-ups or pull-downs is 50 kΩ , unless otherwise specified. † Only one loopback mode can be enabled at a time. Enabling more than one results in all being deactivated. the receive data negative rail. threshold levels provides hysteresis to prevent alarm chatter. enabled), or the pulse-width controller clock. XAIS inserts the AIS signal on the transmit side. sections are exercised in this loopback.

64 Lucent T echnologies Inc. internal pull-ups or pull-downs is 50 kΩ , unless otherwise specified. transmit equalizers and DS1/CEPT mode. See T able 45. transmit equalizers and DS1/CEPT mode. See T able 45. transmit equalizers and DS1/CEPT mode. See T able 45. over a remote loopback if both are operated simultaneously.

39 RCVAIS

in conjunction with LOSSD. See T able 42.

42 LOSSD

function for the receiver during analog and digital loss of signal. LOSSD operates in conjunction with RCVAIS. See T able 42.

41 LOSSTD

density over 255 contiguous pulse positions (ITU-T G.775).

40 ALTIMER

internal pull-ups or pull-downs is 50 kΩ , unless otherwise specified. JA T = 1 and JAR = 1, the jitter attenuator is disabled.

110 JAR

JA T = 1 and JAR = 1, the jitter attenuator is disabled.

118 CMODE

38 JABW0

must be ±20 ppm. See T able 54.

114 ALM I

ALM = 1, the data is assumed to be active-high polarity.

115 ACM I

clock. (This does not affect transmit clock timing.) See Figure 38.

112 DUAL

rail mode and set (DUAL = 1) for dual-rail mode. held low for a minimum of 1 ms. DDD P6 Power Supply for Digital Circuitry. GND D P8 Ground Reference for Digital Circuitry.

66 Lucent T echnologies Inc. TTIP and TRING at the line interface. In single-rail mode only, TND is not needed for data and is used for controlling the B8ZS/HDB3 encoding/decoding. Table 40. System Interface Pin Mapping

Figure 25. TLIU04C1 Block Diagram, CMODE = 0 (Direct Logic Mode)

68 Lucent T echnologies Inc. interfaces is shown. Pin names that apply to all four channels are followed by the designation [1—4]. Figure 26. Block Diagram of the Quad Line Interface Unit (Single Channel)

Advance Data Sheet, Rev. 2 April 1999 TLIU04C1 Quad T1/E1 Line Interface 69Lucent Technologies Inc. Direct Logic Control Mode (continued) Data Recovery The receive line interface unit (RLIU) format is bipolar alternate mark inversion (AMI). The data rate tolerance is ±130 ppm (DS1) or ±80 ppm (CEPT). The receiver first restores the incoming data and detects analog loss of signal. Subsequent processing is optional and depends on the programmable device configuration established with the use of the direct logic control pins. The RLIU utilizes an equalizer to operate on line length with up to 15 dB of loss at 772 kHz (DS1) or 13 dB loss at 1.024 MHz (CEPT). The signal is then peak- detected and sliced to produce digital representations of the data. Clock and data recovery, digital loss of signal, jitter attenuation, and data decoding are performed. The receive digital output format is non-return-to-zero (NRZ) with selectable dual-rail or single-rail system interface. The clock is recovered by a digital phase-locked loop that uses XCLK as a reference to lock to the data rate component. Because the internal reference clock is a multiple of the received data rate, the RCLK output will always be a valid DS1/CEPT clock that eliminates false-lock conditions. During periods with no receive input signal, the free-run frequency of RCLK is defined to be either XCLK/16 or XCLK, depending on the state of CLKS. RCLK is always active with a duty-cycle cen- tered at 50%, deviating by no more than ±5%. Valid data is recovered within the first few bit periods after the application of XCLK. The delay of the data through the receive circuitry is approximately 1 to 14 bit peri- ods, depending on the CODE configurations. Additional delay is introduced if the jitter attenuator is selected for operation in the receive path (see the LIU Delay Values section, page 89). Jitter Accommodation and Jitter Transfer Without the Jitter Attenuator The RLIU is designed to accommodate large amounts of input jitter. The RLIU’s jitter performance exceeds the requirements shown in the RLIU Specifications tables (T able 43 and T able 44). Typical receiver perfor- mance without the jitter attenuator in the path is shown in Figure 27 through Figure 30. Jitter transfer is inde- pendent of input ones density on the line interface. Receiver Configuration Modes Clock/Data Recovery Mode (CDR) The clock/data recovery function in the receive path can be bypassed by setting the FLLOOP, RLOOP and DLLOOP pins for all channels low. Any other combina- tion of the twelve loopback pins results in the clock and data recovery function being enabled and providing a recovered clock (RCLK) with retimed data (RPD/ RDA TA, RND). If all twelve of the loopback pins are asserted, the clock and data recovery function is dis- abled, and the RZ data from the slicers is provided over RPD and RND to the system. In this mode, down- stream functions selected by the JAR, ACM, and LOSSD pins are ignored. Zero Substitution Decoding (CODE) When single-rail operation is selected with DUAL = 0, the B8ZS/HDB3 decoding can be selected. CODE[1— 4] pulled high selects the B8ZS/HDB3 decoding opera- tion for each individual channel. Note: Encoding and decoding are not independent. Selecting B8ZS/HDB3 decoding in the receiver selects B8ZS/HDB3 encoding in the transmitter. When decoding is selected for a given channel, decoded receive data and code violations appear on the RDA TA and BPV pins, respectively. If coding is not selected, receive data and any bipolar violations (such as two consecutive ones of the same polarity) appear on the RDA T A and BPV pins, respectively. Alternate Logic Mode (ALM) The alternate logic mode (ALM) control pin selects the receive and transmit data polarity (i.e., active-high vs. active-low). If ALM = 0, the receiver circuitry (and trans- mit input) assumes the data to be active-low polarity. If ALM = 1, the receiver circuitry (and transmit input) assumes the data to be active-high polarity. The ALM control is used in conjunction with the ACM control to determine the receive data retiming mode. Alternate Clock Mode (ACM) The alternate clock mode (ACM) control pin selects the positive or negative clock edge of the receive clock (RCLK) for receive data retiming. The ACM control is used in conjunction with the ALM control to determine the receive data retiming modes. If ACM = 1, the receive data is retimed on the positive edge of the receive clock. If ACM = 0, the receive data is retimed on the negative edge of the receive clock. Note that this control does not affect the timing relationship for the transmitter inputs. See Figure 38 on page 97.

70 Lucent T echnologies Inc. 4 dB of hysteresis to prevent alarm chattering. and Receiver AIS (RCVAIS) section on page 71. consecutive zeros occur in the receive data stream. Table 41. Digital Loss of Signal Standard Select

) or analog loss of signal (ALOS) alarm occurs. If LOSSD = 0 and RCVAIS = 0, the RND, RPD, and RCLK outputs will be unaffected by the DLOS alarm condition. (dependent on ALM state) and the RCLK free runs (based on XCLK frequency). an alarm indication signal (AIS, all ones) based on the free-running clock frequency, and the RCLK free runs. RND outputs are forced to their inactive state (dependent on ALM state) and the RCLK free runs. independent of LOSSD and RCVAIS settings. The LOSSD and RCVAIS behavior is summarized in Table 42. Table 42. LOSSD and RCVAIS Control Configurations (Not Valid During Loopback Modes)

00 A L O S

00 D L O S Normal Data Recovered Clock

01 A L O S AIS (all ones) Free Runs

01 D L O S AIS (all ones) Free Runs

Figure 27. DS1/T1 Receiver Jitter Accommodation Without Jitter Attenuator

74 Lucent T echnologies Inc. Figure 28. DS1/T1 Receiver Jitter Transfer Without Jitter Attenuator

76 Lucent T echnologies Inc. Figure 29. CEPT/E1 Receiver Jitter Accommodation Without Jitter Attenuator

Figure 30. CEPT/E1 Receiver Jitter Transfer Without Jitter Attenuator

78 Lucent T echnologies Inc. of the EQA, EQB, and EQC pins as described in T able 45. Table 45. Equalizer/Rate Control

• In DS1 mode, the distance to the DSX for 22 gauge PIC (ABAM) cable is specified. Use the maximum cable loss figures for other cable types.

In CEPT mode, equalization is specified for coaxial or twisted-pair cable. used in CEPT 120 Ω applications. attenuator is not selected, JA T = 0), is typically 5 nsp-p and will not exceed 0.02 UIp-p.

Advance Data Sheet, Rev. 2 April 1999 TLIU04C1 Quad T1/E1 Line Interface 79Lucent Technologies Inc. Direct Logic Control Mode (continued) Transmitter Configuration Modes Zero Substitution Encoding (CODE) Zero substitution B8ZS/HDB3 encoding can be acti- vated only in the single-rail system interface mode (DUAL = 0). The B8ZS/HDB3 encoding operation can be selected for individual channels independently by setting the CODE[1—4] pins high for the respective channels. Note:Encoding and decoding are not independent. Selecting B8ZS/HDB3 encoding in the transmit- ter selects B8ZS/HDB3 decoding in the receiver. When coding is selected for a given channel, data transmitted from the system interface on TDA T A will be B8ZS/HDB3 encoded before appearing on TTIP and TRING at the line interface. Alarm Indication Signal Generator (XAIS) When the transmit alarm indication signal control pin is set (XAIS[1—4] = 1) for a given channel, a continuous stream of bipolar ones is transmitted to the line inter- face. The TPD/TDA T A and TND inputs are ignored dur- ing this mode. The XAIS input is ignored when a remote loopback is selected using loopback control pin (RLOOP) transmitter alarms. The normal clock source for the AIS signal is TCLK. If TCLK is not available (loss of TCLK detected), then the AIS signal clock defaults to INTXCLK/16. INTXCLK is either XCLK, or 16x XCLK, depending on the state of the CLKS input pin. See Figure 26 on page 68, and CLKS in Table 39, Pin Descriptions, on page 62. Loss of Transmit Clock (LOTC) Alarm A loss of transmit clock alarm (LOTC[1—4]) is indicated if any of the clocks in the transmit path disappear. This includes loss of TCLK input, loss of RCLK during remote loopback, loss of jitter attenuator output clock (when enabled), or the loss of clock from the pulse- width controller. For all of these conditions, a core transmitter timing clock is lost and no data can be driven onto the line. Output drivers TTIP and TRING are placed in a high- impedance state when this alarm condition is active. The LOTC pin is asserted low between 3 µs and 16 µs after the clock disappears, and deasserts immediately after detecting the first clock edge. Transmit Driver Monitor (TDM) Alarm The transmit driver monitor detects two conditions: a nonfunctional link due to a fault on the primary of the transmit transformer, or periods of no data transmis- sion. The transmit driver monitor alarm (TDM[1—4]) is the ORed function of both faults and provides informa- tion about the integrity of the transmit signal path. The first monitoring function is provided to detect non- functional links and protect the device from damage. The alarm is set (TDM = 0) when one of the transmit- ter's line drivers (TTIP or TRING) is shorted to power supply or ground, or TTIP and TRING are shorted together. Under these conditions, internal circuitry protects the device from damage and excessive power supply cur- rent consumption by 3-stating the output drivers. The monitor detects faults on the transformer primary, but transformer secondary faults may not be detected. The monitor operates by comparing the line pulses with the transmit inputs. After 32 transmit clock cycles, the transmitter is powered up in its normal operating mode. The drivers attempt to correctly transmit the next data bit. If the error persists, TDM remains active to elimi- nate alarm chatter and the transmitter is internally pro- tected for another 32 transmit clock cycles. This process is repeated until the error condition is removed and the TDM alarm is deactivated. The second monitoring function is to indicate periods of no data transmission. The alarm is set (TDM = 0) when 32 consecutive zeros have been transmitted and the alarm condition is cleared on the detection of a single pulse. This alarm condition does not alter the state or functionality of the signal path.

80 Lucent T echnologies Inc. specified by ITU-T G.703 (not shown). Figure 31. DSX-1 Isolated Pulse Template Table 46. DSX-1 Pulse Template Corner Points During DS1 operation, the TTIP and TRING pins will perform as specified in Table 47.

1. In accordance with the line circuitry described (see Line Circuitry on page 94).
2. Measured in a 2 kHz band around the specified frequency.
3. Using Lucent transformer 2795B and components in Table 55.
4. Below the power at 772 kHz.

Table 47. DS1 Transmitter Specifications

82 Lucent T echnologies Inc. During CEPT operation, the transmitter tip/ring (TTIP/TRING pins) will perform as specified in T able 48. quency to within the transmit line rate specification. The jitter attenuator will smooth the gapped clock. jitter attenuator of this device outputs a maximum of 0.05 UIp-p intrinsic jitter. Table 48. CEPT Transmitter Specifications

• In accordance with the line circuitry described (see Line Circuitry on page 94), measured at the transformer secondary.

† Using Lucent transformer 2795D or 2795C and components in T able 30.

Advance Data Sheet, Rev. 2 April 1999 TLIU04C1 Quad T1/E1 Line Interface 83Lucent Technologies Inc. Direct Logic Control Mode (continued) Jitter Attenuator (continued) Jitter Transfer Function The jitter transfer function describes the amount of jitter that is transferred from the input to the output over a range of frequencies. The jitter attenuator exhibits a single-pole roll-off (20 dB/decade) jitter transfer characteristic that has no peaking and a nominal filter corner frequency (3 dB bandwidth) of less than 4 Hz for DS1 operation and approximately 10 Hz for CEPT operation. Optionally, a lower bandwidth of approximately 1.25 Hz can be selected in CEPT operation by setting JABW0 = 1 (register 12, bit 5) for systems desiring compliance with ETSI-TBR12/13 jitter attenuation requirements. When configured to meet ETSI-TBR12/13, the clock connected to the XCLK input must be ±20 ppm. For a given frequency, different jitter amplitudes will cause a slight variation in attenuation because of finite quantization effects. Jitter amplitudes of less than approximately 0.2 UI will have greater attenua- tion than the single-pole roll-off characteristic. The jitter transfer curve is independent of data patterns. T ypical jitter transfer curves of the jitter attenuator are given in Figure 34 and Figure 36. Jitter Accommodation The minimum jitter accommodation of the jitter attenuator occurs when the XCLK frequency and the input clock’s long-term average frequency are at their extreme frequency tolerances. When the jitter attenuator is used in the LIU transmit path, the minimum accommodation is 28 UIp-p at the highest jitter frequency of 15 kHz. T ypical receiver jitter accommodation curves including the jitter attenuator in the LIU receive path are given in Figure 33 and Figure 35. When the jitter attenuator is placed in the data path, a difference between the XCLK/16 frequency and the incoming line rate for receive applications, or the TCLK rate for transmit applications, will result in degraded low- frequency jitter accommodation performance. The peak-to-peak jitter accommodation (JAp-p) for frequencies from above the corner frequency of the jitter attenuator (fc) to approximately 100 Hz is given by the following equation: where: f data = 1.544 MHz for DS1 or 2.048 MHz for CEPT; for JABW0 = 0, fc = 3.8 Hz for DS1 or 10 Hz for CEPT, and for JABW0 = 1, fc = 1.25 Hz for CEPT; Δf xclk = XCLK tolerance in ppm; Δfdata = data tolerance in ppm. Note that for lower corner frequencies, the jitter accommodation is more sensitive to clock tolerance than for higher corner frequencies. When JABW0 = 1 and the jitter attenuator is used in the receive data path, the tolerance on XCLK should be tightened to ±20 ppm in order to meet the jitter accommodation requirements of TBR12/13 as given in G.823 for line data rates of ±50 ppm. JAp-p 64 2f xclkΔΔ fdata–() fdata 2πfc  UI=

Figure 33. DS1/T1 Receiver Jitter Accommodation with Jitter Attenuator

86 Lucent T echnologies Inc. Figure 34. DS1/T1 Jitter Transfer of the Jitter Attenuator

Figure 35. CEPT/E1 Receiver Jitter Accommodation with Jitter Attenuator

88 Lucent T echnologies Inc. Figure 36. CEPT/E1 Jitter Transfer of the Jitter Attenuator

Advance Data Sheet, Rev. 2 April 1999 TLIU04C1 Quad T1/E1 Line Interface 89Lucent Technologies Inc. Direct Logic Control Mode (continued) Loopbacks The device has three independent loopback paths that are activated using the FLLOOP, RLOOP, and DLLOOP pins. The locations of these loopbacks are illustrated in Figure 26. Full Local Loopback (FLLOOP A full local loopback (FLLOOP) connects the transmit line driver input to the receiver analog front-end cir- cuitry. Valid transmit output data continues to be sent to the network. If the transmit AIS (all-ones signal) is sent to the network, the looped data is not affected. The ALOS alarm continues to monitor the receive line inter- face signal while DLOS monitors the looped data. Remote Loopback (RLOOP ) A remote loopback (RLOOP) connects the recovered clock and retimed data to the transmitter at the system interface and sends the data back to the line. The receiver front end, clock/data recovery, encoder/ decoder (if enabled) jitter attenuator (if enabled), and transmit driver circuitry are all exercised during this loopback. The transmit clock, transmit data, and XAIS inputs are ignored. Valid receive output data continues to be sent to the system interface. This loopback mode is very useful for isolating failures between systems. Digital Local Loopback (DLLOOP A digital local loopback (DLLOOP) connects the trans- mit clock and data through the encoder/decoder pair to the receive clock and data output pins at the system interface. This loopback is operational if the encoder/ decoder pair is enabled or disabled. The AIS signal can be transmitted without any effect on the looped signal. Powerdown (PWRDN) Each line interface channel has an independent power- down mode controlled by PWRDN. This provides power savings for systems that use backup channels. If PWRDN = 1, the corresponding channel will be in a standby mode, consuming only a small amount of power. If a line interface channel in powerdown mode needs to be placed into service, the channel should be turned on (PWRDN = 0) approximately 5 ms before data is applied. Reset (RESET) The device provides a hardware reset (RESET ; pin 44). When the device is in reset, all signal-path and alarm monitor states are initialized to a known starting config- uration. During a reset condition, data transmission will be interrupted. The reset condition is initiated by setting RESET = 0 for a minimum of 10 µs. On coming out of the reset condi- tion (RESET = 1), a time of at least 2.7 ms should be allowed to ensure stabilization of the PLL. Loss of XCLK Reference Clock (LOXC) The LOXC output (pin 45) is active when the XCLK ref- erence clock (pin 46) is absent. The LOXC flag is asserted a maximum of 16 µs after XCLK disappears, and deasserts immediately after detecting the first clock edge of XCLK. During the LOXC alarm condition, the clock recovery and jitter attenuator functions are automatically dis- abled. Therefore, if CDR = 1 and/or JAR = 1, the RCLK, RPD, RND, and DLOS outputs will be unknown. If CDR = 0, there will be no effect on the receiver. If the jitter attenuator is enabled in the transmit path (JA T = 1) dur- ing this alarm condition, then a loss of transmit clock alarm, LOTC = 1, will also be indicated. In-Circuit Testing and Driver High-Imped- ance State (ICT) The affect of asserting the ICT input (pin 43) is that all output buffers (TTIP , TRING, RCLK, RPD, RND, LOXC, RDY_ DTACK , INT , AD[7:0]) are placed in a high-imped- ance state. The TTIP and TRING outputs have a limit- ing high-impedance capability of approximately 8 kΩ . LIU Delay Values The transmit coder has 5 UI delay whether it is in the path or not and whether it is B8ZS or HDB3. Its delay is only removed when in single-rail mode. The remainder of the transmit path has 4.6 UI delay. The receive decoder has 5 UI delay whether it is in the path or not and whether it is B8ZS or HDB3. Its delay is only removed when in single-rail mode or CDR = 0. The AFE (equalizer plus slicer) delay is nearly 0 UI delay. The jitter attenuator delay is nominally 33 UI but can be 2 UI—64 UI depending on the state. The DPLL used for timing recovery has 8 UI delay.

90 Lucent T echnologies Inc. or mark on the positive or negative rail and a 0 with no pulse on either rails. This scheme is shown in Table 49. Table 49. AMI Encoding pulses, and no more than 15 zeros may be transmitted consecutively. Table 50. DS1 B8ZS Encoding The line code used for CEPT is described in ITU Rec. G.703 Section 6.1 as high-density bipolar of order 3 (HDB3). violations are indicated as bipolar violations. An example is shown in T able 51. Table 51. ITU HDB3 Coding and DCPAT Binary Coding

must not be derived from any recovered line clock (i.e., from RCLK or any synthesized frequency of RCLK). for the device by CLKS (pin 117) and CLKM (pin 116). synthesizer operates in CEPT mode (2.048 MHz). The CLKM pin is ignored when CLKS = 0. Table 52. XCLK (16x, CLKS = 0) Timing Specifications meet the jitter accommodation requirements of TBR12/13 as given in G.823 for line data rates of ±50 ppm. specifications of 1.544 MHz ± 32 ppm for DS1 (T1) or 2.048 MHz ± 50 ppm for CEPT (E1).

92 Lucent T echnologies Inc. specifications for XCLK using a primary rate reference clock are defined in Table 53. Table 53. XCLK (1x, CLKS = 1) Timing Specifications meet the jitter accommodation requirements of TBR12/13 as given in G.823 for line data rates of ±50 ppm. specifications of 1.544 MHz ± 32 ppm for DS1 (T1) or 2.048 MHz ± 50 ppm for CEPT (E1). bit 5 (RESTART) = 1) does not impact the clock synthesizer circuit. The choices for XCLK are summarized in Table 54. Table 54. XCLK Specifications

• T o meet TBR 12/13 for jitter accommodation.

Advance Data Sheet, Rev. 2 April 1999 TLIU04C1 Quad T1/E1 Line Interface 93Lucent Technologies Inc. Direct Logic Control Mode (continued) Power Supply Bypassing External bypassing is required for all channels. A 1.0 µF capacitor must be connected between VDDX and GNDX. In addition, a 0.1 µF capacitor must be connected between VDDD and GNDD, and a 0.1 µF capacitor must be con- nected between VDDA and GNDA. Ground plane connections are required for GNDX, GNDD, and GNDA. Power plane connections are also required for VDDX and VDDD . The need to reduce high-frequency coupling into the ana- log supply (VDDA ) may require an inductive bead to be inserted between the power plane and the VDDA pin of every channel. Capacitors used for power supply bypassing should be placed as close as possible to the device pins for maximum effectiveness.

94 Lucent T echnologies Inc. T able 55, based on the specific application. Figure 37. Line Termination Circuitry Table 55. Termination Components by Application Resistor tolerances are ±1%. T ransformer turns ratio tolerances are ±2%.

1. Use Lucent 2795B transformer.
2. For CEPT 75 Ω applications, Option 1 is recommended over Option 2 for lower device power dissipation. Option 2 increases power dissipa-
3. Use Lucent 2795D transformer.
4. Use Lucent 2795C transformer.
5. A ±5% tolerance is allowed for the transmit load termination, RL.

ings for extended periods can adversely affect device reliability. Table 56. Absolute Maximum Ratings using these circuit parameters. Table 57. ESD Threshold Voltage Table 58. Recommended Operating Conditions

Advance Data Sheet, Rev. 2 TLIU04C1 Quad T1/E1 Line Interface April 1999 96 Lucent T echnologies Inc. Direct Logic Control Mode (continued) Power Requirements The majority of the power used by the TLIU04C1 device is used by the line drivers. Therefore, the power is very dependent on data pattern and signal amplitude. The signal amplitude is a function of the transmit equalization in DS1 mode. When configured for greater cable loss, the signal amplitude is greater at the output drivers, and thus uses more power. For this reason, the power specification of T able 59 are given for various conditions. The typical specification is for a quasi-random signal and the maximum specification is for a mark (all ones) pattern. The power also varies somewhat for DS1 versus CEPT , so figures are given for both. Table 59. Power Consumption minus the power dissipated in the line. Table 60. Power Dissipation DS1 with Max Eq. TBD TBD mW Parameter Power Unit Typ Max CEPT TBD TBD mW DS1 TBD TBD mW DS1 with Max Eq. TBD TBD mW Table 61. Logic Interface Characteristics sink no more than 20 µA. The device uses TTL input and output buffers; all buffers are CMOS-compatible.

• 100 pF allowed for microprocessor mode AD[7:0] (pins 75—82).

Advance Data Sheet, Rev. 2 TLIU04C1 Quad T1/E1 Line Interface April 1999 98 Lucent T echnologies Inc. Outline Diagram 144-Pin TQFP Dimensions are in millimeters. 5-3815(F)r.6 0.45/0.75 GAGE PLANE SEATING PLANE

1.00 REF

0.25 0.19/0.27 0.08 M 0.106/0.200

1.60 MAX

0.08

0.50 TYP

1.40 ± 0.05 0.05/0.15 DETAIL A DETAIL B PIN #1 IDENTIFIER ZONE 20.00 ± 0.20 22.00 ± 0.20 109144 37 72 108 20.00 ± 0.20 22.00 ± 0.20

Advance Data Sheet, Rev. 2 April 1999 TLIU04C1 Quad T1/E1 Line Interface 99Lucent Technologies Inc.

Ordering Information

Device Code Package Temperature Comcode (Ordering Number) TLIU04C1 144-Pin TQFP –40 °C to +85 °C 108420761

Advance Data Sheet, Rev. 2 T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor April 1999 For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, P A 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA P ACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent T echnologies (China) Co., Ltd., A-F2, 23/F , Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P . R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAP AN: Microelectronics Group, Lucent T echnologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, T okyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DA T ALINE: Tel. (44) 1189 324 299, FAX (44) 1189 328 148 T echnical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 45 77 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), IT AL Y: (39) 02 6608131 (Milan), SP AIN: (34) 1 807 1441 (Madrid) Lucent T echnologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Copyright © 1999 Lucent T echnologies Inc. All Rights Reserved April 1999 DS99-158T1E1-02 (Replaces DS99-158T1E1-01)