TLI5012

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V 0.41 TLI5012 GMR-Based Angular Sensor for Rotary Switches

81726 München, Germany

© 2008 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Target Data Sheet 3 V 0.41, 2009-03 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: sensors@infineon.com TLI5012 GMR-Based Angular Sensor Revision History: 2009-03, V 0.41 Previous Version: V0.4 Page Subjects (major cha nges since last revision) general Correction of typing errors gerneral Name of product type changed

7 Marking and Ordering Code added

12 Figure 4 updated

14 Figure 5 and figure 6 updated

15 Magnetic Induction reduced in Table 3; Storag e Temperature reduced in Table 2; Note added

16 Calculation of the Junction Temperature added

18 Figure 7 updated

19 Angle Delay Time with Prediction in Table 7 added; Figure 8 updated

20 Figure 9 and Figure 10 updated

42 Table 14, Thermal resistance added

Target Data Sheet 4 V 0.41, 2009-03

Target Data Sheet 6 V 0.41, 2009-03

Product Type Marking Ordering Code Package TLI5012 I5012 SP000634318 PG-DSO-8 TLI5012 Target Data Sheet 7 V 0.41, 2009-03

1 Product Description

1.1 Overview

The TLI5012 is a 360° angle sensor that detects the orientation of a magnetic field. This is achieved by measuring sine and cosine angle components with monolithic integrated Giant Magneto Resistance (iGMR) elements. An angle error smaller than 5° will be achieved over temperature. Data communications are accomplished with a bi-directional SSC Interface that is SPI compatible. The absolute angle value and other values are transmi tted via SSC or via a Pulse-Width-Modulation (PWM) Protocol. Also the sine and cosine raw values can be read out. These raw signals are digitally processed internally to calculate the angle orientation of the magnetic field (magnet). The TLI5012 is a precalibrated sensor. The calibration parameters are stored in laser fuses. At start-up the values of the fuses are written into Flip-Flops, where these values can be changed by the application specific parameters.

Target Data Sheet 8 V 0.41, 2009-03

1.2 Features

Giant Magneto Resistance (GMR)-based principle
Integrated magnetic field sensing for angle measurement
Full calibrated 0 - 360° angle measurement with revolution counter and angle speed measurement
Two separate highly accurate single bit SD-ADC
15 bit representation of absolute angle value on the output (resolution of 0.01°)
Bi-directional SSC Interface up to 8Mbit/s
Interfaces: SSC, PWM
0.25 µm CMOS technology
Temperature range: -40°C to 125°C (Junction Temperature)
ESD > 2kV (HBM)
Green package with lead-free (Pb-free) plating

1.3 Application Example

The TLI5012 GMR-Based Angular Sensor is designed for angular position sensing in industrial applications, such as:

Rotary Switch
General Angular Sensing

Target Data Sheet 9 V 0.41, 2009-03

2 Functional Description

2.1 General

The GMR sensor is implemented using vertical integr ation. This means that the GMR sensitive areas are integrated above the logic portion of the TLI5012 device. These GMR elements change their resistance depending on the direction of the magnetic field. Four individual GMR elements are connected to one Wheatstone Sensor Bridge. These GMR elements sense one of two components of the applied magnetic field:

X component, V x (cosine) or the
Y component, V y (sine) The advantage of a full-bridge structure is that the amplitude of the GMR signal is doubled and temperature effects cancel out each other. Figure 1 Sensitive Bridges of the GMR Sensor Note: In Figure 1, the arrows in the resistors symbolize the direction of the Reference Layer, which is used for the further explanation. The output signal of each bridge is only unambiguous over 180° between two maxima. Therefore two bridges are orientated orthogonally to each other to measure 360°. With the trigonometric function ARCTAN, the true 360° angle value can be calulated which is represented by the relation of X and Y signals. Because only the relative values influence the result, the absolute size of the two signals is of minor importance. Therefore, most influences to the amplitudes are compensated. VDDGNDADCX+ GMR Resistors ADCX-A D C Y+A D C Y- VX VY 90° NS

Target Data Sheet 10 V 0.41, 2009-03 Figure 2 Ideal Output of the GMR Sensor Bridges V Angle α 90° 180° 270° 360°0° VX (COS) Y Component (SIN) VY (SIN) VY VX X Component (COS)

Target Data Sheet 11 V 0.41, 2009-03

2.2 Pin Configuration

Figure 3 Pin Configuration (Top View)

2.3 Pin Description

Pin No. Symbol In/Out Function

1 CLK I External Clock (must be

output)

2 SCK I SSC Clock

3 CSQ I SSC Chip Select

4 DATA I/O SSC Data

O Interface A: PWM DD - Supply Voltage 7G N D - G r o u n d

8 IFB O Interface B:

connected via resistor to GND 1234

5678 Center of Sensitive

Target Data Sheet 12 V 0.41, 2009-03

2.4 Block Diagram

Figure 4 TLI5012 Block Diagram

2.5 Functional Block Description

2.5.1 Internal Power Supply

The internal stages of the TLI5012 are supplied with different voltage regulators.

GMR Voltage Regulator VRG
Analog Voltage Regulator VRA
Digital Voltage Regulato r VRD (derived from VRA) These regulators are directly connected to the supply voltage VDD.

2.5.2 Oscillator and PLL

The internal frequency oscillator feeds the Phase Locked Loop (PLL). Also the external clock (CLK) can be used therefore.

2.5.3 SD-ADC

The SD-ADCs transform the analog GMR-voltages and temperature-voltage into the digital domain. X GMR Y GMR SD- ADC SD- ADC Digital Signal Processing VRG VRA VRD SSC Interface Fuses Cordic IFA GND DATA SCK CLK CSQ TLI5012 VDD SD- ADC PWM Osc PLL IFB Temp CCU

Target Data Sheet 13 V 0.41, 2009-03

2.5.4 Digital Signal Processing Unit

The Digital Signal Processing Unit (DSPU) contains the:

Capture Compare Unit (CCU), which is used to generate the PWM signal
COordinate Rotation DIgital Computer (CORDIC), which contains the trigonometric function for angle calculation
Fuses, which contain the calibration parameters

2.5.5 Interfaces

Different Interfaces can be selected:

SSC Interface
P W M

Target Data Sheet 14 V 0.41, 2009-03

3 Specification

3.1 Application Circuit

The application circuit in Figure 5 and Figure 6 show the different communication possibilities of TLI5012. Figure 5 Application Circuit for TLI5012 with SSC and PWM Interface (using internal CLK) Figure 5 shows a basic block-diagram of the TLI5012 with PWM- Interface. Th is interface is selectable by connecting CLK to GND. Additionally to the PWM the SSC Interface could be used. Within the SSC- Interface the PWM mode is selectable between Push-Pull and Open Drain. Figure 6 Application Circuit for TLI5012 with only PWM Interface (using internal CLK) 100n IFA (PWM) DATA CSQ SCK CLK X GMR Y GMR SD- ADC SD- ADC Digital Signal Processing VRG VRA VRD SSC Interface Fuses Cordic PLL VDD (3.0 – 5.5V) TLI5012 SD- ADC PWM Osc Temp CCU 1 kΩ SSC PWM * recommended , e.g. 470 Ω IFB GND 10 kΩ IFB could be remain open or connected via 10 kΩ resistor to GND. 1 kΩ 100 n IFA (PWM) IFB GND DATA CSQ SCK CLK X GMR Y GMR SD- ADC SD- ADC Digital Signal Processing VRG VRA VRD SSC Interface Fuses Cordic PLL VDD (3.0 – 5.5V) TLI5012 SD - ADC PWM Osc Temp CCU 10 kΩ 1 kΩ 10 kΩ DATA and IFB could be remain open or connected via 10 kΩ resistor to GND .

Target Data Sheet 15 V 0.41, 2009-03

3.2 Absolute Maximum Ratings

Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the device.

3.3 Operating Range

The following operating conditions must not be exceeded in order to ensure correct operation of the TLE5012. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Note: The thermal resistances listed in Table 14 “Package Parameters” on Page 42 must be used to calculate the corresponding ambient temperature. Table 3 is valid for -40°C < TJ < 125°C. Table 2 Absolute Maximum Ratings Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Voltage on VDD pin respect to ground (VSS) VDD -0.5 - 6.5 V max 40 h/Lifetime Voltage on any pin respect to ground (VSS) VIN -0.5 - 6.5 V additionally VDD + 0.5 V may not be exceeded Junction Temperature TJ -40 - 125 °C - - 125 °C for 3000h not additive Magnetic Field Induction B - - 125 mT max. 5 min @ tA = 25°C Storage Temperature TST -40 - 125 °C Table 3 Operating Range Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Supply Voltage VDD 3.0 5.0 5.5 V 1) 1) Directly blocked with 100nF ceramic capacitor Output Current (DATA-Pad) IQ - - -25 mA PAD_DRV =’0x’, sink current2) 2) Max. current to GND over Open Drain Output - - -5 PAD_DRV =’10’, sink current2) - - -0.4 PAD_DRV =’11’, sink current2) Output Current (IFA / IFB-Pad) IQ - - -15 mA PAD_DRV =’0x’, sink current2) - - -5 PAD_DRV =’1x’, sink current2) Input Voltage VIN -0.3 - 5.5 V VDD + 0.3 V may not be exceeded Magnetic Induction BXY 30 - 50 mT in X/Y direction3) 3) Values refer to an homogenous magnetic field (B XY) without vertical magnetic induction (BZ = 0mT). Angle Range Ang 0 - 360 °

Target Data Sheet 16 V 0.41, 2009-03 Calculation of the Junction Temperature The total power dissipation PTOT of the chip increases its temperature above the ambient temperature. The power multiplied by the total thermal resistance RthJA (Junction to Ambient) leads to the final junction temperature. RthJA is the sum of the addition of the values of the two components Junction to Case and Case to Ambient. (1) Example (assuming no load on Vout): (2) For moulded sensors, the calculation with RthJC is more adequate. OUTOUTDDDDthJATOTthJA AJ thCAthJCthJA IVIVRPRT TTT RRR ∆+= ( (IDD, IOUT > 0, if direction is into IC ) [] [] [ ] KVAAVW KT mAI VV DD DD 90012.05150 =+×× =∆

Target Data Sheet 17 V 0.41, 2009-03

3.4 Characteristics

3.4.1 Electrical Parameters

The indicated electrical parameters apply to the full operating range, unless otherwise specified. The typical values correspond to a supply voltage V DD = 5.0 V and 25 °C, unless individually sp ecified. All other values correspond to -40 °C < TJ < 125°C.

3.4.2 ESD Protection

Table 4 Electrical Parameters Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Supply Current IDD - 12 13 mA POR Level VPOR 2.0 - 2.9 V Power On Reset POR Hysteresis VPORhy - 30 - mV Power On Time tPon - 4 5 ms VDD > VDDmin 1) Within “Power On Time” write access is not permitted Input Signal Low Level VL - - 0.3 VDD V Input Signal High Level VH 0.7 VDD - - V Pull-Up Current IPU -10 - -225 µA CSQ -10 - -150 DATA Pull-Down Current IPD 10 - 225 µA SCK 10 - 150 µA CLK, IFA, IFB Output Signal Low Level VOL - - 1 V DATA; IQ = - 25 mA (PAD_DRV=’0x’), IQ = - 5 mA (PAD_DRV=’10’), IQ = - 0.4 mA (PAD_DRV=’11’) - - 1 IFA,IFB; IQ = - 15 mA (PAD_DRV=’0x’), IQ = - 5 mA (PAD_DRV=’1x’) Table 5 ESD Protection Parameter Symbol Values Unit Notes min. max. ESD Voltage VHBM - ±2.0 kV Human Body Model1) 1) Human Body Model (HBM) according to: JEDEC EIA/JESD22-A114-B VSDM - ±0.5 kV Socketed Device Model2) 2) Socketed Device Model (SDM) ac cording to: ESD ASS.STD.DS5.3-93

Target Data Sheet 18 V 0.41, 2009-03

3.4.3 Angle Performance

After internal calculation the sensor has a remaining error, as shown in Table 6. The error value refers to BZ = 0mT and the operating conditions given in Table 3 “Operating Range” on Page 15. The overall angle error represents the relative angle error. This error describes the deviation to the reference line after zero angle definition.

3.4.4 Signal Processing

The signal path of the TLI5012 is depicted in Figure 7. It consists of the GMR-bridge, ADC, filter and angle calculation. Depending on the filter co nfiguration a different total delay time is achieved. Additional to this delay time, the delay time of the interface has to be consider ed. The delay time leads to an additional angle error at higher speeds. With enabling the prediction, the signal delay time will be reduced (Figure 8). Figure 7 TLI5012 Signal path At FIR_MD = 0 only raw values can be read out, due to the more time consuming angle calculation. Table 6 Angle Performance Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Overall Angle Error αErr - 0.71) 1) At 25°C, B =30 mT 5.0 ° including temperature drift2)3) 2) Including hysteresis error, caused by revolution direction change. 3) With magnetic setup in chip production (Fused Calibration Parameters); Relative error after zero angle definition. Table 7 Signal Processing Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Update Rate at Interface tupd - 21.3 - µs FIR_MD = 0 (only raw values)1)2) - 85.3 - FIR_MD = 2 (default)1)2) X GMR Y GMR SD- ADC SD- ADC Angle Calculation Filter Filter TLI5012 Microcontrolle r IF delt delIFt updt

Target Data Sheet 19 V 0.41, 2009-03 Figure 8 Delay of Sensor Output Angle Delay Time3) tdel - 60 70 µs FIR_MD = 11)2) - 80 95 FIR_MD = 21)2) - 120 140 FIR_MD = 31)2) Angle Delay Time with Prediction3) tdel - 20 30 µs FIR_MD = 1; PREDICT = 1 1)2) - 5 20 FIR_MD = 2; PREDICT = 1 1)2) - -40 -20 FIR_MD = 3; PREDICT = 1 1)2) Angle Noise NAngle - 0.11 - ° FIR_MD = 0, (1 Sigma)2) - 0.08 - FIR_MD = 1, (1 Sigma)2) - 0.05 - FIR_MD = 2, (1 Sigma)2) (default) - 0.04 - FIR_MD = 3, (1 Sigma)2) 1) depends on internal oscillator frequency variation 2) guaranteed by laboratory characterization 3) valid at constant rotation speed Table 7 Signal Processing Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. time Angle With Prediction Without Prediction tdel tupd Magnetic field direction

Target Data Sheet 20 V 0.41, 2009-03

3.5 Interfaces

3.5.1 Synchronous Serial Co mmunication (SSC) Interface

The 3-pin SSC Interface has a bi-directional push-pull data line, serial clock signal and chip select. The SSC Interface is designed to communicate with a microcontroller pear to pear for fast applications. Figure 9 SSC Configuration in Sensor-Slave Mode with Push-Pull Outputs (High Speed Application) Another possibility is a 3-pin SSC Interface with bidirecti onal open-drain data line, serial cloc k signal and chip select. This setup is designed to commu nicate with a microcontroller in a bus system, together with other SSC slaves (e.g. two TLI5012 for redundancy reasons). This mode can be activated using bit SSC_OD. Figure 10 SSC Configuration in Sensor-Slave Mode and Open Drain (Safe Bus Systems) SSC Communication for pear to pear Data Transmission between TLI5012 and µC Shift Reg. Shift Reg. Clock Gen. DATA MRST MTSR SCK SCK (SSC Slave) TLI5012 µC (SSC Master) CSQ CSQ **) EN EN *) opional , e.g. 100 Ω **) opional , e.g. ≥ 470 Ω Shift Reg. Shift Reg. Clock Gen. DATA MRST MTSR SCK SCK (SSC Slave) TLI5012 µC (SSC Master) CSQ CSQ typ. 1kΩ *) opional , e.g. 100 Ω

Target Data Sheet 21 V 0.41, 2009-03

3.5.1.1 SSC Timing Definition

SSC Inactive Time (CSoff) The SSC inactive time defines the delay time after a transfer before the TLE5012 can be selected again. Table 8 SSC Push-Pull Timing Specification Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. SSC Baud Rate fSSC - 8.0 - Mbit/s CSQ Setup Time tCSs 105 - - ns CSQ Hold Time tCSh 105 - - ns CSQ off tCSoff 600 - - ns SSC inactive time SCK Period tSCKp 120 125 - ns SCK High tSCKh 40 - - ns SCK Low tSCKl 30 - - ns DATA Setup Time tDATAs 25 - - ns DATA Hold Time tDATAh 40 - - ns Write Read Delay twr_delay 130 - - ns Table 9 SSC Open Drain Timing Specification Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. SSC Baud Rate fSSC - 2.0 - Mbit/s Pull-up Resistor = 1kΩ CSQ Setup Time tCSs 300 - - ns CSQ Hold Time tCSh 400 - - ns CSQ off tCSoff 600 - - ns SSC inactive time SCK Period tSCKp 500 - - ns SCK High tSCKh - 190 - ns SCK tCSs tSCKp tSCKh tCSh CSQ tSCKl tCSoff tDATAs DATA tDATAh

Target Data Sheet 22 V 0.41, 2009-03

3.5.1.2 SSC Data Transfer

The SSC data transfer is word aligned. The following transfer words are possible:

Command word (to access and change operating modes of the TLI5012)
Data words (any data transferred in any direction)
Safety word (confirms the data transfer and provide status information) Figure 12 SSC Data Transfer (Data Read Example) Figure 13 SSC Data Transfer (Data Write Example) SCK Low tSCKl - 190 - ns DATA Setup Time tDATAs 25 - - ns DATA Hold Time tDATAh 40 - - ns Write Read Delay twr_delay 130 - - ns Table 9 SSC Open Drain Timing Specification (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. COMMAND READ Data 1 READ Data 2 SAFETY-WORD SSC-Master is driving DATA SSC-Slave is driving DATA twr_de lay COMMAND WRITE Data 1 SAFETY -WORD SSC-Master is driving DATA SSC-Slave is driving DATA twr_delay

Target Data Sheet 23 V 0.41, 2009-03 Command Word TheTLI5012 is controlled by a command word. It is sent first at every data transmission. Safety Word The safety word contains following bits: Table 10 Structure of the Command Word Name Bits Description RW [15] Read - Write 0:Write 1:Read Lock [14..11] 4 bit Lock Value 0x00: Default Operating Access 0x02: Config- Access UPD [10] Update-Register Access 0: Access to current values 1: Access to updated values ADDR [9..4] 6 bit Address ND [3..0] 4 bit Number of Data-Words Table 11 Structure of the Safety Word Name Bits Description STAT Chip and Interface Status [15] Indication of Chip-Reset (resets after readout) via SSC 0: No reset 1: Reset occurred Reset: 0B 0: No error 1: Error occurred (S_VR; S_DSPU; S_OV; S_XYOL: S_MAGOL; S_ADCM) [13] Interface Access Error (access to wrong address; wrong lock) 0: No error 1: Error occurred [12] Valid Angle Value (no system error; no interface error; NO_GMR_A = ’0’; NO_GMR_XY=’0’) 0: Angle value valid 1: Angle value invalid RESP [11..8] Sensor Number Response Indicator The sensor no. bit is pulled low and the other bits are high. CRC [7..0] Cyclic Redundancy Check (CRC)

Target Data Sheet 25 V 0.41, 2009-03

3.5.1.3 Registers Chapter

This chapter defines the registers of the TLI5012 . It also defines the read/write access rights of the specific registers. Table 12 identifies the values with symbols. Access to the registers is accomplished via the SSC Interface. The register is addressed wordwise. Table 12 Registers Overview Register Short Name Register Long Name Offset Address Page Number Registers Chapter, TLI5012 Register STAT Status Register 00H 26 ACSTAT Activation Status Register 01H 28 AVAL Angle Value Register 02H 29 ASPD Angle Speed Register 03H 30 AREV Angle Revolution Register 04H 30 FSYNC Frame Synchronization Register 05H 31 MOD_1 Interface Mode1 Register 06H 32 SIL SIL Register 07H 33 MOD_2 Interface Mode2 Register 08H 34 MOD_3 Interface Mode3 Register 09H 35 OFFX Offset X 0AH 36 OFFY Offset Y 0BH 36 SYNCH Synchronicity 0CH 37 IFAB IFAB Register 0DH 37 MOD_4 Interface Mode4 Register 0EH 38 TCO_Y Temperature Coeffizient Register 0FH 39 ADC_X X-raw value 10H 39 ADC_Y Y-raw value 11H 40

Target Data Sheet 26 V 0.41, 2009-03

3.5.1.3.1 TLI5012 Register

Field Bits Type Description RD_ST 15 r Read Status 0B after readout 1B status values changed Reset: 1B S_NR 14:13 r Slave Number Reset: 00B NO_GMR_A 12 r No GMR Angle Value 0B valid GMR angle value on the interface 1B no valid GMR angle value on the interface Reset: 0B NO_GMR_XY 11 r No GMR XY Values 0B valid GMR_XY values on the interface 1B no valid GMR_XY values on the interface Reset: 0B S_ROM 10 r Status ROM 0B after readout, CRC ok 1B CRC fail or running Reset: 0B S_ADCT 9 r Status ADC-Test 0B after readout 1B Test vectors out of limit Reset: 0B S_MAGOL 7 r Status Magnitude Out of Limit 0B after readout 1B GMR-magnitude out of limit (>23230 digits) Reset: 0B U 5'B67 U 6B15 U 12B*05B U 12B*05B U 6B520 U 6B$'&7 5HV U 6B0$*2/ U 6B;<2/ U 6B29 U 6B'638 U 6B)86( U 6B95 U 6B:' U 6B567

Target Data Sheet 27 V 0.41, 2009-03 S_XYOL 6 r Status X,Y Data Out of Limit 0B after readout 1B X,Y data out of limit (>23230 digits) Reset: 0B S_OV 5 r Status Overflow 0B after readout 1B DSPU overflow occurred Reset: 0B S_DSPU 4 r Status Digital Signal Processing Unit 0B after readout 1B DSPU self test not ok, or selftest is running Reset: 0B S_FUSE 3 r Status Fuse CRC 0B after readout, Fuse CRC ok 1B Fuse CRC fail Reset: 0B S_VR 2 r Status Voltage Regulator 0B after readout 1B VDD overvoltage; VDD undervoltage; VDD-off; GND- off; or VOVG; VOVA; VOVD too high Reset: 0B S_WD 1 r Status Watchdog 0B after chip reset 1B watchdog counter expired Reset: 0B S_RST 0 r Status Reset 0B after readout 1B indication of power-up, short power-break or active reset Reset: 1B Field Bits Type Description

Target Data Sheet 28 V 0.41, 2009-03 Activation Status Register ACSTAT Offset Reset Value Activation Status Register 01H 5CEEH Field Bits Type Description Res 15:10 Reserved Reset: 010111B AS_ADCT 9 rw Enable GMR Vector check Reset: 0B AS_VEC_MAG 7 rw Activation of ADC-Redundancy-BIST 0B after execution 1B activation of redundancy BIST Reset: 1B AS_VEC_XY 6 rw Activation of ADC-BIST 0B after execution 1B activation of BIST Reset: 1B AS_OV 5 rw Enable of DSPU Overflow Check Reset: 1B AS_DSPU 4 rw Activation DSPU BIST 0B after execution 1B activation of DSPU BIST Reset: 0B AS_FUSE 3 rw Activation Fuse CRC 0B after execution 1B activation of Fuse CRC Reset: 1B AS_VR 2 rw Enable Voltage Regulator Check Reset: 1B AS_WD 1 rw Enable DSPU Watchdog-HW-Reset Reset: 1B 5HV UZ $6B$'&7 5HV UZ $6B9(&B 0$* UZ $6B9(&B UZ $6B29 UZ $6B'638 UZ $6B)86( UZ $6B95 UZ $6B:' UZ $6B567

Target Data Sheet 29 V 0.41, 2009-03 Angle Value Register AS_RST 0 rw Activation of Hardware Reset Activation occurs after CSQ switches from ’0’ to ’1’ after SSC transfer. 0B after execution 1B activation of HW Reset Reset: 0B AVAL Offset Reset Value Angle Value Register 02H 8000H Field Bits Type Description RD_AV 15 r Read Status, Angle Value 0B after readout 1B new angle value (ANG_VAL) present Reset: 1B ANG_VAL 14:0 r Calculated Angle Value (ANG_RANGE = 0x080) 4000H -180° 0000H 0° 3FFFH +179.99° Reset: 0H Field Bits Type Description U 5'B$9 U $1*B9$/ U $1*B9$/

Target Data Sheet 30 V 0.41, 2009-03 Angle Speed Register Angle Revolution Register ASPD Offset Reset Value Angle Speed Register 03H 8000H Field Bits Type Description RD_AS 15 r Read Status, Angle Speed 0B after readout 1B new angle speed value (ANG_SPD) present Reset: 1B ANG_SPD 14:0 r Calculated Angle Speed Difference between two consecutive angle values. Reset: 0H AREV Offset Reset Value Angle Revolution Register 04H 8000H U 5'B$6 U $1*B63' U $1*B63' U 5'B5(9 UZ )&17 U 5(92/ U 5(92/

Target Data Sheet 31 V 0.41, 2009-03 Frame Synchronization Register Field Bits Type Description RD_REV 15 r Read Status, Revolution 0B after readout 1B new value (REVOL) present Reset: 1B FCNT 14:9 rw Frame Counter (unsigned 6 bit value) Counts every new angle value Reset: 0H REVOL 8:0 r Number of Revolutions (signed 9 bit value) Reset: 0H FSYNC Offset Reset Value Frame Synchronization Register 05H 0000H Field Bits Type Description FSYNC 15:9 rw Frame Synchronization Counter Value Sub counter within one frame. Reset: 0H UZ )6<1& 5HV 5HV

Target Data Sheet 32 V 0.41, 2009-03 Interface Mode1 Register MOD_1 Offset Reset Value Interface Mode1 Register 06H 8001H Field Bits Type Description FIR_MD 15:14 rw Filter Decimation Setting 00B 21.3µs 01B 42.7µs 10B 85.3µs 11B 170.6µs Reset: 10B CLK_SEL 4 rw Clock Source Select 0B internal oscillator 1B external 4MHz clock Reset: 0B SSC_OD 3 rw SSC-Interface 0B Push-Pull 1B Open Drain Reset: 0B DSPU_HOLD 2 rw Hold DSPU Operation 0B DSPU in normal schedule operation 1B DSPU is on hold Reset: 0B Res 1:0 Reserved Reset: 01B UZ ),5B0' 5HV 5HV UZ &/.B6(/ UZ 66&B2' UZ '638B+2 5HV

Target Data Sheet 33 V 0.41, 2009-03 SIL Register SIL Offset Reset Value SIL Register 07H 0000H Field Bits Type Description FILT_PAR 15 rw Filter Parallel 0B filter parallel disabled 1B filter parallel enabled (source: X-value) Reset: 0B FILT_INV 14 rw Filter Inverted 0B filter inverted disabled 1B filter inverted enabled Reset: 0B FUSE_REL 10 rw Fuse Reload 0B fuse reload disabled 1B fuse parameters reloaded to DSPU at next cycle start Reset: 0B ADCTV_EN 6 rw ADC-Test vectors 0B ADC-Test vectors disabled 1B ADC-Test vectors enabled Reset: 0B ADCTV_Y 5:3 rw Test vector Y 000B 0V 001B +70% 010B +100% 011B +Overflow 101B -70% 110B -100% 111B -Overflow Reset: 000B UZ ),/7B3$ UZ ),/7B,1 5HV UZ )86(B5( 5HV 5HV UZ $'&79B( UZ $'&79B< UZ $'&79B;

Target Data Sheet 34 V 0.41, 2009-03 Interface Mode2 Register ADCTV_X 2:0 rw Test vector X 000B 0V 001B +70% 010B +100% 011B +OV 101B -70% 110B -100% 111B -OV Reset: 000B MOD_2 Offset Reset Value Interface Mode2 Register 08H 0800H Field Bits Type Description ANG_RANGE 14:4 rw Angle Range Angle Range [°] = 360° * (27 / ANG_RANGE) 200H represents 90° 080H represents 360° Reset: 080H ANG_DIR 3 rw Angle Direction 0B counterclockwise rotation of magnet° 1B clockwise rotation of magnet Reset: 0B Field Bits Type Description 5HV UZ $1*B5$1*( UZ $1*B5$1*( UZ $1*B',5 5HV

Target Data Sheet 35 V 0.41, 2009-03 Interface Mode3 Register MOD_3 Offset Reset Value Interface Mode3 Register 09H 0000H Field Bits Type Description ANG_BASE 15:4 rw Angle Base 800H -180° 000H 0° 001H 0.00879° 7FFH +179.912° Reset: 0H SPIKEF 3 rw Analog Spike Filters of Input Pads 0B spike filter disabled 1B spike filter enabled Reset: 0B PAD_DRV 1:0 rw Configuration of Pad-Driver 00B IFA/IFB: strong driver, DATA: strong driver, fast edge 01B IFA/IFB: strong driver, DATA: strong driver, slow edge 10B IFA/IFB: weak driver, DATA: medium driver, fast edge 11B IFA/IFB: weak driver, DATA: weak driver, slow edge Reset: 00B UZ $1*B%$6( UZ $1*B%$6( UZ 63,.() 5HV UZ 3$'B'59

Target Data Sheet 36 V 0.41, 2009-03 Offset X Register Offset Y Register OFFX Offset Reset Value Offset X 0AH 0000H Field Bits Type Description X_OFFSET 15:4 rw Offset Correction of X-value Reset: 0H OFFY Offset Reset Value Offset Y 0BH 0000H Field Bits Type Description Y_OFFSET 15:4 rw Offset Correction of Y-value Reset: 0H UZ ;B2))6(7 UZ ;B2))6(7 5HV UZ <B2))6(7 UZ <B2))6(7 5HV

Target Data Sheet 37 V 0.41, 2009-03 Synchronicity Register IFAB Register SYNCH Offset Reset Value Synchronicity 0CH 0000H Field Bits Type Description SYNCH 15:4 rw Amplitude Synchronicity +2047D 112.494% 0D 100% -2047D 87.500% Reset: 0H IFAB Offset Reset Value IFAB Register 0DH 0004H Field Bits Type Description ORTHO 15:4 rw Orthogonality Correction of X and Y Components +2047D 11.2445° 0D 0° -2047D -11.2500° Reset: 0H UZ 6<1&+ UZ 6<1&+ 5HV UZ 257+2 UZ 257+2 5HV UZ ,)$%B2' 5HV

Target Data Sheet 38 V 0.41, 2009-03 Interface Mode4 Register IFAB_OD 2 rw IFA & IFB Open Drain 0B Push-Pull 1B Open Drain Reset: 1B MOD_4 Offset Reset Value Interface Mode4 Register 0EH 0011H Field Bits Type Description TCO_X_T 15:9 rw Offset Temperature Coefficient for X-Component Reset: 0H IFAB_RES 4:3 rw IFAB Resolution 00B 12bit = 0.088° (244Hz) 01B 11bit = 0.176° (488Hz) 10B 10bit = 0.352° (977Hz) 11B 9bit = 0.703° (1953Hz) Reset: 10B IF_MD 2:0 rw Interface Mode PWM if CLK is connected to GND at startup. Note: Not mentioned combinations are not allowed 001B SSC mode; PWM Reset: 001B Field Bits Type Description UZ 7&2B;B7 5HV 5HV UZ ,)$%B5(6 UZ ,)B0'

Target Data Sheet 39 V 0.41, 2009-03 Temperature Coeffizient Register X-raw Value Register TCO_Y Offset Reset Value Temperature Coeffizient Register 0FH 0000H Field Bits Type Description TCO_Y_T 15:9 rw Offset Temperature Coefficient for Y-Component Reset: 0H CRC_PAR 7:0 rw CRC of Parameters CRC of parameters from address 08H to 0FH Reset: 0H ADC_X Offset Reset Value X-raw value 10H 0000H Field Bits Type Description ADC_X 15:0 r ADC value of X-GMR Read out of this register will update ADC_Y Reset: 0H UZ 7&2B<B7 5HV UZ &5&B3$5 U $'&B;

Target Data Sheet 40 V 0.41, 2009-03 Y-raw Value Register

3.5.2 Pulse Width Modulation Interface

The P ulse Width Modulation ( PWM) update rate can be programmed within the register 0E H (IFAB_RES) in following steps:

0.25 kHz with 12 bit resolution
0.5 kHz with 11 bit resolution
1.0 kHz with 10 bit resolution (default)
2.0 kHz with 9 bit resolution PWM uses a square wave with constant frequency whose du ty cycle is modulated resulting in an average value of the waveform. Figure 16 shows the principle behavior of a PWM with different duty cycles and the definition of timing values. The duty cycle of a PWM is defined by following general formulas: (3) The range between 0 - 6.25% and 93.75 - 100% is used on ly for diagnostic purposes. More details are given in Table 13. ADC_Y Offset Reset Value Y-raw value 11H 0000H Field Bits Type Description ADC_Y 15:0 r ADC value of Y-GMR Updated when ADC_X or ADC_y is read. Reset: 0H U $'&B< PWM PWM offonPWM PWM on tf ttt t tCycleDuty

Target Data Sheet 41 V 0.41, 2009-03 Figure 16 Typical Example for a PWM Signal Table 13 PWM Interface Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. PWM Output Frequency fPWM 244 - 1953 Hz selectable by IFAB_RES1) 1) f PWM = (fDIG * 2IFAB_RES) / (24 * 4096) Output Duty Cycle Range DYPWM 6.25 - 93.75 % Absolute Angle - 2 - % Electrical Error (S_RST; S_VR) - 98 - % System Error (S_FUSE; S_OV; S_XYOL; S_MAGOL; S_ADCT) 0 - 1 % Short to GND 99 - 100 % Short to VDD, Power-Loss PWM Period Variation tPWMvar -5 - 5 % 2) 2) depends on internal oscillator frequency variation tON ‚0' t ON = High level OFF = Low level Duty cycle = 5% Duty cycle = 50% Duty cycle = 95% tPWM tOFF Vdd UIFA Vdd UIFA t ‚0' t Vdd UIFA ‚0'

Package Information

Target Data Sheet 42 V 0.41, 2009-03

4 Package Information

4.1 Package Parameters

4.2 Package Outline

Figure 17 PG-DSO-8 Package Dimension Table 14 Package Parameters Parameter Symbol Limit Values Unit Notes min. typ. max. Thermal Resistance R thJA - 150 200 K/W Junction to Air 1) 1) according to Jedec JESD51-7 RthJC - - 75 K/W Junction to Case RthJL - - 85 K/W Junction to Lead Soldering Moisture Level MSL 3 260°C Lead Frame Cu Plating Sn 100% > 7 µm P-PG-DSO-08-16-S-PO V03 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Lead width can be 0.61 max. in dambar area 3) Max. 3˚ tilt of sensitive area to preference "B" 4) Reference "D" is defined with the center of all 8 pins -0.06 +0.10.41 1 4 1.27 A 0.1 0.2 M A (1.45) 0.175±0.07 1.75 MAX. B B 6±0.2 0.64 0.35 x 45˚ 0.19 +0.06 ±0.25 8˚MAX. 8x0.2 M C 4-0.2 1)5-0.2 1.22±0.18C 1.273 x = 3.81

0.75 D E

E D A Detail A SENSITIVE CENTER OF AREA PLANE SEATING Index Marking ø0.6 Sensitive Area 3) 0.32 MIN.

Target Data Sheet 43 V 0.41, 2009-03

4.3 Footprint

Figure 18 Footprint PG-DSO-8

4.4 Packing

4.5 Marking

Note: For processing recommendations, please refer to Infineon’s Notes on processing Position Marking Description 1st Line I5012xx See ordering table on page 7 2nd Line xxx Lot code 3rd Line Gxxxx G..green, 4-digit..date code 0.65 1.31 5.69 1.27 6.4 5.2 0.3 ±0.312 2.1 1.75

Published by Infineon Technologies AG www.infineon.com

Summary

GMR-Based Angular Sensor for Rotary Switches V 0.41, 2009-03

Description