TLF50201ELV50 INFINEON | Alldatasheet

Document overview

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Technical content

Features

  • 500 mA step down voltage regulator
  • 5 V Output voltage
  • ±2% output voltage tolerance
  • Low quiescent current (less than 45 µA at nominal battery voltage)
  • Integrated power transistor
  • C u r r e n t m o d e P W M r e g u l a t i o n
  • PFM mode for light load current
  • Input voltage range from 4.75 V to 45 V
  • 2.2 MHz switching frequency
  • 100% Duty cycle
  • Synchronization input
  • Soft-start function
  • Input undervoltage lockout
  • Suited for automoti ve applications: Tj = -40°C to 150°C
  • Green Product (RoHS compliant) Potential applications
  • Applications with a 5.0 V switching regulator as replacement for linear voltage regulator with low quiescent current, such as: –d a s h b o a r d – engine management –b r a k i n g –b o d y – infotainment Product validation Qualified for automotive applications. Product Validation according to AEC-Q100/101.

Data Sheet 2 Rev. 1.1 2018-03-07 TLF50201ELV50

2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current

Description

The TLF50201EL is a high frequency PWM step-down DC/DC converter with an integrated PMOS power switch, packaged in a small PG-SSOP-14 with exposed pad. Th e wide input voltage range from 4.75 V to 45 V makes the TLF50201EL suitable for a wide variety of applicatio ns. The device is designed to be used under harsh automotive environmental conditions. The switching frequency of nominal 2.2 MHz allows the use of small and cost-effective inductors and capacitors, resulting in a low, predictable output voltage ripple and in minimized consumption of board space. In light load condition the device op erates in Pulse Frequenc y Modulation (PFM) to op timize the efficiency. Between the single pulses, all intern al controlling circuitry is switched off to redu ce the internal power consumption. The TLF50201EL includes protection fe atures such as a cycle-by-cycle current limitation, overtemperature shutdown and input undervoltage lockout. The voltage regulation loop provides an excellent line and load regulation, the stability of the loop is ensured by an internal compensation network. This compensation network combined with a current mode regulation control guarantees a highly effective line transient rejection. During star t-up the integrated soft-start limits the inrush current peak and prevents output voltage overshoot. Type Package Marking TLF50201EL PG-SSOP-14 TLF50201

Data Sheet 3 Rev. 1.1 2018-03-07 TLF50201ELV50

Data Sheet 4 Rev. 1.1 2018-03-07 TLF50201ELV50

2 Block diagram

3N.C. N.C. INT. SUPPLY 2N.C. 4SYNC GND 9 10 N.C. N.C. N.C. N.C.

Data Sheet 5 Rev. 1.1 2018-03-07 TLF50201ELV50

3 Pin configuration

3.1 Pin assignment

Figure 2 Pin configuration

3.2 Pin definitions and functions

1N . C . Not Connected Internally not connected. Leave open or connect to GND. 2N . C . Not Connected Internally not connected. Leave open or connect to GND. 3N . C . Not Connected Internally not connected. Leave open or connect to GND. 4S Y N C Synchronization input Connect to an external clock signal in order to synchronize/adjust the switching frequency. This feature is not functionally in PFM mode. 5F R E Q Frequency adjustment pin Connect an external resistor to GND to adjust the switching frequency, do not leave open. In case the synchronization option is used, the resistor must be dimensioned close to the desired synchronization frequency. 6N . C . Not Connected Internally not connected. Leave open or connect to GND. 7F B Feedback input Connect this pin directly to the output capacitor. Also input for internal power supply. The internal power supply is taken from the output voltage. 8N . C . Not Connected Internally not connected. Leave open or connect to GND. N.C. N.C. SWO N.C. 2 13 1 14 SYNC TLF50201EL GND5FREQ 7FB GND N.C.8 PG-SSOP14 VS N.C. N.C. N.C.

Data Sheet 6 Rev. 1.1 2018-03-07 TLF50201ELV50 Connect this pin directly with low inductive and broad trace to ground, do not leave open.

10 GND Ground

Connect this pin directly with low inductive and broad trace to ground, do not leave open.

11 SWO Buck Switch Output

Drain of the integrated power-PMOS transistor. Connect directly to the cathode of the catch diode and the buck circuit inductance. 12 N.C. Not Connected Internally not connected. Leave open or connect to GND.

13 VS Supply Voltage input

Connect to supply voltage source. 14 N.C. Not Connected Internally not connected. Leave open or connect to GND. Exposed pad Connect to heatsink area and GND by low inductance wiring. Pin Symbol Function

Data Sheet 7 Rev. 1.1 2018-03-07 TLF50201ELV50 General product characteristics

4 General product characteristics

4.1 Absolute maximum ratings

  1. Stresses above the ones listed here may cause perm anent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection functions are designed to prev ent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Table 1 Absolute maximum ratings 1) Tj = -40°C to 150°C; all voltages with respect to ground (unless otherwise specified) 1) Not subject to production test, specified by design Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Voltages Synchronization input VSYNC -0.3 – 5.5 V – P_4.1.1

6.2 V t < 10 s 2)

2) ESD susceptibility HBM according to ANSI/ESDA/JEDEC JS-001. P_4.1.2 Feedback Input VFB -0.3 – 5.5 V – P_4.1.3 6.2 V t < 10 s 2) P_4.1.4 Frequency adjustment pin VFREQ -0.3 – 5.5 V – P_4.1.5 6.2 V t < 10 s 2) P_4.1.6 Buck switch output VSWO -2.0 – VVS + 0.3 V– P_4.1.7 Supply voltage input VVS -0.3 – 45 V – P_4.1.8 Temperatures Junction temperature Tj -40 – 150 °C – P_4.1.9 Storage temperature Tstg -55 – 150 °C – P_4.1.10 ESD susceptibility ESD resistivity VESD -2 – 2 kV HBM P_4.1.11 ESD resistivity to GND VESD -500 – 500 V CDM 3) 3) ESD susceptibility, Charged Device Mode l “CDM” EIA/JESD22-C101 or ESDA STM5.3.1 P_4.1.12 ESD resistivity corner pins to GND VESD -750 – 750 V CDM 3) P_4.1.13

Data Sheet 8 Rev. 1.1 2018-03-07 TLF50201ELV50 General product characteristics

4.2 Functional range

Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table.

4.3 Thermal resistance

Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Supply voltage VS 4.75 – 45 V – P_4.2.1 Buck inductor LBU 3.3 – 22 µH – P_4.2.2 Buck capacitor CBU1 10 – 50 µF – P_4.2.3 Buck capacitor ESR ESRBU1 0.015 – 0.100 Ω – 1) 1) See section “Application information” on Page 22 for loop compensation requirements and refer to Application Note for dimensioning the output filter. P_4.2.4 Junction temperature Tj -40 – 150 °C – P_4.2.5 Table 3 Thermal resistance Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Junction to case1) 1) Not subject to production test, specified by design. RthJC –1 0 – K / W – P_4.3.1 Junction to ambient 2) 2) Specified RthJA value is according to JEDEC 2s2p (JESD 51-7) + (JESD 51-5) and JEDEC 1s0p (JESD 51-3) + heatsink area at natural convection on FR4 board. RthJA –4 7 – K / W 2 s 2 p P_4.3.2 RthJA – 54 – K/W 1s0p + 600 mm2 P_4.3.3 RthJA – 64 – K/W 1s0p + 300 mm2 P_4.3.4

Data Sheet 9 Rev. 1.1 2018-03-07 TLF50201ELV50

5 Buck regulator

5.1 Description

The TLF50201EL is a monolithic current mode step down converter with adjustable switching frequency fOSC. It is capable to operate either in Pulse Width Modulation (PWM) or in Pulse Frequency Modulation (PFM) Mode.

5.1.1 Regulator loop

The supply voltage is connected to pin VS. Between pin VS and pin SWO there is an internal shunt resistor and the internal PMOS power stage. The PMOS is driven by the driver stage. Regulator block The device is on as soon as an input voltage higher than input voltage startup threshold V S,on is applied to pin VS. The feedback signal VFB is connected to pin FB. Between pin FB and pin GND is an internal resistor divider. An error amplifier and a comparator are connected to this resistor divider: The error amplifier EA-gmV, which is controlling the output voltage in PWM mode, and the PFM comparator, which will switch the TLF50281EL into PFM mode and trigger the pulses. The error amplif ier EA-gmV is connected to the PWM comparator. The regulation loop operates in current mode: The output current of EA-gmV is subtracted from the sum of the current loop CS-gmI and the slope compensation ISLOPE. The result is evaluated by PWM Comp (a current comparator). The output of PWM Comp defines duty cycle (pulse-width-modulated signal) in PWM mode. The Slope Compensation added to the signal from the error amplifier EA-gmV to the PWM Comparator ensures that no sub harmonics will occur on the input current. The PWM comparator output and the PFM comparator output are connected to the PWM /PFM logic. An external resistor at pin FREQ is required to set the switching frequency (for details please refer to chapter 8 Module Oscillator). The TLF50201EL may also be synchronized to an exte rnal frequency. In this case an external clock signal should be connected to pin SYNC . The frequency setting resistor at pin FREQ is still necessary, it has to be selected according to the desired synchronization frequency (for details please refer to Chapter 7 Oscillator . The TLF50201EL can only be synchronized to an external frequency source in PWM mode, this function does not work in PFM mode. The clock manager is clocking the PWM/PFM logic. The PWM/PFM logic is triggering the driver to apply pulses to the internal PMOS power stage. Safety features The shunt resistor in line with the internal PMOS power stage (between pin VS and the power stage) is connected to a current sense amplifier CS-gml. It dete cts the voltage above the shunt resistor. The amplifier creates a signal which shuts the pulse down in case that the shunt volt age exceeds the reference limit. The current limitation acts as a cycle-by -cycle limitation. Cycle-by-cycle li mitation means, that every pulse is switched off as soon as the current through the PMOS exceeds the buck peak over current limit IBUOC. The next pulse starts and will also be switched off as soon as the current limit is exceeded again. This results in a lowered output voltage whilst the output current is limited to a certain value. Input undervoltage shutdown: If the input voltage is below the input undervoltage shutdown threshold VS,off the device will shut down.

Data Sheet 10 Rev. 1.1 2018-03-07 TLF50201ELV50 Output overvoltage protection: If th e output voltage exceeds the PFM thre shold the device will switch from PWM to PFM. Pulses will then be generated only depending on the value of the output voltage VCC. Soft start function: An integrated soft start function of duration tstart ensures, that the inrush current will be limited. After an overtemperature shutdown the regulator always restarts with a soft start. Overtemperature shutdown: An internal temperature sensor detects the temperature of the device. It will be switched off if the junction temperature ex ceeds the overtemperatur e shutdown threshold Tj,sd and restart with a certain hysteresis Tj,sd_hyst (for details please refer to Chapter 6 Thermal shutdown ). Biasing The internal biasing is taken from pin VS as well as from pin FB (connected to VCC) (for details please refer to Chapter 6 Thermal shutdown ). Thus the power consumption from the supply voltage VS can be minimized. Figure 3 Block diagram buck regulator

5.1.2 PWM (Pulse Width Modulation) mode

Under normal conditions the TLF50201EL will operate with a constant switching frequency fOSC in PWM mode. The ratio between switch-on-time TON and switch-off-time TOFF is mainly determined by the ratio between the input voltage VS and the output voltage VCC and is influenced by the output current ICC. In PWM mode the device may operate with 100% duty cy cle, in this case the internal PMOS is constantly conducting current. The current limitation feature is operating under this condition. If the switch-on-time TON should theoretically be below the minimum threshold TON,min (due to low load or due to the ratio between input voltage VS and output voltage VCC depending on the switching frequency), it will be reduced to the minimum value switch-on-time TON,min and stay there. As a consequence the output voltage VCC will increase. The PFM comparator detects the PFM threshold and will then switch the device into PFM mode. There is no possibility to disable the PFM function. Driver CS-gmI EA-gmV PWM PFM Logic Clock Manager PWM Comp SoftStart GateD VS SWO FB FREQ SYNC_IN GND PFM Comparator Slope Comp. VBG CLK CK_A

Data Sheet 11 Rev. 1.1 2018-03-07 TLF50201ELV50

5.1.3 PFM (Pulse Frequency Modulation) mode

To optimize the efficiency and to reduce the current consumption, the TLF50201EL automatically switches to PFM mode under low load conditions. In PFM mode th e internal power stage including the driver stage is switched off and will only be switched on for applying pulses to charge the output capacitor. The pulses will be created by monitoring the voltage of the output filter capacitor COUT. Thus in PFM mode the repetition time of pulses depend on the output current and/or the ratio between input voltage VS and output voltage VCC. Transition from PWM to PFM Figure 4 shows the transition from Pulse Width Modula tion to Pulse Frequency Modulation under the assumption, that the input voltage VS will be constant and only the output current ICC will vary. The diagram shows the principle, in reality the signals might look slightly different. The diagram is without scale in respect of time, voltage and current values. Starting from left of the figure a certain output current, here named i1, is applied to the regulator output. This results in a duty cycle D1 with the on-time TON1 of the internal power st age. The switching frequency fOSC is constant as set by the fr equency setting resistor RFREQ. The regulator is in PWM mode, the output voltage is VREF_PWM which is equal to VFB in PWM mode. At point t1 the output current decreases from i1 to a lower i2. This results in a duty cycle D2 with the on-time TON2 of the internal power stage. Due to the reduced output load the on-time TON2 is shorter (the regulator is in Discontinuous Conduc tion Mode DCM) than TON1. The switching frequency fOSC is constant as set by the frequency setting resistor RFREQ. The regulator is still in PWM mode, the output voltage is VREF_PWM which is equal to VFB in PWM mode. In Continuous Conduction Mode CCM the variation from TON1 to TON2 will be very small due to smaller conduction losses. At point t2 the output current decreases again from i2 to a lower i3. As a consequence the on-time TON will be reduced also. The output current i3 is so low, that the on-time TON3 would be smaller than the TON,min. The regulator does not allow a on-time smaller than TON,min. Therefore we can say that the output current i3 is under the imaginary current threshold for transition from PWM to PFM iPWM/PFM. With the pulse staying at on- time TON,min the output voltage VCC will rise. The regulator is still in PWM mode, but the output voltage rises. At point t3 after a normal time period TPWM as adjusted by the frequency setting resistor RFREQ, a further pulse of the duration TON,min is applied, the output voltage VCC keeps on rising. The regulator is still in PWM mode. At point t4 the output voltage VCC touches (or exceeds) the voltage thre shold for transition from PWM to PFM VPWM/PFM. The regulator is now switching internally from PWM to PFM. In PFM mode the power consumption of the internal blocks is reduced. Th e reference for the output voltage VCC is switched from VREF_PWM (which is equal to VFB in PWM mode) to VREF_PFM (which is equal to VFB in PFM mode). The reference for VFB in PFM mode is higher than the reference in PWM mode to avoid voltage dumps at the output voltage VCC due to sudden load steps and to give the regulator more reaction time to switch back to PWM mode. The regulator is now in PFM mode, the output voltage is VREF_PFM which is equal to VFB (or slightly higher) in PFM mode. The output voltage VCC is monitored and as soon as it touches the PFM reference voltage VREF_PFM a pulse of the on-time TON,min is triggered. The time betw een two pulses is depending on the discharging of the output capacitor COUT.

Data Sheet 12 Rev. 1.1 2018-03-07 TLF50201ELV50 Figure 4 PWM to PFM transition (timing diagram) Transition from PFM to PWM Figure 5 shows the transition from Pulse Frequency Mo dulation to Pulse Width Modulation under the assumption, that the input voltage VS will be constant, and only the output current ICC will vary. The diagram shows the principle, in reality the signals might look slightly different. The diagram is without scale in respect of time, voltage and current values. Starting from left of the figure a certain output current, here named i3, is applied to the regulator output. i3 shall be below the imaginary current thre shold for transition from PFM to PWM iPFM/PWM. The regulator is in PFM mode, the output voltage is VREF_PFM, which is equal to VFB in PFM mode (or slightly higher). Pulses of the duration TON,min are triggered whenever the output voltage VCC touches the PFM reference voltage VREF_PFM. At point t5 the output current increases from i3 to a higher i2, that shall be above the imaginary current threshold for transiti o n f r o m P F M t o P W M iPFM/PWM. Due to the higher output current more pulses of the duration TON,min have to be triggered, the fr equency of these pulses is moni tored. The fre quency of these pulses increases until it is higher than the switching frequency fOSC set by the frequency setting resistor RFREQ. The regulator is still in PFM mode. At point t6 the frequency monitoring detects that the freque ncy of the PFM pulses is being higher than the frequency threshold for transition from PFM to PWM fPFM/PWM. Therefore the regulator switches back to PWM mode. This results in a certain duty cycle D2 with the on-time TON2 of the internal power stage. The time period TPWM is as adjusted by the frequency setting resistor RFREQ. time Output current time Switching signal time Output voltage iPWM/PFM D1 D2 TPWM TPWM t1 t2 t3 t4 VREF_PWM VREF_PFM VPWM/PFM Switch to PFM mode TON1 TON2 TON,min TPWM

Data Sheet 13 Rev. 1.1 2018-03-07 TLF50201ELV50 Figure 5 PFM to PWM transition (timing diagram) Frequency variation during PWM/PFM transition Figure 6 shows the transition from Pulse Frequency Modulation to Pulse Width Modulation (and vice versa) in relation to output current and switching frequency. Th e diagram shows the principle, in reality the signals might be slightly different. The diagram is without scale in respect of frequency and current values. The transition from PWM to PFM is shown in a grey line. Starting from righ t the switching frequency fPWM is constant as set by the frequency setting resistor RFREQ. The output current ICC is decreasing. As soon as the output current ICC is below the imaginary current thresh old for transition from PWM to PFM iPWM/PFM, the regulator will be switched from PWM to PFM mode depending on the output voltage VCC. With the output current ICC decreasing, the switching fr equency will also decrease, as the pulses are triggered by monitoring the output voltage VCCat capacitor COUT. The transition from PFM to PWM is shown in a black line. Starting from left the switching frequency is increasing with the increasing output current ICC. As soon as the switching frequency is crossing the frequency threshold for transition from PFM to PWM fPFM/PWM (which is above the switching frequency fOSC set by the frequency setting resistor RFREQ) the regulator will switch from PFM to PWM. time Output current time Switching signal time Output voltage iPFM/PWM TPWM VREF_PWM VREF_PFM VPWM/PFM Switch to PWM mode TON2TON,min TON,min

Data Sheet 14 Rev. 1.1 2018-03-07 TLF50201ELV50 Figure 6 PWM <-> PFM transitions Output Current (log.scale) Switching Frequency (log.scale) PFM to PWMPWM to PFM fPFM/PWM fPWM iPWM/PFM iPFM/PWM

Data Sheet 15 Rev. 1.1 2018-03-07 TLF50201ELV50

5.2 Electrical characteristics buck regulator

Table 4 Electrical characteristics: buck regulator VS = 6.0 V to 40 V, Tj = -40°C to 150°C, all voltages with respect to ground (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Output voltage VFB 4.90 5.00 5.10 V 7 V < VS < 12 V 100 mA < ICC < 610 mA PWM Mode P_5.2.1 Output voltage VFB 4.90 5.10 5.30 V 10 V < VS < 35 V ICC = 100 µA PFM Mode P_5.2.2 Power stage on-resistance Ron –1 . 5 2 . 3 Ω Tested at 100 mA, VS = 7.0 V P_5.2.8 Buck peak over current limit IBUOC 0.85 – 1.7 A – P_5.2.9 Current transition rise/fall time tR – 100 – mA/ns 1) 1) Specified by design. Not subject to production test. P_5.2.10 Maximum duty cycle Dmax – – 100 % 2) 2) Consider Chapter 4.2 Functional range . P_5.2.11 Minimum switch on-time TON,min – 100 – ns 1) P_5.2.12 Minimum switch off- Time TOFF,min – 200 – ns 1) PFM mode P_5.2.13 Soft start ramp tstart 300 450 750 µs VFB rising from 5% to 95% of VFB,nom P_5.2.14 Input undervoltage shutdown threshold VS,off 3.75 – – V VS decreasing P_5.2.15 Input voltage startup threshold VS,on – – 4.75 V VS increasing P_5.2.16 Input undervoltage shutdown hysteresis VS,hyst 130 300 – mV – P_5.2.17 Voltage threshold for transition from PWM to PFM VPWM/PFM ––5 . 3 V 1) P_5.2.18 Frequency ratio for transition from PFM to PWM fPFM/PWM/ fosc

Data Sheet 16 Rev. 1.1 2018-03-07 TLF50201ELV50

5.3 Performance graphs

Typical performance characteristics Load regulation PWM mode VS = 12 V; TJ = -43°C Line regulation PWM mode VS = 12 V; TJ = +25°C Load regulation PWM mode VS = 12 V; TJ = +150°C 5,000 5,025 5,050 5,075 5,100 VFB (V) 4,900 4,925 4,950 4,975 150 250 350 450 550 650 Icc (mA) 5,000 5,025 5,050 5,075 5,100 VFB (V) 4,900 4,925 4,950 4,975 150 250 350 450 550 650 Icc (mA) 5,000 5,025 5,050 5,075 5,100 VFB (V) 4,900 4,925 4,950 4,975 150 250 350 450 550 650 Icc (mA)

Data Sheet 17 Rev. 1.1 2018-03-07 TLF50201ELV50 ICC = 100 µA; TJ = -43°C Line regulation PFM mode ICC = 100 µA; TJ = +25°C Line regulation PFM mode ICC = 100 µA; TJ = +150°C Power stage on resistance: black TJ = +25°C light grey TJ = -43°C, dark grey TJ = +150°C 5,016 5,032 5,048 5,064 5,08 5,096 5,112 5,128 VFB (V) VS (V) 5,016 5,032 5,048 5,064 5,08 5,096 5,112 5,128 VFB (V) VS (V) 5,016 5,032 5,048 5,064 5,08 5,096 5,112 5,128 VFB (V) VS (V) 0,600 0,800 1,000 1,200 1,400- Vswo (V) 0,000 0,200 0,400 0,1 0,2 0,3 0,4 0,5 0,6 0,7 VS - Iswo(A)

Data Sheet 18 Rev. 1.1 2018-03-07 TLF50201ELV50 VS = 13 V, fOSC = 1.65 MHz, LOUT = 4.7 µH Efficiency for VS = 13 V, fOSC = 1.65 MHz, LOUT = 10 µH Efficiency for VS = 13 V, fOSC = 2.2 MHz, LOUT = 4.7 µH Efficiency for VS = 13 V, fOSC = 2.2 MHz, LOUT = 10 µH 10,00% 20,00% 30,00% 40,00% 50,00% 60,00% 70,00% 80,00% 90,00% 0 100 200 300 400 500 600 ICC (mA) 0,00% 10,00% 20,00% 30,00% 40,00% 50,00% 60,00% 70,00% 80,00% 90,00% 0 100 200 300 400 500 600 ICC (mA) 10,00% 20,00% 30,00% 40,00% 50,00% 60,00% 70,00% 80,00% 90,00% 0 100 200 300 400 500 600 ICC (mA) 0,00% 10,00% 20,00% 30,00% 40,00% 50,00% 60,00% 70,00% 80,00% 90,00% 0 100 200 300 400 500 600 ICC (mA)

Data Sheet 19 Rev. 1.1 2018-03-07 TLF50201ELV50

6 Thermal shutdown

6.1 Description

The integrated thermal shutdown func tion turns off the power switch in case of overtemperature. The typ. junction shutdown temperature is 175°C, with a min. of 155°C. After cooling down , the IC will automatically restart with a soft start into normal operation. The thermal shutdown is an inte grated protection function designed to prevent IC destruction when operating under fault conditions . It should not be used for normal operation.

6.2 Electrical characteristics bias and thermal shutdown

Table 5 Electrical characterist ics:bias and thermal shutdown VS = 6.0 V to 40 V, Tj = -40°C to 150°C, all voltages with respect to ground (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Bias Current consumption of VCC Iq,ON,V_CC ––6 0 µ A VS =1 6V ; VCC =5 . 4V Tj < 105°C; PFM mode P_6.2.5 Current consumption of VS Iq,ON,V_S –1 5 2 5 µ A VS =1 6V ; VCC =5 . 4V ; Tj < 105°C; PFM mode P_6.2.6 Internal overtemperature protection Overtemperature shutdown Tj,sd 155 175 195 °C 1) 1) Specified by design. Not subject to production test. P_6.2.7 Overtemperature shutdown hysteresis Tj,sd_hyst -1 5 – K P_6.2.8

Data Sheet 20 Rev. 1.1 2018-03-07 TLF50201ELV50

7 Oscillator

7.1 Description

The oscillator supplies the device wi th a constant frequency. The power switch will be switched on and off with a constant frequency fOSC. The time period TPWM is derived from this frequency and some safety functions are synchronized to this frequency. The oscillator frequency can be set by connecting an external resistor RFREQ between pin FREQ and GND using the following table (selected values, for more precise setting please refer to Figure 7). Figure 7 Switching frequency fOSC versus frequency setting resistor RFREQ. The turn-on frequency can optionally be set externally via the SYNC pin. In this case the synchronization of the P W M - o n s i g n a l r e f e r s t o t h e f a l l i n g e d g e o f t h e S Y N C-pin input signal. In case the synchronization to an external clock signal is not needed, the SYNC pin should be connected to gr ound. The frequency setting resistor RFREQ is also necessary for SYNC option and mu st be dimensioned according to the desired synchronization frequency (the ratio between synchroniz ation and internal frequency has to be less than or equal to 1). The synchronization function is not available in PFM mode. Frequency setting resistor Frequency adjusting resistor RFREQ 39 43 56 82 100 k Ω P_7.1.1 Oscillator frequency fosc 2400 2250 1800 1330 1100 kHz P_7.1.2 1,15 1,3 1,45 1,6 1,75 1,9 2,05 2,2 2,35 2,5 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 Switching Frequency [MHz] Resistor at Freq pin [kΩ]

Data Sheet 21 Rev. 1.1 2018-03-07 TLF50201ELV50

7.2 Electrical characteristics buck regulator

Table 6 Electrical characteristics: buck regulator VS = 6.0 V to 40 V, Tj = -40°C to 150°C, all voltages with respect to ground (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Frequency setting FREQ Oscillator frequency spread fosc 2025 2250 2475 kHz VSYNC = 0 V; RFREQ = 43 kΩ P_7.2.1 Synchronization SYNC Synchronization capture range fsync 1500 – 2200 kHz – P_7.2.2 SYNC signal high level valid VSYNC,H 2.9 – – V 1) 1) Synchronization of PWM-on signal to falling edge. P_7.2.3 SYNC signal low level valid VSYNC,L ––0 . 8 V 1) P_7.2.4 SYNC signal minimum high time tSYNC,H, min 50 – – ns – P_7.2.6 SYNC signal minimum low time tSYNC,L,min 50 – – ns – P_7.2.7

Data Sheet 22 Rev. 1.1 2018-03-07 TLF50201ELV50

Application information

8 Application information

Note: The following information is given as a hint fo r the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. Figure 8 Application diagram Note: This is a very simplified example of an applicatio n circuit. The function must be verified in the real application. Figure 9 Bill of material for application diagram CIN3 DIN LIN Oscillator Buck Converter FB SWO FREQ VS Soft Start Ramp Generator Bandgap Reference TLF50201EL Over Temperature Shutdown N.C. N.C. DCATCH COUT VS VCC LOUT INT. SUPPLY N.C. SYNC CIN2CIN1 LIN, CIN1 and CIN3 recommended for suppression of EME, DIN depending on application GND GND N.C. N.C. N.C. N.C. CIN2 CIN3 COUT LOUT DCATCH 100nF/50V 47μF/50V 10μF/25V Part-No. Value 1A/100V Type Manufacturer 10μH MSS1278T AVX ceramic ceramic Remark Coilcraft 10BQ100 Schottky International Rectifier 47 kΩ 0.25 W electrolytic 4.7 μH also possible fOSC set to 2.2 MHz For improving EME

1 A current capability

Data Sheet 23 Rev. 1.1 2018-03-07 TLF50201ELV50

8.1 General layout recommendations

Introduction: A switch mode step down converter is a potential source of electromagnetic disturbances which may affect the environment as well as the device itself and cause sporadic malfunction up to damages depending on the amount of noise. In principal we may consider the following basic effects:

  • radiated magnetic fields caused by circular currents, occurring mostly with the switching frequency and their harmonics;
  • radiated electric fields, often ca used by (voltage) oscillations;
  • conducted disturbances (voltage sp ikes or oscillations) on the lines, mostly input and output lines. Radiated magnetic fields: Radiated magnetic fields are caused by circular currents occurring in so called “current windows”. These circular currents are alternating currents which are driven by the switching transistor. The alternating current in these windows are driving magnetic fields. The amount of magnetic emissions is mainly depending on the amplitude of the alternating current and the size of the so-called “window” (this is the area, which is defined by the circular current paths. We can divide into two windows:
  • the input current “window” (path consisting of CIN2, CIN3, LOUT and COUT): Only the alternate content of the input current IS is considered;
  • the output current “window” (path consisting of DCATCH, LOUT and COUT): Output current ripple ∆I. The area of these “windows” has to be kept as small as possible, with the relating elements placed next to each others as close as possible. It is highly recommended to use a ground plane as a single layer which covers the complete regulator area with all co mponents shown in the application diagram. Al l connections to ground shall be as short as possible. Radiated electric fields: Radiated electric fields are caus ed by voltage oscillations occurr ing by stray inductances and stray capacitances at the connection between intern al power stage (pin SWO), freewheeling diode DCATCH, and output capacitor COUT. They are also of course influenced by the commutation of the current from the internal power stage to the freewheeling diode DCATCH. Their frequencies might be above 100 MHz. Therefore, it is recommended to use a fast Schottky diode and to keep the connections in this area as low inductive as possible. This can be achieved by using short and br oad connections and by arranging the related parts as close as possible. Following the recommendation of using a ground layer these low inductive connections will form together with the ground layer small capacitanc es which are desirable to damp the slope of these oscillations. The oscillations use conne ctions or wires as ante nnas, this effect can also be minimized by the short and broad connections. Conducted disturbances: Conducted disturbances are voltage spikes or voltage oscillations, oc curring permanently or by occasion mostly on the input or output conne ctions. Comparable to the radiated electric fields th ey are caused by voltage stage, freewheeling diode DCATCH, and output capacitor COUT. Their frequencies might be above 100 MHz. They are s uper positioned to the input and output voltage and might therefore disturb other components of the application. The countermeasures against conducted disturbances are similar to the radiated electric fields:

Data Sheet 24 Rev. 1.1 2018-03-07 TLF50201ELV50

  • it is recommended to us e short and thick connections between the single parts of the converter;
  • all parts shall be mounted close together;
  • additional filter capacitors (ceramic, with low ESR i.e CIN3 in the application diagram) in parallel to the output and input capacitor and as close as possible to the switching parts. Input and load current must be forced to pass these devices, do not connect them via thin lines. Recommended values from 10 nF to 220 nF;
  • for the input filter a so called π – Filter for maximum suppression might be necessary, which requires additional capacitors on the input.

8.2 Further application information

  • Please contact us for information regarding the FMEA pin
  • Existing Application Notes with more detailed in formation about the possibilities of this device
  • For further information you may contact http://www.infineon.com/

Data Sheet 25 Rev. 1.1 2018-03-07 TLF50201ELV50

9 Package outlines

Figure 10 Package outline PG-SSOP-14 Green Product (RoHS compliant) To meet the world-wide customer requirements for en vironmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). PG-SSOP-14-1,-2,-3-PO V02 1 7 14 8 14x0.25±0.05 2) M0.15 DC A-B 0.65 C Stand Off 0 ... 0.1 (1.45) 1.7 MAX. 0.08 C A B 4.9±0.11) A-BC0.1 2x 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion Bottom View ±0.23 ±0.22.65 0.2 ±0.2 D 6 M D 8x 0.64±0.25 3.9±0.11) 0.35 x 45˚ 0.1 CD +0.06 0.19 8˚ MAX. Index Marking Exposed Diepad For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Dimensions in mm

Data Sheet 26 Rev. 1.1 2018-03-07 TLF50201ELV50

Revision history

Rev 1.1 2018-03-06 P_7.2.6 Min value changed from 25 ns to 50 ns. P_7.2.7 Min value changed from 25 ns to 50 ns. Editorial changes. Rev 1.0 2013-06-19 Initial data sheet.

All referenced product or service names and trademarks are the property of their respective owners. Edition 2018-03-07 Published by Infineon Technologies AG

81726 Munich, Germany

© 2018 Infineon Technologies AG. All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com Document reference IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer's comp liance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer's products and any use of the product of Infineon Technologies in customer's applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer's technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.