TLF30681QVS01

TLF30681QVS01 INFINEON | Alldatasheet

Document overview

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Technical content

Features

• High-efficiency step-down pre-regulator for wide input voltage range from

3.7 V to 35 V (40 V limited time) with low overall power loss and fast

• Suitable for operation with ceramic capacitors
• High-efficiency step-down post-regulator for second output voltage generation
• Step-up post-regulator with 5 V output voltage
• Voltage monitoring for two external voltage rails including enable signals
• 16-bit SPI
• Configurable window watchdog
• Green Product (RoHS compliant) Potential applications
• Automotive applications
• Advanced Driver Assistance Systems (ADAS) - 77 GHz radar ECUs - Camera ECUs
• Human Machine Interface (HMI) applications Product validation Qualified for automotive applications. Product validation according to AEC-Q100.

Description

The OPTIREG™ PMIC TLF30681QVS01 is a multiple rail Power Management IC (PMIC) for automotive applications, optimized for the use in Advanced Driver Assistance Systems (ADAS). The device consists of a battery connected buck regulator (Buck1) providing 3.3 V to external loads and to two low voltage post- regulators. The first post-regulator (Buck2) provides an output voltage of 1.25 V (output voltage adjustment via SPI in the range of 0.9 V to 1.3 V). The second post-regulator (Boost1) provides an output voltage of 5.0 V and is intended to supply up to two CAN transceivers. The TLF30681QVS01 supports 16-bit SPI communication to a microcontroller. SPI commands can read status information from the device and control features of the power regulators, such as PWM synchronization. The device operates at a nominal switching frequency of 2.2 MHz. The switching frequency is selectable via SPI from 1.8 MHz to 2.5 MHz in steps of 100 kHz. The switching regulators can synchronize to an external clock signal. The TLF30681QVS01 can provide a synchronization signal for other DC/DC regulators in the system. The TLF30681QVS01 provides two voltage monitoring channels with Datasheet Please read the Important Notice and Warnings at the end of this document Rev. 1.0 www.infineon.com/OPTIREG-PMIC 2020-04-08

monitoring inputs and enable outputs. The monitoring channels can be used to control and monitor external LDOs or external DC/DC switching regulators. Type Package Marking TLF30681QVS01 PG-VQFN-48 TLF30681 S01 OPTIREG™ PMIC TLF30681QVS01 Power management IC Datasheet 2 Rev. 1.0 2020-04-08

OPTIREG™ PMIC TLF30681QVS01 Power management IC Table of contents Datasheet 3 Rev. 1.0 2020-04-08

OPTIREG™ PMIC TLF30681QVS01 Power management IC Table of contents Datasheet 4 Rev. 1.0 2020-04-08

OPTIREG™ PMIC TLF30681QVS01 Power management IC Table of contents Datasheet 5 Rev. 1.0 2020-04-08

OPTIREG™ PMIC TLF30681QVS01 Power management IC Table of contents Datasheet 6 Rev. 1.0 2020-04-08

1 Block diagram

V_S (T30) TM1 AG2 WDI SDO SDI SCL SCS ENA R1VSx Window Watchdog Reset Generator INT ROT INTERRUPT Generator Bandgap 2 for V- Mon. Bandgap 1 SMPR Buck2 V_Buck2 Feedback R2SWx R2PGx R2FB V_Buck1R1SWx R1PGx R1FB NC R2VS1x R1BTS UV/OV-Monitoring/ Enable Handling Internal Supply SPI_DataIn SPI_Clock SPI_ChipSelect SPI_DataOut Watchdog_TriggerIn µC_Reset Interrupt ExtRail1_Feedback ExtRail1_EnableVM1EN VM1FB ExtRail2_Feedback ExtRail2_EnableVM2EN VM2FB Clock Generation SYNCO SYNCI SYNC_In SYNC_Out MPS R3SWSMPR Boost R3PG V_Boost Feedback R3FB AG3 IOVDD AG4 AG5 R1BTSV Interface_supply NC TM2 AG1 R3VS Buck1 Driver Supply AG6 Figure 1 Block diagram OPTIREG™ PMIC TLF30681QVS01 Power management IC Block diagram Datasheet 7 Rev. 1.0 2020-04-08

2 Pin configuration

2.1 Pin assignment

E R1PG3 12 VM2FB 48 SDO 37

13 R1SW1

24 R2PG2

25 R2SW1

36 SYNCI

E E E SCL 39 SCS 40 ROT 41 INT 42 WDI 43 TM2 44 VM1EN 45 VM2EN 46 VM1FB 47 SDI 38

22 R2FB

21 AG4

20 R1FB

19 AG3

18 AG2

17 AG1

16 R1BTS

15 R1SW3

14 R1SW2

23 R2PG1

34 IOVDD

33 MPS

32 TM1

31 R3FB

30 R3PG1

29 R3SW1

28 R2VS2

27 R2VS1

26 R2SW2

35 SYNCO

Figure 2 Pin configuration OPTIREG™ PMIC TLF30681QVS01 Power management IC Pin configuration Datasheet 8 Rev. 1.0 2020-04-08

2.2 Pin definitions and functions PG-VQFN-48

1 AG5 Analog ground, pin 5:

Connect this pin directly to ground via a low ohmic and low inductive trace.

2 NC Not connected:

Leave the pin floating in the application.

3 AG6 Analog ground, pin 6:

Connect this pin directly to ground via a low ohmic and low inductive trace.

4 R1BTSV Decoupling of internal supply voltage:

Connect a decoupling capacitor between this pin and R1PGx.

5 NC Not connected:

Leave this pin floating in the application.

6 ENA Enable input:

A valid enable condition at this pin enables the device.

7 R1VS1 High voltage regulator supply voltage, pin 1:

Connect this pin in parallel with R1VS2 and R1VS3 and then to the supply (battery) voltage via a reverse protection diode. Additionally connect a capacitor between this pin and ground. An EMC filter is recommended.

8 R1VS2 High voltage regulator supply voltage, pin 2:

Connect this in parallel with R1VS1 and R1VS3 and then to the supply (battery) voltage via a reverse protection diode. Additionally connect a capacitor between this pin and ground. An EMC filter is recommended.

9 R1VS3 High voltage regulator supply voltage, pin 3:

Connect this pin in parallel with R1VS1 and R1VS2 and then to the supply (battery) voltage via a reverse protection diode. Additionally connect a capacitor between this pin and ground. An EMC filter is recommended.

10 R1PG1 High voltage regulator power ground, pin 1:

Connect this pin in parallel with R1PG2 and R1PG3 and then to the Buck1 output capacitor ground terminal to ground.

11 R1PG2 High voltage regulator power ground, pin 2:

Connect this pin in parallel with R1PG1 and R1PG3 and then to the Buck1 output capacitor ground terminal to ground.

12 R1PG3 High voltage regulator power ground, pin 3:

Connect this pin n parallel with R1PG1 and R1PG2 and to the Buck1 output capacitor ground terminal to ground.

13 R1SW1 High voltage regulator power stage output, pin 1:

Connect this pin in parallel with R1SW2 and R1SW3 and then to the pre-regulator Buck1 output filter inductor.

14 R1SW2 High voltage regulator power stage output, pin 2:

Connect this pin in parallel with R1SW1 and R1SW3 and then to the pre-regulator output filter inductor. OPTIREG™ PMIC TLF30681QVS01 Power management IC Pin configuration Datasheet 9 Rev. 1.0 2020-04-08

15 R1SW3 High voltage regulator power stage output, pin 3:

Connect this pin in parallel with R1SW1 and R1SW2 and then to the pre-regulator output filter inductor.

16 R1BTS Bootstrap supply voltage:

Connect this pin via the bootstrap capacitor to the R1SWx pins.

17 AG1 Analog ground, pin 1:

Connect this pin directly to ground via a low ohmic and low inductive trace.

18 AG2 Analog ground, pin 2:

Connect this pin directly to ground via a low ohmic and low inductive trace.

19 AG3 Analog ground, pin 3:

Connect this pin directly to ground via a low ohmic and low inductive trace.

20 R1FB High voltage regulator output voltage feedback:

Connect this pin to the Buck1 output capacitor.

21 AG4 Analog ground, pin 4:

Connect this pin directly to ground via a low ohmic and low inductive trace.

22 R2FB Post-regulator output voltage feedback:

Connect this pin to the Buck2 output capacitor.

23 R2PG1 Pre-regulator power ground, pin 1:

Connect this pin in parallel with R2PG2 and then to the Buck2 output capacitor ground terminal to ground.

24 R2PG2 Pre-regulator power ground, pin 2:

Connect this pin in parallel with R2PG1 and then to the Buck2 output capacitor ground terminal to ground.

25 R2SW1 Post-regulator power stage output, pin 1:

Connect this pin in parallel with R2SW2 and then to the Buck2 output filter inductor.

26 R2SW2 Post-regulator power stage output, pin 2:

Connect this pin in parallel with R2SW1 and then to the Buck2 output filter inductor.

27 R2VS1 Post-regulator supply voltage, pin 1:

Connect this pin to the Buck1 output capacitor. In order to compensate for disturbances, add a local bypass capacitor.

28 R2VS2 Post-regulator supply voltage, pin 2:

Connect this pin to the Buck1 output capacitor. In order to compensate for disturbances, add a local bypass capacitor.

29 R3SW1 Regulator 3 power stage output, pin 1:

Connect this pin to Boost1 inductor and external rectifying diode.

30 R3PG1 Regulator 3 power ground, pin 1:

Connect this pin to Boost1 output capacitor ground terminal to ground.

31 R3FB Regulator 3 output voltage feedback pin:

Connect this pin to Boost1 output capacitor. OPTIREG™ PMIC TLF30681QVS01 Power management IC Pin configuration Datasheet 10 Rev. 1.0 2020-04-08

32 TM1 Test mode 1:

Not for customer use. Leave this pin floating in the application.

33 MPS Microcontroller programming mode

Connect this pin to ground for normal operation in the application. Optionally the pin can be used for microcontroller programming purposes, see Application information.

34 IOVDD I/O supply voltage:

Connect this pin to the I/O supply voltage of the microcontroller. Add a decoupling capacitor.

35 SYNCO Synchronization output:

Optional: Connect this pin to an external switch-mode post-regulator synchronization input. This pin delivers the internal switching frequency signal, either in phase or shifted by 180°, depending on the settings via SPI. The switch-mode post-regulator synchronizes to the rising edge. If this pin is not used, then leave it floating.

36 SYNCI Synchronization input:

Connect this pin to an optional external synchronization signal to synchronize the switching of the internal switch-mode regulators. The feature needs to be enabled via SPI. If the pin is not used, then leave it floating.

37 SDO Serial peripheral interface, signal data output:

SPI signalling port; connect this pin to the SPI port "data input" of the microcontroller to send status information during SPI communication.

38 SDI Serial peripheral interface, signal data input:

SPI signalling port; connect this pin to the SPI port "data input" of the microcontroller to receive status information during SPI communication.

39 SCL Serial peripheral interface, signal clock input:

SPI signalling port; connect this pin to the SPI port "clock" of the microcontroller to clock the device for SPI communication.

40 SCS Serial peripheral interface, signal chip select:

SPI signalling port; connect this pin to the SPI port "chip select" of the microcontroller to address the device for SPI communication.

41 ROT Reset output:

Open drain structure with internal pull up resistor. "Low" indicates a reset event for the microcontroller. Connect this pin to the microcontroller reset input.

42 INT Interrupt output:

OPTIREG™ PMIC TLF30681QVS01 Power management IC Pin configuration Datasheet 11 Rev. 1.0 2020-04-08

Push-pull output. A "low" pulse at this pin indicates an interrupt, and the microcontroller reads the SPI status registers. Connect this pin to a non-maskable interrupt port (NMI) of the microcontroller.

43 WDI Watchdog input, trigger signal:

Connect this pin to the "trigger signal output" of the microcontroller. This pin has an internal pull-down. If this pin is not used, then leave it floating.

44 TM2 Test mode 2:

Not for customer use. Connect this pin to GND in the application.

45 VM1EN Enable signal for external voltage rails 1:

Connect this pin to the enable pin of an optional external voltage regulator 1. If the external regulator is not used, then connect this pin to ground.

46 VM2EN Enable signal for external voltage rails 2:

Connect this pin to the enable pin of an optional external voltage regulator 2. If the external regulator is not used, then connect this pin to ground.

47 VM1FB Input for optional external voltage monitoring rail 1:

Connect this pin to an external resistor divider to adjust the overvoltage threshold and the undervoltage threshold of the monitored external voltage generated by the optional external voltage regulator 1. If the optional external regulator is not used, then connect this pin to ground.

48 VM2FB Input for optional external voltage monitoring rail 2:

Connect this pin to an external resistor divider to adjust the overvoltage threshold and the undervoltage threshold of the monitored external voltage generated by the optional external voltage regulator 2. If the optional external regulator is not used, then connect this pin to ground. Cooling tab GND Cooling tab: Internally connected to GND. – EP1 Edge pin 1: Keep the area below this pin free of ground or other signals. Do not solder this pin to ground or any other signal. This pin must be kept free of soldering. – EP2 Edge pin 2: Keep the area below this pin free of ground or other signals. Do not solder this pin to ground or any other signal. This pin must be kept free of soldering. – EP3 Edge pin 3: Keep the area below this pin free of ground or other signals. Do not solder this pin to ground or any other signal. This pin must be kept free of soldering. – EP4 Edge pin 4: Keep the area below this pin free of ground or other signals. Do not solder this pin to ground or any other signal. This pin must be kept free of soldering. OPTIREG™ PMIC TLF30681QVS01 Power management IC Pin configuration Datasheet 12 Rev. 1.0 2020-04-08

3 General product characteristics

3.1 Absolute maximum ratings

Table 1 Absolute maximum ratings 1) Tj = -40°C to 150°C; all voltages with respect to ground, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Pin MPS VMPS -0.3 – 6.0 V – P_3.1.1 IOVDD VIOVDD -0.3 – 6.0 V – P_3.1.2 SCS VSCS -0.3 – 6.0 V – P_3.1.3 SCL VSCL -0.3 – 6.0 V – P_3.1.4 SDI VSDI -0.3 – 6.0 V – P_3.1.5 SDO VSDO -0.3 – 6.0 V – P_3.1.6 WDI VWDI -0.3 – 6.0 V – P_3.1.7 INT VINT -0.3 – 6.0 V – P_3.1.10 AG1 VAG1 -0.3 – 0.3 V – P_3.1.13 AG2 VAG2 -0.3 – 0.3 V – P_3.1.14 AG3 VAG3 -0.3 – 0.3 V – P_3.1.15 AG4 VAG4 -0.3 – 0.3 V – P_3.1.16 AG5 VAG5 -0.3 – 0.3 V – P_3.1.17 AG6 VAG6 -0.3 – 0.3 V – P_3.1.18 SYNCI VSYNCI -0.3 – 6.0 V – P_3.1.19 SYNCO VSYNCO -0.3 – 6.0 V – P_3.1.20 TM1 VTM1 -0.3 – 6.0 V – P_3.1.22 ENA VENA -0.3 – 35 V 2) P_3.1.23 ENA IENA -5.0 – – mA – P_3.1.24 R1BTS VR1BTS VR1SWx - 0.3 – VR1SWx + 6.0 V – P_3.1.25 R1BTSV VR1BTSV -0.3 – 6.0 V – P_3.1.26 R1VS1 VR1VS1 -0.3 – 35 V 2) P_3.1.27 R1VS2 VR1VS2 -0.3 – 35 V 2) P_3.1.28 1 Not subject to production test, specified by design. 2 Maximum rating is extended to 40 V for an overall time of 7 minutes during the lifetime of the product (load dump requirement). OPTIREG™ PMIC TLF30681QVS01 Power management IC General product characteristics Datasheet 13 Rev. 1.0 2020-04-08

Table 1 Absolute maximum ratings 1) (continued) Tj = -40°C to 150°C; all voltages with respect to ground, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. R1VS3 VR1VS3 -0.3 – 35 V 2) P_3.1.29 R1SW1 VR1SW1 -0.3 – VR1VSx + 2.0 V – P_3.1.30 R1SW2 VR1SW2 -0.3 – VR1VSx + 2.0 V – P_3.1.31 R1SW3 VR1SW3 -0.3 – VR1VSx + 2.0 V – P_3.1.32 R1PG1 VR1PG1 -0.3 – 0.3 V – P_3.1.33 R1PG2 VR1PG2 -0.3 – 0.3 V – P_3.1.34 R1PG3 VR1PG3 -0.3 – 0.3 V – P_3.1.35 R1FB VR1FB -0.3 – 7.0 V – P_3.1.36 R2VS1 VR2VS1 -0.3 – 7.0 V – P_3.1.37 R2VS2 VR2VS2 -0.3 – 7.0 V – P_3.1.38 R2SW1 VR2SW1 -0.3 – 7.0 V – P_3.1.39 R2SW2 VR2SW2 -0.3 – 7.0 V – P_3.1.40 R2PG1 VR2PG1 -0.3 – 0.3 V – P_3.1.41 R2PG2 VR2PG2 -0.3 – 0.3 V – P_3.1.42 R2FB VR2FB -0.3 – 7.0 V – P_3.1.43 R3SW1 VR3SW1 -0.3 – 7.0 V – P_3.1.44 R3PG1 VR3PG1 -0.3 – 0.3 V – P_3.1.45 R3FB VR3FB -0.3 – 7.0 V – P_3.1.46 VM1FB VVM1FB -0.3 – 6.0 V – P_3.1.47 VM1EN VVM1EN -0.3 – 6.0 V – P_3.1.48 VM2FB VVM2FB -0.3 – 6.0 V – P_3.1.49 VM2EN VVM2EN -0.3 – 6.0 V – P_3.1.50 ROT VROT -0.3 – 6.0 V – P_3.1.51 TM2 VTM2 -0.3 – 6.0 V – P_3.1.52 Temperatures Junction temperature Tj -40 – 150 °C – P_3.1.53 Storage temperature Tstg -55 – 150 °C – P_4.1.9 ESD susceptibility 1 Not subject to production test, specified by design. 2 Maximum rating is extended to 40 V for an overall time of 7 minutes during the lifetime of the product (load dump requirement). OPTIREG™ PMIC TLF30681QVS01 Power management IC General product characteristics Datasheet 14 Rev. 1.0 2020-04-08

Table 1 Absolute maximum ratings 1) (continued) Tj = -40°C to 150°C; all voltages with respect to ground, positive current flowing into pin, (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. ESD susceptibility all pins VESD,HBM -2 – 2 kV HBM3) P_4.1.10 ESD susceptibility all pins VESD,CDM -500 – 500 V CDM4) P_4.1.12 ESD susceptibility of corner pins to GND VESD,Corne r -750 – 750 V CDM4) P_4.1.13 Notes: 1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as outside the normal operating range. Protection functions are not designed for continuous repetitive operation.

3.2 Functional range

Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Supply voltage range for normal operation VR1VSx 5.0 – 35 V 5) P_3.2.1 Supply voltage range for reduced operation Junction Temperature Tj -40 – 150 °C – P_4.2.9 Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the electrical characteristics table. 1 Not subject to production test, specified by design. 3 ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5k Ω, 100 pF). 4 ESD susceptibility, Charged Device Model "CDM" according JEDEC JESD22-C101.

5 When first powered up, a proper startup of the device can only be ensured by applying minimum 6 V at

pins R1VSx for at least 2 ms. The device may start at even lower voltages. 6 The current capability of Buck1 is reduced to limit the current stress in the device. OPTIREG™ PMIC TLF30681QVS01 Power management IC General product characteristics Datasheet 15 Rev. 1.0 2020-04-08

3.3 Thermal resistance

Table 3 Thermal resistance 7) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Junction to case RthJC – – 12.2 K/W – P_4.3.1 Junction to soldering point (pin) RthJSP 20.1 – 22.1 K/W JEDEC 2s2p, measured to pin 1, 3, 17, 18, 19, 21 P_3.3.1 Junction to soldering point (pin) RthJSP 34.9 – 37.6 K/W JEDEC 1s0p, measured to pin 1, 3, 17, 18, 19, 21 P_3.3.2 Junction to soldering point (soldering pad) RthJSP 11.0 – 14.7 K/W JEDEC 2s2p P_3.3.3 Junction to soldering point (soldering pad) RthJSP 13.1 – 18.0 K/W JEDEC 1s0p P_4.3.2 Junction to ambient RthJA – 37 – K/W 8) P_4.3.3 Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information visit www.jedec.org. 7 Not subject to production test, specified by design. 8 Specified RthJA value is according to JEDEC JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the product (chip and package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with two inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu). Where applicable, a thermal via array next to the package contacted the first inner copper layer. OPTIREG™ PMIC TLF30681QVS01 Power management IC General product characteristics Datasheet 16 Rev. 1.0 2020-04-08

3.4 Quiescent current

Tj = -40°C to 150°C; VR1VSx = 9 V to 25 V; unless otherwise specified Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. ACTIVE state Iq,OP – – 20 mA Tj ≤ 85°C;

9 V ≤ VR1VSx ≤ 25 V;

no load, watchdog disabled P_3.4.1 DISABLED state Iq,DIS – 13 17.5 µA Tj ≤ 85°C;

9 V ≤ VR1VSx ≤ 25 V

P_3.4.2 DISABLED state Iq,DIS – 11 13.5 µA Tj = 25°C; VR1VSx = 13.5 V P_3.4.3 FAUL T state Iq,FL T – 1 2 mA Tj ≤ 85°C; P_3.4.4 LOCKED state Iq,LCK – 35 50 µA Tj ≤ 85°C; P_3.4.5 OPTIREG™ PMIC TLF30681QVS01 Power management IC General product characteristics Datasheet 17 Rev. 1.0 2020-04-08

3.5 Typical performance characteristics quiescent current

DISABLED state - quiescent current Iq versus supply voltage VR1VSx LOCKED state - quiescent current Iq versus supply voltage VR1VSx OPTIREG™ PMIC TLF30681QVS01 Power management IC General product characteristics Datasheet 18 Rev. 1.0 2020-04-08

4 Power converters and power management

4.1 High voltage step-down regulator Buck1

4.1.1 Functional description Buck1

The high-voltage step-down regulator Buck1 converts the battery voltage R1VSx to the Buck1 voltage. A synchronous, current-mode-controlled buck converter with internal power switches is integrated for this purpose. The output rail VBuck1 can be used as direct supply rail as well as pre-regulated rail for post- regulators. An integrated driver circuit supplied by an external boot-strap capacitor drives the N-/N-MOS power stage. The integrated dead-time optimization prevents cross-conduction, minimizes dead-time and increases system efficiency. An internal voltage divider sets the output voltage. Internal compensation allows for fast loop performance across a wide range of output capacitance. No external tuning of the loop is required. The device supports ceramic capacitors as well as electrolytic capacitors. For detailed information on the selection of the external power stage components, such as the inductor and the filter capacitors for input and output, see Application information. The converter offers various configuration options:

• Switching frequency selectable via SPI
• Synchronization of the switching frequency to other integrated converters as well as to an external synchronization signal
• Protection features that are designed to prevent damage to the converter due to fault conditions, such as: - Overcurrent detection - Overtemperature detection OPTIREG™ PMIC TLF30681QVS01 Power management IC Power converters and power management Datasheet 19 Rev. 1.0 2020-04-08

V_Buck1 R1SWx R1PGx R1FB R1BTS Clock Generation SYNCO SYNCI SYNC_In SYNC_Out R1VSx Vbat Figure 3 Functional block diagram Buck1 Modulation concept The converter uses several modulation schemes, depending on the operation mode. It uses a PWM scheme in most of the operating area. It supports synchronization to internal and external clock sources. For light-load and high-line operation it uses pulse-skipping operation. This allows for an improved system efficiency and ensures a minimum turn-on time to ensure correct operation of the switches. The converter handles the transition between PWM and pulse-skipping automatically, with the need to configure this. The current thresholds and voltage thresholds for this transition depend on the selected power stage components. Loop compensation The converter uses a cascaded current-mode, voltage-mode control scheme. An inner loop controls the inductor current, while the external voltage compensation loop regulates the output voltage. The compensation loop can operate with a variety of power stages. For information on the selection of the external components see Application information. The dynamic performance of the system is a function of the power stage components and the internal compensation loop. To achieve optimum performance, follow the design considerations in Application information. Cycle-by-cycle current limitation The device features cycle-by-cycle current limitation to protect the switches and external components in case of a fault condition. If the current reaches a defined current threshold, then the peak current monitoring turns off the high-side switch. The device also monitors the current in the low side switch. If the current in the low side switch exceeds the overcurrent threshold at the end of the switching period, then the device does not turn on the high side switch in the subsequent switching period. This allows the device to work as a constant current source. OPTIREG™ PMIC TLF30681QVS01 Power management IC Power converters and power management Datasheet 20 Rev. 1.0 2020-04-08

If the current in the inductor exceeds the overcurrent protection threshold for a defined time tR1OCP, then the device signalizes an overcurrent timeout event through an interrupt (OCSF1.BUCK1OCW). It is up to the application to decide how to react in this situation, for example by shutting down the converter. Overtemperature protection The converter includes an overtemperature warning and shutdown function to protect the device against damage. If the junction temperature exceeds the overtemperature warning threshold, the device sets an overtemperature warning flag OTSF1.BUCK1OTW and it generates an interrupt. If the junction temperature continues to rise and exceeds the overtemperature shutdown threshold, then the converter shuts down and generates a thermal shut-down (TSD) event. It sets the OTSF0.BUCK1OT status flag, which the microcontroller can read after the device enters ACTIVE state again. OTSTAT0.BUCK1OTW contains the current status of the overtemperature warning. OTSF1.BUCK1OTW contains the latched information. So ft start The integrated soft start feature limits the inrush current and allows for a smooth startup of the converter. The device supports power-sequencing with the other output rails, see Power sequencing and soft start. OPTIREG™ PMIC TLF30681QVS01 Power management IC Power converters and power management Datasheet 21 Rev. 1.0 2020-04-08

4.1.2 Electrical characteristics Buck1

Table 5 Electrical characteristics Buck1 Tj = -40°C to 150°C; VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Input voltage – TLF30681QVS01 Output voltage – TLF30681QVS01 Output voltage tolerance VR1FB, TOL -2 – +2 % – P_4.1.2.9 Maximum output current – derated High-side switch on- resistance RDSOn,R1HS – 105 – mΩ 5.0 V ≤ VR1VSx ≤ 35 V P_4.1.2.40 High-side switch on- resistance derated RDSOn,R1HS,D R Low-side switch on- resistance RDSOn,R1LS – 95 – mΩ 5.0 V ≤ VR1VSx ≤ 35 V P_4.1.2.42 Low-side switch on- resistance derated RDSOn,R1LS,D R Overcurrent protection threshold Overcurrent timeout tR1OCP 95 100 115 µs – P_4.1.2.23 Minimum on-time tR1SWx 50 58 72 ns Minimum on-time for internal high side control signal. The actual on-time on the R1SWx pins depends on the application design. P_4.1.2.25 Overtemperature warning threshold Tj,R1OT ,WRN 130 145 160 °C 9)Tj increasing P_4.1.2.26 Overtemperature warning threshold Tj,R1OT ,WRN 120 135 150 °C 9) Tj decreasing P_4.1.2.27 Overtemperature shutdown threshold Tj,R1OT ,FL T 175 190 205 °C 9) Tj increasing P_4.1.2.28 Overtemperature shutdown threshold Tj,R1OT ,FL T 165 180 195 °C 9) Tj decreasing P_4.1.2.29 9 Not subject to production test, specified by design. OPTIREG™ PMIC TLF30681QVS01 Power management IC Power converters and power management Datasheet 22 Rev. 1.0 2020-04-08

Table 5 Electrical characteristics Buck1 (continued) Tj = -40°C to 150°C; VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Bootstrap capacitor CR1BST – 100 – nF – P_4.1.2.30 External power stage components Effective output capacitance CR1 75 100 240 µF 10)11) P_4.1.2.35 ESR of output capacitance RR1C 0 5 30 mΩ – P_4.1.2.36 10 For additional information on the allowed L, C combinations see Application information. 11 Effective capacitance including derating over the temperature range, bias voltage and aging. Electrolytic capacitors as well as ceramic capacitors are supported. OPTIREG™ PMIC TLF30681QVS01 Power management IC Power converters and power management Datasheet 23 Rev. 1.0 2020-04-08

4.1.3 Typical performance characteristics Buck1

Buck1 output voltage VR1FB versus load current IR1IOUT Buck1 output voltage VR1FB versus supply voltage VR1VSx (drop-out region) OPTIREG™ PMIC TLF30681QVS01 Power management IC Power converters and power management Datasheet 24 Rev. 1.0 2020-04-08

4.2 Post-regulator step-down converter Buck2

4.2.1 Functional description Buck2

The low-voltage step-down regulator Buck2 converts the output voltage of Buck1 to the VBuck2 voltage. A synchronous, current-mode-controlled buck converter with internal P-/N-MOS power stage is integrated for this purpose. An internal voltage divider sets the output voltage. Internal compensation allows for fast loop performance across a wide range of output capacitance. No external tuning of the loop is required. The design supports ceramic capacitors as well as electrolytic capacitors. For detailed information on the selection of the external power stage components, such as the inductor and the filter capacitors for input and output, see Application information. Synchronization of the switching frequency with the other integrated converters as well as an external synchronization signal is included. Various protection features, for example overcurrent detection, overtemperature detection and overvoltage detection, are designed to prevent damage to the converter due to fault conditions. Loop compensation The integrated loop compensation requires no external components. The dynamic performance of the system is a function of the power stage components and the internal compensation loop. To achieve optimum performance, follow the design considerations in Application information. Cycle-by-cycle current limitation The device features cycle-by-cycle current limitation to protect the switches and external components in case of fault condition. If the current reaches a defined threshold, then the peak current monitoring turns off the high- side switch. The device also monitors the current in the low side switch. If the current in the low side switch exceeds the overcurrent threshold at the end of the switching period, then the device does not turn on the high side switch in the subsequent switching period. This allows the device to work as a constant current source. If this condition persists for a defined time, then the device signalizes an overcurrent timeout event tR2OCP through an interrupt OCSF1.BUCK2OCW. It is up to the application to decide how to react in this situation, for example by shutting down the converter. Overtemperature protection The converter includes an overtemperature warning and shutdown function to protect the device against damage. If the junction temperature exceeds the overtemperature warning threshold, then the device sets an overtemperature warning flag OTSF1.BUCK2OTW and it generates an interrupt. If the junction temperature continues to rise and exceeds the overtemperature shutdown threshold, then the converter shuts down and generates a thermal shut-down (TSD) event. The device sets the OTSF0.BUCK2OT status flag, which the microcontroller can read after the device enters ACTIVE state again. OTSTAT0.BUCK2OTW contains the current status of the overtemperature warning. OTSF1.BUCK2OTW contains the latched information. Output voltage adjustment via SPI The device features output voltage adjustment via SPI. Therefore, the microcontroller can adjust the output voltage during ACTIVE state using the registers B2VCTRL, B2VCTRLN. Changes to the output voltage must be limited to 50 mV at a time. This means that the register values of B2VCTRL and B2VCTRLN must only be increased or decreased by steps of 1. This is important to avoid false triggering of a Buck2 UV or Buck2 OV event. The settling time of the output voltage for a 50 mV step is 50 µs typically, but it may be longer depending on the output filter selection and the load current condition. Automatic use detection OPTIREG™ PMIC TLF30681QVS01 Power management IC Power converters and power management Datasheet 25 Rev. 1.0 2020-04-08

The integrated automatic use detection for Buck2 allows the system to tell, whether the application uses Buck2. The device checks the input voltage on the R2VSx pins prior to startup of Buck2. If the pins are connected to the output voltage, then a voltage above the detection threshold is present at the pins and the device assumes that the application requires Buck2. HWDECT0.BUCK2AVA stores the result of the detection in order to allow the microcontroller to verify correct detection for the specific application and to differentiate the result from a possible fault present on the PCB. To indicate to the device that the application does not require Buck2, connect the R2VSx pins to R2PGx. So ft start The integrated soft start feature limits the inrush current and allows for a smooth startup of the converter. The device supports power-sequencing with the other output rails, see Power sequencing and soft start. OPTIREG™ PMIC TLF30681QVS01 Power management IC Power converters and power management Datasheet 26 Rev. 1.0 2020-04-08

4.2.2 Electrical characteristics Buck2

Table 6 Electrical characteristics Buck2 Tj = -40°C to 150°C; VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Output voltage adjustment range Output voltage adjustment step size VR2FB,STEP – 50 – mV VR2FB = VR2FB,RANGE P_4.2.2.4 Output voltage tolerance VR2FB, TOL -2 – +2 % – P_4.2.2.10 Maximum output current IR2IOUT 1.0 – – A – P_4.2.2.12 High-side switch on- resistance RDSOn,R2HS – 190 – mΩ VR2VSx = 3.3 V P_4.2.2.32 Low-side switch on- resistance RDSOn,R2LS – 115 – mΩ VR2VSx = 3.3 V P_4.2.2.33 Overcurrent protection threshold IR2,OCP – – 3 A – P_4.2.2.19 Overcurrent timeout tR2,OCP 95 100 115 µs – P_4.2.2.20 Minimum on-time tR2SWx 64 79 87 ns Minimum on-time for internal high side control signal. The actual on-time on the R2SWx pins depends on the application design. P_4.2.2.22 Overtemperature warning threshold Tj,R2OT ,WRN 130 145 160 °C 12) Tj increasing P_4.2.2.23 Overtemperature warning threshold Tj,R2OT ,WRN 120 135 150 °C 12) Tj decreasing P_4.2.2.24 Overtemperature shutdown threshold Tj,R2OT ,FL T 175 190 205 °C 12)Tj increasing P_4.2.2.25 Overtemperature shutdown threshold Tj,R2OT ,FL T 165 180 195 °C 12)Tj decreasing P_4.2.2.26 External power stage components Effective output capacitance CR2 52 66 120 µF 13)14) P_4.2.2.30 12 Not subject to production test, specified by design. 13 For additional information on the allowed L, C combinations see Application information. OPTIREG™ PMIC TLF30681QVS01 Power management IC Power converters and power management Datasheet 27 Rev. 1.0 2020-04-08

Table 6 Electrical characteristics Buck2 (continued) Tj = -40°C to 150°C; VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. ESR of output capacitance RR2C 0 5 30 mΩ – P_4.2.2.31 14 Effective capacitance including derating over the temperature range, bias voltage and aging. Electrolytic capacitors as well as ceramic capacitors are supported. OPTIREG™ PMIC TLF30681QVS01 Power management IC Power converters and power management Datasheet 28 Rev. 1.0 2020-04-08

4.2.3 Typical performance characteristics Buck2

Buck2 output voltage VR2FB versus load current IR2IOUT OPTIREG™ PMIC TLF30681QVS01 Power management IC Power converters and power management Datasheet 29 Rev. 1.0 2020-04-08

4.3 Post-regulator step-up converter Boost1

4.3.1 Functional description Boost1

The device integrates a dedicated step-up converter to generate a 5 V output voltage rail from the Buck1 voltage. The converter uses an asynchronous boost topology with internal low-side switch and an external diode. Synchronization of the switching frequency with the other integrated converters as well as an external synchronization signal is included. Loop compensation The integrated loop compensation requires no external components. For information on the selection of the external components see Application information. Overcurrent protection The integrated overcurrent protection is designed to protect the internal low-side switch of the boost converter. Due to the nature of the boost topology the boost output rail is not protected against a short circuit directly. However, indirect protection via an undervoltage protection and current limitation of the front-end converter Buck1 is available. Automatic use detection The integrated automatic use detection allows the system to tell, whether the application uses Boost1. The device checks the input voltage on the R3FB pin prior to startup of Boost1. If the R3FB pin is connected to the output voltage of Buck1 through the boost inductor and rectifying diode, then a voltage above the detection threshold is present at the pin and the device assumes that the application requires Boost1. HWDECT0.BOOST1 AVA stores the result of the detection in order to allow the microcontroller to verify correct detection for the specific application and differentiate the result from a possible fault present on the PCB. To indicate to the device that the application does not require Boost1, connect the R3FB pin to R3PG. OPTIREG™ PMIC TLF30681QVS01 Power management IC Power converters and power management Datasheet 30 Rev. 1.0 2020-04-08

4.3.2 Electrical characteristics Boost1

Table 7 Electrical characteristics Boost1 Tj = -40°C to 150°C; VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Output voltage VR3FB – 5.0 – V – P_4.3.2.2 Output voltage tolerance VR3FB, TOL -2 – 2 % – P_4.3.2.3 Maximum output current IR3IOUT 250 – – mA – P_4.3.2.4 Overcurrent detection threshold IR3,OCP 740 820 900 mA – P_4.3.2.5 Overcurrent timeout tR3,OCP 170 220 260 µs – P_4.3.2.6 External power stage components Effective output capacitance CR3 5.5 10 18 µF 15)16) P_4.3.2.10 ESR of output capacitance RR3C 1 20 50 mΩ – P_4.3.2.11 15 For additional information on the allowed L, C combinations see Application information. 16 Effective capacitance including derating over the temperature range, bias voltage and aging. Electrolytic capacitors as well as ceramic capacitors are supported. OPTIREG™ PMIC TLF30681QVS01 Power management IC Power converters and power management Datasheet 31 Rev. 1.0 2020-04-08

4.3.3 Typical performance characteristics Boost1

Boost1 output voltage VR3FB versus load current IR3IOUT OPTIREG™ PMIC TLF30681QVS01 Power management IC Power converters and power management Datasheet 32 Rev. 1.0 2020-04-08

4.4 Support of external voltage rails

The device supports monitoring of two externally generated voltage rails via voltage monitors. Each voltage monitor consists of an enable pin VMxEN to control the respective regulator and a monitoring input pin VMxFB to monitor the respective voltage rail. The expected voltage on the monitoring input is fixed. If higher voltages is to be monitored, an external voltage divider may be used to reduce the voltage to the expected range. Automatic use detection The integrated automatic use detection for each voltage monitor allows the system to tell, whether the application uses it. If the device can drive the respective enable pin "high" , then it device assumes that an external power regulator is connected and that the voltage monitoring is used. HWDECT0.VM1AVA and HWDECT0.VM2AVA store the result of the detection, respectively, in order to allow the microcontroller to verify correct detection for the specific application and differentiate the result from a possible fault condition on the PCB. To indicate to the device that the application does not require a voltage monitor, connect the respective enable pin VMxEN to ground.

4.4.1 Electrical characteristics support of external voltage rails

Table 8 Electrical characteristics external voltage rails Tj = -40°C to 150°C, VR1VSx = 9 V to 25 V all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Enable signal VMxEN Output level – "high" VVMxEN,high 0.7 – – VIOVDD IVMxEN = -7 mA P_4.4.0.1 Internal pull-down current IVMxEN 10 – – µA VVMxEN = 0.8 V P_4.4.0.3 Monitoring signals VMxFB Nominal input voltage VVMxFB,nom – 0.8 – V 17) P_4.4.0.4 Input pull-up current IVMxFB – 100 130 nA VVMxFB = 0.8 V P_4.4.0.5 17 For information on the monitoring thresholds please refer to Table 14 in Monitoring of external voltage rails. OPTIREG™ PMIC TLF30681QVS01 Power management IC Power converters and power management Datasheet 33 Rev. 1.0 2020-04-08

5 Central functions

5.1 Supply voltages

The device generates an internal supply voltage from the voltage supplied at the R1VSx pins. This supply voltage R1BTSV power the driver circuit for the power switches of Buck1. R1BTSV cannot be used to supply any external load. A ceramic capacitor for decoupling must be placed between R1BTSV and the respective ground pin in order to handle the dynamic gate drive current of the power switches. A supply voltage is required at the IOVDD pin in order to operate the digital outputs of the device, see Microcontroller interface supply IOVDD pin.

5.1.1 Electrical characteristics supply voltages

Table 9 Electrical characteristics supply voltages Tj = -40°C to 150°C; VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Decoupling capacitor for internal supply Internal supply decoupling – connect between R1BTSV and GND OPTIREG™ PMIC TLF30681QVS01 Power management IC Central functions Datasheet 34 Rev. 1.0 2020-04-08

5.2 Enable functionality

The device features an enable functionality which allows powering up the device using the ENA pin. For example, the ENA pin can be connected to the outside of the ECU or to a wake output of a CAN transceiver. The ENA pin is level-sensitive with a duration-based deglitching. "High" indicates the enabled state. If the voltage at the ENA pin is above the enable detection threshold VENA,high for a minimum time of tENA,det, then the device considers the enable signal "high" , see Figure 4. A signal above the detection threshold for a duration shorter than tENA,filt is not a valid "high" signal. If the voltage at the ENA pin is below VENA,low for a minimum time of tENA,det, then the device considers the enable signal "low" . A signal below the detection threshold for a duration shorter than tENA,filt is not a valid "low" signal. The device incorporates an enable event detection, where a "low" to "high" transition or a "high" to "low" transition of the enable signal is considered an enable event. Upon detection of an enable event the device generates an interrupt SYSSF1-QM.ENA. Depending on the device state, an enable event can trigger a state transition (see State transitions and trigger signals), for example to power up the device. An enable event does not disable the device automatically. It is up to the microcontroller to react to the generated interrupt and react accordingly. VMONSTAT0.ENA stores the state of the enable signal, which the microcontroller can use to determine the current state of the enable signal. This information can be used to differentiate between an enable or disable condition on ECU level. t ENA t ENA,filt Enable Signal t ENA,det Figure 4 Enable signal – enable event timing

5.2.1 ENA pin configurability

The functionality of the ENA pin can be configured by the microcontroller as edge-triggered or level-sensitive in register DEVCFG0.ENA_CONFIG. OPTIREG™ PMIC TLF30681QVS01 Power management IC Central functions Datasheet 35 Rev. 1.0 2020-04-08

The ENA pin is by default configured to be edge triggered. The device can then only detect an ENA event, if the voltage on the pin rises from "low" to "high" . If the configuration of the ENA pin is set to level-sensitive, then the device automatically re-enters the ACTIVE state from any state if the ENA pin is "high" . This means that the device automatically returns to ACTIVE state after a HARD reset event or after entering a LOCKED state with the ENA pin configured to level-sensitive as long as the ENA pin is "high" . The ENA pin must be "low" as a prerequisite for the device to enter DISABLED state from ACTIVE state. If the device enters the DISABLED state on an SPI request to DEVCTRL/DEVCTRLN, then the device resets the DEVCFG0 register to the default value. The device can therefore only recognize an ENA event in DISABLED state if the ENA pin has a "low" to "high" transition.

5.2.2 Electrical characteristics enable

Table 10 Electrical characteristics enable Tj = -40°C to 150°C; VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Enable signal ENA Input voltage hysteresis VENA,hys 200 375 – mV – P_5.2.8 Input current "high" IENA,high – 3 5 µA VENA ≥ 2 V P_5.2.4 Input current "low" IENA,low – – 0.1 µA VENA ≤ 1 V P_5.2.5 Enable signal, filtering time tENA,filt – – 20 µs – P_5.2.6 Enable signal, detection time tENA,det 40 – – µs – P_5.2.7 OPTIREG™ PMIC TLF30681QVS01 Power management IC Central functions Datasheet 36 Rev. 1.0 2020-04-08

5.2.3 Typical performance characteristics enable

ENA pin input voltage thresholds VENA versus junction temperature Tj OPTIREG™ PMIC TLF30681QVS01 Power management IC Central functions Datasheet 37 Rev. 1.0 2020-04-08

5.3 Power sequencing and so ft start

The individual output rails are power sequenced to reduce the inrush current during power-up. The device uses a passive power sequencing method where it enables the individual rails when the preceding rail is within its total operating band, that is between the respective undervoltage and overvoltage fault thresholds. Sequence of the output rails:

• Buck1
• Buck2, Boost1
• (VM1), (VM2) Power sequencing is active any time a power rail is enabled or disabled, for example at the transition to ACTIVE. If the device detects via the automatic use detection that a rail is not active, then power sequencing skips this rail and proceeds with the subsequent rail. The following conditions must be fulfilled for the power sequence to proceed with the next stage:
• The output voltage on the individual rails must be above the undervoltage threshold
• The rise time must be completed before the next stage is reached For example, during ramp-up of Buck1 the device waits until its output voltage exceeds the undervoltage threshold and until the rise time tBuck1 has elapsed before it initiates the ramping of Buck2 and Boost1. Under normal operating conditions the output voltage on Buck1, Buck2 and Boost1 cross their respective undervoltage thresholds before the rise time has elapsed. As soon as the device enables a rail, it also enables the corresponding undervoltage monitoring. However, the device only indicates an undervoltage event once, when the voltage rail crosses the undervoltage threshold for the first time. The short-to-ground detection is active and the device uses it as a timeout function for the power sequencing process. If a voltage rail is not valid within the short-to-ground detection time, then the device indicates a fault event. Depending on the configured response to the short-to-ground event (see Table 25), the device may either move into a different state or continue operation and power sequencing. OPTIREG™ PMIC TLF30681QVS01 Power management IC Central functions Datasheet 38 Rev. 1.0 2020-04-08

VBOOST, UV VVM1,UV VVM2,UV VBUCK2,UV VBUCK1,UV tSTARTUP tBUCK1 tBUCK2 tBOOST1 tStartup,Total tVM1* tRD ROT VM1EN VM2EN Figure 5 Power sequencing The device releases the microcontroller reset signal with a configurable delay once the microcontroller supply voltage is within the operating band for a selectable time period DEVCFG0.RESDEL. For generation of the microcontroller reset signal (ROT) see Reset generation (ROT signal). The external voltage regulator monitored by VM1 must have a rise time, tVM1, that is shorter than the short-to- ground detection time, tVM1,StG, see Table 14. OPTIREG™ PMIC TLF30681QVS01 Power management IC Central functions Datasheet 39 Rev. 1.0 2020-04-08

5.3.1 Electrical characteristics power sequencing and so ft start

Table 11 Electrical characteristics power sequencing and so ft start Tj = -40°C to 150°C; VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Internal device startup time tSTARTUP – 300 – µs – P_5.3.1 Output voltage rise time Buck1 tBUCK1 – 640 – µs VBUCK1 = 3.3 V P_5.3.2 Output voltage rise time Buck2 tBUCK2 – 320 – µs VBUCK2 = 1.25 V P_5.3.4 Output voltage rise time Boost1 tBOOST1 – 640 – µs VBUCK1 = 3.3 V, VBOOST1 = 5.0 V P_5.3.5 OPTIREG™ PMIC TLF30681QVS01 Power management IC Central functions Datasheet 40 Rev. 1.0 2020-04-08

5.4 Frequency generation and clock synchronization

The integrated clock generation and a clock manager generate the switching frequencies for the integrated converters. The device support synchronization to an external clock signal as well as generation of the synchronization signal for external circuits. All all converters support spread spectrum modulation for improved EMC and EMI. Internal Clock Generator Spread- spectrum Modulator Clock Synchroni- zation f Main SYNCI Main Clock Selector f Main Buck1 Selector f R1 Buck2 Selector Boost1 Selector 180° f R2 f R3 SYNCO Selector f SYNCO 180° 180° Figure 6 Clock generation and clock manager Main frequency generation Figure 6 shows that the internal clock generation uses an internal main frequency to derive the switching frequency for the power converters and the external synchronization signal. CLKCFG1 allows to adjust the main frequency of the system within a given range. OPTIREG™ PMIC TLF30681QVS01 Power management IC Central functions Datasheet 41 Rev. 1.0 2020-04-08

The power converters can be synchronized to an external clock signal (SYNCI) to improve EMC and EMI performance and to reduce cross-talk to the loads. Table 12 shows the specification of the signal. The clock manager synchronizes the switching frequency to this signal according to the configuration in the SPI registers. The synchronization functionality is disabled by default. To enable synchronization of the switching frequency, an external reference signal is required at the SYNCI pin and the synchronization functionality must be enabled via SPI. The external clock source must not be removed while the device is running in synchronized mode. The device supports a dynamic change of the synchronization frequency during synchronization mode with minimal disturbance of the output voltage. It is recommended to keep the same phase and change the switching frequency with the next rising edge of the synchronization signal to minimize the impact on the output voltage. The output voltage settles within a maximum time of 50 µs. The synchronization output signal SYNCO can be used to synchronize an external switched-mode post-regulator to the device. The output frequency is equal to the switching frequency of Buck1. The synchronization signal has a 50% duty cycle with a selectable phase shift of 0° or 180° with respect to the main clock. The synchronization output is disabled by default. The synchronization output can be enabled via SPI. CLKCFG0 allows to adjust the phase shift between the individual converters. The phase shift is defined between rising edge of the clock signal and the rising edge of the switch node for the buck converters and the falling edge of the boost converter respectively. Furthermore the converters Buck1 and Buck2, as well as SYNCO can be controlled independently with a phase shift of 0° or 180° with respect to the main clock. Spread spectrum The device incorporates spread spectrum in order to improve EMC and EMI performance. Spread spectrum is applied to the main clock source, so it supports all power converters. Spread spectrum is disabled by default. CLKCFG0.SSEN allows to enable spread spectrum.

5.4.1 Electrical characteristics frequency generation and clock

Table 12 Electrical characteristics frequency generation and clock synchronization Tj = -40°C to 150°C; VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Internal clock source Frequency fMAIN 1800 2200 2500 kHz Switching frequency selectable via SPI P_5.4.1 Frequency tolerance fMAIN,tol -10 – 10 % – P_5.4.3 Frequency adjustment step size fMAIN,step – 100 – kHz – P_5.4.4 Synchronization input signal SYNCI18) Input level "high" VSYNCI, high 0.7 – – VIOVDD VSYNCI increasing P_5.4.5 OPTIREG™ PMIC TLF30681QVS01 Power management IC Central functions Datasheet 42 Rev. 1.0 2020-04-08

Table 12 Electrical characteristics frequency generation and clock synchronization (continued) Tj = -40°C to 150°C; VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Input level "low" VSYNCI, low – – 0.8 V VSYNCI decreasing P_5.4.6 Input level hysteresis VSYNCI, hys – 0.06 – VIOVDD – P_5.4.7 Input capacitance CSYNCI – 4 15 pF 19) P_5.4.8 Frequency range fSync 1600 2200 2800 kHz – P_5.4.9 Duty cycle 40 50 60 % – P_5.4.10 Phase delay between SYNCIN and switching edges Output voltage settling time tSync – – 50 µs – P_5.4.12 Synchronization output signal SYNCO18) Output level "high" VSYNCO, high 0.7 – – VIOVDD IIOVDD = -7 mA P_5.4.13 Output level "low" VSYNCO, low – – 0.7 V IIOVDD = -5.5 mA P_5.4.14 Frequency – fMAIN – – P_5.4.15 Duty cycle – 50 – % – P_5.4.16 Spread spectrum modulation Maximum modulation variation from fMAIN,Range Modulation frequency – 9 – kHz – P_5.4.23

18 The voltage levels on this pin are dependent on the IOVDD supply voltage provided (see

Microcontroller interface supply IOVDD pin). 19 Not subject to production test, specified by design. OPTIREG™ PMIC TLF30681QVS01 Power management IC Central functions Datasheet 43 Rev. 1.0 2020-04-08

5.4.2 Typical performance characteristics frequency generation

Switching frequency fMAIN versus junction temperature Tj OPTIREG™ PMIC TLF30681QVS01 Power management IC Central functions Datasheet 44 Rev. 1.0 2020-04-08

5.5 IOVDD - overvoltage detection and undervoltage detection

The IOVDD pin is the supply voltage input for the communication interface towards the microcontroller. The pin can be supplied from one of the voltages generated by the TLF30681QVS01. The TLF30681QVS01 monitors the voltage on the IOVDD pin. An overvoltage event or an undervoltage event triggers a reset and pulls ROT to GND. As long as no reset event occurs, ROT is "high" (VIOVDD) due to an internal pull-up resistor and follows VIOVDD. Figure 7 shows an example of various events with delay and deglitching times. In addition the TLF30681QVS01 also features a short-to-ground detection for the IOVDD voltage. If the IOVDD voltage is below the undervoltage threshold for a period longer the short-to-ground detection time, then the device generates a short-to-ground event. A short-to-ground event on IOVDD triggers a hard reset in the device and the SYSSF0-QM.IOVDDUV. ROT VIOVDD 1 V VIOVDD,OV VIOVDD,UV t t tRD tRDtRD tIOVDD,deg tIOVDD,deg Figure 7 Overvoltage detection and undervoltage detection

5.5.1 Electrical characteristics IOVDD - overvoltage detection and

Table 13 Electrical characteristics IOVDD - overvoltage detection and undervoltage detection Tj = -40°C to 150°C; VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. IOVDD - overvoltage threshold VIOVDD,OV 5.5 – 5.8 V – P_5.6.1 IOVDD - overvoltage hysteresis VIOVDD,OV,Hys 0.4 – 2.25 % – P_5.6.2 IOVDD - undervoltage threshold VIOVDD,UV 2.74 – 2.86 V – P_5.6.3 OPTIREG™ PMIC TLF30681QVS01 Power management IC Central functions Datasheet 45 Rev. 1.0 2020-04-08

Table 13 Electrical characteristics IOVDD - overvoltage detection and undervoltage detection (continued) Tj = -40°C to 150°C; VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. IOVDD - undervoltage hysteresis VIOVDD,UV,Hys 0.4 – 2.25 % – P_5.6.4 Deglitching time tIOVDD,deg 8 – 20 µs – P_5.6.5 Short-to-ground detection time OPTIREG™ PMIC TLF30681QVS01 Power management IC Central functions Datasheet 46 Rev. 1.0 2020-04-08

6 Monitoring functions

The device incorporates various features for using the device as a supply backbone:

• Integrated voltage monitors for the output voltages, see Voltage monitoring
• Integrated window watchdog for supervising microcontroller timing, see Window watchdog

6.1 Voltage monitoring

6.1.1 Monitoring of R1VSx battery supply

If the battery voltage drops below VR1VSx,UV, then the undervoltage monitoring feature for R1VSx sets the SPI status flag GSF.R1VSxUV.

6.1.2 Monitoring of output voltages

The voltage monitoring function supervises the voltages on the feedback pins R1FB, R2FB and R3FB of the switched-mode converters with respect to the thresholds for undervoltage and overvoltage, see Table 14. The device does not detect a signal as a fault event, which crosses the respective thresholds for a time shorter than the deglitching time. When a signal crosses a threshold for a duration longer than the deglitching time, then the device generates an undervoltage event or an overvoltage event. If the voltage is below the undervoltage threshold for a duration longer than the short-to-ground detection time, then the device generates a short-to-ground event in addition. The monitoring also features deep undervoltage detection for Buck1 and Buck2. If the voltage on the feedback pins R1FB or R2FB drops below the deep undervoltage threshold for a duration longer than the deglitching time, then the device generates a short-to-ground event. Depending on the type of fault, the device executes appropriate according actions, see State transitions and trigger signals. When the device enables a power rail, it activates the respective voltage monitoring automatically. For information on the behavior during power sequencing see Power sequencing and soft start.

6.1.3 Monitoring of external voltage rails

The device supports monitoring of two external voltage rails on the pins VM1FB, VM2FB. The device compares external voltages using window comparators against predefined thresholds. These thresholds define levels relative to the assumed nominal input voltage, see Table 14. Resistor dividers are to be used to map the output voltage of the respective voltage rail externally. Signals crossing the thresholds for a time shorter than the deglitching time are not detected as a fault event. When a signal crosses a threshold for a duration longer than the deglitching time, then the device generates an undervoltage event or an overvoltage event. If the voltage is below the undervoltage threshold for a duration longer than the short-to-ground detection time, then the device generates a short-to-ground event in addition. Depending on the type of fault, the device executes appropriate according actions, see State transitions and trigger signals. When the device enables a power rail, it activates the respective voltage monitoring automatically. For information on the behavior during power sequencing see Power sequencing and soft start. If an overvoltage event or a short-to-ground event occurs, then the device shuts down the respective voltage rail to protect the load and the device. OPTIREG™ PMIC TLF30681QVS01 Power management IC Monitoring functions Datasheet 47 Rev. 1.0 2020-04-08

6.1.4 Monitoring of internal supply voltages and bandgaps

The integrated voltage monitoring function monitors internal supply voltages in order to ensure proper operation. If proper operation can not be ensured, then the device reacts accordingly, see Table 26. The device features two independent voltage references:

• for the voltage regulators
• for voltage monitoring The device supervises the difference between the voltage references internally. If the difference exceeds a predefined warning threshold, then the device generates an interrupt and sets one of the following status flags depending on the internal root cause: SYSSF1-QM.BGWARN1 or SYSSF1-QM.BGWARN 2. Based on this information the system can be designed to react appropriately. If the difference exceeds a predefined fault threshold, then the device shuts down and changes into FAUL T state, as proper operation of the device can not be ensured. Depending on the internal root cause the device sets SYSSF0-QM.BGFLT1 or SYSSF0-QM.BGFLT2.

6.1.5 Electrical characteristics voltage monitoring

Table 14 Electrical characteristics voltage monitoring Tj = -40°C to 150°C; VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Input voltage battery supply – (R1VSx-AGx) Output voltage Buck1 – (R1FB-AGx) Overvoltage threshold VBuck1,OV +6.0 +8.0 +10 % Referenced to Buck1 nominal output voltage VR1FB P_6.1.5.3 Undervoltage threshold VBuck1,UV -6.0 -8.0 -10 % Referenced to Buck1 nominal output voltage VR1FB P_6.1.5.7 Deep undervoltage threshold VBuck1,DUV -38 -40 -42 % – P_6.1.5.9 Deep undervoltage hysteresis VBuck1,DUV,Hy s Deglitching time tBuck1,deg 8 - 20 µs – P_6.1.5.11 OPTIREG™ PMIC TLF30681QVS01 Power management IC Monitoring functions Datasheet 48 Rev. 1.0 2020-04-08

Table 14 Electrical characteristics voltage monitoring (continued) Tj = -40°C to 150°C; VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Short-to-ground detection time Output voltage Buck2 (R2FB-AGx) Overvoltage threshold VBuck2,OV +6.0 +8.0 +10 % Referenced to Buck2 nominal output voltage VR2FB P_6.1.5.16 Undervoltage threshold VBuck2,UV -6.0 -8.0 -10 % Referenced to Buck2 nominal output voltage VR2FB P_6.1.5.20 Deep undervoltage threshold Deep undervoltage hysteresis VBuck2,DUV,Hy s Deglitching time tBuck2,deg 8 - 20 µs – P_6.1.5.25 Short-to-ground detection time Output voltage Boost1 – (R3FB-AGx) Overvoltage threshold VBoost1,OV +6.0 +8.0 +10 % Referenced to Boost1 nominal output voltage VR3FB P_6.1.5.28 Overvoltage hysteresis VBoost1,OV,Hy s Undervoltage threshold VBoost1,UV -6.0 -8.0 -10 % Referenced to Boost1 nominal output voltage VR3FB P_6.1.5.32 Undervoltage hysteresis VBoost1,UV,Hy s Deglitching time tBoost1,deg 8 - 20 µs – P_6.1.5.35 Short-to-ground detection time External voltage monitors VM1 (VM1FB-AGx) OPTIREG™ PMIC TLF30681QVS01 Power management IC Monitoring functions Datasheet 49 Rev. 1.0 2020-04-08

Table 14 Electrical characteristics voltage monitoring (continued) Tj = -40°C to 150°C; VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Overvoltage threshold VVM1,OV +6.0 +8.0 +10 % Referenced to VM1 nominal reference voltage VVM1FB,nom P_6.1.5.38 Undervoltage threshold VVM1,UV -6.0 -8.0 -10 % Referenced to VM1 nominal reference voltage VVM1FB,nom P_6.1.5.42 Deglitching time tVM1,deg 8 - 20 µs – P_6.1.5.45 Short-to-ground detection time External voltage monitor VM2 (VM2FB-AGx) Overvoltage threshold VVM2,OV +6.0 +8.0 +10 % Referenced to VM2 nominal reference voltage VVM2FB,nom P_6.1.5.48 Undervoltage threshold VVM2,UV -6.0 -8.0 -10 % Referenced to VM2 nominal reference voltage VVM2FB,nom P_6.1.5.52 Deglitching time tVM2,deg 8 - 20 µs – P_6.1.5.55 Short-to-ground detection time

6.2 Thermal protection

The device incorporates multiple independent temperature sense elements to monitor its temperature, specifically of the high-voltage regulator Buck1 and the post-regulator Buck2. Please refer to the respective sections for more information on the individual blocks. A third temperature sensor is located in the monitoring block of the device. Table 15 shows the temperature thresholds for the sensor in the monitoring block. While the device monitors temperature in the individual blocks, it collects the thermal shutdown (TSD) events of these measurements globally. The device sets an appropriate bit in the SPI registers OTSF0 and OTSF1 for each individual warning and fault event. An overtemperature warning event for any of the three temperature sensors generates an interrupt for the microcontroller. OPTIREG™ PMIC TLF30681QVS01 Power management IC Monitoring functions Datasheet 50 Rev. 1.0 2020-04-08

A thermal shutdown event (TSD) for any of the three sensors triggers a move to the FAUL T state. If a thermal shutdown event occurs, then the device extends the fault time to approximately one second (see Table 27) in order to allow the temperature to drop prior to the restart of the device.

6.2.1 Electrical characteristics temperature sensor monitoring block

Table 15 Electrical characteristics temperature sensor monitoring block VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Overtemperature warning threshold Tj,MONOT ,WRN 130 145 160 °C 20)Tj increasing P_6.2.0.1 Overtemperature warning threshold Tj,MONOT ,WRN 120 135 150 °C 20)Tj decreasing P_6.2.0.2 Overtemperature fault threshold Tj,MONOT ,FL T 175 190 205 °C 20)Tj increasing P_6.2.0.3 Overtemperature fault threshold Tj,MONOT ,FL T 165 180 195 °C 20) Tj decreasing P_6.2.0.4 20 Not subject to production test, specified by design. OPTIREG™ PMIC TLF30681QVS01 Power management IC Monitoring functions Datasheet 51 Rev. 1.0 2020-04-08

7 Microcontroller interface and supervisory functions

This section describes the connections between the device and the microcontroller. Figure 8 shows that the microcontroller and the device use several signals for communication and for mutual monitoring of correct operation. An SPI configures the device and monitors status information. A dedicated interrupt signal of the device notifies the microcontroller about any interaction required. To ensure safe operation of the microcontroller a watchdog trigger line (WDI) is available. The device can use a reset-output signal (ROT) to reset the microcontroller if required. Series Protection resistors µC SPI SPI Reset Control Window Wacthdog Interrupt Generator Reset GeneratorROT WDI SDO SDI SCL SCS INT IOVDD TRIGGER OUTPUT INTERRUPT INPUT µC TLF30681 Figure 8 Interface between device and microcontroller

7.1 Microcontroller interface supply IOVDD pin

The device can handle microcontrollers with different IO supply voltages. This is accommodated by a dedicated supply pin (IOVDD) at which the IO supply voltage is externally supplied to the device. This voltage then drives the logic output pins to the microcontroller. It is also used to determine the input thresholds for the input cells. The affected pins are:

• SCS
• SCL
• SDI
• SDO
• INT
• ROT OPTIREG™ PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 52 Rev. 1.0 2020-04-08

• WDI
• SYNCI
• SYNCO OPTIREG™ PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 53 Rev. 1.0 2020-04-08

7.1.1 Electrical characteristics microcontroller interface supply

Table 16 Electrical characteristics microcontroller interface supply Tj = -40°C to 150°C; VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Microcontroller interface Supply current IIOVDD – 2.5 – mA VIOVDD = 3.3 V; SDO, SDI and SCL switching at

10 MHz;

2.5 MHz;

SCS, ROT , INT and WDI are static signals P_7.1.1.2 OPTIREG™ PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 54 Rev. 1.0 2020-04-08

7.2 Serial peripheral interface (SPI)

7.2.1 SPI introduction

The serial peripheral interface (SPI) is a synchronous serial data link that operates in full duplex mode. The SDI pin receives data from the microcontroller and the SDO pin transmits data to the microcontroller. The device communicates in slave mode where the master, for example the microcontroller, provides a clock on the SCL pin and initiates the data frame. The device is addressed via a dedicated chip select line (SCS pin). Functional description SPI The data on pin SDI is captured on the falling edge of the SPI clock signal (pin SCL) and shifted on the rising edge of the SPI clock signal. The data on pin SDO is set on the falling edge of SPI clock signal (pin SCL) and shifted on the rising edge of the SPI clock signal. The SPI master is to capture the data on the falling edge of the SPI clock signal. An SPI command consists of the following parts, see Figure 9:

• command bit CMD
• 6 address bits A0-A5
• 8 data bits D0-D7
• parity bit P The SPI response for read operations consists of the following parts:
• command bit CMD
• 6 status bits S0-S5
• 8 data bits D0-D7
• parity bit P For a write operation, the data read on SDI is looped back via SDO. A5CMD t trail t lead t interframe t spi_clk SCL SCS SDO (R) SDI t max frame duration A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 PP A51'b1 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 PPSDO (W) 1'b01'b1 1'b0 1'b0 1'b0 1'b0 1'b0 D7 D6 D5 D4 D3 D2 D1 D0 PP Figure 9 SPI frame format The command bit in the SPI command is set to 1’b0 for a read and 1’b1 for a write operation. In the reply, the command bit is always set to 1’b1. The parity bit P is calculated from the 15 data bits of the SPI message consisting of the CMD bit, the 6 address bits and the 8 data bits. The parity bit is set to ‘1’ , if the number of ‘1’s in the data bits is odd, that is it is a XOR function of the 15 data bits. The receiver of the SPI message should verify the parity bit prior to processing the payload of the message. The SPI performs several checks on the communication to ensure proper behavior: OPTIREG™ PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 55 Rev. 1.0 2020-04-08

• If a parity fault occurs, then the device ignores the data, sets the SPI status bit SPISF.PAR and generates an interrupt.
• If a write operation to an invalid address occurs, then the device ignores the data, sets the SPI status SPISF.ADDR and generates an interrupt.
• If a read operation from an invalid address occurs, then the device reads all data bits as zero and sets the parity bit to a wrong value in order to indicate an incorrect message to the SPI master. In addition the device sets the SPI status bit SPISF.ADDR and generates an interrupt.
• If a write operation with an incorrect number of SPI clock cycles occurs while SCS is "low" , then the device ignores the data, sets the SPI status SPISF.LEN and generates an interrupt.
• If a read operation with an incorrect number of SPI clock cycles occurs, then the device sets the SPI status SPISF.LEN and generates an interrupt to indicate an invalid data message to the SPI master. The SDO pin provides the data during this operation. At the end of the message it indicates its correctness.
• If the frame duration exceeds the maximum frame time tSPI_fl, then the device terminates communication by disabling the output driver of the SDO pin. In addition the device sets the SPI status bit SPISF.DUR and generates an interrupt. The device initiates interrupts on SPI errors are only after SCS is driven "high" or after a frame timeout occurs. OPTIREG™ PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 56 Rev. 1.0 2020-04-08

7.2.2 SPI write access to protected registers

Certain registers are protected against accidental write operations. Those protected registers are implemented in pairs, where a protected register (for example PWDCFG0) is used to store a configuration request, while an associated read-only register (for example RWDCFG0) is used to store the currently active configuration. By default, write access to protected registers is disabled. The status of the protection can be checked using PROTSTAT.LOCK. Write access must be enabled using the UNLOCK sequence prior to updating the registers. After completing the register update, the configuration must be activated using the LOCK sequence. This disables the write access to the protected register and copies the data to the read-only registers. After the LOCK sequence an internal configuration time of maximum of 60 µs must be considered to ensure that the new configuration is applied in the device. Read access to protected configuration registers is always possible. Read operations invert the data. The device does not support updating a single protected register. The microcontroller must ensure that all protected registers are configured properly by writing a new value into particular registers and by verifying the content of unchanged registers. UNLOCK sequence An UNLOCK sequence consists of four consecutive key bytes (1: ABH; 2: EFH; 3: 56H; 4: 12H) written into the PROTCFG register. The respective SPI write operations must be atomic, so that they are not interrupted by an SPI write operation to a different register. Read operations to any register are permitted. The progress of the UNLOCK sequence can be monitored in the PROTCFG register where the respective key bit is set for each correctly written key byte. If an incorrect UNLOCK sequence occurs due to a wrong key or an SPI write operation to a different address, then the device resets the UNLOCK sequence and clears all key bits. The device sets the SPISF.LOCK bit and generates an interrupt. The microcontroller must restart the UNLOCK sequence. LOCK sequence A LOCK sequence consists of four consecutive key bytes (1: DFH; 2: 34H; 3: BEH; 4: CAH) written into the PROTCFG register. The respective SPI write operations must be atomic, so that they are not interrupted by an SPI write operation to a different register. Read operations to any register are permitted. The progress of the LOCK sequence can be monitored in the PROTCFG register where the respective key bit is set for each correctly written key byte. If an incorrect LOCK sequence occurs due to a wrong key or an SPI write operation to a different address, then the device resets the LOCK sequence and clears all key bits. The device sets the SPISF.LOCK bit and generates an interrupt. The microcontroller must restart the LOCK sequence. OPTIREG™ PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 57 Rev. 1.0 2020-04-08

7.2.3 SPI write initiated state transition request and regulator

State machine transitions and configuration of output rails can be performed with direct write access to dedicated registers. A defined protocol protects the registers from unintended changes. In order to request a state transition or a change of the configuration of an output rail the request data must be written to two separate, inverted registers (DEVCTRL and DEVCTRLN). The write operation must be atomic, with no other SPI write operation to a different address interrupting the initial write. The data is applied on the rising edge of the CS at the end of the second command. If an invalid protocol occurs, then the device rejects the request, sets the SPI status flag SPISF.DEVCTRL and generates an interrupt. The following conditions lead to invalid requests:

• An SPI write operation to a different address, which interrupts the write operation to DEVCTRL and DEVCTRLN
• The data in DEVCTRL and DEVCTRLN is not consistent If an invalid state transition request occurs, according to the state machine in Chapter 8, then the device ignores the transition request without generating an interrupt. The device executes the change in configuration of output rails.

7.2.4 Configuration of Buck2 output voltage via SPI

The output voltage of Buck2 can be configured with direct write access to dedicated registers. A specific protocol is used to avoid unwanted changes to the registers. In order to request a change of the Buck2 output voltage the configuration data must be written to two separate, inverted registers (B2VCTRL and B2VCTRLN). The write operation must be atomic with no other SPI write operation to a different address interrupting the initial write. The data is applied on the rising edge of the CS at the end of the second command. If an invalid protocol occurs, the device rejects the request, sets the SPI status flag SPISF.B2VCTRL and generates an interrupt. The following conditions lead to invalid requests:

• An SPI write operation to a different address, which interrupts the write operation to B2VCTRL and B2VCTRLN.
• The data in B2VCTRL.B2VOUTF and B2VCTRLN.B2VOUTF is not consistent. If a Buck2 output voltage configuration request is invalid, then the device ignores the request without generating an interrupt. OPTIREG™ PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 58 Rev. 1.0 2020-04-08

7.2.5 SPI timing

N M K DE BA C F G L H I Q A : t SPI_wsclkl B : t SPI_wsclkh C : t SPI_clk D : t SPI_clkr E : t SPI_clkf F : t SPI_su G : t SPI_hi H : t SPI_a I : t SPI_v J : t SPI_fl K : t SPI_dis L : t SPI_lead M : t SPI_lag N : t SPI_td O : t SPI_csf P : t SPI_csr Q : t SPI_dr J Figure 10 SPI timing OPTIREG™ PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 59 Rev. 1.0 2020-04-08

7.2.6 Electrical characteristics SPI

Table 17 Electrical characteristics SPI Tj = -40°C to 150°C; VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. SPI chip select SCS Valid input level "high" VSCS, high 0.7 – – VIOVDD VSCS increasing P_7.2.5.1 Valid input level "low" VSCS, low – – 0.8 V VSCS decreasing P_7.2.5.2 Input hysteresis VSCS, hys – 0.06 – VIOVDD – P_7.2.5.3 Pull-up current ISCS -180 -55 – µA VIOVDD ≤ 5.0 V P_7.2.5.4 Input capacitance CSCS – 4 15 pF 21) P_7.2.5.5 SPI clock SCL Valid input level "high" VSCL, high 0.7 – – VIOVDD VSCL increasing P_7.2.5.6 Valid input level "low" VSCL, low – – 0.8 V VSCL decreasing P_7.2.5.7 Input hysteresis VSCL, hys – 0.06 – VIOVDD – P_7.2.5.8 Pull-up current ISCL -180 -55 – µA VIOVDD ≤ 5.0 V P_7.2.5.9 Input capacitance CSCL – 4 15 pF 21) P_7.2.5.10 SPI data input SDI Valid input level "high" VSDI, high 0.7 – – VIOVDD VSDI increasing P_7.2.5.11 Valid input level "low" VSDI, low – – 0.8 V VSDI decreasing P_7.2.5.12 Input hysteresis VSDI, hys – 0.06 – VIOVDD – P_7.2.5.13 Pull-down current ISDI – 135 330 µA VSDI = VIOVDD P_7.2.5.14 Input capacitance CSDI – 4 15 pF 21) P_7.2.5.15 SPI data output SDO Output level "high" VSDO, high 0.7 – – VIOVDD ISDO = -7 mA P_7.2.5.16 Output rise time tSDO,rise – – 25 ns CSDO,Load = 50 pF P_7.2.5.18 Output fall time tSDO,fall – – 25 ns CSDO,Load = 50 pF P_7.2.5.19 Output tristate capacitance CSDO,tri – 4 15 pF 21) P_7.2.5.20 Output tristate leakage ISDO,tri -10 – 10 µA – P_7.2.5.21 21 Not subject to production test, specified by design. OPTIREG™ PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 60 Rev. 1.0 2020-04-08

7.2.7 Electrical characteristics SPI timing

Table 18 Electrical characteristics SPI timing Tj = -40°C to 150°C; VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. CLK_SPI operating frequency fSPI_clk – – 10 MHz – P_7.2.5.22 CLK signal duty cycle DSCL 45 50 55 % – P_7.2.5.23 CLK_SPI "high" time tSPI_wsclkh 45 – – ns – P_7.2.5.24 CLK_SPI "low" time tSPI_wsclkl 45 – – ns – P_7.2.5.25 CLK_SPI fall time tSPI_clkf – – 100 ns fSPI_clk < 1 MHz P_7.2.5.26 CLK_SPI fall time tSPI_clkf – – 0.1/fSPI_clk ns fSPI_clk ≥ 1 MHz P_7.2.5.27 CLK_SPI rise time tSPI_clkr – – 100 ns fSPI_clk < 1 MHz P_7.2.5.28 CLK_SPI rise time tSPI_clkr – – 0.1/fSPI_clk ns fSPI_clk ≥ 1 MHz P_7.2.5.29 CLK_SPI lead time tSPI_lead 100 – – ns – P_7.2.5.30 CLK_SPI lag time tSPI_lag 50 – – ns – P_7.2.5.31 SPI chip select (SCS) rise time tSPI_csr – – 200 ns tSPI_lead = 100 ns P_7.2.5.32 SPI chip select (SCS) rise time tSPI_csr – – 0.2 × tSPI_lead ns tSPI_lead > 100 ns P_7.2.5.33 SPI chip select (SCS) rise time tSPI_csf – – 200 ns tSPI_lead = 100 ns P_7.2.5.34 SPI chip select (SCS) fall time tSPI_csf – – 0.2 × tSPI_lead ns tSPI_lead > 100 ns P_7.2.5.35 SPI data input (SDI) setup tSPI_su 10 – – ns – P_7.2.5.36 SPI data input (SDI) hold time tSPI_hi 10 – – ns – P_7.2.5.37 SPI data output (SDO) valid after CLK_SPI fSPI_clk) ns CSDO,load = 50 pF; fSPI_clk ≥ 1 MHz P_7.2.5.38 SPI data output (SDO) valid after CLK_SPI tSPI_v – – 136 ns CSDO,load = 50 pF; fSPI_clk < 1 MHz P_7.2.5.39 SPI write propagation delay SDI to SDO tSPI_wpd – – 35 ns – P_7.2.5.40 SPI data output (SDO) access tSPI_a – – 50 ns CSDO,load = 50 pF P_7.2.5.41 SPI data output (SDO) lag tSPI_lag 50 – – ns – P_7.2.5.42 OPTIREG™ PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 61 Rev. 1.0 2020-04-08

Table 18 Electrical characteristics SPI timing (continued) Tj = -40°C to 150°C; VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. SPI data output (SDO) disable time tSPI_dis – – 100 ns CSDO,load = 50 pF P_7.2.5.43 Sequential transfer delay tSPI_td 350 – – ns – P_7.2.5.44 Frame duration (SCS "low") tSPI_fl – – 1.85 ms – P_7.2.5.45 OPTIREG™ PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 62 Rev. 1.0 2020-04-08

7.3 Reset generation (ROT signal)

The reset output pin ROT is an open drain structure. As soon as a reset condition occurs, the device pulls the ROT pin below VROT ,low. Once the internal reset signal is released, an internal pull-up current pulls the ROT pin towards the microcontroller supply voltage VIOVDD. An external pull-up resistor can be connected between the ROT and IOVDD pins to speed up the transition. As soon as all events leading to the reset are cleared and the reset delay time expires, the device releases the internal reset signal. Reset events Different internal events can trigger a reset signal, see Table 26 for details. Depending on the severity of the error event the device triggers a reset of the following types:

• soft reset: the device forces the ROT pin "low" , remains in ACTIVE state and keeps all supply voltages on
• hard reset: the device forces the ROT pin "low" , enters FAUL T state and turns all supply voltages off

7.3.1 Electrical characteristics ROT

Table 19 Electrical characteristics ROT Tj = -40°C to 150°C; VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Reset output ROT Pull-up current IROT ,high -180 -120 – µA VROT ≤ 2.0V P_7.3.1.1 Output level "low" VROT ,low – – 0.4 V VIOVDD = 5.0 V; IROT = 3.5 mA P_7.3.1.2 Output level "low" VROT ,low – – 0.4 V VIOVDD =3.3 V; IROT = 3.5 mA P_7.3.1.3 Output fall time tROT ,fall – – 25 ns CROT ,load = 50 pF P_7.3.1.5 Reset timing Reset cycle time tcycle – 10 – µs – P_7.3.1.6 Reset delay time adjustment range tRD 20 – 2000 tcycle – P_7.3.1.7 Reset delay time default value – 100 – tcycle 22) P_7.3.1.8 22 The default configuration for the reset contributor might not generate a reset at the first start up of the device. OPTIREG™ PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 63 Rev. 1.0 2020-04-08

7.4 Interrupt generation (INT signal)

A dedicated interrupt generation block is implemented which is handling requests from independent sources to generate an interrupt. The different requesters are as follows:

• State machine in case: - A requested state transition has not been performed successfully - A requested state transition has been performed successfully, the microcontroller may only send (additional) SPI commands after an interrupt event has been generated by the system. The purpose of the interrupt event is to inform the microcontroller that a state transition has been performed successfully and that the system can perform SPI communication at full SPI speed.
• Watchdog, an interrupt request is generated if the watchdog is not serviced properly and configured in a way to allow service errors to occur, i.e. an error counter threshold value of more than 2 is configured. In this case an interrupt is generated only if the error counter threshold is not exceeded due to this error
• Error pin monitoring, an interrupt request is generated if the error pin monitoring block detects an error and is configured in a way to allow occurrence of this error for a certain amount of time (recovery delay action enabled). In this case an interrupt is requested if an error is detected by the error pin monitoring and the recovery delay has not expired
• Monitoring Block, an interrupt request is generated based on the defined system reaction.
• Overtemperature warnings and over temperature shutdown of communication LDO.
• Overcurrent conditions of voltage reference or standby LDO.
• SPI block in case an SPI error has occurred.
• Double bit error in the protected configuration. The device generates an interrupt to inform the connected microcontroller that a non-severe event has occurred. This allows the microcontroller to take proper action based on the source of the interrupt. A single interrupt line exists, which is high on default. All Internal interrupt sources are enabled by default and cannot be disabled. An interrupt is signaled by pulling the interrupt line low for at least tINT (interrupt min. pulse width) after an internal interrupt condition occurs. The interrupt line will be driven high if all of the GSF register flag(s) has/ have been cleared via SPI operation earliest after tINT has expired but latest after tINTTO has expired. Special cases:
• If an interrupt is signaled by pulling INT low and not all interrupt status flags are cleared by the microcontroller within tINTTO, the INT will stay low until tINTTO has expired, but no additional interrupt will be generated. Information about a pending interrupt event can be derived via the INTMISS status flag. This status flag is cleared each time the interrupt line is driven low.
• If an interrupt is signaled by pulling INT low and an additional bit is set in the GSF register interrupt flag after the interrupt bits have been read by the microcontroller and this outdated information is used to clear the interrupt flags, the interrupt line will stay low until tINTTO has expired, but no additional interrupt will be generated. Information about a pending interrupt event can be derived via a status flag
• After releasing the interrupt line to high, the interrupt line will stay high for at least tINTTO regardless if any additional internal interrupt condition has occurred or not. If a new interrupt event occurs during the delay time out ( tINTTO), this will be signaled by generating a new pulse after the delay time out tINTTO All interrupt sources can only be cleared by a "write-1-to-clear" (w1c) SPI operation, i.e. writing a logic one to the corresponding bit(s) in the interrupt register will clear the event Interrupt events are organized in a two level approach. The first level (interrupt flag) provides information about different groups of interrupt events. The second level (status flags) provides detailed information about which particular event(s) generated the interrupt. To service an interrupt one would only need to write the interrupt flag register. The status flag registers are only meant to provide detailed information. However all status flags can be cleared as well OPTIREG™ PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 64 Rev. 1.0 2020-04-08

An interrupt is only generated after the reset signal to the microcontroller has been released. An interrupt event which occurred while the reset line for the microcontroller is still active is not signaled at the interrupt line but the particular status bit for this event is set. Details about the timing of the interrupt line are depicted in Figure 11. t POR HIGH LOW FSM State t Internal interrupt request SPI service done t POR ACTIVE HIGH LOW t Interrupt line tSPI service done SPI service done HIGH LOW t HIGH LOW t INT not serviced flag (previously set) INT not serviced flag (previously cleared) tINT tINTTO tINTTO tINTTO tINTTO Figure 11 Interrupt timing Details about the system behavior in case not all interrupt status flags have been cleared are depicted in Figure 12. OPTIREG™ PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 65 Rev. 1.0 2020-04-08

t POR HIGH LOW FSM State t Internal interrupt request t POR ACTIVE HIGH LOW t Interrupt line tSPI service done HIGH LOW t HIGH LOW t INT not serviced flag (previously set) INT not serviced flag (previously cleared) tINTTO tINTTOtINTTO tINTTO Figure 12 Interrupt timing without service in time

7.4.1 Electrical characteristics INT

Table 20 Electrical characteristics INT Tj = -40°C to 150°C; VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Interrupt signal INT Output level "high" VINT ,high 0.7 – – VIOVDD IINT = -7 mA P_7.4.1.1 Output rise time tINT ,rise – – 25 ns CINT ,load = 50 pF P_7.4.1.3 Output fall time tINT ,fall – – 25 ns CINT ,load = 50 pF P_7.4.1.4 Minimum interrupt "low" time tINT ,low 90 100 110 µs – P_7.4.1.5 OPTIREG™ PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 66 Rev. 1.0 2020-04-08

Table 20 Electrical characteristics INT (continued) Tj = -40°C to 150°C; VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Interrupt "low" timeout tINTTO 270 300 330 µs ROT signal for the microcontroller must be released: ROT = "high" P_7.4.1.6 Minimum interrupt "high" time tINT ,high 270 300 330 µs – P_7.4.1.7 OPTIREG™ PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 67 Rev. 1.0 2020-04-08

7.5 Window watchdog

The integrated window watchdog (WWD) can monitor the microcontroller. The microcontroller monitored must provide periodical triggering during the open windows. Depending on the configuration a trigger event is

• a falling edge on the WDI pin
• an SPI write operation to the register WWDSCMD After a trigger event the window watchdog indicates either valid WWD triggering or invalid WWD triggering to the WWD error counter and the device terminates the open window. On valid WWD triggering the device starts a closed window. If there is no triggering during the open window or if triggering occurs during a closed window, then the window watchdog output indicates invalid WWD triggering to the WWD error counter and a new open window starts. If the microcontroller does not trigger the window watchdog with a correct timing, then the device indicates that to the microcontroller. If multiple error events occur, then the device sets ROT "low" . Window Watchdog (WWD)SPI Invalid WWD triggering Valid WWD triggering Window Watchdog Failure counter WWO Interrupt or Reset generation WDI WWO Figure 13 Window watchdog principle of operation Configuration The following parameters of the window watchdog can be configured via SPI in ACTIVE:
• The trigger signal can be configured to be pin triggered (pin WDI) or SPI triggered command (register WWDSCMD). The default configuration is the triggering via SPI.
• The duration of the open window and closed window cycles can be modified according to the application needs (combination of cycle time and number of cycles for open window and closed window CW).
• The threshold for the window watchdog error counter overflow can be configured via SPI. Initialization As soon as the device sets ROT "high" in INIT state, it activates the window watchdog. After activation the watchdog opens a long open window (LOW) with a duration of tLOW. With the default configuration the window watchdog expects a valid trigger event via SPI during the long open window, while it ignores WDI pin signals. Therefore, glitches at the microcontroller output connected to the WDI have no effect during startup and initialization. During the long open window cycle the microcontroller can change the window watchdog trigger source as well as the timing of the open window and of the closed window. On reconfiguration the window watchdog restarts with the new configuration. The window watchdog starts a regular open window cycle, waiting for a valid trigger signal from the selected trigger source. If no valid triggering or configuration of the watchdog occurs during the long open window, then the window watchdog recognizes invalid WWD triggering. If the INIT timer expires while invalid WWD triggering persists, then the device generates a soft reset and it sets the ROT pin to "low" . After the soft reset the window watchdog OPTIREG™ PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 68 Rev. 1.0 2020-04-08

starts a new long open window without indicating an interrupt. The number of repeated long open windows is limited. If the window watchdog does not recognize valid triggering during the second long open window, then the device generates a hard reset, so it enters FAUL T state and it switches off the post regulator output voltages. Normal operation On a valid trigger signal during long open window the window watchdog terminates that window and starts a closed window. The closed window has a fixed duration for operation without invalid triggering. On an in itself valid trigger signal during the closed window the window watchdog recognizes invalid WWD triggering. The window watchdog then terminates the closed window with an invalid trigger signal and starts another open window. Each Invalid WWD triggering increments the window watchdog error counter by 2 and the device indicates an interrupt. After the closed window the window watchdog starts an open window. If the window watchdog detects a valid trigger signal during the open window, then it terminates that window and starts the closed window. If the value of the window watchdog error is greater than 0, then valid WWD triggering decrements the window watchdog error counter by 1. If no valid triggering occurs during the open window, then the window watchdog recognizes invalid WWD triggering and increments the window watchdog error counter by 2, it starts a new open window and the device indicates an interrupt. As long as the window watchdog detects valid triggering during normal operation, it continues to cycle between the open window and the closed window. Window watchdog output WWO The window watchdog output WWO is an internal signal. It is connected to the safe window watchdog error counter. The possible values of WWO are:

• valid WWD triggering
• invalid WWD triggering No Trigger Trigger Open Window (OW) Closed Window (CW) Long Open Window (LOW) Trigger Valid WWD triggering Invalid WWD triggering No Trigger Initialization Normal Operation Status of WWO No Trigger Trigger No Trigger Figure 14 Watchdog state diagram Description:
• Trigger is either an SPI write operation to register WWDSCMD or a valid watchdog trigger signal at pin WDI.
• No trigger during the long open window is invalid WWD triggering. The window watchdog opens a new a long open window. OPTIREG™ PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 69 Rev. 1.0 2020-04-08

• A trigger during the closed window is invalid WWD triggering.
• No trigger during the closed window results in an open window after the closed window.
• A trigger during the open window is valid WWD triggering. The window watchdog closes the open window and opens the closed window.
• No trigger during the open window is invalid WWD triggering. Watchdog input WDI The watchdog input WDI has an integrated pull-down current source IWDI. The watchdog input WDI can have a transition to "high" during the closed window or during the subsequent open window. Valid trigger signal at WDI The window watchdog samples the watchdog input WDI periodically with a period of tSAM. A falling edge from WWDI,high to WWDI,low is a valid trigger signal. To improve immunity against both noise and glitches on the WDI pin, the device requires at least two "high" samples followed by two "low" samples for a valid trigger signal. Whether the triggering is valid, the window watchdog decides at the time of the second consecutive "low" sampling point. For example, if the first three samples (two "high" , one "low") of the trigger pulse at pin WDI are within the closed window and only the fourth sample (the second "low" sample) is in the open window, then the watchdog output WWO indicates valid WWD triggering. Invalid triggering at WDI If the window watchdog does not detect a trigger signal during the open window or if it detects a trigger signal during the closed window, then this is invalid triggering. The watchdog output WDO indicates invalid triggering after no valid trigger during the open window or if it detects a trigger signal during the closed window. Figure 15 Valid and invalid trigger pulses at WDI pin OPTIREG™ PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 70 Rev. 1.0 2020-04-08

7.5.1 Window watchdog timing

Normal operation: correct trigger Long Open Window Closed Window Open Window Closed Window ROT WDI fixedvariable fixedvariable 2 3 4 Valid WWD triggering Invalid WWD triggering immediately immediately WWDSCMD Figure 16 Normal operation: correct trigger 1. If the reset output ROT turns to "high" in ACTIVE state, then the window watchdog starts a long open window. The duration of the first long open window depends on the configured cycle time: 600 ms (WDCYC = 1) or 60 ms (WDCYC = 0). 2. During the long open window the window watchdog waits for valid WWD triggering according to the trigger configuration. The maximum duration of the long open window is fixed. On valid WWD triggering the window watchdog terminates the long open window. 3. The window watchdog starts the closed window. 4. The closed window has a fixed duration of tWD,CW, which can be configured via SPI. The closed window starts after the valid trigger signal, that terminates the open window or after the long open window. A transition from "low" to "high" at the WDI pin does not lead to a trigger event. 5. On a valid trigger signal the window watchdog terminates the open window. The duration of the open window depends on when the microcontroller schedules the triggering. This is an example of valid WWD triggering. OPTIREG™ PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 71 Rev. 1.0 2020-04-08

Fault: no trigger during open window after initialization Long Open Window ROT WDI variable immediately 1 2 3 4 FAULT! Valid WWD triggering Invalid WWD triggering WWDSCMD Closed Window fixed Long Open Window Figure 17 Fault operation: No trigger in open window after initialization 1. The initialization timeout usually finishes slightly before or at the same time as the long open window, which skips the interrupt event. However, the missing valid triggering within the long open window can still lead to an interrupt event after the long open window terminates, which increases the window watchdog error counter by two. 2. The initialization timer expires for the first time. As the window watchdog does not detect valid triggering during ACTIVE state, it generates a soft reset: The device sets ROT to "low" , while the output voltages of the post regulators remain on. 3. After the soft reset the pin ROT turns "high" after the power-on reset delay time trd. The window watchdog opens a long open window, so the microcontroller gets the opportunity to trigger and synchronize to the watchdog period. 4. On valid triggering the window watchdog terminates the open window. The duration of the open window depends on when the triggering occurs. Due to the valid WWD triggering the window watchdog starts a closed window and it decrements the window watchdog error counter by 1. 5. The subsequent closed window lasts for the time tWD,CW. Triggering within this closed window is invalid WWD triggering. OPTIREG™ PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 72 Rev. 1.0 2020-04-08

Fault: no trigger during open window in steady state Open Window ROT WDI variable immediately 1 2 3 4 FAULT! Valid WWD triggering Invalid WWD triggering WWDSCMD Closed Window fixed Open Window Open Window variable immediately Figure 18 Fault operation: no trigger in open window in steady state 1. If the window watchdog does not detect valid triggering during the entire open window, then it recognizes invalid WWD triggering. The window watchdog indicates this event by an interrupt and it increases the window watchdog error counter by 2. 2. After the invalid WWD triggering the window watchdog starts a new open window with the duration tWD,OW so the microcontroller gets the opportunity to trigger and tosynchronize to the watchdog period. 3. On valid triggering the window watchdog terminates the open window. The duration of the open window depends on when the triggering occurs. Due to the valid WWD triggering the window watchdog starts a closed window and it decrements the window watchdog error counter by 1. If multiple invalid WWD triggering occurs during the open windows, then the window watchdog increases the window watchdog error counter by 2 each time, until it reaches the configured threshold and then generates a reset. 4. The subsequent closed window lasts for the time tWD,CW. Triggering during the closed window is invalid WWD triggering. The behavior of pin ROT depends on the configured value of the window watchdog error counter threshold ΣWWO (RWDCFG0.WWDETHR). In this example the amount of invalid triggering does not exceed that threshold. OPTIREG™ PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 73 Rev. 1.0 2020-04-08

Fault: wrong trigger during closed window after initialization Long Open Window Close ROT WDI variable immediately FAULT! Valid WWD triggering Invalid WWD triggering WWDSCMD immediately variable immediately 2 3 4 Closed Window fixed Open Window Open Window variable immediately Figure 19 Fault operation: wrong trigger in closed window after initialization 1. Triggering during the closed window is invalid WWD triggering. The window watchdog indicates this event by an interrupt and it increases the window watchdog error counter by 2. 2. Due to the invalid WWD triggering the window watchdog terminates the closed window before the time tWD,CW expires. The window watchdog starts an open window, so the microprocessor gets the opportunity to synchronize to the window watchdog period. 3. During this open window the window watchdog waits for valid triggering. On valid triggering the window watchdog terminates the open window. The duration of the open window depends on when the triggering occurs. Due to the valid triggering the window watchdog starts a closed window and it decrements the window watchdog error counter by 1. 4. The subsequent closed window lasts for the time tWD,CW. Triggering during the closed window is invalid WWD triggering. The behavior of pin ROT depends on the configured value of the window watchdog error counter threshold ΣWWO (RWDCFG0.WWDETHR). In this example the amount of invalid triggering does not exceed that threshold. OPTIREG™ PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 74 Rev. 1.0 2020-04-08

Fault: wrong trigger during closed window in steady state Open Window Close ROT WDI variable immediately FAULT! Valid WWD triggering Invalid WWD triggering WWDSCMD immediately variable immediately 2 3 4 Closed Window fixed Open Window Open Window variable immediately Figure 20 Fault operation: wrong trigger in closed window in steady state 1. Triggering during the closed window is invalid WWD triggering. The window watchdog indicates this event by an interrupt and it increases the window watchdog error counter by 2. 2. Due to the invalid WWD triggering the window watchdog terminates the closed window before the time tWD,CW expires. The window watchdog starts an open window, so the microprocessor gets the opportunity to synchronize to the window watchdog period. 3. During this open window the window watchdog waits for valid triggering. On valid triggering the window watchdog terminates the open window. The duration of the open window depends on when the triggering occurs. Due to the valid triggering the window watchdog starts a closed window and it decrements the window watchdog error counter by 1. 4. The subsequent closed window lasts for the time tWD,CW. Triggering during the closed window is invalid WWD triggering. The behavior of pin ROT depends on the configured value of the window watchdog error counter threshold ΣWWO (RWDCFG0.WWDETHR). In this example the amount of invalid triggering does not exceed that threshold. OPTIREG™ PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 75 Rev. 1.0 2020-04-08

7.5.2 Electrical characteristics window watchdog

Table 21 Electrical characteristics window watchdog Tj = -40°C to 150°C; VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Watchdog cycle time, configuration option 0 Watchdog cycle time, configuration option 1 tWDCYC 95 100 105 µs – P_7.5.1.2 Long open window time tLOW 570 600 630 ms – P_7.5.1.3 Watchdog input WDI Watchdog sampling time tWDI_filter 380 400 420 µs – P_7.5.1.4 Valid input level "high" VWDI, high 0.7 – – VIOVDD VWDI increasing P_7.5.1.5 Valid input level "low" VWDI, low – – 0.8 V VWDI decreasing P_7.5.1.6 Input hysteresis VWDI, hyst – 0.06 – VIOVDD – P_7.5.1.7 Pull-down current IWDI – 135 330 µA – P_7.5.1.8 Input capacitance CWDI – 4 15 pF 23) P_7.5.1.9

7.6 Microcontroller programming mode

The device includes a feature to support programming of microcontroller firmware during production or in the field by preventing periodic reset triggering during the initialization period. The programming mode can be enabled by pulling the MPS pin "high" . In programming mode the reset generation to the microcontroller is modified, so that fault events of microcontroller monitoring features do not generate a microcontroller reset. All other monitoring features that generate a microcontroller reset are still active, see Table 25. The interrupt generation and the state transitions are still active. However, the initialization timer is disabled, so that the device can remain in ACTIVE state. Operation of the internal state machine and the programming mode are independent, which allows the transition to any state while the microcontroller programming mode is active. However, the microcontroller monitoring is still active and will move the device into ACTIVE state. Therefore, leave the device in ACTIVE state during a programming operation. Voltage monitoring is active and generates the respective fault events. This may generate interrupts or move the device into FAUL T state depending on the nature of the event. 23 Not subject to production test, specified by design. OPTIREG™ PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 76 Rev. 1.0 2020-04-08

7.6.1 Electrical characteristics microcontroller programming mode

Table 22 Electrical characteristics microcontroller programming mode Tj = -40°C to 150°C; VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. MPS pin Valid input level "high" VMPS, high 2.4 – – V VMPS increasing P_7.8.0.1 Valid input level "low" VMPS, low – – 0.8 V VMPS decreasing P_7.8.0.2 Input hysteresis VMPS, hys – 350 – mV 24) P_7.8.0.3 Pull-down current IMPS – 140 330 µA VMPS = 5.0 V P_7.8.0.4 Input capacitance CMPS – 4 15 pF 24) P_7.8.0.5 24 Not subject to production test, specified by design. OPTIREG™ PMIC TLF30681QVS01 Power management IC Microcontroller interface and supervisory functions Datasheet 77 Rev. 1.0 2020-04-08

8 State machine

8.1 State machine introduction

The integrated state machine controls operation in different situations. Figure 21 shows the complete state- diagram. Table 23 and Table 24 describe each state and the transitions. REACTION ON DETECTED FAULTS in ACTIVE *: Switched ON by entering the ACTIVE then selectable via SPI**: ROT will be ACTIVE (pulled high) after the reset delay time has expired POR

• Internal SupplyUV, OV Buck2 OFF Boost1 OFF VM1, VM2 OFF Buck1 OFF Watchdog OFF DISABLED Buck1 ON Buck2 ON* Boost1 ON* VM1, VM2 ON* Watchdog ON* ACTIVE Buck1 OFF Buck2 OFF Boost1 OFF VM1, VM2 OFF REGISTERS ALL ROT ACTIVE** REGISTERS EVENTS ROT LOW REGISTERS NONE ROT LOWEnable event Timer expired Buck1 OFF Buck2 OFF VM1, VM2 OFF LOCKED ROT LOW Fault has occured three times and DEVCFG0.ENA_CONFIG = 0 Enable eventSPI: Goto to LOCKED and DEVCFG0.ENA_CONFIG = 0
• Buck1: · Buck2: · VM1: · IOVDD: · Watchdog error counter overflow · INIT timer expired Generate soft reset (ROT=Low) Generate hard reset Move to FAULT State (ROT = Low)
• Buck1: · Buck2: · Boost1: · VM1: · IOVDD: · Monitoring: · Bandgap faults OV, StG, TSD OV, StG, TSD OV, StG OV, StG OV, StG TSD Generate interrupt
• Boost1: · VM2: · Watchdog error counter increased · Over-temperature warnings · Bandgap warnings · R1VSx UV warning Watchdog OFF Watchdog OFF Boost1 OFF REGISTERS EVENTS UV UV UV UV UV OV, UV, StG FAULT SPI: Go to DISABLED and ENA = LOW V_R1Vsx > 6V Reset delay Fault delay (t_fault or t_fault_SD) Hard reset event Figure 21 State machine OPTIREG™ PMIC TLF30681QVS01 Power management IC State machine Datasheet 78 Rev. 1.0 2020-04-08

8.2 Operation states

The ACTIVE state is the first state that the device enters after power-on. The device powers up all voltage rails and expects to receive configuration from the microcontroller within the initialization time window according to the INIT timer. On deactivation of the microcontroller reset the INIT timer starts. If the following conditions are fulfilled, then the INIT timer stops:

• The device receives valid SPI communication from the microcontroller.
• The window watchdog is serviced once according to its configuration. If the INIT timer is not stopped and expires, then the device detects an initialization error. The first initialization error triggers a soft reset, which activates the reset signal ROT , but no state transition. The second initialization error triggers a hard reset, which activates the reset signal ROT and shuts down the supply rails, thus the device enters FAUL T state and the system restarts. The microcontroller can request a transition from ACTIVE state to either DISABLED state or LOCKED state via an SPI command. On an SPI request to change the state to DISABLED or LOCKED the device enters the FAUL T state for 20 ms before it enters the requested state. This is done to ensure a proper discharge of the output voltages of all switching regulators before the device is be enabled again. DISABLED During DISABLED state the device is powered off and it only monitors the enable signal (ENA) for a valid enable condition. Once a valid enable event is detected, the device enters ACTIVE state and expects configuration from the microcontroller. In DISABLED state the device resets the content of all registers. The device needs to be configured again during the ACTIVE state. FAUL T On detection of a severe fault the device enters FAUL T state. In FAUL T state all regulators are switched off and the microcontroller reset (ROT) is asserted. The device remains in FAUL T state for the specified fault time prior to a transition into ACTIVE state. In FAUL T state the device retains event registers to store the reason for entering the FAUL T state. The device resets all other registers. A soft reset condition on the first detection of a fault condition triggers the reset signal ROT , but no state transition. If the device detects the same soft reset fault condition again, then it increases the severity of the fault to a severe fault. In this case the device enters the FAUL T state. This applies for all soft reset faults except the window watchdog error counter overflow. LOCKED The device enters LOCKED state after three severe faults, brought on by expiration of the initialization counter or by request of the microcontroller. The power consumption in LOCKED state is reduced. The device remains in LOCKED state until it detects the next valid enable event. In LOCKED state the device only retains a limited set of the event registers to store the reason for entering the LOCKED state. The device resets all other registers. Table 23 Operational states functional overview. ACTIVE FAUL T LOCKED DISABLED Block or function Buck1 on R off R off R off R Buck2 on RW off R off R off R Boost1 on RW off R off R off R VM1 on RW off R off R off R OPTIREG™ PMIC TLF30681QVS01 Power management IC State machine Datasheet 79 Rev. 1.0 2020-04-08

Table 23 Operational states functional overview. (continued) ACTIVE FAUL T LOCKED DISABLED Block or function VM2 on RW off R off R off R Window watchdog on RW off R off R off R Microcontroller reset – ROT ACTIVE R "low" R "low" R "low" R Persistent registers All registers - Event registers - Event registers - - -

• on: The function is automatically activated when entering the state . The Function may be configured via SPI within the current state.
• SEL: The function is operating as configured via SPI (during the mode transition or within the current operation mode).
• off: The function is automatically deactivated when entering the operation mode.
• R: The state of the feature cannot be changed in the current operation mode.
• RW: The state of the feature can be changed in the current operation mode.
• "high": The signal is "high" in this operation mode.
• "low": The signal is "low" in this operation mode.
• ACTIVE: The reset signal may generate a reset event (edge) in this operation mode. OPTIREG™ PMIC TLF30681QVS01 Power management IC State machine Datasheet 80 Rev. 1.0 2020-04-08

8.3 State transitions and trigger signals

This section describes the state transitions of the integrated state machine. Table 24 shows the static state transitions with the respective source and destination states, the condition required to trigger the state transition and a transition specific action executed during the transition. Each row refers to one state transition. With multiple conditions in the same row all of the conditions must be met. Table 24 State transitions Source Destination Condition Action Unpowered ACTIVE Device supplied First POR event ACTIVE DISABLED SPI command and ENA = "low" ACTIVE LOCKED SPI command and ENA_CONFIG = 0 ACTIVE FAUL T Hard reset fault detected – DISABLED ACTIVE Enable event Generate MCU reset FAUL T ACTIVE FAUL T timer expires Generate MCU reset FAUL T LOCKED 25) Hard reset fault occurs three times LOCKED ACTIVE Enable event Generate MCU reset Table 25 and Table 26 show the mapping between the fault events and the associated actions. Table 25 Event response mapping – voltage rails Event Move to FAUL T Move to ACTIVE; Generate RESET Move to DISABLED No transition; Generate interrupt Buck1 Buck1: OV X – – – Buck1: UV – X – – Buck1: StG X – – – Buck2 Buck2: OV X – – – Buck2: UV – X – – Buck2: StG X – – – Boost1 Boost1: OV X – – –

25 The ENA pin must either be configured as edge-triggered or the ENA pin must be "low" to trigger the

transition from FAUL T to LOCKED state. OPTIREG™ PMIC TLF30681QVS01 Power management IC State machine Datasheet 81 Rev. 1.0 2020-04-08

Table 25 Event response mapping – voltage rails (continued) Event Move to FAUL T Move to ACTIVE; Generate RESET Move to DISABLED No transition; Generate interrupt Boost1: UV – – – X Boost1: StG X – – – VM1 VM1: OV X – – – VM1: UV – X – – VM1: StG X – – – VM2 VM2: OV – – – X VM2: UV – – – X VM2: StG – – – X Table 26 Event response mapping – other events Event Move to FAUL T Move to ACTIVE; Generate RESET Move to DISABLED No transition; Generate interrupt WWD: counter increase – – – X WWD: counter overflow – X – – INIT timer expired – first time – X – – INIT timer expired – second time X – – – Internal protection: band gap warning – – – X Internal protection: band gap fault X – – – IOVDD: OV X – – – IOVDD: UV – X – – IOVDD: StG X – – – Internal protection: internal supplies (UV,OV) – 26) X – – Buck1: OT warning – – – X Buck1: OT fault X – – –

26 If the TLF30681QVS01 detects an UV or OV fault condition on the internal supplies, then it turns off

completely. The TLF30681QVS01 enters the ACTIVE state when the UV or OV condition is no longer present. OPTIREG™ PMIC TLF30681QVS01 Power management IC State machine Datasheet 82 Rev. 1.0 2020-04-08

t Reset events POR HIGH LOW FSM State t Device enters Fault state after second initialisation error (hard reset event à all regulator off) Stat All RegsON OFF All regulators are switched on ROT Start INIT timer no SPI Com or no WD response is detected before second Initialisation time is expired POR FAULTACTIVE Move to LOCKED state after third Initialisation Error Second INIT error detected, Hard Reset event is generated & FSM moved to Fault state HIGH LOW Start INIT timer Initialisation time windowReset delay timeInitialisation time windowFault time FAULTACTIVE FAULTACTIVE LOCKED t t t Device enters LOCKED state after third initialisation error if ENA = LOW First INIT error detected, Soft Reset event is generated FSM moved to active state after Fault time is expired Figure 23 Hard reset counter

8.4 Electrical characteristics state machine

Table 27 Electrical characteristics state machine Tj = -40°C to 150°C; VR1VSx = 3.7 V to 35 V; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Number Min. Typ. Max. Initialization timeout (INIT timer) tINIT 550 600 650 ms – Fault time tFault – 20 – ms – Fault time TSD tFault, TSD – 1000 – ms – State transition time ttrans – – 100 µs – OPTIREG™ PMIC TLF30681QVS01 Power management IC State machine Datasheet 84 Rev. 1.0 2020-04-08

9 SPI registers

R0 Register is reset on a POR event and on a transition into DISABLED state. R1 Register is reset with reset class R0 and additionally on a transition into LOCKED state. R2 Register is reset with reset class R1 and additionally on a microcontroller reset. r Bit is readable (read-only). rw Bit is readable and writable (read-write). rw1p Bit is protected. Read data is inverted. Write via LOCK/UNLOCK mechanism only. rw1c Bit is readable and can be cleared by a write operation with 1. Bit is updated based on hardware inputs (flags). rwhc Bit is readable and writable. After a write operation with 1 an operation is triggered which upon its completion sets the bit to 0. rwhu Bit is readable and writable. Bit is updated based on hardware inputs (flags). Table 29 Register overview Register ID Description Address Reset Value Reset Class Page DEVCFG0 Device configuration 0 00H F3H R0 Page 88 CLKCFG0 Clock configuration 0 01H 00H R2 Page 89 CLKCFG1 Clock configuration 1 02H 04H R2 Page 90 PROTCFG Configuration protection 03H 00H R2 Page 102 PWDCFG0 Protected watchdog configuration 0 06H 9BH R2 Page 91 RWDCFG0 Read-only watchdog configuration 0 07H 9BH R2 Page 94 PWDCFG1 Protected watchdog configuration 1 08H 46H R2 Page 92 RWDCFG1 Read-only watchdog configuration 1 09H 46H R2 Page 95 PWDCFG2 Protected Watchdog Configuration 2 0AH 78H R2 Page 93 RWDCFG2 Read-only watchdog configuration 2 0BH 78H R2 Page 96 B2VCTRL Buck2 output voltage control 10H 02H R1 Page 100 B2VCTRLN Buck2 output voltage control inverted 11H 0DH R1 Page 101 GSF Global status flags 1AH 00H R0 Page 104 SYSSF0-QM System status flags – faults 1BH 00H R0 Page 106 SYSSF1-QM System status flags – interrupts 1CH 00H R1 Page 107 MCUSF0-QM Microcontroller status flags 0 – faults 1DH 00H R0 Page 109 MCUSF1-QM Microcontroller status flags 1 – warnings 1EH 00H R1 Page 110 SPISF SPI status flags 1FH 00H R1 Page 111 OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 85 Rev. 1.0 2020-04-08

Table 29 Register overview (continued) Register ID Description Address Reset Value Reset Class Page MONSF0 Voltage monitoring status flags 0 – short to ground 20H 00H R0 Page 112 MONSF1 Voltage monitoring status flags 1 – overvoltage 21H 00H R0 Page 113 MONSF2 Voltage monitoring status flags 2 – undervoltage 22H 00H R0 Page 114 OTSF0 Overtemperature events 0 – faults 23H 00H R0 Page 115 OTSF1 Overtemperature flags 1 – warnings 24H 00H R1 Page 116 OCSF1 Overcurrent flags – warnings 25H 00H R1 Page 117 OTSTAT0 Overtemperature status 0 – warnings 26H 00H R1 Page 118 VMONSTAT0 Voltage monitoring 27H 00H R1 Page 119 DEVSTAT Device state information 28H 00H R1 Page 121 PROTSTAT Protection status information 29H 01H R2 Page 122 WWDSTAT Window watchdog status information 2AH 00H R2 Page 123 WWDSCMD Window watchdog service command 33H 00H R2 Page 103 DEVCTRL Device state control 34H 00H R1 Page 98 DEVCTRLN Device state control inverted 35H 00H R1 Page 99 MPSSTAT0 Microcontroller programming support status information 37H 03H R1 Page 124 B2VSTAT Buck2 output voltage status 39H 02H R1 Page 125 HWDECT0 Hardware option information 3BH D3H R1 Page 127 DEVID Device identification 3CH 30H R1 Page 128 OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 86 Rev. 1.0 2020-04-08

9.1 SPI register definition

9.1.1 Device configuration registers (device startup default configuration)

OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 87 Rev. 1.0 2020-04-08

9.1.1.1 Register DEVCFG0

DEVCFG0 RMAP: 1 Address: 00H Device configuration 0 PAGE: 0 Reset Value: F3H 7 6 5 4 3 2 1 0 VM2ENAS VM1ENAS BOOST1EN AS BUCK2ENA S ENA_CONFI G RESDEL r r r r rw rw Field Bits Type Description VM2ENAS 7 r External voltage monitoring 2 enable at start up 0H , disabled 1H , enabled Reset: 1H VM1ENAS 6 r External voltage monitoring 1 enable at start up 0H , disabled 1H , enabled Reset: 1H BOOST1ENAS 5 r Boost1 enable at start up 0H , disabled 1H , enabled Reset: 1H BUCK2ENAS 4 r Buck2 enable at start up 0H , disabled 1H , enabled Reset: 1H ENA_CONFIG 3 rw ENA pin configuration 0H , edge triggered 1H , level sensitive Reset: 0H RESDEL 2:0 rw Reset release delay time 00H , 200 µs 01H , 400 µs 02H , 800 µs 03H , 1 ms 04H , 2 ms 05H , 4 ms 06H , 10 ms 07H , 20 ms Reset: 03H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 88 Rev. 1.0 2020-04-08

9.1.1.2 Register CLKCFG0

CLKCFG0 RMAP: X Address: 01H Clock configuration 0 PAGE: 2 Reset Value: 00H 7 6 5 4 3 2 1 0 nu PHBUCK2 PHBUCK1 PHSO nu SSEN SIEN SOEN r rw rw rw r rw rwhc rw Field Bits Type Description nu 7 r Not used PHBUCK2 6 rw Buck2 phase alignment 0H , 0° phase shift 1H , 180° phase shift Reset: 0H PHBUCK1 5 rw Buck1 phase alignment 0H , 0° phase shift 1H , 180° phase shift Reset: 0H PHSO 4 rw External clock synchronization phase alignment 0H , 0° phase shift 1H , 180° phase shift Reset: 0H nu 3 r Not used SSEN 2 rw Spread spectrum modulation enable 0H , disabled 1H , enabled Reset: 0H SIEN 1 rwhc External clock synchronization input enable 0H , disabled 1H , enabled Reset: 0H SOEN 0 rw External clock synchronization output enable 0H , disabled 1H , enabled Reset: 0H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 89 Rev. 1.0 2020-04-08

9.1.1.3 Register CLKCFG1

CLKCFG1 RMAP: X Address: 02H Clock configuration 1 PAGE: 2 Reset Value: 04H 7 6 5 4 3 2 1 0 nu FREQSEL r rw Field Bits Type Description nu 7:3 r Not used FREQSEL 2:0 rw Main switching frequency 0H , 1.8 MHz 1H , 1.9 MHz 2H , 2.0 MHz 3H , 2.1 MHz 4H , 2.2 MHz 5H , 2.3 MHz 6H , 2.4 MHz 7H , 2.5 MHz Reset: 4H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 90 Rev. 1.0 2020-04-08

9.1.1.4 Register PWDCFG0

PWDCFG0 RMAP: X Address: 06H Protected watchdog configuration 0 PAGE: 2 Reset Value: 9BH 7 6 5 4 3 2 1 0 WWDETHR WWDEN nu WWDTSEL WDCYC rwp rwp r rwp rwp Field Bits Type Description WWDETHR 7:4 rwp Window watchdog error threshold 0H 0 1H 1 ... FH 15 Reset: 9H WWDEN 3 rwp Window watchdog enable

0 B , disabled

1 B , enabled

WWDTSEL 1 rwp Window watchdog trigger selection

0 B , external WDI input used as WWD trigger

1 B , WWD is triggered by SPI write to WWDSCMD register

WDCYC 0 rwp Watchdog cycle time

0 B , 10 µs tick period

1 B , 100 µs tick period

OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 91 Rev. 1.0 2020-04-08

9.1.1.5 Register PWDCFG1

PWDCFG1 RMAP: X Address: 08H Protected watchdog configuration 1 PAGE: 2 Reset Value: 46H 7 6 5 4 3 2 1 0 nu CW r rwp Field Bits Type Description nu 7 r Not used CW 6:0 rwp Window watchdog closed window size 00H 0 watchdog cycles 01H 50 watchdog cycles 02H 100 watchdog cycles ... 7FH 6350 watchdog cycles Reset: 46H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 92 Rev. 1.0 2020-04-08

9.1.1.6 Register PWDCFG2

PWDCFG2 RMAP: X Address: 0AH Protected Watchdog Configuration 2 PAGE: 2 Reset Value: 78H 7 6 5 4 3 2 1 0 nu OW r rwp Field Bits Type Description nu 7 r Not used OW 6:0 rwp Window watchdog open window size 00H 50 watchdog cycles 01H 50 watchdog cycles 02H 100 watchdog cycles ... 7FH 6350 watchdog cycles Reset: 78H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 93 Rev. 1.0 2020-04-08

9.1.2 Read-only registers for protected configuration registers

9.1.2.1 Register RWDCFG0

RWDCFG0 RMAP: X Address: 07H Read-only watchdog configuration 0 PAGE: 2 Reset Value: 9BH 7 6 5 4 3 2 1 0 WWDETHR WWDEN nu WWDTSEL WDCYC r r r r r Field Bits Type Description WWDETHR 7:4 r Window watchdog error threshold ACTIVE 0H 0 1H 1 ... FH 15 Reset: 9H WWDEN 3 r Window watchdog enable STATUS WWDTSEL 1 r Window watchdog trigger selection ACTIVE WDCYC 0 r Watchdog cycle time ACTIVE OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 94 Rev. 1.0 2020-04-08

9.1.2.2 Register RWDCFG1

RWDCFG1 RMAP: X Address: 09H Read-only watchdog configuration 1 PAGE: 2 Reset Value: 46H 7 6 5 4 3 2 1 0 nu CW r r Field Bits Type Description nu 7 r Not used CW 6:0 r Window watchdog closed window size ACTIVE 00H 0 watchdog cycles 01H 50 watchdog cycles 02H 100 watchdog cycles ... 7FH 6350 watchdog cycles Reset: 46H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 95 Rev. 1.0 2020-04-08

9.1.2.3 Register RWDCFG2

RWDCFG2 RMAP: X Address: 0BH Read-only watchdog configuration 2 PAGE: 2 Reset Value: 78H 7 6 5 4 3 2 1 0 nu OW r r Field Bits Type Description nu 7 r Not used OW 6:0 r Window watchdog open window size ACTIVE 00H 50 watchdog cycles 01H 50 watchdog cycles 02H 100 watchdog cycles ... 7FH 6350 watchdog cycles Reset: 78H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 96 Rev. 1.0 2020-04-08

9.1.3 Protected device configuration registers

The registers in this section are protected by a defined access procedure. This procedure is based on the access to two individual registers writing inverted information. For detailed information please refer to SPI write initiated state transition request and regulator configuration. OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 97 Rev. 1.0 2020-04-08

9.1.3.1 Register DEVCTRL

DEVCTRL RMAP: X Address: 34H Device state control PAGE: 1 Reset Value: 00H 7 6 5 4 3 2 1 0 VM2EN VM1EN BOOST1EN BUCK2EN nu STATEREQ rw rw rw rw r rw Field Bits Type Description VM2EN 7 rw External voltage monitoring 2 enable request 0H , disable 1H , enable Reset: 0H VM1EN 6 rw External voltage monitoring 1 enable request 0H , disable 1H , enable Reset: 0H BOOST1EN 5 rw Boost1 enable request 0H , disable 1H , enable Reset: 0H BUCK2EN 4 rw Buck2 enable request 0H , disable 1H , enable Reset: 0H nu 3 r Not used STATEREQ 2:0 rw Device state request 00H Reserved 01H , ACTIVE state 02H Reserved 03H , DISABLED state 04H Reserved 05H Reserved 06H Reserved 07H , LOCKED state Reset: 00H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 98 Rev. 1.0 2020-04-08

9.1.3.2 Register DEVCTRLN

DEVCTRLN RMAP: X Address: 35H Device state control inverted PAGE: 1 Reset Value: 00H 7 6 5 4 3 2 1 0 VM2EN VM1EN BOOST1EN BUCK2EN nu STATEREQ rw rw rw rw r rw Field Bits Type Description VM2EN 7 rw External voltage monitoring 2 enable request 0H , enable 1H , disable Reset: 0H VM1EN 6 rw External voltage monitoring 1 enable request 0H , enable 1H , disable Reset: 0H BOOST1EN 5 rw Boost1 enable request 0H , enable 1H , disable Reset: 0H BUCK2EN 4 rw Buck2 enable request 0H , enable 1H , disable Reset: 0H nu 3 r Not used STATEREQ 2:0 rw Device state request 07H Reserved 06H , ACTIVE state 05H Reserved 04H , DISABLED state 03H Reserved 02H Reserved 01H Reserved 00H , LOCKED state Reset: 00H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 99 Rev. 1.0 2020-04-08

9.1.3.3 Register B2VCTRL

B2VCTRL RMAP: X Address: 10H Buck2 output voltage control PAGE: 1 Reset Value: 02H 7 6 5 4 3 2 1 0 nu B2VOUTF r rwhu Field Bits Type Description nu 7:4 r Not used B2VOUTF 3:0 rwhu Buck2 output voltage setting fine resolution 0H , 1.30 V 1H , 1.20 V 2H , 1.25 V 3H , 1.15 V 4H , 1.10 V 5H , 1.00 V 6H , 1.05 V 7H , 0.95 V 8H , 0.90 V Reset: 2H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 100 Rev. 1.0 2020-04-08

9.1.3.4 Register B2VCTRLN

B2VCTRLN RMAP: X Address: 11H Buck2 output voltage control inverted PAGE: 1 Reset Value: 0DH 7 6 5 4 3 2 1 0 nu B2VOUTF r rwhu Field Bits Type Description nu 7:4 r Not used B2VOUTF 3:0 rwhu Buck2 output voltage setting fine resolution FH 1.30 V EH 1.20 V DH 1.25 V CH 1.15 V BH 1.10 V AH 1.00 V 9H 1.05 V 8H 0.95 V 7H 0.90 V Reset: DH OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 101 Rev. 1.0 2020-04-08

9.1.4 General registers

9.1.4.1 Register PROTCFG

PROTCFG RMAP: X Address: 03H Configuration protection PAGE: 2 Reset Value: 00H 7 6 5 4 3 2 1 0 KEY rw Field Bits Type Description KEY 7:0 rw Protection key Reset: 00H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 102 Rev. 1.0 2020-04-08

9.1.4.2 Register WWDSCMD

WWDSCMD RMAP: X Address: 33H Window watchdog service command PAGE: 2 Reset Value: 00H 7 6 5 4 3 2 1 0 TRIG_STAT US nu TRIG r r rw Field Bits Type Description TRIG_STATUS 7 r Window watchdog last trigger received via SPI Reset: 00H nu 6:1 r Not used TRIG 0 rw Window watchdog trigger command Reset: 00H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 103 Rev. 1.0 2020-04-08

9.1.5 Event status registers

The event status registers of the device are organized hierarchically. The global status register is used to collect information of the status flags set in other registers to enable the user to speed up the event source determination. A bit in the global status register is automatically set, when a bit in the respective status register is set (event based, not level based). If a bit in the global status register is set, the user should read out the corresponding status register for the detailed information on the event source. The bits in the global status flag register can be cleared without effect on the other status registers. Clearing a bit in any of the other status registers does not reset the corresponding bit in the global status register.

9.1.5.1 Register GSF

GSF RMAP: X Address: 1AH Global status flags PAGE: 0 Reset Value: 00H 7 6 5 4 3 2 1 0 INTMISS nu R1VSxUV OT MON SPI MCU SYS r r rw1c rw1c rw1c rw1c rw1c rw1c Field Bits Type Description INTMISS 7 r Interrupt timeout event 0H , no event 1H , event occurred, cleared by hardware when all other flags in IF are cleared. Reset: 0H nu 6 r Not used R1VSxUV 5 rw1c Battery voltage undervoltage event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H OT 4 rw1c Overtemperature or overcurrent monitoring event flag: OTSF0,OTSF1, OCSF1 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H MON 3 rw1c Voltage monitoring event flag: MONSF0, MONSF1, MONSF2 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H SPI 2 rw1c SPI event flag: SPISF 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 104 Rev. 1.0 2020-04-08

(continued) Field Bits Type Description Reset: 0H MCU 1 rw1c MCU event flag: MCUSF0-QM,MCUSF1-QM 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H SYS 0 rw1c System event flag: SYSSF0-QM,SYSSF1-QM 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 105 Rev. 1.0 2020-04-08

9.1.5.2 Register SYSSF0

SYSSF0-QM RMAP: 1 Address: 1BH System status flags – faults PAGE: 0 Reset Value: 00H 7 6 5 4 3 2 1 0 BGFLT2 BGFLT1 IOVDDOV IOVDDUV nu FUSEERR rw1c rw1c rw1c rw1c r rw1c Field Bits Type Description BGFLT2 7 rw1c Bandgap fault event 2 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H BGFLT1 6 rw1c Bandgap fault event 1 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H IOVDDOV 5 rw1c IOVDD overvoltage event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H IOVDDUV 4 rw1c IOVDD undervoltage event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H nu 3:1 r Not used FUSEERR 0 rw1c Double bit error in fuse memory 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 106 Rev. 1.0 2020-04-08

9.1.5.3 Register SYSSF1

SYSSF1-QM RMAP: X Address: 1CH System status flags – interrupts PAGE: 1 Reset Value: 00H 7 6 5 4 3 2 1 0 BGWARN2 BGWARN1 ENA_PWRU P nu SYNC ENA CFG2 CFG rw1c rw1c rw1c r rw1c rw1c rw1c rw1c Field Bits Type Description BGWARN2 7 rw1c Bandgap warning event 2 (VBG1+4%>VBG2) 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H BGWARN1 6 rw1c Bandgap warning event 1 (VBG1-4%<VBG2) 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H ENA_PWRUP 5 rw1c Device wake-up condition 0H , device wake-up on a power-on-reset event, write 0 – no action 1H , device wake-up on ENA event, write 1 to clear the flag Reset: 0H nu 4 r Not used SYNC 3 rw1c External clock synchronization fault event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H ENA 2 rw1c Enable interrupt event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H CFG2 1 rw1c Output voltage configuration change fault event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H CFG 0 rw1c Supervision functions configuration change fault event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 107 Rev. 1.0 2020-04-08

OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 108 Rev. 1.0 2020-04-08

9.1.5.4 Register MCUSF0

MCUSF0-QM RMAP: 1 Address: 1DH Microcontroller status flags 0 – faults PAGE: 0 Reset Value: 00H 7 6 5 4 3 2 1 0 HARDRES SOFTRES nu WWDF nu INITF rw1c rw1c rw1c rw1c r rw1c Field Bits Type Description HARDRES 7 rw1c Hard reset event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H SOFTRES 6 rw1c So ft reset event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H nu 5:4 rw1c Not used WWDF 3 rw1c Window watchdog fault event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H nu 2:1 r Not used INITF 0 rw1c INIT timer error event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 109 Rev. 1.0 2020-04-08

9.1.5.5 Register MCUSF1

MCUSF1-QM RMAP: X Address: 1EH Microcontroller status flags 1 – warnings PAGE: 1 Reset Value: 00H 7 6 5 4 3 2 1 0 nu WWDMISS nu r rw1c r Field Bits Type Description nu 7:4 r Not used WWDMISS 3 rw1c Window watchdog missed trigger event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H nu 2:0 r Not used OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 110 Rev. 1.0 2020-04-08

9.1.5.6 Register SPISF

SPISF RMAP: X Address: 1FH SPI status flags PAGE: 1 Reset Value: 00H 7 6 5 4 3 2 1 0 nu B2VCTRL DEVCTRL LOCK DUR ADDR LEN PAR r rw1c rw1c rw1c rw1c rw1c rw1c rw1c Field Bits Type Description nu 7 r Not used B2VCTRL 6 rw1c SPI protocol B2VCTRL access error event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H DEVCTRL 5 rw1c SPI protocol DEVCTRL access error event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H LOCK 4 rw1c SPI protocol LOCK or UNLOCK access error event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H DUR 3 rw1c SPI duration error event Chip select signal CS "low" for more than 2 ms 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H ADDR 2 rw1c SPI invalid address error event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H LEN 1 rw1c SPI frame length error event Number of detected SPI clock cycles different than 16 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H PAR 0 rw1c SPI parity error event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 111 Rev. 1.0 2020-04-08

9.1.5.7 Register MONSF0

MONSF0 RMAP: 1 Address: 20H Voltage monitoring status flags 0 – short to ground PAGE: 0 Reset Value: 00H 7 6 5 4 3 2 1 0 VM2STG VM1STG nu BOOST1ST G nu BUCK2STG BUCK1STG rw1c rw1c r rw1c r rw1c rw1c Field Bits Type Description VM2STG 7 rw1c External voltage monitoring 2 short to ground event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H VM1STG 6 rw1c External voltage monitoring 1 short to ground event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H nu 5 r Not used BOOST1STG 4 rw1c Boost1 short to ground event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H nu 3:2 r Not used BUCK2STG 1 rw1c Buck2 short to ground event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H BUCK1STG 0 rw1c Buck1 short to ground event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 112 Rev. 1.0 2020-04-08

9.1.5.8 Register MONSF1

MONSF1 RMAP: 1 Address: 21H Voltage monitoring status flags 1 – overvoltage PAGE: 0 Reset Value: 00H 7 6 5 4 3 2 1 0 VM2OV VM1OV nu BOOST1OV nu BUCK2OV BUCK1OV rw1c rw1c r rw1c r rw1c rw1c Field Bits Type Description VM2OV 7 rw1c External voltage monitoring 2 overvoltage event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H VM1OV 6 rw1c External voltage monitoring 1 overvoltage event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H nu 5 r Not used BOOST1OV 4 rw1c Boost1 overvoltage event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H nu 3:2 r Not used BUCK2OV 1 rw1c Buck2 overvoltage event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H BUCK1OV 0 rw1c Buck1 overvoltage event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 113 Rev. 1.0 2020-04-08

9.1.5.9 Register MONSF2

MONSF2 RMAP: 1 Address: 22H Voltage monitoring status flags 2 – undervoltage PAGE: 0 Reset Value: 00H 7 6 5 4 3 2 1 0 VM2UV VM1UV nu BOOST1UV nu BUCK2UV BUCK1UV rw1c rw1c r rw1c r rw1c rw1c Field Bits Type Description VM2UV 7 rw1c External voltage monitoring 2 undervoltage event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H VM1UV 6 rw1c External voltage monitoring 1 undervoltage event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H nu 5 r Not used BOOST1UV 4 rw1c Boost1 undervoltage event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H nu 3:2 r Not used BUCK2UV 1 rw1c Buck2 undervoltage event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H BUCK1UV 0 rw1c Buck1 undervoltage event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 114 Rev. 1.0 2020-04-08

9.1.5.10 Register OTSF0

OTSF0 RMAP: 1 Address: 23H Overtemperature events 0 – faults PAGE: 0 Reset Value: 00H 7 6 5 4 3 2 1 0 MONOT nu BUCK2OT BUCK1OT rw1c r rw1c rw1c Field Bits Type Description MONOT 7 rw1c Monitoring overtemperature fault event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H nu 6:2 r Not used BUCK2OT 1 rw1c Buck2 overtemperature fault event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H BUCK1OT 0 rw1c Buck1 overtemperature fault event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 115 Rev. 1.0 2020-04-08

9.1.5.11 Register OTSF1

OTSF1 RMAP: X Address: 24H Overtemperature flags 1 – warnings PAGE: 1 Reset Value: 00H 7 6 5 4 3 2 1 0 MONOTW nu BUCK2OTW BUCK1OTW rw1c r rw1c rw1c Field Bits Type Description MONOTW 7 rw1c Monitoring overtemperature warning event 0H , no event, write 0 – no action 1H , event detected – write 1 to clear flag Reset: 0H nu 6:2 r Not used BUCK2OTW 1 rw1c Buck2 overtemperature warning event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H BUCK1OTW 0 rw1c Buck1 overtemperature warning event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 116 Rev. 1.0 2020-04-08

9.1.5.12 Register OCSF1

OCSF1 RMAP: X Address: 25H Overcurrent flags – warnings PAGE: 1 Reset Value: 00H 7 6 5 4 3 2 1 0 nu BOOST1OC W nu BUCK2OCW BUCK1OCW r rw1c r rw1c rw1c Field Bits Type Description nu 7:5 r Not used BOOST1OCW 4 rw1c Boost1 overcurrent warning event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H nu 3:2 r Not used BUCK2OCW 1 rw1c Buck2 overcurrent warning event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H BUCK1OCW 0 rw1c Buck1 overcurrent warning event 0H , no event, write 0 – no action 1H , event occurred, write 1 to clear the flag Reset: 0H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 117 Rev. 1.0 2020-04-08

9.1.6 Device status information registers

The device status information registers reflect the current status of the device irrespective of the latched status information in the interrupt flag registers. Therefore, reading these registers reflects the current status of the device, for example the currently active power rails or the temperature warnings.

9.1.6.1 Register OTSTAT0

OTSTAT0 RMAP: X Address: 26H Overtemperature status 0 – warnings PAGE: 1 Reset Value: 00H 7 6 5 4 3 2 1 0 MONOTW nu BUCK2OTW BUCK1OTW r r r r Field Bits Type Description MONOTW 7 r Monitoring overtemperature warning STATUS 0H , no overtemperature warning 1H , overtemperature warning present Reset: 0H nu 6:2 r Not used BUCK2OTW 1 r Buck2 overtemperature warning STATUS 0H , no overtemperature warning 1H , overtemperature warning present Reset: 0H BUCK1OTW 0 r Buck1 overtemperature warning STATUS 0H , no overtemperature warning 1H , overtemperature warning present Reset: 0H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 118 Rev. 1.0 2020-04-08

9.1.6.2 Register VMONSTAT0

VMONSTAT0 RMAP: X Address: 27H Voltage monitoring PAGE: 1 Reset Value: 00H 7 6 5 4 3 2 1 0 VM2OK VM1OK R1VSxUV BOOST1OK SYNCOK ENA BUCK2OK BUCK1OK r r r r r r r r Field Bits Type Description VM2OK 7 r External voltage monitoring 2 STATUS 0H , output rail disabled or not in total operation band 1H , output rail enabled and in total operation band Reset: 0H VM1OK 6 r External voltage monitoring 1 STATUS 0H , output rail disabled or not in total operation band 1H , output rail enabled and in total operation band Reset: 0H R1VSxUV 5 r Battery undervoltage STATUS 0H , battery voltage undervoltage not present. 1H , battery voltage undervoltage present. Reset: 0H BOOST1OK 4 r Boost1 STATUS 0H , output rail disabled or not in total operation band 1H , output rail enabled and in total operation band Reset: 0H SYNCOK 3 r External clock synchronization STATUS 0H , clock synchronization is not operating 1H , clock synchronization is operating. Reset: 0H ENA 2 r Enable signal level 0H , enable signal is "low" 1H , enable signal is "high" Reset: 0H BUCK2OK 1 r Buck2 STATUS 0H , output rail disabled or not in total operation band 1H , output rail enabled and in total operation band Reset: 0H BUCK1OK 0 r Buck1 STATUS 0H , output rail disabled or not in total operation band 1H , output rail enabled and in total operation band Reset: 0H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 119 Rev. 1.0 2020-04-08

OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 120 Rev. 1.0 2020-04-08

9.1.6.3 Register DEVSTAT

DEVSTAT RMAP: X Address: 28H Device state information PAGE: 1 Reset Value: 00H 7 6 5 4 3 2 1 0 VM2EN VM1EN BOOST1EN BUCK2EN nu STATE r r r r r r Field Bits Type Description VM2EN 7 r External voltage monitoring 2 enable STATUS 0H , voltage is disabled 1H , voltage is enabled Reset: 0H VM1EN 6 r External voltage monitoring 1 enable STATUS 0H , voltage is disabled 1H , voltage is enabled Reset: 0H BOOST1EN 5 r Boost 1 enable STATUS 0H , voltage is disabled 1H , voltage is enabled Reset: 0H BUCK2EN 4 r Buck 2 enable STATUS 0H , voltage is disabled 1H , voltage is enabled Reset: 0H nu 3 r Not used STATE 2:0 r Device state 0H reserved 1H , ACTIVE state 2H reserved 3H reserved 4H reserved 5H reserved 6H reserved 7H reserved Reset: 0H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 121 Rev. 1.0 2020-04-08

9.1.6.4 Register PROTSTAT

PROTSTAT RMAP: X Address: 29H Protection status information PAGE: 2 Reset Value: 01H 7 6 5 4 3 2 1 0 KEY4OK KEY3OK KEY2OK KEY1OK nu LOCK r r r r r r Field Bits Type Description KEY4OK 7 r Fourth protection key valid STATUS 0H , key not valid 1H , key valid Reset: 0H KEY3OK 6 r Third protection key valid STATUS 0H , key not valid 1H , key valid Reset: 0H KEY2OK 5 r Second protection key valid STATUS 0H , key not valid 1H , key valid Reset: 0H KEY1OK 4 r First protection key valid STATUS 0H , key not valid 1H , key valid Reset: 0H nu 3:1 r Not used LOCK 0 r Lock STATUS 0H , access to protected registers is unlocked. 1H , access to protected registers is locked. Reset: 0H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 122 Rev. 1.0 2020-04-08

9.1.6.5 Register WWDSTAT

WWDSTAT RMAP: X Address: 2AH Window watchdog status information PAGE: 2 Reset Value: 00H 7 6 5 4 3 2 1 0 nu WWDECNT r r Field Bits Type Description nu 7:4 r Not used WWDECNT 3:0 r Window watchdog error counter level 0H 0 1H 1 ... FH 15 Reset: 0H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 123 Rev. 1.0 2020-04-08

9.1.6.6 Register MPSSTAT0

MPSSTAT0 RMAP: X Address: 37H Microcontroller programming support status information PAGE: 1 Reset Value: 03H 7 6 5 4 3 2 1 0 nu MPSSTAT r r Field Bits Type Description nu 7:4 r Not used MPSSTAT 3:0 r MPS STATUS 3H , device in operating mode 6H , device in programming mode 9H , device in test mode (production test mode, read-back only) Reset: 3H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 124 Rev. 1.0 2020-04-08

9.1.6.7 Register B2VSTAT

B2VSTAT RMAP: X Address: 39H Buck2 output voltage status PAGE: 1 Reset Value: 02H 7 6 5 4 3 2 1 0 BUCK2VOUTC BUCK2VOUTF r r Field Bits Type Description BUCK2VOUTC 7:4 r Buck2 output voltage setting coarse resolution STATUS 0H , Range 0.9 – 1.3 V. Fine resolution is evaluated. 1H , 1.5 V 2H , 1.8 V 3H , 2.45 V 4H , 3.3 V Reset: 0H BUCK2VOUTF 3:0 r Buck2 output voltage setting fine resolution STATUS 0H , 1.30 V 1H , 1.20 V 2H , 1.25 V 3H , 1.15 V 4H , 1.10 V 5H , 1.00 V 6H , 1.05 V 7H , 0.95 V 8H , 0.90 V Reset: 2H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 125 Rev. 1.0 2020-04-08

9.1.7 Device information registers

OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 126 Rev. 1.0 2020-04-08

9.1.7.1 Register HWDECT0

HWDECT0 RMAP: X Address: 3BH Hardware option information PAGE: 1 Reset Value: D3H 7 6 5 4 3 2 1 0 VM2AVA VM1AVA nu BOOST1AV A nu BUCK2AVA FRE r r r r r r r Field Bits Type Description VM2AVA 7 r External voltage monitoring 2 automatic use detection 0H , VM2 is not used in this application. 1H , VM2 is used in this application. Reset: 1H VM1AVA 6 r External voltage monitoring 1 automatic use detection 0H , VM1 is not used in this application. 1H , VM1 is used in this application. Reset: 1H nu 5 r Not used BOOST1AVA 4 r Boost1 automatic use detection 0H , Boost1 is not used in this application. 1H , Boost1 is used in this application. Reset: 1H nu 3:2 r Not used BUCK2AVA 1 r Buck2 automatic use detection 0H , Buck2 is not used in this application. 1H , Buck2 is used in this application. Reset: 1H FRE 0 r Frequency selection information 0H , LF frequency setting 1H , HF frequency setting Reset: 1H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 127 Rev. 1.0 2020-04-08

9.1.7.2 Register DEVID

DEVID RMAP: X Address: 3CH Device identification PAGE: 1 Reset Value: 30H 7 6 5 4 3 2 1 0 DEVTYPE r Field Bits Type Description DEVTYPE 7:0 r Device family 30H , TLF30681 device Reset: 30H OPTIREG™ PMIC TLF30681QVS01 Power management IC SPI registers Datasheet 128 Rev. 1.0 2020-04-08

Note: The following information is given as an example for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. Logic SMPR Buck1 Feedback SPI ENABLE ENABLE Fault Manager V_S (T30) TM1 AG2 WDI SDO SDI SCL SCS ENA R1VSx Window Watchdog Reset Generator INT ROT INTERRUPT Generator Bandgap 2 for V- Mon. Bandgap 1 SMPR Buck2 VBuck2 Feedback R2SWx R2PGx R2FB VBuck1R1SWx R1PGx R1FB NC R2VS1x R1BTS UV/OV-Monitoring/ Enable Handling Internal Supply SPI_DataIn SPI_Clock SPI_ChipSelect SPI_DataOut Watchdog_TriggerIn µC_Reset Interrupt ExtRail1_Feedback ExtRail1_EnableVM1EN VM1FB ExtRail2_Feedback ExtRail2_EnableVM2EN VM2FB Clock Generation SYNCO SYNCI SYNC_In SYNC_Out MPS R3SWSMPR Boost R3PG VBoost1 Feedback R3FB AG3 IOVDD AG4 AG5 R1BTSV Interface_supply NC TM2 AG1 Buck1 Driver Supply AG6 CBuck1_1 CBuck1_2 CBuck1_3 LBuck1 CBuck1_BST CBoost1_1 CBoost1_2 LBoost1 LBuck2 CBuck2_1 CBuck2_2 Figure 24 Application diagram Note: This figure is a simplified example of an application circuit. The function must be verified in the application. Table 30 Recommended values for the passive components in Figure 24 Name Value (typical) Comments LBuck1 3.3 µH Buck1 inductor: Use an inductor with a saturation current above the Buck1 overcurrent protection threshold IR1,OCP. CBuck1_1 33 µF Buck1 output capacitor 1: Use a ceramic capacitor in X7R material with a voltage rating of 6.3 V or higher. Place this capacitor close to the R2VSx input of Buck2 and connect it between the R2VSx and R2PGx pins directly. OPTIREG™ PMIC TLF30681QVS01 Power management IC

Application information

Datasheet 129 Rev. 1.0 2020-04-08

Table 30 Recommended values for the passive components in Figure 24 (continued) Name Value (typical) Comments CBuck1_2, CBuck1_3 33 µF Buck1 output capacitors 2 and 3: Use a ceramic capacitor in X7R material with a voltage rating of 6.3 V or higher. CBuck1_BS T 100 nF Buck1 bootstrap capacitor: Use a ceramic capacitor in X7R material with a voltage rating of 16 V or higher. LBuck2 1.5 µH Buck2 inductor: Use an inductor with a saturation current above the Buck2 overcurrent protection threshold IR2,OCP. CBuck2_1, CBuck2_2, 33 µF Buck2 output capacitors 1 to 2: Use a ceramic capacitor in X7R material with a voltage rating of 6.3 V or higher. LBoost1 6.8 µH Boost1 inductor: Use an inductor with a saturation current above the Boost1 overcurrent protection threshold IR3,OCP. CBoost1_1 100 nF Boost1 output capacitor 1: Use a ceramic capacitor in X7R material with a voltage rating of 10 V or higher. CBoost1_2 10 µF Boost1 output capacitor 2: Use a ceramic capacitor in X7R material with a voltage rating of 10 V or higher. For additional supportive documentation or further information please contact http://www.infineon.com/. OPTIREG™ PMIC TLF30681QVS01 Power management IC Datasheet 130 Rev. 1.0 2020-04-08

(6.8) 7±0.1 (0.2) 0.9 MAX. 0.05 MAX. STANDOFF 0.08C SEATING COPLANARITY PLANE 48x B 0.5 0.23±0.05 0.1 A B C 0.1±0.03 0.1±0.05 5.2±0.1 5.2±0.1 (0.26) 45° 12 1 3625 1) VERTICAL BURR 0.03 MAX. AT ALL SIDES 2) THESE FOUR METAL AREAS HAVE EXPOSED DIEPAD POTENTIAL 3) EXCLUDE MOLD RESIDUES (0.65) 0.5±0.07(6.8) 7±0.1 A INDEX MARKING ALL DIMENSIONS ARE IN UNITS MM THE DRAWING IS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [ ] 48x (0.35) 0.13±0.05 0.15±0.05 INDEX MARKING 0.4 x 45° Figure 25 PG-VQFN-48 Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (Pb- free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Information on alternative packages Please visit www.infineon.com/packages. OPTIREG™ PMIC TLF30681QVS01 Power management IC

Package information

Datasheet 131 Rev. 1.0 2020-04-08

Revision history

1.0 2020-04-08 Datasheet created. OPTIREG™ PMIC TLF30681QVS01 Power management IC Datasheet 132 Rev. 1.0 2020-04-08

All referenced product or service names and trademarks are the property of their respective owners. Edition 2020-04-08 Published by Infineon Technologies AG

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© 2020 Infineon Technologies AG All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com Document reference IFX-Z8F66859087 IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”) . With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury