TLE9261BQXV33

Infineon Technologies A...

System Basis Chip Rev. 1.1 2019-09-27

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PDF pages: 163

Technical content

Features

Two integrated Low-Drop Voltage Regu lators: Main regulator (5 V or 3.3 V up to 250 mA) and auxiliary regulator (5 V up to 100 mA) with off-board usage protection
Voltage regulator (5 V, 3.3 V or 1. 8 V) with external PNP transistor configurable for off-board usage or for load sharing
1 high-speed CAN transceiver supp orting FD communication up to

5 Mbit/s featuring CAN Partial Networking & CAN FD tolerant mode

according to ISO 11898-2:2016 & SAE J2284

4 h i g h - s i d e o u t p u t s 7Ω typ., 2 HV GPIOs, 3 HV wake inputs
Integrated fail-safe and supervisio n functions, e.g. fail-safe, watchdog, interrupt- and reset outputs
16-bit SPI for configur ation and diagnostics Potential applications
Body Control Modules (BMC), Passive keyless entry and start modules, Gateway applications
Heating, ventilation and air conditioning (HVAC)
Seat, roof, tailgate, trailer, door and other closure modules
Light control modules
Gear shifters and selectors Product validation Qualified for automotive applications. Product validation according to AEC-Q100/101.

Description

B o d y S y s t e m I C w i t h I n t e g r a t e d Voltage Regulators, Power Management Functions, HS-CAN Transceiver supporting CAN FD. Featuring Multiple High-Side Switches and High-Voltage Wake Inputs. Type Package Marking TLE9261BQXV33 PG-VQFN-48-31 TLE9261BQXV33

Datasheet 2 Rev. 1.1 2019-09-27 TLE9261BQXV33 Table of Contents

Datasheet 3 Rev. 1.1 2019-09-27 TLE9261BQXV33

Datasheet 4 Rev. 1.1 2019-09-27 TLE9261BQXV33

Datasheet 5 Rev. 1.1 2019-09-27 TLE9261BQXV33 Overview

1 Overview

Scalable System Basis Chip Family

Product family with various products for complete scalable application coverage.
Dedicated Data Sheets are availabl e for the different product variants
Complete compatibility (hardware and software) across the family
TLE9263 with 2 LIN transceivers, 3 voltage regulators
TLE9262 with 1 LIN transceiver, 3 voltage regulators
TLE9261 without LIN transceivers, 3 voltage regulators
Product variants for 5V (TLE926xQX) and 3.3V (TLE926xQXV33) output voltage for main voltage regulator
CAN Partial Networking variants for 5V (TLE 926x-3QX) and 3.3V (TLE926x-3QXV33) output voltage Device Description The TLE9261BQXV33 is a monolithic integrated circuit in an exposed pad VQFN-48 (7mm x 7mm) power package with Lead Tip Inspection (LTI) feature to support Automatic Optical Inspection (AOI). The device is designed for various CAN automotive applications as main supply for the microcontroller and as interface for a CAN bus network. To support these applications, the Syst em Basis Chip (SBC) provides the ma in functions, such as a 3.3V low- dropout voltage regulator (LDO) for e.g. a microcontro ller supply, another 5V low- dropout voltage regulator with off-board protection for e.g. sensor supply, an other 3.3V/1.8V regulator to drive an external PNP transistor, which can be used as an independent supply for off-board usage or in load sharing configuration with the main regula tor VCC1, a HS-CAN transceive r supporting CAN FD for da ta transmission, high-side switches with embedded protective functions and a 16- bit Serial Peripheral Interface (SPI) to control and monitor the device. Also implemented are a configurab le timeout / window watchd og circuit with a reset feature, three Fail Outputs and an undervoltage reset feature. The device offers low-power modes in order to mini mize current consumption on applications that are connected permanently to the battery. A wake-up from the low-power mode is possible via a message on the buses, via the bi-level sensitive monitoring/wake-up inputs as well as via cyclic wake. The device is designed to withstand the severe conditions of automotive applications.

Datasheet 6 Rev. 1.1 2019-09-27 TLE9261BQXV33 Overview Product Features

Very low quiescent current consumption in Stop- and Sleep Mode
Periodic Cyclic Wake in SBC Normal- and Stop Mode
Periodic Cyclic Sense in SBC Normal-, Stop- and Sleep Mode
Low-Drop Voltage Regulator 3.3V, 250mA
Low-Drop Voltage Regulato r 5V, 100mA, protected features for off-board usage
Low-Drop Voltage Regulator, driving an external PNP transistor - 3.3V in load sharing configuration or 3.3V/1.8V in stand-alone configuration, protected features for off-board usage. Current limitation by shunt resistor (up to 350mA with 470mΩ external shunt resistor) in stand-alone configuration
High-Speed CAN Transceiver: – fully compliant to HS-C AN standard ISO 11898-2:2016 – supporting CAN FD communication up to 5 Mbps
Fully compliant to “Hardware Requirements for LIN, CAN and FlexRay Interfaces in Automotive Applications” Revision 1.3, 2012-05-04
F o u r H i g h - S i d e O u t p u t s 7Ω typ.
Dedicated supply pin for High-Side Outputs
Two General Purpose High-Voltage In- and Outputs (GPIOs ) configurable as add. Fail Outputs, Wake Inputs, Low-Side switches or High-Side switches
Three universal High-Voltage Wake In puts for voltage level monitoring
Alternate High-Voltage Me asurement Function, e.g. for battery voltage sensing
Configurable wake-up sources
Reset Output
Configurable timeout and window watchdog
Up to three Fail Outputs (d epending on configuration)
Overtemperature and short circuit protection feature
Wide supply input voltage and temperature range
Software compatible to all SB C families TLE926x and TLE927x
Green Product (RoHS comp liant) & AEC Qualified
PG-VQFN-48 leadless exposed-pad power package with Lead Tip Inspection (LTI) feature to support Automatic Optical Inspection (AOI)

Datasheet 7 Rev. 1.1 2019-09-27 TLE9261BQXV33 Block Diagram

2 Block Diagram

for FO2/3: GPIO1/2 Alternative function for WK 1/2: Voltage measurement

Datasheet 8 Rev. 1.1 2019-09-27 TLE9261BQXV33 Pin Configuration

3 Pin Configuration

3.1 Pin Assignment

Figure 2 Pin Configuration TLE9261 PG-VQFN-48 TLE9261.vsd 1GND 2 n.c.

3 VCC3REF

4 VCC3B

5 VCC3SH

6 n.c. 7 n.c. 8HS1

9 HS2

10 HS3

11 HS4

12 n.c. FO3/TEST 48 FO2 47 n.c. 46 n.c. 45 N.U. 44 GND 43 N.U. 42 n.c. 41 CANH 40 CANL 39 GND 38 VCAN 37

13 VSHS

16 n.c.

17 VCC1

18 VCC2

19 n.c.

20 GND

21 FO1

22 WK1

23 WK2

24 WK3

25 N.U. 26 N.U.

27 CLK

28 SDI

29 SDO

30 CSN

31 INT

33 N.U. 34 N.U.

35 TXDCAN

36 RXDCAN

Datasheet 9 Rev. 1.1 2019-09-27 TLE9261BQXV33 Pin Configuration

3.2 Pin Definitions and Functions

2n . c . not connected; internally not bonded. 3V C C 3 R E F VCC3REF; Collector connection for external PNP, reference input 4V C C 3 B VCC3B; Base connection for external PNP 5V C C 3 S H VCC3SH; Emitter connection for external PNP, shunt connection 6n . c . not connected; internally not bonded. 7n . c . not connected; internally not bonded. 8H S 1 High Side Output 1; typ. 7Ω 9H S 2 High Side Output 2; typ. 7Ω 10 HS3 High Side Output 3; typ. 7Ω 11 HS4 High Side Output 4; typ. 7Ω 12 n.c not connected; internally not bonded.

13 VSHS Supply Voltage HS and GPIO1/2 in HS configuration; Supply voltage for High-

Side Switches modules and respective UV-/OV supervision; Connected to battery voltage with reverse protection diode and filter against EMC; connect to VS if separate supply is not needed

14 VS Supply Voltage; Supply voltage for chip internal supply and voltage

regulators; Connected to Battery Voltage with external reverse protection Diode and Filter against EMC

15 VS Supply Voltage; Supply voltage for chip internal supply and voltage

regulators; Connected to Battery Voltage with external reverse protection Diode and Filter against EMC 16 n.c. not connected; internally not bonded.

17 VCC1 Voltage Regulator Output 1

18 VCC2 Voltage Regulator Output 2

19 n.c. not connected; internally not bonded.

20 GND GND

21 FO1 Fail Output 1

22 WK1 Wake Input 1; Alternative function: HV-measurement function input pin

(only in combination with WK2, see Chapter 11.2.2)

23 WK2 Wake Input 2; Alternative function: HV-measurement function output pin

(only in combination with WK1, see Chapter 11.2.2)

24 WK3 Wake Input 3

25 N.U. Not Used; Used for internal testing purpose. Do not connect, leave open 26 N.U. Not Used; Used for internal testing purpose. Do not connect, leave open

27 CLK SPI Clock Input

28 SDI SPI Data Input; into SBC (=MOSI)

29 SDO SPI Data Output; out of SBC (=MISO)

Datasheet 10 Rev. 1.1 2019-09-27 TLE9261BQXV33 Pin Configuration Note: all VS Pins must be connected to battery potential or insert a reverse polarity diodes where required; all GND pins as well as the Cooling Tab must be connected to one common GND potential; note that the tie bars at each package corner are connected to the cooling tab (see also Chapter 17)

30 CSN SPI Chip Select Not Input

31 INT Interrupt Output; used as wake-up flag for microcontroller in SBC Stop or

Normal Mode and for indicating failures. Active low. During start-up used to set the SBC configuration. External pull-up sets config 1/3, no external pull-up sets config 2/4.

32 RO Reset Output

33 N.U. Not Used; Used for internal testing purpose. Do not connect, leave open 34 N.U. Not Used; Used for internal testing purpose. Do not connect, leave open

35 TXDCAN Transmit CAN

36 RXDCAN Receive CAN

37 VCAN Supply Input; for internal HS-CAN cell

38 GND GND

39 CANL CAN Low Bus Pin

40 CANH CAN High Bus Pin

41 n.c. not connected; internally not bonded. 42 N.U. Not Used; Used for internal testing purpose. Do not connect, leave open

43 GND Ground

44 N.U. Not Used; Used for internal testing purpose. Do not connect, leave open 45 n.c. not connected; internally not bonded. 46 n.c. not connected; internally not bonded. 47 FO2 Fail Output 2 - Side Indicator; Side indicators 1.25Hz 50% duty cycle output; Open drain. Active LOW. Alternative Function: GPIO1; configurable pin as WK, or LS, or HS supplied by VSHS (default is FO2, see also Chapter 13.1.1)

48 FO3/TEST Fail Output 3 - Pulsed Light Output; Break/rear light 100Hz 20% duty cycle

output; Open drain. Active LOW TEST; Connect to GND to activate SBC Development Mode; Integrated pull-up resistor. Connect to VS with pull-up resistor or leave open for normal operation. Alternative Function: GPIO2; configurable pin as WK, or LS, or HS supplied by VSHS (default is FO3, see also Chapter 13.1.1) Coolin g Tab GND Cooling Tab - Exposed Die Pad; For cool ing purposes only, do not use as an electrical ground. 1) The exposed die pad at the bottom of the package allows be tter power dissipation of heat from the SBC via the PCB. The exposed die pad is not connected to any active part of the IC an can be left floating or it can be connected to GND (recommended) for the best EMC performance. Pin Symbol Function

Datasheet 11 Rev. 1.1 2019-09-27 TLE9261BQXV33 Pin Configuration

3.3 Hints for Unused Pins

It must be ensured that the correct configurations are also selected, i.e. in case functions are not used that they are disabled via SPI:

WK1/2/3: connect to GND and disable WK inputs via SPI
HSx: leave open
CANH/L, RXDCAN, TXDCA N: leave all pins open
RO / FOx: leave open
INT: leave open
TEST: connect to GND during power- up to activate SBC Development Mode; connect to VS or leave open for normal user mode operation
VCC2: leave open and keep disabled
V C C 3 : S e e Chapter 8.5
VCAN: connect to VCC1
n.c.: not connected; internal ly not bonded; connect to GND any potential on the board. In case N.U. pins are connected on the board an open bridge has to be foreseen to avoid external disturbances. The bridge can be shorted by a 0 Ω resistance if signal is needed.

3.4 Hints for Alternate Pin Functions

In case of alternate pin functions, selectable via SPI, it must be ensured that the correct configurations are also s e l e c t e d v i a S P I , i n c a s e i t i s n o t d o n e a u t o m a t i c a l l y . P l e a s e c o n s u l t t h e r e s p e c t i v e c h a p t e r . I n a d d i t i o n , following topics shall be considered:

WK1..2: The pins can be either used as HV wake / voltage monitoring inputs or for a voltage measurement function (via bit WK_MEAS). In the second case, the WK1..2 pins shall not be used / assigned for any wake detection nor cyclic sense functionality, i.e. WK1 and WK2 must be disabled in the register WK_CTRL_2 and the level information is to be ignored in the register WK_LVL_STAT.
FO2..3: The pins can also be configured as GPIOs in the GPIO_CTRL register. In this case, the pins shall not be used for any fail output functionality. The default function after Power on Reset (POR) is FOx.

Datasheet 12 Rev. 1.1 2019-09-27 TLE9261BQXV33 General Product Characteristics

4 General Product Characteristics

4.1 Absolute Maximum Ratings

Table 1 Absolute Maximum Ratings 1) Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Voltages Supply Voltage (VS, VSHS) VSx, max -0.3 – 28 V – P_4.1.1 Supply Voltage (VS, VSHS) VSx, max -0.3 – 40 V Load Dump, max. 400 ms P_4.1.2 Voltage Regulator 1 VCC1, max -0.3 – 5.5 V – P_4.1.3 Voltage Regulator 2 VCC2, max -0.3 – 28 V VCC2 = 40V for Load Dump, max. 400 ms; P_4.1.4 Voltage Regulator 3 (VCC3REF) V CC3REF,max -0.3 – 28 V VCC3REF = 40V for Load Dump, max. 400 ms; P_4.1.5 Voltage Regulator 3 (VCC3B) VCC3B,max -0.3 – VS + 10 V VCC3B = 40V for Load Dump, max. 400 ms; P_4.1.25 Voltage Regulator 3 (VCC3SH) VCC3SH,max VS - 0.30 – VS + 0.30 V – P_4.1.26 Fail Pin FO1 VFO1, max -0.3 – 40 V – P_4.1.7 Fail Pins FO2, FO3/TEST VFO2_3, max -0.3 – VS + 0.3 V – P_4.1.23 CANH, CANL VBUS, max -27 – 40 V – P_4.1.8 Maximum Differential CAN Bus Voltage VCAN_Diff, max -5 – 10 V – P_4.1.27 Logic Input Pins (CSN, CLK, SDI, TXDCAN) VI, max -0.3 – VCC1 + 0.3 V – P_4.1.9 Logic Output Pins (SDO, RO, INT, RXDCAN) VO, max -0.3 – VCC1 + 0.3 V – P_4.1.10 VCAN Input Voltage VVCAN, max -0.3 – 5.5 V – P_4.1.11 High Side 1...4 VHS, max -0.3 – VSHS + 0.3 V – P_4.1.12 Currents Wake input WK1 IWK1,max 0 – 500 µA 2) P_4.1.13 Wake input WK2 IWK2,max -500 – 0 µA 2) P_4.1.14

Datasheet 13 Rev. 1.1 2019-09-27 TLE9261BQXV33 General Product Characteristics Notes 1. Stresses above the ones listed he re may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection functions are designed to preven t IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Temperatures Junction Temperature Tj -40 – 150 °C – P_4.1.15 Storage Temperature Tstg -55 – 150 °C – P_4.1.16 ESD Susceptibility ESD Resistivity VESD,11 -2 – 2 kV HBM 3) P_4.1.17 ESD Resistivity to GND, HSx VESD,12 -2 – 2 kV HBM 3) P_4.1.18 ESD Resistivity to GND, CANH, CANL VESD,13 -8 – 8 kV HBM 4)3) P_4.1.19 ESD Resistivity to GND VESD,21 -500 – 500 V CDM 5) P_4.1.20 ESD Resistivity Pin 1, 12,13,24,25,36,37,48 (corner pins) to GND VESD,22 -750 – 750 V CDM 5) P_4.1.21 1) Not subject to production test, specified by design. 2) Applies only if WK1 and WK 2 are configured as alternative HV-measurement function 3) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS-001 (1.5 kΩ, 100 pF) 4) For ESD “GUN” Resistivity 6KV (according to IEC61000-4-2 “gun test” (150pF, 330 Ω)), will be shown in Application Information and test report will be provided from IBEE 5) ESD susceptibility, Charged Device Mode l “CDM” EIA/JESD22-C101 or ESDA STM5.3.1 Table 1 Absolute Maximum Ratings 1) (cont’d) Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 14 Rev. 1.1 2019-09-27 TLE9261BQXV33 General Product Characteristics

4.2 Functional Range

Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. Device Behavior Outside of Specified Functional Range:

28V < VS,func < 40V: Device will still be functional including the state machine; the specified electrical characteristics might not be ensured anymore. The regulators VCC1/2/3 are working properly, however, a thermal shutdown might occur due to high power dissipation. HSx switches might be turned OFF depending on VSHS_OV configurations. The specified SPI communication speed is ensured; the absolute maximum ratings are not violated, however the device is not intended for continuous operation of VS >28V. The device operation at high junction temperatures for long periods might reduce the operating life time;
VCAN < 4.75V: The undervoltage bit VCAN_UV will be set in the SPI register BUS_STAT_1 and the transmitter will be disabled as long as the UV condition is present;
5.25V < VCAN < 5.50V: CAN transceiver still functional. However, the communication might fail due to out-of- spec operation;
V POR,f < VS < 5.5V: Device will still be functional; the specified electrical characteristics might not be ensured anymore. – The voltage regulators will ente r the low-drop operation mode (applies for VCC3 only if bit VCC3_VS_ UV_OFF is set), – A VCC1_UV reset could be triggere d depending on the Vrtx settings, – HSx switch behavior will depend on the respective configuration: - HS_UV_SD_EN = ‘0’ (default): HSx will be turned OFF for VSHS < VSHS_UV and will stay OFF; - HS_UV_SD_EN = ‘1’: HSx stays on as long as possible. An unwanted overcurrent shut down may occur. OC shut down bit set and the respective HSx switch will stay OFF; – FOx outputs will remain ON if they were enabled before VS > 5.5V, – The specified SPI communication speed is ensured. Table 2 Functional Range Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Supply Voltage VS,func VPOR –2 8 V 1) VPOR see Chapter 14.10 1) Including Power-On Reset, Ov er- and Undervoltage Protection P_4.2.1 CAN Supply Voltage VCAN,func 4.75 – 5.25 V – P_4.2.3 SPI frequency fSPI – – 4 MHz see Chapter 15.7 for fSPI,max P_4.2.4 Junction Temperature Tj -40 – 150 °C – P_4.2.5

Datasheet 15 Rev. 1.1 2019-09-27 TLE9261BQXV33 General Product Characteristics

4.3 Thermal Resistance

Table 3 Thermal Resistance 1) 1) Not subject to production test, specified by design. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Junction to Soldering Point RthJSP –6–K / W E x p o s e d P a d P _ 4 . 3 . 1 Junction to Ambient RthJA –3 3 –K / W 2) 2 inner copper layers (35µm thick), with thermal via array under the exposed pad contacting the first inner copper layer and 300mm2 cooling area on the bottom layer (70µm). P_4.3.2

Datasheet 16 Rev. 1.1 2019-09-27 TLE9261BQXV33 General Product Characteristics

4.4 Current Consumption

Table 4 Current Consumption Current consumption values are specified at Tj = 25°C, VS = 13.5V, all outputs open (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. SBC Normal Mode Normal Mode current consumption I Normal –3 . 5 6 . 5 m A VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; VCC2, CAN, VCC3, HSx = OFF P_4.4.1 SBC Stop Mode Stop Mode current consumption I Stop_1,25 –4 4 6 0 µ A 1)VCC2/3, HSx = OFF; CAN, WKx not wake capable; Watchdog = OFF; no load on VCC1; I_PEAK_TH = ‘0’ P_4.4.2 Stop Mode current consumption I Stop_1,85 –5 0 7 0 µ A 1)2)Tj = 85°C; VCC2/3, HSx = OFF; CAN, WKx not wake capable; Watchdog = OFF; no load on VCC1; I_PEAK_TH = ‘0’ P_4.4.3 Stop Mode current consumption (high active peak threshold) I Stop_2,25 –6 4 9 0 µ A 1)VCC2/3, HSx = OFF; CAN, WKx not wake capable; Watchdog = OFF; no load on VCC1; I_PEAK_TH = ‘1’ P_4.4.35 Stop Mode current consumption (high active peak threshold) I Stop_2,85 – 70 100 µA 1)2)Tj = 85°C; VCC2/3, HSx = OFF; CAN, WKx not wake capable; Watchdog = OFF; no load on VCC1; I_PEAK_TH = ‘1’ P_4.4.36 SBC Sleep Mode Sleep Mode current consumption I Sleep,25 – 15 25 µA VCC2/3, HSx = OFF; CAN, WKx not wake capable P_4.4.5 Sleep Mode current consumption I Sleep,85 –2 5 3 5 µ A 2)Tj = 85°C; VCC2/3, HSx = OFF; CAN, WKx not wake capable P_4.4.6

Datasheet 17 Rev. 1.1 2019-09-27 TLE9261BQXV33 General Product Characteristics Feature Incremental Current Consumption Current consumption for CAN module, recessive state ICAN,rec –23m A S B C N o r m a l / S t o p Mode; CAN Normal Mode; VCC1 connected to VCAN; VTXDCAN = VCC1; no RL on CAN P_4.4.7 Current consumption for CAN module, dominant state I CAN,dom –34 . 5 m A 2)SBC Normal/Stop Mode; CAN Normal Mode; VCC1 connected to VCAN; VTXDCAN = GND; no RL on CAN P_4.4.8 Current consumption for CAN module, Receive Only Mode I CAN,RcvOnly –0 . 9 1 . 2 m A 2)SBC Normal/Stop Mode; CAN Receive Only Mode; VCC1 connected to VCAN; VTXDCAN = VCC1; no RL on CAN P_4.4.9 Current consumption for WK1..3 wake capability (all wake inputs) I Wake,WKx,25 –0 . 2 2µ A 3)4)5) SBC Sleep Mode; WK1..3 wake capable (all WKx enabled); CAN = OFF P_4.4.13 Current consumption for WK1..3 wake capability (all wake inputs) IWake,WKx,85 –0 . 5 3µ A 2)3)4)5)SBC Sleep Mode; Tj = 85°C; WK1..3 wake capable; (all WKx enabled); CAN = OFF P_4.4.14 Current consumption for CAN wake capability I Wake,CAN,25 –4 . 5 6µ A 3)SBC Sleep Mode; CAN wake capable; WK1..3 P_4.4.17 Current consumption for CAN wake capability I Wake,CAN,85 –5 . 5 7µ A 2)3)SBC Sleep Mode; Tj = 85°C; CAN wake capable; WK1..3 P_4.4.18 VCC2 Normal Mode current consumption I Normal,VCC2 –2 . 5 3 . 5 m A VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; VCC2 = ON (no load) P_4.4.32 Current consumption for VCC2 in SBC Sleep Mode ISleep,VCC2,25 –2 5 3 5 µ A 1)3)SBC Sleep Mode; VCC2 = ON (no load); CAN, WK1..3 = OFF P_4.4.19 Table 4 Current Consumption (cont’d) Current consumption values are specified at Tj = 25°C, VS = 13.5V, all outputs open (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 18 Rev. 1.1 2019-09-27 TLE9261BQXV33 General Product Characteristics Current consumption for VCC2 in SBC Sleep Mode ISleep,VCC2,85 –3 0 4 0 µ A 1)2)3)SBC Sleep Mode; Tj = 85°C; VCC2 = ON (no load); CAN, WK1..3 = OFF P_4.4.20 Current consumption for VCC3 in SBC Sleep Mode in stand-alone configuration I Sleep,VCC3,25 –4 0 6 0 µ A 1)3)SBC Sleep Mode; VCC3 = ON (no load, stand-along config.); CAN, WK1..3 = OFF P_4.4.21 Current consumption for VCC3 in SBC Sleep Mode in stand-alone configuration I Sleep,VCC3,85 –5 0 7 0 µ A 1)2)3)SBC Sleep Mode; Tj = 85°C; VCC3 = ON (no load, stand-along config.); CAN, WK1..3 = OFF P_4.4.22 Current consumption for HSx in SBC Stop Mode I Stop,HSx,25 – 550 675 µA 3)6)SBC Stop Mode; Cyclic Sense & HSx= ON (no load); CAN, WK1..3 = OFF P_4.4.33 Current consumption for HSx in SBC Stop Mode I Stop,HSx,85 – 575 700 µA 2)3)6)SBC Stop Mode; Tj = 85°C; Cyclic Sense & HSx = ON (no load); CAN, WK1..3 = OFF P_4.4.34 Current consumption for cyclic sense function I Stop,CS25 –2 0 2 8 µ A 3)7)8)SBC Stop Mode; WD = OFF P_4.4.23 Current consumption for cyclic sense function IStop,CS85 –2 4 3 5 µ A 2)3)7)8)SBC Stop Mode; Tj = 85°C; WD = OFF P_4.4.27 Current consumption for watchdog active in Stop Mode IStop,WD25 –2 0 2 8 µ A 2)SBC Stop Mode; Watchdog running P_4.4.30 Current consumption for watchdog active in Stop Mode IStop,WD85 –2 4 3 5 µ A 2)SBC Stop Mode; Tj = 85°C; Watchdog running P_4.4.31 Current consumption for active fail outputs (FO1..3) IStop,FOx –1 . 0 2 . 0 m A 2)all SBC Modes; Tj = 25°C; FOx = ON (no load); P_4.4.24 1) If the load current on VCC1 will exceed the configured VCC1 active peak threshold I VCC1,Ipeak1,r or IVCC1,Ipeak2,r, the current consumption will increase by typ. 2.9mA to ensure optimum dynamic load behavior. Same applies to Table 4 Current Consumption (cont’d) Current consumption values are specified at Tj = 25°C, VS = 13.5V, all outputs open (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 19 Rev. 1.1 2019-09-27 TLE9261BQXV33 General Product Characteristics Note: There is no additional current consum ption contribution due to PWM generators. 2) Not subject to production test, specified by design. 3) Current consumption adders of featur es defined for SBC Sleep Mode also apply for SBC Stop Mode and vice versa (unless otherwise specified). 4) No pull-up or pull-down configuration selected. 5) The specified WKx current consumption adder for wake capability applies regardless how many WK inputs are activated. 6) A typ. 75µA / max 125µA ( T j = 85°C) adder applies for every additionally activated HSx switch in SBC Stop Mode; In SBC Normal Mode every HSx switch consumes the typ. 75µA / max 125µA ( Tj = 85°C) without the initial adder because the biasing is already enabled. 7) HS1 used for cyclic sense, Timer 2, 20m s period, 0.1ms on-time, no load on HS1. In general the current consumption adder for cyclic sense in SBC Stop Mode can be calculated with below equation: IStop,CS = 18µA + (550µA *tON/TPer) 8) Also applies to Cyclic Wake

Datasheet 20 Rev. 1.1 2019-09-27 TLE9261BQXV33 System Features

5 System Features

This chapter describes the system features and behavior of the TLE9261BQXV33:

State machine
SBC mode control
Device configuration
State of supply and peripherals
System functions such as cyclic sense or cyclic wake
Supervision and d iagnosis functions The System Basis Chip (SBC) offers six operating modes:
SBC Init Mode: Power-up of the device and after a soft reset,
SBC Normal Mode: The main operating mode of the device,
SBC Stop Mode: The first-level power saving mode with the main voltage regulator VCC1 enabled,
SBC Sleep Mode: The second-leve l power saving mode with VCC1 disabled,
SBC Restart Mode: An intermedia te mode after a wake event from SBC Sleep or Fail-Safe Mode or after a failure (e.g. WD failure, VCC1 undervoltage reset) to bring the microcontroller into a defined state via a reset. Once the failure condition is not present anymore the device will automatically change to SBC Normal Mode after a delay time ( tRD1).
SBC Fail-Safe Mode: A safe-sta te mode after critical failures (e.g. WD failure, VCC1 undervoltage reset) to bring the system into a safe state and to ensure a proper restart of the system. VCC1 is disabled. It is a permanent state until either a wake event (via CAN or WKx) occurs or the overtemperature condition is not present anymore. A special mode, called SBC Development Mode, is available during software development or debugging of the system. All above mentioned operating modes can be accessed in this mode. However, the watchdog counter is stopped and does not need to be triggered. This mode can be accessed by setting the TEST pin to GND during SBC Init Mode. The device can be configured via hardware (external component) to determine the device behavior after a watchdog trigger failure. See Chapter 5.1.1 for further information. The System Basis Chip is controlled via a 16-bit SPI interface. A detailed description can be found in Chapter 15.The configuration as well as the diagnosis is handled via the SPI. The SPI mapping of the TLE9261BQXV33 is compatible to other devices of the TLE926x and TLE927x families.

Datasheet 21 Rev. 1.1 2019-09-27 TLE9261BQXV33 System Features

5.1 Block Description of State Machine

The different SBC Modes are selected via SPI by setting the respective SBC MODE bits in the register M_S_CTRL. The SBC MODE bits are cleared when going through SBC Restart Mode and thus always show the current SBC mode. Figure 3 State Diagram show ing the SBC Operating Modes SBC Init Mode * (Long open window) VCC1 ON VCC2 OFF VCC3 OFF FOx inact. CAN(3) OFF Wake up event SPI cmd SPI cmd SPI cmd Any SPI command WD trigger First battery connection VCC1 Undervoltage Automatic 1st Watchdog Failure Config 2, 2nd Watchdog Failure, Config 4 VCC1 Short to GND SBC Soft Reset  Reset is released  WD starts with long open window (1) After Fail-Safe Mode entry, the device will stay for at least typ. 1s in this mode (with RO low) after a TSD2 event and min. typ. 100ms after other Fail-Safe Events. Only then the device can leave the mode via a wake-up event. Wake events are stored during this time (2) According to VCC3 configuration. (3) For SBC Development Mode CAN/VCC2 are ON in SBC Init Mode and stay ON when going from there to SBC Normal Mode. (4) See chapter CAN for detailed behavior in SBC Restart Mode. (5) See Chapter 5.1.5 and 13.1 for detailed FOx behavior. (6) Must be set to CAN wake capable / CAN OFF mode before entering SBC Sleep Mode. WD Config. HSx OFF SBC Normal Mode VCC1 ON VCC2 config. VCC3 config. FOx act/inact CAN(3) config. WD config. HSx config. SBC Sleep Mode VCC1 OFF VCC2 fixed FOx fixed CAN(6) Wake capable/off WD OFF. HSx fixed SBC Stop Mode VCC1 ON VCC2 fixed VCC3 fixed FOx fixed CAN fixed WD fixed HSx fixed SBC Restart Mode (RO pin is asserted) VCC1 ON/ ramping VCC2 OFF FOx(5) active/ fixed CAN (4) woken / OFF WD OFF HSx OFF SBC Fail-Safe Mode (1) VCC1 OFF VCC2 OFF VCC3 OFF FOx(5) active CAN Wake capable WD OFF HSx OFF Config.: settings can be changed in this SBC mode; Fixed: settings stay as defined in SBC Normal Mode TSD2 event, VCC3(2) fixed/ ramping VCC3(2) Fixed / OFF * The SBC Development Mode is a super set of state machine where the WD timer is stopped and CAN behavior differs in SBC Init Mode. Otherwise, there are no differences in behavior. Cyc. Wake OFF Cyc. Sense OFF Cyc. Wake config. Cyc. Sense config. Cyc. Wake fixed Cyc. Sense fixed Cyc. Wake OFF Cyc. Sense fixed Cyc. Wake OFF Cyc. Sense OFF Cyc. Wake OFF Cyc. Sense OFF CAN, WKx wake-up event OR Release of over temperature TSD2 after t TSD2 VCC1 over voltage Config 2/4 (if VCC_OV_RST set) VCC1 over voltage Config 1/3 (if VCC_OV_RST set) Watchdog Failure: Config 1/3 & 1st WD failure in Config4 After 4 consecutive VCC1 under voltage events (if VS > VS_UV)

Datasheet 22 Rev. 1.1 2019-09-27 TLE9261BQXV33 System Features

5.1.1 Device Configuration and SBC Init Mode

The SBC starts up in SBC Init Mode after crossing the power-on reset VPOR,r threshold (see also Chapter 14.3) and the watchdog will start with a long open window (tLW). During this power-on phase following configurations are stored in the device:

The device behavior regarding a watchdog trigger failure and a VCC1 overvoltage condition is determined by the external circuitry on the INT pin (see below)
The selection of the normal dev ice operation or the SBC Development Mode (watchdog disabled for debugging purposes) will be set depending on the voltage level of the FO3/TEST pin (see also Chapter 5.1.7).

5.1.1.1 Device Configuration

The configuration selection is inte nded to select the SBC behavior regarding a watchdog trigger failure. Depending on the requirements of the application, the VCC1 output shall be switched OFF and the device shall go to SBC Fail-Safe Mode in case of a watchdog failure (1 or 2 fails). To set this configuration (Config 2/4), the INT pin does not need an external pul l-up resistor. In case VCC1 should not be switched OFF (Config 1/3), the INT pin needs to have an external pull-up resist or connected to VCC1 (s ee application diagram in Chapter 16.1). Figure 5 shows the timing diagram of th e hardware configuration selectio n. The hardware configuration is defined during SBC Init Mode. The INT pin is internally pulled LOW with a weak pull-down resistor during the reset delay time tRD1, i.e.after VCC1 crosses the reset threshold VRT1 and before the RO pin goes HIGH. The INT pin is monitored during this time (with a continuos filter time of tCFG_F) and the configuration (depending on the voltage level at INT) is stored at the rising edge of RO. Note: If the POR bit is not cleared then the internal pull-down resistor will be reactivated every time RO is pulled LOW the configuration will be updated at the rising edge of RO. Therefore it is recommended to clear the POR bit right after initialization. In case there is no stable signal at INT, then the default value ‘0’ will taken as the config select value = SBC Fail-Safe Mode.

Datasheet 23 Rev. 1.1 2019-09-27 TLE9261BQXV33 System Features Figure 4 Hardware Configurat ion Selection Timing Diagram There are four different device configurations (Table 5) available defining the watchdog failure and the VCC1 overvoltage behavior. The configurations can be selected via the external connection on the INT pin and the SPI bit CFG in the HW_CTRL register (see also Chapter 15.4):

CFGP = ‘1’: Config 1 and Config 3: – A watchdog trigger failure leads to SBC Restart Mode and depending on CFG the Fail Outputs (FOx) are activated after the 1st (Config 1) or 2nd (Config 3) watchdog trigger failure; – A VCC1 overvoltage detection will lead to SBC Restart Mode if VCC1_OV_RST is set. VCC1_ OV will be set and the Fail Outputs are activated;
CFGP = ‘0’: Config 2 and Config 4: – A watchdog trigger failure leads to SBC Fail-Safe Mode and depending on CFG the Fail Outputs (FOx) are activated after the 1st (Config 2) or 2nd (Config 4) watchdog trigger failure. The first watchdog trigger failure in Config 4 will lead to SBC Restart Mode; – A VCC1 overvoltage detection will lead to SBC Fail-Safe Mode if VCC1_OV_RST is set. VCC1_ OV will be set and the Fail Outputs are activated; The respective device configuration can be identified by reading the SPI bit CFG in the HW_CTRL register and the CFGP bit in the WK_LVL_STAT register. Table 5 shows the configurations and the device behavior in case of a watchdog trigger failure: Table 5 Watchdog Trigger Failure Configuration Config INT Pin ( CFGP)S P I B i t CFG Event FOx Activation SBC Mode Entry

1 External pull-up 1 1 x Watchdog Failure after 1st WD Failure SBC Restart Mode

2 No ext. pull-up 1 1 x Watchdog Failure aft er 1st WD Failure SBC Fail-Safe Mode

3 External pull-up 0 2 x Watchdog Failure after 2nd WD Failure SBC Restart Mode

4 No ext. pull-up 0 2 x Watchdog Failure aft er 2nd WD Failure SBC Fail-Safe Mode t VCC1 t RO t VS VPOR,r tRD1 VRT1,r tCFG _F Configuration selection monitoring period Continuous Filtering with

Datasheet 24 Rev. 1.1 2019-09-27 TLE9261BQXV33 System Features Table 6 shows the configurations and the device behavior in case of a VCC1 overvoltage detection when VCC1_OV_RST is set: The respective configuration will be stored for all conditions and can only be changed by powering down the device (VS < VPOR,f). Table 6 Device Behavior in Ca se of VCC1 Overvoltage Detection Config INT Pin ( CFGP) CFG Bit VCC1_O V_RST Event VCC1_ OV FOx Activation SBC Mode Entry 1-4 any value x 0 1 x VCC1 OV 1 no FOx activation unchanged

1 External pull-

1 1 1 x VCC1 OV 1 after 1st VCC1 OV SBC Restart Mode 2N o e x t . p u l l - u p 1 1 1 x V C C 1 O V 1 a fter 1st VCC1 OV SBC Fail-Safe Mode

3 External pull-

0 1 1 x VCC1 OV 1 after 1st VCC1 OV SBC Restart Mode 4N o e x t . p u l l - u p 0 1 1 x V C C 1 O V 1 a fter 1st VCC1 OV SBC Fail-Safe Mode

Datasheet 25 Rev. 1.1 2019-09-27 TLE9261BQXV33 System Features

5.1.1.2 SBC Init Mode

In SBC Init Mode, the device waits for the microcontrolle r to finish its startup and initialization sequence. In the SBC Init Mode any valid SPI command will bring the SBC to SBC Normal Mode. During the long open window the watchdog has to be triggered. Thereby the watchdog will be automatically configured. A missing watchdog trigger during the long open wind ow will cause a watchdog failure and the device will enter SBC Restart Mode. Wake events are ignored during SBC Init Mode and will therefore be lost. Note: Any SPI command will bring the SBC to SBC Normal Mode even if it is a illegal SPI command (see Chapter 15.2). Note: For a safe start-up, it is recommended to use the first SPI command to trigger and to configure the watchdog (see Chapter 14.2). Note: At power up no VCC1_UV will be issued nor will FOx be triggered as long as VCC1 is below the VRT,x threshold and if VS is below the VCC1 short circuit detection threshold VS,UV. The RO pin will be kept low as long as VCC1 is below the selected VRT,x threshold.

Datasheet 26 Rev. 1.1 2019-09-27 TLE9261BQXV33 System Features

5.1.2 SBC Normal Mode

The SBC Normal Mode is the standard operating mode for the SBC. All configurations have to be done in SBC Normal Mode before entering a low-power mode (see also Chapter 5.1.6 for the device configuration defining the Fail-Safe Mode behavior). A wake-up event on CAN and WKx will create an interrupt on pin INT - however, no change of the SBC mode will occur. The configuration options are listed below:

VCC1 is active
VCC2 can be switched O N or OFF (default = OFF)
VCC3 is configurable (OFF coming from SBC Init Mode; as previo usly programmed coming from SBC Restart Mode)
CAN is configurable (OFF coming from SBC Init Mode; OFF or wake capable coming from SBC Restart Mode, see also Chapter 5.1.5)
HS Outputs can be switched ON or OFF (default = OF F) or can be controlled by PWM; HS Outputs are OFF coming from SBC Restart Mode
Wake pins show the input level a nd can be selected to be wake capable (interrupt)
Cyclic sense can be configured with HS1...4 and Timer1 or Timer 2
Cyclic wake can be configured with Timer1 or Timer2
Watchdog is configurable
All FOx outputs are OFF by default. Coming from SBC Restart Mo de FOx can be active (due to a failure event, e.g. watchdog trigger failure, VCC1 short circuit, etc.) or inactive (no failure occurred) In SBC Normal Mode, there is the possibility of testing the FO outputs, i.e. to verify if setting the FO pin to low will create the intended behavior wi thin the system. The FO output can be enabled and then disabled again by the microcontroller by setting the FO_ON SPI bit. This feature is only intended for testing purposes.

Datasheet 27 Rev. 1.1 2019-09-27 TLE9261BQXV33 System Features

5.1.3 SBC Stop Mode

The SBC Stop Mode is the first level technique to re duce the overall current co nsumption by setting the voltage regulators VCC1, VCC2 and VCC3 into a low-power mode. In this mode VCC1 is still active and supplying the microcontroller, which can enter a power down mo de. The VCC2 supply, CAN mode as well as the HSx outputs can be configured to stay enabled. All kind of settings have to be done before entering SBC Stop Mode. In SBC Stop Mode any kind of SPI WRITE commands are ignored and the SPI_FAIL bit is set, except for changing to SBC Normal Mode, triggering a SBC Soft Reset, refreshing the watchdog as well as for reading and clearing the SPI status re gisters. A wake-up event on CAN and WKx w i l l c r e a t e a n i n t e r r u p t o n p i n I N T - however, no change of the SBC mode will occur. The configuration options are listed below:

VCC1 is ON
VCC2 is fixed as configured in SBC Normal Mode
VCC3 is fixed as configured in SBC Normal Mode
CAN mode is fixed as configured in SBC Normal Mode
WK pins are fixed as configured in SBC Normal Mode
HS Outputs are fixed as con figured in SBC Normal Mode
Cyclic sense is fixed as c onfigured in SBC Normal Mode
Cyclic wake is fixed as con figured in SBC Normal Mode
Watchdog is fixed as confi gured in SBC Normal Mode
SBC Soft Reset can be triggered
FOx outputs are fixed, i.e. the state from SBC Normal Mode is maintained An interrupt is triggered on the pin INT when SBC Stop Mode is entered and not all wake source signalization flags from WK_STAT_1 and WK_STAT_2 were cleared. Note: If switches are enabled during SBC Stop Mode, e.g. HSx on with or without PWM, then the SBC current consumption will increase (see Chapter 4.4). Note: It is not possible to switch directly from SBC Stop Mode to SBC Sleep Mode. Doing so will also set the SPI_FAIL flag and will bring the SBC into Restart Mode. Note: When WK1 and WK2 are configured fo r the alternate measurement function (WK_MEAS = 1) then the wake inputs cannot be selected as wake input sources.

Datasheet 28 Rev. 1.1 2019-09-27 TLE9261BQXV33 System Features

5.1.4 SBC Sleep Mode

The SBC Sleep Mode is the second level technique to reduce the overall current consumption to a minimum needed to react on wa ke-up events or for th e SBC to perform autonomous acti ons (e.g. cyclic sense). In this mode, VCC1 is OFF and not supplying the microcontroller anymore.The VCC2 supply as well as the HSx outputs can be configured to stay enabled. The settings have to be done before entering SBC Sleep Mode. A wake-up event on CAN or WKx will bring the device via SBC Rest art Mode into SBC Normal Mode again and signal the wake source. The configuration options are listed below:

VCC1 is OFF
VCC2 is fixed as configured in SBC Normal Mode
VCC3 is fixed or OFF as con figured in SBC Normal Mode
CAN mode changes automatically from ON or Receive Only Mode to wake capable mode or can be selected to be OFF
CAN must be set to CAN wake capable / CA N off mode before entering SBC Sleep Mode
WK pins are fixed as configured in SBC Normal Mode
HS Outputs are fixed as con figured in SBC Normal Mode
Cyclic sense is fixed as c onfigured in SBC Normal Mode
Cyclic wake is not available
Watchdog is OFF
FOx outputs are fixed, i.e. the state from SBC Normal Mode is maintained
As VCC1 is OFF during SBC Sleep Mode, no SPI communication is possible;
The Sleep Mode entry is si gnalled in the SPI register DEV_STAT with the bit DEV_STAT It is not possible to switch all wake sources off in SBC Sleep Mode. Doing so will set the SPI_FAIL flag and will bring the SBC into SBC Restart Mode. In order to enter SBC Sleep Mode successfully , all wake source signalization flags from WK_STAT_1 and WK_STAT_2 need to be cleared. A failure to do so will result in an immediate wake-up from SBC Sleep Mode by going via SBC Restart to Normal Mode. All settings must be done before entering SBC Sleep Mode. Note: If switches are enabled during SBC Sleep mode, e.g. HSx on with or without PWM, then the SBC current consumption will increase (see Chapter 4.4). Note: Cyclic Sense function will not work properly an ymore in case of an overcurrent, overtemperature, under- or overvoltage (in case function is selected) event because the respective HS switch will be disabled. Note: When WK1 and WK2 are configured fo r the alternate measurement function (WK_MEAS = 1) then the wake inputs cannot be selected as wake input sources.

Datasheet 29 Rev. 1.1 2019-09-27 TLE9261BQXV33 System Features

5.1.5 SBC Restart Mode

There are multiple reasons to enter the SBC Restart Mode. The purpose of the SBC Restart Mode is to reset the microcontroller:

in case of undervoltage on VCC1 in SBC Normal and in SBC Stop Mode,
in case of overvoltage on VCC1 if the bit VCC1_OV_RST is set and if CFGP = ‘1’,
due to 1st incorrect Watchdog triggering (only if Config1, Con fig3 or Config 4 is selected, otherwise SBC Fail- Safe Mode is immediately entered),
In case of a wake event from SBC Sleep or SBC Fail-Safe Mode or a release of overtemperature shutdown (TSD2) out of SBC Fail-Safe Mode this transition is used to ramp up VCC1 after a wake in a defined way. From SBC Restart Mode, the SBC goes automatically to SBC Normal Mode, i.e the mode is left automatically by the SBC without any microcontroller influence. The SBC MODE bits are cleared. As shown in Figure 41 the Reset Output (RO) is pulled low when entering Restart Mode and is released at the transition to Normal Mode after the reset delay time ( tRD1). The watchdog timer will start with a long open window starting from the moment of the rising edge of RO and the watchdog period setting in the register WD_CTRL will be changed to the respective default value ‘100’. Leaving the SBC Restart Mode will not result in changing / deactivating the Fail outputs. The behavior of the blocks is listed below:
All FOx outputs are activated i n case of a 1st watchdog trigger failure (if Config1 or Config2 is selected) or in case of VCC1 overvoltage detection (if VCC1_OV_RST is set)
VCC1 is ON or ramping up
VCC2 will be disabled if i t was activated before
VCC3 is fixed or ramping as configured in SBC Normal Mode
CAN is “woken” due to a wake event or OFF dependin g on previous SBC and transceiver mode (see also Chapter 10). It is wake capable when it was in CAN Normal-, Receive Only or wake capable mode before SBC Restart Mode
HS Outputs will be disabled if they were activated before
RO is pulled low du ring SBC Restart Mode
SPI communication is ignored by the SBC, i.e. it is not interpreted
The Restart Mode entry is signalled in the SPI register DEV_STAT with the bits DEV_STAT Table 7 Reasons for Restart - State of SP I Status Bits after Return to Normal Mode Prev. SBC Mode Event DEV_STAT WD_FAIL VCC1_UV VCC1_OV VCC1_SC Normal 1x Watchdog Failure 01 01 x x x Normal 2x Watchdog Failure 01 10 x x x Normal VCC1 undervoltage reset 01 xx 1 x x Normal VCC1 overvoltage reset 01 xx x 1 x Stop 1x Watchdog Failure 01 01 x x x Stop 2x Watchdog Failure 01 10 x x x Stop VCC1 undervoltage reset 01 xx 1 x x Stop VCC1 overvoltage reset 01 xx x 1 x Sleep Wake-up event 10 xx x x x Fail-Safe Wake-up event 01 see “Reasons for Fail Safe, Table 8”

Datasheet 30 Rev. 1.1 2019-09-27 TLE9261BQXV33 System Features Note: An overvoltage event on VCC1 will only lead to SBC Restart Mode if the bit VCC1_OV_RST is set and if CFGP = ‘1’ (Config 1/3). Note: The content of the WD_FAIL bits will depend on the device configuration, e.g. 1 or 2 watchdog failures.

5.1.6 SBC Fail-Safe Mode

The purpose of this mode is to bring the system in a safe status after a failure condition by turning off the VCC1 supply and powering off the microcontroller. After a wake event the system is then able to restart again. The Fail-Safe Mode is automatically reached for following events:

after an SBC thermal shut down (TSD2) (see also Chapter 14.9.3),
in case of overvoltage on VCC1 if the bit VCC1_OV_RST is set and if CFGP = ‘0’,
after a 1st incorrect watchdog trigger in Config2 ( CFG = 1) and after a 2nd incorrect watchdog trigger in Config4 (CFG = 0) (see also Chapter 5.1.1),
if VCC1 is shorted to GND (see also Chapter 14.7),
After 4 consecutive VCC1 under voltage events (only if VS > VS,UV, see Chapter 14.6). In this case, the default wake source s (CAN, WK1...3, see also registers WK_CTRL_2, BUS_CTRL_1) are activated, the wake events are cleared in the register WK_STAT_1, and all output drivers and all voltage regulators are switched off. When WK1 and WK2 are configured for the alternate measurement function (WK_MEAS = 1) then WK1 and WK2 will stay configured fo r the measurement function when SBC Fail-Safe Mode is entered, i.e. they will not be activated as wake sources. The SBC Fail-Safe Mode will be maintained until a wake event on the default wake sources occurs. To avoid any fast toggling behavior a filter time of typ. 100ms (tFS,min) is implemented. Wake events during this time will be stored and will automatically lead to entering SBC Restart Mode after the filter time. In case of an VCC1 overtemperature shutdown (TSD 2) the SBC Restart Mode will be reached automatically after a filter time of typ. 1s (tTSD2) without the need of a wake event. Leaving the SBC Fail-Safe Mode will not result in deactivation of the Fail Output pins. The following functions are influenced during SBC Fail-Safe Mode:
All FOx outputs are a ctivated (see also Chapter 13)
VCC1 is OFF
VCC2 is OFF
VCC3 is OFF
C A N i s w a k e c a p a b l e
HS Outputs are OFF
WK pins are wake capable through static sense (with default 16µs filter time)
Cyclic sense and Cyclic wake is disabled
SPI communication is disabled because VCC1 is OFF
The Fail-Safe Mode activation is signalled in the SPI register DEV_STAT with the bits FAILURE and DEV_STAT

Datasheet 31 Rev. 1.1 2019-09-27 TLE9261BQXV33 System Features Note: An overvoltage event on VCC1 will only lead to SBC Fail-Safe Mode if the bit VCC1_OV_RST is set and if CFGP = ‘0’ (Config 2/4). Note: The content of the WD_FAIL bits will depend on the device configuration, e.g. 1 or 2 watchdog failures. Note: See Chapter 14.6.1 for detailed description of the 4x VCC1 undervoltage behavior.

5.1.7 SBC Development Mode

The SBC Development Mode is used during the development phase of the module. It is especially useful for software development. Compared to the default SBC user mode operation, this mode is a super set of the state machine. The device will start also in SBC Init Mode an d it is possible to use all the SB C Modes and functions with following differences:

Watchdog is stopped and does not need to be triggere d. Therefore no reset is triggered due to watchdog failure
SBC Fail-Safe and SBC Restart Mode are not reached due to watc hdog failure but the other reasons to enter these modes are still valid
CAN and VCC2 default value in SBC INIT MODE and entering SBC N ormal Mode from SBC Init Mode is ON instead of OFF The SBC Development Mode is reached automatically if the FO3/TEST pin is set and kept LOW during SBC Init Mode. The voltage level monitoring is started as soon as VS > VPOR,f. The Development Mode is configured and maintained if SBC Init Mode is left by sending any SPI command while FO3/TEST is LOW. In case the FO3/TEST level will be HIGH for longer than t TEST during the monitoring period then the SBC Development Mode is not reached . The SBC will remain in this mode for all conditions and can only be left by powering down the device (VS < VPOR,f). Table 8 Reasons for Fail-Saf e - State of SPI Status Bits after Return to Normal Mode Prev. SBC Mode Failure Event DEV_ STAT TSD2 WD_ FAIL VCC1_ UV VCC1_ UV_FS VCC1_ OV VCC1_ SC Normal 1 x Watchdog Failure 01 x 01 x x x x Normal 2 x Watchdog Failure 01 x 10 x x x x Normal TSD2 01 1 xx x x x x Normal VCC1 short to GND 01 x xx 1 x x 1 Normal 4x VCC1 UV 01 x xx 1 1 x x Normal VCC1 overvoltage 01 x xx x x 1 x Stop 1 x Watchdog Failure 01 x 01 x x x x Stop 2 x Watchdog Failure 01 x 10 x x x x Stop TSD2 01 1 xx x x x x Stop VCC1 short to GND 01 x xx 1 x x 1 Stop 4x VCC1 UV 01 x xx 1 1 x x Stop VCC1 overvoltage 01 x xx x x 1 x

Datasheet 32 Rev. 1.1 2019-09-27 TLE9261BQXV33 System Features Note: The absolute maximum ratings of the pin FO3/TEST must be observed. To increase the robustness of this pin during debugging or programming a series resistor between FO3/TEST and the connector can be added (see Figure 55).

Datasheet 33 Rev. 1.1 2019-09-27 TLE9261BQXV33 System Features

5.2 Wake Features

Following wake sources are implemented in the device:

Static Sense: WK inputs a re permanently active (see Chapter 11)
Cyclic Sense: WK inputs only ac tive during on-time of cyclic sense period (see below)
Cyclic Wake: internal wake source controlled via internal time r (see below)
CAN wake: Wake-up via CAN message (see Chapter 10)

5.2.1 Cyclic Sense

The cyclic sense feature is intended to reduce the quiescent current of the device and the application. In the cyclic sense configuration, one or more high-s ide drivers are switched on periodically controlled by TIMER1_CTRL and TIMER2_CTRL. The respective high-side drivers supp ly external circuitries e.g. switches and/or resistor arrays, which are connected to one or more wake inputs (see Figure 5). Any edge change of the WKx input signal during the on-time of the cyclic se nse period causes a wake. Depending on the SBC mode, either the INT is pulled low (SBC Normal Mode and Stop Mode) or the SBC is woken enabling the VCC1 (after SBC Sleep and SBC Fail-Safe Mode). Figure 5 Cyclic Sense Working Principle Switching Circuitry 1-4 High SideHS x WK x SBC STATE MACHINE GND WK 1-3 WK_FLT_CTRL HS_CTRL TIMER_CTRL Period / On-Time Signals to uC INT

Datasheet 34 Rev. 1.1 2019-09-27 TLE9261BQXV33 System Features

5.2.1.1 Configuration and Op eration of Cyclic Sense

The correct sequence to configur e the cyclic sense is shown in Figure 6. All the configurations have to be performed before the on-time is set in the TIMERx_CTRL registers. The settings “OFF / LOW” and “OFF / HIGH” define the voltage level of the respecti ve HS driver before the start of th e cyclic sense. The intention of this selection is to avoid an unintentional wake due to a voltage level change at the start of the cyclic sense. Cyclic Sense (=TimerX) will start as soon as the respective on-time has been selected independently from the assignment of the HS and filter configuration. The selection of th e respective timer (Config C/D see Chapter 11.2.1) must therefore be done before starting the timer. The correc t configuration sequence is as follows:

Configure the initial level
Mapping of a Timer to the respective HSx outputs
Configuring the respective filter timing and WK pins
Configuring the timer period and on-time Figure 6 Cyclic Sense: Configuration and Sequence Note: All configurations of period and on-time can be selected. However, recommended on-times for cyclic sense are 0.1ms, 0.3ms and 1ms. The SPI_FAIL will be set if the on-time is longer than the period. Cyclic Sense Configuration Assign Timer to selected HS switch in HS_CTRL _X Enable WKx as wake source with configured Timer in WK_FLT_CTRL Cyclic Sense starts / ends by setting / clearing On-time Timer1, Timer2 Select Timer Period and desired On-Time in TIMERx_CTRL WK1, WK2, WK3 with above selected timer Period : 10, 20, 50, 100, 200ms, 1s, 2s On-Time: 0.1, 0.3, 1.0, 10, 20ms Assign TIMERx_ON to OFF/Low or OFF/High in TIMERx_CTRL Timer1, Timer2 Select WKx pull-up / pull-down configuration in WK_PUPD_CTRL No pull-up/-down, pull-down or pull-up selected, automatic switching Changing the settings can be done on the fly, changes become effective at the next on-time or period

Datasheet 35 Rev. 1.1 2019-09-27 TLE9261BQXV33 System Features The first sample of the WK input value (HIGH or LOW) is taken as the reference for the next cycle. A change of the WK input value between the first and second cycle recognized during the on-time of the second cycle will cause a wake from SBC Sleep Mode or an interrupt during SBC Normal or SBC Stop Mode. A filter time of 16µs is implemented to avoid a parasi tic wake-up due to transients or EMC disturbances. The filter time tFWK1 is triggered right at the end of the selected on-time and a wake signal is recognized if:

the input level will not cross th e switching threshold level of typ. 3V during the selected filter time (i.e. if the signal will keep the HIGH or LOW level) and
there was an input level change between the current and previous cycle

Datasheet 37 Rev. 1.1 2019-09-27 TLE9261BQXV33 System Features Figure 9 Cyclic Sense Example in SBC Sleep Mode, HSx starts “OFF”/HIGH, GND based WKx input The cyclic sense function will not work properly anymore in case of following conditions:

in case SBC Fail-Safe Mode is en tered: The respective HS Switch will be disabled and the respective wake pin will be changed to static sensing
In SBC Normal, Stop, or Sleep Mo de in case of an overcurrent, overtemperature, under- or overvoltage (in case function is selected) event: the respective HS switch will be disabled Note: The internal timers for cyclic sense are not disabled automatically in case the HS switch is turned off due to above mentioned failures.This must be considered to avoid loss of wake events.

5.2.1.2 Cyclic Sense in Low Power Mode

If cyclic sense is intended for SBC Stop or SBC Sleep Mode mode, it is necessary to activate the cyclic sense in SBC Normal Mode before going to the low power mode. A wake event due to cyclic sense will set the respective bit WK1_WU, WK2_WU or WK3_WU. In Stop Mode the wake event will trigger an in terrupt, in Sleep Mode the wake event will send the device vi a Restart Mode to Normal Mode. Before returning to SBC Sleep Mode, the wake status register WK_STAT_1 and WK_STAT_2 needs to be cleared. Trying to go to SBC Sleep mode with uncleared wake flags, such as WKx_WU the SBC will directly wake-up from Sleep Mode by going via Restart Mode to Normal Mode, a reset is issued. The WKx_WU bit is seen as source for the wake. This is implemented in order not to loose an wake event during the transition. Start of Cyclic Sense High n-1 Low open closed Filter time INT & WK Bit Set Learning Cycle WKn-1 = Low WKn= Low WKn = WKn-1 ðno wake event WKn = WKn+1 = Low (but ignored because change during filter time ) WKn = WKn+1 ð no wake event WKn+2= High WKn+2 ≠WKn+ 1 ðwake event nn + 1 n + 2 HS WK High Low Switch High Low VCC1 SBC Sleep Mode Spike Transition to: SBC Normal Mode

Datasheet 38 Rev. 1.1 2019-09-27 TLE9261BQXV33 System Features

5.2.2 Cyclic Wake

The cyclic wake feature is intended to reduce the quiescent current of the device and application. For the cyclic wake feature one or both timers are configured as internal wake-up source and will periodically trigger an interrupt in SBC Normal and SBC Stop Mode. The correct sequence to configure the cyclic wake is shown in Figure 10. The sequence is as follows:

First, disable the timers to ens ure that there is not unintentional interrupt when activating cyclic wake,
Enable Timer1 and/or Timer2 as a wake-up source in the register WK_CTRL_1,
Configure the respective period Timer1 and/or Timer2. Also an on-time (any value) must be selected to start the cyclic wake even if the value is ignored. Figure 10 Cyclic Wake: Configuration and Sequence A s i n c y c l i c s e n s e , t h e c y c l i c w a k e f u n c t i o n w i l l s t a r t a s s o o n a s t h e o n - t i m e i s c o n f i g u r e d . A n i n t e r r u p t i s generated for every start of the on time except for the very first time when the timer is started Cyclic Wake Configuration Cyclic Wake starts / ends by setting / clearing On-time INT is pulled low at every rising edge of On-time except first one Select Timer Period and any On-Time in TIMERX_CTRL Periods : 10, 20, 50, 100, 200 ms, 1s, 2s On-times: any (OFF/LOW & OFF/HIGH are not allowed) Disable Timer 1 and/or Timer2 as a wake source in WK_CTRL_1 To avoid unintentional interrupts Select Timer1 and/or Timer2 as a wake source in WK_CTRL_1 No interrupt will be generated , if the timer is not enabled as a wake source

Datasheet 39 Rev. 1.1 2019-09-27 TLE9261BQXV33 System Features

5.2.3 Internal Timer

The integrated Timer1 and Timer2 are typically used to wake up the microcontroller periodically (cyclic wake) or to perform cyclic sense on the wake inputs. Ther efore, the timers can be mapped to the dedicated HS switches by SPI (via HS_CTRL1...2). Following periods and on-times ca n be selected via the register TIMER1_CTRL and TIMER2_CTRL respectively:

Period: 10ms / 20ms / 50ms / 100ms / 200ms / 1s / 2s
On time: 0.1ms / 0.3ms / 1.0ms / 10ms / 20ms / OFF at HIGH or LOW

5.3 Supervision Features

The device offers various supervision features to support functional safety requirements. Please see Chapter 14 for more information.

Datasheet 40 Rev. 1.1 2019-09-27 TLE9261BQXV33 Voltage Regulator 1

6 Voltage Regulator 1

6.1 Block Description

Figure 11 Module Block Diagram Functional Features

3.3V low-drop voltage regulator
Undervoltage monitoring with adjustable reset level, VCC1 prewarning and VCC1 short circuit detection (VRT1/2/3/4, VPW,f ). Please refer to Chapter 14.6 and Chapter 14.7 for more information.
Short circuit detection and sw itch off with undervoltage fail threshold, device enters SBC Fail-Safe Mode
≥470nF ceramic capacitor at voltage output for stability, with ESR < 1Ω @ f = 10 kHz, to achieve the voltage regulator control loop stability based on the safe phase margin (bode diagram).
Output current c apability up to IVCC1,lim. GND Overtemperature Shutdown Bandgap Reference VS State Machine VCC 1 INH Vref

Datasheet 41 Rev. 1.1 2019-09-27 TLE9261BQXV33 Voltage Regulator 1

6.2 Functional Description

The Voltage Regulator 1 (=VCC1) is “ON” in SBC Normal and SBC Stop Mode and is disabled in SBC Sleep and in SBC Fail-Safe Mode. The regulator can provide an output current up to IVCC1,lim. For low-quiescent current reasons, the output voltage tolerance is decreased in SBC Stop Mode because only a low-power mode regulator with a lower accuracy (VCC1,out41) will be active for small loads. If the load current on VCC1 exceeds the selected threshold (IVCC1,Ipeak1,r or IVCC1,Ipeak2,r) then the high-power mode regulator will be also activated to support an optimum dynamic load behavior. The current consumption will then increase by typ. 2.9mA. If the load current on VCC1 falls below the selected threshold (I VCC1,Ipeak1,f or IVCC1,Ipeak2,f), then the low-quiescent current mode is resumed again by disabling the high-power mode regulator. Both regulators (low-power mode and high-power mode) are active in SBC Normal Mode. Two different active peak thresholds can be selected via SPI:

I_PEAK_TH = ‘0’(default): the lower VCC1 active peak threshold 1 is selected with lowest quiescent current consumption in SBC Stop Mode (IStop_1,25, IStop_1,85);
I_PEAK_TH = ‘1’: the higher VCC1 active peak threshold 2 is selected with an increased quiescent current consumption in SBC Stop Mode (IStop_2,25, IStop_2,85);

Datasheet 42 Rev. 1.1 2019-09-27 TLE9261BQXV33 Voltage Regulator 1

6.3 Electrical Characteristics

Table 9 Electrical Characteristics VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Output Voltage including line and Load regulation (VCC1 = 3.3V) VCC1,out5 3.23 3.3 3.37 V 1)SBC Normal Mode; 10µA < IVCC1 < 250mA 6V < VS < 28V P_6.3.14 Output Voltage including line and Load regulation VCC1,out8 3.23 3.3 3.37 V 1)SBC Normal Mode; 10µA < IVCC1 < 150mA P_6.3.22 Output Voltage including line and Load regulation (VCC1 = 3.3V) VCC1,out6 3.29 – 3.35 V 1)2)SBC Normal Mode; 20mA < IVCC1 < 80mA 8V < VS < 18V 25°C < Tj < 125°C P_6.3.15 Output Voltage including line and Load regulation (VCC1 = 3.3V) VCC1,out71 3.29 3.3 3.43 V SBC Stop Mode; 1mA < IVCC1 < IVCC1,Ipeak P_6.3.16 Output Voltage including line and Load regulation (VCC1 = 3.3V) VCC1,out72 3.29 3.3 3.47 V SBC Stop Mode; 10µA < IVCC1 < 1mA P_6.3.21 Output Drop VCC1,d1 – – 500 mV IVCC1 = 50mA VS=3V P_6.3.3 Output Drop VCC1,d2 – – 500 mV IVCC1 = 150mA VS=5V P_6.3.4 VCC1 Active Peak Threshold 1 (Transition threshold between low-power and high- power mode regulator) I VCC1,Ipeak1,r –1 . 9 3 . 5 m A 2) ICC1 rising; VS = 13.5V I_PEAK_TH = ‘0’ P_6.3.13 VCC1 Active Peak Threshold 1 (Transition threshold between high-power and low- power mode regulator) IVCC1,Ipeak1,f 0.5 1.3 – mA 2) ICC1 falling; VS = 13.5V I_PEAK_TH = ‘0’ P_6.3.17 VCC1 Active Peak Threshold 2 (Transition threshold between low-power and high- power mode regulator) I VCC1,Ipeak2,r –4 . 3 7 . 0 m A 2) ICC1 rising; VS = 13.5V I_PEAK_TH = ‘1’ P_6.3.18 VCC1 Active Peak Threshold 2 (Transition threshold between high-power and low- power mode regulator) IVCC1,Ipeak2,f 1.7 3.4 – mA 2) ICC1 falling; VS = 13.5V I_PEAK_TH = ‘1’ P_6.3.19 Overcurrent Limitation IVCC1,lim 250 – 1200 2) mA current flowing out of pin, VCC1 = 0V P_6.3.6

Datasheet 43 Rev. 1.1 2019-09-27 TLE9261BQXV33 Voltage Regulator 1 Figure 12 Typical on-resistanc e characterization results of VCC1 pass device during low drop operation for ICC1 = 100mA 1) In SBC Stop Mode, the specified outp ut voltage tolerance applies when IVCC1 has exceeded the selected active peak threshold (IVCC1,Ipeak1,r or IVCC1,Ipeak2,r) but with increased current consumption. 2) Not subject to production test, specified by design.

Datasheet 44 Rev. 1.1 2019-09-27 TLE9261BQXV33 Voltage Regulator 1 Figure 13 Characterization results of on-resis tance range of VCC1 pass device during low drop operation for ICC1 = 150mA

Datasheet 45 Rev. 1.1 2019-09-27 TLE9261BQXV33 Voltage Regulator 2

7 Voltage Regulator 2

7.1 Block Description

Figure 14 Module Block Diagram Functional Features

5 V low-drop voltage regulator
Protected against short to ba ttery voltage, e.g. for off-board sensor supply
Can also be used for CAN supply
VCC2 undervoltage monitoring. Please refer to Chapter 14.8 for more information
Can be active in SBC N ormal, SBC Stop, and SBC Sleep Mode (not SBC Fail-Safe Mode)
VCC2 switch off after entering SBC Restart Mode. Switch off is latched, LDO must be enabled via SPI after shutdown.
Overtemperature protection
≥ 470nF ceramic capacitor at ou tput voltage for stability, with ESR < 1Ω @ f = 10 kHz, to achieve the voltage regulator control loop stability based on the safe phase margin (bode diagram).
Output current c apability up to IVCC2,lim. GND Overtemperature Shutdown Bandgap Reference VS State Machine VCC 2 INH Vref

Datasheet 46 Rev. 1.1 2019-09-27 TLE9261BQXV33 Voltage Regulator 2

7.2 Functional Description

In SBC Normal Mode VCC2 can be switched on or off via SPI. For SBC Stop- or Sleep Mode, the VCC2 has to be switched on or off before entering the respective SBC mode. The regulator can provide an output current up to IVCC2,lim. For low-quiescent current reasons, the output voltage tolerance is decreased in SBC Stop Mode because only a low-power mode regulator with a lower accuracy (V CC2,out5) will be active for small loads. If the load current on VCC2 exceeds I VCC2 > I VCC2,Ipeak,r then the high-power mode regulato r will also be enabled to support an optimum dynamic load behavior. The current consumption will then increase by typ. 2.9mA. If the load current on VCC2 falls below the threshold (I VCC2 < IVCC2,Ipeak,f), then the low-quiescent current mode is resumed again by disabling the high-power mode regulator. Both regulators are active in SBC Normal Mode. Note: If the VCC2 output voltage is supplying external off-board loads, the application must consider the series resonance circuit built by cable inductance and decoupling capacitor at the load. Sufficient damping must be provided.

7.2.1 Short to Battery Protection

The output stage is protected for short to VBAT.

Datasheet 47 Rev. 1.1 2019-09-27 TLE9261BQXV33 Voltage Regulator 2

7.3 Electrical Characteristics

Table 10 Electrical Characteristics VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Output Voltage including line and Load regulation (SBC Normal Mode) VCC2,out1 4.9 5.0 5.1 V 1)SBC Normal Mode; 10µA < IVCC2 < 100mA 6.5V < VS < 28V 1) In SBC Stop Mode, the specified outp ut voltage tolerance applies when IVCC2 has exceeded the selected active peak threshold (IVCC2,Ipeak,r) but with increased current consumption. P_7.3.1 Output Voltage including line and Load regulation (SBC Normal Mode) V CC2,out2 4.9 5.0 5.1 V 1)SBC Normal Mode; 10µA < IVCC2 < 80mA 6V < VS < 28V P_7.3.16 Output Voltage including line and Load regulation (SBC Normal Mode) VCC2,out3 4.9 5.0 5.1 V 1)SBC Normal Mode; 10µA < IVCC2 < 40mA P_7.3.2 Output Voltage including line and Load regulation (SBC Normal Mode) V CC2,out4 4.97 – 5.07 V 2)SBC Normal Mode; 10µA < IVCC2 < 5mA 8V < VS < 18V 25°C < Tj < 125°C 2) Not subject to production test, specified by design. P_7.3.14 Output Voltage including line and Load regulation (SBC Stop/Sleep Mode) VCC2,out5 4.9 5.05 5.2 V Stop, Sleep Mode; 1mA < IVCC2 < IVCC2,Ipeak P_7.3.3 Output Voltage including line and Load regulation (SBC Stop/Sleep Mode) V CC2,out6 4.9 5.05 5.25 V Stop, Sleep Mode; 10µA < IVCC2 < 1mA P_7.3.18 Output Drop VCC2,d1 – – 500 mV IVCC2 = 30mA VS = 5V P_7.3.4 VCC2 Active Peak Threshold (Transition threshold between low-power and high- power mode regulator) I VCC2,Ipeak,r –1 . 9 3 . 5 m A 2)ICC2 rising; VS = 13.5V -40°C < Tj < 150°C P_7.3.15 VCC2 Active Peak Threshold (Transition threshold between high-power and low- power mode regulator) IVCC2,Ipeak,f 0.5 1.3 – mA 2)ICC2 falling; VS = 13.5V -40°C < Tj < 150°C P_7.3.17 Overcurrent limitation IVCC2,lim 100 – 750 2) mA current flowing out of pin, VCC2 = 0V P_7.3.5

Datasheet 48 Rev. 1.1 2019-09-27 TLE9261BQXV33 Voltage Regulator 2 Figure 15 Typical on-resistance of VCC2 pass device during low drop operation for ICC2 = 30mA

Datasheet 49 Rev. 1.1 2019-09-27 TLE9261BQXV33 Voltage Regulator 2 Figure 16 On-resistance range of VCC2 pass device during low drop operation for ICC2 = 50mA

Datasheet 50 Rev. 1.1 2019-09-27 TLE9261BQXV33 External Voltage Regulator 3

8 External Voltage Regulator 3

8.1 Block Description

Figure 17 Functional Block Diagram Functional Features

Low-drop voltage regulator with external PNP transistor (up to 350mA with 470mΩ shunt resistor)
Four high-voltage pins are us ed: VS, VCC3B, VCC3SH, VCC3REF
Configurable as stand-alone regulator (3.3V or 1.8V ou tput voltage selectable via SPI) or in load-sharing mode with VCC1 (3.3V output voltage)
≥ 4.7µF ceramic capacitor at output voltage for stability, with ESR < 150mΩ @ f = 10 kHz to achieve the voltage regulator control loop stability based on the safe phase margin (bode diagram).
Overcurrent limitation with external shunt in stand-alone configuration
Adjustable load current sharing ratio between VCC1 and VCC3 fo r load-sharing configuration
Undervoltage shutdown in stand-alone configuration only Table 11 1)External Voltage Regulator Configurations depending on VCC1 output voltage 1) This settings are valid only for the VCC3 stand-alone configuration. The bit VCC3_ V_CFG is ignored for VCC3 load sharing configuration VCC1 configuration VCC3 voltage for VCC3_ V_CFG = 0 VCC3 voltage for VCC3_ V_CFG = 1 VCC1 = 3.3V VCC3 = 3.3V VCC3 = 1.8V RBE VS -V CC3shunt > Vshunt_threshold VREF State Machine ICC3base VCC3REFVCC3BVCC3SHVS

Datasheet 51 Rev. 1.1 2019-09-27 TLE9261BQXV33 External Voltage Regulator 3

8.2 Functional Description

The external voltage regulator can be used as an independent voltage regulator or in load-sharing mode with VCC1. Setting VCC3_ON in the M_S_CTRL register in SBC Normal Mode sets the stand-alone configuration of VCC3 as an independent voltage regulator. The load sharing configuration is set via the SPI bit VCC3_LS in the HW_CTRL register. Figure 18 Selecting the Configuration of the VCC3 Regulator Depending on the configuration the regulator will act in the respec tive SBC Mode as described in Table 12. After the VCC3 configuration has been selected, it cannot be changed anymore. In stand-alone configuration the maximum current ICC3max is defined by the current limitation determined by the used shunt. In load sharing configuration, the shunt is used to determine the current ratio between VCC1 and VCC3. Since the junction temperat ure of the external PNP transistor cannot be sensed by the SBC, it cannot be protected against overtemperature by the SBC. Therefore the thermal behavior has to be analyzed by the application. For low-quiescent current reasons, th e output voltage tolerance is decr eased in SBC Stop Mode because a low-power mode regulator with a lower accuracy will be active for small loads. If the base current on VCC3 exceeds IVCC3base > I VCC3base,Ipeak,r then the high-power mode regulator is enabled additionally to support an optimum dynamic load behavior. If the base current on VCC3 falls below the threshold (I VCC3base < IVCC3base,Ipeak,f), then the low-quiescent current consumption is resumed again by disabling the high-power mode regulator. Only the high-power mode regulator is active in SBC Normal Mode. The status of VCC3 is reported in the SUP_STAT_2 SPI register. The regulator will switch OFF in case of VS dropping below VS_UV regardless of the VCC3 configuration and will be automatically enabled again when exceeding this threshold vo ltage unless the control bit VCC3_VS_ UV_OFF is set, i.e. in order to keep VCC3 enabled below VS_UV the bit VCC3_VS_ UV_OFF must be set. VCC3 will also stay active in SBC Stop Mode Set bit VCC3_V_CFG = 0 Set bit VCC3_ON = 0 or 1 Set bit VCC3_LS = 1 VCC3_V_CFG is automatically set to 0 VCC3_LS, VCC3_ON and VCC3_V_CFG cannot be changed anymore VCC3_LS and VCC3_V_CFG cannot be changed anymore (once VCC3_ON is set for the first time ) VCC3 load sharing? Default value of VCC3_LS = ‘0' VCC3 output voltage in stand-alone configuration Set bit VCC3_V_CFG = 1 Set bit VCC3_ON = 0 or 1 stand-alone configuration VCC3 = 3.3V stand-alone configuration VCC3 = 1.8V VCC3 load sharing VCC3 = VCC1 No Yes 3.3V 1.8V

Datasheet 52 Rev. 1.1 2019-09-27 TLE9261BQXV33 External Voltage Regulator 3 when the bit VCC3_LS_ STP_ON is set and when load sharing is config ured (for detailed protection features see Chapter 14.7 and Chapter 15.3). Note: The configuration of the VCC3 voltage regulator behavior must be done immediately after power-up of the device and cannot be changed afterwards as long as the device is supplied. Note: As soon as the bit VCC3_ON or VCC3_LS is set for the first time, the configuration for VCC3 cannot be changed anymore. This configuration is valid - also after a SBC Soft Reset - as long as the SBC is powered. Note: If the VCC3 output voltage is supplying external off-board loads, the application must consider the series resonance circuit built by cable inductance and decoupling capacitor at the load. Sufficient damping must be provided (e.g. a 100Ohm resistor between the PNP collector and VCC3REF with 10uF capacitor on collector - see also Figure 19).

8.2.1 External Voltage Regulator as Independent Voltage Regulator

Configured as an independent voltage regulator the SBC offers with VCC3 a third supply which could be used as off-board supply e.g. for sensors due to the integrated HV pins VCC3B, VCC3SH, VCC3REF. This configuration is set and locked by enabling VCC3_ON while keeping VCC3_LS = 0. VCC3 can be switched ON or OFF but the configuration cannot be changed anymore. However, the SPI_FAIL is not set while trying to change the configuration. An overcurrent limitation function is realized with the external shunt (see Chapter 8.4 for calculating the desired shunt value) and the output current shunt voltage threshold ( Vshunt_threshold). If this threshold is reached, then ICC3 is limited and only the current limitation bit VCC3_OC is set (no other reaction) and can be cleared via SPI once the overcurrent condition is not present anymore. If the overcurrent limitation feature is not needed, then connect the pins VCC3SH and VS together. In this configuration VCC3 has the undervoltage signal ization enabled and an undervoltage event is signaled with the bit VCC3_UV in the SUP_STAT_2 SPI register. Note: To avoid undesired current consum ption increase of the device it must be ensured that VCC3 is not connected to VCC1 in this configuration. Table 12 External Voltage Regulator State by SBC Mode SBC Mode Load Sharing Mode 1) Behaves as VCC1 and has to be configured in SBC Normal Mode Independent Voltage Regulator INIT Mode OFF OFF Normal Mode Configurable Configurable Stop Mode OFF/Fixed 2) Load Sharing operation in SBC Stop Mode is by default disabled for power saving reasons but VCC3_LS bit will stay set. However, it can be also configured via the SPI bit VCC3_LS_ STP_ON to stay enabled in SBC Stop Mode. Fixed Sleep Mode OFF Fixed Restart Mode ON or ramping Fixed Fail-Safe Mode OFF OFF

Datasheet 53 Rev. 1.1 2019-09-27 TLE9261BQXV33 External Voltage Regulator 3 Figure 19 Protecting the VCC3 against inductive short circuits when configured as an independent voltage regulator for off-board supply

8.2.2 External Voltage Regulator in Load Sharing Mode

The purpose of the load sharing mode is to increase th e total current capability of VCC1 without increase of the power dissipation within the SBC. The load current is shared between the VCC1 internal regulator and the external PNP transistor of VCC3. Figure 20 shows the setup for Load Sharing. Load Sharing is active in SBC Normal Mode. It can also be configured via SPI to stay active in SBC Stop Mode. An input voltage up to VSx,MAX is regulated to VCC3,nom = 3.3 V with a precision of ±2% when used in the load sharing configuration in SBC Normal Mode. This configuration is set and locked by enabling VCC3_LS for the first time while VCC3_ON has no function, i.e. keep VCC3_ON = 0. Trying to change th e VCC3 configuration after VCC3_LS has been set will result in the SPI_FAIL bit being set and keeping the VCC3 configuratio ns unchanged. Load sharing will be automatically disabled (only if VCC3_LS_ STP_ON = 0) during SBC Stop Mode due to power saving reasons but the bit will remain set to automatically switch ba ck on after returning to SBC Normal Mode. It must be ensured that the same VCC3 output voltage level is selected as for VCC1. In this configuration VCC3 has no undervoltage signalization. VCC3 shuts down if Fail-Safe Mode is reached, e.g. due to undervoltage shutdown (VS,UV monitoring). VCC3 has no overcurrent limitation in this configuration and the shunt resi stor is defining the load sharing ratio between the VCC1 and VCC3 load currents (see Equation (8.2) in Chapter 8.4). Thus, no overcurrent condition VCC3_OC will be signaled in this configuration. RBE VS -V CC3shunt > Vshunt_threshold VREF State Machine ICC3base VCC3REFVCC3BVCC3SHVS RSHUNT T1 C2C1 VS VCC3 ICC3 RLim 100Ω

Datasheet 54 Rev. 1.1 2019-09-27 TLE9261BQXV33 External Voltage Regulator 3 Figure 20 VCC3 in Load Sharing Configuration

8.3 External Components

Characterization is performed with the BCP52-16 from Infineon (ICC3 < 200 mA) and with MJD253. Other PNP transistors can be used. However, the functionality must be checked in the application. Figure 20 shows one hardware set up used. Note: The SBC is not able to ensure a thermal prot ection of the external PNP transistor. The power handling capabilities for the application must therefore be chosen according to the selected PNP device, the PCB layout and properties of the application to prevent thermal damage, e.g. via the shunt current limitation in stand alone configuration or by selecting the proper ICC1/ICC3 ratio in load-sharing configuration. Note: To ensure an optimum EMC behavior of the VCC3 regulator when the VCC3 output is leaving the PCB, it is necessary to optimize the PCB layout to have the PNP very close to the SBC. If this is not sufficient or possible, an external capacitance should be placed to the off-board connector (see also Chapter 16.1). Table 13 Bill of Materials for the VCC3 Function with and without load sharing configuration Device Vendor Reference / Value C2 Murata 10 µF/10 V GCM31CR71A106K64L RSHUNT - 1 Ω (with / without LS) T1 Infineon BCP52-16 VCC3REFVCC3BVCC3SHVS RSHUNT T1 C2C1 VS VCC13 Vcc3 Vcc1 ICC3 ICC1

Datasheet 55 Rev. 1.1 2019-09-27 TLE9261BQXV33 External Voltage Regulator 3

8.4 Calculation of R SHUNT

As a independent regulator, the maximum current ICC3max where the limit starts and the bit ICC3 > ICC3max is set is determined by the shunt resistor RSHUNT and the Output Current Shunt Voltage Threshold Vshunt_threshold. The resistor can be calculated as following: (8.1) If VCC3 is configured for load sharing, then the shunt resistor determines the load sharing ratio between VCC1 and VCC3. The ratio can be calculated as following: (8.2) Example: A shunt resistor with 470mΩ and a load current of 100mA out of VCC1 would result in ICC3 = 191mA.

8.5 Unused Pins

I n c as e th e V C C3 i s n o t u sed i n t he application, it is recommended to connect the unused pins of VCC3 as followed:

Connect VCC3SH to VS or leave open;
Leave VCC3B open;
Leave VCC3REF open
Do not enable the VCC3 via SPI as this leads to increased current consumption max3 CC thresholdshunt SHUNT I UR = )(15105110 1 3 aR ImV I I SHUNT CC CC CC −Ω= )(151051101 3 bR mVII SHUNT CC CC −Ω⋅=

Datasheet 56 Rev. 1.1 2019-09-27 TLE9261BQXV33 External Voltage Regulator 3

8.6 Electrical Characteristics

VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all outputs open; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Table 14 Electrical Characteristics Parameter Symbol Values Uni t Note or Test Condition Number Min. Typ. Max. Parameters independent from Test Set-up External Regulator Control Drive Current Capability IVCC3base 40 60 80 mA VVCC3base = 13.5 V P_8.6.1 Input Current VCC3ref IVCC3ref 03 1 0 µ A VVCC3ref = 3.3 V P_8.6.2 Input Current VCC3 Shunt Pin IVCC3shunt 03 1 0 µ A VVCC3shunt = VS P_8.6.3 Output Current Shunt Voltage Threshold Vshunt_threshold 180 245 310 mV 1) P_8.6.6 Current increase regulation reaction time trIinc –– 5 µ s 4)VCC3 = 3.3 V to 0 V; ICC3base = 20 mA Figure 21 P_8.6.7 Current decrease regulation reaction time trIdec –– 5 µ s 4)VCC3 = 0 V to 3.3V; ICC3base = 20 mA Figure 21 P_8.6.8 Leakage current of VCC3base when VCC3 disabled IVCC3base_lk –– 5 µ A VCC3base = VS; Tj = 25°C P_8.6.9 Leakage current of VCC3shunt when VCC3 disabled IVCC3shunt_lk –– 5 µ A VCC3shunt = VS; Tj = 25°C P_8.6.11 Base to emitter resistor RBE 120 150 185 k Ω VCC3 = OFF; P_8.6.12 Active Peak Threshold VCC3 (Transition threshold between low-power and high-power mode regulator) I VCC3base,Ipeak,r – 5 06 5µ A 4)Drive current IVCC3base; IVCC3base rising VS =13.5V; -40°C < Tj < 150°C P_8.6.33 Active Peak Threshold VCC3 (Transition threshold between high-power and low-power mode regulator) I VCC3base,Ipeak,f 15 30 – µA 4)Drive current IVCC3base; IVCC3base falling VS =13.5V; -40°C < Tj < 150°C P_8.6.34 Parameters dependent on the Test Set-up (with external PNP device MJD-253) External Regulator Output Voltage (VCC3 = 3.3V) VCC3.out1 3.23 3.3 3.37 V 2)SBC Normal Mode; load sharing configuration with 470 mΩ shunt resistor; 10 µA < I VCC1 + IVCC3 < 300 mA; P_8.6.26

Datasheet 57 Rev. 1.1 2019-09-27 TLE9261BQXV33 External Voltage Regulator 3 External Regulator Output Voltage (VCC3 = 3.3V) VCC3,out4 3.23 3.3V 3.37 V SBC Normal Mode; stand-alone configuration 10 mA < I VCC3 < 300 mA; P_8.6.22 External Regulator Output Voltage (VCC3 = 3.3V) VCC3,out5 3.15 3.3V 3.45 3) V SBC Stop-, Sleep Mode; Stand-alone configuration 10µA < IVCC3 < IVCC3_peak,r P_8.6.23 External Regulator Output Voltage (VCC3 = 1.8V) V CC3,out6 1.75 1.8 1.85 V 2)SBC Normal Mode; stand-alone configuration 10 mA < I CC3 < 300 mA; P_8.6.24 External Regulator Output Voltage (VCC3 = 1.8V) VCC3,out7 1.70 1.8 1.90 3) V 2)SBC Stop-, Sleep Mode; Stand-alone configuration 10µA < I CC3 < IVCC3_peak,r 5); P_8.6.25 Load Sharing Ratio ICC1 : ICC3 RatioLS_1,VCC3 1 : 1.35 1 : 1.9 1 : 2.45 SBC Normal Mode; LS ratio for a 470 mΩ shunt resistor and total load current of 300mA P_8.6.16 Load Sharing Ratio ICC1 : ICC3 Ratio LS_2,VCC3 1 : 0.67 1 : 0.95 1 : 1.23 SBC Normal Mode; LS ratio for a 1 Ω shunt resistor and total load current of 300mA P_8.6.20 Load Sharing Ratio ICC1 : ICC3 Ratio LS_3,VCC3 1 : 1.50 1 : 1.95 1 : 2.40 – 4)5) Tj = 150°C; 8.0V < VS < 18V; SBC Normal Mode; LS ratio for a 470 mΩ shunt resistor and total load current of 300mA P_8.6.27 Load Sharing Ratio ICC1 : ICC3 RatioLS_4,VCC3 1 : 0.75 1 : 0.98 1 : 1.21 – 4)5) Tj = 150°C; 8.0V < VS < 18V; SBC Normal Mode; LS ratio for a 1 Ω shunt resistor and total load current of 300mA P_8.6.28 1) Threshold at which the current limitation starts to operate. This threshold is only active when VCC3 is configured for stand-alone configuration. 2) Tolerance includes load regulation and line regulation. Table 14 Electrical Characteristics (cont’d) Parameter Symbol Values Uni t Note or Test Condition Number Min. Typ. Max.

Datasheet 58 Rev. 1.1 2019-09-27 TLE9261BQXV33 External Voltage Regulator 3 Note: There is no thermal protection available for th e external PNP transistor. Therefore, the application must be designed to avoid overheating of the PNP via the shunt current limitation in stand alone configuration and by selecting the proper ICC1/ICC3 ratio in load-sharing configuration. Note: In SBC Stop Mode, the same output voltage to lerance applies as in SBC Normal Mode when IVCC3 has exceeded the selected active peak threshold (IVCC3base,Ipeak) but with increased current consumption. 3) At Tj > 125°C, the power tran sistor leakage could be increased, which has to be added to the quiescent current of the application independently if the regulator is turned on/off. To prevent an overvoltage condition at no load due to this increased leakage, an internal clamping structure will automatically turn on at typ. 200mV above the upper limit of the programmed output voltage. 4) Not subject to production test, specified by design. 5) a) Ratio will change depending on the chosen shunt resistor which value is correlating to the maximum power dissipation of the PNP pass device. See Chapter 8.4 for the ratio calculation. The ratio will also change at low-drop operation. For supply voltages of 5.5V < VS < 6V the accuracy applies only for a total load current of 250mA. The load sharing ratio in SBC Stop Mode has +/-10% wider limits than specified. b) The output voltage precision in load sharing in SBC Stop Mode is according to VCC1 +/-4% or better for loads up to 20mA and +/-2% with loads greater than 20mA. In SBC Normal the +/-2% precision for 5V/3.3V tolerance is valid regardless of the applied load.

Datasheet 59 Rev. 1.1 2019-09-27 TLE9261BQXV33 External Voltage Regulator 3 Timing diagram for regulator reaction time “current increase regulation reaction time” and “current decrease regulation reaction time” Figure 21 Regulator Reaction Time t t VCC3 ICCbase ICC3base, 50% trlinc trldec

Datasheet 61 Rev. 1.1 2019-09-27 TLE9261BQXV33 High-Side Switch

9 High-Side Switch

9.1 Block Description

Figure 24 High-Side Module Block Diagram

Dedicated supply pin VSH S for high-side outputs
Overvoltage and undervoltage switch off - configurable via SPI
Overcurrent detection and switch off
Open load detection in ON-state
PWM capability with internal timer configurable via SPI
Switch recovery after removal of OV or UV condition configurable via SPI

9.2 Functional Description

The High-Side switches can be used for control of LEDs, as supply for the wake inputs and for other loads. The High-Side outputs can be controlled either directly via SPI by ( HS_CTRL1, HS_CTRL2), by the integrated timers or by the integrated PWM generators. The high-side outputs are supplied by a dedicated suppl y pin VSHS (different to VS). The topology supports improved cranking condition behavior. The configuration of the High-Side (Permanent On, PWM, cyclic sense, etc.) drivers must be done in SBC Normal Mode. The configuration is taken over in SBC Stop- or SBC Sleep Mode and cannot be modified. When entering SBC Restart Mode or SBC Fail-Safe Mode the HSx outputs are disabled. HS Gate Control Overcurrent Detection Open Load (On) VSHS HSx

Datasheet 62 Rev. 1.1 2019-09-27 TLE9261BQXV33 High-Side Switch

9.2.1 Over- and Undervoltage Switch Off

All HS drivers in on-state are switched off in case of overvoltage on VSHS (VSHS,OVD). If the voltage drops below the overvoltage threshold the HS drivers are activated again. The feature can be disabled by setting the SPI bit HS_OV_SD_EN. T h e H S d r i v e r s a r e s w i t c h e d o f f i n c a s e o f u n d e r v o l t a g e o n V S H S (VSHS,UVD). If the voltage rises above the undervoltage threshold the HS drivers are activated agai n. The feature can be disabl ed by setting the SPI bit HS_UV_SD_EN. So after release of undervoltage or overvoltage condit ion the HS switch goes ba ck to programmed state in which it was configured via SPI. This behavior is only valid if the bit HS_OV_UV_REC is set to ‘1’. Otherwise the switches will stay off and the respective SPI control bits are cleared. The overvoltage and undervoltage is signaled in the bits VSHS_OV and VSHS_UV, no other error bits are set.

9.2.2 Overcurrent Detection and Switch Off

If the load current exceeds the ov ercurrent shutdown threshold for a time longer then the overcurrent shutdown filter time the output is switched off. The overcurrent condition an d the switch off is signaled with the respective HSx_OC_OT bit in the register HS_OC_OT_STAT. The HSx configuration is then reset to 000 by the SBC. To activate the High-Side again the HSx configuration has to be set to ON (001) or be programmed to a timer function. It is recommended to clear the overcurrent bit before ac tivation the High-Side switch, as the bi ts are not cleared automatically by the SBC.

9.2.3 Open Load Detection

Open load detection on the High-Side outputs is done during on state of the output. If the current in the activated output falls below then Open Load Detection current, the open load is detected and signaled via the respective bit HS1_OL, HS2_OL, HS3_OL, or HS4_OL in the register HS_OL_STAT. The High-Side output stays activated. If the open load condition disappears the Open Load bit in the SPI can be cleared. The bits are not cleared automatically by the SBC.

9.2.4 HSx Operation in Different SBC Modes

During SBC Stop and SBC Sleep Mo de the HSx outputs can be used for the cyclic sense feature. The open- load detection, overcurrent shut down as well as overvoltage and undervoltage shutdown are available. The overcurrent shutdown protection feature may influence the wake-up behavior1).
the HSx output can also be enabl ed for SBC Stop and SBC Sleep Mode as well as controlled by the PWMx generator. The HSx outputs must be configured in SBC Normal Mode before entering a low-power mode.
The HSx outputs are switched off during SBC Restart or SBC Fai l-Safe Mode. They can be enabled via SPI if the failure condition is removed. 1) For the wake feature, the forced overcurrent shut down case must be considered in the user software for all SBC Modes, i.e. due to disabled HSx switches a level change might not be detected anymore at WKx pins.

Datasheet 63 Rev. 1.1 2019-09-27 TLE9261BQXV33 High-Side Switch

9.2.5 PWM and Timer Function

Two 8-bit PWM generators are dedicate d to generate a PWM signal on th e HS outputs, e.g. for brightness adjustment or compensation of supply voltage fluctuation. The PWM generators are mapped to the dedicated HS outputs, and the duty cycle can be independently configured with a 8bit resolution via SPI ( PWM1_CTRL, PWM2_CTRL). Two different frequencies (200Hz, 400Hz) ca n be selected independently for every PWM generator in the register PWM_FREQ_CTRL. PWM Assignment and Configuration:

Configure duty cycle and frequency for respective PWM generator in PWM1_CTRL/PWM2_CTRL and PWM_FREQ_CTRL
Assign PWM generator to respe ctive HS switch(es) in HSx_CTRL
The PWM generation will start right after the HSx is assigned to the PWM generator (HS_CTRL1, HS_CTRL2) Assignment options of HS1... HS4
T i m e r 1
T i m e r 2
P W M 1
P W M 2 Minimum On-time during PWM Operation The min. on-time during PWM is limited by the actual on - and off-time of the respective HS switch, e.g. the PWM setting ‘0000 0001’ could not be realized. Reliable Open-Load Detection during PWM Operation The minimum PWM setting for a reliable open-load detection is 3digits for a period of 400Hz and >2 digits for the frequency setting of 200Hz, i.e. the high-side on-time must be longer than tOL,HS. Reliable Overcurrent Detection during PWM Operation The minimum PWM setting for a reliable overcurrent detection is >1 digit for a period of 400Hz and 1 digit for the frequency setting of 200Hz, i.e. the high-side on-time must be longer than tSD,HS.

Datasheet 64 Rev. 1.1 2019-09-27 TLE9261BQXV33 High-Side Switch

9.3 Electrical Characteristics

Table 15 Electrical Characteristics VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Output HS1, HS2, HS3, HS4 Static Drain-Source ON Resistance HS1...HS4 R ON,HS25 –71 0 Ω Ids = 60mA, Tj < 25°C P_9.3.1 Static Drain-Source ON Resistance HS1...HS4 RON,HS150 – 11.5 16 Ω Ids = 60mA, Tj < 150°C P_9.3.2 Leakage Current HSx / per channel Ileak,HS ––2µ A 1)0 V < VHSx < VSHS; Tj < 85°C P_9.3.11 Output Slew Rate (rising) SRraise,HS 0.8 – 2.5 V/µs 1)20 to 80% VSHS = 6 to 18V RL = 220Ω 1) Not subject to production test, specified by design. P_9.3.3 Output Slew Rate (falling) SRfall,HS -2.5 – -0.8 V/µs 1)80 to 20% VSHS = 6 to 18V RL = 220Ω P_9.3.4 Switch-on time HSx tON,HS 3 – 30 µs CSN = HIGH to 0.8*VSHS; R L = 220Ω; VSHS = 6 to 18V P_9.3.5 Switch-off time HSx tOFF,HS 3 – 30 µs CSN = HIGH to 0.2*VSHS; RL = 220Ω; VSHS = 6 to 18V P_9.3.6 Short Circuit Shutdown Current ISD,HS 150 245 300 mA VSHS = 6 to 20V, hysteresis included P_9.3.7 Short Circuit Shutdown Filter Time tSD,HS 12 16 20 µs 2), 3) 2) Not subject to production test, tolerance defined by internal oscillator tolerance. 3) Configure proper minimum PWM settings for reliable detection of overcurrent and open load measurement (see also Chapter 9.2.5). P_9.3.8 Open Load Detection Current IOL,HS 0.4 – 3 mA hysteresis included P_9.3.9 Open Load Detection hysteresis Open Load Detection Filter Time tOL,HS 50 64 80 µs 2), 3) P_9.3.10

Datasheet 65 Rev. 1.1 2019-09-27 TLE9261BQXV33 High Speed CAN Transceiver

10 High Speed CAN Transceiver

10.1 Block Description

Figure 25 Functional Block Diagram

10.2 Functional Description

The Controller Area Network (CAN) transceiver part of the SBC provides high-speed (HS) differential mode data transmission (up to 2 Mbaud) an d reception in automotive and industrial applications. It works as an interface between the CAN protocol controller and the physical bus lines compatible to ISO 11898-2:2016 and SAE J2284. The CAN transceiver offers low power modes to reduce current consumption. This supports networks with partially powered down nodes. To support software diagnostic functions, a CAN Receive-only Mode is implemented. It is designed to provide excellent passive behavior when the transceiver is swit ched off (mixed networks, clamp15/30 applications). A wake-up from the CAN wake capable mode is possible via a message on the bus. Thus, the microcontroller can be powered down or idled and will be woken up by the CAN bus activities. The CAN transceiver is designed to withstand the severe conditions of automotive applications and to support 12 V applications. TXDCAN Output Stage Driver Temp.- Protection CANH CANL + timeout RXDCAN Receiver MUX VCC 1 SPI Mode Control To SPI diagnostic VCAN VCC1 RTXD Wake Receiver Vs VCAN VBIAS = 2.5V

Datasheet 67 Rev. 1.1 2019-09-27 TLE9261BQXV33 High Speed CAN Transceiver FD tolerant mode is realized in the physical layer in combination with CAN Partial Networking. The TLE926x- 3QX variants of this family also support the CAN FD tolerant mode.

10.2.1 CAN OFF Mode

The CAN OFF Mode is the default mode after power-up of the SBC. It is available in all SBC Modes and is intended to completely stop CAN activities or wh en CAN communication is no t needed. The CANH/L bus interface acts as a high impedance input with a very small leakage current. In CAN OFF Mode, a wake-up event on the bus will be ignored.

10.2.2 CAN Normal Mode

The CAN Transceiver is enabled via SP I in SBC Normal Mode. CAN Normal Mode is designed for normal data transmission/reception within the HS -CAN network. The Mode is available in SBC Normal Mode and in SBC Stop Mode. The bus biasing is set to VCAN/2. Transmission The signal from the microcontroller is applied to the TXDCAN input of the SBC. The bus driver switches the CANH/L output stages to transfer this input signal to the CAN bus lines. Enabling sequence The CAN transceiver requires an enabling time t CAN,EN before a message can be sent on the bus. This means that the TXDCAN signal can only be pulled LOW after the enabling time. If this is not ensured, then the TXDCAN needs to be set back to HIGH (=recessive) until the enabling time is completed. Only the next dominant bit will be transmitted on the bus. Figure 28 shows different scenarios and explanations for CAN enabling. Figure 28 CAN Transceiver Enabling Sequence Reduced Electromagnetic Emission To reduce electromagnetic emissions (EME), the bus driver controls CANH/L slopes symmetrically. Reception Analog CAN bus signals are converted into digital signals at RXD via the differential input receiver. t VCANDIFF tCAN ,EN t VTXDCAN t CAN Mode CAN NORMAL CAN OFF CAN,ENt recessive TXD level required before start of transmission tCA N, E Nnot ensured , no transmission on bus CAN,ENt Correct sequence , Bus is enabled after tCA N, E N tCA N, E Nnot ensured , no transmission on bus recessive TXD level required Dominant Recessive

Datasheet 68 Rev. 1.1 2019-09-27 TLE9261BQXV33 High Speed CAN Transceiver

10.2.3 CAN Receive Only Mode

In CAN Receive Only Mode (RXD only), the driver stage is de-activated but receptio n is still operational. This mode is accessible by an SPI command in Normal Mode and in Stop Mode. The bus biasing is set to VCAN/2.

10.2.4 CAN Wake Capable Mode

This mode can be used in SBC Stop, Sleep, Restart and Normal Mode and it is used to monitor bus activities. It is automatically accessed in SBC Fail-Safe Mode. Both bus pins CANH/L are connected to GND via the input resistors. A wake-up signal on the bus results in a change of behavior of the SBC, as described in Table 16. The pins CANH/L are terminated to typ. 2.5V through the in put resistors. As a wake-up signalization to the microcontroller, the RXD_CAN pin is set LOW and will stay LOW until the CAN transceiver is changed to any other mode. After a wake-up event, the transceiver can be switched to CAN Normal Mode for communication via SPI. As shown in Figure 29, a wake-up pattern (WUP) is signaled on the bus by two consecutive dominant bus levels for at least tWake1 (filter time t > tWake1) and shorter than tWake2, each separated by a recessive bus level of greater than tWake1 and shorter than tWake2.

Datasheet 69 Rev. 1.1 2019-09-27 TLE9261BQXV33 High Speed CAN Transceiver Figure 29 WUP detection following the definition in ISO 11898-2:2016 Rearming the Transceiver for Wake Capability After a BUS wake-up event, the tran sceiver is woken. However, the CAN transceiver mode bits will still show wake capable (=‘01’) so that the RXD signal will be pulled low. There are two possibilities how the CAN transceiver’s wake capable mode is enabled again after a wake event:

The CAN transceiver m ode must be toggled, i.e. switched from Wake Capable Mode to CAN Normal Mode, CAN Receive Only Mode or CAN Off, before switching to CAN Wake Capable Mode again.
Rearming is done automatically w hen the SBC is changed to SBC Stop or SBC Fail-Safe Mode to ensure wake-up capability.
CAN must be set to CAN wake capable / CA N off mode before entering SBC Sleep Mode Note: It is not necessary to clear the CAN wake-up bit CAN_WU to become wake capable again. It is sufficient to toggle the CAN mode. Note: The CAN module is supplied by an internal volt age when in CAN Wake Capable Mode, i.e. the module must not be supplied through the VCAN pin during this time. Before changing the CAN Mode to Normal Mode, the supply of VCAN has to be activated first. Ini Bias off Bias off Bias off Bias on Bias on Wait Bias off Bus recessive > tWAKE1 Bus dominant > tWAKE1 optional: tWAKE2 expired Bus recessive > tWAKE1 Bus dominant > tWAKE1 Bus recessive > tWAKE1Bus dominant > tWAKE1 optional: tWAKE2 expired tSilence expired AND Device in low-power mode tSilence expired AND device in low-power mode Entering CAN Normal or CAN Recive Only Entering low -power mode , when selective wake-up function is disabled or not supported

Datasheet 70 Rev. 1.1 2019-09-27 TLE9261BQXV33 High Speed CAN Transceiver Wake-Up in SBC Stop and Normal Mode In SBC Stop Mode, if a wake-up is detected, it is always signaled by the INT output and in the WK_STAT_1 SPI register. It is also signaled by RXDCAN pulled to low. The same applies for the SBC Normal Mode. The microcontroller should set the device from SBC Stop M o d e t o S B C N o r m a l M o d e , t h e r e i s n o a u t o m a t i c transition to Normal Mode. For functional safety reasons, the watchdog will be automatically enabled in SBC Stop Mode after a Bus wake event in case it was disabled before (if bit WD_EN_ WK_BUS was configured to HIGH before). Wake-Up in SBC Sleep Mode Wake-up is possible via a CAN message (filter time t > tWake1). The wake-up automatically transfers the SBC into the SBC Restart Mode and from there to Normal Mo de the corresponding RXD pin in set to LOW. The microcontroller is able to detect the low signal on RXD and to read the wake source out of the WK_STAT_1 register via SPI. No interrupt is generated when comi ng out of Sleep Mode. The microcontroller can now for example switch the CAN transceiver into CAN Normal Mode via SPI to start communication. Table 16 Action due to CAN Bus Wake-Up SBC Mode SBC Mode after Wake VCC1 INT RXD Normal Mode Normal Mode ON LOW LOW Stop Mode Stop Mode ON LOW LOW Sleep Mode Restart Mode Ramping Up HIGH LOW Restart Mode Restart Mode ON HIGH LOW Fail-Safe Mode Restart Mode Ramping up HIGH LOW

Datasheet 71 Rev. 1.1 2019-09-27 TLE9261BQXV33 High Speed CAN Transceiver

10.2.5 TXD Time-out Feature

I f t h e T X D s i g n a l i s d o m i n a n t f o r a t i m e t > tTXD_CAN_TO, in CAN Normal Mode, the TXD time-out function deactivates the transmission of the signal at the bus. This is implem ented to prevent the bus from being blocked permanently due to an error. The transmitter is disabled and the transceiver is switched to Receive Only Mode. The failure is stored in the SPI flag CAN_FAIL. The CAN transmitter stage is activated again after the dominant time-out condition is removed and the transceiver is automaticall y switched back to CAN Normal Mode. The transceiver configuration stays unchanged.

10.2.6 Bus Dominant Clamping

If the HS CAN bus signal is dominant for a time t > tBUS_CAN_TO in CAN Normal and Receive Only Mode a bus dominant clamping is detected and the SPI bit CAN_FAIL is set. The transceiver configuration stays unchanged.

10.2.7 Undervoltage Detection

The voltage at the CAN supply pin is monitored only in CAN Normal and Receive Only Mode for SBC Normal and Stop Mode . In case of VCAN un dervoltage a signalization via SPI bit VCAN_UV is triggered and the SBC disables the transmitter stage. If th e CAN supply reaches a higher leve l than the undervoltage detection threshold (VCAN > V CAN_UV), the transceiver is automatically sw itched back to CAN Normal Mode. The transceiver configuration stays unchanged.

Datasheet 72 Rev. 1.1 2019-09-27 TLE9261BQXV33 High Speed CAN Transceiver

10.3 Electrical Characteristics

Table 17 Electrical Characteristics VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; 4.75 V < VCAN < 5.25 V; RL = 60 Ω; CAN Normal Mode; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Uni t Note or Test Condition Number Min. Typ. Max. CAN Bus Receiver Differential Receiver Threshold Voltage, recessive to dominant edge Vdiff,rd_N –0 . 8 0 0 . 9 0 V Vdiff = VCANH - VCANL ; -12V ≤ VCM(CAN) ≤ +12V;

0.9 V ≤ Vdiff,D_Range ≤ 8 V;

P_10.3.2 Dominant state differential input voltage range Vdiff_D_range 0.9 – 8.0 V 1)Vdiff = VCANH - VCANL; -12V ≤ VCM(CAN) ≤ +12V; CAN Normal Mode P_10.3.59 Differential Receiver Threshold Voltage, dominant to recessive edge Vdiff,dr_N 0.50 0.60 – V Vdiff = VCANH -VCANL; -12V ≤ VCM(CAN) ≤ +12V; -3 V ≤ Vdiff,R_Range ≤ 0.5 V; CAN Normal Mode P_10.3.3 Recessive state differential input voltage range Vdiff_R_range -3.0 – 0.5 V 1)Vdiff = VCANH - VCANL; -12V ≤ VCM(CAN) ≤ +12V; CAN Normal Mode P_10.3.60 Common Mode Range CMR -12 – 12 V 1) P_10.3.4 CANH, CANL Input Resistance Rin 20 40 50 k Ω CAN Normal / Wake capable Mode; Recessive state; -2 V ≤ V CANL/H ≤ +7 V P_10.3.6 Differential Input Resistance Rdiff 40 80 100 k Ω CAN Normal / Wake capable Mode; Recessive state; -2 V ≤ VCANL/H ≤ +7 V P_10.3.7 Input Resistance Deviation between CANH and CANL ΔRi -3 – 3 % 1)Recessive state; VCANH = VCANL = 5 V P_10.3.38 Input Capacitance CANH, CANL versus GND Cin –2 0 4 0 p F 2)VTXD = 5 V P_10.3.39 Differential Input Capacitance Cdiff –1 0 2 0 p F 2)VTXD = 5 V P_10.3.40 Wake-up Receiver Threshold Voltage, recessive to dominant edge Vdiff, rd_W – 0.8 1.15 V -12V ≤ VCM(CAN) ≤ +12V;

1.15 V ≤ Vdiff,D_Range ≤ 8 V;

P_10.3.8

Datasheet 73 Rev. 1.1 2019-09-27 TLE9261BQXV33 High Speed CAN Transceiver Wake-up Receiver Dominant state differential input voltage range V diff,D_range 1.15 – 8.0 V 1)-12V ≤ VCM(CAN) ≤ +12V; CAN Wake Capable Mode P_10.3.61 Wake-up Receiver Threshold Voltage, dominant to recessive edge V diff, dr_W 0.4 0.7 – V -12V ≤ VCM(CAN) ≤ +12V; -3 V ≤ Vdiff,R_Range ≤ 0.4 V; CAN Wake Capable Mode P_10.3.9 Wake-up Receiver Recessive state differential input voltage range V diff,R_range_ W -3.0 – 0.4 V 1)-12V ≤ VCM(CAN) ≤ +12V; CAN Wake Capable Mode P_10.3.62 CAN Bus Transmitter CANH/CANL Recessive Output Voltage (CAN Normal Mode) VCANL/H_NM 2.0 – 3.0 V CAN Normal Mode; VTXD = VCC1; no load P_10.3.11 CANH/CANL Recessive Output Voltage (CAN Wake Capable Mode) V CANL/H_LP -0.1 – 0.1 V CAN Wake Capable Mode; VTXD = VCC1; no load P_10.3.43 CANH, CANL Recessive Output Voltage Difference Vdiff = VCANH - VCANL (CAN Normal Mode) Vdiff_r_N -500 – 50 mV CAN Normal Mode VTXD = VCC1; no load P_10.3.12 CANH, CANL Recessive Output Voltage Difference V diff = VCANH - VCANL (CAN Wake Capable Mode) Vdiff_r_W -200 – 200 mV CAN Wake Capable Mode; V TXD = VCC1; no load P_10.3.41 CANL Dominant Output Voltage VCANL 0.5 – 2.25 V CAN Normal Mode; VTXD = 0 V; VCAN = 5 V; 50Ω ≤ RL ≤ 65Ω P_10.3.13 CANH Dominant Output Voltage VCANH 2.75 – 4.5 V CAN Normal Mode; VTXD = 0 V; VCAN = 5 V; 50Ω ≤ RL ≤ 65Ω P_10.3.14 CANH, CANL Dominant Output Voltage Difference Vdiff = VCANH - VCANL Vdiff_d_N 1.5 2.0 2.5 V CAN Normal Mode; VTXD = 0 V; VCAN = 5 V; 50Ω ≤ RL ≤ 65Ω P_10.3.16 Table 17 Electrical Characteristics (cont’d) VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; 4.75 V < VCAN < 5.25 V; RL = 60 Ω; CAN Normal Mode; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Uni t Note or Test Condition Number Min. Typ. Max.

Datasheet 74 Rev. 1.1 2019-09-27 TLE9261BQXV33 High Speed CAN Transceiver CANH, CANL Dominant Output Voltage Difference V diff = VCANH - VCANL Vdiff_d_N 1.5 – 5.0 V 1)CAN Normal Mode; VTXD = 0 V; VCAN = 5 V; RL = 2240Ω P_10.3.55 CANH, CANL Dominant Output Voltage Difference V diff = VCANH - VCANL Vdiff_d_N 1.4 – 3.3 V 1)CAN Normal Mode; VTXD = 0 V; VCAN = 5 V; 45Ω ≤ RL ≤ 70Ω P_10.3.56 CANH, CANL output voltage difference slope, recessive to dominant V diff_slope_rd ––7 0 V / u s 1)30% to 70% of measured differential bus voltage, C L = 100 pF, RL = 60 Ω P_10.3.57 CANH, CANL output voltage difference slope, dominant to recessive Vdiff_slope_dr ––7 0 V / u s 1)70% to 30% of measured differential bus voltage, CL = 100 pF, RL = 60 Ω P_10.3.58 Driver Symmetry VSYM = VCANH + VCANL VSYM 4.5 – 5.5 V 3)CAN Normal Mode; VTXD = 0 V / 5 V; VCAN = 5 V; CSPLIT = 4.7nF; RL = 60Ω; P_10.3.42 CANH Short Circuit Current ICANHsc -115 -80 -50 mA CAN Normal Mode; VCANHshort = -3 V P_10.3.17 CANL Short Circuit Current ICANLsc 50 80 115 mA CAN Normal Mode VCANLshort = 18 V P_10.3.18 Leakage Current (unpowered device) ICANH,lk ICANL,lk – 5 7.5 µA VS = VCAN = 0V; 0V < VCANH,L ≤ 5V; 4)Rtest = 0 / 47 kΩ P_10.3.19 Receiver Output RXD HIGH level Output Voltage VRXD,H 0.8 × VCC1 ––V C A N N o r m a l M o d e IRXD(CAN) = -2 mA; P_10.3.21 LOW Level Output Voltage VRXD,L – – 0.2 × VCC1 VC A N N o r m a l M o d e IRXD(CAN) = 2 mA; P_10.3.22 Transmission Input TXD HIGH Level Input Voltage Threshold VTXD,H – – 0.7 × VCC1 VC A N N o r m a l M o d e recessive state P_10.3.23 LOW Level Input Voltage Threshold VTXD,L 0.3 × VCC1 ––V C A N N o r m a l M o d e dominant state P_10.3.24 Table 17 Electrical Characteristics (cont’d) VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; 4.75 V < VCAN < 5.25 V; RL = 60 Ω; CAN Normal Mode; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Uni t Note or Test Condition Number Min. Typ. Max.

Datasheet 75 Rev. 1.1 2019-09-27 TLE9261BQXV33 High Speed CAN Transceiver TXD Input Hysteresis VTXD,hys 0.08 × VCC1 0.12 × VCC1 0.5 × VCC1 V 1) P_10.3.25 TXD Pull-up Resistance RTXD 20 40 80 k Ω – P_10.3.26 CAN Transceiver Enabling Time tCAN,EN 81 3 1 8 µ s 5)CSN = HIGH to first valid transmitted TXD dominant P_10.3.27 Dynamic CAN-Transceiver Characteristics Min. Dominant Time for Bus Wake-up tWake1 0.50 – 1.8 µs -12V ≤ VCM(CAN) ≤ +12 V; CAN Wake capable Mode P_10.3.28 Wake-up Time-out, Recessive Bus tWake2 0.8 – 10 ms 5)CAN Wake capable Mode P_10.3.29 WUP Wake-up Reaction Time tWU_WUP – – 100 µs 5)6)7) Wake-up reaction time after a valid WUP on CAN bus; P_10.3.44 Loop delay (recessive to dominant) t LOOP,f – 150 255 ns 3)CAN Normal Mode CL = 100 pF; RL = 60 Ω; VCAN = 5 V; CRXD = 15 pF P_10.3.30 Loop delay (dominant to recessive) tLOOP,r – 150 255 ns 3)CAN Normal Mode CL = 100 pF; RL = 60 Ω; VCAN = 5 V; CRXD = 15 pF P_10.3.31 Propagation Delay TXD LOW to bus dominant td(L),T – 50 – ns CAN Normal Mode CL = 100pF; 50Ω ≤ RL ≤ 65Ω; VCAN = 5 V; P_10.3.32 Propagation Delay TXD HIGH to bus recessive td(H),T – 50 – ns CAN Normal Mode CL = 100 pF; 50Ω ≤ RL ≤ 65Ω; VCAN = 5 V; P_10.3.33 Propagation Delay bus dominant to RXD LOW td(L),R – 100 – ns CAN Normal Mode CL = 100pF; 50Ω ≤ RL ≤ 60Ω; VCAN = 5 V; CRXD = 15 pF P_10.3.34 Table 17 Electrical Characteristics (cont’d) VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; 4.75 V < VCAN < 5.25 V; RL = 60 Ω; CAN Normal Mode; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Uni t Note or Test Condition Number Min. Typ. Max.

Datasheet 79 Rev. 1.1 2019-09-27 TLE9261BQXV33 Wake and Voltage Monitoring Inputs

11 Wake and Voltage Monitoring Inputs

11.1 Block Description

Figure 32 Wake Input Block Diagram

Three High-Voltage inputs with a 3V (typ.) threshold voltage
Alternate Measurement function for high-voltage sensing via WK1 and WK2
Wake-up capability fo r power saving modes
Edge sensitive wake feature LOW to HIGH and HIGH to LOW
Pull-up and Pull-down current s ources, configurable via SPI
Selectable configuration for st atic sense or cyclic sense working with TIMER1, TIMER2
In SBC Normal and SBC Stop Mode the level of the WK pin can be read via SPI even if the respective WK is not enabled as a wake source. MONx_Input _Circuit_ext.vsd tWK WKx Internal Supply Logic IPD_WK IPU_WK VRef

Datasheet 80 Rev. 1.1 2019-09-27 TLE9261BQXV33 Wake and Voltage Monitoring Inputs

11.2 Functional Description

The wake input pins are edge-sensitive inputs with a switching threshold of typically 3V. This means that both transitions, HIGH to LOW and LOW to HIGH, result in a signalization by the SBC. The signalization occurs either in triggering the interrupt in SBC Normal Mode and SBC Stop Mode or by a wake up of the device in SBC Sleep and SBC Fail-Safe Mode. Two different wake detection modes can be selected via SPI:

Static sense: WK inputs are always active
Cyclic sense: WK inputs are only active for a certain time period (see Chapter 5.2.1) Two different filter times of 16µs or 64µs can be selected to avoid a parasitic wake-up due to transients or EMC disturbances in static sense configuration. The filter time (tFWK1, tFWK2) is triggered by a level change crossing the switching threshold and a wake signal is recognized if the input level will not cross again the threshold during the selected filter time. Figure 33 shows a typical wake-up timing and parasitic filter. Figure 33 Wake-up Filter Timing for Static Sense The wake-up capability for each WK pin can be e n a b l e d o r d i s a b l e d v i a S P I c o m m a n d i n t h e WK_CTRL_2 register. The wake source for a wake via a WKx pin can always be read in the register WK_STAT_1 at the bits WK1_WU, WK2_WU, and WK3_WU. The actual voltage level of the WK pin (LOW or HIGH) can always be read in SBC Normal and SBC Stop Mode in the register WK_LVL_STAT. During Cyclic Sense, the register show the sampled levels of the respective WK pin. If FO2...3 are configured as WK inputs in its alternative function (16µs static filter time), then the wake events will be signalled in the register WK_STAT_2. VWK,th t VWK tWK,f No Wake Event Wake Event VWK,th tWK,f t VINT tINT

Datasheet 81 Rev. 1.1 2019-09-27 TLE9261BQXV33 Wake and Voltage Monitoring Inputs

11.2.1 Wake Input Configuration

To ensure a defined and stable voltage levels at the in ternal comparator input it is possible to configure integrated current sources via the SPI register WK_PUPD_CTRL. In addition, the wake detection modes (including the filter time) can be configured via the SPI register WK_FLT_CTRL. An example illustration for the automatic switching configuration is shown in Figure 34. Note: If there is no pull-up or pull-d own configured on the WK input, then the respective input should be tied to GND or VS on board to avoid unintended floating of the pin and subsequent wake events. Figure 34 Illustration for Pull -Up / Down Current Sources with Automatic Switching Configuration Config A and B are intended for static sense with two different filter times. Table 18 Pull-Up / Pull-Down Resistor WKx_PUPD_1 WKx_PUPD_0 Current Sources Note 00n o c u r r e n t source WKx input is floating if left open (default setting) 0 1 pull-down WKx input internally pulled to GND 1 0 pull-up WKx input internally pulled to internal 5V supply 1 1 Automatic switching If a high level is detected at the WKx input the pull-up source is activated, if low level is detected the pull down is activated. Table 19 Wake Detection Configuration and Filter Time WKx_FLT_1 WKx_FLT_0 Filter Time Description 0 0 Config A static sense, 16µs filter time 0 1 Config B static sense, 64µs filter time 1 0 Config C Cyclic sense, Timer 1, 16µs filter time. Period, On-time configurable in register TIMER1_CTRL 1 1 Config D Cyclic sense, Timer 2, 16µs filter time. Period, On-time configurable in register TIMER2_CTRL IWK IWKth _min IWKth_max VWKth

Datasheet 82 Rev. 1.1 2019-09-27 TLE9261BQXV33 Wake and Voltage Monitoring Inputs Config C or D are intended for cyclic sense configuration. With the filter settings, the respective timer needs to be assigned to one or more HS output, which supplies an external circuit connected to the WKx pin, e.g. HS1 controlled by Timer 2 (HS1 = 010) and connected to WK3 via an switch circuitry - see also Chapter 5.2.

Datasheet 83 Rev. 1.1 2019-09-27 TLE9261BQXV33 Wake and Voltage Monitoring Inputs

11.2.2 Alternate Measurement Function with WK1 and WK2

11.2.2.1 Block Description

This function provides the possibility to measure a voltage, e.g. th e unbuffered battery voltage, with the protected WK1 HV-input. The measured voltage is routed out at WK2. It allows for example a voltage compensation for LED lighting by chan ging the duty cycle of the High-Side outputs. A simple voltage divider needs to be placed externally to provide the correct voltage level to the microcontroller A/D converter input. The function is available in SBC Normal Mode and it is disabled in all other mode s to allow a low-quiescent current operation.The measurement function can be used instead of the WK1 and WK2 wake and level signalling capability. The benefits of the function is that the signal is measured by a HV-input pin and that there is no current flowing through the resistor divider during low-power modes. The functionality is shown in a simplified application diagram in Figure 54.

11.2.2.2 Functional Description

This measurement function is by default disabled. In this case, WK1 and WK2 have the regular wake and voltage level signalization functionality. The switch S1 is open for this configuration (see Figure 54). The measurement function can be enabled via the SPI bit WK_MEAS. If WK_MEAS is set to ‘1’, then the measurement function is enabled and switch S1 is closed in SBC Normal Mode. S1 is open in all other SBC modes. If this func tion the pull-up and down currents of WK1 and WK2 are disabled, and the internal WK1 and WK2 signals are gat ed. In addition, the settings for WK1 and WK2 in the registers WK_PUPD_CTRL, WK_FLT_CTRL and WK_CTRL_2 are ignored but changing these setting is not prevented. The registers WK_STAT_1 and WK_LVL_STAT are not updated with respect to the inputs WK1 and WK2. However, if only WK1 or WK2 are set as wake sources and a SBC Sleep Mode command is set, then the SPI_FAIL flag will be set and the SBC will be changed into SBC Restart Mode (see Chapter 5.1 also for wake capability of WK1 and WK2). Table 20 Differences between Normal WK Function and Measurement Function Affected Settings/Modules for WK1 and WK2 Inputs WK_MEAS = 0 WK_MEAS = 1 S1 configuration ‘open’ ‘clos ed’ in SBC Normal Mode, ‘open’ in all other SBC Modes Internal WK1 & WK2 signal processing Default wake and level signaling function, WK_STAT_1, WK_STAT_2 are updated accordingly ‘WK1...2 inputs are gated internally, WK_STAT_1, WK_STAT_2 are not updated WK1_EN, WK2_EN Wake-up via WK1 and WK2 possible if bits are set setting the bits is ignored and not prevented. If only WK1_EN, WK2_EN are set while trying to go to SBC Sleep Mode, then the SPI_FAIL flag will be set and the SBC will be changed into SBC Restart Mode. WK_PUPD_CTRL normal configuration is possible n o pull-up or pull-down enabled WK_FLT_CTRL normal configuration is possible se tting the bits is ignored and not prevented

Datasheet 84 Rev. 1.1 2019-09-27 TLE9261BQXV33 Wake and Voltage Monitoring Inputs Note: There is a diode in series to the switch S1 (not shown in the Figure 54), which will influence the temperature behavior of the switch.

11.3 Electrical Characteristics

Table 21 Electrical Characteristics VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. WK1...WK3 Input Pin Characteristics Wake-up/monitoring threshold voltage VWKth 2 3 4 V without external serial resistor RS (with RS: ΔV = IPD/PU * RS); hysteresis included P_12.3.1 Threshold hysteresis VWKNth,hys 0.1 - 0.7 V without external serial resistor RS (with RS: ΔV = IPD/PU * RS); P_12.3.2 WK pin Pull-up Current IPU_WK -20 -10 -3 µA VWK_IN = 4V P_12.3.3 WK pin Pull-down Current IPD_WK 31 0 2 0 µ A VWK_IN = 2V P_12.3.4 Input leakage current ILK,l -2 2 µA 0 V < VWK_IN < 40V P_12.3.5 Drop Voltage across S1 switch VDrop,S1 – 1000 1100 mV 1)Drop Voltage between WK1 and WK2 when enabled for voltage measurement; I WK1 = 500µA; Tj = 25°C Refer to Figure 35 1) Not subject to production test; specified by design P_12.3.13 Timing Wake-up filter time 1 tFWK1 12 16 20 µs 2)SPI Setting 2) Not subject to production test, tolerance defined by internal oscillator tolerance P_12.3.6 Wake-up filter time 2 tFWK2 50 64 80 µs 2)SPI Setting P_12.3.7

Datasheet 85 Rev. 1.1 2019-09-27 TLE9261BQXV33 Wake and Voltage Monitoring Inputs Figure 35 Typical Drop Voltage Charac teristics of S1 (between WK1 & WK2) 800 900 1000 1100 AGE/g3DROP/g3OF/g3SWITCH/g3S1/g3/g3(mV) VS = 13.5V 250 μA 500 μA 500 600 700 /g88250 0 50 100 150 VS1,/g3VOLTA Tj/g3/g3/g3/g882 JUNCTION/g3TEMPERATURE/g3(°C) 50 μA 100 μA

Datasheet 86 Rev. 1.1 2019-09-27 TLE9261BQXV33 Interrupt Function

12 Interrupt Function

12.1 Block and Functional Description

Figure 36 Interrupt Block Diagram The interrupt is used to signalize sp ecial events in real time to the mi crocontroller. The interrupt block is designed as a push/pull output stage as shown in Figure 36. An interrupt is triggered and the INT pin is pulled low (active low) for tINT in SBC Normal and Stop Mode and it is released again once tINT is expired. The minimum HIGH-time of INT between two consecutive interrupts is tINTD. An interrupt does not cause a SBC mode change. Two different interrupt classes could be selected via the SPI bit INT_ GLOBAL:

Class 1 (wake interrupt - INT_ GLOBAL=0): all wake-up events stored in the wake status SPI register (WK_STAT_1 and WK_STAT_2) cause an interrupt (default setting). An interrupt is only triggered if the respective function is also enabled as a wake source (including GPIOx if configured as a wake input).
Class 2 (globa l interrupt - INT_ GLOBAL=1): in addition to the wake-up events, all signalled failures stored in the other status registers cause an interrupt (the register WK_LVL_STAT is not generating interrupts) Note: The errors which will cause SBC Restart or SB C Fail-Safe Mode (Vcc1_UV, WD_FAIL, VCC1_SC, TSD2, FAILURE) are the exceptions of an INT generation on status bits. Also POR and DEV_STAT_x and will not generate interrupts. In addition to this behavior, an INT will be triggered when the SBC is se nt to SBC Stop Mode and not all bits were cleared in the WK_STAT_1 and WK_STAT_2register. The SPI status registers are updated at every falling edge of the INT pulse. All interrupt events are stored in the respective register (except the register WK_LVL_STAT) until the register is read and cleared via SPI command. A second SPI read after reading out the respective status register is optional but recommended to verify that the interrupt event is not present anymore. The interrupt behavior is shown in Figure 37 for class 1 interrupts. The behavior for class 2 is identical. The INT pin is also used during SBC Init Mode to select the hardware configuration of the device. See Chapter 5.1.1 for further information. Interrupt logic INT Time out Vcc1

Datasheet 87 Rev. 1.1 2019-09-27 TLE9261BQXV33 Interrupt Function Figure 37 Interrupt Signalization Behavior Interrupt_Behavior.vsd INT WK1 WK2 tINT tINTD Update of WK_STAT register SPI Read & Clear Update of WK_STAT register WK_STAT

Scenario 1 WK1 no WK WK2 no WK optional SPI Read & Clear WK_STAT Scenario 2 WK1 + WK2 no WK No SPI Read & Clear Command sent

Datasheet 88 Rev. 1.1 2019-09-27 TLE9261BQXV33 Interrupt Function

12.2 Electrical Characteristics

Table 22 Electrical Characteristics VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Interrupt Output; Pin INT INT High Output Voltage V INT,H 0.8 × VCC1 –– V 1)IINT = -1 mA; INT = OFF 1) Output Voltage Value also determines de vice configuration during SBC Init Mode P_13.2.1 INT Low Output Voltage VINT,L – – 0.2 × VCC1 V 1)IINT = 1 mA;INT = ON P_13.2.2 INT Pulse Width tINT 80 100 120 µs 2) 2) Not subject to production test, tolerance defined by internal oscillator tolerance. P_13.2.3 INT Pulse Minimum Delay Time tINTD 80 100 120 µs 2) between consecutive pulses P_13.2.4 Configuration Select; Pin INT Config Pull-down Resistance RCFG 180 250 350 k Ω VINT = 3.3 V P_13.2.5 Config Select Filter Time tCFG_F 5 10 14 µs P_13.2.6

Datasheet 89 Rev. 1.1 2019-09-27 TLE9261BQXV33 Fail Outputs

13 Fail Outputs

13.1 Block and Functional Description

Figure 38 Simplified Fail Output Block Diagram for FO1/2 and for FO3/TEST The fail outputs consist of a failure logic block and three open-drain outputs (FO1, FO2, FO3) with active-low signalization. The fail outputs are activated due to following failure conditions:

Watchdog trigger failure (For config 3&4 only after the 2nd watchdog trigger failure and for config 1&2 after 1st watchdog trigger failure)
Thermal shutdown TSD2
VCC1 short to GND
VCC1 overvoltage (only if the SPI bit VCC1_OV_RST is set)
After 4 consecutive VCC1 undervoltage event (see Chapter 14.6 for details) At the same time SBC Fail-Safe Mode is entered (e xceptions are watchdog trigger failures depending on selected configurations - see Chapter 5.1.1). The fail output activation is signalled in the SPI bit FAILURE of the register DEV_STAT. For testing purposes only the Fa il Outputs can also be activa ted via SPI by setting the bit FO_ON. This bit is independent of the FO failure bits. In case that there is no failure condition, the FO outputs can also be turned off again via SPI, i.e. no successful watchdog trigger is needed. The entry of SBC Fail-Safe Mode due to a watchdog failure can be configured as described in Chapter 5.1.1. In order to deactivate the fail outputs in SBC Normal Mode the failure conditions must not be present anymore (e.g. TSD2, VCC1 short circuit, etc) and the bit FAILURE needs to be cleared via SPI command. In case of a watchdog failure the correct procedure to deactivate the fail outputs is:
a successful WD trigger, i.e. WD_FAIL must be cleared
clearing of the FAILURE bit WD_FAIL will also be cleared when going to SBC Sleep or SBC Fail-Safe Mode due to another failure (not a WD failure) or if the watchdog is disabled in SBC Stop Mode Failure logic FO1/2 FO3/TEST 5V_int RTEST SBC Init Mode Failure Logic T test T FO_PL

Datasheet 90 Rev. 1.1 2019-09-27 TLE9261BQXV33 Fail Outputs Note: The Fail output pin is triggered for any of the above described failures. No FAILURE is caused for the 1st watchdog failure if selected for Config2. The three fail outputs are activated simultaneously with following output functionalities:

FO1: Static fail output
FO2: 1.25Hz, 50% (typ.) duty cycle, e.g. to generate an indicator signal
FO3: 100Hz PWM, 20% (typ.) duty cycle, e.g. to generate a dimmed rear light from a break light. Note: The duty cycle for FO3 can be configured via SP I option to 20%, 10%, 5% or 2.5%. Default value is 20%. See the register FO_DC for configuration.

13.1.1 General Purpose I/O Functionality of FO2 and FO3 as Alternate Function

In case that FO2 and FO3 are not used in the application, those pins can also be configured with an alternate function as high-voltage (VSHS related) General Purpose I/O pins. Figure 39 Simplified General Purpos e I/O block diagram for FO2 and FO3/TEST The pins are by default configured as FO pins. The configuration is done via the SPI register GPIO_CTRL. The alternate function can be:

Wake Inputs: The detection threshold VGPIOI,th is similar as for the WK inputs. The wake-up detection behavior is the same as for WKx pins. Wake events are stored and reported in WK_STAT_2.
Low-Side Switches: The switch i s able to drive currents of up to 10mA (see also VGPIOL,L1). It is self-protected with regards to current limitation. No other diagnosis is implemented.
High-Side Switches: The switch is able to drive currents up to 10mA (see also VGPIOH,H1). It is self-protected with regards to current limitation. No other diagnosis is implemented.
If configured as GPIO then the respective level at the pin will be shown in WK_LVL_STAT in SBC Normal and Stop Mode. This is also the case if configured as LS/HS and can serve as a feedback about the respective state. GPIO2 is shared with the TEST level bit. Table 23 describes the behavior of the FO/GPIO pins in their different configurations and SBC modes. Config & Control Logic FOx/ GPIOx VSHS

Datasheet 91 Rev. 1.1 2019-09-27 TLE9261BQXV33 Fail Outputs Explanation of FO/GPIO states:

configurable: settings can be changed in this SBC mode
fixed: settings stay as configured in SBC Normal Mode
active: FOx is activated due to a failure leading to SBC Restart or Fail-Safe Mode. Restart Behavior: The behavior during SBC Restart and Fail-Safe Mode as well as the transition to SBC Normal Mode is as follows:
if configured as Wake Input: it will stay wake capa ble during SBC Restart Mode and OFF while in SBC Fail- Safe Mode. It will resume wake capability when leaving SBC Restart Mode (SPI register is not modified)
if configured as Low-Side or High-Side: They will be disabled during SBC Restart and Fail-Safe Mode. After leaving SBC Restart Mode the previously configured function will be resumed (SPI register is not modified)
if configured as FO and activated du e to a failure: FO will stay activated during SBC Restart Mode and when entering SBC Normal Mode (SPI register is not modified) Note: In order to avoid unintentional entry of SBC Deve lopment Mode care must be taken that the level of FO3/TEST is HIGH during device power up and SBC Init Mode. Note: The FOx drivers are supplied via VS. However, th e GPIO HS switches (FO2, FO3/TEST) are supplied by VSHS Table 23 Fail-Output and GPIO configuration behavior during the respective SBC Modes FOx Configuration SBC Normal Mode SBC Stop Mode SBC Sleep Mode SBC Restart Mode SBC Fail-Safe Mode FOx (default) configurable fixed fixed active / fixed active OFF OFF OFF OFF OFF Wake Input wake capable wake capable wake capable OFF Low-Side fixed fixed OFF OFF High-Side fixed fixed OFF OFF

Datasheet 92 Rev. 1.1 2019-09-27 TLE9261BQXV33 Fail Outputs

13.2 Electrical Characteristics

Table 24 Electrical Characteristics VSHS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.1) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Pin FO1 FO1 low output voltage (active) V FO,L1 –– 1 . 0 V IFO = 4mA P_14.2.1 FO1 high output current (inactive) IFO,H 0– 2µ A VFO = 28V P_14.2.2 Pin FO2 FO2 side indicator frequency FO2 side indicator duty cycle dFO2SI 45 50 55 % 3) P_14.2.4 Pin FO3/TEST2) Pull-up Resistance at pin FO3/TEST RTEST 2.5 5 10 k Ω VTEST =0V; SBC Init Mode P_14.2.5 TEST Input Filter Time tTEST 50 64 80 µs 3) P_14.2.6 FO3 pulsed light frequency fFO3PL 80 100 120 Hz 3) P_14.2.7 FO3 pulsed light duty cycle dFO3PL 16 20 24 % 3)4)default setting P_14.2.8 Alternate FO2...3 Electrical Characteristics: GPIO GPIO low-side output voltage (active) VGPIOL,L1 –– 1V IGPIO = 10mA P_14.2.9 GPIO low-side output voltage (active) VGPIOL,L2 –– 5m V 5)IGPIO = 50µA P_14.2.17 GPIO high-side output voltage (active) VGPIOH,H1 VSHS-1 – – V IGPO = -10mA P_14.2.10 GPIO high-side output voltage (active) VGPIOH,H2 VSHS-5 – – mV 5)IGPO = -50µA P_14.2.18 GPIO input threshold voltage GPIO input threshold hysteresis VGPIOI,hys 100 400 700 mV 5) P_14.2.12 GPIO low-side current limitation IGPIOL,max 10 – 30 mA VGPIO = 28V P_14.2.13 GPIO high-side current limitation IGPIOH,max -45 – -10 mA VGPIO = 0V P_14.2.14

Datasheet 93 Rev. 1.1 2019-09-27 TLE9261BQXV33 Fail Outputs 1) The FOx drivers are supplied via VS. However, the GP IO HS switches (FO2, FO3/TEST) are supplied by VSHS 2) The external capacitance on this pin must be limite d to less than 10nF to ensure proper detection of SBC Development Mode and SBC User Mode operation. 3) Not subject to production test, tolerance defined by internal oscillator tolerance. 4) The duty cyclic is adjustable via the SPI bits FO_DC. 5) Not subject to production test, specified by design. 6) Applies also for TEST voltage input level

Datasheet 94 Rev. 1.1 2019-09-27 TLE9261BQXV33 Supervision Functions

14 Supervision Functions

14.1 Reset Function

Figure 40 Rese t Block Diagram

14.1.1 Reset Output Description

The reset output pin RO provides a reset information to the microcontroller, for example, in the event that the output voltage has fallen below the undervoltage threshold VRT1/2/3/4. In case of a reset event, the reset output RO is pulled to low after the filter time tRF and stays low as long as the reset event is present plus a reset delay time tRD1. When connecting the SBC to battery voltage, the reset signal remains LOW initially. When the output voltage Vcc1 has reached the reset default threshold V RT1,r, the reset output RO is released to HIGH after the reset delay time t RD1. A reset can also occur due to a watchdog trigger failur e. The reset threshold can be adjusted via SPI, the default reset threshold is VRT1,f. The RO pin has an integrated pull-up resistor. In case reset is triggered, it will be pulled low for Vcc1 ≥ 1V and for VS ≥ VPOR,f (see also Chapter 14.3). The timings for the RO triggering regarding VCC1 undervoltage and watchdog trigger is shown in Figure 41. Reset logic Incl. filter & delay RO VCC1

Datasheet 95 Rev. 1.1 2019-09-27 TLE9261BQXV33 Supervision Functions Figure 41 Reset Timing Diagram

14.1.2 Soft Reset Description

In SBC Normal and SBC Stop Mode, it is also possible to trigger a device internal reset via a SPI command in order to bring the SBC into a defined state in case of failures. In this case the microcontroller must send a SPI command and set the MODE bits to ‘11’ in the M_S_CTRL register. As soon as th is command becomes valid, the SBC is set back to SBC INIT Mode and all SPI registers are set to their default values (see SPI Chapter 15.5 and Chapter 15.6). Two different soft reset configurations are possible via the SPI bit SOFT_ RESET_RO:

The reset output (RO) is trigg ered when the soft reset is executed (default setting, the same reset delay time tRD1 applies)
The reset output (RO) is not tr iggered when the soft reset is executed Note: The device must be in SBC Normal Mode or SBC Stop Mode when sending this command. Otherwise, the command will be ignored. The reset threshold can be configured via SPI in SBC Normal Mode, default is V RT1 tRD1 tLW SBC Init RO SPI t VCC VRT1 undervoltage tRD1 SBC Normal t t tLW t < tRF tRF tCW SBC Restart SBC Normal SPI Init tCW tOW WD Trigger tCW tOW WD Trigger SPI Init tLW= long open window tCW= closed window tOW= open window

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14.2 Watchdog Function

The watchdog is used to mo nitor the software execution of the microc ontroller and to trigger a reset if the microcontroller stops serving the watchdog due to a lock up in the software. Two different types of watchdog functions are implemented and can be selected via the bit WD_WIN:

Time-Out Watchdog (default value)
Window Watchdog The respective watchdog functions can be selected and programmed in SBC Normal Mode. The configuration stays unchanged in SBC Stop Mode. Please refer to Table 25 to match the SBC Modes with the respective watchdog modes. The watchdog timing is programmed via SPI command. As soon as the watchdog is programmed, the timer starts with the new setting and the watchdog must be served. The watchd og is triggered by sending a valid SPI-write command to the watchdog configuration regist er. The trigger SPI comman d is executed when the Chip Select input (CSN) becomes HIGH. When coming from SBC Init, SBC Restart Mode or in certain cases from SBC Stop Mode, the watchdog timer is always started with a long open window. The long open window (t LW = 200ms) allows the microcontroller to run its initialization sequences and then to trigger the watchdog via SPI. The watchdog timer period can be selected via the watchdog timing bit field (WD_TIMER) and is in the range of 10 ms to 1000 ms. This setting is valid for both watchdog types. The following watchdog timer periods are available:
WD Setting 1: 10ms
WD Setting 2: 20ms
WD Setting 3: 50ms
WD Setting 4: 100ms
WD Setting 5: 200ms
WD Setting 6: 500ms
WD Setting 7: 1000ms In case of a watchdog reset, SBC Restart or SBC Fail-Safe Mode is entered according to the configuration and the SPI bits WD_FAIL are set. Once the RO goes HIGH again the watchdog immediately starts with a long open window the SBC enters automatically SBC Normal Mode. In SBC Development Mode the watchdog is OFF and ther efore no reset and interrupt are generated due to a watchdog failure. Table 25 Watchdog Functionality by SBC Modes SBC Mode Watchdog Mode Remarks INIT Mode Starts with Long Open Window Watchdog starts with Long Open Window after RO is released Normal Mode WD Programmable Window Watchdog, Time-Out watchdog or switched OFF for SBC Stop Mode Stop Mode Watchdog is fixed or OFF Sleep Mode OFF SBC will start with Long Open Window when entering SBC Normal Mode. Restart Mode OFF SBC will start with Long Open Window when entering SBC Normal Mode.

Datasheet 97 Rev. 1.1 2019-09-27 TLE9261BQXV33 Supervision Functions Depending on the configuration, the WD_FAIL bits will be set after a watchdog trigger failure as follows:

In case an incorrect WD trigger is received (triggering in the closed watchdog window or when the watchdog counter expires without a valid trigger) then the WD_FAIL bits will be increased (showing the number of incorrect WD triggers)
For config 2: the bits can hav e the maximum value of ‘01’
For config 1, 3 and 4 : the bits can have the maximum value of ‘10’ The WD_FAIL bits are cleared automatically when following conditions apply:
After a successful watchdog trigger
When the watchdog is OFF: in SBC Stop Mode after successfully disabling it, in SBC Sleep Mode, or in SBC Fail-Safe Mode (except for a watchdog failure)

14.2.1 Time-Out Watchdog

The time-out watchdog is an easier and less secure watchdog than a window watchdog as the watchdog trigger can be done at any time within the configured watchdog timer period. A correct watchdog service immediately results in starting a new watchdog timer period. Taking the tolerances of the internal oscillator into account leads to the safe trigger area as defined in Figure 42. If the time-out watchdog pe riod elapses, a watchdog reset is create d by setting the rese t output RO low and the SBC switches to SBC Restart or SBC Fail-Safe Mode. Figure 42 Time-out Watchdog Definition open window t / [tWD_TIMER ] safe trigger area Wd1_TimeOut_per.vsd Watchdog Timer Period (WD_TIMER) uncertainty Typical timout watchdog trigger period tWD x 1.80tWD x 1.20 tWD x 1.50

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14.2.2 Window Watchdog

Compared to the time-out watchdog the characteristic of the window wa tchdog is that the watchdog timer period is divided between an closed and an open window. The watchdog must be triggered within the open window. A correct watchdog trigger results in starting the window watchdog period by a closed window followed by an open window. The watchdog timer period is at the same time the ty pical trigger time and defi nes the middle of the open window. Taking the oscillator tolerances into account leads to a safe trigger area of: tWD x 0.72 < safe trigger area < tWD x 1.20. The typical closed window is defined to a width of 60% of the selected window watchdog timer period. Taking the tolerances of the internal oscillator into account leads to the timings as defined in Figure 43. A correct watchdog service immediately results in starting the next closed window. Should the trigger signal meet the closed window or should the watchdog time r period elapse, then a watchdog reset is created by setting the reset output RO low and the SBC switches to SBC Restart or SBC Fail- Safe Mode. Figure 43 Window Watchdog Definition closed window open window t / [tWD_TIMER ] safe trigger area tWD x 0.72 t WD x 1.20 uncertainty uncertainty tWD x 0.48 t WD x 1.80 Watchdog Timer Period (WD_TIMER) Typ. closed window Typ. open window tWD x 0.6 tWD x 1.0 tWD x 0.9

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14.2.3 Watchdog Setting Check Sum

A check sum bit is part of the SPI commend to trigger the watchdog and to set the watchdog setting. The sum of the 8 data bits in the register WWD_CTRL needs to have even parity (see Equation (14.1)). This is realized by either setting the bit CHECKSUM to 0 or 1. If the check sum is wrong, then the SPI command is ignored, i.e. the watchdog is not triggered or the settings are not changed and the bit SPI_FAIL is set. The checksum is calculated by taking all 8 data bits into account. The written value of the reserved bit 3 of the WWD_CTRL register is considered (even if read as ‘0’ in the SPI output) for checksum calculation, i.e. if a 1 is written on the reserved bit position, then a 1 will be used in the checksum calculation. (14.1) CHKSUM Bit15 … Bit8⊕⊕=

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14.2.4 Watchdog during SBC Stop Mode

The watchdog can be disabled for SBC Stop Mode in SBC Normal Mode. For safety reasons, there is a special sequence to be followed in order to disable the watchdog as described in Figure 44. Two different SPI bits (WD_STM_ EN_0, WD_STM_ EN_1) in the registers WK_CTRL_1 and WD_CTRL need to be set. Figure 44 Watchdog disablin g sequence in SBC Stop Mode If a sequence error occurs, then the bit WD_STM_ EN_1 will be cleared and the sequence has to be started again. The watchdog can be enabled by triggering the watchd og in SBC Stop Mode or by switching back to SBC Normal Mode via SPI command. In bo th cases the watchdog will start with a long open window and the bits WD_STM_EN_1 and WD_STM_ EN_0 are cleared. After the long open window the wa tchdog has to be served as configured in the WD_CTRL register. Note: The bit WD_STM_ EN_0 will be cleared automatically when the sequence is started and it was 1 before. Correct WD disabling sequence Set bit WD_STM_EN_1 = 1 Set bit WD_STM_EN_0 = 1 with next WD Trigger WD is switched off Sequence Errors

Missing to set bit WD_STM_EN_0 with the next watchdog trigger after having set WD_STM_EN_1
Staying in Normal Mode instead of going to Stop Mode with the next trigger Change to SBC Stop Mode Before subsequent WD Trigger Will enable the WD :
Switching back to SBC Normal Mode
Triggering the watchdog

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14.2.5 Watchdog Start in SBC Stop Mode due to Bus Wake

In SBC Stop Mode the Watchdog can be disabled. In addition a feature is avai lable which will start the watchdog with any BUS wake (CAN) during SBC Stop Mode. The feature is enabled by setting the bit WD_EN_ WK_BUS = 1 (= default value after POR). The bit can only be chan ged in SBC Normal Mode and needs to be programmed before starting the watchdog disable sequence. A wake on CAN will generate an interrupt and the RX D pin for CAN is pulled to low. By these signals the microcontroller is informed that the watchdog is startedwith a long open window. After the long open window the watchdog has to be served as configured in the WD_CTRL register. To disable the watchdog again, the SBC needs to be switched to Normal Mode and the sequence needs to be sent again.

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14.3 VS Power On Reset

At power up of the device, the VS Power on Reset is detected when VS > VPOR,r and the SPI bit POR is set to indicate that all SPI registers are set to POR default setti ngs. VCC1 is starting up and the reset output will be kept LOW and will only be released once VCC1 has crossed VRT1,r and after tRD1 has elapsed. In case VS < VPOR,f, an device internal reset will be generated and the SBC is switched OFF and will restart in INIT mode at the next VS rising. This is shown in Figure 45. Figure 45 Ramp up / down example of Supply Voltage t VCC1 t VPOR,f RO t VS VPOR,r tRD1 VRT1,r VRTx,f t SBC Mode SBC OFF SBC OFFSBC INIT MODE Any SBC MODE SPI Command The reset threshold can be configured via SPI in SBC Normal Mode , default is VRT1 Re- start SBC Restart Mode is entered whenever the Reset is triggered

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14.4 Undervoltage VS and VSHS

If the supply voltage VS reaches the undervoltage threshold VS,UV then the SBC does the following measures:

SPI bit VS_UV is set. No other error bits are set. The bit can be cleared once the condition is not present anymore,
VCC3 is disabled (see Chapter 8.2) unless the control bit VCC3_VS_ UV_OFF is set
The VCC1 short circuit prot ection becomes inactive (see Chapter 14.7). However, the thermal protection of the device remains active. If the undervoltage threshold is exceeded (VS rising) then functions will be automatically enabled again. If the supply voltage VSHS passes below the undervoltage threshold ( VSHS,UVD) the SBC does the following measures:
HS1...4 are acting accordingly to the SPI setting (see Chapter 9)
see Chapter 13.2.7
S P I b i t VSHS_UV is set. No other error bits are set. The bit can be cleared once the condition is not present anymore,
VCC1, VCC2, WKx and CAN are no t affected by VSHS undervoltage

14.5 Overvoltage VSHS

If the supply voltage VSHS reac hes the overvoltage threshold ( VSHS,OVD) the SBC triggers the following measures:

HS1...4 are acting accordingly to the SPI setting (see Chapter 9)
SPI bit VSHS_OV is set. No other error bits are set. The bit can be cleared once the condition is not present anymore,
VCC1, VCC2, VCC3, WKx and CAN are not affected by VS overvoltage

14.6 VCC1 Over-/ Undervoltage and Undervoltage Prewarning

14.6.1 VCC1 Undervoltage and Undervoltage Prewarning

A first-level voltage detection threshold is implemented as a prewarning for the microcontroller. The prewarning event is signaled with the bit VCC1_ WARN. No other actions are taken. As described in Chapter 14.1 and Figure 46, a reset will be triggered (RO pulled ‘low’) when the VCC1 output voltage falls below the selected undervoltage threshold (V RTx). The bit VCC1_UV is set and the SBC will enter SBC Restart Mode. Note: The VCC1_ WARN or VCC1_UV bits are not set in Sleep Mode as VCC1 = 0V in this case

Datasheet 104 Rev. 1.1 2019-09-27 TLE9261BQXV33 Supervision Functions Figure 46 VCC1 Underv oltage Timing Diagram An additional safety mechanism is implemented to av oid repetitive VCC1 undervoltage resets due to high dynamic loads on VCC1:

A counter is increase d for every consecutive VCC1 undervoltage event (regardless on the selected reset threshold),
The counter is active in SBC In it-, Normal-, and Stop Mode,
F o r V S < VS,UV the counter will be stopped in SBC Normal Mode (i.e. the VS UV comparator is always enabled in SBC Normal Mode),
A 4th consecutive VCC1 undervoltage event will lead to SBC Fail-Safe Mode entry and to setting the bit VCC1_UV _FS
This counter is cleared: – when SBC Fail-Saf e Mode is entered, – when the bit VCC1_UV is cleared, – when a Soft Reset is triggered. Note: It is recommended to clear the VCC1_UV bit once it was set and detected.

14.6.2 VCC1 Overvoltage

For fail-safe reasons a configurable VCC1 overvoltage detection feature is implemented for SBC Init- and Normal Mode. In case the VCC1,OV,r threshold is crossed, the SBC triggers following measures depending on the configuration:

T h e b i t VCC1_ OV is always set;
I f t h e b i t VCC1_OV_RST is set and CFGP = ‘1’, then SBC Restart Mode is entered. The FOx outputs are activated. After the reset delay time (tRD1), the SBC Restart Mode is left and SBC Normal Mode is resumed even if the VCC1 overvoltage event is still present (see also Figure 47). The VCC1_OV_RST bit is cleared automatically;
I f t h e b i t VCC1_OV_RST is set and CFGP = ‘0’, then SBC Fail-Safe Mode is entered and FOx outputs are activated. Note: Before entering SBC Stop Mode the bit VCC1_OV_RST must be set to ‘0’ to avoid unintentional SBC Restart or Fail-Safe Mode entry. The status bit VCC1_ OV could be set unintentionally. The reason is RO t VCC1 VRTx tRD1 SBC Normal t tRF SBC Restart SBC Normal

Datasheet 105 Rev. 1.1 2019-09-27 TLE9261BQXV33 Supervision Functions that external noise could be coupled into the VCC1 supply line. Especially, in case the VCC1 output current in SBC STOP Mode is below the active peak threshold (IVCC1,Ipeak). Figure 47 VCC1 Overvoltage Timing Diagram

14.7 VCC1 Short Circuit and VCC3 Diagnostics

The short circuit protection feature for VCC1 is implemented as follows (VS needs to be higher than VS,UV):

If VCC1 is not above the V RTx within tVCC1,SC after device power up or after waking from SBC Sleep Mode then the SPI bit VCC1_SC bit is set, VCC1 is turned OFF, the FOx pins are enabled, FAILURE is set and SBC Fail- Safe Mode is entered. The SBC can be activated again via wake on CAN, WKx.
The same behavior applies, if VCC1 falls below VRTx for longer than tVCC1,SC. VCC3 diagnosis features are implemented as follows:
Load Sharing: The external PNP is disabled when VS < VS,UV if VCC3_VS_ UV_OFF = 0 or when in SBC Stop Mode if VCC3_LS_ STP_ON = ‘0’. All other diagnostic features are disabled because they are provided via VCC1.
Stand-alone configuration: The external PNP is disabled when VCC3 < VS,UV if VCC3_VS_ UV_OFF = 0. The overcurrent limitation is signalled via the bit VCC3_OC according to the selected shunt resistor, VCC3 undervoltage is signalled via the bit VCC3_UV and the regulator is disabled due to VS undervoltage when VS,UV is reached. Note: Neither VCC1_SC nor VCC3_UV flags are set during power up of VCC1 or turn on of VCC3 respectively.

14.8 VCC2 Undervoltage and VCAN Undervoltage

An undervoltage warning is implemented for VCC2 and VCAN as follows:

VCC2 undervoltage Detection: In case VCC2 will drop below the VCC2,UV,f threshold, then the SPI bit VCC2_UV is set and can be only cleared via SPI.
VCAN undervoltage Detection: In case the voltage on VCAN will drop below the VCAN_UV threshold, then the SPI bit VCAN_UV is set and can be only cleared via SPI. Note: The VCC2_UV flag is not set during turn-on or turn-off of V CC2. RO t VCC1 tRD1 SBC Normal t tVCC1,OV_F SBC Restart SBC Normal VCC1,OV

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14.9 Thermal Protection

Three independent and different ther mal protection features are implem ented in the SBC according to the system impact:

Individual thermal shutdown of specific blocks
Temperature prewarning of main microcontroller supply VCC1
SBC thermal shutdown due to VCC1 overtemperature

14.9.1 Individual Thermal Shutdown

As a first-level protection measure the output stages VCC2, CAN, and HSx are in dependently switched OFF if the respective block reaches the temperature threshold T jTSD1. Then the TSD1 bit is set. This bit can only be cleared via SPI once the overtemperature is not present anymore. Independent of the SBC Mode the thermal shutdown protection is only active if the respective block is ON. The respective modules behave as follows:

VCC2: Is switched to OFF and the control bits VCC2_ON are cleared. The status bit VCC2_OT is set. Once the overtemperature condition is not present anymore, then VCC2 has to be configured again by SPI.
VCC3 as a stand-alone regulator : Is switched to OFF and the control bits VCC3_ON are cleared. The status bit VCC3_OT is set. Once the overtemperature condition is not present anymore VCC3 has to be configured again by SPI. It is recommended to clear the VCC3_OT bit before enabling the regulator again.
VCC3 in load sharing configuration: in case of overtemperature at VCC3 the bit VCC3_OT is set and VCC3 is switched off. The regulator will be switched on again automatically once the overtemperature event is not present anymore. Also in this case it is recommended to clear the VCC3_OT bit right away.
CAN: The transmitter is disabled and stays in CAN No rmal Mode acting like CAN Receive only mode. The status bits CAN_FAIL = ‘01’ are set. Once the overtemperature condition is not present anymore, then the CAN transmitter is automatically switched on.
HSx: If one or more HSx switches reach the TSD1 threshold, then all HSx switches are turned OFF and the control bits for HSx are cleared (see registers HS_CTRL1 and HS_CTRL2). The status bits HSx_OC_OT are set (see register HS_OC_OT_STAT). Once the overtemperature condition is not present anymore, then HSx has to be configured again by SPI. Note: The diagnosis bits are not cleared automatically and have to be cleared via SPI once the overtemperature condition is not present anymore.

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14.9.2 Temperature Prewarning

As a next level of thermal protection a temperature prewarning is implemented if the main supply VCC1 reaches the thermal prewarning temperature threshold TjPW. Then the status bit TPW is set. This bit can only be cleared via SPI once the overtemperature is not present anymore. Independent of the SBC Mode the thermal prewarning is only active if the VCC1 is ON.

14.9.3 SBC Thermal Shutdown

As a highest level of thermal protection a temperature shutdown of the SBC is implemented if the main supply VCC1 reaches the thermal shutdown temperature threshold TjTSD2. Once a TSD2 event is detected SBC Fail- Safe Mode is entered for tTSD2 to allow the device to cool down. Af ter this time has expired, the SBC will automatically change via SBC Restart Mode to SBC Normal Mode (see also Chapter 5.1.6). When a TSD2 event is detected, then the status bit TSD2 is set. This bit can only be cleared via SPI in SBC Normal Mode once the overtemperat ure is not present anymore. Indepe ndent of the SBC Mode the thermal shutdown is only active if VCC1 is ON.

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14.10 Electrical Characteristics

Table 26 Electrical Specification VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. VCC1 Monitoring; VCC1 = 3.3V Version Undervoltage Prewarning Threshold Voltage PW,f 3.3V option V PW,f 3.0 3.1 3.2 V VCC1 falling, SPI bit is set P_15.10.36 Undervoltage Prewarning Threshold Voltage PW,r 3.3V option Reset Threshold Voltage RT1,f 3.3V option VRT1,f 2.95 3.05 3.15 V default setting; VCC1 falling P_15.10.37 Reset Threshold Voltage RT1,r 3.3V option V RT1,r 3.0 3.1 3.2 V default setting; VCC1 rising P_15.10.38 Reset Threshold Voltage RT2,f 3.3V option Reset Threshold Voltage RT2,r 3.3V option Reset Threshold Voltage RT3,f 3.3V option V RT3,f 2.2 2.3 2.4 V SPI option; VS ≥ 4V; VCC1 falling P_15.10.41 Reset Threshold Voltage RT3,r 3.3V option VRT3,r 2.25 2.35 2.45 V VS ≥ 4V; VCC1 rising P_15.10.42 Reset Threshold Voltage RT4,f 3.3V option V RT4,f 2.0 2.1 2.2 V VS ≥ 4V; VCC1 falling P_15.10.43 Reset Threshold Voltage RT4,r 3.3V option, VRT4,r 2.05 2.15 2.25 V VS ≥ 4V; VCC1 rising, P_15.10.44 Reset Threshold Hysteresis 3.3V option VRT,hys 30 67 140 mV – P_15.10.45 VCC1 Overvoltage Detection Threshold Voltage 3.3V option VCC1,OV,r 3.5 – 3.7 V rising VCC1 P_15.10.70

Datasheet 109 Rev. 1.1 2019-09-27 TLE9261BQXV33 Supervision Functions VCC1 Overvoltage Detection Threshold Voltage 3.3V option VCC1,OV,f 3.40 – 3.60 V falling VCC1 P_15.10.73 VCC1 OV Detection Filter Time tVCC1,OV_F 51 0 1 4 u s 2) P_15.10.51 VCC1 Short to GND Filter Time tVCC1,SC 3.2 4 4.8 ms 2) P_15.10.12 Reset Generator; Pin RO Reset Low Output Voltage VRO,L –0 . 2 0 . 4 V IRO = 1 mA for VCC1 ≥ 1 V & VS ≥VPOR,f P_15.10.14 Reset High Output Voltage VRO,H 0.8 x VCC1 – VCC1 + 0.3 V V IRO = -20 µA P_15.10.15 Reset Pull-up Resistor RRO 10 20 40 k Ω VRO = 0 V P_15.10.16 Reset Filter Time tRF 41 0 2 6 µ s 2)VCC1 < VRT1x to RO = L see also Chapter 14.3 P_15.10.17 Reset Delay Time tRD1 1.5 2 2.5 ms 1) 2) P_15.10.18 VCC2 Monitoring VCC2 Undervoltage Threshold Voltage (falling) VCC2,UV,f 4.5 – 4.75 V VCC2 falling P_15.10.19 VCC2 Undervoltage Threshold Voltage (rising) VCC2,UV,r 4.6 – 4.9 V VCC2 rising P_15.10.77 VCC2 Undervoltage detection hysteresis VCC2,UV, hys 20 100 250 mV – P_15.10.20 VCC3 Monitoring VCC3 Undervoltage Detection VCC3,UV 2.65 2.85 3.00 V 3.3V option or VCC3_ V_CFG=0 hysteresis included P_15.10.47 VCC3 Undervoltage Detection VCC3,UV 1.45 1.52 1.65 V VCC3_ V_CFG=1 hysteresis included P_15.10.61 VCC3 Undervoltage detection hysteresis V CC3,UV, hys 20 100 250 mV – P_15.10.22 Table 26 Electrical Specification (cont’d) VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 110 Rev. 1.1 2019-09-27 TLE9261BQXV33 Supervision Functions VCAN Monitoring CAN Supply undervoltage detection threshold VCAN_UV 4.45 – 4.85 V CAN Normal Mode, hysteresis included; P_15.10.23 Watchdog Generator Long Open Window tLW 160 200 240 ms 2) P_15.10.24 Minimum Waiting time during SBC Fail-Safe Mode Min. waiting time Fail-Safe tFS,min 80 100 120 ms 2)3) P_15.10.75 Power-on Reset, Over- / Undervoltage Protection VS Power on reset rising VPOR,r – 4.5 V VS increasing P_15.10.26 VS Power on reset falling VPOR,f – 3 V VS decreasing P_15.10.27 VS Undervoltage Detection Threshold 3.3V option VS,UV 3.7 – 4.4 V Supply UV threshold for VCC3 and VCC1 SC detection; hysteresis included P_25.10.46 VSHS Overvoltage Detection Threshold V SHS,OVD 20 22 V Supply OV supervision for HSx; hysteresis included P_15.10.28 VSHS Overvoltage Detection hysteresis V SHS,OVD,hys 100 500 – mV 4) P_15.10.29 VSHS Undervoltage Detection Threshold VSHS,UVD 4.8 5.5 V Supply UV supervision for HSx, and HS of GPIOx; hysteresis included P_15.10.30 VSHS Undervoltage Detection hysteresis V SHS,UVD,hys 50 200 350 mV 4) P_15.10.31 Overtemperature Shutdown4) Thermal Prewarning Temperature TjPW 125 145 165 °C P_15.10.32 Thermal Shutdown TSD1 TjTSD1 165 185 200 °C P_15.10.33 Table 26 Electrical Specification (cont’d) VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 111 Rev. 1.1 2019-09-27 TLE9261BQXV33 Supervision Functions Thermal Shutdown TSD2 TjTSD2 165 185 200 °C P_15.10.34 Thermal Shutdown hysteresis TjTSD,hys 5 15 25 °C P_15.10.68 Deactivation time after thermal shutdown TSD2 tTSD2 0.8 1 1.2 s 2) P_15.10.35 1) The reset delay time will start when VCC1 crosses above the selected Vrtx threshold 2) Not subject to production test, tolerance defined by internal oscillator tolerance. 3) This time applies for all failure en tries except a device thermal shutdown (TSD2 has a typ. 1s waiting time tTSD2) 4) Not subject to production test, specified by design. Table 26 Electrical Specification (cont’d) VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

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15 Serial Peripheral Interface

15.1 SPI Block Description

The 16-bit wide Control Input Word is read via the data input SDI, which is synchronized with the clock input CLK provided by the microcontroller. The output word appears synchron ously at the data output SDO (see Figure 48). The transmission cycle begins when the chip is selected by the input CSN (Chip Select Not), LOW active. After the CSN input returns from LOW to HIGH, the word that has been read is interpreted according to the content. The SDO output switches to tristate status (high impeda nce) at this point, thereby releasing the SDO bus for other use.The state of SDI is shifted into the input regist er with every falling edge on CLK. The state of SDO is shifted out of the output register after every rising edge on CLK. The SPI of the SBC is not daisy chain capable. Figure 48 SPI Data Transfer Timing (note the re versed order of LSB and MSB shown in this figure compared to the register description) 0 0 +1 2 3 4 5 6 7 8 9 10 15 1 0 1 2 3 4 5 6 11 12 13 147 8 9 10 15 CSN high to low: SDO is enabled. Status information transferred to output shift register CSN low to high: data from shift register is transferred to output functions SDI: will accept data on the falling edge of CLK signal SDO: will change state on the rising edge of CLK signal Actual status 11 12 13 14 Actual data New data New status SDO SDI CSN CLK time time time time ERRERR - 0

Datasheet 113 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface

15.2 Failure Signalization in the SPI Data Output

When the microcontroller sends a wr ong SPI command to the SBC, the SB C ignores the information. Wrong SPI commands are either invalid SBC mode command s or commands which are pr ohibited by the state machine to avoid undesired device or system states (see below). In this case the diagnosis bit ‘SPI_FAIL’ is set and the SPI Write command is ignored (mostly no partial interpretation). This bit can be only reset by actively clearing it via a SPI command. Invalid SPI Commands leading to SPI_FAIL are listed below:

Illegal state transitions: Going from SBC Stop to SBC Sl eep Mode. In this case the SBC enters in addition the SBC Restart Mode; Trying to go to SBC Stop or SBC Sleep mode from SBC Init Mode. In this case SBC Normal Mode is entered;
Uneven parity in the data bit of the WD_CTRL register. In this case the watchdog trigger is ignored or the new watchdog settings are ignored respectively;
In SBC Stop Mode: attempting to ch ange any SPI settings, e.g. changing the watchdog configuration, PWM settings and HS configuration settings during SBC Stop Mode, etc.; the SPI command is ignored in this case; only WD trigger, returning to Normal Mode, triggering a SBC Soft Reset, and Read & Clear status registers commands are valid SPI commands in SBC Stop Mode;
When entering SBC Stop Mode and WK_STAT_1 and WK_STAT_2 are not cleared; SPI_FAIL will not be set but the INT pin will be triggered;
Changing from SBC Stop to Normal Mode and changing the other bits of the M_S_CTRL register. The other modifications will be ignored;
SBC Sleep Mode: attempt to go to Sleep Mode when all bits in the BUS_CTRL_1 and WK_CTRL_2 registers are cleared. In this case the SPI_FAIL bit is set and the SBC enters Restart Mode. Even though the Sleep Mode command is not entered in this case, the rest of the command (e.g modifying VCC2 or VCC3) is executed and the values stay unchanged during SBC Restart Mode; Note: At least one wake source must be activated in order to avoid a deadlock situation in SBC Sleep Mode, i.e. the SBC would not be able to wake up anymore. If the only wake source is a timer and the timer is OFF then the SBC will wake immediately from Sleep Mode and enter Restart Mode; No failure handling is done for the attempt to go to SBC STOP Mode when all bits in the registers BUS_CTRL_1 and WK_CTRL_2 are cleared because the microcontroller can leave this mode via SPI;
If VCC3 load sharing VCC3_LS is enabled and the microcontroller tries to clear the bit, then the rest of the command executed but VCC3_LS will remain set;
Attempt to enter SBC Sleep Mode if WK_MEAS is set to ‘1’ and only WK1_EN or WK2_EN are set as wake sources. Also in this case the SPI_FAIL bit is set and the SBC enters Restart Mode;
Setting a longer or equal on-time than the timer period of the respective timer;
SDI stuck at HIGH or LOW, e.g. SDI received all ‘0’ or all ‘1’; Note: There is no SPI fail in formation for unused addresses. Signalization of the ERR Flag (high active) in the SPI Data Output (see Figure 48): The ERR flag presents an additional diagnosis possibility for the SPI communication. The ERR flag is being set for following conditions:
in case the number of receiv ed SPI clocks is not 0 or 16,
in case RO is LOW and SPI frames are being sent at the same time.

Datasheet 114 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface Note: In order to read the SPI ERR flag properly, CLK must be low when CSN is triggered, i.e. the ERR bit is not valid if the CLK is high on a falling edge of CSN The number of received SPI clocks is not 0 or 16: The number of received input clocks is supervised to be 0- or 16 clock cycles and the input word is discarded in case of a mismatch (0 clock cycle to enable ERR signalization). The error logic also recognizes if CLK was high during CSN edges. Both errors - 0 bit and 16 bit CLK mismatch or CLK high during CSN edges - are flagged in the following SPI output by a “HIGH” at the data output (SDO pin, bit ERR) before th e first rising edge of the clock is received. The complete SPI command is ignored in this case. RO is LOW and SPI frames are being sent at the same time: The ERR flag will be set when the RO pin is triggered (during SBC Restart) and SPI frames are being sent to the SBC at the same time. The behavior of the ERR flag wi ll be signalized at the next SPI command for below conditions:

if the command begins when RO is HIGH and it ends when RO is LOW,
if a SPI command will be sent while RO is LOW,
If a SPI command begins when RO is LOW and it ends when RO is HIGH. and the SDO output will behave as follows:
always when RO is LOW then SDO will be HIGH,
when a SPI command begins with RO is LOW and ends when RO is HIGH, then the SDO should be ignored because wrong data will be sent. Note: It is possible to quickly check fo r the ERR flag without sending any data bits. i.e. only the CSN is pulled low and SDO is observed - no SPI Clocks are sent in this case Note: The ERR flag could also be set after the SB C has entered SBC Fail-Safe Mode because the SPI communication is stopped immediately.

Datasheet 115 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface

15.3 SPI Programming

For the TLE9261BQXV33, 7 bits are used or the address selection (BIT6...0). Bit 7 is used to decide between Read Only and Read & Clear for the status bits, and be tween Write and Read Only for configuration bits. For the actual configuration and status information, 8 data bits (BIT15...8) are used. Writing, clearing and reading is done byte wise. The SPI status bits are not cleared automatically and must be cleared by the microcontroller, e.g. if the TSD2 was set due to overtemperature. The configuration bits will be partially automatically clea red by the SBC - please refer to the in dividual registers description for detailed information. During SBC Restart Mode the SPI communication is ignored by the SBC, i.e. it is not interpreted. There are two types of SPI registers:

Control registers: Those are the registers to config ure the SBC, e.g. SBC mode, watchdog trigger, etc
Status registers: Those are the regi sters where the status of the SBC is signalled, e.g. wake events, warnings, failures, etc. For the status registers, the requested information is given in the same SPI command in DO. For the control registers, also the status of the respective byte is shown in the same SPI command. However, if the setting is changed this is only shown with the next SPI command (it is only valid afte r CSN high) of the same register. The SBC status information from the SPI status register s, is transmitted in a comp ressed way with each SPI response on SDO in the so called Status Information Field register (see also Figure 49). The purpose of this register is to quickly signal the information to the microcontroller if there was a change in one of the SPI status registers. In this way, the microcontroller does not need to read constantly all the SPI status registers but only those registers, which were changed. Each bit in the Status Information Field represents a SPI status register (see Table 27). As soon as one bit is set in one of the status registers, then the respective bit in the Status Information Field register will be set. The register WK_LVL_STAT is not included in the status Information field. This is listed in Table 27. For Example if bit 0 in the Status Information Field is set to 1, one or more bits of the register 100 0001 (SUP_STAT_1) is set to 1. Then this register needs to be read in a second SPI command. The bit in the Status Information Field will be set to 0 when all bits in the register 100 0001 are set back to 0. Table 27 Status Information Field Bit in Status Information Field Corresponding Address Bit Status Register Description 0 100 0001 SUP_STAT_1: Supply Status -VSHS fail, VCCx fail, POR 1 100 0010 THERM_STAT: Thermal Protection Status 2 100 0011 DEV_STAT: Device Status - Mode before Wake, WD Fail, SPI Fail, Failure 3 100 0100 BUS_STAT: Bus Fa ilure Status: CAN; 4 100 0110 WK_STAT_1, WK_STAT_2: Wake Source Status; Status bit is set as combinational OR of both registers 5 100 0000 SUP_STAT_2: VCC1_WARN/OV, VCC3 Status 6 101 0100 HS_OC_OT_STAT: High-Side Over Load Status 7 101 0101 HS_OL_STAT: High-Side Open Load Status

Datasheet 116 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface Figure 49 SPI Operation Mode 0 1 2 3 4 5 76 8 9 10 11 12 13 1514 Data Bits DI Address Bits x x x x x x xx R/W 0 1 2 3 4 5 76 8 9 10 11 12 13 1514 Data Bits DO Status Information Field x x x x x x xx Register content of selected address LSB MSB time LSB is sent first in SPI message

Datasheet 117 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface

15.4 SPI Bit Mapping

The following figures show the mapping of the registers and the SPI bits of the respective registers. The Control Registers ‘000 0000’ to ‘001 1110’ are Read/Write Register. Depending on bit 7 the bits are only read (setting bit 7 to ‘0’) or also written (setting bit 7 to ‘1’). The new setting of the bit after write can be seen with a new read / write command. The registers ‘100 0000’ to ‘111 1110’ are Status Registers and can be read or read with clearing the bit (if possible) depending on bit 7. To clear a Data Byte of on e of the Status Registers bit 7 must be set to 1. The registers WK_LVL_STAT, and FAM_PROD_STAT are an exception as they show the actual voltage level at the respective WK pin (LOW/HIGH), or a fixed family/ produc t ID respectively and can th us not be cleared. It is recommended for proper diagnosis to clear respective status bits for wake events or failure. However, in general it is possible to enable drivers without clearing the respective failure flags. When changing to a different SBC Mode, certain configurations bits will be cleared automatically or modified:

The SBC Mode bits are updated to the actual status, e.g. when returning to Normal Mode
When changing to a low-power mode (Stop/Sleep), the diagnosis bits of the switches and transceivers are not cleared. FOx will stay activated if it was triggered before.
When changing to SBC Stop Mode, the CA N control bits will not be modified.
When changing to SBC Sleep Mode, th e CAN control bits will be modified if they were not OFF or wake capable before.
HSx, VCC2 and VCC3 will stay on when going to Sleep -/Stop Mode (configuration can only be done in Normal Mode). Diagnosis is active (OC, OL, OT). In case of a failure the switch is turned off and no wake-up is issued
The configuration bits for HSx and VCC2 in stand-al one configuration are cleared in SBC Restart Mode. FOx will stay activated if it was triggered before. Depending on the respective configuration, CAN transceivers will be either OFF, woken or still wake capable. Note: The detailed behavior of the respective SPI bits and control functions is described in Chapter 15.5, Chapter 15.6.and in the respective module chapter. The bit type be marked as ‘rwh’ in case the SBC will modify respective control bits.

Datasheet 118 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface Figure 50 SPI Register Mapping 0 0 0 0 1 0 1BUS_CTRL_2 rw 1 0 0 0 1 1 1WK_STAT_2 rc 4 0 0 1 0 1 1 1GPIO_CTRL rw 15 14 13 12 11 10 89 7 6 5 4 3 2 01 7 Address Bits [bits 0...6] for Register Selection 8 Data Bits [bits 8...15] for Configuration & Status Information LSBMSB 0 0 0 0 0 0 1M_S_CTRL Reg. Type rw 0 0 0 0 0 1 0rwHW_CTRL 0 0 0 0 0 1 1WD_CTRL rw 0 0 0 0 1 0 0BUS_CTRL_1 rw 0 0 0 0 1 1 0WK_CTRL_1 rw 0 0 0 1 0 0 0WK_PUPD_CTRL rw 0 0 0 1 0 0 1WK_FLT_CTRL rw 0 0 0 1 1 0 0TIMER1_CTRL rw 0 0 1 0 0 0 0SW_SD_CTRL rw 0 0 1 0 1 0 0HS_CTRL_1 rw 0 0 1 0 1 0 1HS_CTRL_2 rw 0 0 1 1 0 0 0PWM1_CTRL rw 0 0 1 1 0 0 1PWM2_CTRL rw 1 0 0 0 0 0 1SUP_STAT_1 rc 1 0 0 0 0 1 0THERM_STAT rc 1 0 0 0 0 1 1DEV_STAT rc 1 0 0 0 1 0 0BUS_STAT_1 rc 1 0 0 0 1 1 0WK_STAT_1 rc 1 0 0 1 0 0 0WK_LVL_STAT r 1 0 1 0 1 0 0HS_OC_OT_STAT rc 1 0 1 0 1 0 1HS_OL_STAT rc 0 0 0 1 1 0 1TIMER2_CTRL rw 0 0 0 0 1 1 1WK_CTRL_2 rw 0 0 1 1 1 0 0PWM_FREQ_CTRL rw 1 1 1 1 1 1 0FAM_PROD_STAT r 0 0 1 1 1 1 0SYS_STAT_CTRL rw 1 0 0 0 0 0 0SUP_STAT_2 rc Status Registers Status Information Field Bit Control Registers

Datasheet 119 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface Figure 51 TLE9261BQXV33 SPI Bit Mapping 15 14 13 12 11 10 9 8 7 6...0 Data Bit 15…8 D7 D6 D5 D4 D3 D2 D1 D0 M_S_CTRL MODE_1 MODE_0 VCC3_ON VCC2_ON_1 VCC2_ON_0 V CC1_OV_RST VCC1_RT_1 VCC1_RT_0 read/write 0000001 HW_CTRL VCC3_V_CFG SOFT_RESET_RO FO_ON VCC3_VS_UV_OFF VCC3_LS reserved VCC3_LS_STP_ON CFG read/write 0000010 WD_CTRL CHECKSUM WD_STM_EN_0 WD_WIN WD_EN_WK_BUS reserved WD_TIMER_2 WD_TIMER_1 WD_TIMER_0 read/write 0000011 BUS_CTRL_1 reserved reserved reserved reserved reserved reserved CAN_1 CAN_0 read/write 0000100 BUS_CTRL_2 reserved reserved I_PEAK_TH reserved reserved reserved reserved reserved read/write 0000101 WK_CTRL_1 TIMER2_WK_EN TIMER1_WK_EN reserved reserved reserved WD_STM_EN_1 reserved reserved read/write 0000110 WK_CTRL_2 INT_GLOBAL reserved WK_MEAS reserved reserved WK3_EN WK2_EN WK1_EN read/write 0000111 WK_PUPD_CTRL reserved reserved WK3_PUPD_1 WK3_PUPD_0 WK2_PUPD_1 WK2_PUPD_0 WK1_PUPD_1 WK1_PUPD_0 read/write 0001000 WK_FLT_CTRL reserved reserved WK3_FLT_1 WK3_FLT_0 WK2_FLT_1 WK2_FLT_0 WK1_FLT_1 WK1_FLT_0 read/write 0001001 TIMER1_CTRL reserved TIMER1_ON_2 TIMER1_ON_1 TIMER1_ON_0 reserved TIMER1_PER_2 TIMER1_PER_1 TIMER1_PER_0 read/write 0001100 TIMER2_CTRL reserved TIMER2_ON_2 TIMER2_ON_1 TIMER2_ON_0 reserved TIMER2_PER_2 TIMER2_PER_1 TIMER2_PER_0 read/write 0001101 SW_SD_CTRL reserved HS_OV_SD_EN HS_UV _SD_EN HS_OV_UV_REC reserved reserved reserved reserved read/write 0010000 HS_CTRL_1 reserved HS2_2 HS2_1 HS2_0 reserved HS1_2 HS1_1 HS1_0 read/write 0010100 HS_CTRL_2 reserved HS4_2 HS4_1 HS4_0 reserved HS3_2 HS3_1 HS3_0 read/write 0010101 GPIO_CTRL FO_DC_1 FO_DC_0 GPIO2_2 GPIO2_1 GPIO2_0 GPI O1_2 GPIO1_1 GPIO1_0 read/write 0010111 PWM1_CTRL PWM1_DC_7 PWM1_DC_6 PWM1_DC_5 PWM1_DC_4 PWM1_DC_3 PWM1_DC_2 PWM1_DC_1 PWM1_DC_0 read/write 0011000 PWM2_CTRL PWM2_DC_7 PWM2_DC_6 PWM2_DC_5 PWM2_DC_4 PWM2_DC_3 PWM2_DC_2 PWM2_DC_1 PWM2_DC_0 read/write 0011001 PWM_FREQ_CTRL reserved reserved reserved reserved reserved PWM2_FREQ_0 reserved PWM1_FREQ_0 read/write 0011100 SYS_STAT_CTRL SYS_STAT_7 SYS_STAT_6 SYS_STAT_5 SYS_STAT_4 SYS_ST AT_3 SYS_STAT_2 SYS_STAT_1 SYS_STAT_0 read/write 0011110 SUP_STAT_2 reserved VS_UV reserved VCC3_OC VCC3_UV VCC3_OT VCC1_OV VCC1_WARN read/clear 1000000 SUP_STAT_1 POR VSHS_UV VSHS_OV VCC2_OT VCC2_UV VCC1_SC VCC1_UV_FS VCC1_UV read/clear 1000001 THERM_STAT reserved reserved reserved reserved reserved TSD2 TSD1 TPW read/clear 1000010 DEV_STAT DEV_STAT_1 DEV_STAT_0 reserved reserved WD_FAIL_1 WD_FAIL_0 SPI_FAIL FAILURE read/clear 1000011 BUS_STAT_1 reserved reserved reserved reserved reserved CAN_FAIL_1 CAN_FAIL_0 VCAN_UV read/clear 1000100 WK_STAT_1 reserved reserved CAN_WU TIMER_WU reserved WK3_WU WK2_WU WK1_WU read/clear 1000110 WK_STAT_2 reserved reserved GPIO2_WU GPIO1_WU reserved reserved reserved reserved read/clear 1000111 WK_LVL_STAT SBC_DEV_LVL CFGP GPIO2_LVL GPIO1_LVL reserved WK3_LVL WK2_LVL WK1_LVL read 1001000 HS_OC_OT_STAT reserved reserved reserved reserved HS4_OC_OT HS3_OC_OT HS2_O C_OT HS1_OC_OT read/clear 1010100 HS_OL_STAT reserved reserved HS4_OL HS3_OL HS2_OL HS1_OL read/clear 1010101 FAM_PROD_STAT FAM_3 FAM_2 FAM_1 FAM_0 PROD_3 PROD_2 PROD_1 PROD_0 read 1111110 F A M I LY A N D P R O D U C T R E G I S T E R S Register Short Name Access Mode Address A6…A0 C O N T R O L R E G I S T E R S S T A T U S R E G I S T E R S

Datasheet 120 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface

15.5 SPI Control Registers

READ/WRITE Operation (see also Chapter 15.3):

The ‘POR / Soft Reset Value’ defines the register content after POR or SBC Reset.
The ‘Restart Value’ defines the register content after SBC Restart, where ‘x’ means the bit is unchanged.
One 16-bit SPI command consist of two bytes: - the 7-bit address and one additional bit for the register access mode and - following the data byte The numbering of following bit definitions refers to the data byte and correspond to the bits D0...D7 and to the SPI bits 8...15 (see also figure before).
There are three different bit types: - ‘r’ = READ: read only bits (or reserved bits) - ‘rw’ = READ/WRITE: readable and writable bits - ‘rwh’ = READ/WRITE/Hardware: readable/writable bits, which can also be modified by the SBC hardware
Reserved bits are marked as “Reserved” and always read as “0”. The respective bits shall also be programmed as “0”.
Reading a register is done byte wise by setting the SPI bit 7 to “0” (= Read Only).
Writing to a register is done byte wise by setting the SPI bit 7 to “1”.
SPI control bits are in general not cleared or ch anged automatically. This must be done by the microcontroller via SPI programming. Exceptions to this behavior are stated at the respective register description and the respective bit type is marked with a ‘h’ meaning that the SBC is able to change the register content. The registers are addressed wordwise.

Datasheet 121 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface

15.5.1 General Control Registers

It is not possible to change from Stop to Sleep Mo de via SPI Command. See also the State Machine Chapter 2. After entering SBC Restart Mode, the MODE bits will be automatically set to SBC Normal Mode. The VCC2_ON bits will be automatically set to OFF after entering SBC Restart Mode and after OT. 3. The SPI output will always show the previously written state with a Write Command (what has been programmed before) M_S_CTRL Mode- and Supply Control (Address 000 0001B) POR / Soft Reset Value: 0000 0000B; Restart Value: 00x0 00xx B 76543210 MODE_1 MODE_0 VCC3_ON VCC2_ON_1 VCC2_ON_0 VCC1_OV_RS T VCC1_RT_1 VCC1_RT_0 r rwh rwh rwh rwh rwh rwh rw rw Field Bits Type Description MODE 7:6 rwh SBC Mode Control 00B , SBC Normal Mode 01B , SBC Sleep Mode 10B , SBC Stop Mode 11B , SBC Reset: Soft Reset is ex ecuted (configuration of RO triggering in bit SOFT_ RESET_RO) VCC3_ON 5r w h VCC3 Mode Control 0B , VCC3 OFF 1B , VCC3 is enabled (as independent voltage regulator) VCC2_ON 4:3 rwh VCC2 Mode Control 00B , VCC2 off 01B , VCC2 on in Normal Mode 10B , VCC2 on in Normal and Stop Mode 11B , VCC2 always on (except in SBC Fail-Safe Mode) VCC1_OV_R ST 2r w h VCC1 Overvoltage leading to Restart / Fail-Safe Mode enable 0B , VCC1_ OV is set in case of VCC1_OV; no SBC Restart or Fail- Safe is entered for VCC1_OV 1B , VCC1_ OV is set in case of VCC1_OV; depending on the device configuration SBC Restart or SBC Fail-Safe Mode is entered (see Chapter 5.1.1); VCC1_RT 1:0 rw VCC1 Reset Threshold Control 00B , Vrt1 selected (highest threshold) 01B , Vrt2 selected 10B , Vrt3 selected 11B , Vrt4 selected

Datasheet 122 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface Notes 1. Clearing the FO_ON bit will not disable the FOx outputs for the case a failure occurred which triggered the FOx outputs. In this case the FOx outputs have to be disabled by clearing the FAILURE bit. HW_CTRL Mode- and Supply Control (Address 000 0010B) POR / Soft Reset Value: y000 y000B; Restart Value: xx0x x00x B 76543210 VCC3_V_CFG SOFT_RESET _RO FO_ON VCC3_VS_UV _OFF VCC3_LS Reserved VCC3_LS_ST P_ON CFG r rw rw rwh rw rw r rw rw Field Bits Type Description VCC3_ V_CFG 7r w VCC3 Output Voltage Configuration (if configured as independent voltage regulator) 0B , VCC3 has same output voltage as VCC1 1B , VCC3 is configured to either 3.3V or 1.8V (depending on VCC1 derivative) SOFT_ RESET_RO 6r w Soft Reset Configuration 0B , RO will be triggered (pulled low) during a Soft Reset 1B , No RO triggering during a Soft Reset FO_ON 5r w h Failure Output Activation (FO1..3) 0B , FOx not activated by softwa re, FO can be activated by defined failures (see Chapter 13) 1B , FOx activated by software (via SPI) VCC3_VS_ UV_OFF 4r w VCC3 VS_UV shutdown configuration 0B , VCC3 will be disabled automatically at VS_UV 1B , VCC3 will stay enabled even below VS_UV VCC3_LS 3r w VCC3 Configuration 0B , VCC3 operating as a stand-alone regulator 1B , VCC3 in load sharing operation with VCC1 Reserved 2r Reserved, always reads as 0 VCC3_LS_ STP_ON 1r w VCC3 Load Sharing in SBC Stop Mode configuration 0B , VCC3 in LS configuration du ring SBC Stop Mode and high- power mode: disabled 1B , VCC3 in LS configuration du ring SBC Stop Mode and high- power mode: enabled CFG 0r w Configuration Select (see also Table 5) 0B , Depending on hardware config uration, SBC Restart or Fail- Safe Mode is reached after the 2. watchdog trigger failure (=default) - Config 3/4 1B , Depending on hardware config uration, SBC Restart or Fail- Safe Mode is reached after the 1. watchdog trigger failure - Config 1/2

Datasheet 123 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface If the FO_ON bit is set by the software then it will be cleared by the SBC after SBC Restart Mode was entered and the FOx outputs will be disabled. See also Chapter 13 for FOx activation and deactivation. 2. After triggering a SBC Soft Reset the bits VCC3_V_CFG an d VCC3_LS are not reset if they were set before, i.e. it stays unchanged, which is stated by the ‘y’ in the POR / Soft Reset Value. POR value: 0000 0000 and Soft Reset value: xx00 x00x 3. VCC3_LS_STP_ON: Is a combination of load sharing and VCC1 active peak in Stop mode

Datasheet 124 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface Notes 1. See also Chapter 14.2.4 for more information on disabling the watchdog in SBC Stop Mode. 2. See Chapter 14.2.5 for more information on the effect of the bit WD_EN_WK_BUS. 3. See Chapter 14.2.3 for calculation of checksum. WD_CTRL Watchdog Control (Address 000 0011B) POR / Soft Reset Value: 0001 0100B; Restart Value: x0xx 0100 B 76543210 CHECKSUM WD_STM_ EN_0 WD_WIN WD_EN_ WK_BUS Reserved WD_TIMER_2 WD_TIMER_1 WD_TIMER_0 r rw rwh rw rw r rwh rwh rwh Field Bits Type Description CHECKSUM 7r w Watchdog Setting Check Sum Bit The sum of bits 7:0 needs to have even parity (see Chapter 14.2.3) 0B , Counts as 0 for checksum calculation 1B , Counts as 1 for checksum calculation WD_STM_ EN_0 6r w h Watchdog Deactivation during Stop Mode, bit 0 (Chapter 14.2.4) 0B , Watchdog is active in Stop Mode 1B , Watchdog is deactivated in Stop Mode WD_WIN 5r w Watchdog Type Selection 0B , Watchdog works as a Time-Out watchdog 1B , Watchdog works as a Window watchdog WD_EN_ WK_BUS 4r w Watchdog Enable after Bus (CAN) Wake in SBC Stop Mode 0B , Watchdog will not start after a CAN wake 1B , Watchdog starts with a long open window after CAN Wake Reserved 3r Reserved, always reads as 0 WD_TIMER 2:0 rwh Watchdog Timer Period 000B , 10ms 001B , 20ms 010B , 50ms 011B , 100ms 100B , 200ms 101B , 500ms 110B , 1000ms 111B , reserved

Datasheet 125 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface Notes 1. The reset values for the CAN transceivers are marked with ‘y’ because they will vary depending on the cause of change - see below. 2. see Figure 26 for detailed state changes of CAN Transceiver for different SBC modes. 3. Failure Handling Mechanism: When the device enters Fa il-Safe Mode due to a failure (TSD2, WD-Failure,...), then the wake registers BUS_CTRL_1 and WK_CTRL_2 are reset to following values (=wake sources) ‘xxx0 0001’ and ‘x0x0 0111’ in order to ensure that the device can be woken again. BUS_CTRL_1 Bus Control (Address 000 0100B) POR / Soft Reset Value: 0000 0000B; Restart Value: 0000 00yy B 76543210 Reserved Reserved Rese rved Reserved Reserved Reserved CAN_1 CAN_0 r rrrrrr r w h r w h Field Bits Type Description Reserved 7:3 r Reserved, always reads as 0 Reserved 2r Reserved, always reads as 0 CAN 1:0 rwh HS-CAN Module Modes 00B , CAN OFF 01B , CAN is wake capable 10B , CAN Receive Only Mode 11B , CAN Normal Mode BUS_CTRL_2 Bus Control (Address 000 0101 POR / Soft Reset Value: 0000 0000B; Restart Value: 00x0 0000B 76543210 Reserved Reserved I_PEAK_TH Reserved Reserved Reserved Reserved Reserved r rr r w rrrrr Field Bits Type Description Reserved 7:6 r Reserved, always reads as 0 I_PEAK_TH 5r w VCC1 Active Peak Threshold Selection 0B , low VCC1 active peak thre shold selected (ICC1,peak_1) 1B , higher VCC1 active peak threshold selected (ICC1,peak_2) Reserved 4:0 r Reserved, always reads as 0

Datasheet 126 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface Notes 1. The bit I_PEAK_TH can be modified in SBC Init and Normal Mode. In SBC Stop Mode this bit is Read only but SPI_FAIL will not be set when trying to modify the bit in SBC STOP Mode and no INT is triggered in case INT_ GLOBAL is set. 2. see Figure 26 for detailed state changes of CAN Transceiver for different SBC modes 3. Failure Handling Mechanism: When the device enters Fa il-Safe Mode due to a failure (TSD2, WD-Failure,...), then the wake registers BUS_CTRL_1, and WK_CTRL_2 are reset to following values (=wake sources) ‘xxx0 1001’, and ‘x0x0 0111’ in order to ensure that the device can be woken again.

Datasheet 127 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface WK_CTRL_1 Internal Wake Input Control (Address 000 0110B) POR / Soft Reset Value: 0000 0000B; Restart Value: xx00 0000 B 76543210 TIMER2_WK_ EN TIMER1_WK_ EN Reserved Reserved Reserved WD_STM_ EN_1 Reserved Reserved r rw rw r r r rwh r r Field Bits Type Description TIMER2_WK _EN 7r w Timer2 Wake Source Control (for cyclic wake) 0B , Timer2 wake disabled 1B , Timer2 is enabled as a wake source TIMER1_WK _EN 6r w Timer1 Wake Source Control (for cyclic wake) 0B , Timer1 wake disabled 1B , Timer1 is enabled as a wake source Reserved 5:3 r Reserved, always reads as 0 WD_STM_ EN_1 2r w h Watchdog Deactivation during Stop Mode, bit 1 (Chapter 14.2.4) 0B , Watchdog is active in Stop Mode 1B , Watchdog is deactivated in Stop Mode Reserved 1:0 r Reserved, always reads as 0

Datasheet 128 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface Notes 1. WK_MEAS is by default configured for standard WK functionality (WK1 and WK2). The bits WK1_EN and WK2_EN are ignored in case WK_MEAS is activated. If the bit is set to ‘1’ then the measurement function is enabled during Normal Mode & the bits WK1_EN and WK2_EN are ignored. The bits WK1/”_LVL bits need to be ignored as well. 2. The wake sources CAN are selected in the register BUS_CTRL_1 by setting the respective bits to ‘wake capable’ 3. Failure Handling Mechanism: When the device enters Fa il-Safe Mode due to a failure (TSD2, WD-Failure,...), then the wake registers BUS_CTRL_1 and WK_CTRL_2 are reset to following values (=wake sources) ‘xxx0 0001’ and ‘x0x0 0111’ in order to ensure that the device can be woken again. WK_CTRL_2 External Wake Source Control (Address 000 0111B) POR / Soft Reset Value: 0000 0111B; Restart Value: x0x0 0xxx B 76543210 INT_GLOBAL Reserved WK_MEAS Reserved Reserved WK3_EN WK2_EN WK1_EN w r r wrr wr rr w r w r w Field Bits Type Description INT_ GLOBAL 7r w Global Interrupt Configuration (see also Chapter 12.1) 0B , Only wake sources trigger INT (default) 1B , All status information register bits will trigger INT (including all wake sources) Reserved 6r Reserved, always reads as 0 WK_MEAS 5r w WK / Measurement selection (see also Chapter 11.2.2) 0B , WK functionality enabled for WK1 and WK2 1B , Measurement functionality enabled; WK1 & WK2 are disabled as wake sources, i.e. bits WK1/2_EN bits are ignored Reserved 4:3 r Reserved, always reads as 0 WK3_EN 2r w WK3 Wake Source Control 0B , WK3 wake disabled 1B , WK3 is enabled as a wake source WK2_EN 1r w WK2 Wake Source Control 0B , WK2 wake disabled 1B , WK2 is enabled as a wake source WK1_EN 0r w WK1 Wake Source Control 0B , WK1 wake disabled 1B , WK1 is enabled as a wake source

Datasheet 129 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface WK_PUPD_CTRL Wake Input Level Control (Address 000 1000B) POR / Soft Reset Value: 0000 0000B; Restart Value: 00xx xxxx B 76543210 Reserved Reserved WK3_PUPD_1 WK3_PUPD_0 WK2_PUPD_1 WK2_PUPD_0 WK1_PUPD_1 WK1_PUPD_0 r r r rw rw rw rw rw rw Field Bits Type Description Reserved 7:6 r Reserved, always reads as 0 WK3_PUPD 5:4 rw WK3 Pull-Up / Pull-Down Configuration 00B , No pull-up / pull-down selected 01B , Pull-down resistor selected 10B , Pull-up resistor selected 11B , Automatic switching to pull-up or pull-down WK2_PUPD 3:2 rw WK2 Pull-Up / Pull-Down Configuration 00B , No pull-up / pull-down selected 01B , Pull-down resistor selected 10B , Pull-up resistor selected 11B , Automatic switching to pull-up or pull-down WK1_PUPD 1:0 rw WK1 Pull-Up / Pull-Down Configuration 00B , No pull-up / pull-down selected 01B , Pull-down resistor selected 10B , Pull-up resistor selected 11B , Automatic switching to pull-up or pull-down

Datasheet 130 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface Note: When selecting a filter time configuration, the us er must make sure to also assign the respective timer to at least one HS switch during cyclic sense operation WK_FLT_CTRL Wake Input Filter Time Control (Address 000 1001B) POR / Soft Reset Value: 0000 0000B; Restart Value: 00xx xxxx B 76543210 Reserved Reserved WK3_FLT_1 WK3_FLT_0 WK2_FLT_1 WK2_FLT_0 WK1_FLT_1 WK1_FLT_0 r r r rw rw rw rw rw rw Field Bits Type Description Reserved 7:6 r Reserved, always reads as 0 WK3_FLT 5:4 rw WK3 Filter Time Configuration 00B , Configuration A: Filter with 16µs filter time (static sensing) 01B , Configuration B: Filter with 64µs filter time (static sensing) 10B , Configuration C: Filtering at the end of the on-time; a filter time of 16µs (cyclic sensing) is selected, Timer1 11B , Configuration D: Filtering at the end of the on-time; a filter time of 16µs (cyclic sensing) is selected, Timer2 WK2_FLT 3:2 rw WK2 Filter Time Configuration 00B , Configuration A: Filter with 16µs filter time (static sensing) 01B , Configuration B: Filter with 64µs filter time (static sensing) 10B , Configuration C: Filtering at the end of the on-time; a filter time of 16µs (cyclic sensing) is selected, Timer1 11B , Configuration D: Filtering at the end of the on-time; a filter time of 16µs (cyclic sensing) is selected, Timer2 WK1_FLT 1:0 rw WK1 Filter Time Configuration 00B , Configuration A: Filter with 16µs filter time (static sensing) 01B , Configuration B: Filter with 64µs filter time (static sensing) 10B , Configuration C: Filtering at the end of the on-time; a filter time of 16µs (cyclic sensing) is selected, Timer1 11B , Configuration D: Filtering at the end of the on-time; a filter time of 16µs (cyclic sensing) is selected, Timer2

Datasheet 131 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface Notes 1. A timer must be first assigned and is then automati cally activated as soon as the on-time is configured. 2. If cyclic sense is selected and the HS switches ar e cleared during SBC Restart Mode, then also the timer settings (period and on-time) are cleared to avoid incorrect switch detection. 3. In case the timer are set as wake sources and cyclic se nse is running, then both cyclic sense and cyclic wake will be active at the same time. TIMER1_CTRL Timer1 Control and Selection (Address 000 1100B) POR / Soft Reset Value: 0000 0000B; Restart Value: 0000 0000 B 76543210 Reserved TIMER1_ ON_2 TIMER1_ ON_1 TIMER1_ ON_0 Reserved TIMER1_ PER_2 TIMER1_ PER_1 TIMER1_ PER_0 r r rwh rwh rwh r rwh rwh rwh Field Bits Type Description Reserved 7r Reserved, always reads as 0 TIMER1_ ON 6:4 rwh Timer1 On-Time Configuration 000B , OFF / Low (timer not running, HSx output is low) 001B , 0.1ms on-time 010B , 0.3ms on-time 011B , 1.0ms on-time 100B , 10ms on-time 101B , 20ms on-time 110B , OFF / HIGH (timer not running, HSx output is high) 111B , reserved Reserved 3r Reserved, always reads as 0 TIMER1_ PER 2:0 rwh Timer1 Period Configuration 000B , 10ms 001B , 20ms 010B , 50ms 011B , 100ms 100B , 200ms 101B , 1s 110B , 2s 111B , reserved

Datasheet 132 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface Notes 1. A timer must be first assigned and is then automati cally activated as soon as the on-time is configured. 2. If cyclic sense is selected and the HS switches ar e cleared during SBC Restart Mode, then also the timer settings (period and on-time) are cleared to avoid incorrect switch detection. TIMER2_CTRL Timer2 Control and selection (Address 000 1101B) POR / Soft Reset Value: 0000 0000B; Restart Value: 0000 0000 B 76543210 Reserved TIMER2_ ON_2 TIMER2_ ON_1 TIMER2_ ON_0 Reserved TIMER2_ PER_2 TIMER2_ PER_1 TIMER2_ PER_0 r r rwh rwh rwh r rwh rwh rwh Field Bits Type Description Reserved 7r Reserved, always reads as 0 TIMER2_ ON 6:4 rwh Timer2 On-Time Configuration 000B , OFF / Low (timer not running, HSx output is low) 001B , 0.1ms on-time 010B , 0.3ms on-time 011B , 1.0ms on-time 100B , 10ms on-time 101B , 20ms on-time 110B , OFF / HIGH (timer not running, HSx output is high) 111B , reserved Reserved 3r Reserved, always reads as 0 TIMER2_ PER 2:0 rwh Timer2 Period Configuration 000B , 10ms 001B , 20ms 010B , 50ms 011B , 100ms 100B , 200ms 101B , 1s 110B , 2s 111B , reserved

Datasheet 133 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface SW_SD_CTRL Switch Shutdown Control (Address 001 0000B) POR / Soft Reset Value: 0000 0000B; Restart Value: 0xxx 0000 B 76543210 Reserved HS_OV_SD_E N HS_UV_SD_E N HS_OV_UV_R EC Reserved Reserved Reserved Reserved r rr w r w r wr r r r Field Bits Type Description Reserved 7r Reserved, always reads as 0 HS_OV_SD_ EN 6r w Shutdown Disabling of HS1...4 in case of VSHS OV 0B , shutdown enabled in case of VSHS OV 1B , shutdown disabled in case of VSHS OV HS_UV_SD_ EN 5r w Shutdown Disabling of HS1...4 in case of VSHS UV 0B , shutdown enabled in case of VSHS UV 1B , shutdown disabled in case of VSHS UV HS_OV_UV_ REC 4r w Switch Recovery after Removal of VSHS OV/UV for HS1...4 0B , Switch recovery is disabled 1B , Previous state before VSHS OV/UV is enabled after OV/UV condition is removed Reserved 3:0 r Reserved, always reads as 0

Datasheet 134 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface Note: The bits for the switches are also rese t in case of overcurrent and overtemperature. HS_CTRL1 High-Side Switch Control 1 (Address 001 0100B) POR / Soft Reset Value: 0000 0000B; Restart Value: 0000 0000 B 76543210 Reserved HS2_2 HS2_1 HS2_0 Reserved HS1_2 HS1_1 HS1_0 r rw rwh rwh rwh r rwh rwh rwh Field Bits Type Description Reserved 7r Reserved, always reads as 0 HS2 6:4 rwh HS2 Configuration 000B , Off 001B , On 010B , Controlled by Timer1 011B , Controlled by Timer2 100B , Controlled by PWM1 101B , Controlled by PWM2 110B , Reserved 111B , Reserved Reserved 3r Reserved, always reads as 0 HS1 2:0 rwh HS1 Configuration 000B , Off 001B , On 010B , Controlled by Timer1 011B , Controlled by Timer2 100B , Controlled by PWM1 101B , Controlled by PWM2 110B , Reserved 111B , Reserved

Datasheet 135 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface Note: The bits for the switches are also rese t in case of overcurrent and overtemperature. HS_CTRL2 High-Side Switch Control 2 (Address 001 0101B) POR / Soft Reset Value: 0000 0000B; Restart Value: 0000 0000 B 76543210 Reserved HS4_2 HS4_1 HS4_0 Reserved HS3_2 HS3_1 HS3_0 r r rwh rwh rwh r rwh rwh rwh Field Bits Type Description Reserved 7r Reserved, always reads as 0 HS4 6:4 rwh HS4 Configuration 000B , Off 001B , On 010B , Controlled by Timer1 011B , Controlled by Timer2 100B , Controlled by PWM1 101B , Controlled by PWM2 110B , Reserved 111B , Reserved Reserved 3r Reserved, always reads as 0 HS3 2:0 rwh HS3 Configuration 000B , Off 001B , On 010B , Controlled by Timer1 011B , Controlled by Timer2 100B , Controlled by PWM1 101B , Controlled by PWM2 110B , Reserved 111B , Reserved

Datasheet 136 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface Note: When selecting a filter time configuration, the us er must make sure to also assign the respective timer to at least one HS switch during cyclic sense operation GPIO_CTRL GPIO Configuration Control (Address 001 0111B) POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxx B 76543210 FO_DC_1 FO_DC_0 GPIO2_2 GPIO2_1 GPIO2_0 GPIO1_2 GPIO1_1 GPIO1_0 r rw rw rw rw rw rw rw rw Field Bits Type Description FO_DC 7:6 rw Duty Cycle Configuration of FO3 (if selected) 00B , 20% 01B , 10% 10B , 5% 11B , 2.5% GPIO2 5:3 rw GPIO2 Configuration 000B , FO3 selected 001B , FO3 selected 010B , FO3 selected 011B , FO3 selected 100B , OFF 101B , Wake input enabled (16µs static filter) 110B , Low-Side Switch ON 111B , High-Side Switch ON GPIO1 2:0 rw GPIO1 Configuration 000B , FO2 selected 001B , FO2 selected 010B , FO2 selected 011B , FO2 selected 100B , OFF 101B , Wake input enabled (16µs static filter) 110B , Low-Side Switch ON 111B , High-Side Switch ON

Datasheet 137 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface Note: The min. On-time during PWM is limited by the ac tual Ton and Toff time of the respective HS switch, e.g. the PWM setting ‘000 0001’ could not be realized. Note: The min. On-time during PWM is limited by the ac tual Ton and Toff time of the respective HS switch, e.g. the PWM setting ‘000 0001’ could not be realized. PWM1_CTRL PWM1 Configuration Control (Address 001 1000B) POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxx B 76543210 r rw rw rw rw rw rw rw rw Field Bits Type Description PWM1_DC 7:0 rw PWM1 Duty Cycle (bit0=LSB; bit7=MSB) 0000 0000B, 100% OFF xxxx xxxx B, ON with DC fraction of 255 1111 1111B, 100% ON PWM2_CTRL PWM2 Configuration Control (Address 001 1001 POR / Soft Reset Value: 0000 0000B; Restart Value: xxxx xxxx B 76543210 r rw rw rw rw rw rw rw rw Field Bits Type Description PWM2_DC 7:0 rw PWM2 Duty Cycle (bit0=LSB; bit7=MSB) 0000 0000B, 100% OFF xxxx xxxxB, ON with DC fraction of 255 1111 1111B, 100% ON

Datasheet 138 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface Note: The min. On-time during PWM is limited by the ac tual Ton and Toff time of the respective HS switch, e.g. the PWM setting ‘000 0001’ could not be realized. Notes 1. The SYS_STATUS_CTRL register is an exception for the default values, i.e. it will keep its configured value also after a Soft Reset. 2. This byte is intended for storing system configurations of the ECU by the microcontroller and is only accessible in SBC Normal Mode. The byte is not accessible by the SBC and is also not cleared after Fail-Safe or SBC Restart Mode. It allows the microcontroller to quickly store system configuration without loosing the data. PWM_FREQ_CTRL PWM Frequency Configuration Control (Address 001 1100B) POR / Soft Reset Value: 0000 0000B; Restart Value: 0000 0x0x B 76543210 Reserved Reserved Reserv ed Reserved Reserved PWM2_FREQ Reserved PWM1_FREQ r rrrrr r w r r w Field Bits Type Description Reserved 7:3 r Reserved, always reads as 0 PWM2_ FREQ 2r w PWM2 Frequency Selection 0B , 200Hz configuration 1B , 400Hz configuration Reserved 1r Reserved, always reads as 0 PWM1_ FREQ 0r w PWM1 Frequency Selection 0B , 200Hz configuration 1B , 400Hz configuration SYS_STATUS_CTRL System Status Control (Address 001 1110B) POR Value: 0000 0000B; Restart Value/Soft Reset Value: xxxx xxxx B 76543210 SYS_STAT_7 SYS_STAT_6 SYS_STAT_5 SYS_STAT_4 SYS_STAT_3 SYS_STAT_2 SYS_STAT_1 SYS_STAT_0 r rw rw rw rw rw rw rw rw Field Bits Type Description SYS_STAT 7:0 rw System Status Control Byte (bit0=LSB; bit7=MSB) Dedicated byte for system configuration, access only by microcontroller. Cleared after power up and Soft Reset

Datasheet 139 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface

15.6 SPI Status Information Registers

READ/CLEAR Operation (see also Chapter 15.3):

One 16-bit SPI command consist of two bytes: - the 7-bit address and one additional bit for the register access mode and - following the data byte The numbering of following bit definitions refers to the data byte and correspond to the bits D0...D7 and to the SPI bits 8...15 (see also figure).
There are two different bit types: - ‘r’ = READ: read only bits (or reserved bits) - ‘rc’ = READ/CLEAR: readable and clearable bits
Reading a register is done byte wise by setting the SPI bit 7 to “0” (= Read Only)
Clearing a register is done byte wi se by setting the SPI bit 7 to “1”
SPI status registers are in general not cleare d or changed automatically (an exception are the WD_FAIL bits). This must be done by the microcontroller via SPI command The registers are addressed wordwise.

Datasheet 140 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface

15.6.1 General Status Registers

The VCC1 undervoltage prewarning threshold V PW,f / VPW,r is a fixed threshold and independent of the VCC1 undervoltage reset thresholds. SUP_STAT_2 Supply Voltage Fail Status (Address 100 0000B) POR / Soft Reset Value: 0000 0000B; Restart Value: 0x0x xxxx B 76543210 Reserved VS_UV Reserved VCC3_OC VCC3_UV VCC3_OT VCC1_OV VCC1_WARN r r rc r rc rc rc rc rc Field Bits Type Description Reserved 7r Reserved, always reads as 0 VS_UV 6r c VS Undervoltage Detection (VS,UV) 0B , No VS undervoltage detected 1B , VS undervoltage detected Reserved 5r Reserved, always reads as 0 VCC3_OC 4r c VCC3 Overcurrent Detection 0B , No OC 1B , OC detected VCC3_UV 3r c VCC3 Undervoltage Detection 0B , No VCC3 UV detection 1B , VCC3 UV Fail detected VCC3_OT 2r c VCC3 Overtemperature Detection 0B , No overtemperature 1B , VCC3 overtemperature detected VCC1_ OV 1r c VCC1 Overvoltage Detection (V CC1,OV,r) 0B , No VCC1 overvoltage warning 1B , VCC1 overvoltage detected VCC1_ WARN 0r c VCC1 Undervoltage Prewarning (VPW,f) 0B , No VCC1 undervoltage prewarning 1B , VCC1 undervoltage prewarning detected

Datasheet 141 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface Notes 1. The MSB of the POR/Soft Reset value is marked as ‘y’: the default value of the POR bit is set after Power-on reset (POR value = 1000 0000). However it will be cleared after a SBC Soft Reset command (Soft Reset value = 0000 0000). 2. During Sleep Mode, the bits V CC1_SC,VCC1_OV and VCC1_UV will not be set when VCC1 is off 3. The VCC1_UV bit is never updated in SBC Restart Mode, in SBC Init Mode it is only updated after RO was released for the first time, it is always updated in SBC Normal and Stop Mode, and it is always updated in any SBC modes in a VCC1_SC condition (after VCC1_UV = 1 for >4ms). SUP_STAT_1 Supply Voltage Fail Status (Address 100 0001B) POR / Soft Reset Value: y000 0000B; Restart Value: xxxx xx0x B 76543210 POR VSHS_UV VSHS_OV VCC2_OT VCC2 _UV VCC1_SC VCC1_UV_FS VCC1_UV r rc rc rc rc rc rc rc rc Field Bits Type Description POR 7r c Power-On Reset Detection 0B , No POR 1B , POR occurred VSHS_UV 6r c VSHS Undervoltage Detection (V SHS,UVD) 0B , No VSHS-UV 1B , VSHS-UV detected VSHS_OV 5r c VSHS Overvoltage Detection (VSHS,OVD) 0B , No VSHS-OV 1B , VSHS-OV detected VCC2_OT 4r c VCC2 Overtemperature Detection 0B , No overtemperature 1B , VCC2 overtemperature detected VCC2_UV 3r c VCC2 Undervoltage Detection (VCC2,UV,f) 0B , No VCC2 undervoltage 1B , VCC2 undervoltage detected VCC1_SC 2r c VCC1 Short to GND Detection (<Vrtx for t>4ms after switch on) 0B , No short 1B , VCC1 short to GND detected VCC1_UV _FS 1r c VCC1 UV-Detection (due to Vrtx reset) 0B , No Fail-Safe Mode entry du e to 4th consecutive VCC1_UV 1B , Fail-Safe Mode entry due to 4th consecutive VCC1_UV VCC1_UV 0r c VCC1 UV-Detection (due to Vrtx reset) 0B , No VCC1_UV detection 1B , VCC1 UV-Fail detected

Datasheet 142 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface Note: TSD1 and TSD2 are not reset automatically, ev en if the temperature pre warning or TSD1 OT condition is not present anymore. Also TSD2 is not reset. THERM_STAT Thermal Protection Status (Address 100 0010B) POR / Soft Reset Value: 0000 0000B; Restart Value: 0000 0xxx B 76543210 Reserved Reserved Reserved Re served Reserved TSD2 TSD1 TPW r rrrrr r c r c r c Field Bits Type Description Reserved 7:3 r Reserved, always reads as 0 TSD2 2r c TSD2 Thermal Shut-Down Detection 0B , No TSD2 event 1B , TSD2 OT detected - leading to SBC Fail-Safe Mode TSD1 1r c TSD1 Thermal Shut-Down Detection 0B , No TSD1 fail 1B , TSD1 OT detected TPW 0r c Thermal Pre Warning 0B , No Thermal Pre warning 1B , Thermal Pre warning detected

Datasheet 143 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface Notes 1. The bits DEV_STAT show the status of the device before it went through Restart. Either the device came from regular Sleep Mode (‘10’) or a failure (‘01’ - SBC Restart or SBC Fail-Safe Mode: WD fail, TSD2 fail, VCC_UV fail or VCC1_OV if bit VCC1_OV_RST is set) occurred. Failure is also an illegal command from SBC Stop to SBC Sleep Mode or going to SBC Sleep Mode without activation of any wake source. Coming from SBC Sleep Mode (‘10’) will also be shown if there was a trial to enter SBC Sleep Mode without having cleared all wake flags before. 2. The WD_FAIL bits are configured as a counter and are the only status bits, which are cleared automatically by the SBC. They are cleared after a successful watchdog trigger and when the watchdog is stopped (also in SBC Sleep and Fail-Safe Mode unless it was reached due to a watchdog failure). See also Chapter 13.1. 3. The SPI_FAIL bit is cleared only by SPI command 4. In case of Config 2/4 the WD_Fail co unter is frozen in case of WD trigger failure until a successful WD trigger. 5. If CFG = ‘0’ then a 1st watchdog failure will not trigger the FO outputs or the FAILURE bit but only force the SBC into SBC Restart Mode. DEV_STAT Device Information Status (Address 100 0011B) POR / Soft Reset Value: 0000 0000B; Restart Value: xx00 xxxx B 76543210 DEV_STAT_1 DEV_STAT_0 Reserved Reserved WD_FAIL_1 WD_FAIL_0 SPI_FAIL FAILURE r rc rc r r rh rh rc rc Field Bits Type Description DEV_STAT 7:6 rc Device Status before Restart Mode 00B , Cleared (Register must be actively cleared) 01B , Restart due to failure (WD fa il, TSD2, VCC1_UV); also after a wake from Fail-Safe Mode 10B , Sleep Mode 11B , Reserved Reserved 5:4 r Reserved, always reads as 0 WD_FAIL 3:2 rh Number of WD-Failure Events (1/2 WD failures depending on CFG) 00B , No WD Fail 01B , 1x WD Fail, FOx activation - Config 2 selected 10B , 2x WD Fail, FOx activation - Config 1 / 3 / 4 selected 11B , Reserved (never reached) SPI_FAIL 1r c SPI Fail Information 0B , No SPI fail 1B , Invalid SPI command detected FAILURE 0r c Activation of Fail Output FO 0B , No Failure 1B , Failure occurred

Datasheet 144 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface Notes 1. The VCAN_UV comparator is enabled if the mode bit CAN_1 = ‘1’, i.e. in CAN Normal or CAN Receive Only Mode. BUS_STAT_1 Bus Communication Status (Address 100 0100B) POR / Soft Reset Value: 0000 0000B; Restart Value: 0000 0xxx B 76543210 Reserved Reserved Reserved Reserved Reserved CAN_FAIL_1 CAN_FAIL_0 VCAN_UV r rrrrr r c r c r c Field Bits Type Description Reserved 7r Reserved, always reads as 0 Reserved 6:5 r Reserved, always reads as 0 Reserved 4:3 r Reserved, always reads as 0 CAN_FAIL 2:1 rc CAN Failure Status 00B , No error 01B , CAN TSD 10B , CAN_TXD_DOM: TXD dominant time out for longer than t TxD_CAN_TO 11B , CAN_BUS_DOM: BUS dominant time out for longer than tBUS_CAN_TO VCAN_UV 0r c Undervoltage CAN Bus Supply 0B , Normal operation 1B , CAN Supply undervoltage detected. Transmitter disabled

Datasheet 145 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface Note: The respective wake source bit will also be set when the device is woken from SBC Fail-Safe Mode WK_STAT_1 Wake-up Source and Information Status (Address 100 0110B) POR / Soft Reset Value: 0000 0000B; Restart Value: 00xx 0xxx B 76543210 Reserved Reserved CAN_WU TIMER_WU Reserved WK3_WU WK2_WU WK1_WU r rr r c r c r r c r c r c Field Bits Type Description Reserved 7r Reserved, always reads as 0 Reserved 6r Reserved, always reads as 0 CAN_WU 5r c Wake up via CAN Bus 0B , No Wake up 1B , Wake up TIMER_WU 4r c Wake up via TimerX 0B , No Wake up 1B , Wake up Reserved 3r Reserved, always reads as 0 WK3_WU 2r c Wake up via WK3 0B , No Wake up 1B , Wake up WK2_WU 1r c Wake up via WK2 0B , No Wake up 1B , Wake up WK1_WU 0r c Wake up via WK1 0B , No Wake up 1B , Wake up

Datasheet 146 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface WK_STAT_2 Wake-up Source and Information Status (Address 100 0111B) POR / Soft Reset Value: 0000 0000B; Restart Value: 00xx 0000 B 76543210 Reserved Reserved GPIO2_WU GPIO1_WU Reserved Reserved Reserved Reserved r rr r c r c rrrr Field Bits Type Description Reserved 7:6 r Reserved, always reads as 0 GPIO2_WU 5r c Wake up via GPIO2 0B , No Wake up 1B , Wake up GPIO1_WU 4r c Wake up via GPIO1 0B , No Wake up 1B , Wake up Reserved 3:0 r Reserved, always reads as 0

Datasheet 147 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface Note: GPIOx_LVL is updated in SBC Norm al and Stop Mode if configured as wake input, low-side switch or high-side switch. In cyclic sense or wake mode, the registers contain the sampled level, i.e. the registers are updated after every sampling. The GPIOs are not capable of cyclic sensing. If selected as GPIO then the respective level is shown even if configured as low-side or high-side. WK_LVL_STAT WK Input Level (Address 100 1000B) POR / Soft Reset Value: xx00 0xxxB; Restart Value: xxxx 0xxx B 76543210 SBC_DEV _LVL CFGP GPIO2_LVL GPIO1_LVL Reserved WK3_LVL WK2_LVL WK1_LVL r rrrrrrrr Field Bits Type Description SBC_DEV _LVL 7r Status of SBC Operating Mode at FO3/TEST Pin 0B , User Mode activated 1B , SBC Development Mode activated CFGP 6r Device Configuration Status 0B , No external pull-up resistor connected on INT (Config 2/4) 1B , External pull-up resistor connected on INT (Config 1/3) GPIO2_LVL 5r Status of GPIO2 (if selected as GPIO) 0B , Low Level (=0) 1B , High Level (=1) GPIO1_LVL 4r Status of GPIO1 (if selected as GPIO) 0B , Low Level (=0) 1B , High Level (=1) Reserved 3r Reserved, always reads as 0 WK3_LVL 2r Status of WK3 0B , Low Level (=0) 1B , High Level (=1) WK2_LVL 1r Status of WK2 0B , Low Level (=0) 1B , High Level (=1) WK1_LVL 0r Status of WK1 0B , Low Level (=0) 1B , High Level (=1)

Datasheet 148 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface Note: The OC/OT bit might be set for V POR,f < VS < 5.5V (see also Chapter 4.2) HS_OC_OT_STAT High-Side Switch Overload Status (Address 101 0100B) POR / Soft Reset Value: 0000 0000B; Restart Value: 0000 xxxx B 76543210 Reserved Reserved Reserved Reserved HS4_OC_OT HS3_OC_OT HS2_OC_OT HS1_OC_OT r rrrr r c r c r c r c Field Bits Type Description Reserved 7:4 r Reserved, always reads as 0 HS4_OC_OT 3r c Overcurrent & Overtemperature Detection HS4 0B , No OC or OT 1B , OC or OT detected HS3_OC_OT 2r c Overcurrent & Overtemperature Detection HS3 0B , No OC or OT 1B , OC or OT detected HS2_OC_OT 1r c Overcurrent & Overtemperature Detection HS2 0B , No OC or OT 1B , OC or OT detected HS1_OC_OT 0r c Overcurrent & Overtemperature Detection HS1 0B , No OC or OT 1B , OC or OT detected

Datasheet 149 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface HS_OL_STAT High-Side Switch Open-Load Status (Address 101 0101B) POR / Soft Reset Value: 0000 0000B; Restart Value: 0000 xxxx B 76543210 Reserved Reserved Reserved Rese rved HS4_OL HS3_OL HS2_OL HS1_OL r rrrr r c r c r c r c Field Bits Type Description Reserved 7:4 r Reserved, always reads as 0 HS4_OL 3r c Open-Load Detection HS4 0B , No OL 1B , OL detected HS3_OL 2r c Open-Load Detection HS3 0B , No OL 1B , OL detected HS2_OL 1r c Open-Load Detection HS2 0B , No OL 1B , OL detected HS1_OL 0r c Open-Load Detection HS1 0B , No OL 1B , OL detected

Datasheet 150 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface

15.6.2 Family and Produc t Information Register

The actual default register value after POR, Soft Reset or Restart of PROD will depend on the respective product. Therefore the value ‘y’ is specified. 2. SWK = Selective Wake feature in CAN Partial Networking standard FAM_PROD_STAT Family and Product Identification Register (Address 111 1110B) POR / Soft Reset Value: 0011 yyyy B; Restart Value: 0011 yyyy B 76543210 FAM_3 FAM_2 FAM_1 FAM_0 PROD_3 PROD_2 PROD_1 PROD_0 r rrrrrrrr Field Bits Type Description FAM 7:4 r SBC Family Identifier (bit4=LSB; bit7=MSB) 0 001B, Driver SBC Family 0 010B, DC/DC-SBC Family 0 011B, Mid-Range SBC Family 0 100B, Multi-CAN SBC Family 0 101B, Lite-CAN SBC Family 0 111B, Mid-Range+ SBC Family x x x xB, reserved for future products PROD 3:0 r SBC Product Identifier (bit0=LSB; bit3=MSB) 0 0 0 1B, reserved 0 1 0 1B, TLE9261QXV33 (VCC1 = 3.3V, no LIN, VCC3, no SWK) 1 0 0 1B, TLE9262QXV33 (VCC1 = 3.3V, 1 LIN, VCC3, no SWK) 1 1 0 1B, TLE9263QXV33 (VCC1 = 3.3V, 2 LIN, VCC3, no SWK)

Datasheet 151 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface

15.7 Electrical Characteristics

Table 28 Electrical Characteristics VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. SPI frequency Maximum SPI frequency fSPI,max ––4 . 0 M H z 1) P_16.7.1 SPI Interface; Logic Inputs SDI, CLK and CSN H-input Voltage Threshold VIH – – 0.7* VCC1 V – P_16.7.2 L-input Voltage Threshold VIL 0.3* VCC1 – – V – P_16.7.3 Hysteresis of input Voltage VIHY 0.08 × VCC1 0.12 × VCC1 0.5 × VCC1 V 1) P_16.7.4 Pull-up Resistance at pin CSN RICSN 20 40 80 k Ω VCSN = 0.7 x VCC1 P_16.7.5 Pull-down Resistance at pin SDI and CLK RICLK/SDI 20 40 80 k Ω VSDI/CLK = 0.2 x VCC1 P_16.7.6 Input Capacitance at pin CSN, SDI or CLK CI –1 0 –p F 1) P_16.7.7 Logic Output SDO H-output Voltage Level VSDOH VCC1 - 0.4 VCC1 - 0.2 –V IDOH = -1.6 mA P_16.7.8 Tristate Leakage Current ISDOLK -10 – 10 µA VCSN = VCC1;

0 V < VDO < VCC1

P_16.7.10 Tristate Input Capacitance CSDO –1 0 1 5 p F 1) P_16.7.11 Data Input Timing1) Clock Period tpCLK 250 – – ns – P_16.7.12 Clock High Time tCLKH 125 – – ns – P_16.7.13 Clock Low Time tCLKL 125 – – ns – P_16.7.14 Clock Low before CSN Low tbef 125 – – ns – P_16.7.15 CSN Setup Time tlead 250 – – ns – P_16.7.16 CLK Setup Time tlag 250 – – ns – P_16.7.17 Clock Low after CSN High tbeh 125 – – ns – P_16.7.18 SDI Set-up Time tDISU 100 – – ns – P_16.7.19 SDI Hold Time tDIHO 50 – – ns – P_16.7.20 Input Signal Rise Time at pin SDI, CLK and CSN trIN – – 50 ns – P_16.7.21

Datasheet 152 Rev. 1.1 2019-09-27 TLE9261BQXV33 Serial Peripheral Interface Figure 52 SPI Timing Diagram Note: Numbers in drawing correlate to the last 2 digits of the Number field in the Electrical Characteristics table. Input Signal Fall Time at pin SDI, CLK and CSN tfIN – – 50 ns – P_16.7.22 Delay Time for Mode Changes2) tDel,Mode – – 6 µs includes internal oscillator tolerance P_16.7.23 CSN High Time t CSN(high) 3 – – µs – P_16.7.24 Data Output Timing1) SDO Rise Time trSDO –3 0 8 0 n s CL = 100 pF P_16.7.25 SDO Fall Time tfSDO –3 0 8 0 n s CL = 100 pF P_16.7.26 SDO Enable Time tENSDO – – 50 ns low impedance P_16.7.27 SDO Disable Time tDISSDO – – 50 ns high impedance P_16.7.28 SDO Valid Time tVASDO ––5 0 n s CL = 100 pF P_16.7.29 1) Not subject to production test; specified by design 2) Applies to all mo de changes triggered via SPI commands Table 28 Electrical Characteristics (cont’d) VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. CSN CLK SDI SDO 1413 not defined LSB MSB Flag LSB MSB 27 29 15 18

Datasheet 153 Rev. 1.1 2019-09-27 TLE9261BQXV33

Application Information

16.1 Application Diagram

Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. Figure 53 Simplified Application Diagram VBAT C11 R10 CANH C12 R11 CANL VSS VDDCSN CLK SDI SDO µC INT CSN CLK SDO SDI FOx VCC1 VCC1 WK1 HS1 VS Reset INT RO VCAN GND VCC GND IC1 VS LOGIC State Machine Application _information _TLE 9261 .vsd VS CANH CANL CAN cell VBAT VBAT VS TLE9261 VS VCC3REF HS2 HS3 VSHS HS4 LH VCC2 WK3 WK2 R5R3 Hall1 Hall2 Other loads , e.g. sensor , opamp , ... TxD CAN RxD CAN TxD CAN RxD CAN VCC2 VSHS VSHS VSHS VSHS D2 C2 Note: The external capacitance on FO3/TEST must be <=10nF in oder to ensure proper detection of SBC Development Mode und SBC user mode operation C13 R12 VCC3 VCC3BVCC3SH C14 C10 VCC2 C17 C18

Datasheet 154 Rev. 1.1 2019-09-27 TLE9261BQXV33 Note: Unused outputs are recommended to be left un connected on the application board. If unused output pins are routed to an external connector which leaves the ECU, then these pins should have provision for a zero ohm jumper (depopulated if unused) or ESD protection. Table 29 Bill of Material for Simplified Application Diagram Ref. Typical Value Purpose / Comment Capacitances C1 68µF Buffering capacitor to cut off ba ttery spikes, depending on application C2 100nF EMC, blocking capacitor C3 22µF Buffering capacitor to cut off battery spikes from VSHS as separate supply input; Depending on application, only needed if VSHS is not connected to VS; C4 2.2µF low ESR As required by applicatio n, min. 470nF for stability and max. 68µF recommended C5 100nF ceramic Spike filtering, improve st ability of supply for microcontroller; not needed for SBC C6 2.2µF low ESR Blocking capacito r, min. 470nF for stability; if used for CAN supply place a 100nF ceramic capacitor in addition very close to VCAN pin for optimum EMC behavior C7 33nF As required by application, mandatory protection for off-board connections C8 33nF As required by application, mandatory protection for off-board connections C17 47pF Only required in case of off-bo ard connection to optimize EMC behavior, place close to pin C18 47pF Only required in case of off-bo ard connection to optimize EMC behavior, place close to pin C9 10nF Spike filtering, as required by ap plication, mandatory protection for off- board connections (see also Simplified Application Diagram with the Alternate Measurement Function) C10 10nF Spike filtering, as required by application, mandatory protection for off- board connections C11 10nF Spike filtering, as required by application, mandatory protection for off- board connections C12 4.7nF / OEM dependent Split termination stability C13 10µF low ESR Stability of VCC3, cera mic capacitor, e.g. Murata 10 µF/10 V GCM31CR71A106K64L or 2x 4.7 µF/10 V C14 47nF Only required in case of off-bo ard connection to optimize EMC behavior, place close to connector Resistances R1 10k Ω Wetting current of the switch, as required by application R2 10k Ω Limit the WK pin current, e.g. for ISO pulses R3 10k Ω Wetting current of the switch, as required by application

Datasheet 155 Rev. 1.1 2019-09-27 TLE9261BQXV33 Note: This is a simplified example of an application ci rcuit. The function must be verified in the real application. R4 10k Ω Limit the WK pin current, e.g. for ISO pulses R5 10k Ω Wetting current of the switch, as required by application R6 10k Ω Limit the WK pin current, e.g. for ISO pulses R7 depending on LED config. LED current li mitation, as required by application R8 depending on LED config. LED current li mitation, as required by application R9 47k Ω Selection of hardware configuration 1/3, i.e. in case of WD failure SBC Restart Mode is entered. If not connected, then hardware configuration 2/4 is selected R10 60 Ω / OEM dependent CAN bus termination R11 60 Ω / OEM dependent CAN bus termination R12 1 Ω shunt, depending on required current limitation or load sharing ratio Sense shunt for ICC3 current limitation (configured to typ. 235mA with 1Ω shunt) for stand-alone configuration; Setting of load sharing ratio (here ICC3/ICC1 = 1) in load sharing configuration. R15 10k Ω WK1 pin current limitation, e.g. for ISO pulses, for alternate measurement function (see also Simplified Application Diagram with the Alternate Measurement Function) R16 depending on application and microcontroller Voltage Divider resistor to adjust measurement voltage to microcontroller ADC input range (see also Simplified Application Diagram with the Alternate Measurement Function) R17 depending on application and microcontroller Voltage Divider resistor to adjust measurement voltage to microcontroller ADC input range (see also Simplified Application Diagram with the Alternate Measurement Function) Active Components D1 e.g. BAS 3010A, Infineon Re verse polarity protection for VS supply pins D2 e.g. BAS 3010A, Infineon Reverse pola rity protection for VSHS supply pin; if separate supplies are not needed, then connect VSHS to VS pins D3 LED As required by application, co nfigure series resistor accordingly D4 LED As required by application, co nfigure series resistor accordingly T1 e.g. BCR191W High active FO control T2 BCP 52-16, Infineon Power element of VCC3, cu rrent limit or load sharing ratio to be configured via shunt MJD 253, ON Semi Alternative power element of VCC3 µC e.g. TC2xxx Microcontroller Table 29 Bill of Material for Simplified Application Diagram (cont’d) Ref. Typical Value Purpose / Comment

Datasheet 156 Rev. 1.1 2019-09-27 TLE9261BQXV33 Figure 54 Simplified Applic ation Diagram with the Alternate Measurement Function via WK1 and WK2 Note: This is a very simplified example of an applicatio n circuit. The function must be verified in the real application.WK1 must be connected to signal to be measured and WK2 is the output to the microcontroller supervision function. The maximum current into WK1 must be <500uA. The minimum current into WK1 should be >5uA to ensure proper operation. e.g. 470uF VSS VDDCSN CLK SDI SDO µC TxD CAN RxD CAN INT CSN CLK SDO SDI TxD CAN RxD CAN VCC1 VCC1 WK1 VS Reset INT RO GND VS LOGIC State Machine VBAT VBAT VS TLE9261 WK2 ADC_xVbat_uC ≥10k ≥10n Vbat_uC R16 R17 max. 500uA ISO Pulse protection Note: Max. WK1 input current limited to 500µA to ensure accuracy and proper operation ;

Datasheet 157 Rev. 1.1 2019-09-27 TLE9261BQXV33 Figure 55 Hint for Increasing th e Robustness of pin FO3/TEST during Debugging or Programming FO3/ TEST 5V_int RTEST SBC Init Mode Failure Logic T test T FO_PL Connector/ Jumper REXT

Datasheet 158 Rev. 1.1 2019-09-27 TLE9261BQXV33

16.2 ESD Tests

Note: Tests for ESD robust ness according to IEC61000-4-2 “gun test” (150pF, 330Ω) has been performed. The results and test conditions are available in a test report. The target values for the test are listed in Table 30 below. EMC and ESD susceptibility tests according to SAE J2 962-2 (2010) have been performed. Tested by external test house (UL LLC). Table 30 ESD “Gun Test” Performed Test Result Unit Remarks ESD at pin CANH, CANL, VS, WK1..3, HSx, VCC2, VCC3 versus GND >6 kV 1)2)positive pulse 1) ESD Test “Gun Test” is specified with external components for pins VS, WK1..3, HSx, VCC3 and VCC2. See the application diagram in Chapter 16.1 for more information. 2) ESD susceptibility “ESD GUN” according LIN EMC 1.3 Test Specification, Section 4.3 (IEC 61000-4-2). Tested by external test house (IBEE Zwickau, EMC Test report Nr. 04-01-17) ESD at pin CANH, CANL, VS, WK1..3, HSx, VCC2, VCC3 versus GND < -6 kV 1)2)negative pulse

Datasheet 159 Rev. 1.1 2019-09-27 TLE9261BQXV33

16.3 Thermal Behavior of Package

Below figure shows the thermal resistance (Rth_JA) of the device vs. the cooling area on the bottom of the PCB for Ta = 85°C. Every line reflects a different PCB and thermal via design. Figure 56 Thermal Resistance ( Rth_JA) vs. Cooling Area

Datasheet 160 Rev. 1.1 2019-09-27 TLE9261BQXV33 Board setup is defined according to JESD 51-2,-5,-7. Board: 76.2x114.3x1.5mm3 with 2 inner copper layers (35µm thick), with thermal via array under the exposed pad contacting the first inner copper layer and 300mm2 cooling area on the bottom layer (70µm). PCB (top view) PCB (bottom view) Detail SolderArea 1,5 mm 1,5 mm 70µm modelled (traces) 35µm, 90% metalization* 35µm, 90% metalization* 70µm / 5% metalization + cooling area *: means percentual Cu metalization on each layer Cross Section (JEDEC 1s0p) with Cooling AreaCross Section (JEDEC 2s2p) with Cooling Area

Datasheet 161 Rev. 1.1 2019-09-27 TLE9261BQXV33 Package Outlines Figure 58 PG-VQFN-48-31 Note: Dimensions in mm. The tie bars have an internal connection to the exposed pad. For assembly recommendations please also refer to the documents "Recommendations for Board Assembly (VQFN and IQFN)" and "VQFN48 Layout Hints" on the Infineon website (www.infineon.com). The PG-VQFN-48-31 package is a leadless exposed pad po wer package featuring Lead Tip Inspection (LTI) to support Automatic Optical Inspection (AOI). Green Product (RoHS compliant) To meet the world-wide customer requirements for en vironmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). PG-VQFN-48-29, -31-PO V03 7±0.1 A6.8 7±0.1 B 11 x 0.5 = 5.5 0.5 0.5±0.07 0.1±0.05 0.15±0.05 (6) (5.2) 0.9 MAX. (0.65) +0.03 48x 0.08 (0.2) 0.05 MAX.C (5.2) (6) 0.1±0.03 ±0.050.23 M 48x

0.1 A B C

1) Vertical burr 0.03 max., all sides 2) This four metal areas have exposed diepad potential Index Marking SEATING PLANE Index Marking 6.8 12 1 25 36 (0.35) 0.4 x 45° For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Dimensions in mm

Datasheet 162 Rev. 1.1 2019-09-27 TLE9261BQXV33

Revision History

Rev. 1.1 2019-09-27 Datasheet updated:

Editorial changes
Updated Table 4 – corrected footnote 9) to match P_4.4.33, i.e changed 525µA to 550µA
Chapter 5.1.4 “SBC Sleep Mode”: added condition for CAN mode handling before SBC Sleep Mode entry
Figure 3 “State Diagram ...”: added footnote with condition for CAN mode handling before SBC Sleep Mode entry
Figure 26 “CAN Mode Control Diagram”: added Footnote 2) with condition for CAN mode handling before SBC Sleep Mode entry
Updated Table 17 – added P_10.3.57 and P_10.3.58 (no product change) – tightened P_10.3.16 – tightened P_10.3.39 and P_10. 3.40 by additional footnote
Figure 10.2.4 “CAN Wake Capable Mode”, rearming the transceiver for wake capability: added condition for CAN mode handling before SBC Sleep Mode entry Rev. 1.0 2017-07-31 Initial Release

© 2020 Infineon Technologies AG. All Rights Reserved. Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2019-09-27 Published by Infineon Technologies AG

81726 Munich, Germany

Do you have a question about any aspect of this document? Email: erratum@infineon.com Document reference Z8F68436601 IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer's comp liance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer's products and any use of the product of Infineon Technologies in customer's applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer's technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.

Product Information

TLE9261BQXV33 specifications and overview.

Summary

System Basis Chip Rev. 1.1 2019-09-27

Description

System Basis Chip Rev. 1.1 2019-09-27

Source title TLE9261BQXV33 Datasheet(PDF) - Infineon Technologies AG

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