TLE6368

TLE6368_06 INFINEON | Alldatasheet

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Multi-Voltage Processor Power Supply Data Sheet 1 Rev. 2.2, 2006-12-01 TLE 6368 / SONIC 1O v e r v i e w

1.1 Features

• High efficiency regulator system
• Wide input voltage range from 5.5V to 60V
• Stand-by mode with low current consumption
• Suitable for sta ndard 12V/24V and 42V PowerNets
• Step down converte r as pre-regulator: 5.5V / 1.5A
• Step down slope cont rol for lowest EME
• Switching loss minimization
• Three high current linea r post-regulators with selectable output voltages: 5V / 800mA 3.3V or 2.6V / 500mA 3.3V or 2.6V / 350mA
• Six independent voltage trackers (followers): 5V / 17mA each
• Stand-by regulator with 1mA current capability
• Three independent undervo ltage detection circuits (e.g. reset, early warning) for each linear post-regulator
• Power on reset functionality
• Tracker control and diagnosis by SPI
• All outputs protected against short-circuit
• Power PG-DSO-36-26 package
• Green (RoHS compliant) version of TLE 6368 G1
• AEC qualified SMD = Surface Mounted Device Type Package TLE 6368 G1 / SONIC PG-DSO-36-26 (RoHS compliant)

Data Sheet 2 Rev. 2.2, 2006-12-01

1.2 Short functional description

The TLE 6368 G1 / SONIC is a multi voltage power supply system especially designed for automotive applications using a standard 12V / 24V batte ry as well as the new 42V powernet. The device is intended to supply 32 bit micro-controller systems which require different supply voltage rails such as 5V, 3.3V and 2. 6V. The regulato rs for external sensors are also provided. The TLE 6368 G1 / SONIC cascades a Buck converter block with a linear regulator and tracker block on a single ch ip to achieve lowe st power dissipation thus being able to power the application even at very high ambient temperatures. The step-down converter delivers a pre-regu lated voltage of 5.5V with a minimum current capability of 1.5A. Supplied by this step down converter three low drop linear post-regulators offer 5V, 3.3V, or 2.6V of output voltages de pending on the configuration of the device with current capabilities of 800mA, 500mA and 350mA. In addition the inputs of six voltage trackers are connected to the 5.5V bus voltage. Their outputs follow the main 5V linear regulator (Q_LDO1) with high accuracy and are able to drive a current of 17mA each. The trackers can be turned on and off individually by a 16 bit serial peripheral interface (SPI). Through this interface also the status information of each tracker (i.e. short circuit) can be read out. To monitor the output voltage levels of each of the linear regulators three independent undervoltage detection circuits are available which can be used to implement the reset or an early warning function . The supervision of the µC can be managed by the SPI- triggered window watchdog. For energy saving reasons while the motor is turned off, the TLE 6368 G1 / SONIC offers a stand-by mode, where the qui escent current does not e xceed 30µA. In this stand-by mode just the stand-by regulator remains active. The TLE 6368 G1 / SONIC is based on Infineon Power technology SPT  which allows bipolar , CMOS and Po wer DMOS circuitry to be inte grated on the same monolithic circuitry.

Data Sheet 3 Rev. 2.2, 2006-12-01

1.3 Pin configuration

Figure 1 Pin Configuration (Top View), bottom heat slug and GND corner pins are connected WAKE Bootstrap SEL Q_LDO2 Q_LDO1 CLK GND CS ERR Q_T2 GND Q_T3 Q_T4 Q_T5 Q_T6 GND IN BOOST SLEW SW FB/L_IN CCP GND IN SW FB/L_IN DO DI Q_STB Q_T1 Q_LDO3 4 33 8 29 13 24 17 20 TLE 6368 PG-DSO-36-

Data Sheet 4 Rev. 2.2, 2006-12-01

1.4 Pin definitions and functions

Pin No. Symbol Function 1,18,19, GND Ground; to reduce thermal resistance place cooling areas on PCB close to these pins. The GND pins are connected internally to the heat slug at the bottom. 2C L K SPI Interface Clock input; clocks the shift register; CLK has an internal active pull down and requires CMOS logic level inputs;see also chapter SPI 3C S SPI Interface chip select input; CS is an active low input; serial communication is enabled by pulling the CS terminal low; CS input should only be switched when CLK is low; CS has an internal active pull up and requires CMOS logic level inputs ;see also chapter SPI 4D I SPI Interface Data input; receives serial data from the control device; serial data transmitted to DI is a 16 bit control word with the Least Significant Bit (LSB) being transferred first; the input has an active pull down and requires CMOS logic level inputs; DI will accept data on the falling edge of CLK-signal; see also chapter SPI 5D O SPI Interface Data output; this tristate output transfers diagnosis data to the controlling device; the output will remain 3- stated unless the device is selected by a low on Chip-Select CS; see also the chapter SPI 6E R R Error output; push-pull output. Monitors failures in parallel to the SPI diagnosis word, reset via SPI. ERR is an active low, latched output. 7Q _ S T B Standby Regulator Output; the output is active even when the buck regulator and all other circuitry is in off mode

8 Q_T1 Voltage Tracker Output T1 tracked to Q_LDO1; bypass with a

1µF ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed.

9 Q_T2 Voltage Tracker Output T2 tracked to Q_LDO1; bypass with a

1µF ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed.

10 Q_T3 Voltage Tracker Output T3 tracked to Q_LDO1; bypass with a

1µF ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed.

Data Sheet 5 Rev. 2.2, 2006-12-01

11 Q_T4 Voltage Tracker Output T4 tracked to Q_LDO1; bypass with a

1µF ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed.

12 Q_T5 Voltage Tracker Output T5 tracked to Q_LDO1; bypass with a

1µF ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed.

13 Q_T6 Voltage Tracker Output T6 tracked to Q_LDO1; bypass with a

1µF ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed. 14 Q_LDO3 Voltage Regulator Output 3; 3.3V or 2.6V output; output voltage is selected by pin SEL (see also 2.2.2); For stability a ceramic capacitor of 470nF to GND is sufficient.

15 R3 Reset output 3, undervoltage detection for output Q_LDO3;

open drain output; an external pullup resistor of 10kΩ is required

16 R2 Reset output 2, undervoltage detection for output Q_LDO2;

open drain output; an external pullup resistor of 10kΩ is required

17 R1 Reset output 1, undervoltage detection for output Q_LDO1 and

watchdog failure reset; open drain output ; an external pullup resistor of 10kΩ is required

20 C- Charge pump capacitor connection; Add the fly-capacitor of

21 C+ Charge pump capacitor connection; Add the fly-capacitor of

22 CCP Charge Pump Storage Capacitor Output; Add the storage

capacitor of 220nF between pin CCP and GND.

23 SEL Select Pin for output voltage adjust of Q_LDO2 and Q_LDO3

(see also 2.2.2) 24 Q_LDO2 Voltage Regulator Output 2; 3.3V or 2.6V output; output voltage is selected by pin SEL (see also 2.2.2); For stability a ceramic capacitor of 470nF to GND is sufficient. 25, 26 FB/L_IN Feedback and Linear Regulator Input; input connection for the Buck converter output

1.4 Pin definitions and functions (cont’d)

Pin No. Symbol Function

Data Sheet 6 Rev. 2.2, 2006-12-01

27 Q_LDO1 Voltag e Regulator Output 1; 5V output; acts as the reference

for the voltage trackers.The SPI and window watchdog logic is supplied from this voltage. For stability a ceramic capacitor of 470nF to GND is sufficient.

28 Bootstrap Bootstrap Input; add the bootstrap capacitor between pin SW

and pin Bootstrap, the capcitance value should be 2% of the Buck converter output capacitance 29, 31 SW Switch Output; connect both pins externally through short lines directly to the cathode of the catch diode and the Buck circuit inductance. 30, 32 IN Supply Voltage Input; connect both pins externally through short lines to the input filter/the input capacitors.

33 BOOST Boost Input; for switching loss minimization connect a diode

(cathode directly to boost pin) in series with a 100nF ceramic capacitor to the IN pin and from the anode of the diode to the buck converter output a 22Ω resistor. Recommended for 42V applications. In 12/24V applications connect boost directly to IN.

34 WAKE Wake Up Input; a positive voltage applied to this pin turns on

35 SLEW Slew control Input; a resistor to GND defines the current slope

in the buck switch for reduced EME Pin No. Symbol Function

Data Sheet 7 Rev. 2.2, 2006-12-01

1.5 Basic block diagram

Reg. 1 Linear Reg. 2 Tracker Reset Logic Window Watchdog SPI 16 bit µ-controller / memory supply Sensor supplies (off board supplies) Power Down Logic Tracker Tracker Tracker Tracker Tracker TLE 6368 Standby Regulator OSZ PWM Driver Error- Amplifier Internal Referencefeedback ref ref ref ref ref ref Protection BUCK REGULATOR Boost IN Slew Wake CLK CS DI DO ERR GND Q_STB SW Bootstrap FB/L_IN CCP SEL Q_LDO1 Q_LDO2 Q_LDO3 Q_T1 Q_T2 Q_T3 Q_T4 Q_T5 Q_T6 Charge Pump Linear Reg. 3

Data Sheet 8 Rev. 2.2, 2006-12-01

2 Detailed circuit description

In the following major buck regu lator blocks, the linear voltage regulators and trackers, the undervoltage reset function, the watchdog and the SPI are described in more detail. For applications information e.g. choice of external components, please refer to section

2.1 Buck Regulator

The diagram below shows the internal implemented circuit of the Buck converter, i. e. the internal DMOS devices, the regulation loop and the other major blocks. Figure 3 Detailed Buck regulator diagram The 1.5A Buck regulator consists of two internal DMOS power stages including a current mode regulation scheme to avoid external compensation components plus additional blocks for low EME and reduced switching loss. Figure 3 indicates also the principle how Int. voltage regulator Int. charge pump Zero cross detection Divider Oscillator 1.4MHz Slope logic under- voltage lockout Gate driver Delay unit 5V 14V 150µA Vref=6V Voltage feedback amplifier Current sense amplifier Current comparator PWM logic Gate off signal from overtemp or sleep command Trigger for gate on Trigger for gate off Slope compensation Lowpass Lowpass switching frequency 330kHz Slope control from current sensing to current sense amplifier FB/L_IN C+ CCP SLEW SWBOOT- STRAP BOOST SW IN IN external components Main switch ON/OFF Slope switch charge signal Slope switch discharge signal 8 to 10V Main DMOS Slope DMOS pins

Data Sheet 9 Rev. 2.2, 2006-12-01 the gate driver supply is managed by the combination of internal charge pump, external charge pump and bootstrap capacitor.

2.1.1 Current mode control scheme

The regulation loop is located at the left lower corner in the schematic, there you find the voltage feedback amplifier which gives the actual information of the actual output voltage level and the current sense ampl ifier for the load current information to form finally the regulation signal. To avoid subharmonic oscillations at duty cycles higher than 50% the slope compensation block is necessary. The control signal formed out of those three blocks is fi nally the input of the PWM regulator for the DMOS gate turn off command, which means this signal determines the duty cycle. The gate turn on si gnal is set by the oscillator periodically every 3µs which leads to a Buck converter switching frequency around 330kHz. With decreasing input voltage the device changes to the so called pulse skipping mode which means basically that some of the oscillator gate turn off signals are ignored. When the input voltage is still reduced the DMOS is turned on statically (100% duty cycle) and its gate is supplied by the internal charge pump. Below typical 4.5V at the feedback pin the device is turned off.During normal switching operation the gate driver is supplied by the bootstrap capacitor.

2.1.2 Start-up procedure

To guarantee a device startup even under full load condition at the linear regulator outputs a special start up proc edure is implemented. At fi rst the bootstrap capacitor is charged by the internal charge pump. Afterwards the output capacitor is charged where the driver supply in that case is maintain ed only by the bootstrap capacitor. Once the output capacitor of the buck converter is charged the external charge pump is activated being able to supply the linear regulators and finally the linear regulators are released to supply the loads.

2.1.3 Reduction of elec tromagnetic emission

In figure 3 it is recognized that two internal DMOS switches are used, a main switch and an auxiliary switch. The second implemented switch is used to adjust the current slope of the switching current. The slope adjustment is done by a controlled charge and discharge of the gate of this DMOS. By choosing the external resistor on the SLEW pin appropriate the current transition time can be adjusted between 20ns and 100ns.

2.1.4 Reducing the switching losses

The second purpose of the slope DMOS is to minimise the switching losses. Once being in freewheeling mode of the buck regulator the output voltage level is sufficient to force the load current to flow, the input voltage level is not needed in the first moment. By a feedback network consisting of a resistor and a diode to the bo ost pin (connection see

Data Sheet 10 Rev. 2.2, 2006-12-01 section 5) the output voltage level is presen t at the drain of the switch. As soon as the voltage at the SW pin passes zero volts the handover to the main switch occurs and the traditional switching behaviour of the Buck switch can be observed.

2.2 Linear Voltage Regulators

The Linear regulators offer, depending on the version, voltage rails of 5V, 3.3V and 2.6V which can be determined by a hardware connection (see table at 2.2.2) for proper power up procedure. Being supplied by the output of the Buck pre-regulator the power loss within the three linear regulators is minimized. All voltage regulators are short circuit protected which means that each regulator provides a maximum current a ccording to its current limit when shorted. Together with the external charge pump the NPN pass elements of th e regulators allow low dropout voltage operation. By using this structure the linear regulators work st able even with a minimum of 470nF ceramic capacitors at their output. Q_LDO1 has 5V nominal outp ut voltage, Q_LDO2 ha s a hardware programmable output voltage of 3.3V or 2.6V and Q_LDO3 is also programmable to 3.3V or 2.6V (see section 2.2.2). All three regula tors are on all the time, if one regulator is not needed a base load resistor in parall el to the output capacitance for contro lled power down is recommended.

2.2.1 Startup Sequence Linear Regulators

When acting as a 32 bit µC supply the so-called power sequencing (the dependency of the different voltage rails to each other) is important. Within the TLE 6368 G1 / SONIC, the following Startup-Sequence is defined (see also figure 4): VQ_LDO2 ≤ VQ_LDO1; VQ_LDO3 ≤ VQ_LDO1 with VQ_LDO1=5V, VQ_LDO2 = 2.6V or 3.3V and VQ_LDO3 = 2.6V or 3.3V The power sequencing refers to the regulator itself, ex ternally voltages applied at Q_LDO2 and Q_LDO3 are not pu lled down actively by the device if Q_LDO1 is lower than those outputs. That means for the power down sequencing if different outp ut capacitors and different loads at the three outputs of the linear regulators are used the voltages at Q_LDO2 and Q_LDO3 might be higher than at Q_LDO1 due to slower discharging. To avoid this behaviour three Schottky diodes have to be connected between the three outputs of the linear regulators in that way that the cathodes of the diodes are always connected to the higher nominal rail.

Data Sheet 11 Rev. 2.2, 2006-12-01 Figure 4 Power-up and -down sequencing of the regulators

2.2.2 Q_LDO2 and Q_LDO3 output voltage selection*

To determine the output voltage levels of th e three linear regulato rs, the selection pin (SEL, pin 23) has to be connected according to the matrix given in the table below. * for different output voltages please refer to the multi voltage supply TLE6361 Definition of Output voltage Q_LDO2 and Q_LDO3 Select Pin SEL connected to Q_LDO2 output voltage Q_LDO3 output voltage GND 3.3 V 3.3 V Q_LDO1 2.6 V 2.6 V Q_LDO2 2.6 V 3.3 V VLDO_EN t VFB/L_IN Power Sequencing 0.7V 3.3V 2.6V VRth5 t 2.6V VRth2.6 t 0.7V VQ_LDO1 +/- 50mV VQ_LDO3 (3.3V Mode) 3.3V VRth3.3 t +/- 50mV VQ_LDO2 (2.6V Mode) 5V LDO 5V LDO 5V LDO 5V LDO

Data Sheet 12 Rev. 2.2, 2006-12-01

2.3 Voltage Trackers

For off board supplies i.e. sensors six voltage trackers Q_T1 to Q_T6 with 17mA output current capability each are available. The output voltages match Q_LDO1 within +5 / -15mV. They can be individually turned on and off by the appropriate SPI command word sent by the microcontroller. A ceramic capacitor with the value of 1µF at the output of each tracker is sufficient for stable operation without oscillation. The tracker outputs can be connected in par allel to obtain a hi gher output current capability, no matter if only two or up to al l six trackers are tied together. For uniformly distributed current density in each tracker internal bala nce resistors at each output are foreseen internally. By connecting two sets of three trackers in parallel two sensors with more than 50mA each can be supplied, all six in parallel give more than 100mA. The tracker outputs can withstand short circuits to GND or battery in a range from -4 to +40V. A short circuit to GND is detected and indicated individually for each tracker in the SPI status word. Also an open load conditi on might be recognise d and indicated as a failure condition in th e SPI status word. A minimum load current of 2mA is required to avoid open load failure indica tion. In case of connecting several trackers to a common branch balancing currents can prevent proper operation of the failure indication.

2.4 Standby Regulator

The standby regulator is an ultra low power 2.5V linear voltage regulator with 1mA output current which is on all the time. It is intended to supply the microcontroller in stop mode and requires then only a minimum of quie scent current (<30µA) to extend the battery lifetime.

2.5 Charge Pump

The 1.6 MHz charge pump with the two external capacitors will serve to supply the base of the NPN linear regulators Q_LDO1 and Q_LDO3 as well as the gate of the Buck DMOS transistor in 100% duty cycle operation at low battery condition. The charge pump voltage in the range of 8 to 10V can be measured at pin 22 (CCP) but is not intended to be used as a supply for additional circuitry.

2.6 Power On Reset

A power on reset is available for each linear voltage regulator output. The reset output lines R1, R2 and R3 are active (low) during start up and turn inactive with a reset delay time after Q_LDO1, Q_LDO2 and Q_LDO3 have reached their reset threshold. The reset outputs are open drain, three pull up resistors of 10kΩ each have to be connected to the I/O rail (e.g. Q_LDO1) of the µC. All three reset outputs can be linked in parallel to obtain a wired-OR. The reset delay time is 8 ms by default and can be set to higher values as 16 ms, 32 ms or 64 ms by SPI command. At each power up of the device in case the output voltage at

Data Sheet 13 Rev. 2.2, 2006-12-01 Q_LDO1 had decreased below 3. 3V (max.), the SPI will re set to the default settings including the 8ms delay time. If the voltage on Q_LDO1 during sleep or power off mode was kept above 3.3V the delay time set by the last SPI command is valid. Figure 5 Undervoltage reset timing

2.7 RAM good flag

A RAM good flag will be set within the SPI status word when the Q_LDO1 voltage drops below 2.3V. A second one will be set if Q_LDO2 drops below typical 1.4V. Both RAM good flags can be read after power up to determine if a co ld or warm start needs to be processed. Both RAM good flags will be reset after each SPI cycle.

2.8 ERR Pin

A hardware error pin indicates any fault conditions on the chip. It should be connected to an interrupt input of the microcontroller. A low signal indicates an error condition. The microcontroller can read the root cause of the error by reading the SPI register.

2.9 Window Watchdog

The on board window watchdog for supervision of the µC works in combination with the SPI. The window watc hdog logic is turned of f per default and can be activated by one special bit combination in the SPI command word. W hen operating, the window watchdog is triggered when CS is low and Bit WD-Trig in the SPI command word is set to “1”. The watchdog trigger is recognized with the low to high transition of the CS signal. To allow reading the SPI at any time without getting a reset due to misinterpretation the WD-Trig bit has to be set to “0” to avoid false trigger conditions. VFB/L_IN t VQ_LDOx t VRx t VRTH,Q_LDOx tRES trr < trr thermal shutdown under voltage over load tRES tRES tRES

Data Sheet 16 Rev. 2.2, 2006-12-01 the closed window (CW) starts. Then three valid watchdog triggers are shown, no effect on the reset line and/or error pin is observ ed. With the missing watchdog trigger signal the error signal turns low immediately where the reset is asserted after another delay of half the closed window time. Also shown in the figure are two typical fa ilure modes, one pretrigger and one missing signal. In both cases the error signal will go low immediately the failure is detected with the reset following after the half closed window time.

2.10 Overtemperature Protection

At a chip temperature of more than 150° an error and temperature flag is set and can be read through the SPI. The device is switched off if the device reaches the overtemperature threshold of 170°C. The overtemperature shutdown has a hysteresis to avoid thermal pumping.

2.11 Power Down Mode

The TLE 6368 G1 / SONIC is started by a static high signal at the wake input or a high pulse with a minimum of 50µs duration at the Wake input (pin 34). Voltages in the range between the turn on and turn off thresholds for a few 100µs must be avoided! By SPI command (“Sleep”-bit, D8, equals zero) al l voltage regulators including the switching regulator except the standby regulator can be turned off completely only if the wake input is low. In the ca se the Wake input is permanent ly connected to battery the device cannot be turned off by SPI command, it will always turn on again. For stable “on” operation of the device the “Sleep”-bit, D8 has to be set to high at each SPI cycle! When powering the device again after power down the st atus of the SPI controlled devices (e.g. trackers, watchdog etc.) depen ds on the output vo ltage on Q_LDO1. Did the voltage at Q_LDO1 decrease below 3.3V the default status (given in the next section) is set otherwise the last SPI command defines the status.

2.12 Serial Peripheral Interface

A standard 16 bit SPI is available for control and diagnostics. It is capable to operate in a daisy chain. It can be written or read by a 16 bit SPI interface as well as by an 8 bit SPI interface. The 16-bit control word (write bit assignment, see Figure 8) is read in via the data input DI, synchronous to the clock input CLK supplied by the µC beginning with the LSB D0. The diagnosis word appears in the same way synchronously at the data output DO (read bit assignment, see figure 9), so with the first bit shifted on the DI line the first bit appears on the DO line. The transmission cycle begins when the TLE 6368 G1 / SONIC is selected by the “not chip select” input CS (H to L). After the CS input returns from L to H, the word that has

Data Sheet 17 Rev. 2.2, 2006-12-01 been read in at the DI line becomes the ne w control word. The DO output switches to tristate status at this point, thereby releasing the DO bus circuit for other uses. For details of the SPI timing please refer to Figures 10 to 13. The SPI will be reset to default values given in the following table “write bit meaning” if the RAM good flag of Q_LDO1 indicates a cold start (lower output voltage than 3.3V). The reset will be active as long as the power on reset is present so during the reset delay time at power up no SPI commands are accepted. The register content of the SPI - including watchdog timings and reset delay timings - is maintained if the RAM good flag of Q_LDO1 indicates a warm start (i.e. Q_LDO1 did not decrease below 3.3V).

2.12.1 Write mode

The following tables show the bit assignment to the differe nt control functions, how to change settings with the right bit combination and also the default status at power up.

2.12.2 Write mode bit assignment

Figure 8 Write Bit assignment Write Bit meaning Function Bit Combination Default Not assigned D1 X X Tracker 1 to 6 - control: turn on/off the individual trackers 0: OFF 1: ON Power down: send device to sleep D8 0: SLEEP 1: NORMAL WD_ OFF1 T6- control T5- control T4- control T6- control T2- control T1- control NOT assigned sleep WD_ TRIG WD_ OFF3WD2WD1reset 2reset 1WD_ OFF2 1 111111X 1 0100110 BIT Default Name D 15D8 D9 D10 D11 D12 D13 D14D7DO D1 D2 D3 D4 D5 D6

Data Sheet 18 Rev. 2.2, 2006-12-01

2.12.3 Read mode

Below the status information word and the bit assignments for diagnosis are shown.

2.12.3.1 Read mode bit assignment

Figure 9 Read Bit assignment Error bit D0: The error output ERR is low and the error bi t indicates fail functi on if the temperature prewarning or the watchdog error is active, further if one RAM good indicates a cold start or if a voltage tracker does not settle within 1ms when it is turned on. Reset timing: Reset delay time tRES valid at warm start D10D11 00: 64ms 10: 32ms 01: 16ms 11: 8ms Window watchdog timing: Open window time tOW and closed window time tCW valid at warm start D12D13 00: 128ms 10: 64ms 01: 32ms 11: 16ms Window watchdog function: Enable /disable window watchdog D0D9D14 010: ON 1xx: OFF x0x: OFF xx1: OFF 101 Window watchdog trigger: Enable / disable window watchdog trigger D15 0: not triggered 1: triggered Write Bit meaning Function Bit Combi nation Default ERROR T6- status T5- status T4- status T3- status T2- status T1- status temp_ warn RAM Good 1 DC/DC status WD ErrorR-Error3R-Error2R-Error1WD Window RAM Good 2 0 1111110 0 1000000 BIT Default Name D 15D8 D9 D10 D11 D12 D13 D14D7DO D1 D2 D3 D4 D5 D6

Data Sheet 19 Rev. 2.2, 2006-12-01 Read Bit meaning Function Type Bit Combination Default Error indication, explanation see below this table Latched D0 0: normal operation 1: fail function Overtemperature warning Not latched D1 0: normal operation 1: prewarning Status of Tracker Output Q_T[1:6],only if output is ON Not latched D2 1: settled output voltage 0:Tracker turned off or shorted output. Also open load may possibly be indicated as 0. Indication of cold start/ warm start, Q_LDO1 Latched D8 0: cold start 1: warm start Indication of cold start/ warm start, Q_LDO2 Latched D9 0: cold start 1: warm start Indication for open or closed window Not latched D10 0 : open window 1: closed window Reset condition at output Q_LDO1 Not latched D11 0: normal operation 1: Reset R1 Reset condition at output Q_LDO2 Not latched D12 0: normal operation 1: Reset R2 Reset condition at output Q_LDO3 Not latched D13 0: normal operation 1: Reset R3 Watchdog Error Latched D14 0: normal operation 1: WD error DC/DC converter status Not latched D15 0: off 1: on 1) Min. load current to avoid ’0’ signal caused by open load is 2mA.

Data Sheet 20 Rev. 2.2, 2006-12-01

2.12.4 SPI Timings

Figure 10 SPI Data Transfer Timing DI CLK CS DO Data Out (N-1) Data In (N) DI: Data will be accepted on the falling edge of CLK-Signal DO: State will change on the rising edge of CLK-Signal time Data In (N+1) Data Out (N) Tracker- control Setting (N)Setting (N-1) D1D0 151413321 D1D0 D15D14D13D2 D3 D15D14D13D3D2D1 D1 CS High to Low & rising edge of CLK: DO is enabled. Status information is transferred to Output Shift Register CS Low to High: Data from Register are transferred to e.g. Trackers e.g. Status (N)Status (N-1) e.g. Tracker- status

Data Sheet 21 Rev. 2.2, 2006-12-01 Figure 11 SPI-Input Timing Figure 12 DO Valid Data Delay Time and Valid Time CLK

0.7 VQ_LDO1

0.2 VQ_LDO1

50% DO 90% 10% DO 90% 10% (low to high) (high to low) trIN tfIN <10ns trDO tfDO tVADO

Data Sheet 22 Rev. 2.2, 2006-12-01 Figure 13 DO Enable and Disable Time CS 50% DO DO tfIN trIN <10ns tENDO tDISDO 50% 50% 10kΩ Pullup to VQ_LDO1 10kΩ Pulldown to GND

Data Sheet 23 Rev. 2.2, 2006-12-01

3 Characteristics

3.1 Absolute Maximum Ratings

Item Parameter Symbol Limit Values Unit Test Condition Min. Max.

3.1.1 Supply Voltage Input IN

Voltage VIN -0.5 60 V – Voltage VIN -1.0 60 V Tj = -40 °C Current IIN –– –

3.1.2 Buck-Switch Output SW

Voltage VSW -2 V S+0.5 V – Current ISW –– –

3.1.3 Feedback and Linear Voltage Regulator Input

Voltage VFB/L_IN -0.5 8 V – Current IFB/L_IN –– –

3.1.4 Bootstrap Connector Bootstrap

0.5V VSW+ 10V V Voltage VBootstrap -0.5 70 V Current IBootstrap –– – Internally limited

3.1.5 Boost Input

Voltage VBoost -0.5 60 V – Current IBoost –– – Internally limited

3.1.6 Slope Control Input Slew

Voltage VSlew -0.5 6 V – Current ISlew –– – Internally limited

3.1.7 Charge Pump Capacitor Connector C-

Voltage VCL -0.5 V FB/L_IN +0.5 V Current ICL -150 +150 mA

Data Sheet 24 Rev. 2.2, 2006-12-01

3.1.8 Charge Pump Capacitor Connector C+

Voltage VCH -0.5 13 V Current ICH -150 +150 mA

3.1.9 Charge Pump Storage Capacitor CCP

Voltage VCCP -0.5 12 V Current ICCP -150 – mA

3.1.10 Standby Voltage Regulator output Q_STB

Voltage VQ_Stb -0.5 6 V – Current IQ_Stb –– – Internally limited

3.1.11 Voltage Regulator output voltage Q_LDO1

Voltage VQ_LDO1 -0.5 6 V – Current IQ_LDO1 –– – Internally limited

3.1.12 Voltage Regulator output voltage Q_LDO2

Voltage VQ_LDO2 -0.5 6 V – Current IQ_LDO2 –– – Internally limited

3.1.13 Voltage Regulator output voltage Q_LDO3

Voltage VQ_LDO3 -0.5 6 V – Current IQ_LDO3 –– – Internally limited

3.1.14 Voltage Tracker output voltage Q_T1

Voltage VQ_T1 -4 40 V – Current IQ_T1 –– mA Internally limited

3.1.15 Voltage Tracker output voltage Q_T2

Voltage VQ_T2 -4 40 V – Current IQ_T2 –– mA Internally limited

3.1.16 Voltage Tracker output voltage Q_T3

Voltage VQ_T3 -4 40 V – Current IQ_T3 –– mA Internally limited

3.1.17 Voltage Tracker output voltage Q_T4

Voltage VQ_T4 -4 40 V – Current IQ_T4 –– mA Internally limited

Data Sheet 25 Rev. 2.2, 2006-12-01

3.1.18 Voltage Tracker output voltage Q_T5

Voltage VQ_T5 -4 40 V – Current IQ_T5 –– mA Internally limited

3.1.19 Voltage Tracker output voltage Q_T6

Voltage VQ_T6 -4 40 V – Current IQ_T6 –– mA Internally limited 3.1.20Select Input SEL Voltage VSEL -0.5 6 V – Current ISEL –– – Internally limited 3.1.21Wake Up Input Wake Voltage VWake -0.5 60 V – Current IWake –– – 3.1.22Reset Output R1 Voltage VR1 -0.5 6 V – Current IR1 –– – 3.1.23Reset Output R2 Voltage VR2 -0.5 6 V – Current IR2 –– – 3.1.24Reset Output R3 Voltage VR3 -0.5 6 V – Current IR3 –– – 3.1.25SPI Data Input DI Voltage VDI -0.5 6 V – Current IDI –– – 3.1.26SPI Data Output DO Voltage VDO -0.5 6 V – Current IDO –– – Internally limited 3.1.27SPI Clock Input CLK Voltage VCLK -0.5 6 V – Current ICLK –– –

Data Sheet 26 Rev. 2.2, 2006-12-01 1) Package mounted on FR4 47x50x1.5mm3; 70µ Cu, zero airflow Note: Maximum ratings are abso lute ratings; exceeding an y one of these values may cause irreversible damage to the integrated circuit. 3.1.28SPI Chip Select Not Input CS Voltage VCS -0.5 6 V – Current ICS –– – 3.1.29Error Output Pin Voltage VERR -0.5 6 V – Current IERR –– – Internally limited 3.1.30Thermal Resistance Junction- ambient Rthja 37 K/W 1)PCB heat sink area 300mm2 Junction- ambient Rthja 29 K/W 1)PCB heat sink area 600mm2 Junction- case Rthjc – 2 K / W 3.1.31Temperature Junction temperature Tj -40 150 °C Junction temperature transient T jt 175 °C lifetime=TBD Storage temperature Tstg -50 150 °C 3.1.32ESD ESD V ESD -1 1 kV HBM-Model

Data Sheet 27 Rev. 2.2, 2006-12-01

3.2 Functional Range

Note: Within the functional range the IC can be operated . The electrical characteristics, however, are not guaranteed over this full functional range. Item Parameter Symbol Limit Values Unit Condition min. max. Supply Voltage VIN, min 5.5 V V IN increased from 0V; VWAKE =5V; IQ_LDO1=400mA; IQ_LDO2=200mA Supply Voltage VIN, max 60 V Ripple at FB/L_IN VFB/L_IN ripple 0 150 mV PP

Data Sheet 28 Rev. 2.2, 2006-12-01

3.3 Recommended Operation Range

Item Parameter Symbol Limit Values Unit Condition min. typ. max. Buck Inductor LB 18 100 µH 1) 1) CB, min needs about LB=47µH to avoid instabilities Buck Capacitor CB 10 µF ESR <0.15 Ω, ceramic capacitor (X7R) recommended1) Bootstrap Capacitor C BTP 2% o f C B SLEW resistor RSLEW 02 0 k Ω Linear regulator capacitors CQ_LDO1-3 470 nF ceramic capacitor (X7R) Tracker bypass capacitors C Q_T1-6 1µ F c e r a m i c capacitor (X7R) SPI rise and fall timings, CS, DI, CLK tr,f 200 ns

Data Sheet 29 Rev. 2.2, 2006-12-01

3.4 Electrical Characteristics

The electrical characteristic s involve the spread of valu es guaranteed within the specified supply voltage and ambient temperature range. Ty pical values represent the median values at room temperature, which are related to production processes. -40 < Tj <150 °C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Values Unit Test Conditions min. typ. max. Buck regulator

3.4.1 Switching

3.4.2 Current

time, min., rising edge tr_I_SW 20 ns R SL=0Ω; 1)

3.4.3 Current

time, max., rising edge t r_I_SW 100 ns R SL=20kΩ; 1)

3.4.4 Current

time, min., falling edge tf_I_SW 20 ns R SL=0Ω; 1)

3.4.5 Current

time, max., falling edge t f_I_SW 100 ns R SL=20kΩ; 1)

3.4.6 Voltage rise /

tf_V_SW 25 ns 1)

3.4.7 Static on

RON 160 m Ω Tj=25°C in static operation

3.4.8 Static on

RON 280 400 m Ω Tj=150°C in static operation

3.4.10 Output

VOUT 5.40 6.05 V I OUT=1.5A VIN=13.5 V

Data Sheet 30 Rev. 2.2, 2006-12-01

3.4.11 Output

VOUT 5.4 6.3 V I OUT=0.1A VIN=13.5 V

3.4.12 Bootstrap

IBTSTR 80 160 220 µA

3.4.13 Bootstrap

(internal charge pump) V BTSTR 10 15 V V FB/L_IN=6.5V, Buck converter off

3.4.14 Bootstrap

lockout, Buck turn on threshold V BTSTR, turn on 59 V

3.4.15 Bootstrap

lockout, hysteresis V BTSTR, turn on - VBTSTR, turn off 2.5 V

3.4.16 External

VCCP 7.9 11.0 V I Q_LDO1 = 800mA, VFB/L_IN=6.0V, CFLY=100nF, CCCP=220nF 3.4.17 Max. Duty Cycle dutymax 95 % Switching operation 3.4.18 Min. Duty Cycle dutymin 0% S t a t i c - o f f operation Voltage Regulator Q_LDO1

3.4.19 Output

VQ1 4.9 5.1 V 100mA < I Q_LDO1 < 800mA

3.4.20 Output

VQ1 5.0 V I Q_LDO1 = 800mA -40 < Tj <150 °C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Va lues Unit Test Conditions min. typ. max.

Data Sheet 31 Rev. 2.2, 2006-12-01

3.4.21 Load

∆VQ_LDO1 40 mV 100mA< I Q_LDO1 <800mA; VFB/L_IN=5.5V

3.4.22 Current limit I Q_LDO1limit 800 1050 1400 mA V Q_LDO1=4V

3.4.23 Ripple

PSRR1 26 40 dB f=330kHz; 1)

3.4.24 Output

CQ_LDO1 470 nF Ceramic type, value for stability Voltage Regulator Q_LDO2

3.4.25 Output

voltage 3.3V VQ_LDO2 3.14 3.46 V 50mA < I Q_LDO2 < 400mA; 3.3V mode

3.4.26 Output

voltage 3.3V VQ_LDO2 3.32 V I Q_LDO2 =400mA; 3.3V mode

3.4.27 Output

voltage 2.6V VQ_LDO2 2.500 2.750 V 50mA < I Q_LDO2 < 400mA; 2.6V mode

3.4.28 Output

voltage 2.6V VQ_LDO2 2.62 V I Q_LDO2 =400mA; 2.6V mode

3.4.29 Output

voltage 2.6V VQ_LDO2 2.50 2.70 V 85mA < I Q_LDO2 < 400mA; 2.6V mode

3.4.30 Load

∆VQ_LDO2 50 mV 50mA< I Q_LDO2 <400mA; V FB/L_IN=5.5V 3.3V mode

3.4.31 Load

∆VQ_LDO2 50 mV 50mA< I Q_LDO2 <400mA; VFB/L_IN=5.5V 2.6V mode 3.4.32 Current limit I Q_LDO2limit 500 650 850 mA V Q_LDO2= 2.8V; 3.3V mode

3.4.33 Current limit I Q_LDO2limit 500 650 850 mA V Q_LDO2= 2V;

2.6V mode -40 < Tj <150 °C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Values Unit Test Conditions min. typ. max.

Data Sheet 32 Rev. 2.2, 2006-12-01

3.4.34 Ripple

PSRR2 26 40 dB f=330kHz; 1)

3.4.35 Output

CQ_LDO2 470 nF Ceramic type, value for stability Voltage Regulator Q_LDO3

3.4.36 Output

voltage 3.3V VQ_LDO3 3.14 3.46 V 20mA < I Q_LDO3 < 300mA; 3.3V mode

3.4.37 Output

voltage 3.3V V Q_LDO3 3.32 V I Q_LDO3 =300mA; 3.3V mode

3.4.38 Output

voltage 2.6V VQ_LDO3 2.500 2.750 V 20mA < I Q_LDO3 < 300mA; 2.6V mode

3.4.39 Output

voltage 2.6V V Q_LDO3 2.625 V I Q_LDO3 =300mA; 2.6V mode

3.4.40 Load

∆VQ_LDO3 30 mV 20mA< I Q_LDO3 <300mA; VFB/L_IN=5.5V 3.3V mode

3.4.41 Load

∆VQ_LDO3 30 mV 20mA< I Q_LDO3 <300mA; V FB/L_IN=5.5V 2.6V mode

3.4.42 Current limit I Q_LDO3

350 500 600 mA V Q_LDO3=2.8V; 3.3V mode

3.4.43 Current limit I Q_LDO3

350 500 600 mA V Q_LDO3=2V; 2.6V mode

3.4.44 Ripple

PSRR3 26 40 dB f=330kHz; 1)

3.4.45 Output

CQ_LDO3 470 nF Ceramic type, value for stability Voltage Tracker Q_T1 -40 < Tj <150 °C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Va lues Unit Test Conditions min. typ. max.

Data Sheet 33 Rev. 2.2, 2006-12-01

3.4.46 Output

Q_T1 -15 -2 5 mV V Q_T1-VQ_LDO1; 1mA < IQ_T1 < 17mA

3.4.47 Output

∆VQ_T1 -10 mV V Q_T1-VQ_LDO1; IQ_T1 = 17mA

3.4.48 Overvoltage

VOVQ_T1 VQ_T1, nom mV I Q_T1 = 0mA; 1)

3.4.49 Undervoltage

VUVQ_T1 VQ_T1- 15mV mV 1)

3.4.50 Current limit I Q_T1 limit 17 30 mA V Q_T1=4V

3.4.51 Ripple

PSRR 26 dB f=330kHz; 1)

3.4.52 Tracker load

CQ_T1 1 µF Ceramic type, minimum for stability Voltage Tracker Q_T2

3.4.53 Output

∆VQ_T2 -15 -2 5 mV V Q_T2-VQ_LDO1; 1mA < IQ_T2 < 17mA

3.4.54 Output

Q_T2 -10 mV V Q_T2-VQ_LDO1; IQ_T2 = 17mA

3.4.55 Overvoltage

VOVQ_T2 VQ_T2, nom mV I Q_T2 = 0mA; 1)

3.4.56 Undervoltage

VUVQ_T2 VQ_T2- 15mV mV 1)

3.4.57 Current limit I Q_T2 limit 17 30 mA V Q_T2=4V

3.4.58 Ripple

PSRR 26 dB f=330kHz; 1) -40 < Tj <150 °C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Values Unit Test Conditions min. typ. max.

Data Sheet 34 Rev. 2.2, 2006-12-01

3.4.59 Tracker load

CQ_T2 1 µF Ceramic type, minimum for stability Voltage Tracker Q_T3

3.4.60 Output

Q_T3 -15 -2 5 mV V Q_T3-VQ_LDO1; 1mA < IQ_T3 < 17mA

3.4.61 Output

Q_T3 -10 mV V Q_T3-VQ_LDO1; IQ_T3 = 17mA

3.4.62 Overvoltage

VOVQ_T3 VQ_T3, nom mV I Q_T3 = 0mA; 1)

3.4.63 Undervoltage

VUVQ_T3 VQ_T3- 15mV mV 1)

3.4.64 Current limit I Q_T3 limit 17 30 mA V Q_T3=4V

3.4.65 Ripple

PSRR 26 dB f=330kHz; 1)

3.4.66 Tracker load

CQ_T3 1 µF Ceramic type, minimum for stability Voltage Tracker Q_T4

3.4.67 Output

∆VQ_T4 -15 -2 5 mV V Q_T4-VQ_LDO1; 1mA < IQ_T4 < 17mA

3.4.68 Output

Q_T4 -8 mV V Q_T4-VQ_LDO1; IQ_T4 = 17mA

3.4.69 Overvoltage

VOVQ_T4 VQ_T4, nom mV I Q_T4 = 0mA; 1) -40 < Tj <150 °C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Va lues Unit Test Conditions min. typ. max.

Data Sheet 35 Rev. 2.2, 2006-12-01

3.4.70 Undervoltage

VUVQ_T4 VQ_T4- 15mV mV 1)

3.4.71 Current limit I Q_T4 limit 17 30 mA V Q_T4=4V

3.4.72 Ripple

PSRR 26 dB f=330kHz; 1)

3.4.73 Tracker load

CQ_T4 1 µF Ceramic type, minimum for stability Voltage Tracker Q_T5

3.4.74 Output

∆VQ_T5 -15 -1 5 mV V Q_T5-VQ_LDO1; 1mA < IQ_T5 < 17mA

3.4.75 Output

Q_T5 -9 mV V Q_T5-VQ_LDO1; IQ_T5 = 17mA

3.4.76 Overvoltage

VOVQ_T5 VQ_T5, nom mV I Q_T5 = 0mA; 1)

3.4.77 Undervoltage

VUVQ_T5 VQ_T5- 15mV mV 1)

3.4.78 Current limit I Q_T5 limit 17 30 mA V Q_T5=4V

3.4.79 Ripple

PSRR 26 dB f=330kHz; 1)

3.4.80 Tracker load

CQ_T5 1 µF Ceramic type, minimum for stability Voltage Tracker Q_T6

3.4.81 Output

Q_T6 -15 -1 5 mV V Q_T6-VQ_LDO1; 1mA < IQ_T6 < 17mA -40 < Tj <150 °C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Values Unit Test Conditions min. typ. max.

Data Sheet 36 Rev. 2.2, 2006-12-01

3.4.82 Output

∆VQ_T6 -9 mV V Q_T6-VQ_LDO1; IQ_T6 = 17mA

3.4.83 Overvoltage

VOVQ_T6 VQ_T6 mV I Q_T6 = 0mA; 1)

3.4.84 Undervoltage

VUVQ_T6 VQ_T6- 15mV mV 1)

3.4.85 Current limit I Q_T6 limit 17 30 mA V Q_T6=4V

3.4.86 Ripple

PSRR 26 dB f=330kHz; 1)

3.4.87 Tracker load

CQ_T6 1 µF Ceramic type, minimum for stability Standby Regulator

3.4.88 Output

VQ_STB 2.2 2.4 2.6 V 0µA <IQ_STB<500µA

3.4.89 Current limit I Q_STB limit 136 m A V Q_STB=2V

3.4.90 Standby

CQ_STB 100 nF Ceramic type, minimum for stability Current consumption in off-mode and Wake block

3.4.91 Supply

Iq,off 10 30 µA V IN=13.5V, Vwake=0 IQ_STB=0µA

3.4.92 Supply

Iq,off 10 30 µA V IN=42V, Vwake=0 IQ_STB=0µA

3.4.93 Turn on

V wake th, on 2.4 2.8 V V wake increasing -40 < Tj <150 °C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Va lues Unit Test Conditions min. typ. max.

Data Sheet 37 Rev. 2.2, 2006-12-01

3.4.94 Turn off

Vwake th, off 1.8 2.35 V V wake decreasing

3.4.95 Wake-up

Iwake 50 150 µA V wake=5V

3.4.96 Wake up

twake,min 41 0 5 0 µ s V wake > Vwake th, max; 1) Reset R1

3.4.97 Reset

Q_LDO1 VRTH Q_LDO1, de 4.5 4.65 4.8 V V Q_LDO1 decreasing

3.4.98 Reset

Q_LDO1 V RTH Q_LDO1, in 4.55 4.70 4.9 V V Q_LDO1 increasing

3.4.99 Reset output

VR1 L 0.4 V I R1=1.6mA; VQ_LDO1 =5V

3.4.100 R e s e t o u t p u t

VR1 L 0.3 V I R1=0.3mA; VQ_LDO1 =1V

3.4.101 R e s e t o u t p u t

I R1 L 10 µA V Q_LDO1 =0.75V; Tj > 25°C

3.4.102 R e s e t H i g h

IR1 H 1µ A Reset R2

3.4.103 R e s e t

Q_LDO2 VRTH Q_LDO2, de 2.6 2.8 3.0 V 3.3V mode; VQ_LDO2 decreasing

3.4.104 R e s e t

Q_LDO2 V RTH Q_LDO2, in - VRTH Q_LDO2, de 40 mV 3.3V mode -40 < Tj <150 °C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Values Unit Test Conditions min. typ. max.

Data Sheet 38 Rev. 2.2, 2006-12-01

3.4.105 R e s e t

Q_LDO2 VRTH Q_LDO2, de 2.3 2.4 2.5 V 2.6V mode; VQ_LDO2 decreasing

3.4.106 R e s e t

Q_LDO2 V RTH Q_LDO2, in - VRTH Q_LDO2, de 40 mV 2.6V mode

3.4.107 R e s e t o u t p u t

VR2 L 0.4 V I R2=1.6mA; VQ_LDO2 =2.5V

3.4.108 R e s e t o u t p u t

VR2 L 0.3 V I R2=0.3mA; VQ_LDO2 =1V

3.4.109 R e s e t o u t p u t

I R2 L 10 µA V Q_LDO2 =0.75V; Tj > 25°C

3.4.110 R e s e t H i g h

IR2 H 1µ A Reset R3

3.4.111 R e s e t

Q_LDO3 VRTH Q_LDO3, de 2.7 2.85 3.0 V 3.3V mode; VQ_LDO3 decreasing

3.4.112 R e s e t

Q_LDO3 V RTH Q_LDO3, in - VRTH Q_LDO3, de 40 mV 3.3V mode

3.4.113 R e s e t

Q_LDO3 VRTH Q_LDO3, de 2.3 2.35 2.5 V 2.6V mode; VQ_LDO3 decreasing

3.4.114 R e s e t

Q_LDO3 V RTH Q_LDO3, in - VRTH Q_LDO3, de 40 mV 2.6V mode

3.4.115 R e s e t o u t p u t

VR3 L 0.4 V I R3=1.6mA; VQ_LDO3 =3.3V -40 < Tj <150 °C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Va lues Unit Test Conditions min. typ. max.

Data Sheet 39 Rev. 2.2, 2006-12-01

3.4.116 R e s e t o u t p u t

VR3 L 0.3 V I R3=0.3mA; VQ_LDO3 =1V

3.4.117 R e s e t o u t p u t

IR3 L 10 µA V Q_LDO3 =0.75V; Tj > 25°C

3.4.118 R e s e t H i g h

I R3 H 1µ A

3.4.119 R e s e t

trr 121 0 µ s 1) Valid for R1, R2 and R3

3.4.120 R e s e t D e l a y

tNORM,RES 0.75 1 1.25 1

3.4.121 R e s e t D e l a y

tRES 0.75 1 1.25 t RES(SPI) Valid for R1, R2 and R3; tRES (SPI) is defined by the SPI word (see section 2.12) RAM Good 3.4.122 V Q1 threshold V Th Q1 2.3 2.8 3.3 V Window Watchdog

3.4.125 C l o s e d

tCW_tol 0.75 1 1.25 Multiply with watchdog window time set by SPI to obtain the limits (2.12)

3.4.126 O p e n

t OW_tol 0.75 1 1.25 Multiply with watchdog window time set by SPI to obtain the limits (2.12) -40 < T j <150 °C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Values Unit Test Conditions min. typ. max.

Data Sheet 40 Rev. 2.2, 2006-12-01

3.4.127 W a t c h d o g

3.4.128 W a t c h d o g

3.4.129 H - o u t p u t

VERR,H VQ_LDO1 – 2.0 VQ_LDO1 – 0.7 –V I ERR, H =1 m A

3.4.130 L - o u t p u t

VERR,L –0 . 3 0 . 5 V I ERR, L = – 1.6 mA SPI

3.4.131 S P I c l o c k

fCLK 0 2.5 MHz Production test up to 1MHz; For 2.5MHz: SPI Input DI

3.4.132 H - i n p u t

VIH –4 0 7 0 % o f VQ_LDO1

3.4.133 L - i n p u t

36 – % of VQ_LDO1

3.4.134 H y s t e r e s i s o f

VIHY 50 200 500 mV 1)

3.4.135 P u l l d o w n

II 52 5 1 0 0 µA VDI = 0.2 * VQ_LDO1

3.4.136 I n p u t

CI –1 0 1 5 p F 0 V < VQ_LDO1 < 5.25 V

3.4.137 I n p u t s i g n a l

tr – – 200 ns

3.4.138 I n p u t s i g n a l

tf – – 200 ns SPI Clock Input CLK -40 < Tj <150 °C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Va lues Unit Test Conditions min. typ. max.

Data Sheet 41 Rev. 2.2, 2006-12-01

3.4.139 H - i n p u t

VIH –4 0 7 0 % o f VQ_LDO1

3.4.140 L - i n p u t

36 – % of VQ_LDO1

3.4.141 H y s t e r e s i s o f

VIHY 50 200 500 mV 1)

3.4.142 P u l l d o w n

II 5 25 100 µA VCLK = 0.2 * VQ_LDO1

3.4.143 I n p u t

CI –1 0 1 5 p F 0 V < VQ_LDO1 < 5.25 V

3.4.144 I n p u t s i g n a l

tr – – 200 ns

3.4.145 I n p u t s i g n a l

tf – – 200 ns SPI Chip Select Input CS

3.4.146 H - i n p u t

VIH –3 9 7 0 % o f VQ_LDO1

3.4.147 L - i n p u t

35 – % of VQ_LDO1

3.4.148 H y s t e r e s i s o f

VIHY 50 200 500 mV 1)

3.4.149 P u l l u p

II, CS – 100 – 25 – 5 µA VCS = 0.2 * VQ_LDO1

3.4.150 I n p u t

CI –1 0 1 5 p F 0 V < VQ_LDO1 < 5.25 V

3.4.151 I n p u t s i g n a l

tr – – 200 ns

3.4.152 I n p u t s i g n a l

tf – – 200 ns -40 < Tj <150 °C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Values Unit Test Conditions min. typ. max.

Data Sheet 42 Rev. 2.2, 2006-12-01 Logic Output DO

3.4.153 H - o u t p u t

VDOH VQ_LDO1 – 1.0 VQ_LDO1 – 0.8 –V I DOH =1 m A

3.4.154 L - o u t p u t

VDOL – 0.2 0.4 V I DOL = – 1.6 mA

3.4.155 T r i - s t a t e

IDO_TRI – 10 – 10 µAV CS = V Q_LDO1; 0V < V DO < VQ_LDO1

3.4.156 T r i - s t a t e

CDO –1 0 1 5 p F V CS =V Q_LDO1 0V < VQ_LDO1 < 5.25 V Data Input Timing

3.4.157 C l o c k p e r i o dtpCLK 1000 – – ns

3.4.158 C l o c k h i g h

tCLKH 500 – – ns

3.4.159 C l o c k l o w

tCLKL 500 – – ns 1)

3.4.160 C l o c k l o w

tbef 500 – – ns 1)

3.4.161 C S setup

tlead 500 – – ns

3.4.162 C L K s e t u p

tlag 500 – – ns

3.4.163 C l o c k l o w

tbeh 500 – – ns

3.4.164 D I s e t u p t i m etDISU 250 – – ns

3.4.165 D I h o l d t i m etDIHO 250 – – ns

-40 < Tj <150 °C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Va lues Unit Test Conditions min. typ. max.

Data Sheet 43 Rev. 2.2, 2006-12-01

3.4.166 D O r i s e t i m etrDO – 50 100 ns CL = 100 pF

3.4.167 D O f a l l t i m etfDO – 50 100 ns CL = 100 pF

3.4.168 D O e n a b l e

tENDO – – 250 ns low impedance

3.4.169 D O d i s a b l e

tDISDO – – 250 ns high impedance

3.4.170 D O v a l i d t i m etVADO – 100 250 ns VDO < 10%

VDO > 90% CL = 100 pF General

3.4.171 T e m p e r a t u r e

TJ,Flag 140 °C 2)

3.4.172 O v e r

T J,Shutdown 150 170 200 °C 2)

3.4.173 O v e r -

sd_hys 30 K

3.4.174 D e l t a o f T W F

TJ,Shutdown - TJ,Flag 20 K 1) Specified by design, not subject to production test 2) Simulated at wafer test only, not absolutely measured -40 < Tj <150 °C; VIN=13.5V unless otherwise specified Item Parameter Symbol Limit Values Unit Test Conditions min. typ. max.

Data Sheet 44 Rev. 2.2, 2006-12-01

4 Typical performance

Buck converter switching frequency vs. junction temperature Buck converter output voltage at 1.5A load vs. junction temperature Buck converter DMOS on-resistance vs. junction temperature Buck converter current limit vs. junction temperature -50 -20 10 40 70 100 130 160Tj fSW kHz 280 300 420 320 340 360 380 400 -50 -20 10 40 70 100 130 160Tj VFB/L_IN V 5.3 5.4 6.0 5.5 5.6 5.7 5.8 5.9 -50 -20 10 40 70 100 130 160Tj RON mΩ 100 400 150 200 250 300 350 -50 -20 10 40 70 100 130 160Tj IMAX A 0.5 1.0 4.0 1.5 2.0 2.5 3.0 3.5

Data Sheet 45 Rev. 2.2, 2006-12-01 Start-up bootstrap charging current vs. junction temperature Device start-up voltage (acc. to spec. 3.2) vs. junction temperature Bootstrap UV lockout, turn on threshold vs. junction temperature Device wake up thresholds vs. junction temperature -50 -20 10 40 70 100 130 160Tj IBTSTR µA 280 120 160 200 240 -50 -20 10 40 70 100 130 160Tj VIN V 2.5 3.0 6.0 3.5 4.0 4.5 5.0 5.5 -50 -20 10 40 70 100 130 160Tj VBTSTR, turn on V 5.0 5.5 8.5 6.0 6.5 7.0 7.5 8.0 -50 -20 10 40 70 100 130 160Tj Vwake th V 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Vwake th, on Vwake th, off

Data Sheet 46 Rev. 2.2, 2006-12-01 Q_LDO1 output voltage at 800mA load vs. junction temperature Reset1 threshold at decreasing V_LDO1 vs. junction temperature Q_LDO1 current limit vs. junction temperature Q_LDO2 output voltage at 400mA load (2.6V mode) vs. junction temperature -50 -20 10 40 70 100 130 160Tj VQ_LDO1 V 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 -50 -20 10 40 70 100 130 160Tj VRTH Q_LDO1, de V 4.45 4.50 4.55 4.60 4.65 4.70 4.75 4.80 -50 -20 10 40 70 100 130 160Tj IQ_LDO1 V 1400 1300 700 800 900 1000 1100 1200 -50 -20 10 40 70 100 130 160Tj VQ_LDO2 V 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80

Data Sheet 47 Rev. 2.2, 2006-12-01 Q_LDO2 current limit (2.6V mode) vs. junction temperature Q_LDO3 output voltage at 300mA load (3.3V mode) vs. junction temperature Reset2 threshold at decreasing V_LDO2 (2.6V mode) vs. junction temperature Q_LDO3 current limit (3.3V mode) vs. junction temperature -50 -20 10 40 70 100 130 160Tj IQ_LDO2 V 850 500 550 600 650 700 750 800 -50 -20 10 40 70 100 130 160Tj VQ_LDO3 V 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 -50 -20 10 40 70 100 130 160Tj VRTH Q_LDO2, de V 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 -50 -20 10 40 70 100 130 160Tj IQ_LDO3 V 600 250 300 350 400 450 500 550

Data Sheet 48 Rev. 2.2, 2006-12-01 Reset3 threshold at decreasing V_LDO3 (3.3V mode) vs. junction temperature Tracker current limit vs. junction temperature Tracker accuracy with respect to V_LDO1 vs. junction temperature Q_STB output voltage at 500µA load vs. junction temperature -50 -20 10 40 70 100 130 160Tj VRTH Q_LDO3, de V 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 -50 -20 10 40 70 100 130 160Tj IQ_Tx mA -50 -20 10 40 70 100 130 160Tj dVQ_Tx mV -10 -50 -20 10 40 70 100 130 160Tj VQ_STB V 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8

Data Sheet 49 Rev. 2.2, 2006-12-01 Q_STB current limit vs. junction temperature Device current consumption in off mode vs. junction temperature -50 -20 10 40 70 100 130 160Tj IQ_STB mA 4.0 3.5 0.5 1.0 1.5 2.0 2.5 3.0 -50 -20 10 40 70 100 130 160Tj Iq, off µA

Data Sheet 50 Rev. 2.2, 2006-12-01

5 Application Information

5.1 Application Diagram

Figure 14 Application Diagram TLE 6368 AEA03380ZR.VSD Buck Regulator Standby Regulator 2.5 V Driver PWMOSZ BOOTSTRAP Q_STB Buck Output IN BOOST SLEW CI3 10 to 100 nF RSlew 0 to 20 kΩ + CI2 47 µF LI Up to 47 µH CI1 100 nF Battery CBOOST 100 nF DBOOST FB/L_IN Charge Pump CFLY 100 nF CCCP 220 nF CCP Protection To IGN WAKE Lin. Reg. 5 V Lin. Reg. 3.3/2.6 V Lin. Reg. 5/3.3 V Tracker 5 V Ref CLDO1,1 470 nF + CLDO1,2 4.7 µF SEL Q_LDO1 CLDO2,1 470 nF + CLDO2,2 4.7 µF Q_LDO2 CLDO3,1 470 nF + CLDO3,2 4.7 µF Q_LDO3 CT1 1 µF Q_T1 Tracker 5 V Ref CT2 1 µF Q_T2 Tracker 5 V Ref CT3 1 µF Q_T3 Tracker 5 V Ref CT4 1 µF Q_T4 Tracker 5 V Ref CT5 1 µF Q_T5 Tracker 5 V Ref CT6 1 µF Q_T6 SPI

16 Bit

1 kΩ DO 10 kΩ DI CS10 kΩ CLK10 kΩ Power Down Logic Reset Logic Q_LDO1 Window Watchdog GND Sensor Supplies (off board supplies) µ-Controller/ Memory Supply CSTB 100 nF RBoost 22 Ω SW 2* LB 47 µH CBTSTR 680 nF DB 3 A, 60 V CB > 10 µF ceramic or > 20 µF low ESR tantalum ERR To µC To µC 10 kΩ10 kΩ Error- Amplifier Internal Reference Feedback 10 kΩ 10 kΩ

Data Sheet 51 Rev. 2.2, 2006-12-01

5.2 Buck converter circuit

A typical choice of external components for the buck converter is given in figure 14. For basic operation of the buck co nverter the input capacitor C I2, the bootstrap capacitor CBTP, the catch diode D B, the inductance L B, the output capacitor C B and the charge pump capacitors CFLY and CCCP are necessary. A Zener Di ode at the FB/L_IN input is recommended as a protection against overvoltage spikes. The additional compone nts shown on top of the circ uit lower the el ectromagnetic emission (LI, CI1, CI3, RSlew) and the switching losses (R Boost, CBoost, DBoost). For 12V battery systems the switching loss minimization feature might not be used. The Boost pin (33) is connected directly to the IN pins (32, 30) in that case and the components RBoost, CBoost and DBoost are left away.

5.2.1 Buck inductance (L B) selection:

The inductance value determines together with the input voltage, the output voltage and the switching frequency the cu rrent ripple which occurs du ring normal operation of the step down converter. This current ripple is important for the all over ripple at the output of the switching converter. As a rule of thumb this current ripple ∆I is chosen between 10 % and 50% of the load current. For optimum operation of the control loop of the Buck c onverter the inductance value should be in the range indicated in section 3.3, recommended operation range. When picking finally th e inductance of a certain suppli er (Epcos, Coilcraft etc.) the saturation current has to be considered. With a maximu m current limit of the Buck converter of 3.2A an inducta nce with a minimum saturation current of 3.2A has to be chosen. L VI VOUT–() VOUT⋅

Data Sheet 52 Rev. 2.2, 2006-12-01

5.2.2 Buck output capacitor (C B) selection:

The choice of the output capacitor effects straight to the minimum achievable ripple which is seen at the output of the buck converter. In continuous conduction mode the ripple of the output voltage equals: From the formula it is recogni zed that the ESR has a big infl uence in the total ripple at the output, so ceramic types or low ESR tantalum capacitors are recommended for the application. One other important thing to note are the requirements for the resonant frequency of the output LC-combination. The choi ce of the component s L and C have to meet also the specified range given in section 3.3 otherwise instabilities of the re gulation loop might occur.

5.2.3 Input capacitor (C I2) selection:

At high load currents, where the current through the inductance flows continuously, the input capacitor is expose d to a square wave curre nt with its duty cycle V OUT/VI. To prevent a high ripple to the battery line a capacitor with low ESR should be used. The maximum RMS current which the capacitor has to withstand is calculated to:

5.2.4 Freewheeling diode / catch diode (D B)

For lowest power loss in the freewheeling path Schottky diodes are recommended. With those types the reverse recovery charge is negligible and a fast handover from freewheeling to forward conduction mode is possible. Depending on the application (12V battery systems) 40V types could be also used instead of the 60V diodes. A fast recovery diode with recovery times in the range of 30ns can be also used if smaller junction capacitance values (smaller spikes) are desired, the slew resistor should be set in this case between 10 and 20kW. VRipple ∆IR ESRCB ⋅= IRMS ILOAD VOUT VIN 3--- ∆I  2 ⋅+⋅⋅=

Data Sheet 53 Rev. 2.2, 2006-12-01

5.2.5 Bootstrap capacitor (C BTP)

The voltage at the Bootstrap capacitor does not exceed 15 V, a ceramic type with a minimum of 2% of the buck output ca pacitance and voltage class 16V would be sufficient.

5.2.6 External charge pump capacitors (C FLY, CCCP)

Out of the feedback voltage the charge pump generates a voltage between 8 and 10V. The fly capacitor connected be tween C+ and C- is charged with the feedback voltage level and discharged to achieve the (almost) double voltage level at CCP. CFLY is chosen to 100nF and CCCP to 220nF, both ceramic types. The connection of CCP to a vo ltage source of e.g. 7V (take care of the maximum ratings!) via a diode improves the start-up behavior at very low battery voltage. The diode with the cathode on CCP has to be used in order to avoid any influence of the voltage source to the device’s operation and vice versa.

5.2.7 Input filter compone nts for reduced EME (CI1, CI2, CI3, LI, RSlew)

At the input of Buck converters a squa re wave current is observed causing electromagnetical interferenc e on the battery line. The em ission to the battery line consists on one hand of components of the switching frequency (fundamental wave) and its harmonics and on the other hand of the high frequency components derived from the current slope. For proper attenuation of those interferers a π-type input filter structure is recommended which is built up with inductive (LI) and capacitive components (CI1, CI2, CI3). The inductance can be chos en up to the value of th e Buck converter inductance, higher values might not be necessary, CI1 and CI3 should be ceramic types and for CI2 an input capacitance with very low ESR should be chosen and placed as close to the input of the Buck converter as possible. Inexpensive input filters show due to their parasitics a notc h filter characteristic, which means basically that the lowpass filter acts from a certain frequency as a highpass filter and means further that the high frequency components are not attenuated properly. For that reason the TLE 6368 G1 / SONIC offers the possibility of current slope adjustment. The current transition time can be set by the external resistor (located on the SLEW pin) to times between 20ns and 80ns by varying the re sistor value between 0 Ω (fastest transition) and 20kΩ (slowest transition).

5.2.8 Feedback circuit for minimum switching loss (RBoost, CBoost, DBoost)

To decrease the switching losses to a minimum the external components RBoost, CBoost and DBoost are needed. The current though the feedback resistor RBoost is about a few mA where the Diode DBoost and the capacitor CBoost run a part of the load current. If this feature is not needed the three components are not needed and the Boost pin (33) can be connected directly to the IN pins(32, 30).

Data Sheet 54 Rev. 2.2, 2006-12-01

5.3 Reverse polarity protection

The Buck converter is due to the parasitic source drain diode of the DMOS not reverse polarity protected. Therefore, as an example, the reverse polarity diode is shown in the application circuit, in general the reverse polarity protecti on can be done in different ways.

5.4 Linear voltage regulators (C LDO1, 2, 3)

As indicated before the linear regulators show stable operation with a minimum of 470nF ceramic capacitors. To avoid a high ripple at the output due to load steps this output cap might have to be increased to some few µF capacitors.

5.5 Linear voltage trackers (C T1,2,3,4,5,6)

The voltage trackers require at their outputs 1µF ceramic capacitors each to avoid some oscillation at the output. If needed the tracker outputs can be connected in parallel, in that the output capacitor increases linear according to the number of parallel outputs.

5.6 Reset outputs (R1,2,3)

The undervoltage/watchdog reset outputs are open drain structures and require external pull up resistors in the range of 10kΩ to the µC I/O voltage rail.

Data Sheet 55 Rev. 2.2, 2006-12-01

5.7 Components recommendation - overview

Device Type Supplier Remark LI B82479 EPCOS 22 µH, 3.5A, 47mΩ DO3340P-473 Coilcraft 47 µH, 3.8A, 110mΩ DO5022P-683 Coilcraft 68 µH, 3.5A, 130mΩ DS5022P-473 Coilcraft 47 µH, 4.0A, 97mΩ SLF12575T-330M3R2- H TDK 33 µH, 3.2A CI1 Ceramic various 100nF, 60V CI2 Low ESR tantalum various 47 µF, 60V CI3 Ceramic various 10nF to 100nF, 60V DBoost S3B various LB B82479 EPCOS 22 µH, 3.5A, 47mΩ DO3340P-473 Coilcraft 47 µH, 3.8A, 110mΩ DO5022P-683 Coilcraft 68 µH, 3.5A, 130mΩ DS5022P-473 Coilcraft 47 µH, 4.0A, 97mΩ SLF12575T-330M3R2- H TDK 33 µH, 3.2A CBTSR Ceramic various 680nF, 10V DB MBRD360 ON Schottky, 60V, 3A MBRD340 ON Schottky, 40V, 3A SS34 FCH Schottky, 40V, 3A C B B45197-A2226 EPCOS Low ESR Tantalum, 22 µF, 10V, C-case 2 * LMK316BJ475ML Taiyo Y uden 2* Ceramic X7R, 4.7 µF, 10V C3216X7R1C106M TDK Cera mic X7R, 10µF, 16V TPSC476K010R350 AVX Lo w ESR Tantalum, 47µF, 10V, C-case CLDOx Ceramic various 470nF, 10V CTx Ceramic various 1µF, 60V

Data Sheet 56 Rev. 2.2, 2006-12-01

5.8 Layout recommendation

The most sensitive points for Buck converte rs - when considering the layout - are the nodes at the input and the output of the Buck switch, the DMOS transistor. For proper operation the external catc h diode and Buck inductance have to be connected as close as possible to the SW pins (29, 31). Best suitable for the connection of the cathode of the Schottky diode and one terminal of the inductance would be a small plain located next to the SW pins. The GND connection of the catch diode must be also as short as possible. In general the GND level should be implemented as surface area over the whole PCB as second layer, if necessary as third layer. The pin FB/L_IN is sensitive to noise. Wi th an appropriate la yout the Buck output capacitor helps to avoid noise coupling to this pin. Also filtering of steep edges at the supply voltage pin e.g. as shown in the application diagram is mandatory. CI2 may either be a low ESR Tantalum capacitor or a ce ramic capacitor. A mi nimum capacitance of 10µF is recommended for CI2. To obtain the optimum filt er capability of the input π-filter it has to be located also as close as possible to the IN pins, at least the ceramic capacitor CI3 should be next to those pins.

Data Sheet 57 Rev. 2.2, 2006-12-01

6 Package Outlines

Green Product (RoHs compliant) To meet the world-wi de customer requirements for envi ronmentally friendly products and to be compliant with government regula tions the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Bottom View 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Stand off 1 18 0.25 ±0.11.1 +0.13 0.25 36x M (Heatslug) 15.74 0.65 17 x 0.65 = 11.05 ±0.1 CAB C 3.25 3.5 MAX. +0.1 2) 0.1 ±0.1 2.8 B11±0.15 1) 1.3 5˚0.25 ±3˚ -0.02+0.07 6.3 14.2 ±0.3 B ±0.15 0.25 Heatslug 0.95 Heatslug ±0.15.9 3.2 ±0.1 13.710 1 -0.2 Index Marking 15.9 1)±0.1 A 1 x 45˚ PG-DSO-36-26 SMD = Surface Mounted Device Dimensions in mm You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products.

Data Sheet 58 Rev. 2.2, 2006-12-01 TLE 6368 / SONIC Revision History: 2006-12-01 Rev. 2.2 Previous Version: 2.1 Page Subjects (major chan ges since last revision) general Updated Infineon logo #1 Added “AEC” and “Green” logo #1 Added “Green Product ” and “AEC qualified” to the feature list #1 Updated Package Name #57 Added “Green Product” remark #59 Disclaimer Update

Data Sheet 59 Rev. 2.2, 2006-12-01 Edition 2006-12-01 Published by Infineon Technologies AG

81726 München, Germany

© Infineon Technologies AG 2007. All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.