TLE6228

TLE6228GP INFINEON | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 18

Technical content

Features

• Shorted Circuit Protection
• Overtemperature Protection
• Overvoltage Protection
• Parallel Control of the Inputs (PWM Applications)
• Seperate Diagnostic Pin for Each Channel
• Power - SO 20 - Package with integrated cooling area
• Standby mode with low current consumption
• µC compatible Input
• Electrostatic Discharge (ESD) Protection Application
• All kinds of resistive and inductive loads (relays,electromagnetic valves)
• µC compatible power switch for 12 and 24 V applications
• Solenoid control switch in automotive and industrial control systems
• Robotic Controls General description Quad channel Low-Side-Switch (2x5A/2x3A) in Smart Power Technology (SPT) with four separate in- puts and four open drain DMOS output stages. The TLE 6228 GP is fully protected by embedded pro- tection functions and designed for automotive and industrial applications. Each channel has its own status signal for diagnostic feedback. Therefore the TLE 6228 GP is particularly suitable for ABS or Powertrain Systems. Block Diagram Supply voltage V S 4.8 - 32 V Drain source voltage V DS(AZ)max 60 V On resistance R ON 1,2 0.23 Ω RON 3,4 0.28 Ω Output current I D 1,2 (max) 2 x 5 A ID 3,4 (max) 2 x 3 A P-DSO-20-12 Ordering Code: Q67006-A9364 Output Stage Gate Control LOGIC ST1 ST2 GND VS ST3 1 4 IN1 IN2 IN3 IN4 OUT1 OUT4 STBY VBB as Ch. 1 as Ch. 1 as Ch. 1 GND normal function SCB / overload overtemperature open load/sh. to gnd as ST 1 as ST 1 as ST 1ST4 ENA

V3.1 Page 26. Aug. 2002 2 Detailed Block Diagram VS LOGIC LOGIC ST4 IN4 ST1 IN1 ENA Open Load Overload Open Load Overload Overtemperature Channel 1 Overtemperature Channel 4 LOGIC LOGIC GND ST3 IN3 ST2 IN2 Open Load Overload Open Load Overload STBY internal supply IPD Overtemperature Channel 2 Overtemperature Channel 3 IPD IPD IPD OUT1 OUT OUT OUT

V3.1 Page 26. Aug. 2002 3 Pin Description Pin Configuration (Top view) Pin Symbol Function

1 GND Ground

2 OUT1 Power Output channel 1

3 ST1 Status Output channel 1

4 IN4 Control Input channel 4

5 VS Supply Voltage

6 STBY Standby

7 IN3 Control Input channel 3

8 ST2 Status Output channel 2

9 OUT2 Power Output channel 2

10 GND Ground

11 GND Ground

12 OUT3 Power Output channel 3

13 ST3 Status Output channel 3

14 IN2 Control Input channel 2

15 GND Ground Logic

16 ENA Enable Input for all four channels

17 IN1 Control Input channel 1

18 ST4 Status Output channel 4

19 OUT4 Power Output channel 4

20 GND Ground

Heat slug internally connected to ground pins GND 1 • 20 GND OUT1 2 19 OUT4 ST1 3 18 ST4 IN4 4 17 IN1 VS 5 16 ENA STBY 6 15 GNDL IN3 7 14 IN2 ST2 8 13 ST3 OUT2 9 12 OUT3 GND 10 11 GND P - DSO - 20 - 12

V3.1 Page 26. Aug. 2002 4 Maximum Ratings for Tj = – 40°C to 150°C The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result. Parameter Symbol Values Unit Supply voltage VS -0.3 ... + 40 V Continuous drain source voltage (OUT1...OUT4) VDS 45 V Input voltage IN1 to IN4, ENA VIN , VENA - 0.3 ... + 6 V Input voltage STBY VSTBY - 0.3 ... + 40 Status output voltage VST - 0.3 ... + 32 V Load Dump Protection VLoad Dump = UP+US; UP=13.5 V RI 1)=2 Ω; td=400ms; IN = low or high With RL= 5 Ω for Ch. 1,2; 10 Ω for Ch. 3,4 (ID = 2,7A respectively 1,35A) VLoad Dump 2) 55 V Operating temperature range Storage temperature range Tj Tstg - 40 ... + 150 - 55 ... + 150 Output current per channel (see page 6) ID(lim) ID(lim) min A Status output current IST - 5 ... + 5 mA Inductive load switch off energy (single pulse) Tj = 25°C EAS 50 mJ Electrostatic Discharge Voltage (human body model) according to MIL STD 883D, method 3015.7 and EOS/ESD assn. standard S5.1 - 1993 VESD 2000 V DIN Humidity Category, DIN 40 040 E IEC Climatic Category, DIN IEC 68-1 40/150/56 Thermal resistance junction – case (die soldered on the frame) junction - ambient @ min. footprint junction - ambient @ 6 cm 2 cooling area RthJC RthJA K/W 1) RI=internal resistance of the load dump test pulse generator LD200 2) VLoadDump is setup without DUT connected to the generator per ISO 7637-1 and DIN 40 839. PCB with heat pipes, backside 6 cm2 cooling area Minimum footprint

V3.1 Page 26. Aug. 2002 5

Electrical Characteristics

Parameter and Conditions Symbol Values Unit VS = 4.8 to 18 V ; Tj = - 40 °C to + 150 °C (unless otherwise specified) min typ max 1. Power Supply (VS) Supply current (Outputs ON) IS 8m A Supply current (Outputs OFF) VENA = L, VSTBY = H IS 4m A Standby current V STBY = L IS 10 µA Operating voltage VS 4.8 32 V 2. Power Outputs ON state resistance Channel 1,2 T j = 25 ° C ID = 1A; VS ≥ 9.5 V T j = 150°C RDS(ON) 0.23 0.26 0.5 Ω ON state resistance Channel 3,4 T j = 25 ° C ID = 1A; VS ≥ 9.5 V T j = 150°C RDS(ON) 0.28 0.4 0.75 Ω Z-Diode clamping voltage (OUT1...4) I D ≥ 100 mA VDS(AZ) 45 60 V Pull down current V STBY = H, VIN = L IPD 10 20 50 µA Output leakage current3 VSTBY = L, 0V ≤ VDS ≤ 20V IDlk 5µ A Output turn on time 4 I D = 1 A Output turn off time 4 ID = 1 A Output on fall time 4 I D = 1 A Output off rise time 4 ID = 1 A Overload switch-off delay time 4 Output off status delay time 4 Failure extension Time for Status Report Input Suppression Time Open Load (off) filtering Time ton toff tfall trise tDSO tD tD-failure tD-IN tfOL(off) 500 500 500 1200 1200 1200 100 3000 3000 3000 100 µs 3. Digital Inputs (IN1, IN2, IN3, IN4, ENA) Input low voltage VINL - 0.3 1.0 V Input high voltage VINH 2.0 6.0 V Input voltage hysteresis 5 VINHys 50 200 mV Input pull down current V IN = 5 V; VS ≥ 6.5 V IIN 10 30 60 µA Enable pull down current VENA = 5 V; VS ≥ 6.5 V IENA 10 20 40 µA 4. Digital Status Outputs (ST1 - ST4) Open Drain Output voltage low I ST = 2 mA VSTL 0.5 V Leakage current high ISTH 2µ A 3 If the output voltage exceeds 35V, this current (zener current of a internal structure) can rise up to 1mA

4 See timing diagram, resistive load condition; VS ≥ 9 V

5 This parameter will not be testet but assured by design

V3.1 Page 26. Aug. 2002 6 Parameter and Conditions Symbol Values Unit VS = 4.8 to 18 V ; Tj = – 40 °C to + 150 °C (unless otherwise specified) min typ max 5. Standby Input (STBY) Input low voltage VSTBY 01 V Input high voltage VSTBY 3.5 V S V Input current V STBY = 18 V ISTBY 300 µA 6. Diagnostic Functions Open load detection voltage V S ≥ 6.5 V VENA = X, VIN = L VDS(OL) 0.3*VS 0.33*VS 0.36*VS V Open load detection current channel 1,2 V S ≥ 6.5 V VENA = VIN = H ID(OL) 1,2 100 160 250 mA Open load detection current channel 3,4 V S ≥ 6.5 V VENA = VIN = H ID(OL) 3,4 100 160 250 mA Overload detection current channel 1,2 V S ≥ 6.5 V ID(lim) 1,2 57 . 5 A Overload detection current channel 3,4 V S ≥ 6.5 V ID(lim) 3,4 35 . 5 A Overtemperature shutdown threshold 5 Hysteresis Tth Thys 170 200 °C K Pulse Width for static diagnostic output tIN 500 µs

5 This parameter will not be tested but assured by design

V3.1 Page 26. Aug. 2002 7 Application Description This IC is especially designed to drive inductive loads (relays, electromagnetic valves). Integrated clamp-diodes limit the output voltage when inductive loads are discharged. Four open-drain logic outputs indicate the status of the integrated ciruit. The following conditions are monitored and signalled: - overloading of output (also shorted load to supply) in active mode - open and shorted load to ground in active and inactive mode - overtemperature Circuit Description Input Circuits The control and enable inputs, both active high, consist of schmitt triggers with hysteresis. All inputs are provided with pull-down current sources. Not connected inputs are interpreted as low and the re- spective output stages are switched off. In standby mode (STBY = LOW ) the current consumption is greatly reduced. The circuit is active when STBY = HIGH. If the standby function is not used, it is allowed to connect the standby pin directly to VS. Status Signals: The status signals are undefined for 2ms after a power up event or a STBY low to high transition. Output Stages The four power outputs consist of DMOS-power transistors with open drains. The output stages are short circuit protected throughout the operating range. Each output has it's own zenerclamp. This causes a voltage limitation at the power transistor when inductive loads are switched off. Parallel to the DMOS transistors there are internal pull down current sources. They are provided to detect an open load condition in the off state. They will be disconnected in the standby mode. Due to EMI measures there is an internal zenerclamp in parallel to the output stage. It gets active above 33V drain source voltage. This leads to an increasing leakage current up to 1 mA @ V DS = 40V. Protective Circuits The outputs are protected 6) against current overload and overtemperature. If the output current in- creases above the overload detection threshold I QO for a longer time then t DSO or the temperature in- creases above Tth, then the power transistor is immediately switched off. It remains off until the control signal at the input is switched off and on again. Fault Detection The status outputs indicate the switching state of the output stage. Under normal conditions is: ST = low Output off; ST = high Output on. If an error occurs, the logic level of the status output is in- verted, as listed in the diagnostic table. 6) The integrated protection functions prevent an IC destruction under fault conditions and may not be used in normal operation or permanently.

V3.1 Page 26. Aug. 2002 8 If current overload or overtemperature occurs for a longer time than t DSO, the fault condition is latched into an internal register and the output is shutdown. The reset is done by switching off the correspond- ing control input for a time longer than tD-IN. Open load is detected for all four channels in on and off mode. In the on mode the load current is monitored. If it drops below the specified threshold value IQU then an open load condition is detected. In the off mode, the output voltage is monitored. An open load condition is detected when the output voltage of a given channel is below the threshold V DS(OL), which is typ. 33 % of the supply voltage VS. To prevent an open load diagnosis in case of transient Voltages on the outputs the open load detection in off mode uses a filter of typ. 50µs. Status output at pulse width operation If the input is operated with a pulsed signal, the status does not follow each single pulse of the input signal. An internal delay t D of typ. 1.2ms ( min 500 µs) enables a continuous status output signal. See the timing diagrams on the following pages for further information. This internal status delay simplifies diagnostic software for pwm applications. Diagnostic Table In general the status follows the input signal in normal operating conditions. If any error is detected the status is inverted. Operating Condition Standby Input Enable Input Control Input Power Output Status Output STBY ENA IN Q ST Standby L X X off H Normal function H H H L H H X L H off off ON L L H Open load or short to ground H H H H L L H H L H L H off off off ON H H H L Overload or short to supply1) reset latch 2) H H H H H L H H → L X off off off L L L Overtemperature1) reset latch 2) H H H H H L H H → L X off off off L L L Note 1) : overload/short-to-supply/overtemperature - events shorter than min. time tDSO specified in 2.10 will not be latched and not reported at the status pin.

V3.1 Page 26. Aug. 2002 9 Note 2) : to reset latched status-output in case of overload/short-to-supply/overtemperature the control input has to go low and stay low for longer than max. input suppression time tD-IN specified in 2.13 of the characteristics Failure Situations and Status Report Logic Block Diagram Open load "on" Open load "off" Overload Input 1....On 0... Off ENA 1....enabled 0... disabled Overtemperature Delay D Delay D Delay D IN IN IN OUT OUT OUT EN EN EN Filter 30µs HI Q Q SET CLR S R Gate Driver 1... Output 0....Output Status 0....High 1....Low Delay 60µs Delay D IN OUT tD 1,2ms typ. Delay 60µs IN OUT tD 60µs typ. tDSO Filter tD tD-IN when load tD-failure tD-failure

V3.1 Page 26. Aug. 2002 10 Timing Diagrams Output Slope V VIN H V t VDS t VST 85% 15% t f ton t r tD t VS INL IN t off Fig. 1 Overload Switch OFF Delay ID ID(lim) ID(OL) t VST t t DSO t D-failure Fig. 2

V3.1 Page 26. Aug. 2002 11 Test Circuit VD = 5V 10k 10k 10k 10k ST1 ST2 ST3 ST4 IN1 IN2 IN3 IN4 ENA ST1 ST2 ST3 ST4 IN1 IN2 IN3 IN4 ENA STBY VS OUT1 OUT2 OUT3 OUT4 GND VS RL2RL3 RL1RL4 OUT1 OUT2 OUT3 OUT4 TLE 6227 VST1 VST2 VST3 VIN1 VIN3 VIN4VIN2VST4 VENA VSTBY VDS(OUT4) VDS(OUT3) VDS(OUT2) VDS(OUT1) ID1 ID2 ID3 ID4 IST1 IST2 IST3 IST4 IIN2 IIN3 IIN1 IIN4 IENA ISTBY IVS TLE 6228 GP

V3.1 Page 26. Aug. 2002 12 Application Circuit STBY ST1 ST2 ST3 ST4 VS IN1 IN2 IN3 IN4 ENA GND OUT1 OUT2 OUT3 OUT4 L1 L2 L3 L410k 10k 10k 10k Status Output Control Inputs Enable Input VD = 5V C +12VTLE 6228 The blocking capacitor C is recommended to avoid critical negative voltage spikes on VS in case of battery interruption during OFF-commutation.

V3.1 Page 26. Aug. 2002 13 Timing Diagrams of Diagnostic with Pulsed Input Signal Normal condition, resistive load, pulsed input signal t D t D IN V I D STV t IN Fig. 3 Current Overload t DSO F current overload condition IN V I D STV t DSO I D(lim) tINoff tD-IN tINoff < tD-IN : Input suppression time avoids a restart after overtemperature Fig. 4

V3.1 Page 26. Aug. 2002 14 Diagnostic status output at different open load current conditions INV I D STV t D I D(OL) D-failuret Fig. 5 INV I D STV t D I D(OL) tINoff tD-failure tINOFF < tD leads to a static status signal Fig. 6 tD INV I STV D I D(OL) tINoff tD-failure tD-failure tD-failure tINoff > tD : Intermittend status signal Fig. 7

V3.1 Page 26. Aug. 2002 15 Normal operation, followed by open load condition INV ID STV tD 12V ~ 55V 33% Open load voltage condition DSV ID(OL) tD-failure tfOL(off)- tD-failure Fig. 8 Overtemperature INV ID STV t DSO Overtemperature tINoff > tD-IN Reset of overload Flip Flop ID(OL) tD-failure tD-failure Fig. 9

V3.1 Page 26. Aug. 2002 17 Package and ordering code all dimensions in mm TLE 6228 GP Q67006-A9364 0.1 1.3 1.2 -0.3 15.9 +/-0.15 A 2.8 8° 8° 8°6.3 11 +/-0.15 1) 14.2 +/-0.3 11 0 1120 PIN 1 INDEX MARKING 1 x 45° 13.7 -0.2 9 x = 11.431.27 1.27 0.25 AM0.4 +0.13 3.2 +/-0.1 5.9 +/- 0. 1 15.74 +/- 0.1

V3.1 Page 26. Aug. 2002 18 Published by Infineon Technologies AG, Bereichs Kommunikation St.-Martin-Strasse 76, D-81541 München © Infineon Technologies AG 1999 All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Tech- nologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are in- tended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.