TLE6210G INFINEON | Alldatasheet
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V1.2 Data Sheet 1 2002-08 ABS System IC TLE 6210 TLE 6211 1O v e r v i e w
1.1 Features
- 5 V, 800 mA linear regulator Undervoltage/overvoltage reset Undervoltage and overvoltage logout Digital watchdog supervision for 2 Microcontrollers (motor) relay driver (valve) relay driver Inverted or non inverted lamp relay driver Enable output Overtemperature and overcurrent protection
1.2 Functional Description
The TLE 6210 and TLE 6211 are integrated circuit consisting of a 5 V voltage regulator with 800 mA current capability, different relay driver outputs and supervision logic. The supervision logic watches the input voltage and the regulator output voltage both for over-voltage and under-voltage. In addition two window watchdogs supervise the correct operation of 2 independent watchdog signals, e.g. from two Microcontrollers. The TLE 6210 and TLE 6211 are designed especially for the severe conditions of ABS/ ASR applications in an automotive environment. Type Ordering code Package/Shipment TLE 6210 C on request Bare dice TLE 6210 G on request P-DSO-20-12, Tape and Reel TLE 6211 G on request P-DSO-20-12, Tape and Reel
V1.2 Data Sheet 2 2002-08
1.3 Block Diagram
AD 20.09.01 UST USTS UZP GND RES1 RES2 EN PGND Window watchdog SIA MRA WD1 WD 2 Oscillator Clock super- vision Charge Pump UCP SupervisionLogic PGND SILA PGND NSILA PGND MR PGND VR
V1.2 Data Sheet 3 2002-08
2 Pin / Pad Configuration
Figure 2 Pin Configuration P-DSO-20-12 Figure 3 Chip-Layout 11 0 1120 Layout VR NSILA GNDP SILA GNDP GND MR RES2 EN RES1 UCP UZP SIA WD2 MRA WD1 GND USTS UST
V1.2 Data Sheet 4 2002-08 Pin / Pad Definitions and Functions Pin Number Symbol Pad Name Function TLE 6210 G TLE 6211G
11 G N D Power GND connection
22 N . C . Not Connected UZP Supply Voltage; reverse protection diode is required
44 UCP Charge Pump Capacitor pin; An external
capacitor is the energy storage for the charge pump
55 R E S 1 Reset Output 1; open collector output with
integrated pull-up resistor. A high indicates normal operation; function identical to RES2
66 E N Enable Output; open collector; low indicates an
77 R E S 2 Reset Output 2; open collector output with
integrated pull-up resistor. A high indicates normal operation; function identical to RES1
88 V R Valve Relay Output; open drain output
9– S I L A Lamp Output; open drain output; For TLE 6210 CW only –9 N S I L A Inverted Lamp Output; open drain output; For TLE 6211 CW only 10 10 GND Power Ground connection 11 11 GND Power Ground connection 12 12 MR Motor Relay Output; open drain output 13 13 SIA Lamp Control Signal Input; controls SILA/NSILA; a logic high switches SILA off and NSILA on 14 14 WD2 Watchdog Input 2 15 15 MRA Motor Relay Control Input; A logic High switches MR on 16 16 WD1 Watchdog Input 1 17 17 GND Logic Ground 18 18 USTS Sense input for UST supervision 19 19 UST 5 V Linear Regulator Output 20 20 GND Ground Connection Backside metallization GND The lead frame connects the pins 1, 10, 11 and 20 to the backside metallization.
Electrical Characteristics
V1.2 Data Sheet 5 2002-08
3 Electrical Characteristics
3.1 Absolute Maximum Ratings
-40 /g176C /g163 Tj /g163 150 /g176C # Parameter Symbol Limit Values Unit Conditions min. max. M1 Supply Voltage UZP 02 0 V – 02 6 . 5 V 0 < tp /g163 5 min.; -40 /g176C /g163 80 /g176C 03 5 V 0 < tp /g163 200 ms; f < 0.067 Hz; n /g163 360 cycles 03 5 V 0 < tp /g163 50 ms; 0 < fp /g163 1 Hz; n /g163 36000 cycles -1.5 – V tp = 2 s M2 Supply Voltage variation d UZP/dt – /g12410/g124V//g109s– M3 Output voltage at VR, MR UVR, UMR – 60 V VR, MR-DMOS off M4 Output voltage at SILA USILA – 42 V SILA-DMOS off M5 Output voltage at NSILA UNSILA – 42 V NSILA-DMOS off M6 Output voltage at RES1, RES2 URES1 URES2 -0.5 7 V – M7 Output voltage at EN UEN -0.5 7 V – M8 Input Voltage at WD1, WD2, MRA, SIA UWD1, UWD2 UMRA, USIA -0.5 7 V – M9 Voltage UCP UCP -0.5 20 V – M10 Storage Temperature Tstg -55 150 /g176C – M11 Junction Temperature Tj -40 150 175 /g176C /g176C continuos short term (< 50 h over lifetime)
V1.2 Data Sheet 6 2002-08 Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. M12 ESD – /g1774000 /g1772000 V V according to EIA/JESD 22-A 114B UZP, MR, EN, VR, SILA, all other pins M13 Life Time tb 10000 – h ambient temperature range: -40°C 2% -20°C 10% 25°C 24% 60°C 34% 80°C 24% 100°C 5% >120°C 1%
3.1 Absolute Maximum Ratings (cont’d)
-40 /g176C /g163 Tj /g163 150 /g176C # Parameter Symbol Limit Values Unit Conditions min. max.
V1.2 Data Sheet 7 2002-08 Within the functional range the device works according to the functional description. However parameters may exceed the values given in the Characteristics.
3.2 Functional Range
# Parameter Sym- bol Limit Values Unit Conditions min. typ. max. F1 Supply voltage UZP 4.5 14.0 18 V – – – 26.5 V t < 5 min. ––4 . 5 V UST /g163 0.3 V; Reset = Low; Enable = Low; VR and MR off F2 Input capacitor CUZP 0.33 3.3 – /g109F TU = 20 /g176C UN = 63 V Typ. = MKT Case Temperature TC -40 – 125 /g176C P-DSO-20-12 Junction Temperature Tj -40 150 175 /g176C /g176C life time short time1) F5 Thermal resistance junction-ambient Rthja – 40 – K/W P-DSO-20-12 minimum footprint F6 Thermal resistance junction-case Rthjc – – 2.4 K/W P-DSO-20-12 1) Parameter may deviate in the temperature range Tj = 150 /g176C … 175 /g176C Total operation time max. 50 h for temperature range Tj > 150 /g176C
Block Description and Electrical Characteristics V1.2 Data Sheet 8 2002-08
4 Block Description and Electrical Characteristics
4.1 General
4.2 Oscillator
A 16 kHz oscillator is used as time base for the 1 kHz clock. An independent clock supervision circuit supervises the oscillator. If the oscillator clock is missing the error flag is set. Characteristics
6 V /g163 UZP /g163 18 V, -40 /g176C /g163 Tj /g163 +150 /g176C, if not otherwise specified
# Parameter Sym- bol Limit Values Unit Conditions min. typ. max.
4.1.1 Power consumption
IUZP –71 5 m A UZP = 16 V, IUST = 800 mA, VR on, SILA on, EN, RES1, RES2 = High
4.1.2 Overtemperature
Tab 150 – – /g176C Tj > Tab Characteristics Internal Oscillator # Parameter Sym- bol Limit Values Unit Conditions min. typ. max. 4.2.1 Frequency fOSZ 14.4 13.6 17.6 18.4 kHz kHZ UZP /g179 6 V
4.7 V /g163 UZP < 6 V
4.2.2 Clock supervision tCLUE – 120 – /g109s error if
tLow or tHigh > tCLUE 4.2.3 Logic time base tCLK 0.9 1 1.1 ms Period
Block Description and Electrical Characteristics V1.2 Data Sheet 9 2002-08
4.3 Charge Pump
The integrated charge pump requires an external capacitor at pin UCP. The charge pump voltage is typically 15 V. It is internally used for the voltage regulator only. It is only intended for internal function and may not be used for any external loads. The output voltage is short circuit protected against the supply voltage. Characteristics Charge Pump 6 V /g163 UZP /g163 18 V, -40 /g176C /g163 Tj /g163 +150 /g176C, if not otherwise specified # Parameter Sym- bol Limit Values Unit Conditions min. typ. max.
4.3.1 Power up time tCP –1 0 – m s UZP = 6 V; CCP = 68 nF;
U =0 . 9/g180UCPmax
4.3.2 Charge pump voltage UCP – 15 22 V Regulator on
4.3.3 Frequency fCP 1.4 3.2 – MHz –
Block Description and Electrical Characteristics V1.2 Data Sheet 10 2002-08
4.4 Voltage Regulator
The 5 V low drop linear regulator can supply up to 800 mA current. The regulator requires an output capacitor. The linear regulator is equipped with overcurrent protection and its own overtemperature protection. The linear element consists of 2 anti-serial DMOS transistors. In case of low input supply voltage this avoids discharging of the output capacitor. The output voltage UST is supervised for over- and undervoltage. UST output has to be connected externally to the sense input USTS. If over- or undervoltage condition is detected the Reset outputs RES1 and RES2 are logical low. For a detailed description of the reset logic please see Chapter 4.9. Characteristics Voltage Regulator # Parameter Sym- bol Limit Values Unit Conditions min. typ. max.
4.4.1 Nominal output
4.95 4.925 5.00 5.00 5.05 5.075 V V UZP = 14 V; IST = 400 mA; Output capacitor as defined in 4.4.11; on wafer level Tj = 25 /g176C P-DSO-20-12
4.4.2 UST load current IST – – 800 mA –
4.4.3 Line variation /g68UST –– /g12450/g124mV Tj = 25 /g176C; 6.0 V /g163 UZP /g163 18 V; IST = 600 mA; capacitor as defined in 4.4.11; dUZ/dt < 1 V//g109s
Block Description and Electrical Characteristics V1.2 Data Sheet 11 2002-08
4.4.4 Load variation /g68UST –– /g12450/g124mV Tj = 25 /g176C; UZP = 14 V;
0 mA /g163 IST /g163 800 mA; capacitor as defined in 4.4.11; dIST/dt /g163 1 mA//g109s
4.4.5 Temperature
/g68UST – /g12450/g124/g124100/g124mV UZP = 14 V; IST = ISTmax; -40 /g176C /g163 Tj /g163 150 /g176C; capacitor as defined in 4.4.11; for die mounted in a hybrid: d TU/dt /g163 10 K/s for P-DSO-20-12: dTG/dt /g163 5 K/min.
4.4.6 Long time drift /g68UST
–– /g12450/g124mV UZP /g163 UZPmax.; 0 mA /g163 IST /g163 ISTmax.; -40 /g176C /g163 Tj /g163 150 /g176C; tb = 10000 h, see conditions M13.
4.4.7 Overall output
4.4.6
4.4.8 Power Supply
/g68USTss –– /g12425/g124mV 0 Hz /g163 fUST /g163 10 kHz; capacitor as defined in 4.4.11;
7 V /g163 UZP /g163 24 V
4.4.9 Series Resistor RDSon –
1.7 2.7 /g87 /g87 Tj = 25 /g176C Tj = 150 /g176C UCP > 15 V; UZP = 6 V; IST = 800 mA
4.4.10 Maximum output
current (output shorted) IK 0.8 – 1.6 A UCP > 15 V; UST = 0 V;
4.5 V /g163 UZP /g163 18 V
4.4.11 Load capacitor at
CUST 3.3 – 150 /g109F TU = 20 /g176C; UN = 25 V; Type ETQW Roederstein Z –4– /g87 f = 100 kHz; TU = 20 /g176C
4.4.12 UST off voltage USTRest – – 400 mV IST = 0 mA
4.4.13 Clamping
UZST 5.5 – 7 V clamping voltage at I = 100 mA Characteristics Voltage Regulator (cont’d) # Parameter Sym- bol Limit Values Unit Conditions min. typ. max.
Block Description and Electrical Characteristics V1.2 Data Sheet 12 2002-08
4.5 Enable-Output EN
The open collector enable output EN informs the system about any error condition. Any error except a detected supply under-voltage will set the EN output Low. Of cause for long under-voltage at the supply line, soon the UST output capacitor will be discharged and this will cause UST under-voltage and therefore EN Low. The time depends on the load and the output capacitor. The EN is an open collector output. It is short circuit protected to UST. After power up when the first watchdog edges at WD1 a WD2 are detected the Enable output is switched into High state. Characteristics EN Output # Parameter Symbol Limit Values Unit Conditions min. typ. max.
4.5.1 Output Low voltage UL –
0.4 0.2 V V IL /g163 10 mA IL /g163 1 mA
4.5.2 Reverse current IR ––5 /g109A UEN = 5 V
Block Description and Electrical Characteristics V1.2 Data Sheet 13 2002-08 Power Driver The TLE 6210/TLE 6211 includes 3 open drain outputs for loads up to 0.5 A: The two drivers VR and MR are intended for (valve and motor) relays, while the SILA/NSILA output is designed for a lamp. In the TLE 6210 GW the SILA output is available. The output goes low if the supply voltage UZP is no longer available – the DMOS is switched on automatically. In the TLE 6211 GW the NSILA has the inverted polarity related to SILA. In bare dice both outputs SILA and NSILA can be used.
4.6 Valve Relay Output VR
The valve relay output VR is switched On after the power up reset and valid watchdog signals. The driver has an open drain configuration and can supply up to 500 mA. The output is protected against overtemperature and overcurrent. The output is short circuit protected to UZ. The output stage is equipped with its own overtemperature protection. In case of overvoltage at the supply UZP the output is switched off. However the output is not protected against overvoltages caused by switching inductive loads. Therefore externally a free wheeling diode is required as shown in the application diagram. The valve relay output VR is controlled by the internal supervision logic. If any watchdog errors or supply over-voltage is detected or the 5 V regulator is out of range, the VR is switched off (please see also Table 1 on Page 19 and Table 2 on Page 28). Characteristics Relay Driver Output VR 6 V /g163 UZP /g163 18 V, -40 /g176C /g163 Tj /g163 +150 /g176C, if not otherwise specified # Parameter Sym- bol Limit Values Unit Conditions min. typ. max. 4.6.1 Saturation Voltage UDS ––1 . 2 V Rlast /g179 35 /g87; IL /g163 0.5 A;
6 V /g163 UZP /g163 16 V
4.6.2 On state resistance RDSon ––2 . 4 /g87 Tj = 150 /g176C; IL = 0.5 A; UZP = 6 V
4.6.3 Overload detection
IK 500 – – mA –
4.6.4 Output leakage
IR – 0.5 mA mA UA /g163 16 V
16 V < UA /g163 60 V
4.6.5 Overtemperature
TK 150 – – /g176C –
Block Description and Electrical Characteristics V1.2 Data Sheet 14 2002-08
4.7 Motor Relay Driver
The motor relay driver MR is controlled by the MRA input signal and the internal control logic. A logic High at the MRA input switches the MR low side switch on, a logic Low signal switches it off. However the supervision logic overrules the MRA input condition. Please see also Table 1 on Page 19 and Table 2 on Page 28. The output is an open collector output and can sink up to 500 mA. It is protected against overtemperature and overcurrent and short circuit prove to UZ. Even the output is switched off by the supervision logic at UZP overvoltage externally a free wheeling diode is required to protect the output against switching off inductive loads. Characteristics Relay Driver Output MR # Parameter Sym- bol Limit Values Unit Conditions min. typ. max. 4.7.1 Saturation Voltage UDS ––1 . 2 V Rlast /g179 35 /g87; IL /g163 0.5 A; 4.7.2 On state resistance RDSon ––2 . 4 /g87 Tj = 150 /g176C; IL = 0.5 A; UZP = 6 V
4.7.3 Overload detection
IK 500 – – mA –
4.7.4 Output leakage
IR – 0.5 mA mA UA /g163 16 V
4.7.5 Overtemperature
TK 150 – – /g176C –
Block Description and Electrical Characteristics V1.2 Data Sheet 15 2002-08
4.7.1 Control Input MRA
The logic inputs MRA expect TTL-type signals from a /g109-controller with 5 V I/Os. An integrated pull-up resistor ensures that an open input is read High. Characteristics Control Inputs MRA # Parameter Sym- bol Limit Values Unit Conditions min. typ. max.
4.7.6 Internal pull-up
RWD 10 20 40 k/g870 V /g163 UE /g163 UST + 0.3 V 4.7.7 Input voltage Low UL -0.3 – 1.0 V – 4.7.8 Input voltage High UH 2.0 – UST + 1.0
4.7.9 Input current IH –– /g1245/g124/g109A UE = UST
––1 . 0 m A UST < UE /g163 UST + 1 V
Block Description and Electrical Characteristics V1.2 Data Sheet 16 2002-08
4.8 Error Lamp Output SILA and Lamp Relay Output NSILA
The SILA output is a 300 mA open collector output. It is available in the TLE 6210 G. SILA is a self-on output: It is switched on if the supply voltage is missing. The TLE 6211 G is equipped with the logically inverted NSILA output. NSILA is a 30 mA open collector output. It is intended to drive the lamp relay. In the dice version TLE 6211 C both outputs can be used. Both SILA and NSILA are intended to control a warning lamp. The output is controlled by the internal supervision logic and control signal at the SIA pin. A logic High at the SIA input switches SILA off and NSILA on. The supervision logic will switch on SILA if a watchdog timing violation is detected or the output voltage UST is out of range. Table 1 on Page 19 and Table 2 on Page 28 give an overview on the different errors. The SILA output is equipped with its own overtemperature protection. Characteristics Lamp Driver Output SILA # Parameter Sym- bol Limit Values Unit Conditions min. typ. max.
4.8.1 Saturation voltage USILA –
2.5 2.5 V I = 300 mA; UZP /g179 6 V I = 300 mA; UZP = 0 V
4.8.2 Overload detection
IK 3 0 0 ––m A –
4.8.3 Output leakage
IR – 0.1 mA mA USILA /g163 16 V
16 V < USILA < 42 V
4.8.4 Threshold voltage for
UZP 1–4 . 7 V USILA /g163 2.5 V; I = 300 mA
4.8.5 Overtemperature
TK 150 – – /g176C UZP /g179 6 V
Block Description and Electrical Characteristics V1.2 Data Sheet 17 2002-08
4.8.1 Control Input SIA
The logic inputs SIA expect TTL-type signals from a /g109-controller with 5 V I/Os. An integrated pull-up resistor ensures that an open input is read High. Characteristics Lamp-Relay Driver Output NSILA # Parameter Sym- bol Limit Values Unit Conditions min. typ. max.
4.8.6 On state resistance RDSon ––3 3 /g87 Tj = 150 /g176C; I = 30 mA;
4.8.7 Overload detection
IK 3 0 ––m A –
4.8.8 Output leakage
IR ––1 0 /g109A UNSILA /g163 42 V Characteristics Control Inputs SIA # Parameter Sym- bol Limit Values Unit Conditions min. typ. max.
4.8.9 Internal pull-up
RWD 10 20 40 k/g870 V /g163 UE /g163 UST + 0.3 V 4.8.10 Input voltage Low UL -0.3 – 1.0 V – 4.8.11 Input voltage High UH 2.0 – UST + 1.0
4.8.12 Input current IH –– /g1245/g124/g109A UE = UST
––1 . 0 m A UST < UE /g163 UST + 1 V
Block Description and Electrical Characteristics V1.2 Data Sheet 18 2002-08 Supervision The TLE 6210 and TLE 6211 are equipped with a complex supervision logic. The input voltage and the regulator output voltage is supervised. In addition two /g109-controller are supervised by independent watchdog circuits.
4.9 Overvoltage and Undervoltage
Both the supply voltage UZP and the output voltage UST are supervised for over- and undervoltage. In case any undervoltage or overvoltage condition at UST or UZP is detected, the reset outputs RES1 and RES2 are switched to low state. RES1 and RES2 are not controlled by the watchdog logic. To supervise the output voltage UST an independent bandgap from the reference bandgap is used. The reset outputs RES1 and RES2 are together controlled by the UST reset logic and the supply undervoltage lockout (UVLO) and overvoltage lockout (OVLO). A logic High at the RES1 and RES2 indicates normal operation. The outputs are open collector type outputs with integrated pull-up resistors to UST. Even when the UST voltage drops, the reset outputs RES1 and RES2 remain low (< 0.4 V). Both undervoltage and overvoltage detection of UST and UZP use a voltage hysteresis to avoid any reset toggling. Undervoltage and Overvoltage Detection UST The UST output voltage has to be externally connected to the USTS sense input. To be able to detect also wrong output voltages causes by a malfunction of the related bandgap reference for supervision an independent bandgap is used. As soon as any reset condition is detected the RES1 and RES2 go low.
4.9.1 Undervoltage Lockout (UVLO) and Overvoltage Lockout (OVLO)
The supply voltage UZP is supervised as well. If the voltage rises above the upper threshold value of 19.5 V reset is asserted. When an undervoltage occurs, after some time the output voltage will drop below the reset threshold and a reset is asserted. The undervoltage lockout is only valid during power up. Both the OVLO and the UVLO threshold use a hysteresis to avoid reset glitches. In addition the OVLO is digitally filtered. Overvoltage below 2 to 3 clock cycles (equals typical 2 µs or 3 µs) are neglected to avoid resetting the system when any inductive load is switched off.
Block Description and Electrical Characteristics V1.2 Data Sheet 19 2002-08 When the undervoltage condition at UST or UZP is no longer detected a reset reaction time of typical 52 ms (52 clock cycles) is started. After this time the reset signal is set high. Z: high impedance * In the application the voltage is undefined as regulator is off Table 1 Truth Table Overvoltage and Undervoltage Supervision The table assumes that no other error is detected, especially no watchdog failure and no clock failure. Supply voltage UZP Regulator Voltage UST SILA NSILA MR VR EN RES 1 RES 2 Regulator ok ok = SIA = not SIA = not MRA LZHO N ok under- voltage LZ ZZLL O N normal over- voltage LZ ZZLHO N under- voltage under- voltage LZ ZZZ * L O F F under- voltage ok = SIA = not SIA not MRA LH HO N over- voltage x = L Z ZZZ * L O F F
Block Description and Electrical Characteristics V1.2 Data Sheet 20 2002-08
4.9.2 Under- and Overvoltage Reset Behavior
Characteristics Supervision of UZP, UST # Parameter Symbol Limit Values Unit Conditions min. typ. max. UZP-Undervoltage
4.9.1 UZP undervoltage
UZPU 5.2 5.3 5.4 V UST off
4.9.2 UZP undervoltage
UH 20 – 50 mV UZPU(ON) = UZPU(OFF) + UH UZP-Overvoltage
4.9.3 UZP overvoltage
UZUE 18.75 19.5 20.25 V Outputs NSILA, VR, MR, UST off UZP 12V 5.3V t UST 4.6V t t t RES1 RES2 52ms
Block Description and Electrical Characteristics V1.2 Data Sheet 21 2002-08
4.9.4 UZP overvoltage
UH 0.5 – 1.0 V UH = UZUE(on) - UZUE(off)
4.9.5 UZP overvoltage
1.8 3.4 /g180 tCLK ms UZP /g179 overvoltage threshold toff 2 1.8 3.4 /g180 tCLK ms UZP < overvoltage threshold UST-Undervoltage
4.9.6 UST undervoltage
USTU 4.5 4.6 4.7 V RES1, RES2 = low
4.9.7 UST undervoltage
UH 20 – 50 mV USTU(on) = USTU(off) + UH UST-Overvoltage
4.9.8 UST overvoltage
USTUE 5.3 5.4 5.5 V Error flag is set
4.9.9 UST overvoltage
UH 20 – 50 mV USTUE(ON) = USTUE (off) - UH
4.9.10 U STS input
ISTS 0.94 1.5 2.2 mA USTS = 6 V Reset timing
4.9.11 Reset delay time tRH –
46.35 58.85 /g180 tCLK ms UZP /g179 5.4 V UST /g179 4.75 V 1) Hysteresis guaranteed by design. Characteristics Supervision of UZP, UST (cont’d) # Parameter Symbol Limit Values Unit Conditions min. typ. max.
Block Description and Electrical Characteristics V1.2 Data Sheet 22 2002-08
4.10 Reset Outputs RES1, RES2
The two reset outputs RES1 and RES2 are open collector outputs with integrated pull- up resistor of typical 10 k /g87 to UST. Both outputs are protected against short circuits to UST. Characteristics RES1 and RES2 # Parameter Sym- bol Limit Values Unit Conditions min. typ. max.
4.10.1 Output low
UL – 0.4 0.4 V V IL = 0.8 mA; UST = 1.8 V IL = 2 mA; UST = 4.5 V 1.8 V /g163 UST /g163 4.5 V
4.10.2 Output high
- 0.1 – UST V RL /g179 10 M/g87
4.10.3 Internal pull-up
RRES 51 0 2 0 k/g870 V /g163 UA /g163 UST + 0.3 V
Block Description and Electrical Characteristics V1.2 Data Sheet 23 2002-08
4.11 Watchdog
To supervise the operation of 2 /g109-processors watchdog logic for two input signals is integrated. The logic expects at each WD1 and WD2 rectangular signals with 10 ms high and 10 ms low time. Deviations from the expected time are counted as errors and influence the output signals. A digital filter suppresses noise or pulses below 3 clock cycles (typ. 3 ms). The detection ciruit is described in Figure 12. After power up and 1or 2 valid watchdog edges the WD logic enables the output Drivers. Figure 5 Enable output EN after correct watchdog signals at WD1 and WD2 are present; WD1 and WD2 start with logic Low Figure 6 Enable output EN after correct watchdog signals at WD1 and WD2 are present; WD1 and WD2 start with logic High WD1 WD2 EN 10ms 3* tCLK after the 2nd WD-edge (falling edge) wd-start-up-with Low AD 04/02 WD1 WD2 EN 3 * tCLK after 1st. WD edge 10ms wd-start-up-with High AD 04/02
Block Description and Electrical Characteristics V1.2 Data Sheet 24 2002-08 The logic expects the time between two clock edges between 3 and 15 clock-cycles. If this window is not met, the outputs VR, MR and NSILA are switched off, SILA is switched on and the enable output goes low. An internal counter ( seeFigure 12) includes a 4 bit counter. Each time the value 15 is reached a dominant counter reset signal is generated at the output "=15". This pulse is generated continuously at after the last valid watchdog pulse was detected. When internal resets and watchdog edges occur at the same time, the internal reset is dominant. Figure 7 Missing watchdog signals cause EN low 15* tCLK + Delay = 15* tCLK + 3* tCLK 10ms WD1 WD2 EN Delay (3* tCLK) t > 16 *tCLK wd-controls-en-2 AD 04/02
Block Description and Electrical Characteristics V1.2 Data Sheet 26 2002-08 Any watchdog high or low time above 15 ms influences the enable (EN) and the VR output.If the time after the last watchdog edge exceeds 120 clock cycles - typical 120 ms- an error flag is set. This flag can only be removed by powering down the IC. Figure 10 Missing watchdog signals for more than 120 * t CLK (typ. 120ms) sets the failure register An integrated pull-up resistor to UST in the WD1 and WD2 inputs ensures to detect a permanent logic High in case the input is open. 10ms WD1 WD2 EN (15+3) * tCLK 112 * tCLK + Delay = 112 * t CLK+ 3 * tCLK ) Counter reset 16 * tCLK set error flag set-error-flag AD 03/02
Block Description and Electrical Characteristics V1.2 Data Sheet 27 2002-08 Characteristics WD1, WD2 # Parameter Sym- bol Limit Values Unit Conditions min. typ. max.
4.11.1 Internal pullup
RWD 10 20 40 k/g87 0 V /g163 UE /g163 UST + 0.3 V 4.11.2 Input voltage Low UL -0.3 – 1.0 V – 4.11.3 Input voltage High UH 2.0 – UST + 1.0
4.11.4 Input current IH –– /g1245/g124/g109A UE = UST
––1 . 0 m A UST < UE /g163 UST + 1 V Characteristics Watchdog # Parameter Sym- bol Limit Values Unit Conditions min. typ. max.
4.11.5 Release
tON 1– 2 /g180 tCLK Number of valid Watchdog input clock edges
4.11.6 Closed
tpulse – 2.25 1.8 3.3 3.3 /g180 tCLK ms ms The distance between clock edges is at least tpulse equals: periodically pulse
4.11.7 Open
tVR – 13.5 17.6 /g180 tCLK ms if the edge distance /g68t > tVR, VR is switched off equals
4.11.8 Error flag
tFSP – 108 120 120 132 /g180 tCLK ms if /g68t > tFSP, the error flag is set. equals
Block Description and Electrical Characteristics V1.2 Data Sheet 28 2002-08
4.11.1 Watchdog Logic
Table 2 and Figure 11 show the watchdog logic. figure 12 shows the logic implementation Z: High impedance Watchdog WD1, WD2 Time between Edges Clock SILA NSILA MR VR EN RES1/2 Error Flag ok ok = SIA = not SIA = not MRA LZH L < 3 * tCLK ok L Z Z Z L H L > 15 * tCLK ok L Z Z Z L H L > 120 * tCLK ok L Z Z Z L H H ok error L Z Z Z L H H Table 2 Watchdog and Clock Supervision Truth Table The table assumes that no other error is detected, especially no undervoltage or overvoltage at the supply and regulator output.
Block Description and Electrical Characteristics V1.2 Data Sheet 29 2002-08 Figure 11 Watchdog Violation Reaction t1: No watchdog signals at WD1 or WD2 t2: Normal operation. EN is going high after the first watchdog edges at WD1 and WD2 are detected. t3: Watchdog open window time exceeded: but below 120 *t CLK (typ. 120 ms). Error Flag is not set. t4: Watchdog time too short (below closed window time) t5: Normal operation WD1 t EN t WD2 t VR t SILA t NSILA t MR t t 1 t 2 t 3 t 4 t 5
Block Description and Electrical Characteristics V1.2 Data Sheet 30 2002-08 Figure 12 Logic Diagram: Detection of Watchdog Edges. The watchog signal is clocked through the shiftregister. The output condition of the edge detection circuit above is true for register state 111000 and 000111. 3 clks after the rising edge or falling edge of WDx the logic below will get a pulse of 1 clk length. Figure 13 Block Diagram Watchdog Logic
6 BIT
/g1791 /g1791 /g1791 wd-detect AD06/02 CLK J K C WD1 WD2 CLK Counter C R overvoltage at UST (active H) Set Error register 1 sets VR high ohmic; ENQ on /g179120 =15 D C Q Q“ 1 “ Undervoltage reset (low active) /g179/g49/g53 CLK CLK CLK TLE6210-wd-logic AD 04/02 D C R Q Q R Q J K C Q
V1.2 Data Sheet 31 2002-08
5 Application Diagram
Figure 14 Application Diagram Linear Regulator Reset detection UZP UVLO and OVLO detection USTS under- and overvoltage reset detection TLE6210-app-diagram AD 11.7.02 UST USTS UZP GND RES1 RES2 EN PGND Window watchdog SIA MRA WD1 WD 2 Oscillator Clock super- vision Charge Pump UCP SupervisionLogic GND CCP 68nF Logic GND Power GND U Bat UST from Microcontroller from Microcontroller from Microcontroller from Microcontroller to Microcontroller to Microcontroller to Microcontroller PGND SILA PGND NSILA PGND MR PGND VR U Bat U Bat U Bat U Bat TLE6210/1
V1.2 Data Sheet 32 2002-08
6 Package Outlines
Does not include plastic or metal protrusion of 0.15 max. per side 1 x 45˚ (Mold) 15.9 1)±0.15 A -0.2 (Metal) 13.7 0 +0.1 +0.130.4 20 11
0.25 M A
1.27 1.2 -0.3 (Heatslug) 15.74 ±0.1 (Metal) 0.25 Heatslug(Mold) 20x 3.2 14.2 ±0.3 ±0.1 0.95 3.25 3.5 MAX. 0.1 1.3 ±0.1 -0.02+0.07 6.3 0.25 ±0.15 2.8 11 1) B (Metal) 5.9 B ±0.1 ±0.15 5˚±3˚ P-DSO-20-12 (Plastic Dual Small Outline Package) GPS05791 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mmSMD = Surface Mounted Device
Revision History
V1.2 Data Sheet 33 2002-08 Version Date Major Changes V0.0 2002-08 Advanced Information Data Sheet TLE 6210, TLE 6211 Device is a replacement of the TLE 5200/TLE 5201 with the following deviations form the specification from 1998-01-21. Devices are only available in the P-DSO-20-12 package or as bare dice The data sheet structure was changed and some chapters where moved. Parameter reference numbers are changed now: TLE 5200/01 TLE 6210/11 Control input SIA 1.x 4.8.x Control input MRA 1.x 4.7.x Enable 2.x 4.5.x Reset outputs 3.x 4.10.x SILA/NSILA 4.x 4.8.x VR 5.x 4.6.x MR 5.x 4.7.x Voltage supervision 6.x 4.9.x Oscillator 7.x 4.2.x Watchdog 8.x 4.11.x Charge Pump 9.x 4.3.x 5 V Regulator 10.x 4.4.x General information 10.x 4.1.x Absolute Maximum Ratings: Digital I/Os (reference M6, M7, M8) changed to -0.5 to 7 V V0.1 2001-11 Update truth table V0.2 2002-04 increase error flag detection time t FSP from 112 clock cycles to 120 clock cycles (parameter 4.11.8) Add of logic block diagram (figure 12) and watchdog timing diagrams (figure 5 to 10)
V1.2 Data Sheet 34 2002-08 Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Characteristics show the deviation of parameter at the given supply voltage and junction temperature. Typical values show the typical parameters expected from manufacturing. V1.0 2002-07 Data sheet Remove pad / chip information from the datasheet ESD value SILA, MR, VR,UZP 4kV Update typ. value 4.3.3 Extend and correct block description at chapters 4.4; 4.6; 4.7; 4.8 Table 1: SILA function at overtemperature changed Table 2: timings as a function of t CLK Figure 11, t3: corect timing Chapter 4.11: Extend description; add figure 12: Detection of watchdog edges Appplciation diagram: replace free wheeling zener diodes at MR and VR relay by normal diodes. V1.1 2002-07 change device suffixes: bare dice: TLE621x C packaged: TLE621x G V1.2 2002-08 Table 1 and text chapter 4.8: correct NSILA at overvoltage Change long term drift 4.4.6 to 10000h Add a more detailed description to figure 12. Version Date Major Changes
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