TLE6208-3-G

TLE6208-3-G INFINEON | Alldatasheet

Document overview

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Technical content

Triple-Half-Bridge TLE 6208-3 G Data Sheet 1 2001-05-10

1 Overview

1.1 Features

• Three Half-Bridges  Optimized for DC motor management applications  Delivers up to 0.6 A continuous, 1.2 A peak current R DS ON ; typ. 0.8 Ω , @ 25°C per switch  Output: short circuit protected and diagnosis  Overtemperature-Protection with hysteresis and diagnosis  Standard SPI-Interface/Daisy chain capable  Very low current consumption in stand-by (Inhibit) mode (typ. 10µA for power and 2µA for logic supply, @ 25°C)  Over- and Undervoltage-Lockout  CMOS/TTL compatible inputs with hysteresis  No crossover current  Internal clamp diodes  Enhanced power P-DSO-Package  Programming compatibility to the TLE 5208-6 G Functional Description The TLE 6208-3 G is a fully protected Triple-H alf-B ridge-D river designed specifically for automotive and industrial motion control applications. The part is based on the Siemens power technology SPT® which allows bipolar and CMOS control circuitry in accordance with DMOS power devices existing on the same monolithic circuitry. In motion control up to 2 actuators (DC-Motors) can be connected to the 3 halfbridge- outputs (cascade configuration). Operation modes forward (cw), reverse (ccw), brake and high impedance are controlled from a standard SPI-Interface. The possibility to control the outputs via software from a central logic, allows limiting the power dissipation. So the standard P-DSO-14-package meets the application requirements and saves PCB-Board-space and cost. Furthermore the build-in features like Over- and Undervoltage-Lockout, Over-Temperature-Protection and the very low quiescent current in stand-by mode opens a wide range of automotive- and industrial-applications. Type Ordering Code Package TLE 6208-3 G Q67006-A9334 P-DSO-14-9

1.2 Pin Configuration (top view)

V CC SV P-DSO-14-9 AEP02438 GND CSN

1.3 Pin Definitions and Functions

Pin No. Symbol Function 1G N D Ground; Reference potential; internal connection to pin 7, 8 and 14; cooling tab; to reduce thermal resistance place cooling areas on PCB close to these pins. 2O U T 3 Halfbridge-Output 3; Internally contected to Highside-Switch 3 and Lowside-Switch 3. The HS-Switch is a Power-MOS open drain with internal reverse diode; The LS-Switch is a Power-MOS open source with internal reverse diode; no internal clamp diode or active zenering; short circuit protected and open load controlled. VS Power Supply; needs a blocking capacitor as close as possible to GND Value: 22 µF electrolytic in parallel to 220 nF ceramic. 5D I Serial Data Input; receives serial data from the control device; serial data transmitted to DI is an 16bit control word with the Least Significant Bit (LSB) being transferred first: the input has an active pull down and requires CMOS logic level inputs; DI will accept data on the falling edge of CLK-signal; see Table Input Data Protocol. 4C S N Chip-Select-Not Input; CSN is an active low input; serial communication is enabled by pulling the CSN terminal low; CSN input should only be transitioned when CLK is low; CSN has an internal active pull up and requires CMOS logic level inputs. 6C L K Serial Clock Input; clocks the shiftregister; CLK has an internal active pull down and requires CMOS logic level inputs. 7, 8, 14 GND Ground; see pin 1. 9D O Serial-Data-Output; this 3-state output transfers diagnosis data to the control device; the output will remain 3-stated unless the device is selected by a low on Chip-Select-Not (CSN); see Table Diagnosis Data Protocol.

10 INH Inhibit Input; has an internal pull down;

device is switched in standby condition by pulling the INH terminal low. VCC Logic Supply Voltage; needs a blocking capacitor as close as possible to GND; Value: 10 µF electrolytic in parallel to 220 nF ceramic. 12 OUT2 Halfbridge-Output 2; see pin 2. 13 OUT1 Halfbridge-Output 1; see pin 2.

1.4 Functional Block Diagram

16 Bit

1,7,8,14 GND OUT 2 OUT 1 OUT 3 DO CLK DI CSN INH V CC S V AEB02439 DRV1 DRV2 DRV3

1.5 Circuit Description

Figure 2 shows a block schematic diagram of the module. There are 3 halfbridge drivers on the right-hand side. An HS driver and an LS driver are combined to form a halfbridge driver in each case. The drivers communicate via the internal data bus with the logic and the other control and monitoring functions: undervoltage (UV), overvoltage (OV), overtemperature (TSD), charge pump and fault detect. Two connection interfaces are provided for supply to the module: All power drivers are connected to the supply voltage VS. These are monitored by overvoltage and undervoltage comparators with hysteresis, so that the correct function can be checked in the application at any time. The logic is supplied by the V CC voltage, typ. with 5 V. The V CC voltage uses an internally generated Power-On Reset (POR) to initialize the module at power-on. The advantage of this system is that information stored in the logic remains intact in the event of short- term failures in the supply voltage V S. The system can therefore continue to operate following VS undervoltage, without having to be reprogrammed. The “undervoltage” information is stored, and can be read out via the interface. The same logically applies for overvoltage. “Interference spikes” on VS are therefore effectively suppressed. The situation is different in the case of undervoltage on the VCC connection pin. If this occurs, then the internally stored data is deleted, and the output levels are switched to high-impedance status (tristate). The module is initialized by VCC following restart (Power-On Reset = POR). The 16-bit wide programming word or control word (see Table Input Data Protocol) is read in via the DI data input, and this is synchronized with the clock input CLK. The status word appears synchronously at the DO data output (see Table Diagnosis Data Protocol). It is also possible to connect two TLE 6208-3 G in a daisy chain configuration. The DO data output of one device is connected with the DI data input of the second device. In this configuration these two devices are controlled with a single CSN chip select and using a 32-bit wide control word. The transmission cycle begins when the chip is selected with the CSN input (H to L). If the CSN input changes from L to H then the word which has been read in becomes the control word. The DO output switches to tristate status at this point, thereby releasing the DO bus circuit for other uses. The INH inhibit input can be used to cut off the complete module. This reduces the current consumption to just a few µA, and results in the loss of any data stored. The output levels are switched to tristate status. The module is reinitialized with the internally generated POR (Power-On Reset) at restart. This feature allows the use of this module in battery-operated applications (vehicle body control applications).

Every driver block from DRV 1 to 3 contains a low-side driver and a high-side driver. Both drivers are connected internally to form a half-bridge at the output. This reduction of output pins was necessary to meet the small P-DSO-14 package. When commutating inductive loads, the dissipated power peak can be significantly reduced by activating the transistor located parallel to the internal freewheeling diode. A special, integrated “timer” for power ON/OFF times ensures that there is no crossover current. Input Data Protocol Diagnosis Data Protocol BIT BIT

15 OVLO on/off 15 Power supply fail

13 Overcurrent SD on/off 13 Overload

6 HS-Switch 3 6 Status HS-Switch 3

5 LS-Switch 3 5 Status LS-Switch 3

4 HS-Switch 2 4 Status HS-Switch 2

3 LS-Switch 2 3 Status LS-Switch 2

2 HS-Switch 1 2 Status HS-Switch 1

1 LS-Switch 1 1 Status LS-Switch 1

0 Status Register Reset 0 Temp. Prewarning H=O N L=O F F H=O N L=O F F

Fault Diag.-Bit Result Overcurrent (load) 13 Only the failed output is switched OFF. Function can be deactivated by bit No. 13. Short circuit to GND (high-side-switch) 13 Only the failed output is switched OFF. Function can be deactivated by bit No. 13. Short circuit to V S (low-side-switch) 13 Only the failed output is switched OFF. Function can be deactivated by bit No. 13. Temperature warning 0 Reaction of control device needed. Temperature shut down (SD) – All outputs OFF. Temperature warning is set before. Underload/Openload 14 Reaction of control device needed. Undervoltage lockout (UVLO) 15 All outputs OFF. Overvoltage lockout (OVLO) 15 All outputs OFF. Function can be deactivated by bit No. 15. H = failure; L = no failure.

Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2 Electrical Characteristics

2.1 Absolute Maximum Ratings

Parameter Symbol Limit Values Unit Remarks min. max. Supply voltage VS – 0.3 40 V – Supply voltage VS – 1 – V t < 0.5 s; IS > – 2 A Logic supply voltage VCC – 0.3 5.5 V 0 V < VS < 40 V Logic input voltages (DI, CLK, CSN, INH) VI – 0.3 5.5 V 0 V < VS < 40 V 0 V < VCC < 5.5 V Logic output voltage (DO) VDO – 0.3 5.5 V 0 V < VS < 40 V 0 V < VCC < 5.5 V Output voltage (OUT 1-3) VOUT – 0.3 40 V 0 V < VS < 40 V Output current (cont.) IOUT1-3 –– A internal limited Output current (peak) IOUT1-3 –– A internal limited Note: Current limits are mentioned in the overcurrent section of electrical charateristics Junction temperature Tj – 40 150 °C – Storage temperature Tstg – 50 150 °C – ESD voltage, human body model, according to:  MIL STD 883D,  ANSI EOS\\ESD S5.1  JEDEC JESD22-A114 VESD-HBM –– 4kV all pins VESD-HBM- OUT –– 8kV only pins 2, 12 and 13 (outputs) ESD voltage, mashine model, according to:  ANSI EOS\\ESD S5.2  JEDEC JESD22-A115 VESD-MM –– 300V all pins

Note: In the operating range, the functions given in the circuit description are fulfilled.

2.2 Operating Range

Parameter Symbol Limit Values Unit Remarks min. max. Supply voltage VS VUV OFF 40 V After VS rising above VUV ON Supply voltage slew rate d V S /dt – 10 V/ µs – Logic supply voltage VCC 4.75 5.50 V – Supply voltage increasing VS – 0.3 VUV ON V Outputs in tristate Supply voltage decreasing VS – 0.3 VUV OFF V Outputs in tristate Logic input voltage (DI, CLK, CSN, INH) VI – 0.3 VCC V – SPI clock frequency fCLK – 1M H z – Junction temperature Tj – 40 150 °C – Thermal Resistances Junction pin Rthj-pin – 30 K/W measured to pin 1, 7, 8, 14 Junction ambient RthjA – 65 K/W –

2.3 Electrical Characteristics

8V< VS < 40 V; 4.75 V <V CC < 5.25 V; INH = High; all outputs open; – 40 °C< Tj < 150°C; unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max. Current Consumption Quiescent current IS – 82 0 µA INH = Low; VS = 13.2 V Tj = 25°C Quiescent current IS –– 30 µA INH = Low; VS = 13.2 V; Logic-Supply current ICC – 21 0 µA INH = Low Logic-Supply current ICC – 1 2 mA SPI not active Supply current IS – 25m A – Over- and Under-Voltage Lockout UV-Switch-ON voltage VUV ON – 6.5 7 V VS increasing UV-Switch-OFF voltage VUV OFF 5.6 6.1 6.6 V VS decreasing UV-ON/OFF-Hysteresis VUV HY – 0.4 – V VUV ON – VUV OFF OV-Switch-OFF voltage VOV OFF 34 37 40 V VS increasing OV-Switch-ON voltage VOV ON 30 33 36 V VS decreasing OV-ON/OFF-Hysteresis VOV HY – 4 – V VOV OFF – VOV ON

Static Drain-Source-On Resistance Source (High-Side) IOUT = – 0.5 A RDS ON H – 0.8 0.95 Ω 8V < VS < 40 V Tj = 25 °C – 1.6 Ω 8V < VS < 40 V 1 – Ω V SO F F < VS ≤ 8V Tj = 25 °C – 2 Ω V SO F F < VS ≤ 8V Sink (Low-Side) IOUT = 0.5 A RDS ON L – 0.75 0.9 Ω 8V < VS < 40 V Tj = 25 °C – 1.5 Ω 8V < VS < 40 V 1 – Ω V SO F F < VS ≤ 8V Tj = 25 °C – 2 Ω V SO F F < VS ≤ 8V Leakage Current Source-Output-Stage 1 to 3IQLH – 5 – 1 – µA V OUT1-3 = 0 V Sink-Output-Stage 1 to 3 IQLL – 150 300 µA V OUT1-3 = VS Overcurrent Source shutdown thresholdISDU – 2 – 1.3 – 1A – Sink shutdown threshold ISDL 11 . 2 2A – Current limit IOCL – 2.4 4 A sink and source Shutdown delay time tdSD 10 28 40 µs sink and source

2.3 Electrical Characteristics (cont’d)

8V< VS < 40 V; 4.75 V <VCC < 5.25 V; INH = High; all outputs open; – 40 °C< Tj <1 5 0°C; unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Open Circuit/Underload Detection Detection current IOCD 15 30 45 mA – Delay time tdOC 200 370 600 µs – Output Delay Times; V S = 13.2 V; R Load = 25 Ω (device not in stand-by for t > 1 ms) Source ON tdO NH – 82 0 µs – Source OFF tdO F FH – 42 0 µs – Sink ON tdO NL – 72 0 µs – Sink OFF tdO F FL – 32 0 µs – Dead time tDH L 13 – µs tdO NL – tdO F FH Dead time tDL H 15 – µs tdO NH – tdO F FL Output Switching Times; V S = 13.2 V; R Load = 25 Ω (device not in stand-by for t > 1 ms) Source ON tON H – 52 0 µs – Source OFF tOFF H – 25 µs – Sink ON tON L – 2.0 10 µs – Sink OFF tOFF L – 1.5 5 µs – Clamp Diodes Forward Voltage Upper VFU – 0.9 1.3 V IF = 0.5 A Lower VFL – 0.9 1.3 V IF = 0.5 A 8V< VS < 40 V; 4.75 V <V CC < 5.25 V; INH = High; all outputs open; – 40 °C< Tj < 150°C; unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max.

H-input voltage thresholdVIH – 0.52 0.7 VCC – L-input voltage thresholdVIL 0.2 0.48 – VCC – Hysteresis of input voltageVIHY 50 200 500 mV – Pull down current II 5 25 100 µA V I = 0.2 × VCC Input capacitance C I – 10 15 pF 0 V < VCC < 5.25 V Note: Capacitances are guaranteed by design. SPI-Interface Delay Time from Stand-by to Data In/Power on Reset Setup time tset –– 100 µs – Logic Inputs DI, CLK and CSN H-input voltage thresholdVIH – 0.52 0.7 VCC – L-input voltage thresholdVIL 0.2 0.48 – VCC – Hysteresis of input voltageVIHY 50 200 500 mV – Pull up current at pin CSNIICSN – 50 – 25 – 10 µA V CSN = 0.7 × VCC Pull down current at pin DIIIDI 10 25 50 µA V DI = 0.2 × VCC Pull down current at pin CLKIICLK 10 25 50 µA V CLK = 0.2 × VCC Input capacitance at pin CSN, DI or CLK C I – 10 15 pF 0 V < VCC < 5.25 V Note: Capacitances are guaranteed by design. 8V< VS < 40 V; 4.75 V <VCC < 5.25 V; INH = High; all outputs open; – 40 °C< Tj <1 5 0°C; unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max.

H-output voltage level VDOH VCC – 1.0 V CC – 0.7 – V IDOH =1 m A L-output voltage level VDOL – 0.2 0.4 V IDOL = – 1.6 mA Tri-state leakage currentIDOLK – 10 0 10 µA VCSN =VCC 0V < VDO < VCC Tri-state input capacitanceC DO – 10 15 pF VCSN = VCC 0V < VCC < 5.25 V Note: Capacitances are guaranteed by design. Data Input Timing Clock period tpCLK 1000 – – ns – Clock high time tCLKH 500 – – ns – Clock low time tCLKL 500 – – ns – Clock low before CSN low tbef 500 – – ns – CSN setup time tlead 500 – – ns – CLK setup time tlag 500 – – ns – Clock low after CSN high tbeh 500 – – ns – DI setup time tDISU 250 – – ns – DI hold time tDIHO 250 – – ns – Input signal rise time at pin DI, CLK and CSN trIN – – 200 ns – Input signal fall time at pin DI, CLK and CSN tfIN – – 200 ns – 8V< VS < 40 V; 4.75 V <V CC < 5.25 V; INH = High; all outputs open; – 40 °C< Tj < 150°C; unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max.

DO rise time trDO – 50 100 ns C L = 100 pF DO fall time tfDO – 50 100 ns C L = 100 pF DO enable time tENDO – – 250 ns low impedance DO disable time tDISDO – – 250 ns high impedance DO valid time tVADO – 100 250 ns V DO < 0.2 V CC ; V DO > 0.7 V CC ; C L = 100 pF Thermal Prewarning and Shutdown Thermal prewarning junction temperature TjPW 120 145 170 °C – Temperature prewarning hysteresis ∆T – 30 – K – Thermal shutdown junction temperature TjSD 150 175 200 °C – Thermal switch-on junction temperature TjSO 120 – 170 °C – Temperature shutdown hysteresis ∆T – 30 – K – Ratio of SD to PW temperature TjSD/TjPW 1.05 1.20 –– – Note: Temperatures are guaranteed by design. The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25°C and the given supply voltage. 8V< VS < 40 V; 4.75 V <VCC < 5.25 V; INH = High; all outputs open; – 40 °C< Tj <1 5 0°C; unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max.

3 Timing Diagrams

Figure 3 Data Transfer Timing AET02177 0 12 3 4 5 6 7 89 1 0 11 12 13 14 15 0 1++ CSN CLK DI DO HS1 e.g. Old Data Actual Data time New Data Actual Status CSN High to Low & rising edge of CLK: DO is enabled. Status information is transferred to Output Shift Register CSN Low to High: Data from Shift-Register is transferred to Output Power Switches Actual Data Previous Status DI: Data will be accepted on the falling edge of CLK-Signal DO: State will change on the rising edge of CLK-Signal time time time time 40 12 3 5 6 7 89 1210 11 13 14 15 0 1

Figure 8 DO Enable and Disable Time AET02181 CSN tfIN rINt DO DO 10 ns tENDO ENDOt DISDOt tDISDO VCCto Pullup Pulldown to GND 10 kΩ 50% 50% 50% 0.7VCC CCV0.2 10 kΩ

Figure 9 Application Circuit Bias Inhibit Charge Pump Detect Fault- SPI 1,7,8,14 GND OUT 2 OUT 1 OUT 3 DO CLK DI CSN V CC S V AEB02441 DRV1 DRV2 DRV3 INH Pµ GND CCVRWD Q Reset Watchdog D TLE 4278G Ι D01 1N4001 D02 Z39 SC

10 Fµ47 nF

µ22 F C Q V S = 12V M M

4 Package Outlines

Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mmSMD = Surface Mounted Device P-DSO-14-9 (Plastic Dual Small Outline Package) GPS09222