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TLE5010

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GMR Based Angular Sensor V 0.9, May 2007

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D raft Preliminary Data Sheet, V 0.9, May 2007 TLE5010 GMR Based Angular Sensor Sensors

81726 München, Germany

© 2007 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Template: mc_a5_ds_tmplt.fm / 4 / 2004-09-15 TLE5010 Draft Revision History: 2007-05 V 0.9 Previous Version: - Page Subjects (major changes since last revision) We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: sensors@infineon.com

Preliminary Data Sheet 4 V 0.9, 2007-05

Preliminary Data Sheet 5 V 0.9, 2007-05

Type Marking Ordering Code Package TLE5010 5010-2 tbd. PG-DSO-8 GMR Based Angular Sensor TLE5010 PG-DSO-8-3 Preliminary Data Sheet 6 V 0.9, 2007-05 Draft

1 Overview

1.1 Features

G iant M agnetoR esistance based principle Integrated magnetic field sensing for angle measurement Full 0 - 360° angle measurement Highly accurate single bit SD-ADC 1 6 bit representation of sine / cosine values on the interface Bidirectional SSC interface up to 2 Mbit/s 3 pin SSC interface, SPI compatible with open drain ADCs and filters are synchronized with external commands via SSC Test resistors for simulating angle values Core supply voltage 2.5 V 0 . 2 5 µm CMOS technology Automotive qualified: -40°C to +150°C (Junction Temperature) Latch up immunity according JEDEC standard E S D > 2 kV (HBM) Green package with lead-free plating

Preliminary Data Sheet 7 V 0.9, 2007-05

1.2 Target Applications

Angular position sensing in automotive applications like: Steering Angle Brushless DC Motor Commutation (e.g. EPS) Rotary Switch General Angular sensing in automotive applications

1.3 Product Description

The TLE5010 is a 360° angle sensor, which detects the orientation of a magnetic field. This is achieved by measuring sine and cosine angle components with monolithic integrated GMR elements (Giant Magnetic Resistance). Data communication is done with a bi-directional SSC interface (SPI compatible). The sine and cosine values can be read out. These signals can be digitally processed to calculate the angle orientation of the magnetic field (magnet). This calculation can be done by using a cordic algorithm. It is possible to connect more than one TLE5010 to one SSC Interface of a µC for redundancy or any other reasons. In this case the synchronization of the connected TLE5010 is done by a broadcast command. Each connected TLE5010 can be addressed by a dedicated chip select CS pin. Online diagnostic functionalities are provided to ensure a reliable operation. These are Angle Test (generated via test voltages feeding the ADC). Crossed signal paths (switchable for comparison) Inverted signs of bit streams Over and undervoltage detections

Preliminary Data Sheet 8 V 0.9, 2007-05

1.4 Pin Configuration (top view)

Figure 1 Pin Configuration Table 1 Pin Definitions and Functions Pin No. Symbol In/Out Function

1 CLK I Chip Clock

2 SCK I SSC Clock

3 CS I SSC Chip Select

4 DATA I/O SSC Data, open drain

5 TST1 I/O Test Pin 1, must be connected to GND

6 VDD - Supply voltage

7 GND - Ground

8 TST2 I/O Test Pin 2, must be connected to GND

5678 Center of

Preliminary Data Sheet 9 V 0.9, 2007-05

2 General

2.1 Functional Description

The clock for the sensors will be provided by external. This ensures a synchronously operation in case of multiple system participants. The sensor has its own PLL to generate the necessary clock frequency for the chip operation.

2.2 Block Diagram

The block diagram shows all switches in reset position. Figure 2 Block Diagram YH YL XH XL TLE5010 SSC Control FSM SCK DAT A CS differential Comb Filter FIR Filter Comb Filter FIR Filter FSYNC FCNT VRA VRA_RstVRA_OV VRD_RstVRD_OVVRD VDD PLL CLK Reset Analog Clock Digital Clock Digital Reset VRG_Rst VRD_Rst LockVRA_Rst TST1 TST2 GMR X VDDG VDDG GND GND GMR Y Angle Voltage Angle Voltage VDD-off Comp CLK SCK VDD_OV CompTST1VDD_maxGND-off Comp VRG VRG_RstVRG_OV GND Temperature Sensor A D A

Preliminary Data Sheet 10 V 0.9, 2007-05

2.3 Internal Power Supply

The internal stages of the TLE5010 are supplied with different voltage regulators. Each voltage regulator has its own over- and undervoltage detection circuits. GMR Voltage Regulator VRG (VDDG-Voltage) The GMR voltage regulator supplies all GMR parts. GMR Bridges Test Voltages for Angle Test ADC Reference Voltage The voltages are monitored in the VRG over- and undervoltage detectors. Analog Voltage Regulator VRA (VDDA-Voltage) The analog voltage regulator supplies the analog parts. ADCs PLL (analog) VDD-Off comparator GND-Off comparator VDD Overvoltage detection The voltages are monitored in the VRA over- and undervoltage detectors. Digital Voltage Regulator VRD (VDDD-Voltage) The digital voltage regulator supplies all digital parts. Comb filters, FIR filters and Low Pass filter PLL (digital) Control FSM with Bitmap SSC -Interface Counters (Reset, FSYNC, FCNT) The voltages are monitored in the VRD over- and undervoltage detectors.

Preliminary Data Sheet 11 V 0.9, 2007-05

2.4 GMR Functionality

The GMR sensor is implemented in vertical integration. This means, that the GMR active areas are integrated above the logic part. GMR elements change their resistance depending on the direction of the magnetic field. 4 individual GMR elements are connected to one Wheatstone sensor bridge. They sense either the X component, VX (cosine) or the Y component, VY (sine) of the applied magnetic field. The advantage of a full-bridge structure is that the GMR signal amplitude is doubled. Figure 3 Sensitive bridges of the GMR Sensor1) 1) The arrows in the resistor symbols show the direction of the reference layer V DDGGNDADC X+ GMR Resistors ADC X -A D C Y+A D C Y - VX VY 90° NS

Preliminary Data Sheet 12 V 0.9, 2007-05 The output signal of each bridge is only unambiguous over 180° between two maxima. Therefore two bridges are orientated orthogonal to each other. Using the ARCTAN function, the true 360° angle value can be calculated which is represented by the relation of the X and Y signals. As only the relative values influence the result, the absolute size of the two signals is of minor importance. Therefore most influences to the amplitudes are compensated. Figure 4 Ideal Output of the GMR Sensor V Angle α 90° 180° 270° 360°0° VX (COS) X Component (COS) Y Component (SIN) VY (SIN) VY VX

Absolute Maximum RatingsDraft Preliminary Data Sheet 13 V 0.9, 2007-05

3 Absolute Maximum Ratings

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDD or VIN < GND ) the voltage on VDD pins with respect to ground (GND ) must not exceed the values defined by the absolute maximum ratings. Table 2 Absolute Maximum Rating Parameters Parameter Symbol Limit Values Unit Notes min. max. Voltage on VDD pin respect to ground (VSS ) VDD -0.5 6.5 V max 40 h / lifetime Voltage on any pin respect to ground (VSS ) VIN -0.5 6.5 V VDD + 0.35 V may not be exceeded Junction Temperature TJ -40 150 °C Magnetic Field InductionB - |125| mT max 5 min. @ tA = 25°C - |80| max 5 h @ tA = 25°C

Preliminary Data Sheet 14 V 0.9, 2007-05

4 Operating Range

The following operating conditions must not be exceeded in order to ensure correct operation of the TLE5010. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Note: For a calculation of the corresponding ambient temperature the thermal resistances in Table 20 "Package Parameters" on Page 51 have to be used. Table 3 Operating Range ( - 40°C < TJ < 150°C ) Parameter Symbol Limit Values Unit Notes min. typ. max. Supply Voltage VDD 4.5 - 5.5 V 1) 1) Directly blocked with 100 nF ceramic capacitor Output Current IQ - -5 -10 mA 2) 3) 2) Max current to GND over Open Drain Output 3) The corresponding voltage levels are listed in Table 5 "Electrical Parameters for 4.5V < V DD < 5.5V" on Page 16 Input Voltage VIN -0.3 - 5.5 V VDD + 0.5 V may not be exceeded Magnetic InductionB XY 25 30 45 mT In X / Y direction4) 4) Values refer to an homogenous magnetic field (Bxy) without vertical magnetic induction (Bz = 0 mT). By applying a vertical magnetic induction an additional error has to be considered Angle Range Ang 0 - 360 ° sine / cosine Storage Temperature TST -40 - 50 °C Overall Life Timetlife - - 15 Years

Electrical and Magnetic ParametersDraft Preliminary Data Sheet 15 V 0.9, 2007-05

5 Electrical and Magnetic Parameters

5.1 Electrical Parameters

These are all parameters over operating range, unless otherwise specified. Unless individually specified, typical values correspond to a supply voltage VDD = 5.0 V and 25°C. All other values correspond to - 40°C < TJ < 150°C Table 4 Electrical Parameters Parameter Symbol Limit Values Unit Notes min. typ. max. Supply Current 1) 1) Without external pull-up resistor for SSC-Interface IDD - 15 20 mA VDD = 4.5 to 5.5V - - 21 VDD = 6.5 V POR Level VPOR 2.0 2.3 2.9 V Power On Reset POR Hysteresis VPORhy - 30 - mV Power On Time tPon 50 100 200 µs VDD > VDDmin & after first edge on fCLK PLL Jitter tPLLjit_S - 1.3 2.0 2) 2) Not tested ns short term 3) 3) From pulse to pulse tPLLjit_L 3.0 3.9 long term 4) 4) Accumulated over 1 ms ADC Noise 5) 5) ADC noise in respect to the peak ADC value specified in “Signal Processing” on Page 23. Noise tested using 1 σ of 100 sample values from Angle Test “000” N ADC - 1 2.2 digits1 σ @ FIR_BYP = 0 - 2 4.42) 1 σ @ FIR_BYP = 1 Input Signal Low Level VL -0.35 - 0.3 VDD V Tested only at DATA pin as structures of all pins are identicalInput Signal High Level VH 0.7 VDD - VDD +0.35 V Capacitance of SSC Data Pin C LDATA - 4 6 2) pF Internal

Electrical and Magnetic ParametersDraft Preliminary Data Sheet 16 V 0.9, 2007-05 . .

5.2 ESD Protection

Table 5 Electrical Parameters for 4.5V < V DD < 5.5V Parameter Symbol Limit Values Unit Notes min. typ. max. Input HysteresisVHY 0.07 VDD - - V Pull-Up Current IPU -10 - -150 µA CS , DATA Pull-Down CurrentIPD 15 - 225 µA SCK, CLK 15 - 225 TST1 10 - 150 TST2 Output Signal Low Level VOL - 0.7 0.4 V IQ = - 10 mA IQ = - 5 mA 1) 1) The value -5 mA is not tested Table 6 ESD Protection Parameter Symbol Limit Values Unit Notes min. max. ESD Voltage VHBM - ± 2 kV HBM 1) 1) Human Body Model (HBM) according to: JEDEC EIA/JESD22-A114-B (R = 1.5 kΩ , C = 100 pF, TA = 25°C) VCDM - ± 500 V CDM 2) 2) Charge Device Model (CDM) according to: ANSI ESD STM JEDEC JESD 22-C101-A Class III.

Electrical and Magnetic ParametersDraft Preliminary Data Sheet 17 V 0.9, 2007-05

5.3 GMR Parameters

All parameters over operating range, unless otherwise specified. Offset and Amplitude Figure 5 Offset and Amplitude Definition Table 7 Basic GMR Parameters Parameter Symbol Limit Values Unit Notes min. typ. max. X, Y Output rangeRG ADC - - ±23230 digits X, Y Amplitude 1) 1) See Figure 4, Page 12 AX, AY 7402 12337 15781 digits@ Calib. Conditions 3922 - 20620 Operating Range X, Y Synchronism 2) 2) k = 100 x ( AX / AY ). k 80 100 120 % @ Calib. Conditions X; Y Offset 3) 3) O SIN = ( YMAX + YMIN ) / 2 ; O COS = ( XMAX + XMIN ) / 2 O X, O Y -3000 0 3000 digits@ Calib. Conditions X, Y Orthogonality Error ϕ -10.0 0 10.0 ° @ Calib. Conditions X,Y without fieldX0, Y0 -5000 - 5000 digitswithout magnet4) 4) Not tested. Angle 90° 180° 270° 360°0° Offset VY

Electrical and Magnetic ParametersDraft Preliminary Data Sheet 18 V 0.9, 2007-05 Amplitude Definition The amplitude is defined as half difference between the signed maximum and minimum values of the idealized (fitted) sine or cosine wave. Offset Definition The offset of the X and Y signals is defined as the mean value between the signed maximum and minimum values of the idealized (fitted) sine or cosine wave. Temperature dependent behavior The temperature offset gradients for both channels depend on the value at 25°C. It can be calculated using following linear equations: O X25, O Y25: Offset values at 25°C in digits. Table 8 GMR Temperature Coefficients Parameter Symbol Limit Values Unit Notes min. typ. max. Offset Temperature Coefficient base tco_d_x - +0.116296 - digits_/_K Offset Temperature Coefficient gain A X X MAX X MIN– A Y YMAX YMIN– O X X MAX X MIN+ O Y YMAX YMIN+ KT OX tco_d_x tco_k_x O X25×()+= KT OY tco_d_y tco_k_y O Y25×()+=

Electrical and Magnetic ParametersDraft Preliminary Data Sheet 19 V 0.9, 2007-05 Orthogonality Definition The corresponding maximum and zero crossing points of the SIN and COS signals are not exactly in a distance of 90°. The difference between X and Y phase is called ’Orthogonality Error’. jideal = 0° jX : Phase error of X (= cos) Signal jY : Phase error of Y (= sin) Signal

5.4 Calibration

The end-of-line calibration can be done using following sequence. The conditions are specified in Table 9. Turn magnetic field left and measure X and Y values Calculation of Amplitude, Offset, Phase correction values of left turn Turn further 90° left and 90° back right without measurement Turn magnetic field right and measure X and Y values Calculation of Amplitude, Offset, Phase correction values of right turn Calculation of mean values of Amplitude, Offset, Phase correction values The above gained values have to be stored in a non-volatile memory. They are used for the correction of the read-out X and Y values before the angular calculation. The resulting angular deviation is calculated using above determined parameters. Temperature Measurement The signal amplitude T25 of the temperature measurement path at calibration conditions has to be measured and stored. Calibration Conditions All errors are related to a calibration done using following conditions: Table 9 GMR calibration conditions Parameter Symbol Limit Values Unit Notes min. typ. max. Flux density BCAL - 30 - mT BZ = 0 mT Temperature TCAL - 25 - °C ϕϕ X ϕ Y–=

Electrical and Magnetic ParametersDraft Preliminary Data Sheet 20 V 0.9, 2007-05

5.5 Angle Calculation

5.5.1 Components of the Output Signals

The X and Y signals at the output can be described with following equations: AX : Amplitude of X (= cos) Signal AY : Amplitude of Y (= sin) Signal O X : Offset of X (= cos) Signal O Y : Offset of Y (= sin) Signal ϕX : Phase error of X (= cos) Signal ϕY : Phase error of Y (= sin) Signal

5.5.2 GMR Error Compensation

Temperature dependent Offset Value To increase the accuracy, the temperature dependent offset drift can be compensated. The temperature of the chip has to be read out. The Offset values O X and O Y have to be multiplied with the Offset temperature coefficient and the temperature value. O X25 , O Y25 : Offset value at 25°C in digits T25 : Temperature value at 25°C in digits T : Temperature value in digits ST : Sensitivity of the temperature measurement path, (see chapter “Temperature Measurement” on Page 46). XA X αϕ X+()cos× O X+= YA Y αϕ Y+()sin× O Y+= O X O X25 KT OX ST O Y O Y25 KT OY ST

Electrical and Magnetic ParametersDraft Preliminary Data Sheet 21 V 0.9, 2007-05 Offset Correction After read-out of the X and Y value first the temperature corrected offset value has to be subtracted. Amplitude Normalization Then the X and Y values are normalized using the peak values determined in the calibration. Non-Orthogonality Correction The influence of the non-orthogonality can be compensated using following equation. Only the Y channel has to be corrected. Resulting Angle After correction of all errors, the resulting angle can be calculated using the arctan function1). 1) µC-function “arctan2(Y3,X2)” to resolve 360° X 1 XO X–= Y1 YO Y–= X 2 X 1 A X A Y Y2 X 2 ϕ–()sin×– α arc Y 3 X 2 tan ϕ X–=

Electrical and Magnetic ParametersDraft Preliminary Data Sheet 22 V 0.9, 2007-05

5.6 GMR Parameters after Calibration

After calibration under the conditions specified in Table 9 "GMR calibration conditions" on Page 19, the sensor has following remaining error: The error value refers to BZ = 0 mT and operating conditions given in Table 3 "Operating Range ( - 40°C < T J < 150°C )" on Page 14. Table 10 GMR parameter with temperature dependent offset compensation Parameter Symbol Limit Values Unit Notes min. typ. 1) At 25°C, B=30mT max. Overall Error - 0.7 2,0 ° 2) 3) 2) incl. hysteresis error 3) At 0h

Preliminary Data Sheet 23 V 0.9, 2007-05

6 Signal Processing

Table 11 Signal Processing Parameter Symbol Limit Values Unit Notes min. typ.1) 1) For 4 Mhz input frequency max. Internal Cutoff Frequency (-3dB) of sin or cos Value fCut-Off - 4.9 - kHz FIR_BYP=0

19.6 FIR_BYP=1

sin or cos Value2) 2) tupd = 8192 / (25 x fCLK ) for FIR_BYP = 0 tupd = 8192 / (100 x fCLK ) for FIR_BYP = 1 tupd - 81,9 - µs FIR_BYP=0 - 20,5 - FIR_BYP=1 Settle Time 3) 3) tsettle = 2 x tupd , after change of ADC input source tsettle - 163,8 - FIR_BYP=0 - 41,0 - FIR_BYP=1 Peak ADC Output value ADC Pk - - 23230 digitssigned 16 bit integer (2s complement) 4) 5) 4) Output values are valid up to this limit. Above it, corrupted results may occur due to non-linearity of the ADC. 5) The internal quantization is typically 5.166 µV per digit. 6) Correspond to max. GMR output value.

Clock Supply (CLK Timing Definition)Draft Preliminary Data Sheet 24 V 0.9, 2007-05

7 Clock Supply (CLK Timing Definition)

The clock signal input “CLK” must fulfill certain requirements which are described in the following: The high or low pulse width must not exceed the specified values, because the PLL needs a minimum pulse width and must be spike filtered. The duty cycle factor should be 0.5 but can deviate to the values limited by tCLKh(f_min) and tCLKl(f_min). The PLL is triggered at the positive edge of the clock. If more than 2 edges are missing, a chip reset is generated automatically. Figure 6 CLK Timing Definition Table 12 CLK Timing Specification Parameter Symbol Limit Values Unit Notes min. typ. max. Input Frequency fCLK 3.9 4.00 4.2 MHz CLK Duty Cycle 1) 1) Minimum duty cycle factor: tCLKh(f_min) / tCLK(f_min) with tCLK(f_min) = 1 / fCLK(f_min) Maximum duty cycle factor: tCLKh(f_max) / tCLK(f_min)with tCLKh(f_max) = tCLK(f_min) - tCLKl(min) CLK DUTY 30 50 70 % CLK rise time tCLKr - - 20 ns from VL to VH CLK fall time tCLKf - - 20 ns from VH to VL PLL Frequency fPLL - 100 - MHz fCLK * 25 Digital Clock fDIG - 25 - MHz ( 25 / 4 ) * fCLK Digital Clock PeriodetDIG - 40 - ns 4 / (25 * fCLK ) tCLKh tCLKl tCLK t V L VH

Synchronous Serial Communication Interface (SSC)Draft Preliminary Data Sheet 25 V 0.9, 2007-05

8 Synchronous Serial Communication Interface (SSC)

The 3 pin synchronous serial interface (SSC) has a bidirectional data line (open drain), serial clock signal and chip select. It is designed to communicate with a micro controller with bidirectional SSC interface supporting Open Drain. Other micro controllers may require an external NPN transistor. This allows communication with SPI compatible devices. Figure 7 SSC Half-Duplex Configuration for µC with Open Drain support Figure 8 SSC Half-Duplex Configuration for µC without Open Drain support DATADATA SCK SCK TLE 501x (SSC Slave) µC (SSC Master) typ. 1kΩ *) optional , e.g . 100ΩClock Generator Shift Register CS CS *) *) Shift Register DATA MRST MTSR SCK SCK TLE 501x (SSC Slave) µC (SSC Master) typ. 1kΩ *) optional , e.g. 100ΩClock Generator Shift Register CS CS optional Shift Register

Synchronous Serial Communication Interface (SSC)Draft Preliminary Data Sheet 26 V 0.9, 2007-05

8.1 SSC Timing Definition

Figure 9 SSC Timing Definition SSC Inactive Time ( CS off ) The SSC inactive time defines the delay, before the TLE5010 can be selected again after a transfer. The TLE5010 reacts only to one command after SSC inactive time. Then the SSC Interface of the TLE5010 is disabled until the next SSC Inactive Time is performed. DATA Write Time ( tDATW ) During this time the TLE5010 changes the data line, thus the data are invalid. The DATA Write Time values are defined without pull-up resistor. Pull-up Time Value ( tPU ) The value in Table 13 "SSC Timing Specification" on Page 27 is estimated with 60 ns. Chip Select Off time ( tCSOFF ) SCK DATA tSCKp CS VL VH VL VH VL VH tCSh tCSofftCSs tDATr tDATw tSCKh tSCKl

Synchronous Serial Communication Interface (SSC)Draft Preliminary Data Sheet 27 V 0.9, 2007-05 Table 13 SSC Timing Specification 1) 1) Timings have to be calculated acc. Table 12 "CLK Timing Specification" on Page 24. Parameter Symbol Limit Values Unit Notes min. typ. max. SSC Baud Rate fSSC - 2.0 2.12) 2) fCLK /2, synchronized to fCLK if fCLK = fCLK (max) MBit / s CS Setup Time tCSs 3*tDIG+10 - - ns CS Hold Time tCSh 5*tDIG+10 - - ns CS off tCSoff 10*tDIG - - ns SSC inactive time SCK High tSCKh 5*tDIG - - ns SCK Low tSCKl 5*tDIG - - ns DATA Read Time (Data Valid Time) tDATr 6*tDIG-10 - 7*tDIG+10 ns SSC_FILT = 0 5*tDIG-10 - 7*tDIG+10 SSC_FILT = 1 DATA Write Time (Data Valid Time) 3) tPU is the time generated by the pull-up resistor tDATw 6*tDIG+25 - 7*tDIG+50 + tPU ns DATA slope tDATs - 20 30 4) 4) Not tested. ns Falling edge 5) 5) Internal slope control of falling edge for data bit transition from V H to V L.

Synchronous Serial Communication Interface (SSC)Draft Preliminary Data Sheet 28 V 0.9, 2007-05 Figure 10 SSC Interface Timing Details with worst-case specified Timing Note: – The read window includes the sampling of the data bit. – For SSC_FILT = 1, the 2-of-3 selection is already regarded. Only the 2 last data values have to be equal. – For SSC_FILT = 0 only one sample point is selected. SCK SSC _FILT=0 SCK SSC _FILT=1 Wr tDATw MIN tDATw MAX tPU Wr tDATw MIN tDATw MAX tPU Earliest sample timepoint Rd tDATr MIN tDATr MAX Rd tDATr MI N tDATr MAX Earliest sample timepoint of second sample from 2 of 3 filter tSCKhtSCKl MIN

Synchronous Serial Communication Interface (SSC)Draft Preliminary Data Sheet 29 V 0.9, 2007-05 The margin time in following table is the time between write access to the SSC Data Line and the earliest possible sample read of the TLE5010 itself for read back. It is useful to have a maximum distance between WRITE and subsequent READ. This ensures a reliable read back of the written data for the Slave-Active Byte generation.

8.2 SSC Baud rate

The SSC Baud rate depends on the internal clock frequency. 12 internal digital clock cycles are necessary to ensure a reliable operation. Therefore the maximum SSC Baud rate depends on the external CLK.

8.3 SSC Spike Filter

A SSC Spike Filter for all SSC lines can be selected via the SSC_FILT bit.

8.3.1 SSC Spike Filter Off

When the spike filter is disabled, each slope of a rising voltage is used to define a bit. This is independent of the length of the sampled pulse. For example a positive spike generates therefore a rising and a falling edge. Table 14 Maximum Pull-up Time Margin with worst-case specified Timing SSC_FILT SSC_TIMING Min. tPU Margin 1) 1) Calculation: Margin=tSCKl(min)+tDATwMAX -(tPU )-tDATrMIN .For Margin<50 ns no problems can occur. Unit Comment 0 don’t care 90 ns 1 50 fSSC fCLK

Synchronous Serial Communication Interface (SSC)Draft Preliminary Data Sheet 30 V 0.9, 2007-05

8.3.2 SSC Spike Filter On

A sliding window with four consecutive sample bits is analyzed. The sample frequency is: Rising Edge Detect for SCK After a rising edge (LH combination), at least one of the 2 following samples has to be ’high’. Valid bit combinations: 0111 , 0110 , 0101. A falling condition has to be detected before. Falling Edge Detect for SCK After a falling edge (HL combination), at least one of the 2 following samples has to be ’low’. Valid bit combinations: 1000 , 1001 , 1010. A rising condition has to be detected before. Figure 11 SSC Spike Filter Filter for DATA and CS The DATA pin has a ’2-of-3’ filter. The CS input has a ’2-of-3’ filter, which suppresses only positive spikes. fS fDIGIT SCK (PAD) SCK Rise SCK Fall Masked, because no fall detected Suppressed Spike SCK fall detected SCK rise detected

Synchronous Serial Communication Interface (SSC)Draft Preliminary Data Sheet 31 V 0.9, 2007-05

8.4 SSC Data Transfer

The following transfer bytes are possible: Command byte (to access and change operating modes of the TLE5010) Data bytes (any data transferred in any direction) CRC byte (cyclic redundancy check) Slave Active byte (response of all selected slaves) Figure 12 SSC Data Transfer (Data Read Example)

8.5 SSC Command Byte

The TLE5010 is controlled by a command byte. It is sent first at every data transmission. Table 15 Structure of the Command Byte Name Bits Description RW [7] Read - Write ’0’ = write, ’1’ = read ADDR [6..3] Address to be read / written ’0..15’ - register start address (address auto increment) ND [2..0] Number of data bytes ’0..7’ - number of data bytes to be transferred SCK DATA Command Byte Data Byte(s) SSC-Maste r is d riving DATA (µC) SSC-Slave is d riving DATA (Sen sor) CS DATA Command Byte Data CRC SlaveActive SSC-Slave is driving DATA (Sensor)SSC-Master is driving DATA (µC) LSB321MS B 6 5 4 LSB321MSB 6 5 4

Preliminary Data Sheet 32 V 0.9, 2007-05

9 Register Table

This chapter defines the complete address range as well as all registers of the TLE5010. It also defines the read/write access rights of the specific registers. In the following table values through symbols are listed. Access to the registers is done via the SSC interface. Table 16 Address Map Addr. Name Bits 7 6 5 4 3 2 1 0 00H CTRL1 - - - - SSC_ FILT - AUTO UR 01H XL XLow 02H XH XHigh 03H YL YLow 04H YH YHigh 05H FCNT_ STAT - STAT_ VR GMR_ OFF UPDATE FCNT 06H FSYNC_ INV FILT_ INV FSYNC 07H ANGT - ANGT_ EN ANGT_Y ANGT_X 08H - reserved 09H - reserved 0AH - reserved 0BH - reserved 0C H TST TEMP_ EN ADCPY FILT_ PAR FILT_ CRS FILT_ BYP TST_ ADC TST_ GMR TST_ CHAN 0D H ID DEV_ID REV_ID 0EH LOCK LOCK 0FH CRTL2 VDD_ OV VDD_ OFF GND_ OFF VRG_ OV VRA_ OV VRD_ OV S_NO

Preliminary Data Sheet 33 V 0.9, 2007-05 Bit Types Abbreviation Function Description L Locked Locked register. These registers can only be written, when the unlock- value is written in the lock register (0EH ). This ensures, that these bits cannot be modified unwanted during normal operation. U Update Update-Buffer is for this bit is present. In case of an Update Command and the Update- Mode bit (UR in CTRL1) is set, the immediate values are stored in this Update-Buffer simultaneous. This enables a snapshot of all necessary system parameters at the same time. S Status Reset only after readout R Read Read-only registers W Write Read and write registers

Preliminary Data Sheet 34 V 0.9, 2007-05 CTRL1 Addr: 00H Reset Value: 01H 7 6 5 4 3 2 1 0 reserved reserved reserved reserved SSC_FILT reserved AUTO UR - - - W L W L - W L W L Field Bits Type Description reserved 7 - reserved, has to be set to 0 reserved 6 - reserved, has to be set to 0 reserved 5 - reserved, has to be set to 0 reserved 4 - reserved, has to be set to 0 SSC_FILT 3 W L SSC Digital Spike Filter enable for all SSC lines ( CS , CLK and DATA ) 0: Digital SSC Spike filters off 1: Digital SSC Spike filters on (modified timing) reserved 2 - reserved, has to be set to 0 AUTO 1 W L Automatic update at angle tests 0: no automatic update in Angle Test Mode 1: automatic update-command after tsettle, counters FSYNC and FCNT are reset to “0”. Then the Angle-Test (ANGT_EN) is automatically disabled and switches back to normal operation. Also the UPDATE bit is toggled UR 0 W L Update / Run Mode 0: Run Mode (Buffer1 values are immediate values) 1: Update Mode (Buffer2 values are stored values)

Preliminary Data Sheet 35 V 0.9, 2007-05 The values in Register 01H to 04H represent one byte of two’s complement signed 16 bit integer values. X_L Addr: 01H Reset Value: 00H 7 6 5 4 3 2 1 0 X Low Byte R U X_H Addr: 02H Reset Value: 00H 7 6 5 4 3 2 1 0 X High Byte R U Y_L Addr: 03H Reset Value: 00H 7 6 5 4 3 2 1 0 Y Low Byte R U Y_H Addr: 04H Reset Value: 00H 7 6 5 4 3 2 1 0 Y High Byte R U

Preliminary Data Sheet 36 V 0.9, 2007-05 FCNT_STAT Addr: 05H Reset Value: 80H 7 6 5 4 3 2 1 0 reserved STAT_VR GMR_OFF UPDATE FCNT - R S R U R S R U Field Bits Type Description reserved 7 - STAT_VR 6 RS Voltage Regulator Status This bit is a logical OR combination of Digital, Analog, GMR and VDD OV Comparator and GNDOFF , and VDD OFF Comparator outputs. 0: Voltage Supply ok 1: Voltage Supply not ok GMR_OFF 5 RU ADC Values are no GMR values (e.g.: Temperature measurement is active) This bit indicates, whether GMR values or any other values are connected to the ADCs. This value is read back from the multiplexer control signals. 0: X,Y Values are GMR values 1: X,Y Values normally represent temp. measurement or angle test values. In case of non functional MUX this bit is set to “1” UPDATE 4 RU Update Toggle bit. This bit toggles after every update (update command or automatic update at angle test) The bit is independent of 'UR' bit in CTRL1 FCNT 3-0 RU Frame Counter (4 bit unsigned integer value) This counter counts every new X,Y value pair coming out of the data path. (approx. 80µs) This counter is reset to 0H after any write to FSYNC and after every change of the ANGT_EN bit. As tsettle time has to be waited for valid X,Y data, this counter must be ≥ 2H to indicate valid X,Y values. If it overflows, it resets to 3H to show, that values are still valid. Note: If FIR_BYP is activated, this counter counts 4 times faster!

Preliminary Data Sheet 37 V 0.9, 2007-05 FSYNC_INV Addr: 06H Reset Value: 00H 7 6 5 4 3 2 1 0 FILT_INV FSYNC WU WU Field Bits Type Description FILT_INV 7 WU Filter Input Inversion (to check the digital data path during operation) 0: Filter Inputs are not inverted 1: Filter Inputs are inverted FSYNC 6-0 WU Frame Synchronization (7bit unsigned integer value) The Filter Update time of approx. 80 µs results from the filter decimation. The phase of this decimation can be set and checked by this counter. If FIR_BYP is activated, this counter overflows at the value 31 D . ANGT Addr: 07H Reset Value: 00H 7 6 5 4 3 2 1 0 reserved ANGT_EN ANGT_Y ANGT_X - W W W Field Bits Type Description reserved 7 - reserved, has to be set to 0 ANGT_EN 6 W Angle Test Enable 0: Angle Test disable command 1: Angle Test enable command in this case X and Y values represent resistive test values, which can be used to simulate angle values ANGT_Y 5-3 W Angle Test X and Y value see : Table 17 "Functional Angle Test" on Page 45ANGT_X 2-0 W

Preliminary Data Sheet 38 V 0.9, 2007-05 Reserved Registers (08H to 0BH ) The values in these registers are 8 bit unsigned integer values. The values in addr.8 and addr.9 have to be in reset status. Reserved Addr: 08H Reset Value: FFH 7 6 5 4 3 2 1 0 Reserved Reserved Addr: 09H - 0BH Reset Value: 00H 7 6 5 4 3 2 1 0 Reserved

Preliminary Data Sheet 39 V 0.9, 2007-05 TST Addr: 0CH Reset Value: 00H 7 6 5 4 3 2 1 0 TEMP_EN ADCPY FILT_PAR FILT_CRS FIR_BYP TST_ADC TST_GMR TST_ CHAN W L W L W L W L W L W L W L W L Field Bits Type Description TEMP_EN 7 W L Temperature Device Enable 0: Temperature Measurement disabled 1: Temperature Measurement enabled The X value represents the temperature. Automatic update mode enabled, if AUTO='1' ADCPY 6 W L Y Polarity 0: No inversion of Y bit stream 1: Inversion of Y bit stream (rotating direct. changed) FILT_PAR 5 W L Filter switched parallel 0: Filters in normal mode 1: Filters parallel, input selected by TST_CHAN FILT_CRS 4 W L Filter switched across 0: Filters in normal mode 1: Filters crossed, X and Y outputs are exchanged FIR_BYP 3 W L FIR Filter Bypass 0: No FIR Bypass 1: FIR Bypass TST_ADC 1) 1) Only for test purposes

2 W L ADC input switch to TST1and TST2

0: No ADC input switch, normal operation 1: ADC input switched to TST1,2, ADC selected by TST_CHAN 2) 2) if TST_ADC and TST_GMR are set to ’1’ at the same time, TST_GMR is forced to 0. TST_ADC has the higher priority. TST_GMR 1) 1 W L GMR switch to TST1and TST2 0: No GMR switch, normal operation 1: GMR switched to TST1,2 2) TST_CHAN 0 W L Test Channel select 0: X channel linked to TST1and TST2 1: Y channel linked to TST1and TST2

Preliminary Data Sheet 40 V 0.9, 2007-05 ID Addr: 0DH Reset Value: 12H 7 6 5 4 3 2 1 0 DEV_ID DEV_REV R R Field Bits Type Description DEV_ID 7-4 R Device Identifier 001H : TLE5010 productive chip DEV_REV 3-0 R Device Revision (current number) 00H : TLE5010 productive chip, 1st revision (B11) 01H : TLE5010 productive chip, 2nd revision (B21) 02H : TLE5010 productive chip, 3rd revision (B31) 03H : TLE5010 productive chip, 4th revision (B41) (Referred to errata sheets for further versions) LOCK Addr: 0EH Reset Value: 00H 7 6 5 4 3 2 1 0 LOCK W Field Bits Type Description LOCK 7-0 W Lock Byte ≠ 5AH : Lock registers locked = 5AH : Lock registers unlocked CTRL2 Addr: 0FH Reset Value: 00H 7 6 5 4 3 2 1 0 VDD_OV VDD_OFF GND_OFF VRG_OV VRA_OV VRD_OV S_NO R S R S R S R S R S R S W L

Preliminary Data Sheet 41 V 0.9, 2007-05 Field Bits Type Description VDD_OV 7 R S VDD Overvoltage Comparator 0: No VDD Overvoltage occurred 1: VDD Overvoltage occurred VDD_OFF 6 R S VDD - Off Comparator 0: No VDD - Off occurred 1: VDD - Off occurred GND_OFF 5 R S GND - Off Comparator 0: No GND - Off occurred 1: GND - Off occurred VRG_OV 4 R S GMR Voltage Regulator Overvoltage Comparator 0: Voltage ok 1: VRG Overvoltage occurred VRA_OV 3 R S Analog Voltage Regulator Overvoltage Comparator 0: Voltage ok 1: VRA Overvoltage occurred VRD_OV 2 R S Digital Voltage Regulator Overvoltage Comparator 0: Voltage ok 1: VRD Overvoltage occurred S_NO 1-0 W L Slave Number Used in the SSC protocol

Data Communication via SSCDraft Preliminary Data Sheet 42 V 0.9, 2007-05

10 Data Communication via SSC

The data transmission order is ’MSB first’. Data is put on the data line with the rising edge on SCK and read with the falling edge on SCK. The SSC interface is byte aligned. Functions are activated after each transmitted byte. A “high” condition on the negated chip select pin (CS ) of the selected TLE5010 interrupts the transfer immediately. The CRC calculator is automatically resetted. Every access to the TLE5010 with ND (number of data) ≥ 1 is done with address auto increment. After an auto-increment overflow the addresses are beginning from 00H again. For every data transfer with ND ≥ 1 a 8 bit CRC byte will be appended by the selected TLE5010. No CRC byte is sent in a data transfer with ND = 0 (e.g. Update Command). After the CRC byte is sent, the bit represented by S_NO is pulled low by the selected slave in the Slave-Active-Byte (bits [3..0], low nibble). In this way, also broadcast- messages produce an individual feedback of every selected slave. This is necessary to differentiate the individual TLE5010 slave response, because the CRC byte is written by both TLE5010 in parallel. If the CRC byte on the bus is the same as the internal generated CRC of each TLE5010, each slave pulls low the dedicated bit in the Slave-Active-Byte (bits [7..4], high nibble). If not, the bit in the high nibble remains ’1’. A write command to address 00H with ND = 0 will update all values inside the TLE5010, and only in this case the transfer can proceed. Furthermore this command is add to the CRC-calculation of the following SSC Transfer. A command of “0000_0000” is called ’Update Command ’. This command transfers the present immediate values of each register to the update register. After an Update Command, the CS line need not set and reset again. After the CRC and Slave-Active byte have been sent the transfer ends. The TLE5010 always sends logical “1” and all following sent bits from the SSC Master are ignored (TLE5010 is in idle mode). To enable data transfers again the chip select pin (CS ) of the TLE5010 has to be deselected for CS off (see Table 13) once. If the update mode is selected (CTRL register, UR = ’1’), all accesses are done to update registers where update registers are present. Other registers are accessed directly.

Data Communication via SSCDraft Preliminary Data Sheet 43 V 0.9, 2007-05

10.1 CRC Generation

This CRC is according to the J1850 Bus-Specification of 15.Feb.1994 for Class B Data Communication. Every new transfer resets the CRC generation. Every byte of a transfer will be taken into account to generate the CRC (also the sent command(s)). Generator Polynom: X8+X4+X3+X2+1, for the CRC generation the fast CRC generation circuit is used. (See Figure 13) The remainder of the fast CRC circuit is initial set to ’11111111B’. Remainder is bit inverted before transmission. Figure 13 shows the fast CRC Polynom. The zero extension for initial CRC calculation is included! Figure 13 Fast CRC polynomial division circuit

10.2 Slave Active Byte Generation

The position of the ’0’ in a nibble corresponds to the given slave number. The slave active byte (cccc_nnnn) is made up of a low nibble (nnnn). One ’0’ is generated always according to the slave number. high nibble (cccc). The ’0’ is only generated, if the readback CRC is correct. Slave1: S_NO = 0 Ö bit 0 is pulled low Slave Active Byte: 1110_1110 Slave2: S_NO = 1 Ö bit 1 is pulled low Slave Active Byte: 1101_1101 Slave3: S_NO = 2 Ö bit 2 is pulled low Slave Active Byte: 1011_1011 Slace4: S_NO = 3 Ö bit 3 is pulled low Slave Active Byte: 0111_0111 Example for a communication disturbed by other bus participants: Slave1: S_NO = 0 Ö bit 0 is pulled low, but the high nibble remains as ’1111’. > Slave Active Byte: 1111_1110 X7X6X5X4X3X2X0 xorInput Serial CRC outputTX_CRC X1 1 1 xor 1 xor 1 xor 1 1 11& parallel Remainder

Data Communication via SSCDraft Preliminary Data Sheet 44 V 0.9, 2007-05 Example: Update X and Y and set ADC-Test Mode Command Data CRC (init all ‘0’) 00000001 00000101 00000000 xor 11111111 =11111110.0 . .A xor 10001110.1 . . = 01110000.10 . .B xor 1000111.01 . . = 0110111.110 . .C xor 100011.101 . . = 10100.0110 . .D xor 10001.1101 . . -----.---- . . = 00101.101101 . .E xor 100.011101 . . = 001.11000001. .F xor 1.00011101. . =.11011100.0 .G xor.10001110.1 . = 1010010.10 .H xor 1000111.01 . = 10101.1100 .I xor 10001.1101 . ----.----- . = 100.000100 .J xor 100.011101 . =01100100. Remainder 10011011 inverted Remainder Transmitted Sequence: Command Data CRC 00000001 00000101 10011011

Preliminary Data Sheet 45 V 0.9, 2007-05

11 Test Structures

Two different test signal structures are implemented in the TLE5010. These are: Functional angle test. In this case, well-knows signals feed the ADCs. Temperature measurement. This is useful to read out the chip temperature for compensation purposes.

11.1 Functional Angle Tests

It is possible to feed the ADCs with appropriate values to simulate a certain magnet- position and other GMR effects. The values are generated with resistors on the chip. Following X / Y ADC values can be programmed: 4 points, circle amplitude = 70.7% 8 points, circle amplitude = 100.0% 8 points, circle amplitude = 122.1% 4 points, circle amplitude = 141.4% Note: The 100% values correspond to typically 21700 digits and a voltage of ~ 110 mV. Table 17 Functional Angle Test Register Bits X / Y Values (decimal) min. typ. max. 000 -400 0 400 001 14800 15500 16200 010 20700 21700 22700 011 32767 100 1) 1) Not allowed to use. -400 0 400 101 -14800 -15500 -16200 110 -20700 -21700 -22700 111 -32768

Preliminary Data Sheet 46 V 0.9, 2007-05 ADC Test Vectors Figure 14 ADC Test Vectors

11.2 Temperature Measurement

An internal bandgap voltage can be used to measure the temperature on the chip. This may be used to compensate temperature dependent errors. The temperature value is sent out instead of the X value. Table 18 Temperature Measurement Parameter Symbol Limit Values Unit Notes min. typ. max. Value at -40°C T-40 - - +22000 digits Value at 25°C T25 +2550 +5775 +9000 digits Value at 150°C T150 -22000 - - digits Temperature SensitivityST - -188.75 - dig / K 1) 1) Should be used for temperature compensation of offset errors X Y 122.1% 100.0% 70.7% 141.4%

Preliminary Data Sheet 47 V 0.9, 2007-05

11.3 Angle Test and Temperature Measurement Timing

The angle test and the temperature readout is based on the same mechanism. In the Normal Mode, the output path is linked to the angle test or temperature measurement unit until the mode is terminated. Figure 15 Measurement in Normal Mode In the Automatic Mode, the signal is automatically switched back to GMR measurement after the read-out of one value. Figure 16 Measurement in Automatic Mode ADC&Filter Val_G4 FCNT[4] 4 Val_G5 Val_A0 Val_A1 FSYNC (reset) Update GMR_OFF Val_G1 Val_G0 useful X[16],Y[16] Buffer1 Val_G3 Val_G0 Val_G 1 Val_G 2 Val_A0 tupd tupd tupd tupd < tupd < tupd tupd tupd 05 02 Val_A2 Val_A1Val_G 4 ANGT_EN or TEMP_EN No GMR signal available Val_G4 Val_G5 Val_A0 Val_A1 Val_G1 0 1 Val_G0 Val_G3 Val_G 4 Val_A1 Val_G1 Val_G2 automatic! Val_A0 Val_G0 tupd tupd tupd tupd tupd tupd < tupd Updated FCNT=2 ADC&Filter FCNT[4] ANGT_EN or TEMP_EN FSYNC (reset) Update GMR_OFF X[16],Y[16] Buffer1 No GMR signal available

Overvoltage ComparatorsDraft Preliminary Data Sheet 48 V 0.9, 2007-05

12 Overvoltage Comparators

Various comparators monitor the voltage in order to ensure a error free operation. The overvoltages must be active for at least tDEL to set the test comparator bits in the SSC Interface registers. This works as digital spike suppression.

12.1 Internal Supply Voltage Comparators

Every voltage regulator has an overvoltage comparator to detect a malfunction. If the nominal output voltage of 2.5 V is larger than VOVG , VOVA and VOVD , then this overvoltage comparator is activated. It sets the VRx_O V bit. Figure 17 OV Comparator

12.2 V DD Overvoltage Detection

This comparator (see Figure 17) monitors the external supply voltage at the VDD pin. It activates the STAT_VR bit. Table 19 Test Comparators Parameter Symbol Limit Values Unit Notes min. typ. max. Overvoltage Detection VOVG - 2.80 - V VOVA - 2.80 - V VOVD - 2.80 - V VDD Overvoltage VDDOV - 6.5 - V GND - Off VoltageVGNDoff - 0.54 - V VGND_OFF = VGND - VTST1 VDD - Off VoltageVVDDoff - 0.48 - V VVDD_off = VCLK - VDD or VSCK - VDD Spike filter DelaytDEL - 10 - µs The error condition has to be longer than this value (min. 256 clocks of fDIG) REF - 10µs Spike Filter xxx_OV VDDA GNDGND VDD VRG VRA VRD

Overvoltage ComparatorsDraft Preliminary Data Sheet 49 V 0.9, 2007-05

12.3 GND - Off Comparator

This comparator is used to detect a voltage difference between the GND pin and TST1 (which must be soldered to GND in the application). It activates the STAT_VR bit. This circuit can detect a disconnection of the Supply GND Pin. Figure 18 GND - Off Comparator

12.4 V DD - Off Comparator

This comparator detects a disconnection of the VDD pin supply voltage. In this case the TLE5010 is supplied by the SCK, CLK and CS input pins via the ESD structures. It activates the STAT_VR bit. The retriggerable analog monoflop is necessary because of the not static signal of the CLK and SCK signals. This comparator is also activated, if spikes on CLK or SCK achieve the condition: (VCLK - VDD ) > VVDDoff or (VSCK - VDD ) > VVDDoff Figure 19 V DD - Off Comparator 10µs Spike Filter GND_OF F VDDA GND TST1 GND VDD +dV VGNDoff 10µs Spike Filter VDD _OF F VDDA GND VDD C LK SCK -dV GND 1µs Mono Flop VVDDoff

Typical Application CircuitDraft Preliminary Data Sheet 50 V 0.9, 2007-05

13 Typical Application Circuit

The application circuit shows the µC version with open drain capabilities. Figure 20 Application Circuit

13.1 Angle Sensor System

A complete system may consist out of one TLE5010 and a micro controller. The second TLE5010 can be redundand in order to increase the system reliability. The µC should contain a CORDIC coprocessor for fast angle calculations and a flash memory for the calibration data storage. CAN RX CAN TX Voltage Regulator GMR-Sensor TLE5010 12V GND CAN µController Master DATA_i SCK CSQ SSC CLK 1keach 100R 100R 100nF VDD VDD GND DATA_o CAN Tranceiver

Preliminary Data Sheet 51 V 0.9, 2007-05

14.1 Package Parameters

Table 20 Package Parameters Parameter Symbol Limit Values Unit Notes min. typ. max. Thermal Resistance RthJA - 150 200 K/W Junction to Air 1) 1) according to Jedec JESD51-7 RthJC - - 75 K/W Junction to Case RthJL - - 85 K/W Junction to Lead Soldering Moisture Level MSL 3 260°C Lead frame Cu194 / OLIN Fe 2.35%, P 0.03%, Cu 97.5%, Zn0.12% stamped Plating Sn 100% > 7 µm Molding Compound EME-G700 Halogen Free

Preliminary Data Sheet 52 V 0.9, 2007-05 Package Outline PG-DSO-8 Figure 21 Package Outline PG-DSO-8 GPS1903 2 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Max. 3˚ tilt of sensitive area to preference "E" 3) Independent from dimensions 1.65 and 1.22 -0.05 ±0.1 +0.1 5.06 0.41 1 4 1.27 B 0.1 0.2M D (1.5) 0.1 MIN. 1.65 C C 6±0.2 0.64 0.33 -0.01 0.2 +0.05 x 45˚±0.08 ±0.25 ±0.1 1.22±0.18 8˚MAX. Pin 1 STAND OF F ±0.084.9 D SEATING PLANE ±0.13.9 E A 1.273 x = 3.81 0.4B 2.53 1.95 A0.4 A Detail A Sensitive Area C enter of Index Marking ø0.6 Sensitive Area 2) 0.32 MIN.3)

Preliminary Data Sheet 54 V 0.9, 2007-05 Marking Figure 24 Marking Processing For processing recommendations please refer Infineon’s “Notes on Processing” 123456 G 0624 Pin 1 Top view Bottom view 111111 11111 111111 Production Code Date code (Y ear/Month) Type code Green PackagePin 1 marking HLGM1227

Preliminary Data Sheet 55 V 0.9, 2007-05

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Product Information

TLE5010 specifications and overview.

Summary

GMR Based Angular Sensor V 0.9, May 2007

Description

GMR Based Angular Sensor V 0.9, May 2007

Source title TLE5010 Datasheet(PDF) - Infineon Technologies AG

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