TLE4267

TLE4267 SIEMENS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 16

Technical content

Features

l Output voltage tolerance £ – 2 % l Low-drop voltage l Very low standby current consumption l Input voltage up to 40 V l Overvoltage protection up to 60 V (£ 400 ms) l Reset function down to 1 V output voltage l ESD protection up to 2000 V l Adjustable reset time l On/off logic l Overtemperature protection l Reverse polarity protection l Short-circuit proof l Wide temperature range l Suitable for use in automotive electronics P-TO220-7-3 P-TO220-7-180 P-TO220-7-230 TLE 4267

Semiconductor Group 2 1998-11-01 Design Notes for External Components The input capacitor C I is necessary for compensation line influences. The resonant circuit consisting of lead inductance and input capacitance can be damped by a resistor of approx. 1W in series with C I. The output capacitor is necessary for the stability of the regulating circuit. Stability is guaranteed at values of ‡ 22 mF and an ESR of £ 3 W within the operating temperature range. Circuit Description The control amplifier compares a reference voltage, which is kept highly accurate by resistance adjustment, to a voltage that is proportional to the output voltage and drives the base of the series transistor via a buffer. Saturation control as a function of the load current prevents any over-saturating of the power element. A comparator in the reset-generator block compares a reference that is independent of the input voltage to the scaled-down output voltage. If this reaches a value of 4.5 V, the reset-delay capacitor is discharged and then the reset output is set Low. As the output voltage increases again, the reset-delay capacitor is charged with constant current from VQ = 4.5 V onwards. When the capacitor voltage reaches the upper switching threshold, reset goes High again. The reset delay can be set within wide range by selection of the external capacitor. With the integrated turn-ON/turn-OFF logic it is simple to implement delayed turn-OFF without external components. Truth Table for Turn-ON/Turn-OFF Logic Pin 2: (Inhibit, E2) Enable function, active High Pin 6: (Hold, E6) Hold and release function, active Low Pin 2 Pin 6 V Q Remarks L X OFF Initial state, pin 6 internally pulled up H X ON Regulator switched on via pin 2, by ignition for example H L ON Pin 6 clamped active to ground by controller while pin 2 is still high X L ON Previous state remains, even ignition is shut off: self-holding state L L ON Ignition shut off while regulator is in self-holding state L H OFF Regulator shut down by releasing of pin 6 while pin 2 remains Low, final state. No active clamping required by external self- holding circuit (mC) to keep regulator shut off.

Semiconductor Group 3 1998-11-01 Pin Configuration (top view) Pin Definitions and Functions Pin Symbol Function

1 I Input; block to ground directly at the IC by a ceramic capacitor

2E 2 Inhibit; device is turned-ON by High signal on this pin; internal pulldown resistor of 100 kW 3R Reset Output; open-collector output internally connected to the output via a resistor of 30 kW 4G N D Ground; connected to rear of chip 5D Reset Delay; connect with capacitor to GND for setting delay 6E 6 Hold; see truth table above for function; this input is connected to output voltage across pullup resistor of 50 kW 7Q 5-V Output; block to GND with 22-mF capacitor, ESR < 3 W AEP02123 I R GND D Q 43215 6 7 AEP01481 I R GND D Q 43215 6 7 P-TO220-7-3 P-TO220-7-230 76512 34 AEP01724 D GND R I P-TO220-7-180

Semiconductor Group 4 1998-11-01 Block Diagram Absolute Maximum Ratings TJ = – 40 to 150 °C Parameter Symbol Limit Values Unit Notes min. max. Input Voltage VI – 42 42 V – Voltage VI –6 0 V t £ 400 ms Current II – – – Limited internally Reset Output Voltage VR – 0.3 7 V – Current IR – – – Limited internally Reset Delay Voltage Vd – 0.3 42 V – AEB01482 Saturation Control and Protection Circuit Turn-ON/Turn-OFF Logic Reset Generator Buffer Control Amplifier Sensor 462 GND Output Reset Delay Reset Outputput In- 1 Temperature Reference BandgapAdjustment E6 HoldInhibit

Semiconductor Group 5 1998-11-01 Operating Range Current Id ––– – Output Voltage VQ – 0.3 7 V – Current IQ – – – Limited internally Inhibit Voltage VE2 – 42 42 V Current IE2 – 5 5 mA t £ 400 ms Hold Voltage VE6 – 0.3 7 V – Current IE6 – – mA Limited internally GND Current IGND – 0.5 – A – Temperatures Junction temperature TJ –1 5 0 °C– Storage temperature Tstg – 50 150 °C– Parameter Symbol Limit Values Unit Notes min. max. Input voltage VI 5.5 40 V see diagram Junction temperature TJ – 40 150 °C– Thermal Resistance Junction ambient Rthja –7 0 K / W – Junction-case Rthjc –6K / W – Junction-case Rthjc –2K / W t < 1 ms Absolute Maximum Ratings (cont’d) TJ = – 40 to 150 °C Parameter Symbol Limit Values Unit Notes min. max.

Semiconductor Group 6 1998-11-01 Characteristics VI = 13.5 V; – 40 °C < TJ < 125 °C; VE2 > 4 V (unless specified otherwise) Parameter Symbol Limit Values Unit Test Condition min. typ. max. Output voltage VQ 4.9 5 5.1 V 5 mA £ IQ £ 400 mA

6 V £ VI £ 26 V

Output voltage VQ 4.9 5 5.1 V 5 mA £ IQ £ 150 mA

6 V £ VI £ 40 V

Output-current limitingIQ 500 – – mA TJ = 25 °C Current consumption Iq = II – IQ Iq ––5 0 mA Regulator-OFF Current consumption Iq = II – IQ Iq –1 . 0 1 0 mA TJ = 25 °C IC turned off Current consumption Iq = II – IQ Iq –1 . 3 4m A IQ = 5 mA IC turned on Current consumption Iq = II – IQ Iq ––6 0 m A IQ = 400 mA Current consumption Iq = II – IQ Iq ––8 0 m A IQ = 400 mA VI = 5 V Drop voltage VDr –0 . 3 0 . 6 V IQ = 400 mA1) Load regulation DVQ ––5 0 m V 5 m A £ IQ £ 400 mA Supply-voltage regulation DVQ – 1 52 5m V VI = 6 to 36 V; IQ = 5 mA Supply-voltage rejectionSVR –5 4 –d B fr = 100 Hz; Vr = 0.5 Vpp Longterm stability DVQ –0–m V 1 0 0 0 h 1) Drop voltage = VI – VQ (measured when the output voltage VQ has dropped 100 mV from the nominal value obtained at VI = 13.5 V)

Semiconductor Group 7 1998-11-01 Characteristics (cont’d) Parameter Symbol Limit Values Unit Test Condition min. typ. max. Reset Generator Switching threshold Vrt 4.2 4.5 4.8 V – Reset High level – 4.5 – – V Rext = ¥ Saturation voltage VR –0 . 1 0 . 4 V RR = 4.7 kW 1) 1) The reset output is Low between VQ = 1 V and VRT Pullup RR –3 0 –k W – Saturation voltage VD,sat – 50 100 mV VQ < VRT Charge current Id 81 5 2 5 mA VD = 1.5 V Delay switching thresholdVdt 2.6 3 3.3 V – Delay td –2 0 –m s C d = 100 nF Switching threshold Vst –0 . 4 3 –V – Delay tt –2– ms C d = 100 nF Inhibit Turn-ON voltage VE2 –34V I C t u r n e d - O N Turn-OFF voltage VE2 2––V I C t u r n e d - O F F Pulldown RE2 50 100 200 k W – Hysteresis DVE2 0.2 0.5 0.8 V – Input current IE2 – 35 100 mA VIP2 = 4 V Holding voltage VE6 30 35 40 % Referred to VQ Turn-OFF voltage VE6 60 70 80 % Referred to VQ Pullup RE6 20 50 100 k W – Overvoltage Protection Turn-OFF voltage Vi,ov 42 44 46 V – Turn-ON hysteresis DVi,ov 2–6V –

Semiconductor Group 8 1998-11-01 Test Circuit Application Circuit AES01483 22 F IQ IR VE6 W4.7 k 645 E2I

1000 F 470 nF

5 V Output

E2; eg from Terminal 15 To MC Input Reset 4267TLE

Semiconductor Group 9 1998-11-01 Time Response AET01985 td tt tt< Power Reset Shutdown Thermal Voltage Drop at Input Undervoltage at Output Secondary Spike Bounce Load Shutdownon satVR, STV dTV Vd, sat RTV OFFE2,V ONVE2, EV RV Vd QV iV

Semiconductor Group 10 1998-11-01 Enable and Hold Behaviour AET01986 E2,V ON VE2, OFF VE2 Vi VRT VQ d,V VdT VST dV R,V VR td VE6 V E6,V E6, VQ, 10 s<<1 10) 5)1) 2) 4) 6) 9)3) 1) Enable active Hold inactive, pulled up by 2) QV 3) Power-ON reset 4) Hold active, clamped to GND by externalm 5) Enable inactive, clamped by int. pull-down resistor 6) Pulse width smaller than 1 s 7) Hold inactive, released by 8) Voltage controller shutdown 9) Output-low reset 10) No switch on via VE6 possible after E6 was released toVE6 >VE6, relfor more than 4 sat sat s rel hold s tt C Cm m m mm

Semiconductor Group 11 1998-11-01 TLE 4267 Output Voltage V Q versus Temperature Tj Charge Current Id versus Temperature Tj Drop Voltage V Dr versus Output Current IQ Delay Switching Threshold V dT versus Temperature Tj AED01486 -40 4.70 Q T V I = 5.10 V 4.80 4.90 5.00 13.5 V C0 40 80 160 V j AED01485 -40 Id T V I = 13.5 V C0 40 80 160 A VC =0 V m dI j AED01488 IQ CT 125 C =2 5 100 200 300 400 500 mV 700 100 200 300 400 mA 600 DrV j j AED01487 -40 dT T V I = 13.5 V C0 40 80 160 0.5 1.0 1.5 2.0 2.5 3.0 V 4.0 VdT V j

Semiconductor Group 12 1998-11-01 TLE 4267 Current Consumption Iq versus Output Current IQ Output Current IQ versus Temperature Tj Current Consumption Iq versus Input Voltage V I Output Current IQ versus Input Voltage V I AED01490 IQ mA 100 200 300 400 mA 600 Iq V I = 13.5 V AED01489 -40 IQ T C0 40 80 160 mA 100 200 300 400 500 700

13.5 V=IV

j AED01491 qI = 10 20 30 50 R L IV V W25 mA AED01987 IQ V V i mA 100 200 300 400 500 600 700 10 20 30 40 50 125 C= = C25 jT jT

Semiconductor Group 13 1998-11-01 TLE 4267 Output Voltage V Q versus Inhibit Voltage V E2 Inhibit Current IE2 versus Inhibit Voltage V E2 AED01988 V Q V E2V 1 2 3 4 5 6V 0 AED01989 IE2 V V 1 2 3 4 5 6 Am

Semiconductor Group 14 1998-11-01 Package Outlines P-TO220-7-3 (Plastic Transistor Single Outline) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” Dimensions in mm

Semiconductor Group 15 1998-11-01 P-TO220-7-180 (Plastic Transistor Single Outline) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” Dimensions in mmSMD = Surface Mounted Device

Semiconductor Group 16 1998-11-01 P-TO220-7-230 (Plastic Transistor Single Outline) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” Dimensions in mm