TLE4269

TLE4269 SIEMENS | Alldatasheet

Document overview

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Technical content

Features

l Output voltage tolerance £ – 2 % l Very low current consumption l Early warning l Reset output low doown to VQ = 1 V l Overtemperature protection l Reverse polarity proof l Settable reset threshold l Very low drop voltage l Wide temperature range l Integrated pull up resistor at logic outputs t New type Type Ordering Code Package TLE 4269 A Q67000-A9190 P-DIP-8-4 TLE 4269 G Q67006-A9173 P-DSO-8-1 (SMD) t TLE 4269 GM Q67006-A9288 P-DSO-14-4 (SMD) TLE 4269 GL Q67006-A9192 P-DSO-20-6 (SMD)

Semiconductor Group 2 1998-11-01 Pin Configuration (top view) Pin Definitions and Functions (TLE 4269 A and TLE 4269 G) Pin No. Symbol Function 1 I Input; block directly to GND on the IC with a ceramic capacitor. 2S I Sense Input; if not needed connect to Q. 3R E Reset Threshold; if not needed connect to ground. 4D Reset Delay; to select delay time, connect to GND via external capacitor. 5G N D Ground 6R Reset Output; the open-collector output is internally linked to Q via a 20 kW pull-up resistor. 7S O Sense Output; the open-collector output is internally linked to the output via a 20 kW pull-up resistor. 8Q 5-V Output; connect to GND with a 10mF capacitor, ESR < 10W . GND R SO RE AEP01668 Q IS I P-DIP-8-4 P-DSO-8-1 S AEP01813 SO72 R63 GNDD5 4 RE I Q I

Semiconductor Group 3 1998-11-01 Pin Configuration (top view) Pin Definitions and Functions (TLE 4269 GM) Pin No. Symbol Function 1R E Reset Threshold; if not needed connect to GND. 2D Reset Delay; connect to GND via external delay capacitor for setting delay time. 3, 4, 5, 6 GND Ground 7R Reset Output; open-collector output, internally connected to Q via a pull-up resistor of 20 kW . 8S O Sense Output; open-collector output, internally connected to Q via a 20 kW pull-up resistor. 9Q 5-V Output; connect to GND with a 10mF capacitor, ESR < 10W . 10, 11, 12 GND Ground 13 I Input; block to GND directly at the IC by a ceramic capacitor. 14 SI Sense Input; if not needed connect to Q. P-DSO-14-4 AEP02248 Q GND SI GND R GND I GND GND GND 7S O D GND RE

Semiconductor Group 4 1998-11-01 Pin Configuration (top view) Pin Definitions and Functions (TLE 4269 GL) Pin No. Symbol Function 1R E Reset Threshold; if not needed connect to GND. 2D Reset Delay; to select delay time connect to GND via external capacitor. 4-7, 14-17 GND Ground

10 R Reset Output; the open-collector output is internally linked to

Q via 20 kW pull-up resistor.

11 SO Sense Output; the open-collector output is internally linked to

Q via 20 kW pull-up resistor. 12 Q Output; connect to GND with a 10mF capacitor, ESR < 10W . 19 I Input; block directly to GND at the IC by a ceramic capacitor. 20 SI Sense Input; if not needed connect to Q. P-DSO-20-6 N.C. N.C. N.C. GND N.C. Q RE D GND I AEP01802 N.C. GND GND R S GND SO GND GND GND I

Semiconductor Group 5 1998-11-01 Circuit Description The control amplifier compares a reference voltage, made highly accurate by resistance balancing, with a voltage proportional to the output voltage and drives the base of the series PNP transistor via a buffer. Saturation control as a function of the load current prevents any over-saturation of the power element. In the reset generator block a comparator compares a reference voltage independent of the input voltage with the scaled-down output voltage. If the output voltage reaches 4.6 V the reset delay capacitor is discharged and the reset output is set to low. This low is guaranteed down to an output voltage of 1 V. As the output voltage increases again, from 4.6 V onward the reset delay capacitor is charged with constant current. When the capacitor voltage reaches the upper switching threshold VdT, the reset returns to high. By choosing the value of this capacitor, the reset delay time can be selected over a wide range. With the reset threshold input RE it is possible to lower the reset threshold Vrt. If pin RE is connected to pin Q via a voltage divider, for example, the reset condition is reached when this voltage is decreased below the switching threshold Vre of 1.35 V. Another comparator compares the signal of the pin SI, normally fed by a voltage divider from the input voltage, with the reference and gives an early warning on the pin SO. It is also possible to superwise an other voltage e.g. of a second regulator, or to build a watchdog circuit with few external components. Application Description The input capacitor C I is necessary for compensating line influences. Using a resistor of approx. 1W in series with C I, the oscillating circuit consisting of input inductivity and input capacitance can be damped. The output capacitor C Q is necessary for the stability of the regulating circuit. Stability is guaranteed at values‡ 10 mF and an ESR £ 10 W within the operating temperature range. For small tolerances of the reset delay the spread of the capacitance of the delay capacitor and its temperature coefficient should be noted.

Semiconductor Group 6 1998-11-01 Block Diagram AEB01669 Control Saturation Current andReference Trimming 20 kWW k20 Amplifier Error Reference I D RE SI Q R SO

Semiconductor Group 7 1998-11-01 Absolute Maximum Ratings Tj= – 40 to 150°C Parameter Symbol Limit Values Unit Notes min. max. Input Input voltage VI – 40 45 V – Input current II – – – internal limited Sense Input Input voltage VSI – 0.3 45 V – Input current ISI 11m A – Reset Threshold Voltage VRE – 0.3 7 V – Current IRE – 10 10 mA – Reset Delay Voltage VD – 0.3 7 V – Current ID – – – internal limited Ground Current IGND 50 – mA – Reset Output Voltage VR – 0.3 7 V – Current IR – – – internal limited

Semiconductor Group 8 1998-11-01 Sense Output Voltage VSO – 0.3 7 V – Current ISO – – – internal limited 5-V Output Output voltage VQ – 0.3 7 V – Output current IQ –5 – m A – Temperature Junction temperature Tj – 150 °C– Storage temperature TStg – 50 150 °C – Operating Range Input voltage VI –4 5 V – Junction temperature Tj – 40 150 °C – Thermal Data Junction-ambient Rthja – 100 200 K/W K/W K/W K/W P-DIP-8-4 P-DSO-8-1 P-DSO-14-4 P-DSO-20-6 Rthjc –6 0 K/W K/W K/W K/W P-DIP-8-4 P-DSO-8-1 P-DSO-14-4 P-DSO-20-6 Absolute Maximum Ratings (cont’d) Tj= – 40 to 150°C Parameter Symbol Limit Values Unit Notes min. max.

Semiconductor Group 9 1998-11-01 Characteristics VI =1 3 . 5V ; Tj= – 40 °C< Tj< 125 °C Parameter Symbol Limit Values Unit Measuring Condition min. typ. max. Output voltage VQ 4.90 5.00 5.10 V 1 mA £ IQ £ 100 mA 6V £ VI £ 16 V Current limit IQ 150 200 500 mA – Current consumption; Iq = II – IQ Iq – 150 300 mA IQ £ 1m A ,Tj<8 5°C Current consumption; Iq = II – IQ Iq – 250 700 mA IQ =1 0m A Current consumption; Iq = II – IQ Iq –2 8 m A IQ =5 0m A Drop voltage Vdr –0 . 2 5 0 . 5 V IQ = 100 mA1) 1) Drop voltage =VI – VQ (measured when the output voltage has dropped 100 mV from the nominal value obtained at 13.5 V input.) Load regulation DVQ –1 0 3 0 m V IQ = 5 mA to 100 mA Line regulation DVQ –1 0 4 0 m V VI = 6 V to 26 V IQ =1m A Reset Generator Switching threshold Vrt 4.50 4.60 4.80 V – Reset pull up – 10 20 40 k W – Reset low voltage VR –0 . 1 0 . 4 V Rintern Delay switching threshold Vdt 1.4 1.8 2.2 V – Switching threshold Vst 0.3 0.45 0.60 V – Reset delay low voltageVD –0 . 1 V VQ < VRT Charge current Id 3.0 6.5 9.5 mA VD =1 V

Semiconductor Group 10 1998-11-01 Characteristics (cont’d) VI = 13.5 V; Tj= – 40 °C< Tj < 125 °C Parameter Symbol Limit Values Unit Measuring Condition min. typ. max. Delay time L fi H td 17 28 –m s C D =1 0 0n F Delay time H fi L tt –1 – ms C D =1 0 0n F Switching voltage Vre 1.26 1.35 1.44 V VQ >3 . 5V Input Voltage Sense Sense threshold high Vsi, high 1.24 1.31 1.38 V – Sense threshold low Vsi, low 1.16 1.20 1.28 V – Sense output low voltage VSO, low –0 . 1 0 . 4 V VSI <1 . 2 0V ; Vi >3V Rintern Sense pull up – 10 20 40 k W – Sense input current ISI – 10 . 11 mA –

Semiconductor Group 11 1998-11-01 Measuring Circuit (P-DIP-8-4/P-DSO-8-1) Reset Timing Diagram AES01670 1000 Fm VI QV II ID IGND IQ C D 100 nF IRE

22 Fm470 nF

I DV IS QC AED01542 Thermal td Power-on-Reset Voltage Dip Secondary Overload at OutputSpike VST V I V D V RO dI Vd dt VQ RTV tRR< RRt VDT at Input Undervoltage Shutdown C D

Semiconductor Group 12 1998-11-01 Sence Timing Diagram AED02559 t Sense t SI, HighV SI, LowV Input Voltage High Low Output Sense

Semiconductor Group 13 1998-11-01 TLE 4269 Charge Current Id versus Temperature Tj Drop Voltage Vdr versus Output Current IQ Switching Voltage Vdt and Vst versus Temperature Tj Reset Switching Threshold Vre versus Temperature Tj AED01803 -40 Id 04 0 8 0 120 C 160 IV = 13.5 V Am

1.0 V=V C

=2 5C IQ 30 60 90 120 180mA C125= 100 200 300 400 500 jT jT AED01804 -40 V 04 0 8 0 120 C 160 IV = 13.5 V 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 V Vst dtV D jT AED01806 -40 Vre 04 0 8 0 120 C 160 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 V jT

Semiconductor Group 14 1998-11-01 TLE 4269 Current Consumption IQ versus Input Voltage VI Sense Threshold Vsi versus Temperature Tj Output Voltage VQ versus Input Voltage VI Output Voltage VQ versus Temperature Tj AED01807 Iq mA 10 20 30 40 V5 0 IV R L =5 0 W W33=LR W100=LR R L = 200 W AED01809 -40 04 0 8 0 120 C 160 1.0 IV = 13.5 V V si 1.1 1.2 1.3 1.4 1.5 1.6 V Sense Output High Sense Output Low jT AED01808 VQ V 246 8 V1 0 IV R L =5 0 W AED01671 -40 VQ V 04 0 8 0 120 C 160 4.6 4.7 4.8 4.9 5.0 5.1 IV = 13.5 V 5.2 jT

Semiconductor Group 15 1998-11-01 TLE 4269 Output Current IQ versus Input Voltage VI Current Consumption Iq versus Output Current IQ Current Consumption Iq versus Output Current IQ AED01810 IQ mA 10 20 30 40 V5 0 =2 5C IV 100 150 200 250 300 350 C125= jT jT AED01812 Iq mA =2 5 C IQ

13.5 V=V I

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 10 20 30 40 50 jT AED01811 Iq mA =2 5 C IQ

Semiconductor Group 16 1998-11-01 Package Outlines P-DIP-8-4 (Plastic Dual In-line) GPD05583 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” Dimensions in mm

Semiconductor Group 17 1998-11-01 1.27 1.45-0.2 8.75-0.2 14 8 1.75 max 0.2 6 ±0.2 0.35 x 45˚ -0.24 0.1 -0.1 0.4+0.8 Index Marking +0.150.35 2) 2) Does not include dambar protrusion of 0.05 max. per side 1) Does not include plastic or metal protrusion of 0.15 max. per side 0.2 14x 0.19 +0.06 8˚ max. GPS05093 P-DSO-14-4 (SMD) (Plastic Dual Small Outline) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” Dimensions in mm SMD = Surface Mounted Device

Semiconductor Group 18 1998-11-01 P-DSO-8-1 (SMD) (Plastic Dual Small Outline) GPS05121 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” Dimensions in mmSMD = Surface Mounted Device

Semiconductor Group 19 1998-11-01 11 0 1120 Index Marking 1) Does not include plastic or metal protrusions of 0.15 max per side 2) Does not include dambar protrusion of 0.05 max per side GPS05094 2.65 max 0.1 0.2-0.1 2.45-0.2 +0.150.35 1.27 0.2 24x -0.27.6 1) 0.35 x 45˚ 0.238˚ max +0.09 +0.8 ±0.310.3 0.4 12.8-0.2 P-DSO-20-6 (SMD) (Plastic Dual Small Outline) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” Dimensions in mm SMD = Surface Mounted Device