TLE4262

TLE4262 SIEMENS | Alldatasheet

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Technical content

Features

l Output voltage tolerance £ – 2 % l Low-drop voltage l Very low standby current consumption l Overtemperature protection l Reverse polarity protection l Short-circuit proof l Settable reset threshold l Wide temperature range l Suitable for use in automotive electronics t New type Type Ordering Code Package TLE 4262 G Q67006-A9068 P-DSO-20-6 (SMD) t TLE 4262 GM Q67006-A9356 P-DSO-14-4 (SMD) Functional Description TLE 4262 G is a 5-V low-drop voltage regulator in a P-DSO-20-6 SMD package. The maximum input voltage is 45 V. The maximum output current is more than 200 mA. The IC is short-circuit proof and incorporates temperature protection that disables the IC at overtemperature. The IC regulates an input voltage VI in the range of 6 V < VI < 45 V to VQrated = 5.0 V. A reset signal is generated for an output voltage of VQ < 4.5 V. This voltage threshold can be decreased to 3.5 V by external connection. The reset delay can be set externally with a capacitor. The IC can be switched off via the inhibit input, which causes the current consumption to drop from 720mA to < 50mA.

Semiconductor Group 2 1998-11-01 Dimensioning Information on External Components The input capacitor C I is necessary for compensating line influences. Using a resistor of approx. 1W in series with C I, the oscillating circuit consisting of input inductivity and input capacitance can be damped. The output capacitor is necessary for the stability of the regulating circuit. Stability is guaranteed at values ‡ 22 mF and an ESR of £ 3 W within the operating temperature range. For small tolerances of the reset delay, the spread of the capacitance of the dalay capacitor and its temperature coefficient should be noted. Pin Configuration (top view) TLE 4262 G TLE 4262 GM N.C. IV1 AEP02588 QRES GND GND GND GND GND GND DRES N.C. SRES INH QV

Semiconductor Group 3 1998-11-01 Pin Definitions and Functions Pin Symbol Function 1I N H Inhibit; TTL-compatible, low-active input 2Q R E S Reset output; open-collector output internally connected to the output via a resistor of 30 kW . 4-7, 14-17 GND Ground 9D R E S Reset delay; connected to ground by a capacitor

10 SRES Reset threshold; for setting the switching threshold connect

by a voltage divider from output to ground. If this input is connected to GND, reset is triggered at an output voltage of 4.5 V. VQ 5-V output voltage; block to ground by a 22-mF capacitor.

20 VI Input voltage; block to ground directly at the IC by a ceramic

capacitor. 3, 8, 12, 13, 18, 19 N.C. Not connected

Semiconductor Group 4 1998-11-01 Circuit Description The control amplifier compares a reference voltage, which is kept highly accurate by resistance adjustment, to a voltage that is proportional to the output voltage and drives the base of the series transistor via a buffer. Saturation control as a function of the load current prevents any over-saturation of the power element. If the externally scaled down output voltage at the reset threshold input drops below 1.35 V, the external reset delay capacitor is discharged by the reset generator. If the voltage on the capacitor reaches the lower threshold VST , a reset signal is issued on the reset output and not cancelled again until the upper threshold VdT is exceeded. If the reset threshold input is connected to GND, reset is triggered at an output voltage of 4.5 V. The IC can be switched at the TTL-compatible, low-active inhibit input. It also incorporates a number of internal circuits for protection against: l Overload l Overtemperature l Reverse polarity Block Diagram

Semiconductor Group 5 1998-11-01 Absolute Maximum Ratings Parameter Symbol Limit Values Unit Remarks min. max. Input Input voltage Input current VI II –4 2 V internally limited Reset Output Voltage Current VR IR – 0.3 V internally limited Reset Input Reset threshold VRE – 0.3 6 V – Reset Delay Voltage Current Vd Id –0 . 3 V internally limited Output Voltage Current VQ IQ –5 . 2 5 VI V internally limited Inhibit Voltage Ve –4 2 4 5 V – Ground Current IGND –0 . 5 – A –

Semiconductor Group 6 1998-11-01 Temperature Junction temperature Storage temperature Tj Tstg –5 0 150 150 Operating Range Input voltage VI 5.2 45 V *) Junction temperature Tj – 40 150 °C– Thermal resistance junction-ambient junction-case Rth JA Rth JC K/W K/W soldered *) Corresponds with characteristics of drop voltage, output current and power description (see diagrams). Absolute Maximum Ratings (cont’d) Parameter Symbol Limit Values Unit Remarks min. max.

Semiconductor Group 7 1998-11-01 Characteristics VI = 13.5 V; Tj = 25 °C; Ve > 3.5 V; (unless specified otherwise) Parameter Symbol Limit Values Unit Test Condition min. typ. max. Normal Operation Output voltage VQ 4.9 5.00 5.10 V 5 mA £ IQ £ 150 mA;

6 V £ VI £ 28 V;

– 40 °C £ Tj £ 125 °C Output voltage VQ 4.95 5.00 5.05 V 6 V £ VI £ 32 V; IQ = 100 mA Tj > 100 °C Output current limitingIQ 200 250 mA – Current consumption; Iq = Ii – IQ Iq Iq Iq Iq 720 mA mA mA mA Ve < 0.8 V IQ = 0 mA IQ = 150 mA IQ = 150 mA; Vi = 4.5 V Drop voltage VDr – 0.35 0.6 V IQ = 150 mA *) Load regulation DVQ ––2 5 m V IQ = 5 mA to 150 mA Supply-voltage regulation DVQ – 1 52 5m V VI = 6 V to 28 V; IQ = 150 mA Ripple rejection SVR –5 4 –d B fr = 100 Hz; Vr = 0.5 Vpp Reset Generator Switching threshold VRT 4.2 4.5 4.8 V VRE = 0 V Switching voltage VRE 1.28 1.35 1.42 V VQ > 3.5 V Saturation voltage VR – 0.10 0.40 V IR = 1 mA *) Drop voltage VI ‡ 4.5 V; drop voltage = VI – VQ (below regulating range) Note: The reset output is low within the range VQ = 1 V to VRT .

Semiconductor Group 8 1998-11-01 Saturation voltage VC – 50 100 mV VQ < VRT Charge current Id 71 0 1 4 mA– Delay switching threshold VdT 1.5 1.7 2.1 V – Switching threshold VST 0.2 0.35 0.55 V – Delay time tD –1 7 –m s C d = 100 nF Delay time tt –2– ms C d = 100 nF Inhibit Switch-ON voltage Ve ON 3.5 – – V IC turned on Switch-OFF voltage Ve OFF – – 0.8 V IC turned off Input current Ie 51 0 1 5 mA Ve = 5 V Note: The reset output is low within the range VQ = 1 V to VRT . Characteristics (cont’d) VI = 13.5 V; Tj = 25 °C; Ve > 3.5 V; (unless specified otherwise) Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Semiconductor Group 9 1998-11-01 Application Circuit Test Circuit AES01084 Input 6 V...45 V KL15 Reset to MC TLE 4262G 470 nF nF100 Output

22 F 100 kW

m I TLE 4262G SVR = 20 log V V Dr r D QV V = IVV - Q r+I V V e V I C 100 nF d dI 9 4 470 nFm1000 F II 20 Ie 2 AES01082 cdGND V V R QV 5.6 k Q11 IR I W 22 Fm *) Below Regulating Range

Semiconductor Group 10 1998-11-01 Time Response Power-on-Reset Over- temperature Voltage Drop at Input Undervoltage Secondary Spike Load Bounce AET01085 V I QV cdV RTV dTV STV td tt RV tt< d =d d dt V C I

Semiconductor Group 11 1998-11-01 TLE 4262 G Charge Current versus Temperature Reset Switching Threshold versus Temperature Switching Voltage V dT and V ST versus Temperature Current Consumption of Inhibit versus Temperature Output Current C -40 80400 dI 160 AED01086 120 dI V I m A = 13.5 V V cd = 1.5 V jT 0.2 -40 0.6 0.4 0 160 j 80 120 T C 1.0 0.8 1.4 1.2 V 1.6 AED01088 V RE ST 1.2 0-40 0.8 0.4 3.2 2.8 2.4 2.0 V 1.6 V V I T 12080 C j 160 = 13.5 V AED01087 ,dTVV cd V AED01089 eV = 5 V Ie m A -40 0 80 40 120 T j 160 C

Semiconductor Group 12 1998-11-01 Output Voltage versus Temperature Input Response Output Current versus Input Voltage Load Response V 0-40 4.6 4.7 4.8 5.1 5.2 V 5.0 4.9 T 12080 C j 160 = 13.5 Ve AED01090 V Q -10 -20 -40 3020100 V I AED01092 t Q mV V VD D m s40 C Q = 22 Fm ft m1 s=tr T 100 100 250 300 QI mA 200 150 V 4030 V I = 25 Cj AED01091 = 22 F 200 mV 100 -200 -100 D QV 01 0-10 C Q D QI 150 mA 295 40 sm 5030 t m AED01093 TLE 4262 G

Semiconductor Group 13 1998-11-01 Drop Voltage versus Output Current Current Consumption versus Input Voltage Current Consumption versus Output Current Output Voltage versus Input Voltage 400 200 300 100 500 100 800 600 700 500 DrV mA200150 300 IQ AED01094 mV jT = 125 C 25 C 2001 0 mA qI = 25R L 50V30 40 V I AED01096 W 150 10005 0 mA 300200 mA IQ AED01095 IV = 13.5 V Iq R 40 2 QV V 10V68 V I AED01097 = 25L W

Semiconductor Group 14 1998-11-01 Package Outlines 11 0 1120 Index Marking 1) Does not include plastic or metal protrusions of 0.15 max per side 2) Does not include dambar protrusion of 0.05 max per side GPS05094 2.65 max 0.1 0.2-0.1 2.45-0.2 +0.150.35 1.27 0.2 24x -0.27.6 1) 0.35 x 45˚ 0.238˚ max +0.09 +0.8 ±0.310.3 0.4 12.8-0.2 P-DSO-20-6 (Plastic Dual Small Outline) Weight approx. 0.6 g Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mmSMD = Surface Mounted Device

Semiconductor Group 15 1998-11-01 1.27 1.45-0.2 8.75-0.2 14 8 1.75 max 0.2 6 ±0.2 0.35 x 45˚ -0.24 0.1 -0.1 0.4+0.8 Index Marking +0.150.35 2) 2) Does not include dambar protrusion of 0.05 max. per side 1) Does not include plastic or metal protrusion of 0.15 max. per side 0.2 14x 0.19 +0.06 8˚ max. GPS05093 P-DSO-14-4 (Plastic Dual Small Outline) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mmSMD = Surface Mounted Device