TLE4208 SIEMENS | Alldatasheet

Document overview

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Technical content

Features

  • Driver for up to 3 motors
  • Delivers up to 0.8 A continuous
  • Optimized for DC motor management applications
  • Very low current consumption in stand-by (Inhibit) mode
  • Low saturation voltage ; typ.1.2 V total @ 25°C; 0.4 A
  • Output protected against short circuit
  • Error flag diagnosis
  • Overvoltage lockout and diagnosis
  • Undervoltage lockout
  • CMOS/TTL compatible inputs with hysteresis
  • No crossover current
  • Internal clamp diodes
  • Overtemperature protection with hysteresis and diagnosis
  • Enhanced power P-DSO-Package

Description

The TLE 4208 is a fully protectedQuad-H alf-B ridge-D river designed specially for automotive and industrial motion control applications. The part is built using the Siemens bipolar high voltage power technology DOPL. In a cascade configuration up to three actuators (DC motors) can be connected between the four half-bridges. These four half-bridges are configured as 2 dual-half-bridges, which are supplied and controlled separately. Operation modes forward (cw), reverse (ccw), brake and high impedance are invoked from a standard interface. The standard enhanced power P-DSO-28 package meets the application requirements and saves PCB-board space and costs. Furthermore the built-in features like diagnosis, over- and undervoltage-lockout, short- circuit protection, over-temperature protection and the very low quiescent current in stand-by mode will open a wide range of automotive and industrial applications. Type Ordering Code Package TLE 4208 G Q67007-A9335 P-DSO-28-6

Semiconductor Group 2 1998-06-03 Figure 1 Pin Configuration(top view) 12 8 AEP02349 TLE 4208 G 21 GND GND GND OUT1 N.C. N.C. OUT3 GND IN1 GND IN3 N.C. IN4 EF OUT4 GND GND GND GND OUT2 IN2 GND V S34 S12V 12INH N.C. 34INH EF 12

Semiconductor Group 3 1998-06-03 Pin Definitions and Functions Pin No. Symbol Function 1, 6, 7, 8, 9, 14, 20, 21, 22, 23 GND Ground; negative reference potential for blocking capacitor 2E F

12 Error Flag output of half-bridges 1and 2;

open collector; low = error

3 IN1 Input channel of half-bridge 1;

4, 11, 15, 28 N.C. Not connected

5 OUT1 Power output of half-bridge 1;

full short circuit protected; with integrated clamp diodes

10 OUT3 Power output of half-bridge 3;

full short-circuit protected; with integrated clamp diodes

12 IN3 Input channel of half-bridge 3;

13 INH 34 Inhibit input of half-bridges 3 and 4;

low = half-bridges 3 and 4 in stand-by

16 EF 34 Error Flag output of half-bridges 3 and 4;

open collector; low = error

17 IN4 Input channel of half-bridge 4;

18 VS34 Power supply voltage of half-bridges 3 and 4;

positive reference potential for blocking capacitor

19 OUT4 Power output of half-bridge 4;

full short circuit protected; with integrated clamp diodes

24 OUT2 Power-output of half-bridge 2;

full short circuit protected; with integrated clamp diodes

25 VS12 Power supply voltage of half-bridges 1 and 2;

positive reference potential for blocking capacitor

26 IN2 Input channel of half-bridge 2;

27 INH 12 Inhibit input of half-bridges 1and 2;

low = half-bridges 1 and 2 in stand-by

Semiconductor Group 4 1998-06-03 Figure 2 Block Diagram Fault-Detection 1,2 IN1 IN2 OUT1 OUT2 ZXZ X L0 L0 H0 L1 L1 H0 H1 H11 Inhibit 1,2 OUT4 Inhibit 3,4 Fault-Detection 3,4 X IN3 OUT3 X IN4 LH H H H L L Z L Z TLE 4208 G 9,14, 20,21, DRV1 DRV2 DRV3 DRV4 OUT4 OUT3 OUT2 OUT1 GND IN1 IN2 IN3 IN4 V S12 S34V INH AEB02350 22,23 EF 12 INH EF 34 1,6,7,8, 34INH INH 12

Semiconductor Group 5 1998-06-03 Note: Half-Bridge 1 and 2 connected to a full-bridge IN: 0 = Logic LOW OUT: Z = Output in tristate condition 1 = Logic HIGH L = Output in sink condition X = don’t care H = Output in source condition Note: Half-Bridge 3 and 4 connected to a full-bridge Input Logic Functional Truth Table of Halfbridge 1 and 2 INH12 IN1 IN2 OUT1 OUT2 Mode

0 X X Z Z Stand-By

L L H H L H L H Brake LL CW CCW Brake HH Functional Truth Table of Half-Bridge 3 and 4 INH

34 IN3 IN4 OUT3 OUT4 Mode

L L H H L H L H Brake LL CW CCW Brake HH Diagnosis EF

12 EF 34 Error

over temperature of half-bridge 1 and 2 or over voltage of half-bridge 1 and 2 over temperature of half-bridge 3 and 4 or over voltage of half-bridge 3 and 4 over temperature of all half-bridges or over voltage of all half-bridges

Semiconductor Group 6 1998-06-03

Electrical Characteristics

Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. Absolute Maximum Ratings Parameter Symbol Limit Values Unit Remarks min. max. Voltages Supply voltage VS12, VS34 – 0.3 45 V – Supply voltage VS12, VS34 – 1 – V t < 0.5 s; IS12,IS34 > – 2 A Logic input voltages (IN1; IN2; INH12; IN3; IN4; INH34) VI – 5 20 V 0V < VS12, VS34 < 45 V Logic output voltage (EF12; EF34) VEF12 , VEF34 – 0.3 20 V 0 V < VS12, VS34 < 45 V Currents Output current (cont.)IOUT1-4 – – A internally limited Output current (peak)IOUT1-4 – – A internally limited Output current (diode)IOUT1-4 –1 1 A – Output current (EF) IEF12-34 –2 5 mA – Temperatures Junction temperature Tj – 40 150 °C– Storage temperature Tstg – 50 150 °C– Thermal Resistances Junction pin Rthj-pin – 25 K/W measured to pin 7 Junction ambient RthjA – 65 K/W –

Semiconductor Group 7 1998-06-03 Note: In the operating range the functions given in the circuit description are fulfilled. Operating Range Parameter Symbol Limit Values Unit Remarks min. max. Supply voltage VS12, VS34 VUV OFF 18 V After VS12,VS34 rising above VUV ON Supply voltage increasingVS12, VS34 – 0.3 VUV ON V Outputs in tristate Supply voltage decreasingVS12, VS34 – 0.3 VUV OFF V Outputs in tristate Logic input voltages (IN1; IN2; INH12; IN3; IN4; INH34) VI – 2 18 V – Junction temperature Tj – 40 150 °C–

Semiconductor Group 8 1998-06-03

8 V <VS12 =VS34 < 18 V; INH12 = INH34 = HIGH;IOUT1-4 = 0 A; – 40°C < Tj < 150°C;

unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max. Current Consumption INH12 = INH34 = LOW Quiescent current IS – – 100 mA IS =IS12 +IS34 Quiescent current IS –2 0 4 0 mA IS =IS12 +IS34; VS12 = VS34 = 13.2 V; Tj = 25°C INH12 = HIGH and INH34 = LOW or INH12 = LOW and INH34 = HIGH Supply current IS12,IS34 –1 0 2 0 m A – Supply current IS12,IS34 – – 30 mA IOUT1/3 = 0.4 A IOUT2/4 = – 0.4 A Supply current IS12,IS34 – – 50 mA IOUT1/3 = 0.8 A IOUT2/4 = – 0.8 A Over- and Under Voltage Lockout UV Switch ON voltage VUV ON – 6.5 7.5 V VS12,VS34 increasing UV Switch OFF voltage VUV OFF 56 – V VS12,VS34 decreasing UV ON/OFF hysteresis VUV HY – 0.5 – V VUV ON –VUV OFF OV Switch OFF voltage VOV OFF –2 0 2 4 V VS12,VS34 increasing OV Switch ON voltage VOV ON 18 19.5 – V VS12,VS34 decreasing OV ON/OFF hysteresis VOV HY – 0.5 – V VOV OFF –VOV ON

Semiconductor Group 9 1998-06-03 Outputs OUT1; OUT2; OUT 3; OUT 4 Saturation Voltages Source (upper) IOUT12 , IOUT34 = – 0.2 A VSAT U – 0.85 1.15 V Tj = 25°C Source (upper) IOUT12 , IOUT34 = – 0.4 A VSAT U – 0.90 1.20 V Tj = 25°C Sink (upper) IOUT12 , IOUT34 = – 0.8 A VSAT U – 1.10 1.50 V Tj = 25°C Sink (lower) IOUT12 , IOUT34 = 0.2 A VSAT L – 0.15 0.23 V Tj = 25°C Sink (lower) IOUT12 , IOUT34 = 0.4 A VSAT L – 0.25 0.40 V Tj = 25°C Sink (lower) IOUT12 , IOUT34 = 0.8 A VSAT L – 0.45 0.75 V Tj = 25°C Total Drop IOUT12 , IOUT34 = 0.2 A VSAT – 1 1.4 V VSAT = VSAT U + VSAT L Total Drop IOUT12 , IOUT34 = 0.4 A VSAT – 1.2 1.7 V VSAT = VSAT U + VSAT L Total Drop IOUT12 , IOUT34 = 0.8 A VSAT – 1.6 2.5 V VSAT = VSAT U + VSAT L Clamp Diodes Forward voltage; upper VFU – 1 1.5 V IF = 0.4 A Upper leakage current ILKU –– 5 m A IF = 0.4 A1) Forward voltage; lower VFL – 0.9 1.4 V IF = 0.4 A Notes see page 11. Electrical Characteristics(cont’d) unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Semiconductor Group 10 1998-06-03 Input Interface Logic Inputs IN1; IN2; IN3; IN4 H-input voltage VIH – 2.0 3.0 V – L-input voltage VIL 1.0 1.5 – V – Hysteresis of input voltageVIHY – 0.5 – V – H-input current IIH –2 – 1 0 mA VI = 5 V L-input current IIL – 100 – 20 – 5 mA VI = 0 V Logic Inputs INH12; INH34 H-input voltage VIH – 2.7 3.5 V – L-input voltage VIL 1.0 2.0 – V – Hysteresis of input voltageVIHY – 0.7 – V – H-input current IIH – 100 250 mA VINH = 5 V L-input current IIL –1 0 – 1 0 mA VINH = 0 V Error-Flags EF12; EF34 L-output voltage level VEFL – 0.2 0.4 V IEF = 2 mA Leakage current IEFLK – – 1 0 mA 0 V < VEF < 7 V Electrical Characteristics(cont’d) unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Semiconductor Group 11 1998-06-03 Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply atTA = 25°C and the given supply voltage. 1) Guaranteed by design. Thermal Shutdown Thermal shutdown junction temperature TjSD 150 175 200 °C– Thermal switch-on junction temperature TjSO 120 – 170 °C– Temperature hysteresis DT –3 0 – K – Electrical Characteristics(cont’d) unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Semiconductor Group 12 1998-06-03 Figure 3 Application Circuit 1 (Device is used as Dual-Full-Bridge-Driver) Fault-Detection 1,2 IN1 IN2 OUT1 OUT2 ZXZ X L0 L0 H0 L1 L1 H0 H1 H11 Inhibit 1,2 OUT4 Inhibit 3,4 Fault-Detection 3,4 X IN3 OUT3 X IN4 LH H H H L L Z L Z TLE 4208 G 6,7,8,9, 20,21, DRV1 DRV2 DRV3 OUT4 OUT3 OUT2 OUT1 GND IN1 IN2 IN3 IN4 V S12 S34V EF34 INH34 EF12 INH12 AES02351 Cm TLE 4278 G 3,4,5,10,11,12 769 Q Reset Out Watchdog Out Watchdog In 13 Watchdog Adjust Input V CCRWDIWDO 1N4001 C 22 F S m100 nF C I 100 k R WA W Reset Adjust GNDD 100 nF C D 22 Fm C Q W10 k QBR10 kW QAR VS = 12 V DRV4 INH12 INH34 22,23

Semiconductor Group 13 1998-06-03 Diagrams Quiescent currentIS over Temperature Saturation Voltage of SinkV SAT L over Temperature -50 0 A 15050 IS C AED02352 100 T j SV = 18 V = 13.2 VV S = 8 VV S m AED02309 -50 mV SAT LV ˚C0 50 100 150 = 800 mAOUTI = 14 VSV 250 500 750 1000 = 400 mAOUTI = 200 mAOUTI Tj Saturation Voltage of SourceV SAT U over Temperature Total Drop at outputsV SAT over Temperature AED02308 -50 mV SAT UV IOUT = 800 mA ˚C0 50 100 150 250 500 750 1000 1250 1500 = 400 mAOUTI = 200 mAOUTI = 14 VSV Tj AED02310 -50 mV SAT V ˚C0 50 100 150 = 14 VSV 500 1000 1500 2000 = 800 mAOUTI = 400 mAOUTI = 200 mAOUTI Tj

Semiconductor Group 14 1998-06-03 Package Outlines 11 4 1528 18.1-0.4 Index Marking 2.45 -0.1 7.6 10.3±0.3 -0.2 0.2 2.65 max -0.2 1.27 0.23 +0.09 0.1 0.4 0.35 x 45˚ +0.8 +0.150.35 2) 8˚ max 0.2 28x 2) Does not include dambar protrusion of 0.05 max per side 1) Does not include plastic or metal protrusions of 0.15 max rer side GPS05123 P-DSO-28-6 (Plastic Dual Small Outline Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mmSMD = Surface Mounted Device