TLE4207 SIEMENS | Alldatasheet

Document overview

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Technical content

Features

  • Delivers up to 0.8 A continuous
  • Optimized for DC motor management applications
  • Very low current consumption in stand-by (Inhibit) mode
  • Low saturation voltage; typ.1.2 V total @ 25°C; 0.4 A
  • Output protected against short circuit
  • Error flag diagnosis
  • Overvoltage lockout and diagnosis
  • Undervoltage lockout
  • CMOS/TTL compatible inputs with hysteresis
  • No crossover current
  • Internal clamp diodes
  • Overtemperature protection with hysteresis and diagnosis
  • Enhanced power P-DSO-Package

Description

The TLE 4207 is a fully protected Dual-H alf-B ridge-D river designed specially for automotive and industrial motion control applications. The part is built using the Siemens bipolar high voltage power technology DOPL. The actuator (DC motor) can be connected direct between the halfbridges. Operation modes forward (cw), reverse (ccw), brake and high impedance are invoked from a standard interface. The standard enhanced power P-DSO-14 package meets the application requirements and saves PCB-board space and costs. Furthermore the built in features like diagnosis, over- and undervoltage-lockout, short- circuit-protection, over-temperature-protection and the very low quiescent current in stand-by mode will open a wide range of automotive and industrial applications. Type Ordering Code Package TLE 4207 G Q67006-A9275 P-DSO-14-4 TLE 4207 GL on request P-DSO-20-6

Semiconductor Group 2 1998-02-01 Figure 1 Pin Configuration (top view) Pin Definitions and Functions Pin No. P-DSO-14-4 Pin No. P-DSO-20-6 Symbol Function

11 VS Power supply voltage;

positive reference potential for blocking capacitor 22O U T 2 Power-output 2; full short circuit protected; with integrated clamp diodes 3, 4, 5, 10, 11, 12 4, 5, 6, 7, 14, 15, 16, GND Ground; negative reference potential for blocking capacitor 69I N 2 Input channel 2; controls OUT2 (not inverted) 71 0 I N H Inhibit input; low = IC in stand-by 81 1 E F Error Flag output; open collector; low = error 91 2 I N 1 Input channel 1; controls OUT1 (not inverted) 13 19 OUT1 Power output 1; full short circuit protected; with integrated clamp diodes 14 3, 8, 13, 18, 20 N.C. Not connected AEP02303 INH IN2 GND OUT2 IN1 GND OUT1 N.C. GND GND GND GND VS EF TLE 4207G AEP02304

11 EFINH

N.C. N.C. GND GND GND GND GND GND GND GND N.C. N.C. OUT2 OUT1 N.C. SV TLE 4207GL

Semiconductor Group 3 1998-02-01 Figure 2 Block Diagram AEB02080 IN2 OUT2 XXZZ LL00 HL10 LH01 HH11 OUT1 OUT2 4207GTLE OUT1IN1INH GND Fault-Detection DRV1 DRV2 Inhibit VS INH EF IN1 IN2 6 3, 4, 5, 10, 11, 12

Semiconductor Group 4 1998-02-01 IN: 0 = Logic LOW OUT: Z = Output in tristate condition 1 = Logic HIGH L = Output in sink condition X = don’t care H = Output in source condition Functional Truth Table INH IN1 IN2 OUT1 OUT2 Mode

0 X X Z Z Stand-By

L L H H L H L H Brake LL CW CCW Brake HH Diagnosis EF Error no error over temperature over voltage

Semiconductor Group 5 1998-02-01

Electrical Characteristics

Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. Absolute Maximum Ratings Parameter Symbol Limit Values Unit Remarks min. max. Voltages Supply voltage VS – 0.3 45 V – Supply voltage VS – 1 – V t < 0.5 s; IS > – 2 A Logic input voltages (IN1; IN2; INH) VI – 5 20 V 0 V < VS < 45 V Logic output voltage (EF)VEF – 0.3 20 V 0 V < VS < 45 V Currents Output current (cont.) IOUT1-2 – – A internally limited Output current (peak) IOUT1-2 – – A internally limited Output current (diode) IOUT1-2 –1 1 A – Output current (EF) IOUT1-2 –2 5 m A – Temperatures Junction temperature Tj – 40 150 °C– Storage temperature Tstg – 50 150 °C– Thermal Resistances Junction pin Rthj-pin – 25 K/W measured to pin 5 Junction ambient RthjA –6 5 K / W –

Semiconductor Group 6 1998-02-01 Note: In the operating range the functions given in the circuit description are fulfilled. Operating Range Parameter Symbol Limit Values Unit Remarks min. max. Supply voltage VS VUV OFF 18 V After VS rising above VUV ON Supply voltage increasing VS – 0.3 VUV ON V Outputs in tristate Supply voltage decreasing VS – 0.3 VUV OFF V Outputs in tristate Logic input voltage (IN1; IN2; INH) VI – 2 18 V – Junction temperature Tj – 40 150 °C–

Semiconductor Group 7 1998-02-01

8 V < VS < 18 V; INH = High; IOUT1-2 = 0 A; – 40 °C < Tj < 150 °C;

unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max. Current Consumption Quiescent current IS –2 0 5 0 mA INH = LOW Quiescent current IS –2 0 3 0 mA INH = LOW; VS = 13.2 V; Tj = 25°C Supply current IS –1 0 2 0 m A – Supply current IS –– 3 0 m A IOUT1 = 0.4 A IOUT2 = – 0.4 A Supply current IS –– 5 0 m A IOUT1 = 0.8 A IOUT2 = – 0.8 A Over- and Under Voltage Lockout UV Switch ON voltage VUV ON –6 . 5 7 . 5 V VS increasing UV Switch OFF voltage VUV OFF 5.0 6 – V VS decreasing UV ON/OFF hysteresis VUV HY –0 . 5 – V VUV ON – VUV OFF OV Switch OFF voltage VOV OFF –2 0 2 4 V VS increasing OV Switch ON voltage VOV ON 18.0 19.5 – V VS decreasing OV ON/OFF hysteresis VOV HY –0 . 5 – V VOV OFF – VOV ON

Semiconductor Group 8 1998-02-01 Outputs OUT1-2 Saturation Voltages Source (upper) IOUT = – 0.2 A VSAT U – 0.85 1.15 V Tj = 25 °C Source (upper) IOUT = – 0.4 A VSAT U – 0.90 1.20 V Tj = 25 °C Sink (upper) IOUT = – 0.8 A VSAT U – 1.10 1.50 V Tj = 25 °C Sink (lower) IOUT = 0.2 A VSAT L – 0.15 0.23 V Tj = 25 °C Sink (lower) IOUT = 0.4 A VSAT L – 0.25 0.40 V Tj = 25 °C Sink (lower) IOUT = 0.8 A VSAT L – 0.45 0.75 V Tj = 25 °C Total Drop IOUT = 0.2 A VSAT –1 1 . 4 V VSAT = VSAT U + VSAT L Total Drop IOUT = 0.4 A VSAT –1 . 2 1 . 7 V VSAT = VSAT U + VSAT L Total Drop IOUT = 0.8 A VSAT –1 . 6 2 . 5 V VSAT = VSAT U + VSAT L Clamp Diodes Forward voltage; upper VFU –1 1 . 5 V IF = 0.4 A Upper leakage current ILKU –– 5 m A IF = 0.4 A1) Forward voltage; lower VFL –0 . 9 1 . 4 V IF = 0.4 A Notes see page 10. Electrical Characteristics (cont’d) unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Semiconductor Group 9 1998-02-01 Input-Interface Logic Inputs IN1; IN2 H-input voltage VIH –2 3 V – L-input voltage VIL 11 . 5 – V – Hysteresis of input voltageVIHY –0 . 5 – V – H-input current IIH –2 – 1 0 mA VI = 5 V L-input current IIL –1 0 0 –2 0 –5 mA VI = 0 V Logic Input INH H-input voltage VIH –2 . 7 3 . 5 V – L-input voltage VIL 12 – V – Hysteresis of input voltageVIHY –0 . 7 – V – H-input current IIH – 100 250 mA VINH = 5 V L-input current IIL –1 0 – 1 0 mA VINH = 0 V Error-Flag EF L-output voltage level VEFL –0 . 2 0 . 4 V IEF =2 m A Leakage current IEFLK – – 1 0 mA0 V < VEF < 7 V Electrical Characteristics (cont’d) unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Semiconductor Group 10 1998-02-01 Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25°C and the given supply voltage. 1) Guaranteed by design. Thermal Shutdown Thermal shutdown junction temperature TjSD 150 175 200 °C – Thermal switch-on junction temperature TjSO 120 – 170 °C– Temperature hysteresis DT –3 0 – K – Electrical Characteristics (cont’d) unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Semiconductor Group 11 1998-02-01 Figure 3 Application Circuit AES02081 SV = 12 V Watchdog Reset Q DG N D I WD R CCV IN2 OUT2 XXZZ LL00 HL10 LH01 HH11 RQ 10 kW CQ CD 100 nF EF IN1 IN2 OUT1 OUT2 1N4001 22 F P F22 CS TLE 4268G 4207GTLE OUT1IN1INH GND Fault-Detection DRV1 DRV2 InhibitINH VS DO1 10, 11, 12 3, 4, 5, 6 2 m mm

Semiconductor Group 12 1998-02-01 Diagrams Quiescent current IS over Temperature Saturation Voltage of Sink VSAT L over Temperature AED02307 -50 A SI V S = 18 V ˚C0 50 100 150 = 13.2 VSV = 8 VSV m Tj AED02309 -50 mV SAT LV ˚C0 50 100 150 = 800 mAOUTI = 14 VSV 250 500 750 1000 = 400 mAOUTI = 200 mAOUTI Tj Saturation Voltage of Source VSAT U over Temperature Total Drop at outputs VSAT over Temperature AED02308 -50 mV SAT UV IOUT = 800 mA ˚C0 50 100 150 250 500 750 1000 1250 1500 = 400 mAOUTI = 200 mAOUTI = 14 VSV Tj AED02310 -50 mV SAT V ˚C0 50 100 150 = 14 VSV 500 1000 1500 2000 = 800 mAOUTI = 400 mAOUTI = 200 mAOUTI Tj

Semiconductor Group 13 1998-02-01 Package Outlines 1.27 1.45-0.2 8.75-0.2 14 8 1.75 max 0.2 6 ±0.2 0.35 x 45˚ -0.24 0.1 -0.1 0.4+0.8 Index Marking +0.150.35 2) 2) Does not include dambar protrusion of 0.05 max. per side 1) Does not include plastic or metal protrusion of 0.15 max. per side 0.2 14x 0.19 +0.06 8˚ max. GPS05093 P-DSO-14-4 (Plastic Dual Small Outline Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mmSMD = Surface Mounted Device

Semiconductor Group 14 1998-02-01 11 0 1120 Index Marking 1) Does not include plastic or metal protrusions of 0.15 max per side 2) Does not include dambar protrusion of 0.05 max per side GPS05094 2.65 max 0.1 0.2-0.1 2.45-0.2 +0.150.35 1.27 0.2 24x -0.27.6 1) 0.35 x 45˚ 0.238˚ max +0.09 +0.8 ±0.310.3 0.4 12.8-0.2 P-DSO-20-6 (Plastic Dual Small Outline Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mmSMD = Surface Mounted Device