TLE4205G

TLE4205 SIEMENS | Alldatasheet

Document overview

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Technical content

Features

l Max. driver current 1 A l Integrated free-wheeling diodes l Short-circuit proof to ground l Inhibit l ESD protected inputs l Temperature range – 40 °C £ Tj £ 150 °C

Semiconductor Group 2 1998-02-01 Figure 1 Pin Configuration (top view) TLE 4205 TLE 4205 G AEP00636 GND V S 10INH GND must be connected to Pin 4 I + I1 I1- GND GND N.C. I AEP01318 I GND GND SV GND GND I2+ N.C. GND GND N.C. INH I-1 N.C. 12 0 21 9 31 8 41 7 51 6 61 5 71 4 81 3 9 12

Semiconductor Group 3 1998-02-01 Pin Definitions and Functions Pin No. Symbol Function 1Q 1 Output Q1 of channel 1; push-pull B output with DC short-circuit protection to ground. Integrated free-wheeling diodes to ground and the supply voltage.

2 VS Supply voltage V S; must be blocked to ground with a ceramic

capacitor of at least 100 nF directly on the pins of the IC. 3Q 2 Output Q2 of channel 2; see pin 1.

4 GND Ground

5 – I2 Inverting input channel 2; to be wired according to general rules. 6 + I2 Non-inverting input channel 2; to be wired according to general rules. 7 + I1 Non-inverting input channel 1; see pin 6. 8 – I1 Inverting input channel 1; see pin 5. 9I N H Inhibit; the IC is passive when this pin is open or connected to ground. 10-18 GND Ground; must be connected to pin 4.

Semiconductor Group 4 1998-02-01 Pin Definitions and Functions (TLE 4205 G) Pin No. Symbol Function 1Q 2 Output 2 of channel 2; push-pull B output with DC short-circuit protection to ground. Integrated free-wheeling diodes to ground and the supply voltage. 2 N.C. Not connected 3 N.C. Not connected 4-7 GND Ground 8 – I2 Inverting input channel 2; to be wired according to general rules. 9 + I2 Non-inverting input channel 2; to be wired according to general rules. 10 + I1 Non-inverting input channel 1; see pin 9. 11 – I1 Inverting input channel 1; see pin 8.

12 INH Inhibit; the IC is passive when this pin is open or connected to

ground. 13 N.C. Not connected 14-17 GND Ground 18 N.C. Not connected 19 Q1 Output Q1 of channel 1, see pin 1. VS Supply voltage V S; must be blocked with a ceramic capacitor of at least 100 nF directly on the pins of the IC.

Semiconductor Group 5 1998-02-01 Figure 2 Block Diagram AEB00637 VS 2 (20) (19) Power Limiting for T1, T3 Temperature Protection (1) (14-17) GND (4-7) (9) (8) INH 9 (12) 1 7 (11) (10) 4, 10-18 I I + I

Semiconductor Group 6 1998-02-01 Circuit Description The IC contains two amplifiers with typical open-loop gain of 80 dB at 500 Hz. The input stages consist of PNP-differential amplifiers. This produces a common-mode input range of 0 V to nearly VS and a maximum differential input voltage of VS. The IC is guarded against ground shorts by an SOA-protective circuit. The output transistors are turned off if the chip temperature exceeds approx. 160 °C. The IC can be turned off by an inhibit input, which very much reduces current consumption. Figure 3 Circuit Diagram AES00665 (1) (3) Q Q GND VS (5) (4) (2) I I + I (10-18) 200 kWWk10 INH 10 kW Wk10 GND (9) (6) (8) (7) Wk10 10 kW TLE 4205 Wk30

Semiconductor Group 7 1998-02-01 Absolute Maximum Ratings Tj = - 40 to 150 °C Parameter Symbol Limit Values Unit Remarks min. max. Supply voltage VS –0 . 3 4 5 V – Differential input voltageVID – – VS V DV6-5 or DV7-8 TLE 4205 DV8-9 or DV10-11 TLE 4205 G Output current IQ – 1 1 A – Supply current IS 2.5 3 A – Ground current IGND –3 2 . 5 A I 2 Input voltage VI –1 5 VS V V5; V6; V7; V8 TLE 4205 V8; V9; V10; V11 TLE 4205 G Inhibit input VInh –1 5 VS V V9 TLE 4205 V12 TLE 4205G Junction temperature Tj – 150 °C– Storage temperature Tstg – 50 150 °C– Operating Range Supply voltage VS 63 2 V – Case temperature TC – 40 105 °C PDmax = 3 W; DIP Case temperature TC – 40 95 °C PDmax = 3 W; SO Thermal resistance junction - ambient junction - case Rth JA Rth JC K/W K/W TLE 4205 TLE 4205 Thermal resistance junction - ambient junction - case Rth JA Rth JC K/W K/W TLE 4205 G TLE 4205 G Outputs pin 1 (19) and pin 3 (1) short-circuit proof to GND at VS £ 18 V for TLE 4205 (TLE 4205G)

Semiconductor Group 8 1998-02-01 Characteristics 6V < VS < 18 V; – 40 °C < Tj < 150 °C Parameter Symbol Limit Values Unit Test Condition min. typ. max. General Open-circuit current consumption IS – 10 30 mA active, both outputs high Open-circuit current consumption IS –1 0 1 0 0 mA inhibit Turn-ON dead time ref. to V9 OFF/ON td ON –1 0 2 0 ms| I1,3| < 1 A TLE 4205 I1,19| < 1 A TLE 4205 G Turn-OFF dead time ref. to V9 OFF/ON td OFF –1 0 2 0 ms| I1,3| < 1 A TLE 4205 |I1,19| < 1 A TLE 4205 G Open-loop gain G VO 50 80 – dB f = 500 Hz Inputs Input zero voltage VIO – 7.5 – 7.5 mV RS = 10 kW; Input-voltage driftDVIO/DT –2 0 3 0 mV/K – Input zero current IIO –7 5 – 7 5 m A – Input current II – 300 – 300 nA – Input-current driftDII/DT ––5n A / K – Input common-mode range, positive VIC –– VS – 2 V – Input common-mode range, negative VIC ––– 0 . 5 V– Power-supply rejection ratio PSSR ––2 0 0 mV/V RS = 10 kW; Common-mode rejection ratio CMRR 70 80 – dB –

Semiconductor Group 9 1998-02-01 Note: VSat U = upper VSat L = lower Outputs Saturation voltage VSat U – 1.35 1.5 V IQ = – 0.6 A Saturation voltage VSat L –0 . 8 1 . 2 V IQ = 0.6 A Forward voltage of free-wheeling diode VFU –11 . 5 V IF = 0.6 A Forward voltage of free-wheeling diode VFL –11 . 5 V IF = 0.6 A; Slew rate of VQ dVqdtr –0 . 5 –V / ms– Inhibit Input Switching threshold high VIH 2––V– Switching threshold low VIL ––0 . 8 V– H-input current IIH –1 0 0 – mA V9 = 5 V L-input current IIH –0– mA V9 = 0 V Characteristics (cont’d) 6V < VS < 18 V; – 40 °C < Tj < 150 °C Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Semiconductor Group 11 1998-02-01 TLE 4205 Forward Voltage of the Free-Wheeling Diodes versus Junction Temperature Saturation Voltage versus Junction Temperature Start Point of the SOA- Protection Circuit versus Junction Temperature Current Consumption versus Junction Temperature FUV IED00955 V TJ F 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 V 12080400-40 IF = 0.6 A VFL SV -40 0 40 80 120 V 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 Sat JT V IED00957 IQ V V Sat U Sat L = 600 mA = 13.5 V 0.8 = 13.5 V IED00956 I TJ 2.4 2.0 1.6 0.4 1.2 A 12080400-40 V S = 13.5 V IED00958 I TJ mA 12080400-40 V S S

Semiconductor Group 12 1998-02-01 Package Outlines 1018 Index Marking GPD05035 2.54 1.5 max 0.45+0.1 18x0.25 ~ 1.2~ 0.5 min ±0.33.5 4.2 max ±0.27.6 +1.27.6 +0.10.25 -0.26.4 0.4 max22.7-0.2 P-DIP-18-3 (Plastic Dual In-line Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mm

Semiconductor Group 13 1998-02-01 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mmSMD = Surface Mounted Device 11 0 1120 Index Marking 1) Does not include plastic or metal protrusions of 0.15 max per side 2) Does not include dambar protrusion of 0.05 max per side GPS05094 2.65 max 0.1 0.2-0.1 2.45-0.2 +0.150.35 1.27 0.2 24x -0.27.6 1) 0.35 x 45˚ 0.238˚ max +0.09 +0.8 ±0.310.3 0.4 12.8-0.2 P-DSO-20-6 (Plastic Dual Small Outline Package)