TLE4202B SIEMENS | Alldatasheet

Document overview

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Technical content

Features

  • Drives motors up to 2 A
  • Integrated free-wheeling diodes 2.5 A
  • Short-circuit proof to ground
  • Overtemperature protection
  • Low saturation voltages through bootstrap
  • Wide temperature range
  • Suitable for applications in automotive engineering

Semiconductor Group 2 1998-02-01 Figure 1 Pin Configuration (top view) AEP00612 V S3 GND 43215 6 7 12 I I I

Semiconductor Group 3 1998-02-01 Pin Definitions and Functions Pin No. Symbol Function 1I 1 Input 1 Non-inverting input 1, to be connected to pin 2 and pin 3 according to general rules 2I 3 Inverting input 3 Inverting inputs of the two comparators; internally connected to reference voltage across 50 kW (typ. 1.7 V) 3Q 1 Output Q1 Push-pull output B DC-short-circuit proof to ground. Integrated free-wheel diodes to ground and to supply voltage 4G N D Ground 5Q 2 Output Q2, see pin 3

6 VS Supply voltage

Has to be blocked to ground with a ceramic capacitor of at least 100 nF directly at the pins of the ICs 7I 2 Input 2 Non-inverting input 2; see pin 1

Semiconductor Group 4 1998-02-01 Figure 2 Block Diagram AEB00613 Power Limiter and Temperature Protection TLE 4202B

3 Output Q1

3 +1.7 V 50 kW VS VS Amp 1 80 dB 0 dB 0 dB 2Amp 80 dB I I I

Semiconductor Group 5 1998-02-01 1) The output voltages are kept within a permissible range by free-wheel diodes Outputs Q1 and Q2 short-circuit proof to ground RL: Resistance between output 1 and output 2 Absolute Maximum Ratings TC = – 40 to 130 °C Parameter Symbol Limit Values Unit min. max. Supply voltage VS –4 0 V Output current of sink transistors TC £ 85 °C Output current of source transistors internally limited Diode peak currents to + VS to ground IQ IQ IF + IF – 2.5 2.5 2.5 A A A Voltage at pins I1, I2, I3 Voltage at pins Q1, Q2 V1, 2, 7 V3, 5 – 0.3 VS V V Junction temperature Storage temperature T j Tstg – 55 150 125 Operating Range Supply voltage VS 3.5 17 V Case temperature during operation RL ‡ 6 W, VS = 7 … 16 V RL ‡ 9 W, VS = 16 V TC – 40 130 Voltage amplification (at negative feedback with external connection) VV 30 – dB Thermal resistance system - case Rth SC –4 K / W

Semiconductor Group 6 1998-02-01 Characteristics VS = 13 V; Tj = 25 °C Parameter Symbol Limit Values Unit Test Condition Test Circuitmin. typ. max. General Data Quiescent current Open-loop gain IS G VO mA dB S = 1 f = 500 Hz VS £ 7 V £ 16 V TC = – 40°C to 110 °C Input Characteristics Input current (pins I1, I2) Input current Input resistance Input reference voltage Input offset voltage II 1, 7 II 2 – II 2 RI 1, 7 VI 2 VI 0 1.4 – 20 230 1.7 300 mA mA mA M W V mV VI 1, 12 = 0 VI 2 = 0; VI 1, 7 = VS VI 2 £ VS; VI 1, 7 = 0 V f = 1 kHz I2 = 0; VI 1, 7 = 0 V

Semiconductor Group 7 1998-02-01 Output Characteristics Saturation voltages Source operation measured to VS Sink operation Short-circuit current Diode forward voltage to + VS to ground Slew rate falling edge Slew rate rising edge VSato VSato VSato VSatu VSatu ISC VF + VF – SR SR 0.9 1.2 1.5 0.25 0.5 1.25 0.9 1.6 2.1 0.4 0.75 1.3 1.6 1.3 1.2 V V V V V V A V V V/ms V/ms IQ = – 2 A; S1 = 1 IQ = 0.3 A; S1 = 2 IQ = 1 A; S1 = 2 IQ = 2 A; S1 = 2 VQ = 0 V IF = IQ = 1 A IF = IQ = 1 A Switching Times Rise time of VQ Fall time of VQ Switch-ON delay Switch-OFF delay tr tf tON tOFF 1.5 1.5 1.5 ms ms ms ms Quiescent current IS –1 5 3 0 m A S = 1 1 Characteristics (cont’d) VS = 13 V; Tj = 25 °C Parameter Symbol Limit Values Unit Test Condition Test Circuitmin. typ. max.

Semiconductor Group 8 1998-02-01 Characteristics VS £ 7 V to 17 V; TC = – 40 to 110 °C Parameter Symbol Limit Values Unit Test Condition Test Circuitmin. typ. max. Saturation Voltage Source operation measured to VS VSato VSato VSato 0.9 1.2 1.5 1.2 1.8 2.4 V V V IQ = – 0.3 A;S = 1 IQ = – 1 A; S = 1 IQ = – 2 A; S = 1 Sink operation VSatu VSatu VSatu 0.25 0.5 1.2 0.60 1.1 V V V IQ = 0.3 A; S1 = 2 IQ = 1 A; S1 = 2 IQ = 2 A; S1 = 2 Short-circuit current ISC ––3 . 5 V VQ = 0 V TC = 25 °C to 110 °C

Semiconductor Group 9 1998-02-01 Figure 3 Test Circuit 1 AES00614 W V Q1 100 nF100 mF VS+ Q2V 220 nF 220 nF 8 W 1000 mF Fm1000 V I TLE 4202B Amp 1 Amp 2 TDB 7805 510 W510 0 S V12 I12

Semiconductor Group 10 1998-02-01 Figure 4 Test Circuit 2 AES00615 100 nF100 mF VS+ TLE 4202 A

47 W /

VSato = VS -VQ3/5 VSatu = VQ3/5 ISC = IQ Amp 1 Amp 2 VQ3 VQ5 IQ =- ISC

Semiconductor Group 11 1998-02-01 Figure 5 Test Circuit 3 AES00616 TLE 4202B Amp 1 Amp 2

50 W 50 W

50 W50 W

4.95 kW Wk4.95 +11.3 V 100 nF 100 mF 100 Fn 100 mF 100 xV I 100 xV I -1.7 V

Semiconductor Group 13 1998-02-01 TLE 4202 B Saturation Voltage versus Output Current Saturation Voltage versus Temperature AED01340 0.0 0.0 V SAT 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 V I V Sato SatuV V S TC = 13 V = 25 ˚C L AED01341 0.0 -40 V SAT 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 40 80 120 160˚C V V Sato SatuV V S IL = 13 V = 1 A Tj

Semiconductor Group 14 1998-02-01 Package Outlines 10 +0.4 3.75+0.1 1.27 0.6 8.4±0.4 ±0.44.5 0.4+0.1 10.2 15.4±0.3 8.8-0.2 1.27+0.1 +0.1 2.8 4.6-0.2 2.6 8.6±0.3 ±0.3 ±0.4 19.5 max 1 x 45˚ at dam bar (max 1.8 from body) im Dichtstegbereich (max 1.8 vom Körper) -0.15 -0.15 M0.6 -0.210.2 1) 0.75 1) 0.75 GPT05108 P-TO220-7-1 (Plastic Transistor Single Outline) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mm