TLD6098-1EP

TLD6098-1EP INFINEON | Alldatasheet

Document overview

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Technical content

Features

• Wide input voltage (up to 58 V) and output voltage range (up to 70 V)
• Switching frequency range from 100 kHz to 500 kHz and synchronization at 2.2 MHz with an external clock source
• EMC optimized device
• Analog adjust input
• Overvoltage, Short to ground, overcurrent, open feedback and overtemperature diagnostic output
• PMOS gate driver for dimming and protection with enhanced dimming features
• LED current accuracy ±3.5% Product type Package Marking TLD6098-1EP PG-TSDSO-14 TLD6098-1 Potential applications
• LED driver for: front light module, rear light module, interior light
• Voltage regulator TLD6098-1EP IVCC IVCC CBO RSWCS M N RFB CIVCC RFAUL T RSETH RSETL RCOMP CCOMP1 RVFBH RVFBL LED 1 LED 2 LED 3 LED 4 LED 5 LED 6 LED 7 LED 8 GND SWO SWCS FBH FBL VFB COMP DC/PWMI SET FREQ/SYNC/SPREAD FPWM/FAUL T IVCC IN RFREQ IVCC RDCH RDCL VS B2G-1ch.vsdx M P PWMO CCOMP2 Figure 1 Application diagram Datasheet Please read the Important Notice and Warnings at the end of this document Rev.1.10 www.infineon.com 2021-09-30

Description of TLD6098-1EP TLD6098-1EP is a multi-topology DC-DC controller designed for LED applications with built-in protection features to implement a compact LED driver. The output current is regulated by means of peak current control loop. An internal slope compensation is used to avoid sub-harmonic oscillation at high duty cycle (e.g. higher than 50%). The current accuracy is better than 3.5% (with no analog adjustment applied) over the operating temperature range. A rail to rail current sense amplifier provides flexibility on the topology choice needed to supply LED string with more than 20 white LED (up to 70 V at output). The switching frequency can be adjusted from 100 kHz to 500 kHz using an external resistor. A synchronization with an external clock is also possible. The device incorporates even a spread spectrum modulator to achieve easy fulfilment of electromagnetic emission standards. TLD6098-1EP can drive an external PMOS for dimming and protection. For this purpose the device incorporates even a PWM generator controlled by an analog voltage on DC/PWMI pin. The generated PWM signal has the duty cycle adjustable from 0 to 100% with 10 bits of resolution and the frequency range programmable from 150 Hz to 750 Hz. On the same DC/PWMI pin the digital PWM signal can also be used. Product validation Qualified for automotive applications. Product validation according to AEC-Q100. LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Description of TLD6098-1EP Datasheet 2 Rev.1.10 2021-09-30

LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Table of contents Datasheet 3 Rev.1.10 2021-09-30

LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Table of contents Datasheet 4 Rev.1.10 2021-09-30

1 Block diagram

Slope comp. Internal supply On/Off logic + digital PWM dimming Leading edge blanking PWMO EN_INT/ PWM_INT Thermal protection Over voltage protection Open load and short to GND DC/DC switching regulator and logic Power switch gate driver Dimming switch gate driver Power on reset EN_INT/ PWM_INT Switch current error amplifier Reference current generation Embedded PWM dimming generator + fault report logic FPWM/FAUL T GND VM_INT VM_INT V IVCC V IVCC V FBH - V FBL V FBH - V FBL V FBH - V FBL V FBH V FBH Block diagram TLD6098-1.vsdx x1g m2 g m1 V VFB_REF Figure 2 Block diagram LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 5 Rev.1.10 2021-09-30

2 Pin configuration

PIN_POS_14.VSDX IN Exposed Pad Figure 3 Pin configuration PG-TSDSO-14 Table 1 Pin configuration PG-TSDSO-14 Name Pos. Description Direction PWMO 1 PMOS driver for dimming and protection Connect to gate of external MOSFET Pin must be left open if external MOSFET is not used Output SET 2 Analog adjustment Load current adjustment pin Pin must not be left open If analog adjustment is not used, connect to IVCC pin Input IVCC 3 Internal linear voltage regulator Used for internal biasing and gate drive Bypass with external capacitor Pin must not be left open Output COMP 4 Compensation Connect R and C network for stability Input FPWM/FAUL T 5 PWM frequency selector/Fault Connect external R to set PWM frequency Faults are reported by raising the voltage on this pin Input/ Output IN 6 Supply Supply for internal biasing Input DC/PWMI 7 PWM adjustment Set duty cycle of PWM engine or digital input for PWM dimming Input FREQ/SYNC/SPREAD 8 Frequency selector or synchronization Connect external resistor to GND to set switching frequency Apply square waveform for synchronization Input (table continues...) LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 6 Rev.1.10 2021-09-30

Table 1 (continued) Pin configuration PG-TSDSO-14 Name Pos. Description Direction GND 9 Ground – SWCS 10 Current sense/Power ground Detects peak current through power switch Power ground of gate driver of SWO Input SWO 11 Switch gate driver Connect to gate of external switching power n-channel MOSFET Output VFB 12 Overvoltage/Voltage loop reference Connect to resistive voltage divider to set the maximum voltage at output and the short to ground threshold Input FBL 13 Voltage feedback negative Inverting input (-) Input FBH 14 Voltage feedback positive Non inverting input (+) Input Exposed pad EP Exposed pad Used only for heat dissipation Connect to pin 9 (GND) LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 7 Rev.1.10 2021-09-30

3 General product characteristics

3.1 Absolute maximum ratings

Table 2 Absolute maximum ratings TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Not subject to production test, specified by design Parameter Symbol Values Unit Note or condition P- NumberMin. Typ. Max. Power supply input voltage VIN -0.3 – 60 V – PRQ-31 Voltage at pin SET VSET -0.3 – 5.5 V – PRQ-44 Voltage at pin DC/PWMI VDC/PWMI -0.3 – 60 V – PRQ-32 Voltage at pin FBH VFBH -1 – 75 V – PRQ-33 Voltage at pin FBL VFBL -1 – 75 V – PRQ-34 Differential input voltage VREF(MAX) -75 – 75 V VREF(MAX) = VFBH -VFBL Differential signal (not referred to ground) PRQ-35 Current at pin FBH, FBL IFBH, IFBL -7.5 – 7.5 mA VFBH - VFBL = 150 mV PRQ-36 Voltage at pin VFB VFB -0.3 – 5.5 V – PRQ-37 Voltage at pin SWCS VSWCS -0.3 – 0.3 V – PRQ-38 Voltage at pin SWO VSWO -0.3 – 5.5 V – PRQ-39 Voltage at pin FPWM/ FAUL T VFPWM/FAUL T -0.3 – 5.5 V – PRQ-40 Voltage at pin COMP VCOMP -0.3 – 5.5 V – PRQ-41 Voltage at pin FREQ/ SYNC/SPREAD VFREQ/SYNC -0.3 – 5.5 V – PRQ-42 Voltage at pin PWMO VPWMO -0.3 – 75 V – PRQ-43 PMOS output voltage VPMOS -1 – 10 V VPMOS = VFBH - VPWMO Differential signal (Not referred to ground) PRQ-579 Voltage at pin IVCC VIVCC -0.3 – 5.5 V – PRQ-45 Temperature Junction temperature TJ -40 – 150 °C – PRQ-46 Storage temperature Tstg -40 – 150 °C – PRQ-47 ESD susceptibility (table continues...) LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 8 Rev.1.10 2021-09-30

Table 2 (continued) Absolute maximum ratings TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Not subject to production test, specified by design Parameter Symbol Values Unit Note or condition P- NumberMin. Typ. Max. ESD susceptibility VESD_HBM -2 – 2 kV HBM: ESD susceptibility, Human Body Model "HBM" according to AEC Q100-002 PRQ-48 ESD susceptibility inner pins VESD_CDM -0.5 – 0.5 kV CDM: ESD susceptibility, Charged Device Model "CDM" according to AEC Q100-011 PRQ-49 ESD susceptibility corner pins VESD_CDM_CR -0.75 – 0.75 kV CDM: ESD susceptibility, Charged Device Model "CDM" according to AEC Q100-011 PRQ-50 Attention: 1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability 2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the datasheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for repetitive operation.

3.2 Functional range

TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P- NumberMin. Typ. Max. Extended power supply input voltage range VIN_EXT 4.5 – 58 V 1) Parameter deviations possible PRQ-51 Power supply input voltage operating range VIN_OP 8 – 36 V – PRQ-52 Operating voltage at pin FBH VFBH_OP 0 – 70 V – PRQ-581 (table continues...) LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 9 Rev.1.10 2021-09-30

Table 3 (continued) Functional range TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P- NumberMin. Typ. Max. Operating voltage at pin FBL VFBL_OP -0.3 – 70 V – PRQ-53 Switching frequency adjustment range fSWO 100 – 500 kHz – PRQ-85 Synchronization low frequency capture range fFREQ/SYNC/ SPREAD(LF) 100 – 500 kHz – PRQ-90 Synchronization high frequency capture range fFREQ/SYNC/ SPREAD(HF) 2 – 2.4 MHz – PRQ-132 PWMO frequency range fPWMO 150 – 750 Hz – PRQ-113 1) Not subject to production test, specified by design Attention: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table.

3.3 Thermal resistance

Table 4 Thermal resistance Not subject to production test, specified by design Parameter Symbol Values Unit Note or condition P- NumberMin. Typ. Max. Junction to case RthJC – 20.9 – K/W 1) PRQ-54 Junction to ambient RthJA – 57.2 – K/W 2) 2s2p PRQ-55 Junction to ambient RthJA – 73.2 – K/W 2) 1s0p + 600 mm2 PRQ-56 Junction to ambient RthJA – 85.5 – K/W 2) 1s0p + 300 mm2 PRQ-57 1) Specified RthJC value is simulated at natural convection on a cold plate setup (all pins and exposed pads are fixed to ambient temperature) TA = 25°C dissipates 1 W 2) Specified RthJA value is according JEDEC 2s2p (JESD 51-7) + (JESD 51-5) and JEDEC 1s0p (JESD 51-3) + heatsink area at natural convection on FR4 board. The device was simulated on 76.2 x 114.3 x 1.5 mm board. The 2s2p board has 2 outer copper layers (2 x 70 μm Cu) and 2 inner copper layer (2 x 35 μm Cu). A thermal via (diameter = 0.3 mm and 25 μm plating) array was applied under the exposed pad and connected the top layer and the inner layers to bottom layers of JEDEC PCB. TA = 25°C; IC dissipates 1 W Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For further information visit https://www.jedec.org LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 10 Rev.1.10 2021-09-30

4 Switching regulator

TLD6098-1EP implements a regulator suitable for Boost-to-ground, Boost-to-battery, Buck-to-battery, SEPIC, Flyback and Cuk configurations. The device has two distinct control loops:

• A current control loop (always enabled)
• A voltage control loop (optional) If the voltage loop is enabled the device regulates the output current as long as the feedback voltage on the VFB pin is below the VFB voltage mode ON threshold (VVFB_VM(ON)). The voltage control loop takes over and regulates the output voltage once the VFB reference voltage VVFB_REF is reached. The controller generates a PWM signal by sensing the inductor peak current and the output of the internal error amplifier. The control signal is applied to the internal gate driver connected to SWO pin to drive the external n-channel MOSFET

4.1 Soft start

The soft start routine has 2 functionalities:

• Limiting the input current and output overshoot
• Guaranteeing that the system output reaches the target value in a reasonable time even when being operated in PWM dimming with low duty cycles The first rising edge on DC/PWMI pin or the first cycle of the embedded PWM engine enables the soft start routine. It is then performed in the following cases:
• At start-up
• After an overvoltage on FBH pin
• After an overvoltage on VFB pin
• After an overtemperature fault
• After an undervoltage on IVCC pin The soft start is applied after a short to ground fault and retriggered every tFAUL T in case of continuous presence of the fault. The operation of the soft start is conditioned by the analog output adjustment. During the soft start the switching regulator adjusts the PWM signal to make the voltage between FBH and FBL evolve from 0 to VREF(100%)in tSS time. The evolution is performed in 15 steps if the analog adjustment is not applied, otherwise the intended steady-state is reached before the soft start ends. An ON time extension of the PWM dimming pulses is applied to ensure a reasonable power-up time when a low duty cycle dimming is applied. LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller

Datasheet 11 Rev.1.10 2021-09-30

Gate driver enabled Gate driver enabled V IN V DC/PWMI V FBH - V FBL SWO V REF V PWM_EXT t t t t V IN(ON) ON time extension PMOS ON PMOS ON PWMO t PMOS OFF PMOS OFF PMOS OFF soft start timing diagram.vsdx Figure 4 Soft start timing diagram (the linear waveform of VVFBH-VVFBL is an example of possible scenario) The ON time extension is triggered if :

• The applied PWM dimming signal (or the signal generated by the PWM engine) has an ON time shorter than tSS during the soft start and
• The voltage across FBH and FBL is lower than the reference voltage during PWM extension VPWM_EXT at the end of the ON time of the PWM signal The ON time extension lasts as long as the voltage across FBH and FBL reaches the VPWM_EXT . The VPWM_EXT is limited by the analog output adjustment down to a minimum reference voltage during ON time extension VPWM_MIN. For the first 3 steps of the VREF signal, the VPWM_EXT is higher than VREF. If the reference voltage across FBH and FBL adjusted by analog adjustment feature is lower than the VPWM_MIN the ON time extension ends after tSS. LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller

Datasheet 12 Rev.1.10 2021-09-30

t tSS VREF VPWM_EXT VPWM_MIN VPWM_EXT VREF VREF(100%) VREF evolution during soft-start.vsdx Figure 5 VREF and VPWM_EXT waveforms during the soft start routine without analog output adjustment VREF evolution during soft-start.vsdx tSS VREF VPWM_EXT VPWM_MIN VPWM_EXT VREF Adjusted VREF Soft start steady state t Figure 6 VREF and VPWM_EXT waveforms during the soft start routine with analog output adjustment If the ON time extension ends before tSS elapsed, the ON time extension is retriggered in the following PWM cycle, in case the voltage between FBH and FBL is once again lower than VPWM_EXT When the ON time extension ends, the remaining part of the soft start is allowed to evolve during the following ON time of the PWM dimming signal. In this case the actual duration of soft start could be longer than tSS. LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 13 Rev.1.10 2021-09-30

4.2 Electrical characteristics

Table 5 Electrical characteristics VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin; (unless otherwise specified) Parameter Symbol Values Unit Note or condition P- NumberMin. Typ. Max. Regulator VFB reference voltage (voltage loop) VVFB_REF 1.568 1.6 1.632 V – PRQ-142 Current loop reference voltage VREF(100%) 144.75 150 155.25 mV Differential signal (not referred to ground) VREF = VFBH - VFBL VSET = 5 V PRQ-66 Current loop reference voltage VREF(40%) 54.6 60 65.4 mV 1) Differential signal (not referred to ground) VSET = 940 mV PRQ-67 Current loop reference voltage VREF(0%) – – 10 mV Differential signal (not referred to ground) VSET = 100 mV PRQ-68 Transconductance error amplifier voltage loop gm1 – 0.95 – mS 1) PRQ-600 Transconductance error amplifier current loop gm2 – 1.6 – mS 1) PRQ-463 Switch current limit threshold VSWCS_TH 80 100 120 mV – PRQ-69 Maximum duty cycle in adjust. freq. mode DMAX 91 – – % RFREQ/SYNC/ SPREAD = 27 kΩ PRQ-70 Maximum duty cycle in low frequency sync mode DMAX(LF) 88 – – % fSW = 500 kHz PRQ-71 Maximum duty cycle in high frequency sync mode DMAX(HF) 80 – – % fSW = 2.2 MHz PRQ-289 Soft start time tSS 1.8 2 2.2 ms 1) PRQ-72 Reference voltage during PWM extension VPWM_EXT – 0.8*VRE F1,2 – V 1) VPWM_EXT > VPWM_MIN PRQ-588 Minimum reference voltage during PWM extension VPWM_MIN – 31.5 – mV 1) PRQ-589 (table continues...) LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 14 Rev.1.10 2021-09-30

Table 5 (continued) Electrical characteristics VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin; (unless otherwise specified) Parameter Symbol Values Unit Note or condition P- NumberMin. Typ. Max. Input current at pin FBH IFBH – 550 800 μA VFBH - VFBL = 0.15 V VFBH = 60 V PRQ-73 Input current at pin FBL IFBL – 50 70 μA VFBH - VFBL = 0.15 V VFBH = 60 V PRQ-74 Input current at pin FBH IFBH – 50 70 μA VFBH - VFBL = 0.15 V VFBL = 0 V Current flows out of pin PRQ-75 Input current at pin FBL IFBL – 50 70 μA VFBH - VFBL = 0.15 V VFBL = 0 V Current flows out of pin PRQ-76 Threshold voltage high side sensing VFBH_HSS – 2.55 2.8 V 1) VFBH increasing PRQ-267 Threshold voltage low side sensing VFBH_LSS 2.1 2.3 – V 1) VFBH decreasing PRQ-268 Power supply undervoltage shutdown VIN(OFF) 2.5 – 4.5 V VIN decreasing PRQ-77 Power supply minimum startup voltage VIN(ON) – – 5.5 V VIN increasing PRQ-78 Power supply current consumption IIN – 5 8 mA VDC/PWMI = 0 V VSET = VIVCC RFREQ/SYNC/SPREAD = 33 kΩ RFPWM/FAUL T = 57 kΩ no faults detected PRQ-426 Gate driver for external switch Gate driver peak output current ISWO 1 – – A 1) VSWO increasing 1 V to 4 V Current flows out of pin PRQ-79 (table continues...) LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 15 Rev.1.10 2021-09-30

Table 5 (continued) Electrical characteristics VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin; (unless otherwise specified) Parameter Symbol Values Unit Note or condition P- NumberMin. Typ. Max. Gate driver peak output current ISWO 1 – – A 1) VSWO decreasing 4 V to 1 V PRQ-80 Gate driver output rise time tR_SWO – – 20 ns 1) CL_SWO = 3.3 nF VSWO increasing 1 V to 4 V PRQ-81 Gate driver output fall time tF_SWO – – 20 ns 1) CL_SWO = 3.3 nF VSWO decreasing 4 V to 1 V PRQ-82 Gate driver high side resistance RSWO_HS – 1 3 Ω 1) ISWO = -10 mA PRQ-83 Gate driver low side resistance RSWO_LS – 1 3 Ω 1) ISWO = 10 mA PRQ-196 1) Not subject to production test, specified by design LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 16 Rev.1.10 2021-09-30

5 Linear regulator

The device incorporates a linear regulator to generate a 5 V output used to supply the internal gate drivers and, through IVCC pin, other auxiliary devices on the PCB (for example a microcontroller and resistor dividers). The maximum output current of the linear regulator is limited to the IVCC output current limit IIVCC. If the load on IVCC (gate drivers plus connected devices on PCB) draws more than IIVCC the linear regulator output voltage decreases. The linear regulator starts to deliver current to IVCC pin when the input voltage VIN goes above the power supply minimum start up voltage VIN (ON) for a time longer than IVCC start time tST A low ESR capacitor has to be connected from IVCC to ground (CIVCC in the figure) to stabilize the output voltage of the linear regulator. The ESR of the capacitor CIVCC has to be lower than IVCC buffer capacitor ESR RIVCC(ESR). TLD6098-1EP Clock generator IN IVCC SWO FREQ/SYNC DC/PWMI C IVCC Switching regulator V S Linear regulator on TLD6098-1EP .vsdx Voltage regulator Figure 7 Block diagram of the linear regulator

5.1 Undervoltage protection for the external switching MOSFET

During the ON time of the switching PWM signal, the gate driver has to bias the switching NMOS in deep ohmic region to avoid the overheating of the MOSFET itself during the conduction time. This is ensured by choosing a logic level MOSFET with a maximum threshold voltage lower than IVCC undervoltage switch-off threshold VIVCC_TH_D. TLD6098-1EP has an integrated undervoltage reset threshold circuit to disable the gate driver if the VIVCC drops below the VIVCC_TH_D. The gate driver is then enabled again when the VIVCC goes above the IVCC undervoltage switch-on threshold VIVCC_TH_I. LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 17 Rev.1.10 2021-09-30

Gate driver disabled Gate driver enabled Gate driver disabled Gate driver enbled Gate driver disabled tST VDC/PWMI(ON) VIVCC_TH_D VIVCC_TH_I VIN(OFF) VIN(ON) VFPWM/FAUL T tSS t t t t t Timing diagram of linear regulator on TLD6098-1EP .vsdx tSS Soft start routine Figure 8 Thresholds and timing diagram related to the linear regulator

5.2 Electrical characteristics

Table 6 Electrical characteristics VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin; (unless otherwise specified) Parameter Symbol Values Unit Note or condition P- NumberMin. Typ. Max. IVCC output voltage VIVCC 4.85 5 5.15 V 8 V ≤ VIN ≤ 36 V; 0.1 mA ≤ IIVCC ≤ 40 mA PRQ-58 IVCC output current limit IIVCC 51 – 100 mA 8 V < VIN < 13.5 V; VIVCC < 4.5 V; Current flows out of pin PRQ-59 IVCC dropout voltage VIVCC_DV – – 0.5 V VIN = 5 V; IIVCC < 20 mA PRQ-60 IVCC start time tST – – 300 μs 1) VIN slew rate higher than 1 V/10 μs PRQ-285 IVCC buffer capacitor CIVCC 1 4.7 10 μF 1) If embedded PWM engine is used, 4.7 μF has to be chosen as a minimum PRQ-61 (table continues...) LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 18 Rev.1.10 2021-09-30

Table 6 (continued) Electrical characteristics VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin; (unless otherwise specified) Parameter Symbol Values Unit Note or condition P- NumberMin. Typ. Max. IVCC buffer capacitor ESR RIVCC(ESR) – – 0.2 Ω 1) Maximum value given for regulator stability PRQ-62 IVCC undervoltage switch-off threshold VIVCC_TH_D 3.6 – 4.0 V VIVCC decreasing PRQ-64 IVCC undervoltage switch-on threshold VIVCC_TH_I – – 4.5 V VIVCC increasing PRQ-65 1) Not subject to production test, specified by design Attention: Select external switching MOSFET with worst case threshold voltage VGS(th) lower than minimum VIVCC_TH_D LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 19 Rev.1.10 2021-09-30

6 Switching frequency setup and synchronization

The DC-DC switching frequency is adjusted by a resistor placed from FREQ/SYNC/SPREAD pin to ground or by providing to this pin a digital clock. The device incorporates also a spread spectrum modulator to reduce the design effort to fulfill the EMI compliance. By using a resistor, the switching frequency of the regulator is adjusted in the switching frequency adjustment range fSWO. If an external clock is provided, the device accepts a digital clock in these two working windows:

• Synchronization low frequency capture range fFREQ/SYNC/SPREAD(LF) (low frequency synchronization mode)
• Synchronization high frequency capture range fFREQ/SYNC/SPREAD(HF) (high frequency synchronization mode) Outside these ranges, the device does not recognize a valid clock and then the behavior of the regulator can be out of specification. TLD6098-1EP Clock generator Clock frequency detector FREQ/SYNC/SPREAD Multiplexer DC/DC switching regulator Gate driver SWO Spread spectrum modulator Oscillator and Synch block-TLD6098-1EP .vsdx Figure 9 Diagram of switching frequency adjustment and synchronization blocks

6.1 Switching frequency setup with external resistor

The resistor placed on FREQ/SYNC/SPREAD pin adjusts the frequency of the DC-DC and enables or disables the spread spectrum modulator. The relationship between the biasing resistor and switching frequency with spread spectrum activated is fSW = 1 1 . 11 · 10−9 · RFREQ/SYNC /SPREAD (1) The relationship between the biasing resistor and the switching frequency with the spread spectrum not active is fSW = 1 1 . 11 · 10−10 · RFREQ/SYNC /SPREAD (2) LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 20 Rev.1.10 2021-09-30

Figure 10 Switching frequency versus RFREQ/SYNC/SPREAD

6.1.1 Electrical characteristics

Table 7 Electrical characteristics VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin; (unless otherwise specified) Parameter Symbol Values Unit Note or condition P- NumberMin. Typ. Max. Switching frequency fSWO_SSM(OFF) 288 333 378 kHz RFREQ/SYNC/SPREAD = 27 kΩ PRQ-277 FREQ/SYNC/SPREAD output current IFREQ/SYNC/ SPREAD – – 3 mA VFREQ/SYNC/SPREAD = 0 V Current flowing out of pin PRQ-86 FREQ/SYNC/SPREAD output voltage VFREQ/SYNC/ SPREAD_SSM(OFF) 0.72 0.8 0.88 V RFREQ/SYNC/SPREAD = 27 kΩ PRQ-87

6.1.2 Spread Spectrum

The spread spectrum modulation technique significantly reduces the electromagnetic harmonics emission at the lower frequency range of the spectrum (f < 30 MHz). This technique is enabled by changing the switching frequency over the time. The final result is the movement over a broad band of the energy associated with the peaks of the electromagnetic harmonics emission. The switching frequency is modulated with a triangular shape digitalized in 7 steps equally distributed over the entire frequency span (2 times the frequency deviation fDEV). LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 21 Rev.1.10 2021-09-30

t fSW_SSM(ON) fDEV Spread spectrum modulator characteristic.vsdx Figure 11 Spread spectrum modulator characteristic

6.1.2.1 Electrical characteristics

Table 8 Electrical characteristics VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin; (unless otherwise specified) Parameter Symbol Values Unit Note or condition P- NumberMin. Typ. Max. Average switching frequency fSWO_SSM(ON) 288 333 378 kHz 1) RFREQ/SYNC/SPREAD = 2.7 kΩ PRQ-84 Modulation frequency fFM 13.5 15 16.5 kHz 1) 1.8 kΩ ≤ RFREQ/SYNC/ SPREAD ≤ 9 kΩ PRQ-88 Frequency deviation fDEV 0.09*fS WO 0.15*fS WO – kHz 1) 1.8 kΩ ≤ RFREQ/SYNC/ SPREAD ≤ 9 kΩ PRQ-89 FREQ/SYNC/SPREAD output voltage VFREQ/SYNC/ SPREAD_SSM(ON) 0.72 0.8 0.88 V RFREQ/SYNC/SPREAD = 2.7 kΩ PRQ-385 1) Not subject to production test, specified by design LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 22 Rev.1.10 2021-09-30

6.2 Synchronization with external clock (low frequency mode)

The switching frequency is synchronized with an external clock source applied on FREQ/SYNC/SPREAD pin if the frequency is in the synchronization low frequency capture range fFREQ/SYNC/SPREAD(LF) and the duty cycle is in the synchronization input duty cycle range DCFREQ/SYNC/SPREAD. The device detects the external clock source if the voltage on FREQ/SYNC/SPREAD exceeds the two thresholds:

• The synchronization input high voltage VFREQ/SYNC/SPREAD(H) during the positive pulse,
• The synchronization input low voltage VFREQ/SYNC/SPREAD(L) during the negative pulse. V FREQ/SYNC/SPREAD t VFREQ/SYNC/SPREAD(H) VFREQ/SYNC/SPREAD(L) tFREQ/SYNC/SPREAD = 1 / f FREQ/SYNC/SPREAD tFREQ/SYNC/SPREAD(H)DCSWO = tFREQ/SYNC/SPREAD(ON) tFREQ/SYNC/SPREAD Timing diagram in synchronization mode.vsdx Figure 12 Timing diagram when synchronization mode is enabled

6.2.1 Electrical characteristics

Table 9 Electrical characteristics VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin; (unless otherwise specified) Parameter Symbol Values Unit Note or condition P- NumberMin. Typ. Max. Synchronization input high voltage VFREQ/SYNC/ SPREAD(H) 3.0 – – V – PRQ-91 Synchronization input low voltage VFREQ/SYNC/ SPREAD(L) – – 0.8 V – PRQ-92 Synchronization input duty cycle range DCFREQ/SYNC/ SPREAD 40 – 60 % 1) PRQ-94 1) Not subject to production test, specified by design

6.3 Synchronization with external clock (high frequency range)

High switching frequency enables a system cost down due to reduced value for the reactive components. The high frequency synchronization is enabled if the input clock is in the synchronization high frequency capture range fFREQ/SYNC/SPREAD(HF). Voltage threshold levels on FREQ/SYNC/SPREAD pin are the same as in the low frequency synchronization mode. LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 23 Rev.1.10 2021-09-30

7 Analog output adjustment

The device adjusts the reference voltage VREF across FBH and FBL pins (thus adjusting the output current) by monitoring the analog voltage on SET pin (VSET). The SWO NMOS gate driver is disabled if the voltage applied on the SET pin is lower than SET input voltage no switching activity VSET(NOSW). The SET pin has to be connected to a voltage higher than VSET(100%) (e.g. connecting SET pin to IVCC pin) to exclude the output current adjustment feature. V SET V FBH- V FBL V REF(100%) V REF(40%) V REF(0%) V SET(100%)V SET(40%)V SET(0%)V SET(NOSW) Gate driver disabled V REF(100%)V REF(0%) Analog dimming with TLD6098-1EP .vsdx Figure 13 Relationship between VSET and reference voltage VREF The SET pin can also be wired to an external thermistor (usually mounted on the LED module) to perform a thermal protection.

7.1 Electrical characteristics

Table 10 Electrical characteristics VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin; (unless otherwise specified) Parameter Symbol Values Unit Note or condition P- NumberMin. Typ. Max. SET input voltage 100% VSET(100%) – 2.2 – V 1) PRQ-95 SET input voltage 40% VSET(40%) – 940 – mV 1) PRQ-429 SET input voltage 0% VSET(0%) – 100 – mV 1) PRQ-428 SET input voltage no switching activity VSET(NOSW) – – 50 mV – PRQ-368 1) Not subject to production test, specified by design LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 24 Rev.1.10 2021-09-30

8 Dimming functions

The TLD6098-1EP offers a dimming input for pulse width modulating (PWM) the output current. This modulation is beneficial to reduce the average current at output (and then the brightness of the LEDs), without showing color shift on the light produced by the LEDs. The output current modulation is operated by the device as function of the voltage on DC/PWMI pin

• A digital clock signal imposes the duty cycle and the frequency
• An analog voltage is translated to a duty cycle and the frequency is adjusted with a resistor on FPWM/ FAUL T pin. Different voltage levels on DC/PWMI pin activates different functions, as described below:
• If the voltage is higher than DC/PWMI input voltage high threshold VDC/PWMI(ON) the dimming duty cycle is set to 100%
• If the voltage is in between the two digital thresholds ( VDC/PWMI(100%) and VDC/PWMI(0%)), the embedded PWM dimming function is activated
• If the voltage is lower than DC/PWMI input voltage low threshold VDC/PWMI(OFF) the dimming duty cycle is 0% When a dimming function is activated, the PWM signal controls the switching regulator gate driver and the PMOS gate driver To allow fast transitions of the dimming PMOS even at low output voltage, the positive power supply of the PWMO gate driver is connected to FBH pin if its voltage VFBH is higher than VIVCC, otherwise the gate driver is supplied by the IVCC pin. During the ON state of the PWM dimming, the PMOS is biased with a PWMO output voltage ON state VPWMO,ON (minimum VPWMO,ON cannot go below 0 V).

8.1 Electrical characteristics

Table 11 Electrical characteristics VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin; (unless otherwise specified) Parameter Symbol Values Unit Note or condition P- NumberMin. Typ. Max. PWMO peak output current IPWMO 2 5 – mA 1) VFBH = 14V VPWMO increasing VPWMO(ON) + 0.5 V to VPWMO(ON) + 3.5 V CL,PWMO = 3.3 nF current flows out of pin PRQ-102 PWMO peak output current IPWMO 2 5 – mA 1) VFBH = 14V VPWMO decreasing VPWMO(OFF) - 0.5 V to VPWMO(OFF) - 3.5 V CL,PWMO = 3.3 nF PRQ-103 (table continues...) LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 25 Rev.1.10 2021-09-30

Table 11 (continued) Electrical characteristics VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin; (unless otherwise specified) Parameter Symbol Values Unit Note or condition P- NumberMin. Typ. Max. PWMO gate driver output rise time tR_PWMO – 2 6 μs 1) VFBH = 14V VPWMO increasing VPWMO(ON) + 0.5 V to VPWMO(ON) + 3.5 V CL,PWMO = 3.3 nF PRQ-104 PWMO gate driver output fall time tF_PWMO – 2 6 μs 1) VFBH = 14 V VPWMO decreasing VPWMO(OFF) - 0.5 V to VPWMO(OFF) - 3.5 V CPWMO = 3.3 nF PRQ-105 PWMO output voltage ON state VPWMO(ON) – VFBH - 6.5 VFBH - 5 V 1) VFBH > 7.5 V PRQ-106 PWMO output voltage OFF state VPWMO(OFF) – VFBH – V 1) VFBH = 14 V PRQ-107 1) Not subject to production test, specified by design

8.2 Digital PWM dimming

The TLD6098-1EP has a dedicated input pin to modulate the average current in a LED string with a digital pattern. The device recognizes a digital PWM dimming signal on DC/PWMI pin if:

• The minimum voltage on DC/PWMI is lower than VDC/PWMI(OFF)
• The maximum voltage on DC/PWMI is higher than VDC/PWMI(ON)
• The maximum frequency on DC/PWMI is less than 1 kHz
• No faults are detected If a valid pattern is recognized and the VDC/PWMI is higher than VDC/PWMI(ON) the NMOS gate driver is enabled and the voltage of PWMO pin is VPWMO(ON); else the NMOS gate driver is disabled and the voltage of PWMO pin is VPWMO(OFF) LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller

Datasheet 26 Rev.1.10 2021-09-30

8.2.1 Electrical characteristics

Table 12 Electrical Characteristics VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin; (unless otherwise specified) Parameter Symbol Values Unit Note or condition P- NumberMin. Typ. Max. DC/PWMI input voltage high threshold VDC/PWMI(ON) 4.0 – – V – PRQ-97 DC/PWMI input voltage low threshold VDC/PWMI(OFF) – – 0.8 V – PRQ-98 DC/PWMI input current IDC/PWMI – – 200 μA VDC/PWMI = VIN PRQ-99 DC/PWMI input current IDC/PWMI – – 1 μA VDC/PWMI = 0.8 V PRQ-100 DC/PWMI minimum ON time tDC/PWMI(ON) 6 – – μs – PRQ-101

8.3 Embedded PWM engine

The embedded PWM engine helps to reduce the color shift when a LED string is dimmed down without using timer or microcontroller. It generates a pulse width modulation (PWM) adjustable in frequency and duty cycle. A possible application is the daytime running light dimmed down to position light without using microcontroller or timer. The embedded PWM dimming function is enabled if the voltage on DC/PWMI pin is in between DC/PWMI input voltage 0% dimming VDC/PWM_0% and DC/PWMI input voltage 100% dimming VDC/PWM_100%. This voltage is translated in the duty cycle of the PWM signal with DC/PWMI duty cycle resolution nDC/PWMI. DC PWM V DC/PWMI 100% V DC/PWMI(100%)V DC/PWMI(0%) Digital dimming Digital dimming Embedded PWM engine working window V DC/PWMI(ON)V DC/PWMI(OFF) Duty cycle vs PWMI voltage.vsdx Figure 14 Relationship between VDC/PWMI and dimming duty cycle If the embedded PWM dimming function is enabled, the behavior of PWMO pin is the following:

• The PWMO voltage switches between PWMO output voltage ON state VPWMO(ON) and PWMO output voltage OFF state VPWMO(OFF) LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller

Datasheet 27 Rev.1.10 2021-09-30

• The PWMO switching frequency depends on the resistor value placed on FPWM/FAUL T pin
• The PWM duty cycle is linearly adjusted with the voltage on DC/PWMI pin Any faults disables the embedded PWM engine and forces the voltage on PWMO pin to VPWMO(OFF). The resistor connected on FPWM/FAUL T is used to:
• Adjust the frequency of the embedded PWM engine
• Enable two different reactions on FPWM/FAUL T pin during the fault report
• Enable or disable the voltage control loop If the resistor on FPWM/FAUL T pin is in FPWM/FAUL T high resistor range RFPWM/FAUL T(H) the device has the following behavior:
• The frequency of PWM engine is adjusted in fPWMO range
• In case a fault is detected, it is reported on FPWM/FAUL T pin with proper duty cycle
• The voltage loop is disabled and the overvoltage is detected with a comparator (detailed information are described in Protection and fault management chapter) While if resistor on FPWM/FAUL T pin is in FPWM/FAUL T low resistor range RFPWM/FAUL T(L)
• The frequency of PWM engine is adjusted in fPWMO range
• The faults are reported on FPWM/FAUL T1,2 pin without a specific indication
• Voltage regulation loop is enabled and concurrent to current regulation loop The frequency of embedded PWM generator can be calculated by: fPWMO _HR = 1 7 . 4 · 10−8 · RFPWM /FAULT (3) for resistor RFPWM/FAUL T(H) range fPWMO _LR = 1 7 . 4 · 10−7 · RFPWM /FAULT (4) for resistor RFPWM/FAUL T(L) range. LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller

Datasheet 28 Rev.1.10 2021-09-30

Figure 15 Relationship between RFPWM/FAUL T and the frequency of PWMO The table below summarizes the differences between two resistor sets on FPWM/FAUL T pin Table 13 Resistor differences on fault pin RFPWM/FAUL T(H) RFPWM/FAUL T(L) Fault report Each fault reported with a dedicated duty cycle on FPWM/FAUL T The faults are reported by raising the voltage on FPWM/FAUL T pin until the faulty status is removed Voltage loop Disabled Enabled LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 29 Rev.1.10 2021-09-30

8.3.1 Electrical characteristics

Table 14 Electrical characteristics VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin; (unless otherwise specified) Parameter Symbol Values Unit Note or condition P- NumberMin. Typ. Max. DC/PWMI input voltage 0% dimming VDC/PWMI(0%) 0.965 1 1.035 V VIVCC = 5 V PRQ-110 DC/PWMI input voltage 100% dimming VDC/PWMI(100%) 3.53 3.6 3.67 V VIVCC = 5 V PRQ-111 DC/PWMI equivalent pull down resistor RDC/PWMI 1.5 2.5 3.5 MΩ VDC/PWMI = 4 V PRQ-433 PWMO duty cycle DCPWMO 8 10 12 % VPWMI = 1.26 V VIVCC = 5 V PRQ-112 FPWM/FAUL T reference voltage VFPWM/ FAUL T(REF) 0.72 0.8 0.88 V – PRQ-114 FPWM/FAUL T output current IFPWM/FAUL T – – 3 mA VFPWM/FAUL T = 0 V PRQ-115 PWMO dimming frequency fPWMO 315 345 375 Hz RFPWM/FAUL T = 3.92 kΩ PRQ-116 PWMO dimming frequency fPWMO 315 345 375 Hz RFPWM/FAUL T = 39.2 kΩ PRQ-370 DC/PWMI duty cycle resolution nDC/PWMI – 10 – bit 1) PRQ-313 FPWM/FAUL T high range resistor RFPWM/FAUL T(H) 18 – 90 kΩ 1) PRQ-590 FPWM/FAUL T low range resistor RFPWM/FAUL T(L) 1.8 – 9 kΩ 1) PRQ-591 1) Not subject to production test, specified by design LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 30 Rev.1.10 2021-09-30

9 Protections and fault management

The fault conditions are identified by checking the status of PWMO, IVCC and FPWM/FAUL T pins. The device disables the gate driver and reports fault on FPWM/FAUL T pin if the following faults are detected:

• Short to ground
• Overvoltage on VFB pin
• Overtemperature
• Overvoltage on FBH pin
• Overcurrent The faults are reported by raising the voltage on FPWM/FAUL T pin to VFPWM/FAUL T(FAUL T). The output waveform of the fault reporting depends on the resistor connected to FPWM/FAUL T pin. The status of FPWM/FAUL T pin can be monitored by a microcontroller. In this case a series resistor (10 kΩ minimum) has to be used between FPWM/FAUL T and the input pin of the microcontroller. The PWMO gate driver biases the PMOS in OFF state to disconnect the load from the DC-DC output during:
• Overvoltage on VFB pin,
• Overvoltage on FBH pin
• Overtemperature
• Overcurrent During a short to ground, the PMOS is biased in OFF state during the tS2G and it is biased in ON state every tFAUL T for a (tSS) to detect if the fault has been removed.

9.1 Electrical characteristics

Table 15 Electrical characteristics VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin; (unless otherwise specified) Parameter Symbol Values Unit Note or condition P- NumberMin. Typ. Max. FPWM/FAUL T output voltage with fault VFPWM/ FAUL T(FAUL T) 4 – – V 1) PRQ-117 Fault period tFAUL T 9 10 11 ms 1) PRQ-133 1) Not subject to production test, specify by design

9.2 Short to ground

The short to ground detection feature protects the LED driver from an excess of current during a short circuit. This fault is detected if the voltage of VFB pin is lower than short to ground voltage threshold VFB_S2G for a time longer than short to ground reaction time tS2G_RT. After a fault time with short to ground tS2G a soft start routine is triggered. The fault is released if the voltage on VFB pin is higher than (VFB_S2G+VFB_S2G_HYST) at the end of the soft start. During soft-start routine, the short to ground detection is disabled and the voltage of FPWM/FAUL T pin is kept at VFPWM/FAUL T(REF). The reaction to short to ground is: 1. The voltage on FPWM/FAUL T pin is raised to VFPWM/FAUL T(FAUL T) for tS2G time 2. After a tS2G time the soft-start routine is performed 3. At the end of soft-start routine, the check on the voltage VVFB is redone LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 31 Rev.1.10 2021-09-30

If the fault is still present, the procedure is repeated, otherwise the driver restarts. This routine is valid whatever resistor used on FPWM/FAUL T pin. V VFB_S2G V VFB_S2G_HYS Gate driver enabled Gate driver disabled ON Gate driver disabled Gate driver disabled Gate driver enabled t fault t S2G t SS ON t fault t fault t SS V VFB V PWM/FAUL T V SWO V FPWM/FAUL T(FAUL T) V FPWM/FAUL T(REF) t SS t t t S2G - TLD6098-1EP .vsdx Figure 16 Timing diagram during short to ground detection A short to ground event simultaneous with an overcurrent event is detected once even the voltage on DC/PWMI pin is lower than VDC/PWMI(OFF). In all the other cases, the short to ground is not detected when the voltage on DC/PWMI pin is lower than VDC/PWMI(OFF).

9.2.1 Electrical characteristics

Table 16 Electrical characteristics VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin; (unless otherwise specified) Parameter Symbol Values Unit Note or condition P- NumberMin. Typ. Max. Fault time with short to ground tS2G 7.2 8 8.8 ms 1) PRQ-134 Short to ground reaction time tS2G_RT 4 – 20 μs – PRQ-121 Short to ground voltage threshold VFB_S2G 93 100 107 mV Voltage decreasing PRQ-119 Short to ground voltage hysteresis VFB_S2G_HYST – 5 10 mV 1) PRQ-120 1) Not subject to production test, specified by design

9.3 Output overvoltage and voltage regulation

Based on the resistor used on FPWM/FAUL T pin the device implements an overvoltage detection with a comparator or enabling a voltage regulation by using the internal voltage loop. LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 32 Rev.1.10 2021-09-30

If the resistor connected to FPWM/FAUL T pin is in the RFPWM/FAUL T(H) range, the overvoltage comparator is enabled with VFB overvoltage threshold VVFB_OV. The fault is detected when the VFB voltage is above this threshold. The device reacts by:

• raising the VFPWM/FAUL T to VFPWM/FAUL T(FAUL T) for a fault time with overvoltage tOVFB
• disabling the NMOS gate driver for tFAUL T after tFAUL T the voltage of VFB is rechecked and if it is still higher than (VVFB_OV -VVFB_OV,HYS) the routine is repeated, else the device restarts with a soft-start routine. Gate driver enabled Gate driver disabled Gate driver enabled Gate driver disabled Gate driver enabled tfault tOVFB tfault tfault VVFB_OV VVFB_OV_HIS V VFB V FPWM/FAUL T V SWO t t t OVFB-HR TLD6098-1EP .vsdx VFPWM/FAUL T(FAUL T) VFPWM/FAUL T(REF) Figure 17 Timing diagram during overvoltage detection The driver works as a voltage regulator with the voltage loop enabled if the resistor connected to FPWM/FAUL T pin is in the RFPWM/FAUL T(L) range. The voltage loop is taking over the regulation when the voltage on VFB pin goes higher than VFB_VM(ON). At this time the voltage on FPWM/FAUL T pin is raised to VFPWM/FAUL T(FAUL T). On the other side, the device reports the voltage loop is ineffective when the voltage on VFB pin goes below VFB_VM(OFF) by lowering the voltage on FPWM/FAUL T pin to VFPWM/FAUL T(REF). The fault is detected even the voltage on DC/PWMI pin is lower than VDC/PWMI(OFF). LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller

Datasheet 33 Rev.1.10 2021-09-30

VVFB_VM(ON) V VFB V FPWM/FAUL T VVFB_VM(OFF) VVFB_REF t t t V SWO VFPWM/FAUL T(FAUL T) VFPWM/FAUL T(REF) OVFB-LR-TLD6098-1EP .vsdx Figure 18 Timing diagram in voltage regulation

9.3.1 Electrical characteristics

Table 17 Electrical characteristics VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin; (unless otherwise specified) Parameter Symbol Values Unit Note or condition P- NumberMin. Typ. Max. VFB overvoltage threshold VVFB_OV 1.568 1.6 1.632 V Voltage increasing PRQ-118 VFB overvoltage hysteresis VVFB_OV_HYS 180 200 220 mV 1) PRQ-323 VFB input current IVFB -1 -0.1 1 μA VFB = 1.6 V PRQ-122 VFB Voltage mode ON threshold VVFB_VM(ON) 1.45 1.5 1.55 V Voltage increasing PRQ-376 VFB voltage mode OFF threshold VVFB_VM(OFF) 1.3 1.35 1.4 V Voltage decreasing PRQ-377 Fault time with overvoltage tOVFB 3.6 4 4.4 ms 1) PRQ-135 1) Not subject to production test, specified by design

9.4 Overvoltage on FBH pin

The driver has a protection feature to prevent an excess voltage on FBH pin. The report of this fault depends on the resistor connected to FPWM/FAUL T pin. LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 34 Rev.1.10 2021-09-30

The device recognizes an overvoltage on FBH pin fault if the VFBH is higher than FBH overvoltage high threshold VFBH(H) and the fault is released when it is below the FBH overvoltage low threshold VFBH(L). With a resistor on FPWM/FAUL T pin in RFPWM/FAUL T(H) range the device reacts by:

• Disabling the NMOS gate driver
• Raising the voltage of FPWM/FAUL T pin to VFPWM/FAUL T(FAUL T) for tFBH time
• After tFAUL T period, the device checks if VFBH is still higher than VFBH(L) Gate driver enabled V VFBH(H) V VFBH V FPWM/FAUL T V VFBH(L) Gate driver enabledGate driver disabled t fault t fault t fault t FBH V SWO OV_FBH_HRES_TLD6098-1EP .vsdx t t t V FPWM/FAUL T(FAUL T) V FPWM/FAUL T(REF) Figure 19 Timing diagram during overvoltage on FBH detection with RFPWM/FAUL T(H) used on FPWM/FAUL T pin With a resistor on FPWM/FAUL T pin in RFPWM/FAUL T(L) range the device reacts to the fault by:
• Disabling the NMOS gate driver
• Raising the voltage of FPWM/FAUL T pin to VFPWM/FAUL T(FAUL T)
• After tFAUL T period, the device checks if the voltage on FBH pin is still higher than VFBH(L) LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller

Datasheet 35 Rev.1.10 2021-09-30

V VFBH(H) V VFBH V FPWM/FAUL T V FPWM/FAUL T(FAUL T) V VFBH(L) Gate driver enabledGate driver disabled t FAUL T t FAUL T t FAUL T V FPWM/FAUL T(REF) V SWO OV_FBH_LRES_TLD6098-1EP .vsdx t t t Figure 20 Timing diagram during overvoltage on FBH detection with RFPWM/FAUL T(L) used on FPWM/FAUL T pin When the fault disappears the device restarts with soft-start routine and lowers the voltage of FPWM/FAUL T pin to VFPWM/FAUL T(REF). If the fault appears during the soft-start routine, it interrupts the soft-start for a tFAUL T time and then the routine restarts. The fault is detected even when the voltage on DC/PWMI pin is lower than VDC/PWMI(OFF).

9.4.1 Electrical characteristics

Table 18 Electrical characteristics VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin; (unless otherwise specified) Parameter Symbol Values Unit Note or condition P- NumberMin. Typ. Max. FBH overvoltage upper threshold VFBH(H) 70 – 75 V VFBH increasing PRQ-327 FBH overvoltage lower threshold VFBH(L) 65 – – V VFBH decreasing PRQ-328 Fault time FBH tFBH 5.4 6 6.6 ms 1) PRQ-329 1) Not subject to production test, specified by design LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 36 Rev.1.10 2021-09-30

9.5 Output overcurrent

An output overcurrent event could damage the load if the current exceed the load specification. The output overcurrent detection increases the system reliability by reducing the load average current. The output overcurrent is detected when voltage across FBH and FBL is higher than overcurrent detection threshold VOC_200% . The device reacts in overcurrent detection time tOC_200% by rising the voltage of PWMO pin to VPWMO(OFF) and disabling the NMOS gate driver. The protection is released when the voltage across VFBH - VFBL drops below VOC_200% - VOC_HYS. At this time the NMOS gate driver is enabled again and the voltage of PWMO pin evolves as demanded by the dimming features. A continuously re-triggering of the protection could cause an overheating of the PMOS. Then a timer records the period in which the device is in over current state. The fault reporting depends on the resistor used on FPWM/FAUL T pin. With a resistor on FPWM/FAUL T pin in RFPWM/FAUL T(H) range, the device reacts to an overcurrent by:

• Entering into the overcurrent state
• Disabling the NMOS gate driver and raises the voltage on PWMO pin to VPWMO(OFF)
• As soon as ( VFBH - VFBL) < (VOC_200% - VOC_HYS) the NMOS gate driver is enabled again
• PWMO pin is again controlled by the dimming feature
• Exiting from the overcurrent state When the cumulative time in which the device is in overcurrent state reaches the overcurrent detection tOC in a time window of 8*tFAUL T the device:
• Raises the voltage of FPWM/FAUL T pin at VFPWM/FAUL T(FAUL T) for the overcurrent fault time tFBH-FBL and then releases the voltage of FPWM/FAUL T pin to VFPWM/FAUL T(REF) for (tFAUL T - tFBH-FBL)
• Repeats this sequence 8 times VREF 8* tFAUL T time windowV FBH-FBL V FPWM/FAUL T 8* tFAUL T VOC_200% V SWO Gate driver enebled Gate driver enabledGate driver disabled V PWMO VPWMO(OFF) VPWMO(ON) Fault Fault Fault Fault Fault Cumulative time > t OC OFF OFF OFF OFF VOC_HYS tFBH-FBL tFAUL T VFPWM/FAUL T(FAUL T) VFPWM/FAUL T(REF) t t t t Overcurrent HRES with PMOS.vsdx Figure 21 System behavior with RFPWM/FAUL T(H) during overcurrent detection with PMOS as dimming/protection element LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller

Datasheet 37 Rev.1.10 2021-09-30

8* tFAUL T V OC_200% V SWO Gate driver enabled Gate driver enabledGate driver disabled tOC tFBH-FBL tFAUL T t t t Overcurrent HRES without PMOS.vsdx V FPWM/FAUL T(REF) V FPWM/FAUL T(FAUL T) V IN V OUT t Figure 22 System behavior with RFPWM/FAUL T(H) during overcurrent detection without PMOS as dimming/protection element With a resistor on FPWM/FAUL T pin in RFPWM/FAUL T(L) range, the device reacts to an overcurrent by:

• Entering into the overcurrent state
• Disabling the NMOS gate driver and raises the voltage on PWMO pin to VPWMO(OFF)
• As soon as ( VFBH - VFBL) < (VOC_200% - VOC_HYS) the NMOS gate driver is enabled again
• PWMO pin is again controlled by the dimming feature
• Exiting from the overcurrent state When the cumulative time in which the device is in overcurrent state reaches tOC in a time window of 8*tFAUL T the device:
• Raises the voltage of FPWM/FAUL T pin at VFPWM/FAUL T(FAUL T) for a time 8*tFAUL T and then releases it to VFPWM/ FAUL T(REF) LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller

Datasheet 38 Rev.1.10 2021-09-30

8* tFAUL T time windowV FBH-FBL V FPWM/FAUL T 8* tFAUL T VOC_200% V SWO Gate driver enebled Gate driver enabledGate driver disabled V PWMO VPWMO(OFF) VPWMO(ON) Fault Fault Fault Fault Fault Cumulative time > t OC OFF OFF OFF OFF VOC_HYS VFPWM/FAUL T(FAUL T) VFPWM/FAUL T(REF) t t t t Overcurrent LRES with PMOS-TLD6098-1EP .vsdx Figure 23 System behavior with RFPWM/FAUL T(L) during overcurrent detection with PMOS as dimming/protection element V REF V FBH -V FBL V FPWM/FAUL T 8* t FAUL T V OC_200% V SWO Gate driver enabled Gate driver enabledGate driver disabled t OC t t t Overcurrent LRES without PMOS-TLD6098-EP .vsdx V FPWM/FAUL T(REF) V FPWM/FAUL T(FAUL T) V IN V OUT t Figure 24 System behavior RFPWM/FAUL T(L) during overcurrent detection without PMOS as dimming/protection element LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 39 Rev.1.10 2021-09-30

During the overcurrent detection, the tS2G_RT filter time is bypassed. In case of simultaneous short to ground detection and overcurrent detection, the device reacts to short to ground failure, cumulating the time in which the device is in overcurrent state. When the cumulated time reaches the tOC, in a time window of 8*tFAUL T, the overcurrent is detected. The fault is detected even the voltage on DC/PWMI pin is lower than VDC/PWMI(OFF).

9.5.1 Electrical characteristics

Table 19 Electrical characteristics VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin; (unless otherwise specified) Parameter Symbol Values Unit Note or condition P- NumberMin. Typ. Max. Overcurrent detection threshold VOC_200% 280 300 – mV VFBH- VFBL increasing PRQ-531 Overcurrent detection hysteresis VOC_HYS 15 – 35 mV 1) PRQ-532 Overcurrent detection time tOC 3.6 4 4.4 ms 1) PRQ-533 Overcurrent fault time tFBH-FBL 1.8 2 2.2 ms 1) PRQ-555 Reaction time during overcurrent detection tOC_200% – – 2 μs 1) PRQ-538 1) Not subject to production test, specified by design

9.6 Overtemperature

Thermal shutdown is an internal feature designed to prevent the device destruction and it is not intended for continuous use in normal operation. If the junction temperature reaches the overtemperature shutdown TJ(SD), the integrated thermal shutdown function turns off the gate drivers and internal linear voltage regulator. The junction temperature is checked each tFAUL T period, and when it is cooled down to (TJ(SD)-TJ(SD_HYS)) the device will automatically restart with a soft-start. LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 40 Rev.1.10 2021-09-30

T J(SD) Gate driver enabled Gate driver disabled Gate driver enabled T J V FPWM/FAUL T T J(SD_HYS) V IVCC V SWO V IVCC_TH_I tfault Gate driver disabled Gate driver enabled V FPWM/FAUL T(FAUL T) tfault tfault tfault t t t t V FPWM/FAUL T(REF) Overtemperatue-TLD6098-1EP .vsdx Figure 25 Timing diagram during overtemperature protection

9.6.1 Electrical characteristics

Table 20 Electrical characteristics VIN = 8 V to 36 V; TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin; (unless otherwise specified) Parameter Symbol Values Unit Note or condition P- NumberMin. Typ. Max. Overtemperature shutdown TJ(SD) 160 175 190 °C 1) PRQ-336 Overtemperature shutdown hysteresis TJ(SD_HYS) – 10 – °C 1) PRQ-337 1) Not subject to production test, specified by design LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 41 Rev.1.10 2021-09-30

Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device TLD6098-1EP IVCC IVCC CBO RSWCS M N RFB CIVCC RFAUL T RSETH RSETL RCOMP CCOMP1 RVFBH RVFBL LED 1 LED 2 LED 3 LED 4 LED 5 LED 6 LED 7 LED 8 GND SWO SWCS FBH FBL VFB COMP DC/PWMI SET FREQ/SYNC/SPREAD FPWM/FAUL T IVCC IN RFREQ IVCC RDCH RDCL VS B2G-1ch.vsdx M P PWMO CCOMP2 Figure 26 Boost to ground application schematic LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 42 Rev.1.10 2021-09-30

L C BO1 D R SWCS M N R FB C IVCC R FAUL T R SETH R SETL R COMP C COMP1 R VFBH R VFBL LED 1LED 2LED 3LED 4 GND SWO SWCS FBH FBL VFB COMP DC/PWMI SET FREQ/SYNC/SPREAD FPWM/FAUL T IVCC IN R FREQ IVCC R DCH R DCL V S B2B-1ch.vsdx PWMO M P C BO2 C COMP2 Figure 27 Boost to battery application schematic LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 43 Rev.1.10 2021-09-30

D RSWCS MN RFB CIVCC RFAUL T RSETH RSETL RCOMP CCOMP1 RVFBH RVFBL LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8 GND SWO SWCS FBH FBL VFB COMP DC/PWMI SET FREQ/SYNC/SPREAD FPWM/FAUL T IVCC IN RFREQ IVCC RDCH RDCL VS SEPIC-1ch.vsdx MP CSEPIC PWMO CCOMP2 Figure 28 SEPIC application schematic TLD6098-1EP IVCC IVCC CBO RSWCS MN RFB CIVCC RFAUL T RSETH RSETL RCOMP CCOMP1 LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8 GND SWO SWCS VFB COMP DC/PWMI SET FREQ/SYNC/SPREAD FPWM/FAUL T IVCC IN RFREQ IVCC RDCH RDCL Cuk-1ch.vsdx L2C1 PWMO FBL FBH RPWMO1 ROVH ROVL RCMRRCML IVCC IVCC VS RPWMO2 Q1 Q2 MPWM MP CCOMP2 Figure 29 Cuk application schematic LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 44 Rev.1.10 2021-09-30

B2G_CV-1ch.vsdx PWMO R LOAD C COMP2 Figure 30 Constant output voltage boost converter application schematic LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 45 Rev.1.10 2021-09-30

Figure 31 Package dimensions PG-TSDSO-14 Note: Green product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e. Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Further information on packages https://www.infineon.com/packages LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 46 Rev.1.10 2021-09-30

Rev.1.10 2021-09-30 • Editorial changes

• New application schematics Rev.1.00 2021-04-16 Initial Datasheet LITIX™ Power TLD6098-1EP Multitopology single-channel DC-DC controller Datasheet 47 Rev.1.10 2021-09-30

All referenced product or service names and trademarks are the property of their respective owners. Edition 2021-09-30 Published by Infineon Technologies AG

81726 Munich, Germany

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