TLD5190

TLD5190_18 INFINEON | Alldatasheet

Document overview

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• PDF pages: 59

Technical content

Features

• Single Inductor high power Buck-Boost controller
• Wide LED forward voltage Range (2 V up to 55 V)
• Wide VIN Range (IC 4.5 V to 40 V, Power 4.5 V to 55 V)
• Switching Frequency Range from 200 kHz to 700 kHz
• Maximum Efficiency in ev ery condition (up to 96%)
• Constant Current (LED) and Constant Voltage Regulation
• EMC optimized device: Features an auto Spread Spectrum
• Open Load, Overvoltages, Shorted LED faul t and Overtemperature Diagnostic Outputs
• LED and Input current sense wi th dedicated monitor Outputs
• Advanced protection features for device and load
• Enhanced Dimming features: Analog and PWM dimming
• LED current accuracy +/- 3%
• Available in a small thermally enhanc ed PG-VQFN-48-31 or PG-TQFP-48-9 package
• Automotive AEC Qualified Figure 1 Application Drawing - TLD5190 as current regulator H-Bridge DC/DC Controller Infineon ® LITIX™ Power Package PG-VQFN-48-31 PG-TQFP-48-9 Marking TLD5190QV TLD5190QU Sales Name TLD5190QV TLD5190QU VIN VREF SET EF1 EF2 CLKOUT COMP IIN2 IIN1 SYNC VIN AGND PWMI LOUT IVCC BST1 BST2 HSGD1 LSGD1 SWN1 LSGD2 HSGD2 SWN2 FBH FBL SWCS SGND PGND1 CIVCC CBST1 CBST2 D1 D2 M2 M3 CIN2 CCOMP Digital dimminig µC SYNC signal CIN1 EN/INUVLO Alternative external VREG supply INOVLO SOFT_START CSOFT_START PGND2 VSS VFB FREQ Cfilter IVCC_ext IINMON IOUTMONAdvanced monitoring CREF Analog dimminig SYNC of other DCDC Errorflag monitoring Spread_spectrumSpread Spectrum ON/OFF COUT1 High Power LED Load RFB RVFB HRVFBL COUT2 COUT3 IVCC_ext RPWMI RSE NSE RSE NSE RSET RCOMP RFREQ Rfilter RIIN R1R2R3 REF 2 REF 1 RSWCS RSYNC

Datasheet 2 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Overview

Description

The TLD5190 is a synchronous MOSFET H-Bridge DC/DC controller with built in protection features. This concept is beneficial for driving hi gh power LEDs with maximum system efficiency and minimum number of external components. The TLD5190 offers both analog and digital (PWM) dimming.The switching frequency is adjustable in the range of 200 kHz to 700 kHz. It can be synchronized to an extern al clock source. A built in Spread Spectrum switching freque ncy modulation and the forced co ntinuous current regulation mode improve the overall EMC behavior. Furthermore the cu rrent mode regulation sc heme provides a stable regulation loop maintained by sma ll external compensation components. The adjustable soft start feature limits the current peak as well as voltage overshoot at start-up. The TLD 5190 is suitable for use in the harsh automotive environment. Protective Functions

• Over load protection of external MOSFETs
• Shorted load, open load, ou tput overvoltage protection
• Input overvoltage and undervoltage protection
• Thermal shutdown of device with autorestart behavior
• Electrostatic discharge protection (ESD) Diagnostic Functions
• Diagnostic information via Error Flags
• Open load detection in ON-state
• Device Overtemperature shutdown
• Advanced diagnostic functions provide I LED and IIN information

Applications

• Especially designed for dr iving high power LEDs in automotive applications
• Automotive Exterior Lighting: full LED headlamp assemblies (Low Beam, High Beam, Matrix Beam, Pixel Light)
• General purpose curr ent/voltage controlled DC/DC LED driver Table 1 Product Summary Power Stage input voltage range VPOW 4.5 V … 55 V Device Input supply voltage range VVIN 4.5 V … 40 V Maximum output voltage (depending by the application conditions) VOUT(max) 55 V as LED Driver Boost Mode

50 V as LED Driver Buck Mode

50 V as Voltage regulator

Switching Frequency range fSW 200 kHz... 700 kHz Typical NMOS driver on-state resistance at Tj = 25°C (Gate Pull Up) RDS(ON_PU) 2.3 Ω Typical NMOS driver on-state resistance at Tj = 25°C (Gate Pull Down) RDS(ON_PD) 1.2 Ω

Datasheet 3 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Block Diagram

2 Block Diagram

Figure 2 Block Diagram - TLD5190

Datasheet 4 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Pin Configuration

3 Pin Configuration

3.1 Pin Assignment

Figure 3 Pin Configuration - TLD5190

Datasheet 5 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Pin Configuration

3.2 Pin Definition s and Functions

Pin Symbol I/O 1) Function Power Supply 1, 12, 15, 45, n.c. - Not connected, tie to AGND on the Layout;

44 VIN - Power Supply Voltage;

Supply for internal biasing.

47 IVCC_EXT I PD External LDO input;

Input to alternatively supply internal Gate Drivers via an external LDO. Connect to IVCC pin to use internal LDO to supply gate drivers. Must not be left open. 5, 8 PGND1, 2 - Power Ground; Ground for power potential. Connect externally close to the chip.

26 VSS - Digital GPIO Ground;

Ground for GPIO pins.

40 AGND - Analog Ground;

-E P - Exposed Pad; Connect to external heatspreading Cu area (e.g. inner GND layer of multilayer PCB with thermal vias). Gate Driver Stages 2H S G D 1 O Highside Gate Driver Output 1; Drives the top n-channel MOSFET with a voltage equal to VIVCC_EXT superimposed on the switch node voltage SWN1. Connect to gate of external switching MOSFET.

11 HSGD2 O Highside Gate Driver Output 2;

Drives the top n-channel MOSFET with a voltage equal to VIVCC_EXT superimposed on the switch node voltage SWN2. Connect to gate of external switching MOSFET. 6L S G D 1 O Lowside Gate Driver Output 1; Drives the lowside n-channel MOSFET between GND and VIVCC_EXT. Connect to gate of external switching MOSFET. 7L S G D 2 O Lowside Gate Driver Output 2; Drives the lowside n-channel MOSFET between GND and VIVCC_EXT. Connect to gate of external switching MOSFET. 4S W N 1 I O Switch Node 1; SWN1 pin swings from a diode voltage drop below ground up to VIN. 9S W N 2 I O Switch Node 2; SWN2 pin swings from ground up to a diode voltage drop above VOUT.

46 IVCC O Internal LDO output;

Used for internal biasing and gate driver supply. Bypass with external capacitor close to the pin. Pin must not be left open.

Datasheet 6 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Pin Configuration Inputs and Outputs

23 TEST1 - Test Pin;

Used for Infineon end of line test, connect to GND in application.

25 TEST2 - Test Pin;

Used for Infineon end of line test, connect to GND in application.

28 TEST3 - Test Pin;

Used for Infineon end of line test, connect to GND in application.

29 TEST4 - Test Pin;

Used for Infineon end of line test, connect to GND in application.

30 TEST5 - Test Pin;

Used for Infineon end of line test, connect to GND in application.

31 TEST6 - Test Pin;

Used for Infineon end of line test, connect to GND in application.

41 EN/INUVLO I PD Enable/Input Under Voltage Lock Out;

Used to put the device in a low current consumption mode, with additional capability to fix an undervoltage threshold via external components. Pin must not be left open.

35 FREQ I Frequency Select Input;

Connect external resistor to GND to set frequency.

34 SYNC I PD Synchronization Input;

Apply external clock signal for synchronization. 24 PWMI I PD Control Input; Digital input 5 V or 3.3 V.

13 FBH I Output current Feedback Positive;

Non inverting Input (+).

14 FBL I Output current Feedback Negative;

Inverting Input (-). 3B S T 1 I O Bootstrap capacitor; Used for internal biasing and to drive the Highside Switch HSGD1. Bypass to SWN1 with external capacitor close to the pin. Pin must not be left open.

10 BST2 IO Bootstrap capacitor;

Used for internal biasing and to drive the Highside Switch HSGD2. Bypass to SWN2 with external capacitor close to the pin. Pin must not be left open.

17 SWCS I Current Sense Input;

Inductor current measurement - Non Inverting Input (+).

18 SGND I Current Sense Ground;

Inductor current sense - Inverting Input (-). Route as Differential net with SWCS on the Layout.

42 IIN1 I Input Current Monitor Positive;

Non Inverting Input (+), connect to VIN if input current monitor is not needed.

43 IIN2 I Input Current Monitor Negative;

Inverting Input (-), connect to VIN if input current monitor is not needed. Pin Symbol I/O 1) Function

Datasheet 7 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Pin Configuration

19 COMP O Compensation Network Pin;

Connect R and C network to pin for stability phase margin adjustment.

38 SOFT_START O Softstart configuration Pin;

Connect a capacitor CSOFT_START to GND to fix a soft start ramp default time.

36 INOVLO I Input Overvoltage Protection Pin;

Define an upper voltage threshold and switches OFF the device in case of overvoltages on the VIN supply. Must not be left open.

20 VFB I Voltage Loop Feedback Pin;

VFB is intended to set output protection functions.

22 SET I Analog current sense adjustment Pin;

A voltage VSET between 0.2 V and 1.5 V will adjust the ILED or VOUT in a linear relation.

37 SPREAD_SPECTR

IP D Spread Spectrum Pin; This pin is enabling and disabling the SPREAD SPECTRUM function. This feature is beneficial to improve the EMC performance.

39 IINMON O Input current monitor output;

Monitor pin that produces a voltage that is 20 times the voltage VIN1-IN2. IINMON will be equal 1 V when VIIN1-VIIN2 = 50 mV.

16 IOUTMON O Output current monitor output;

Monitor pin that produces a voltage that is 200 mV + 8 times the voltage VFBH-FBL. IOUTMON will be equal 1.4 V when VFBH-FBL = 150 mV.

21 VREF O PD Voltage Reference Output Pin;

Supplies an accurate 2 V output voltage for standalone analog dimming and LED temperature compensation via external resistors. Bypass with an external 100nF capacitor close to the pin. Pin must not be left open. Logic Outputs

27 CLKOUT O Clock Output Pin;

Switching Oscillator output signal to supply additional SYNC Inputs of other DCDC devices (beneficial for standalone operations without µC).

33 EF1 O Error Flag 1;

An open drain output which is pulled to LOW when an output Short to GND or Overtemperature occurs.

32 EF2 O Error Flag 2;

An open drain output which is pulled to LOW when an OPEN load, Overvoltages or Overtemperature occurs. 1) O: Output, I: Input, PD: pull-down circuit integrated, PU: pull-up circuit integrated Pin Symbol I/O 1) Function

Datasheet 8 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller General Product Characteristics

4 General Product Characteristics

4.1 Absolute Maximum Ratings

Table 2 Absolute Maximum Ratings 1) TJ = -40°C to +150°C; all voltages with respect to AGND, (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Supply Voltages VIN Supply Input IVCC Internal Linear Voltage Regulator Output voltage VIVCC -0.3 – 6 V – P_4.1.3 IVCC_EXT External Linear Voltage Regulator Input voltage VIVCC_EXT -0.3 – 6 V – P_4.1.4 VREF Voltage reference output Gate Driver Stages LSGD1,2 - PGND1,2 Lowside Gatedriver voltage VLSGD1,2- PGND1,2 HSGD1,2 - SWN1,2 Highside Gatedriver voltage VHSGD1,2- SWN1,2 SWN1, SWN2 switching node voltage VSWN1, 2 -1 – 60 V – P_4.1.6 (BST1-SWN1), (BST2-SWN2) Boostrap voltage VBST1,2- SWN1,2 BST1, BST2 Boostrap voltage related to GND SWCS Switch Current Sense Input voltage VSWCS -0.3 – 0.3 V – P_4.1.9 SGND Switch Current Sense GND voltage SWCS-SGND Switch Current Sense differential voltage VSWCS- SGND PGND1,2 Power GND voltage High voltage Pins IIN1, IIN2 Input Current monitor voltage

Datasheet 9 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller General Product Characteristics IIN1-IIN2 Input Current monitor differential voltage VIIN1-IIN2 -0.5 – 0.5 V – P_4.1.13 FBH, FBL Feedback Error Amplifier voltage VFBH, FBL -0.3 – 60 V – P_4.1.14 FBH-FBL Feedback Error Amplifier differential voltage V FBH-FBL -0.5 – 0.5 V – P_4.1.15 EN/INUVLO Device enable/input undervoltage lockout VEN/INUVLO -0.3 – 60 V – P_4.1.16 Digital (I/O) Pins PWMI Digital Input voltage SYNC Synchronization Input voltage CLKOUT Clock Output voltage VCLKOUT -0.3 – 5.5 V – P_4.1.23 SPREAD_SPECTRUM Spread Spectrum Input voltage VSPREAD_SP ECTRUM Analog Pins VFB Loop Input voltage INOVLO Input overvoltage lockout VINOVLO -0.3 – 5.5 V – P_4.1.26 EF1, 2 Error Flags output voltage SET Analog dimming Input voltage COMP Compensation Input voltage SOFT_START Softstart Voltage VSOFT_STAR T FREQ Voltage at frequency selection pin IINMON Voltage at input monitor pin VIINMON -0.3 – 3.6 V – P_4.1.33 IOUTMON Voltage at output monitor pin VIOUTMON -0.3 – 5.5 V – P_4.1.34 Temperatures Table 2 Absolute Maximum Ratings 1) (cont’d) TJ = -40°C to +150°C; all voltages with respect to AGND, (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 10 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller General Product Characteristics Note: Stresses above the ones listed here may caus e permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the datasheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation.

4.2 Functional Range

Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table.

4.3 Thermal Resistance

Note: This thermal data was generated in accord ance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Junction Temperature Tj -40 – 150 °C – P_4.1.35 Storage Temperature Tstg -55 – 150 °C – P_4.1.36 ESD Susceptibility ESD Resistivity of all Pins VESD,HBM -2 – 2 kV HBM 2) P_4.1.37 ESD Resistivity to GND VESD,CDM -500 – 500 V CDM 3) P_4.1.38 ESD Resistivity of corner Pins to GND VESD,CDM_c orner -750 – 750 V CDM 3) P_4.1.39 1) Not subject to production test, specified by design. 2) ESD susceptibility, HBM accordin g to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF) Table 3 Functional Range Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Device Extended Supply Voltage Range VVIN 4.5 – 40 V 1) 1) Not subject to production test, specified by design. P_4.2.1 Device Nominal Supply Voltage Range VVIN 8– 3 6 V – P_4.2.2 Power Stage Voltage Range VPOW 4.5 – 55 V 1) P_4.2.5 Junction Temperature Tj -40 – 150 °C – P_4.2.4 Table 2 Absolute Maximum Ratings 1) (cont’d) TJ = -40°C to +150°C; all voltages with respect to AGND, (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 11 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller General Product Characteristics Table 4 Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Junction to Case RthJC –0 . 9 –K / W 1) 2) 1) Not subject to production test, specified by design. 2) Specified RthJC value is simulated at natural convection on a cold plate setup (all pins and the exposed pad are fixed to ambient temperature). Ta = 25°C; The IC is dissipating 1 W. P_4.3.1 Junction to Ambient RthJA –2 5 –K / W 3) 2s2p 3) Specified RthJA value is according to JEDEC 2s2p (JESD 51-7) + (JESD 51-5) and JEDEC 1s0p (JESD 51-3) + heatsink area at natural convection on FR4 board; The device was simulated on a 76.2 x 114.3 x 1.5 mm board. The 2s2p board has 2 outer copper layers (2 x 70 µm Cu) and 2 inner copper layers (2 x 35 µm Cu). A thermal via (diameter = 0.3 mm and 25 µm plating) array was applied under the exposed pad and connected the first outer layer (top) to the first inner layer and second outer layer (bottom) of the JEDEC PCB. Ta = 25°C; The IC is dissipating 1 W. P_4.3.2

Datasheet 12 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Power Supply

5 Power Supply

The TLD5190 is supplied by the following pins:

• VIN (main supply voltage)
• IVCC_EXT (supply for internal gate driver stages) The VIN supply provides internal supply voltages for the analog and digital blocks. IVCC_EXT is the supply for the low side driver stages. This supply is used also to charge, through external Schottky diodes, the bootstrap capacito rs which provide supply voltages to the high side driver stages. If no external voltage is available this pin must be shorted to IVCC, which is the output of an internal 5 V LDO. The supply pins VIN and IVCC_EXT have undervoltage detections. U n d e r v o l t a g e o n I V C C _ E X T o r I V C C v o l t a g e s f o r c e s a d e a c t i v a t i o n o f t h e d r i v e r s t a g e s , t h u s s t o p p i n g t h e switching activity. Moreover the double function pin EN/INUVLO can be used as an input undervoltage protection by placing a resistor divider from VIN to GND (refer to Chapter 10.3). If EN/INUVLO undervoltage is detected, it will turn-off the IVCC voltage regulator and stop switching. Figure 4 shows a basic concept drawing of the supply domains and interactions among pins VIN and IVCC/IVCC_EXT. Figure 4 Power Supply Concept Drawing EN/INUVLO VIN VREG (5V) Internal pre-regulated voltage Supply VREG analog VREG digital Bandgap Reference LOGIC IVCC LS - Drivers HS - Drivers BSTx SWNx IVCC_EXT PGND Undervoltage detection

Datasheet 13 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Power Supply Usage of EN/INUVLO pin in different applications The pin EN/INUVLO is a double function pin and can be used to put the device into a low current consumption mode. An undervoltage threshold should be fixed by plac ing an external resistor divider (A) in order to avoid low voltage operating conditions. This pin can be driven by a µC-port as shown in (B) . Figure 5 Usage of EN/INUVLO pi n in different applications A EN/INUVLO GND VIN Vin B EN/INUVLO GND VIN Vin R2 µC Port

Datasheet 14 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Power Supply

5.1 Different Power States

TLD5190 has the following power states:

• S L E E P s t a t e
• I D L E s t a t e
• A C T I V E s t a t e The transition between the power states is determined according to these variables after a filter time of max. 3 clock cycles:
• V I N l e v e l
• E N / I N U V L O l e v e l
• IVCC level
• IVCC_EXT level The state diagram including the possible transitions is shown in Figure 6. The Power-up condition is ente red when the supply voltage V VIN exceeds its minimum supply voltage threshold VVIN(ON). SLEEP When the TLD5190 is in the SLEEP state, all outputs are OFF, independently from the supply voltages VIN, IVCC and IVCC_EXT. The current consumption is low. Refer to parameter: IVIN(SLEEP). The transition from SLEEP to ACTIVE state requires a specified time: tACTIVE. IDLE In IDLE state the internal voltage regulator is work ing. Diagnosis functions ar e not available. The output drivers are switched OFF, independently from the supply voltages VIN, IVCC and IVCC_EXT. ACTIVE In active state the device will start switching activity to provide power at the output only when PWMI = HIGH. To start the Highside gate driv ers HSGD1,2 the voltage level VBST1,2 - VSWN1,2 needs to be above the threshold VBST1,2 - VSWN1,2_UVth. In ACTIVE state the device current consumption via VIN is dependent on the external MOSFET used and the switching frequency fSW. Figure 6 Simplified State Diagram SLEEP IDLE ACTIVE EN/INUVLO = LOW EN/INUVLO = LOW EN/INUVLO = LOW VIN = HIGH & IVCC = HIGH & IVCC_EXT = HIGH VIN = LOW or IVCC = LOW or IVCC_EXT = LOW Power-up EN/INUVLO = HIGH

Datasheet 15 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Power Supply

5.2 Electrical Characteristics

VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Power Supply VIN Input Voltage Startup VVIN(ON) ––4 . 7 V VIN increasing; VEN/INUVLO = HIGH; IVCC = IVCC_EXT = 10 mA; P_5.3.1 Input Undervoltage switch OFF VVIN(OFF) ––4 . 5 V VIN decreasing; VEN/INUVLO = HIGH; IVCC = IVCC_EXT = 10 mA; P_5.3.14 Device operating current I VIN(ACTIVE) –4 . 4 6m A 1)ACTIVE mode; CLKOUT freq.

300 KHz;

VPWMI = 0 V; 1) Not subject to production test, specified by design. P_5.3.2 VIN Sleep mode supply current IVIN(SLEEP) ––1 . 5 µ A VEN/INUVLO = 0 V; VIN = 13.5 V; VIVCC = VIVCC_EXT= 0 V; P_5.3.3 EN/INUVLO Pin characteristics Input Undervoltage falling Threshold EN/INUVLO Rising Hysteresis VEN/INUVLO(hy st) EN/INUVLO input Current LOW I EN/INUVLO(LO EN/INUVLO input Current HIGH I EN/INUVLO(HI GH) Timings SLEEP mode to ACTIVE time tACTIVE ––0 . 7 m s 1) VIVCC = VIVCC_EXT; CIVCC = 10 µF; VIN = 13.5 V; P_5.3.11

Datasheet 16 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Regulator Description

6 Regulator Description

The TLD5190 includes all of the functions necessary to provide constant current to the output as usually required to drive LEDs. A voltage mode regulation can also be implemented (Refer to Chapter 6.6). It is designed to control 4 gate driver outputs in a H-Bridge topology by using only one inductor and 4 external MOSFETs. This topology is able to operate in high power BOOST, BUCK-BOOST and BUCK mode applications with maximum efficiency. The transition between the different regulation modes is done automatically by the device itself, with respect to the application boundary conditions. The transition phase between modes is seamless.

6.1 Regulator Diagram Description

The TLD5190 includes two analog current control inputs (IIN1, IIN2) to limit the maximum Input current (Block A1 and A7 in Figure 7). A second analog current control loop (A5, A6 with complessive gain = IFBxgm) connected to the sensing pins FBL, FBH regulates the output current. The regulator function is implemented by a pulse width modulated (PWM) current mode controller. The error in the output current loop is used to determine the appropriate duty cycle to get a constant output current. An external compensation network ( RCOMP, CCOMP) is used to adjust the contro l loop to various application boundary conditions. The inductor current for the current mode loop is sensed by the RSWCS resistor. RSWCS is used also to limit the maximum external switches / inductor current. If the Voltage across RSWCS exceeds its overcurrent threshold ( VSWCS_buck or V SWCS_boost for buck or boost operation respectively) the device reduces the duty cy cle in order to bring the switches current below the imposed limit. The current mode controller has a built-in slope compensation as well to prevent sub-harmonic oscillations. The control loop logic block (LOGIC) provides a PWM sign al to four internal gate drivers. The gate drivers (HSGD1,2 and LSGD1,2) are used to dr ive external MOSFETs in an H-Bridge setup . Once the soft start expires a forced CCM regulation mode is performed. The control loop block diagram displayed in Figure 7 shows a typical constant current application. The voltage across RFB sets the output current. RIN is used to fix the maximum input current.

Datasheet 17 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Regulator Description Figure 7 Regulator Block Diagram - TLD5190 VIN + - +-+- + - +-+- -++- LOGIC CLK HSGD1 HSGD2M1 M2 M3 RSWCS COUT Vi_REF SET RFBIIN LOUT RCOMP CCOMP IOUT VOUT SLOPE SELECTION & Compensation BOOST BUCK IIN2IIN1 RIN SWCS SGND FBH FBL COMP VCOMP HSGD2 LSGD1 LSGD2 LSGD2 HSGD1 LSGD1 Rfilter Cfilter ISWCSx

Datasheet 18 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Regulator Description

6.2 Adjustable Soft Start Ramp

The soft start routine limits the current through th e inductor and the external MOSFET switches during initialization to minimize potential overshoots at the output. The soft start routine is applied:

• At first turn on (first PWM rise after EN = High)
• After Output Short to GN D or Open Load detection
• After Input Overvoltage detection The soft start rising edge gradually increases the current of the inductor (L OUT) over tSOFT_START by clamping the COMP voltage . The soft start ramp is defined by a capacitor placed at the SOFT_START pin. Selection of the SOFT_START capacitor ( CSOFT_START) can be done according to the approximate formula described in Equation (6.1): (6.1) Note: V ss_th_eff is the soft start effectiveness threshold, that depends on load condition. Its value is about 0.7 V for the buck mode and 1.4 V for the boost mode The SOFT START pin is also used to implement a fault mask and wait-before-retry time, on rising and falling edge respectively, see and chapter Chapter 10.2 for details. If an open load or a short on the output is detected, a pull-down current source ISOFT_START_PD (P_6.4.20) is activated. Through a pull-up resistor connected from VREF to the SOFT START pin it is possible to source a current higher than ISOFT_START_PD, the TLD5190 will latch OFF until the EN /INUVLO pin is toggled. Without any resistor to VREF the pull-down current decreases until V SOFT_START_RESET (P_6.4.22) is reached (the pull-up current source turns on again). If the fa ult condition hasn’t been removed until VSOFT_START_LOFF (P_6.4.21) is reached, the pull-down current source ISOFT_START_PD turns on again initiating a new cycle. This will continue until the fault is removed. If an input overvoltage is detected the soft start is kept low as long as the overvoltage remains. At first PWMI rise after EN = High, the internal PWM is extended till one of the 2 following condition is reached:
• U n t i l VSOFT_START exceeds VSoft_Start1,2_LOFF
• U n t i l VFBH-FBL exceeds VFBH_FBL_OL STARTSOFT PUSTARTSOFT effthss STARTSOFT CI Vt _ )(_ _ ⋅=

Datasheet 19 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Regulator Description Figure 8 Soft Start timing diagram on a sh ort to ground detected by the VFB pin

6.3 Switching Frequency setup

The switching frequency can be set from 200 kHz to 700 kHz by an external resistor connected from the FREQ pin to GND or by supplying a sync signal as specified in chapter Chapter 11.2. Select the switching frequency with an external resistor according to the graph in Figure 9 or the following approximate formulas. (6.2) (6.3) Figure 9 Switching Frequency fSW versus Frequency Select Resistor to GND RFREQ VVFB_S2G VFB1 SWN SHORT DETECTION Normal Operation Vout shorted to GND Normal Operation Application Status Vsoft_Start_RESET Vsoft_Start_LOFF Event Vout short to GND applied Event Vout short to GND removed ISOFT_START 8 clock cycles VSOFT_START Vsoft_Start_reg ISOFT_START_PU ISOFT_START_PD 8.0)][(*5375][ −Ω= kRkHzf FREQSW 25.1])[(*46023][ −=Ω kHzfkR SWFREQ

Datasheet 20 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Regulator Description

6.4 Operation of 4 switche s H-Bridge architecture

Inductor LOUT connects in an H-Bridge configuration with 4 external N channel MOSFETs (M1, M2, M3 & M4)

• Transistor M1 and M3 provides a path between V IN and ground through LOUT in one direction (Driven by top and bottom gate drivers HSGD1 and LSGD2)
• Transistor M2 and M4 provides a path between VOUT and ground through L OUT in the other direction (Driven by top and bottom gate drivers HSGD2 and LSGD1)
• Nodes SWN1, SWN2, voltage across R SWCS, input and load currents are also monitored by the TLD5190 Figure 10 4 switches H-Bridge archit ecture Transistor Status summary Figure 11 4 switches H-Brid ge architecture overview

6.4.1 Boost mode (V IN < VOUT)

• M1 is always ON, M2 is always OFF
• Every cycle M3 turns ON first and inducto r current is sensed (peak current control)
• M3 stays ON until the upper reference threshold is reached across RSWCS (Energizing) BOOST MODE BUCK-BOOST MODE BUCK MODE M1 ON PWM PWM M2 OFF PWM PWM M3 PWM PWM OFF M4 PWM PWM ON LOUT SWN1 SWN2 RSWCS LSGD1 HSGD1 LSGD2 HSGD2 VIN VOUT

Datasheet 21 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Regulator Description

• M3 turns OFF, M4 turns ON until th e end of the cycle (Recirculation)
• Switches M3 and M4 alternate, behaving li ke a typical synchronous boost Regulator (see Figure 12) Figure 12 4 switches H-Bridge architecture in BOOST mode Simplified comparison of 4 switches H-Bridge architecture to traditional asynchronous Boost approach.
• M2 is always OFF in this mode (open)
• M1 is always ON in this mode (c losed connection of inductor to VIN)
• M4 acts as a synchronous diode, with sign ificantly lower conduction power losses (I2 x RDSON vs. 0.7 V x I) Note: Diode is source of losses and lower system efficiency! Figure 13 4 switches H-Bridge architecture in B OOST mode compared to standard async Booster

6.4.2 Buck mode (V IN > VOUT)

• M4 is always ON, M3 is always OFF
• Every cycle M2 turns ON and inductor current is sensed (valley current control)
• M2 stays ON until the lower refere nce threshold is reached across RSWCS (Recirculation) (2) Recirculation (1) Energizing LOUT SWN1 SWN2 RSWCS LSGD1 HSGD1 LSGD2 HSGD2 VIN VOUT M1+M3 ILOUT t M1+M3 M1+M3 OFF ON LSGD2 HSGD2 LSGD1 (OFF)HSGD1 M1 (ON) RSWCS VIN VOUT LOUT VIN VOUT LOUT RSWCS a) 4 switch architecture BOOSTER b) standard asynchronous BOOSTER

Datasheet 22 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Regulator Description

• M2 turns OFF, M1 turns ON until the end of the cycle (Energizing)
• Switches M1 and M2 alternate, behaving li ke a typical synchronous BUCK Regulator (see Figure 14) Figure 14 4 switches H-Bridge architecture in BUCK mode Simplified comparison of 4 switches architecture to traditional asynchronous Buck approach.
• M3 is always OFF in this mode (open).
• M4 is always ON in this mode (closed connection inductor to VOUT).
• M2 acts as a synchronous diode, with significantly lower conduction losses (I2 x RDSON vs. 0.7 V x I) Figure 15 4 switches H-Bridge architecture in BUCK mode compared to standard async BUCK

6.4.3 Buck-Boost mode (V IN ~ VOUT)

• W h e n V IN is close to VOUT the controller is in Buck-Boost operation
• All switches are switching in buck-boost operation. The direct energy transfer from the Input to the output (M1+M4 = ON) is beneficial to reduce ripple current and improves the energy efficiency of the Buck-Boost control scheme
• The two buck boost waveforms and sw itching behaviors are displayed in Figure 16 below LOUT SWN1 SWN2 RSWCS LSGD1 HSGD1 LSGD2 HSGD2 VIN VOUT (4) Recirculation (3) Energizing M2+M4 M2+M4 ILOUT tM1 M2+M4 OFF ON LSGD1 HSGD1 LSGD2 (OFF) HSGD2 (ON) HSGD1 RSWCS VIN VOUT LOUT VIN VOUT LOUT a) 4 switch architecture BUCK b) standard asynchronous BUCK

Datasheet 23 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Regulator Description Figure 16 4 switches H-Bridge ar chitecture in BUCK-BOOST mode

6.5 Flexible current sense

The flexible current sense implementation enables highside and lowside current sensing. The Figure 17 displays the application examples for the highside and lowside current sense concept. Figure 17 Highside and lowside current sensing - TLD5190 LOUTSWN1 SWN2 RSWCS LSGD1 HSGD1 LSGD2 HSGD2 VIN VOUT (3) Recirculation (4) Direct Transfer (2) Direct Transfer (1) Energizing ILOUT t VIN ≤ VOUT M2+ M4 M2+ M4 M2+ M4 VIN ≥ VOUT ILOUT t M1+ M3 M1+ M3 M1+ M3 VIN Highside Sensing VIN Lowside Sensing FBH FBL FBH FBL

Datasheet 24 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Regulator Description

6.6 Programming Output Voltage (Constant Voltage Regulation)

For a voltage regulator, the output volt age can be set by selecting the values RFB1, RFB2 and RFB3 according to the following Equation (6.4): (6.4) If Analog dimming is performed, due to the variations on the IFBL ( IFBL_HSS (P_6.4.9) and IFBL_LSS (P_6.4.40)) current on the entire voltage spanning, a non linearit y on the output voltage may be observed. To minimize this effect RFBx resistors should be properly dimensioned. Figure 18 Programming Output Voltage (Constant Voltage Regulation) FBLFBHFBFBL FB FBLFBH FB FB FBLFBH FBHOUT VRIR VRR VIV − ⎛ += 3 FBH VOUT RFB1 RFB2 FBL RFB3 IFBH IFBL

Datasheet 25 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Regulator Description

6.7 Electrical Characteristics

VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Regulator: V (FBH-FBL) threshold V(FBH-FBL) 145.5 150 154.5 mV VSET = 2 V; P_6.4.1 V(FBH-FBL) threshold @ analog dimming 10% V(FBH- FBL)_10 10 15 20 mV VSET = 0.32 V; P_6.4.6 FBH Bias current @ highside sensing setup IFBH_HSS 65 110 155 µA 1)VFBL = 7 V; VFBH - FBL = 150 mV; P_6.4.8 FBL Bias current @ highside sensing setup IFBL_HSS 17 30 43 µA 1)VFBL = 7 V; VFBH - FBL = 150 mV; P_6.4.9 FBH Bias current @ lowside sensing setup IFBH_LSS -7.5 -4 -2.5 µA 1)VFBL = 0 V; VFBH - FBL = 150 mV; P_6.4.39 FBL Bias current @ lowside sensing setup IFBL_LSS -45 -30 -20 µA 1)VFBL = 0 V; VFBH - FBL = 150 mV; P_6.4.40 FBH-FBL High Side sensing entry threshold VFBH_HSS_in c -2 -V 1)VFBH1 increasing; P_6.9.1 FBH-FBL High Side sensing exit threshold VFBH_HSS_d ec -1 . 7 5 -V 1)VFBH decreasing; P_6.9.2 OUT Current sense Amplifier gm IFBxgm – 890 – µS 1) P_6.4.10 Maximum BOOST Duty Cycle DBOOST_MA X 89 91 93 % 1)fsw = 300 kHZ; P_6.4.12 Input Current Sense threshold VIIN1-IIN2 VIIN1-IIN2 46 50 54 mV – P_6.4.13 Input Current sense Amplifier gm IIN_gm –2 . 1 2 –m S 1) P_6.4.14 Input current Monitor Voltage VIINMON 0.95 1 1.05 V 1)VIIN1 - IIN2 = 50 mV; VIIN1 = VVIN(ON) to 55 V; P_6.4.15 Switch Peak Over Current Threshold - BOOST VSWCS_boost 40 50 60 mV 1) P_10.8.1 Switch Peak Over Current Threshold - BUCK VSWCS_buck -60 -50 -40 mV 1) P_10.8.1 Soft Start Soft Start pull up current I Soft_Start_P U 22 26 32 µA VSoft_Start = 1 V; P_6.4.19 Soft Start pull down current ISoft_Start_P D

Datasheet 26 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Regulator Description Soft Start Latch-OFF Threshold VSoft_Start_L OFF Soft Start Reset Threshold VSoft_Start_R ESET Soft Start Voltage during regulation VSoft_Start_r eg 1.9 2 2.1 V 1)No Faults P_6.9.3 Oscillator Switching Frequency fSW 285 300 315 kHz Tj = 25°C; RFREQ= 37.4 kΩ; P_6.4.23 SYNC Frequency fSYNC 200 – 700 kHz – P_6.4.24 SYNC Turn On Threshold VSYNC,ON 2––V – P_6.4.25 SYNC Turn Off Threshold VSYNC,OFF ––0 . 8 V – P_6.4.26 SYNC High Input Current ISYNC,H 15 30 45 µA VSYNC = 2.0 V; P_6.4.62 SYNC Low Input Current ISYNC,L 6 1 21 8µ A VSYNC = 0.8 V; P_6.4.63 Gate Driver for external Switch Gate Driver undervoltage threshold VBST1,2- VSWN1,2_UVth V BST1,2- VSWN1,2_UVt h 3.4 – 4 V VBST1,2 - VSWN1,2 decreasing; P_6.4.64 HSGD1,2 NMOS driver on-state resistance (Gate Pull Up) RDS(ON_PU) HS 1.4 2.3 3.7 Ω VBST1,2 - VSWN1,2 = 5 V; Isource = 100 mA; P_6.4.28 HSGD1,2 NMOS driver on-state resistance (Gate Pull Down) RDS(ON_PD) HS 0.6 1.2 2.2 Ω VBST1,2 - VSWN1,2 = 5 V; Isink = 100 mA; P_6.4.29 LSGD1,2 NMOS driver on-state resistance (Gate Pull Up) RDS(ON_PU) LS 1.4 2.3 3.7 Ω VIVCC_EXT = 5 V; Isource = 100 mA; P_6.4.30 LSGD1,2 NMOS driver on-state resistance (Gate Pull Down) RDS(ON_PD)L S 0.4 1.2 1.8 Ω VIVCC_EXT = 5 V; Isink = 100 mA; P_6.4.31 HSGD1,2 Gate Driver peak sourcing current IHSGD1,2_SR C 380 – – mA 1) VHSGD1,2 - VSWN1,2 = 1 V to 4 V; V BST1,2 - VSWN1,2 = 5 V P_6.4.32 HSGD1,2 Gate Driver peak sinking current IHSGD1,2_SN K 410 – – mA 1) VHSGD1,2 - VSWN1,2 = 4 V to 1 V; VBST1,2 - VSWN1,2 = 5 V P_6.4.33 Table 6 EC Regulator (cont’d) VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 27 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Regulator Description LSGD1,2 Gate Driver peak sourcing current ILSGD1,2_SRC 370 – – mA 1) VLSGD1,2 = 1 V to 4 V; VIVCC_EXT = 5 V; P_6.4.34 LSGD1,2 Gate Driver peak sinking current ILSGD1,2_SN K 550 – – mA 1) VLSGD1,2 = 4V t o 1V ; VIVCC_EXT = 5 V; P_6.4.35 LSGD1,2 OFF to HSGD1,2 ON delay tLSOFF- HSON_delay 15 30 40 ns 1) P_6.4.36 HSGD1,2 OFF to LSGD1,2 ON delay tHSOFF- LSON_delay 35 60 75 ns 1) P_6.4.37 1) Not subject to production test, specified by design Table 6 EC Regulator (cont’d) VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Datasheet 28 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Digital Dimming Function

7 Digital Dimming Function

PWM dimming is adopted to vary LEDs brightness wi th greatly reduced chroma ticity shift. PWM dimming achieves brightness reduction by varying the duty cycle of a constant current in the LED string.

7.1 Description

A PWM signal can be transmitted to the TLD5190 as described below. PWM via direct interface The PWMI pin can be fed with a pulse width modulated (PWM) signals, this enables when HIGH and disables when LOW the gate drivers of the main switches. Figure 19 Digital Dimming Overview To avoid unwanted output overshoots due to not soft start assisted startups, PWM dimming in LOW state s h o u l d n o t b e u s e d t o s u s p e n d t h e o u t p u t c u r r e n t f o r l o n g t i m e i n t e r v a l s . T o s t o p i n a s a f e m a n n e r EN/INUVLO=LOW can be used. AGNDVSS µC PWMIDigital dimming PWM

Datasheet 29 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Digital Dimming Function Figure 20 Timing Diagram LED Dimming and Start up behavior example ( VVIN stable in the functional range and not during startup) VEN/INUVLO VIVCC_EXT_RTH,d +VIVCCX_HYST VIOUTMON ILED VEN/INUVLOth t t t t Normal Gate ON Diagnosis ON Dim Gate OFF Diag OFF Power ON Normal Gate ON Diag ON tACTIVE VPWMI VPWMI,ON VPWMI,OFF t TPWMI tPWMI,H Dim Gate OFF Diag OFF Dim Gate OFF Diag OFF Normal Gate ON Diag ON Softstart t 200mV Switching activity

Datasheet 30 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Digital Dimming Function

7.2 Electrical Characteristics

Table 7 EC Digital Dimming VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. PWMI Input: PWMI Turn On Threshold V PWMI,ON 2–– V– P_7.2.1 PWMI Turn Off Threshold VPWMI,OFF ––0 . 8 V– P_7.2.2 PWMI High Input Current IPWMI,H 15 30 45 µA VPWMI = 2.0 V; P_7.2.4 PWMI Low Input Current IPWMI,L 61 2 1 8 µ A VPWMI = 0.8 V; P_7.2.5

Datasheet 31 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Analog Dimming

8 Analog Dimming

The analog dimming feature allows further control of the output current. This approach is used to:

• Reduce the default current in a narr ow range to adjust to different binning classes of the used LEDs.
• Adjust the load current to enable the usage of one hardware for several LED types where different current levels are required.
• Reduce the current at high temperatures (protect LEDs from overtemperature).
• Reduce the current at low input volt ages (for example, cranking-pulse breakdown of the supply or power derating).

8.1 Description

The analog dimming feature is adjust ing the average load current level vi a the control of the feedback error Amplifier voltage (VFBH-FBL). The SET pin is used to adjust the mean output current/voltage. The VSET range where analog dimming is enabled is from 200 mV to 1.5 V. Different application scenarios are described in Figure 22. Using the SET pin to adjust the output current: For the calculation of the output current IOUT the following Equation (8.1) is used: (8.1) A decrease of the average output current can be ac hieved by controlling the voltage at the SET pin (V SET) between 0.2 V and 1.4 V. The mathematical relation is given in the Equation (8.2) below: (8.2) If VSET is 200 mV (typ.) the LED current is only determined by the internal offset voltages of the comparators. To assure the switching activity is stopped and IOUT = 0, VSET has to be < 100 mV, see Figure 21. Figure 21 Analog Dimming Overview FB FBLFBH OUT R VVI −= 200 FB SET OUT R mVVI 150mV Analog Dimming Enabled 0mV Analog Dimming Disabled 200mV 1.4V 1.5V 100mV VFBH-FBL VSET

Datasheet 32 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Analog Dimming Multi-purpose usage of the Analog dimming feature 1) A μC integrated digital analog conver ter (DAC) output or a stand alone DAC can be used to supply the SET pin of the TLD5190. 2) The usage of an external resistor divider connected between VREF (accurate regulated supply output) SET and GND can be chosen for systems without μC on board. The concept allows control of the LED current by placing low power resistors. 3) Furthermore a temperature sensitive resistor (T hermistor) to protect the LED loads from thermal destruction can be connected. 4) If the analog dimming feature is not needed, the SET pin should be connected to the VREF pin. 5) Instead of a DAC, the μC can provide a PWM signal and an external R-C filter to produce a constant voltage for the analog dimming. The voltage level depends on the PWM frequency (fPWM) and duty cycle which can be controlled by the μc software after reading the coding resistor placed on the LED module. Figure 22 Different use cases for analog dimming pin SET

8.2 Electrical Characteristics

µC D/A-Output GND VSET SET GNDVSET ~ VREF VREF Cfilter Rfilter 1 2 3 4 Rfilter PWM SET µC (e.g. XC2000) PWM output GND VSET Cfilter µC_supply SET GNDVSET VREF Cfilter RSET1 RSET2 SET GNDVSET VREF Cfilter RSET1 Rthermistor µC_supply CREF CREFCREF

Datasheet 33 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Analog Dimming Table 8 EC Analog Dimming VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Source current on SET Pin ISET_source –– 1µ A 1)VSET = 0.2 V to 1.4 V; 1) Specified by design: not subject to production test. P_8.3.4

Datasheet 34 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Linear Regulator

9 Linear Regulator

The TLD5190 features an integrated voltage regulator for the supply of the internal gate driver stages. Furthermore an external voltage regulator can be conne cted to the IVCC_EXT pin to achieve an alternative gate driver supply if required.

9.1 IVCC Description

When the IVCC pin is connected to the IVCC_EXT pin, the internal linear voltage regulator supplies the internal gate drivers with a typical voltage of 5 V and current up to ILIM (P_9.2.2). An external output capacitor with low ESR is required on pin IVCC for stab ility and buffering transient load cu rrents. During normal operation the external MOSFET switches will draw transient currents from the linear regulator and its output capacitor (Figure 23, drawing A). Proper sizing of the output capacitor must be considered to supply sufficient peak current to the gate of the external MOSFET switches. A minimum capacitance value is given in parameter CIVCC (P_9.2.4). Alternative IVCC_EXT Supply Concept: The IVCC_EXT pin can be used for an external voltage supply to alternatively supply the MOSFET Gate drivers. This concept is beneficial in the high input voltage range to avoid power losses in the IC (Figure 23, drawing B). Integrated undervoltage protection for the external switching MOSFET: An integrated undervoltage reset threshold circuit monitors the linear regu lator output voltage. This undervoltage reset threshold circuit will turn OFF th e gate drivers in case the IV CC or IVCC_EXT voltage falls The Undervoltage Reset threshold for the IVCC and the IVCC_EXT pins help to pr otect the external switches from excessive power dissipation by ensuring the gate drive voltage is sufficient to enhance the gate of the external logic level N-channel MOSFETs. Figure 23 Voltage Regulator Configurations Internal VREG Gate Drivers VIN IVCC IVCC_EXT A B External VREG Power On Reset Internal VREG Gate Drivers VIN IVCC IVCC_EXT Power On Reset

Datasheet 35 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Linear Regulator

9.2 Electrical Characteristics

VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. IVCC Output Voltage V IVCC 4.8 5 5.2 V VIN= 13.5 V; 0.1 mA ≤ IIVCC ≤ 50 mA; P_9.2.1 Output Current Limitation ILIM 70 90 110 mA 1) VIVCC = 4 V; 1) Not subject to production test, specified by design P_9.2.2 Drop out Voltage (VIN - VIVCC) VDR – 200 350 mV VIN = 5 V; IIVCC = 10 mA; P_9.2.3 IVCC Buffer Capacitor C IVCC 10 – – µF 1) 2) 2) Minimum value given is needed for regu lator stability; application might need higher capacitance than the minimum. Use capacitors with LOW ESR. P_9.2.4 IVCC_EXT Undervoltage Reset switch OFF Threshold VIVCC_EXT_R TH,d 3.7 3.9 4.1 V 3) VIVCC_EXT decreasing; 3) Selection of external swit ching MOSFET is crucial. VIVCC_EXT_RTH,d and VIVCC_RTH,d min. as worst case VGS must be considered. P_9.2.5 IVCC Undervoltage Reset switch OFF Threshold VIVCC_RTH,d 3.7 3.9 4.1 V 3) VIVCC decreasing; P_9.2.9 IVCC and IVCC_EXT Undervoltage Hysterisis VIVCCX_HYST 0.3 0.33 0.36 V VIVCC increasing; VIVCC_EXT increasing; P_9.2.6 VREF voltage VREF 1.94 2 2.06 V 0 ≤ IVREF ≤ 200 µA; P_9.2.8

Datasheet 36 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Protection and Diagnostic Functions

10 Protection and Diagnostic Functions

10.1 Description

The TLD5190 has integrated circuits to diagnose and protect against overvoltage, open load, short circuits of the load and overtemperature faults. In IDLE state, only the Over temperature Shut Down, Over Temperature Wa rning, IVCC or IVCC_EXT Undervoltage Monitor or VEN/INUVLO Undervoltage Monitor are reported according to specifications. In Figure 24 a summary of the protection, diagnostic and monitor functions is displayed. Figure 24 Protection, Diagnostic an d Monitoring Overview - TLD5190 Figure 25 Diagnostic Truth Table - TLD5190 Note: A device Overtemperature even t overrules all other fault events! Monitoring Overvoltages Open Load Device Overtemperature Protection and Diagnostic OR Input Undervoltage Short at the Load OR IOUT IIN IOUTMON IINMON KILIS Factor 20 KILIS Factor 8 EF1, EF2 No output current Linear Regulators OFF (only IVCC disabled in case of overtemperature) Output Gate Drivers IVCCEF1 Input Open Load / Overvoltages Overtemperature Level*Condition H L H Sw* L L Shutdown H Sw* *Note: Sw = Switching False = Condition does not exist True = Condition does exist False True False True Shorted LED fault L L H Sw*False True Active Active Active Active Active EF2 L H L H H H

Datasheet 37 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Protection and Diagnostic Functions

10.2 Output Overvoltage, Open Load, Short circuit protection

The VFB pin measures the voltage on the application output and in accordance with the populated resistor divider, short to ground, open load and outp ut overvoltage thresholds are set. Refer to Figure 26 for more details. Figure 26 VFB Protection Pin - Overview

10.2.1 Short Circuit protection

The device detects a short circuit at the output if this condition is verified:

• The pin VFB falls below the threshold voltage VVFB_S2G for at least 8 clock cycles During the rising edge of the Soft Start the short circuit detection via VFB is ignored until VSOFT_START_LOFF (see Figure 8). A voltage divider between VOUT, VFB pin and AGND is used to adjust the application short circuit thresholds following Equation (10.1). (10.1) The TLD5190 provides an open-drain st atus pin, EF1, which pulls low when the short circuit is detected. The only time the FB pin will be below VVFB_S2G is during start-up or if the LEDs are shorted. During start-up the TLD5190 ignores the detection of a shor t circuit or an open load until th e soft-start capacitor reaches 1.75 V. To prevent false tripping after startup, a large enough soft-start capacitor must be used to allow the output to get up to approximately 50% of the final value. Note: If the short circuit condition di sappears, the device will re-start with the soft start routine as described in Chapter 6.2.

10.2.2 Overvoltage Protection

A voltage divider between VOUT, VFB pin and AGND is used to adjust the overvoltage protection threshold (refer to Figure 26). LOUT COUT VIN IVCC BST1 BST2 HSGD1 LSGD1 SWN1 LSGD2 HSGD2 SWN2 FBH FBL SWCS SGND PGND CIVCC RSWCS CBST1 CBST2 D1 D2 M2 M3 RFB VFB VVFB_OVTH VVFB_OL,rise VVFB_S2G VOUT RVFBH RVFBL VFBL VFBLVFBH GSVFBledshort R RRVV +⋅= 2__

Datasheet 38 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Protection and Diagnostic Functions To fix the overvoltage protection threshold the following Equation (10.2) is used: (10.2) In case of overvoltage event at the output, the open-drain status pin EF2 will toggle to LOW, while EF1 will stay at HIGH. After the overvoltage event disappeared the device will auto restart and the status pin EF2 will toggle to HIGH.

10.2.3 Open Load Protection

To reliably detect an open load event, two conditions need to be observed: 1) Voltage threshold: VVFB > VVFB_OL,rise 2) Output current information: V(FBH-FBL) < VFBH_FBL_OL During the rising edge of the Soft Start the open load detection is ignored until VSOFT_START_LOFF. The TLD5190 provides an open-drain status pin, EF2, which pulls low when the VFB pin is above VVFB_OL,rise threshold and the voltage across V(FBH-FBL) is less than VFBH_FBL_OL. If the open LED clamp voltage is programmed correctly using the VFB pin, then the VFB pin should never exceed 1.28 V ( VVFBOL,fall when the LEDs are connected. After an Open Load error the TLD5190 is autorestarting the output control accord ingly to the implemented Softstart routine. An Open Load er ror causes an increase of the outp ut voltage as well. An Overvoltage condition could be reported in combination with an Open Load error (in general, multiple error detection may happen if more error detection thresholds are reached during the autorestart funcion, as possible consequence of reactive behavior at the output node during open load). The COMP capacitor is discharged during an Open Load condition to prevent spikes if load reconnects. This measure could artificially generate Short Circuit detections after open loads events.

10.3 Input voltage monitoring, protection and power derating

Input overvoltage and undervoltage shutdown levels can both be defined through an external resistor divider, as shown in Figure 27. Both INOVLO and EN/INUVLO pin voltages are internally compared to their respective thresholds by means of hysteretic comparators. VFBL VFBLVFBH OVTHVFBprotectedOVOUT R RRVV +⋅= ___

Datasheet 39 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Protection and Diagnostic Functions Neglecting the hysteresis, the following equations hold: (10.3) (10.4) (10.5) (10.6) (10.7) (10.8) Figure 27 Input Voltage Protection In case of overvoltage event at the input, the open-drain status pin EF2 will toggle to LOW, while EF1 will stay at HIGH. The softstart capacitor will be discharged by an internal pull down switch. After the overvoltage event disappeared the device will auto restart with the softstart function, and the status pin EF2 will toggle to HIGH.

10.4 Input current Moni toring and Limiter

The two inputs (IIN1, IIN2) can be used to limit and monitor the Input current (Block A1 and A7 in Figure 7). thth INUVLOENRR RUV /1 1 ⋅⎟⎟ ++= thth INOVLOR RROV ⋅⎟⎟ ⎛ ++= 211 η OUTOUT IN IVP ⋅= η ⎛ ⋅ IN OUTOUT boundaryIN I IV V _ IN ININ IN R VI 21−= FB FBLFBH OUT R VI −=

Datasheet 40 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Protection and Diagnostic Functions The control loop reduces the Comp voltage when the voltage accross th e pins reaches Input Current Sense threshold VIIN1-IIN2 to keep the input current below IINMax Equation (10.9) (10.9) The IINMON pin provides a linear indication of the current flowing through the input. The following Equation (10.10) is applicable: (10.10) Note: If the R IN value is choosen in a way that the current limitiation is much bigger than the nominal input current during the application the current measurement becomes inaccurate. Best results for an accurate current measurement via the VIINMON pin is to set the current limit only slightly above the specific application related nominal input current.

10.5 Output current Monitoring

The IOUTMON pin provides a linear indication of the current flowing throug h the LEDs. The following Equation (10.11) is applicable: (10.11) IIN Max VIIN1 IIN2– RIIN 20⋅⋅= ININIINMON RIV 8200 ⋅⋅+= FBOUTIOUTMON RImVV

Datasheet 41 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Protection and Diagnostic Functions

10.6 Device Temperat ure Monitoring

A temperature sensor is integrated on the chip. The temperature monito ring circuit compares the measured temperature to the shutdown threshold. If the internal temperature sensor reaches the shut-down temperature, the Gate Drivers plus the IVCC regulator are shut down as described in Figure 28. The CLKOUT function is disabled during an overtemperature event an d will autorestar t when the device cooled down and IVCC is present again. Note: The Device will start up with a soft start routine after a overtemperature condition disappear. Figure 28 Device Overtemperat ure Protection Behavior xSGDx t LED current t ΔΤ Tj tTa TjSD TjSO t Normal OperationDevice OFF Overtemp Fault ON Overtemp Fault ON Overtemp Fault ON Overtemp Fault EF1, EF2 and IVCC

Datasheet 42 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Protection and Diagnostic Functions

10.7 Electrical Characteristics

Note: Integrated protection function s are designed to prevent IC destruction under fault conditions described in the datasheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Table 10 EC Protection and Diagnosis VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Short Circuit Protection Short to GND threshold V Temperature Protection: Over Temperature Shutdown Tj,SD 160 175 190 °C 1) 1) Specified by design; not subject to production test. P_10.8.4 Over Temperature Shutdown Hysteresis Tj,SD,hyst –1 0 – ° C 1) P_10.8.5 Overvoltage Protection: VFB Over Voltage Feedback Threshold Output Over Voltage Feedback Hysteresis VVFB_OVTH, HYS 25 40 58 mV Output Voltage decreasing; P_10.8.7 Open Load and Open Feedback Diagnostics Open Load rising Threshold Open Load reference Voltage VFBH-FBL VFBH_FBL_O L – 15 22.5 mV VFB = 1.4 V; P_10.8.10 Open Load falling Threshold Input Overvoltage protection Input Overvoltage rising Threshold VINOVLOth 1.9 2 2.1 V – P_10.8.12 Input Overvoltage Threshold Hysteresis VINOVLO(hys 18 40 62 mV – P_10.8.13 Error Flags EF1,2 Pin Output Impedance REF12 –2 . 1 – k Ω 1)Fault Condition I=100uA P_10.8.14

Datasheet 43 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Infineon FLAT SPECTRUM Feature set

11 Infineon FLAT SPECTRUM Feature set

11.1 Description

The Infineon FLAT SPECTRUM feature set has the target to minimize external additional filter circuits. The goal is to provide several beneficial concepts to provide easy adjustments for EMC improvements after the layout is already done and the HW designed.

11.2 Synchronization Function

The TLD5190 features a SYNC input pin which can be us e d b y a µ C p i n t o d e f i n e a n o s c i l l a t o r s w i t c h i n g frequency. The µC is responsible to synchronize with various devices by applying appropriate SYNC signals to the dedicated DC/DC devices in the system. Refer to Figure 29 Note: The Synchronization function can not be used when the Spread Spectrum is active. Figure 29 Synchronization Overview

11.3 CLKOUT Function

The CLKOUT pin provides an in-phase clock signal provided by the internal oscillator. This signal can be used to synchronize two devices for extending output power capability. H-Bridge DCDC MASTER INPUT µC SYNC LOGIC BUCK- BOOST GATE CONTROL SYNC1 e.g. 400kHz Phaseshift A defined phase shift between Outputs of different devices H-Bridge DCDC Slave SYNC LOGIC BUCK- BOOST GATE CONTROL SYNC2 e.g. 400kHz Phaseshift B

Datasheet 44 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Infineon FLAT SPECTRUM Feature set Figure 30 CLKOUT Overview CLKOUT DCDC MASTER OUTPUT INPUT LOGIC BUCK- BOOST GATE CONTROL DCDC Slave SYNC LOGIC BUCK- BOOST GATE CONTROL

Datasheet 45 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Infineon FLAT SPECTRUM Feature set

11.4 Spread Spectrum

The Spread Spectrum modulation technique significantly improves the lower fr equency range of the spectrum (f < 30 MHz). By using the spread spectrum technique, it is possible to optimize the input filter only for the peak limits, and also pass the average limits (average emission limits are -20dB lower than the peak emission limits). By using spread spectrum, the need for low ESR input capacitors is relaxed because the input capacitor series resistor is important for the low frequency filt er characteristic. This can be an ec onomic benefit if there is a strong requirement for average limits. The TLD5190 features a built in Spread Spectrum fu nction which can be enab led via an external Pin (SPREAD_SPECTRUM = HIGH). The modulation frequency fFM, P_11.6.3 and the deviation frequency fdev, P_11.6.2 are internally fixed. Refer to Figure 31 for more details. Note: The Spread Spectrum function can not be used when the synchronization pin is used. Figure 31 Spread Spectrum Overview fSW tfdev FMf

Datasheet 46 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Infineon FLAT SPECTRUM Feature set

11.5 EMC optimized schematic

Figure 32 below displays the Application circuit with additional external components for improved EMC behavior. Figure 32 Application Drawing Incl uding Additional Components for an Improved EMC Behavior Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. VIN COMP IIN2 IIN1 SYNC VIN AGND PWMI LOUT COUT IVCC BST1 BST2 HSGD1 LSGD 1 SWN1 LSGD2 HSGD2 SWN2 FBH FBL SWCS SGND PGND1 CIVCC RSWCS CBST1 CBST2 D1 D2 M2 M3 RFB CIN2 RCOMPCCOMP RIIN Digital dimminig µC SYNC signal CIN1 EN/INUVLO 4LED in series / Alternative external VREG supply INOVLO SOFT_START CSOFT_START PGND2 VSS RVFBH RVFBL VFB FREQ RFREQ Rfilter Cfilter IVCC_EXT IINMON IOUTMONAdvanced monitoring via µC LPI CPI1 CPI2 CPI4CPI3 DHSG1 DLSG1 DLSG2 DHSG2 RHSG1 RLSG1 RLSG2 RHSG2 DVS RM1 CM1 RM4 CM4 RM2 CM2 RM3 CM3 CFBL CFBHCFBH-FBL VREF SET EF1 EF2 CLKOUT CREF Analog dimminig SYNC of other DCDC Errorflag monitoring Spread SpectrumSpread Spectrum ON /OFF LPO CPO1 CPO2 CPO4CPO3

Datasheet 47 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Infineon FLAT SPECTRUM Feature set

11.6 Electrical Characteristics

Table 11 EC Spread Spectrum VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Spread Spectrum Parameters Frequency Deviation f dev – ±16 – % 1) SPREAD_SPECT RUM = HIGH;; 1) Specified by design; not subject to production test. P_11.6.2 Frequency Modulation fFM –1 2 –k H z 1) SPREAD_SPECT RUM = HIGH; P_11.6.3 Input Characteristics (SPREAD_SPECTRUM) SPREAD_SPECTRUM Turn On Threshold VSPREAD_SPECT RUM,ON 2––V – P_11.6.5 SPREAD_SPECTRUM Turn Off Threshold VSPREAD_SPECT RUM,OFF SPREAD_SPECTRUM High Input Current ISPREAD_SPECT RUM,H 15 30 45 µA VSPREAD_SPECTRUM = 2.0 V; P_11.6.8 SPREAD_SPECTRUM Low Input Current ISPREAD_SPECT RUM,L 6 1 21 8µ A VSPREAD_SPECTRUM = 0.8 V; P_11.6.9 Output Characteristics (CLKOUT) L level output voltage VCLKOUT(L) 0–0 . 4 V ICLKOUT = -2 mA; P_11.6.10 H level output voltage VCLKOUT(H) VIVCC - 0.4 V – VIVCC V ICLKOUT = 2 mA; P_11.6.11

Datasheet 48 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller

Application Information

Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. Figure 33 Application Drawing - TLD5190 as current regulator Table 12 BOM - TLD5190 as current regulator ( IOUT = 1 A, fSW = 300 kHz) Reference Designator Value Manufacturer Part Number Type D1 , D2 BAT46WJ -- BAT46WJ Diode CIN1 1 µF, 100 V TDK X7R Capacitor CIN2 4.7 µF, 100 V TDK X7R Capacitor Cfilter 470 nF, 6.3 V TDK X7R Capacitor CCOMP 22 nF, 16 V TDK X7R Capacitor CSOFT_START 22 nF, 16 V TDK X7R Capacitor COUT1 4.7 µF, 100 V TDK X7R Capacitor COUT2 , COUT3 , CREF 100 nF, 100 V TDK X7R Capacitor CIV 10 µF , 10 V TDK X7R Capacitor CBST1 , CBST2 100 nF, 16 V TDK X7R Capacitor IC1 -- Infineon TLD5190 IC LOUT 10 µH Coilcraft XAL1010-103MEC Inductor Rfilter 50 Ω, 1% Panasonic -- Resistor RFB 0.150 Ω, 1% Panasonic -- Resistor RIN 0.003 Ω, 1% Panasonic -- Resistor VIN VREF SET EF1 EF2 CLKOUT COMP IIN2 IIN1 SYNC VIN AGND PWMI LOUT IVCC BST1 BST2 HSGD1 LSGD1 SWN1 LSGD2 HSGD2 SWN2 FBH FBL SWCS SGND PGND1 CIVCC CBST1 CBST2 D1 D2 M2 M3 CIN2 CCOMP Digital dimminig µC SYNC signal CIN1 EN/INUVLO Alternative external VREG supply INOVLO SOFT_START CSOFT_START PGND2 VSS VFB FREQ Cfilter IVCC_ext IINMON IOUTMONAdvanced monitoring CREF Analog dimminig SYNC of other DCDC Errorflag monitoring Spread_spectrumSpread Spectrum ON/OFF COUT1 High Power LED Load RFB RVFBHRVFB L COUT2 COUT3 IVCC_ext RPWMI RSE NSE RSE NSE RSET RCOMP RFREQ Rfilter RIIN R1R2R3 REF2 REF1 RSWCS RSY NC

Datasheet 49 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Figure 34 Application Drawing - TL D5190 as 10V voltage regulator R1 , R2 , R3 , REN , RPWMI , RSense1 , RSense2 , RSYNC , REF1 , REF2 , RSET XX kΩ, 1% Panasonic -- Resistor RVFBL , RVFBH 1.5 kΩ, 56 kΩ, 1% Panasonic -- Resistor RCOMP 0 Ω Panasonic -- Resistor RFREQ 37.4 kΩ, 1% Panasonic -- Resistor RSWCS 0.005 Ω, 1% Panasonic ERJB1CFRO5U Resistor M1 , M2 , M3 , M4 Dual MOSFET:

100 V / 35 mΩ, N-ch

Infineon IPG20N10S4L-35 Transistor Table 13 BOM - TLD5190 as voltage regulator ( IOUT = 1 A, fSW = 300 kHz) Reference Designator Value Manufacturer Part Number Type D1 , D2 BAT46WJ -- BAT46WJ Diode CIN1 1 µF, 100 V TDK X7R Capacitor CIN2 4.7 µF, 100 V TDK X7R Capacitor Cfilter 470 nF, 6.3 V TDK X7R Capacitor CCOMP 22 nF, 16 V TDK X7R Capacitor CFF 10 nF, 50 V TDK X7R Capacitor CSOFT_START 22 nF, 16 V TDK X7R Capacitor COUT1 4.7 µF, 100 V TDK X7R Capacitor Table 12 BOM - TLD5190 as current regulator ( IOUT = 1 A, fSW = 300 kHz) Reference Designator Value Manufacturer Part Number Type VIN VREF SET EF1 EF2 CLKOUT COMP IIN2 IIN1 SYNC VIN AGND PWMI LOUT IVCC BST1 BST2 HSGD1 LSGD1 SWN1 LSGD2 HSGD2 SWN2 FBH FBL SWCS SGND PGND1 CIVCC CBST1 CBST2 D1 D2 M2 M3 CIN2 CCOMP µC SYNC signal CIN1 EN/INUVLO Alternative external VREG supply INOVLO SS CSS PGND2 VSS VFB FREQ Cfilter IVCC_ext IINMON IOUTMON SYNC of other DCDC Spread_spectrumSpread Spectrum ON/OFF COUT1 RVFB HRVFB L COUT2 RFB2RFB3 VOUT COUT3 Digital dimminig Advanced monitoring CREF Analog dimminig Errorflag monitoring IVCC_ext RPW MI RSE NSE RSE NSE RSET RCOMP RFREQ Rfilter RIIN R1R2R3 REF2 REF1 RSYNC RSW CS RFF CFF

Datasheet 50 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller COUT2 , COUT3 , CREF 100 nF, 100 V TDK X7R Capacitor CIVCC 10 µF , 10 V TDK X7R Capacitor CBST1 , CBST2 100 nF, 16 V TDK X7R Capacitor IC1 -- Infineon TLD5190 IC LOUT 10 µH Coilcraft XAL1010-103MEC Inductor Rfilter 50 Ω, 1% Panasonic -- Resistor RFB2 , RFB3 150Ω, 10.1kΩ, 1% Panasonic -- Resistor RFF 1.5 kΩ, 1% Panasonic -- Resistor RIN 0.003 Ω, 1% Panasonic -- Resistor R1 , R2 , R3 , REN , RPWMI , RSense1 , RSense2 , RSYNC , REF1 , REF2 , RSET XX kΩ, 1% Panasonic -- Resistor RVFBL , RVFBH 1.5 kΩ, 56 kΩ, 1% Panasonic -- Resistor RCOMP 0 Ω Panasonic -- Resistor RFREQ 37.4 kΩ, 1% Panasonic -- Resistor RSWCS 0.005 Ω, 1% Panasonic ERJB1CFRO5U Resistor M1 , M2 , M3 , M4 Dual MOSFET: Infineon IPG20N10S4L-35 Transistor Table 13 BOM - TLD5190 as voltage regulator ( IOUT = 1 A, fSW = 300 kHz) Reference Designator Value Manufacturer Part Number Type

Datasheet 51 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller

12.1 Further Application Information

Typical Performance Characteristics of Device Figure 35 Characterization Diagrams 1 0,5 1,5 2,5 0 1 02 03 04 05 0 VIN/g882VIVCC [V] LDO/g3current/g3[mA] IVCC/g3Dropout/g3vs/g3Current/g3 Tj=/g88240°C Tj=150°C Tj=25°C 4,80 4,85 4,90 4,95 5,00 5,05 5,10 5,15 5,20 /g88240 10 60 110 VIVCC [V] Temperature/g3[°C] IVCC/g3Voltage/g3vs/g3Temperature 4,8 4,85 4,9 4,95 5,05 5,1 5,15 5,2 0 1 02 03 04 05 0 VIVCC [V] IIVCC[mA] IVCC/g3Load/g3regulation/g3 IIVCC=10mA 146 147 148 149 150 151 152 153 154 0 1 02 03 04 05 06 0 V(FBH/g882FBL)/g3[mV] VFBH/g3[V] V(FBH/g882FBL)/g3Threshold/g3vs/g3VFBH Analog/g3Dim./g3=/g3100% 1,36 1,37 1,38 1,39 1,4 1,41 1,42 1,43 1,44 /g88240 10 60 110 VIOUTMON [V] Temperature/g3[°C] IOUTMON/g3Voltage/g3vs/g3Temp V(FBH/g882FBL)=/g3/g3150mV 146 147 148 149 150 151 152 153 154 /g88240 10 60 110 V(FBH/g882FBL)/g3[mV] Temperature/g3[°C] V(FBH/g882FBL)/g3Threshold/g3vs/g3Temp Analog/g3Dim.=100%,/g3FBH=0,15V Analog/g3Dim.=100%,/g3FBH=12V Analog/g3Dim.=100%,/g3FBH=60V TJ/g3=/g325°C,/g3VIN=12V/g3unless/g3otherwise/g3specified

Datasheet 52 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Figure 36 Characterization Diagrams 2 0,2 0,4 0,6 0,8 1,2 1,4 0 2 04 06 08 0 1 0 0 1 2 0 1 4 0 VIOUTMON [V] V(FBH/g882FBL)[mV] IOUTMON/g3Voltage/g3vs/g3V(FBH/g882FBL) VIN =/g312V/g3 IVCC=10mA VIN =/g312V/g3 V(FBH/g882FBL)=/g3/g3150mV 100 200 300 400 500 600 700 800 /g88240 10 60 110 fSW [kHz] Temperature/g3[°C] Oscillator/g3Frequency/g3vs/g3Temp R_FREQ=61.9/g3kOhm R_FREQ=37.4/g3kOhm R_FREQ=12.7/g3kOhm /g88240 10 60 110 V(IIN1/g882IIN12[mV] Temperature/g3[°C] V(IIN1/g882IIN2)/g3Threshold/g3vs/g3Temp VIIN1=8V VIIN1=13.5V VIIN1=55V 0,96 0,97 0,98 0,99 1,01 1,02 1,03 1,04 /g88240 10 60 110 VIINMON [V] Temperature/g3[°C] IINMON/g3Voltage/g3vs/g3Temp V(IIN1/g882IIN2)/g3=/g350mV 3,1 3,2 3,3 3,4 3,5 3,6 3,7 3,8 3,9 /g88240 10 60 110 V(SBTx/g882SWNx)[V] Temperature/g3[°C] V(BSTx/g882SWNx)/g3vs/g3Temp VBSTx/g882VSWNx_dec/g3[V] VBSTx/g882VSWNx_inc/g3[V] TJ/g3=/g325°C,/g3VIN=12V/g3unless/g3otherwise/g3specified /g88240 /g88220 100 120 0 5 10 15 20 25 30 35 40 45 50 55 60 IFBH [uA],/g3IFBL [uA] VFBH/g3[V] IFBH ,/g3IFBL vs/g3VFBH I_FBL/g3[uA] I_FBH/g3[uA] V(FBH/g882FBL)=/g3/g3150mV

Datasheet 53 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Figure 37 Characterization Diagrams 3

• For further information you may contact http://www.infineon.com/ 1,96 1,97 1,98 1,99 2,01 2,02 2,03 2,04 -40 10 60 110 VREF [V] Temperature [°C] VREF Voltage vs Temperature VIN=8V VIN=13.5V VIN=40V 1,94 1,96 1,98 2,02 2,04 2,06 05 0 1 0 0 1 5 0 2 0 0 VREF [V] IREF [uA] VREF Load Regulation Iref = 100uA TJ = 25°C, VIN=12V unless otherwise specified 0,5 1,5 2,5 3,5 4,5 -40 10 60 110 LSGDx [Ohm] Temperature [°C] LSGDx on-state resistance vs Temp LSGDx_Pull-Up LSGDx_Pull-down 0,5 1,5 2,5 3,5 4,5 -40 10 60 110 HSGDx [Ohm] Temperature [°C] HSGDx on resistance vs Temp HSGDx_Pull-up HSGDx_Pull-down 100 120 0,6 0,8 1 1,2 1,4 1,6 Duty Cycle [%] VCOMP [V] VCOMP Voltage vs LSGD Duty Cycle LSGD1_Buck [%] LSGD2_Boost [%] -60 -40 -20 -40 10 60 110 V(SWCS-SGND) [mV] Temperature [°C] V(SWCS-SGND) Treshold vs Temp Boost Buck V(SWCS-SGND) =0 fsw=300kHz

Datasheet 54 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Package Outlines Figure 38 PG-VQFN-48-31 (with LTI) PG-VQFN-48-29, -31-PO V05 7±0.1 A6.8 7±0.1 B 11 x 0.5 = 5.5 0.5 0.5±0.07 0.1±0.05 0.13 ±0.05 0.26 0.15±0.05 (6) (5.2) 0.9 MAX. (0.65) +0.03 48x 0.08 (0.2) 0.05 MAX.C (5.2) (6) 0.1±0.03 ±0.050.23 M 48x

0.1 A B C

1) Vertical burr 0.03 max., all sides 2) These four metal areas have exposed diepad potential Index Marking SEATING PLANE Index Marking 6.8 12 1 25 36 (0.35) 0.4 x 45°

Datasheet 55 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Package Outlines Figure 39 PG-TQFP-48-9 Green Product (RoHS compliant) To meet the world-wide customer requirements for en vironmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). 2)EXPOSEDPADFORSOLDERINGPURPOSE 1)DOESNOTINCLUDEPLASTICORMETALPROTRUSIONOF 0.25MAX.PERSIDE 1±0.05 1.2MAX. C SEATING

0.08 C 48x

0.5

0.08 A-B D C 48x

H 0.6±0.15 0.125 +0.075 -0.035 0.25 GAUGE PLANE D BA 48x0.2 A-B D

0.2 A-B D H 4x

0°..7° 0.1±0.05 STAND OFF 0.22±0.05 For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Dimensions in mm

Datasheet 56 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller

Revision History

Rev. 1.0 2016-05-20 Released Datasheet Rev. 1.1 2018-02-08 Added: CCM on regulator description Chapter 6.1 Rev. 1.1 2018-02-08 Added TQFP package Rev. 1.1 2018-02-08 Corrected graph V COMP vs DUTY Rev. 1.1 2018-02-08 Corrected soft start behavior Chapter 6.2 “if an open load” Rev. 1.1 2018-02-08 Removed “F lex” from Family name. Chapter 1 Rev. 1.1 2018-02-08 Specified Comp lessive gain of error amp Chapter 6.1 Rev. 1.1 2018-02-08 Improved description of soft start Chapter 6.2 Rev. 1.1 2018-02-08 Added Soft Start mask in the Short circuit description Chapter 10.2 Rev. 1.1 2018-02-08 Added input current limiter description Chapter 10.4

Datasheet 57 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller Table of Content

Datasheet 58 Rev. 1.1 2018-02-08 TLD5190 H-Bridge DC/DC Controller

Trademarks of Infineon Technologies AG µHVIC™, µIPM™, µPFC™, AU-ConvertIR™, AURIX™ , C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP ™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™, CoolSiC™, DAVE™, DI-POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, Ec onoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, Ga NpowIR™, HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LI TIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, O PTIGA™, OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PR OFET™, PRO-SIL™, RASIC™, REAL 3™, SmartLEWIS™, SOLID FLAS H™, SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™. Trademarks updated November 2015 Other Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2018-02-08 Published by Infineon Technologies AG

81726 Munich, Germany

© 2018 Infineon Technologies AG. All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com Document reference (doc_number) IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer's comp liance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer's products and any use of the product of Infineon Technologies in customer's applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer's technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. Please read the Important Notice and Warnings at the end of this document