TL7231MD SAMSUNG | Alldatasheet
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FULL LAYER - III ISO/IEC 11172 - 3 AUDIO DECODER n Single - chip ISO/IEC 11172 - 3 Layer III Audio Decoder n Supports All MPEG Bit Rates Including Free Format n Supports 32/44.1/48KHz Sampling Frequencies for MPEG Bit Stream n Supports Single Channel, Dual Channel, Ste reo, and Joint Stereo n Any Combination of Intensity Stereo and MS Stereo is supported. n Serial Bit Stream Input n 8 - bit Host Interface Port n Digital Volume Control n Digital Bass/Treble Control n 6 - Band Equalizer Function n Voice Record/Playback Capability n On - chip DAC with 1 - bit Sigma Delta Modulation n Supports Off - chip DAC Interface n On - chip ADC with 12 - bit Resolution n Power Management to Reduce Power Consumption n PLL for Internal Clocks and for Output PCM Clock Generation n Single 16.9344MHz External Clock Input n 3.0 V Operation n Small Footprint 100 - pin Thin Quad Flat Package
DESCRIPTION
TL7231MD is a single - chip ISO/IEC 11172 - 3 Layer III audio decoder, capable of decoding compressed elementary bit streams as specified in ISO/IEC standard. Since it integrated on - chip ADC and on - chip DAC, it can provide you more small and cheaper solution for MP3 player application. It is designed to be well suited for portable audio appliances. TL7231MD receives the input data bit stream through a serial data interface. The decoded si gnal is 16 - bit serial PCM format that can be sent directly to DAC. The generated PCM data can be sent to on - chip DAC or off - chip DAC according to user preference. The off - chip DAC interface is programmable to adapt the PCM output of TL7231MD to the most co mmon DACs used on the market. An 8 - bit host interface port is provided to receive control information from and send status information to host. 8 - bit microcontrollers such as those of Intel or Motorola can be connected easily. TL7231MD has the capability of compressing voice signals. It can receive voice signals through on - chip ADC. The compressed voice signals are transmitted to or received from host through serial data interface. It can also reproduce the voice signals from the compressed voice signals.
2 /37 SAMSUNG Electronics Co. Figure 1. Functional Block Diagram of TL7231MD
Figure 2. 100 - pin Thin Quad Flat Package (TQFP)
4 /37 SAMSUNG Electronics Co. Table 1. Pin Locations with Pin Names
1 DACVSSA 26 VDDIO 51 HD3 76 VSS
2 DACVDDA 27 VSSIO 52 HD4 77 VSS
3 DACVHALF 28 RESET 53 HD5 78 VSS
4 AOUTR 29 WAKEUP 54 HD6 79 VSS
5 DACVSSD 30 PWRDN 55 HD7 80 DACMSCK
6 DACVDDD 31 VSS 56 HWR# 81 DACBCK
7 ADCAIN 32 VSS 57 HRD# 82 DACLRCK
8 ADCVSSA 33 VSS 58 HSEL# 83 DACSDAT A
9 ADCVBB 34 VSS 59 HALE 84 DACDEEM
10 ADCVDDA 35 VSS 60 VDD 85 DACMUTE#
11 ADCREFN 36 VSS 61 REQSTRM 86 VSSIO
12 ADCREFP 37 VDD 62 DXRM 87 VDDIO
13 ADCVSSD 38 VSS 63 CLKXRM 88 VSS
14 ADCVDDD 39 VDDIO 64 VSSIO 89 VDD
15 PLLVDDA 40 VSSIO 65 VDDIO 90 NC
16 PLLVSSA 41 NC 66 VSS 91 NC
17 PLLVBB 42 NC 67 VDD 92 NC
18 FILTER 43 NC 68 NC 93 VSS
19 CPUXO 44 NC 69 NC 94 NC
20 CPUXI 45 VSS 70 NC 95 VSS
21 VDD 46 VSS 71 VDD 96 NC
22 VSS 47 VSS 72 VSS 97 VSS
23 BCLK 48 HD0 73 VSS 98 DACVBB
24 VDD 49 HD 1 74 VSS 99 AOUTL
25 VSS 50 HD2 75 VSS 100 DACVREF
Table 2. Pin Functions with Location
6 /37 SAMSUNG Electronics Co. Table 3. Pin Descriptions CPUXI I CPU Clock In. 16.9344MHz crystal clock input. CPUXO O CPU Clock Out. 16.9344MHz crystal clock output. between this pin and analog gro und. BCLK O Processor Clock Output. RESET I Chip Reset. Reset input to the chip. Internal pull down. the host issues next SLEEP command. Internal pull down. (Restriction: This pin should be active ONLY in SLEEP state. CLKXRM I Serial Clock. MCU serial interface clock . from negative edge of CLKXRM to next negative edge of CLKXRM. TL7231MD is set to transmit the most signifi cant bit first. data during this signal active. HSEL# I HIP Enable. When Low, HIP is selected. address, which is sampled at negative edge of this signal. should be sampled at positive edge of this signal. HD[7:0] I/O HIP Address/Data Bus. Multiplexed address lines and data lines. ADCREFN I ADC Internal Reference Bottom Bias. Connect this pin to ground.
SAMSUNG Electronics CO. 7 /37 ADCVDDA PWR ADC Supply Voltage for Analog Circuit. Connect t his pin to the +3.0V supply voltage. ADCVSSA GND ADC Ground for Analog Circuit. Connect this pin to ground. ADCVDDD PWR ADC Supply Voltage for Digital Circuit. Connect this pin to the +3.0V supply voltage. ADCVSSD GND ADC Ground for Digital Circuit. Con nect this pin to ground. ADCVBB GND ADC Analog/Digital Bulk Bias. Connect this pin to ground. External DAC Interface DACMSCK O DAC Master Clock. 384 × Fs clock. DACBCK O DAC Bit Clock. 32 × Fs clock . DACLRCK O DAC Sample Rate Clock. Fs clock. DACSDATA O DAC Serial Data. Serial data . DACDEEM O DAC Deemphasis. When deemphasis is on, this signal is high. It can be set/clear through HIP commands. DACMUTE# O DAC Mute. Analog output mute. When external DAC is set to mute on, this signal is low. It can be set /clear through HIP commands. Internal DAC Interface AOUTL O Analog Output for Left - Channel. AOUTR O Analog Output for Right - Channel. DACVHALF I/O DAC Reference Voltage Output for Bypass. DACVREF I/O DAC Reference Voltage Output for Bypass. DACVDDA P WR DAC Supply Voltage for Analog Circuit. Connect this pin to the +3.0V supply voltage. DACVSSA GND DAC Ground for Analog Circuit. Connect this pin to ground. DACVDDD PWR DAC Supply Voltage for Digital Circuit. Connect this pin to the +3.0V supply voltag e. DACVSSD GND DAC Ground for Digital Circuit. Connect this pin to ground. DACVBB GND DAC Pad Bulk Bias. Connect this pin to ground. Power/Ground Pins VDD PWR Supply Voltage. Connect this pin to the +3.0V supply voltage. VSS GND Circuit Ground. Connec t this pin to ground. VDDIO PWR Supply Voltage for I/O Buffers. Connect this pin to the +3.0V supply voltage. VSSIO GND Circuit Ground for I/O Buffers. Connect this pin to ground.
8 /37 SAMSUNG Electronics Co. signals including internal DAC/ADC clocks are generated with the input clock. Figure 3. Clock Circuit most - significant bit (MSB) first. The clock for the serial interface should be generated externally.
REQSTRM to decide whether next byte is to be transmitted or not. is operating at full speed. HIP transfers are managed using interrupt scheme. command requires parameters, user should write parameters first, and then write command. Serial ID number can be used to check whether given command has been accepted or not. revision number, not the ID number. are shown from Figure 4 to Figure 16. Table 4. Address of Host Interface Port Registers
10 /37 SAMSUNG Electronics Co. The information provided by HDO6 to HDO15 depends on the mode setting of TL7231MD. Table 5. The contents of HDO6 ~ HDO15 according to mode setting enabled, 1 is reported. Otherwise, 0 is reported.
SAMSUNG Electronics CO. 11 /37 Mode1: Tone Control – Treble Cutoff Frequency Mode2: The most recently synchronized frame header of MP3 bit stream. (Fig. 12) Mode3: 00h Mode4: EQ Control – Band3 Gain 1Bh HDO11 Mode0: 00h Mode1: Tone Control – Treble Gain Mode2: The most recently synchronized frame header of MP3 bit strea m. (Fig. 13) Mode3: 00h Mode4: EQ Control – Band4 Gain 1Ch HDO12 Mode0: 00h Mode1: 00h Mode2: The most recently synchronized frame header of MP3 bit stream. (Fig. 14) Mode3: 00h Mode4: EQ Control – Band5 Gain 1Dh HDO13 Mode0: 00h Mode1: 00h Mode2: Bass B oost Information (Fig. 15) Mode3: 00h Mode4: EQ Control – Band6 Gain 1Eh HDO14 Mode0: 00h Mode1: 00h Mode2: DAC Output Valid (Fig. 16) Mode3: 00h Mode4: 00h 1Fh HDO15 Mode0: 00h Mode1: 00h Mode2: CRC Error Count Mode3: 00h Mode4: 00h
12 /37 SAMSUNG Electronics Co. Table 6. Host Int erface Port Commands 00h None Stop Stop execution and go into WAIT state. 01h None MP3 Decoding Execute MP3 decoding. 04h None Voice Encoding Execute voice encoding (16Kbps). 05h None Voice Decoding Execute voice d ecoding (16Kbps). 06h None Voice Encoding Execute voice encoding (24Kbps). 07h None Voice Decoding Execute voice decoding (24Kbps). 08h None Voice Encoding Execute voice encoding (32Kbps). 09h None Voice Decoding Execute voice decoding (32Kbps). 0Dh N one Revision Code Report the TL7231MD revision number in HDO0. execution, TL7231MD becomes unstable. 11h None Mute OFF Mute is disabled. 12h None Internal ADC Use Internal ADC. External ADC interfaces are disabled. After reset, it is the default value. meaning of I 2 S, PL, and PB, refer to Figure 8. according to parameter of this command.
1 Tone Control Information
2 MP3 Decoding Information
3 Voice Encoding/Decoding
4 Equalizer Control Informa tion
SAMSUNG Electronics CO. 13 /37 20h 1byte Bass Boost Control (MP3 Only) Control Bass boost. The upper nibble of the parameter controls the cutoff frequency of bass boost, and the lower nibble controls the level of bass boost. The value of upper nibble should be in the rang e of 0 to 6. The cutoff frequency is 25 × upper nibble + 50 (Hz). If the values of the lower nibble is in the range of 0 to 12, the low frequency band below the cutoff frequency is boosted by 0dB ~ 18dB (1.5dB step). The other values mean no boost. Fo r example, if the parameter value is 42h, then the cutoff frequency will be 25 × 4+50=150Hz, and the frequency band below 150Hz will be boosted by 3dB compared to the upper frequency band. In case of using bass boost, volume is reduced by 1.5 × n dB where n means the parameter value. The reset value is FFh(disabled). 21h 1byte Volume Control Control volume. The parameter should have the value of range from 0 to 255. If the value is n , the volume is attenuated by n /2 dB compared to maximum volume. The reset v alue is 0. 22h 1byte Prescale Control Control the prescaling. The parameter is a signed value and can be - 128 to 127. The prescaling is done by 0.5 × n dB according to parameter value n . That is, 0h ~ 7Fh means 0dB ~ 63.5dB scaling, 80h ~ FFh means – 64dB ~ - 0.5dB scaling. The reset value is 0dB. 23h 1byte Tone Control – Bass Gain (MP3 Only) Control the Bass Gain. The parameter is a signed value and can be - 128 to 127. The gain can be 0.5 × n dB according to parameter value n . The reset value is 0. 24h 1byte Tone Control – Treble Gain (MP3 Only) Control the Treble Gain. The parameter is a signed value and can be - 128 to 127. The gain can be 0.5 × n dB according to parameter value n . The reset value is 0. 25h 1byte Tone Control – Bass Cutoff (MP3 On ly) Control the Bass Cutoff Frequency. The parameter can have the value of 0 to 255. The cutoff frequency can be 20 + 5 × n Hz according to parameter value n . The reset value is 0. 26h 1byte Tone Control – Treble Cutoff (MP3 Only) Control the Treble Cuto ff Frequency. The parameter can have the value of 0 to 255. The cutoff frequency can be 5000 + 20 × n Hz according to parameter value n . The reset value is 0. 27h none Tone Control – Enable (MP3 Only) Enable the Tone Control Function. Tone Control Function is disabled when reset. 28h none Tone Control – Disable (MP3 Only) Disable the Tone Control Function. Tone Control Function is disabled when reset. 30h none MP3 CRC Bypass (MP3 Only) During MP3 decoding, even if the input bit stream contai ns the CRC field, TL7231MD doesn’t check the CRC error. After reset, TL7231MD is set to check CRC error.
14 /37 SAMSUNG Electronics Co. 31h none MP3 CRC Check During MP3 decoding, if the input bit stream contains the CRC field, check the CRC error. If an error occurs , TL7231MD outputs 0 during the period of corresponding MP3 frame. The reset value is MP3 CRC check. 40h 1byte EQ Control – Band1 Gain (MP3 Only) Control the gain of Band1(<30Hz) of 6 - band equalizer. The parameter is a signed value and can be - 128 to 127. The gain can be 0.5 × n dB according to parameter value n . The reset value is 0dB. 41h 1byte EQ Control – Band2 Gain (MP3 Only) Control the gain of Band2(30Hz~125Hz) of 6 - band equalizer. The parameter is a signed value and can be - 128 to 127. The gain can be 0.5 × n dB according to parameter value n . The reset value is 0dB. 42h 1byte EQ Control – Band3 Gain (MP3 Only) Control the gain of Band3(125Hz~500Hz) of 6 - band equalizer. The parameter is a signed value and can be - 128 to 127. The gain can be 0.5 × n dB accordin g to parameter value n . The reset value is 0dB. 43h 1byte EQ Control – Band4 Gain (MP3 Only) Control the gain of Band4(500Hz~2KHz) of 6 - band equalizer. The parameter is a signed value and can be - 128 to 127. The gain can be 0.5 × n dB according to param eter value n . The reset value is 0dB. 44h 1byte EQ Control – Band5 Gain (MP3 Only) Control the gain of Band5(2KHz~8KHz) of 6 - band equalizer. The parameter is a signed value and can be - 128 to 127. The gain can be 0.5 × n dB according to parameter value n . The reset value is 0dB. 45h 1byte EQ Control – Band6 Gain (MP3 Only) Control the gain of Band6(>8KHz) of 6 - band equalizer. The parameter is a signed value and can be - 128 to 127. The gain can be 0.5 × n dB according to parameter value n . The reset va lue is 0dB. 46h none EQ Control – Enable (MP3 Only) Enable the Equalizer Function. The equalizer function is disabled after reset. 47h none EQ Control – Disable (MP3 Only) Disable the Equalizer Function. The equalizer function is disabled a fter reset. 8xh None External DAC Format2 Same as External DAC Format command. Parameter values are located at lower nibble of the command. The command should be the form of {1, 0, 0, 0, 0, I 2 S, PL, PB}.
SAMSUNG Electronics CO. 15 /37 Bass boost control command(20h) is another form of tone control command(23h ~28h). It is implemented by using the same filter as tone control command. Thus, if bass boost control command is received with valid parameter value, gains and cutoffs are changed as follows; l Bass gain and cutoff frequency of tone control are changed according to the parameter value. l Treble gain is changed to 0. l Prescaling is set to – 12dB to remove clipping noise. l Tone control is enabled. If bass boost command is received with invalid parameter value, the gains and cutoff fre quencies are not changed, and tone control is disabled. If a command related to tone control is received, only the related gain or cutoff frequency is changed, and the command has no effect on the tone control enable/disable and prescaling, and the informa tion of bass boost which is reported through HDO13 is not changed. For the tone control enable command(27h), it just enables the tone control function, and has no effect on the gains and cutoff frequencies. Tone control disable command(28h) disable tone co ntrol function, and change the bass boost status which is reported through HDO13 to FFh(disable). Prescaling has effect when tone control or equalizer is enabled or bass boost command is received. Equalizer consists of 6 bands, and band1 and band6 are sh elving type, band2 to band5 are peaking type. Since each band has relatively small Q value, correction matrix is automatically used to complement this small Q value whenever attenuation value is set by using EQ gain control commands(40h ~ 45h). It is not r ecommended that gain difference of neighbor bands exceeds 10dB.
16 /37 SAMSUNG Electronics Co.
3 S3 When set, it means that host wrote parameter to HDI3
register, but it isn ’ t read by TL7231MD.
2 S2 When set, it means that host wrote parameter to HDI2
register, but it isn ’ t read by TL7231MD.
1 S1 When set, it means that host wrote command ID to HDI1
register, but it isn ’ t read by TL7231MD.
0 S0 When set, it means that host wrote command to HDI0
register, but it isn ’ t read by TL7231MD. Figure 4. HDI Status Reported through HSR4 Figure 5. Command ID reported through HDO0
Figure 6. TL7231MD Status reported through HDO1
18 /37 SAMSUNG Electronics Co.
3 DE Deemphasis Enable:
When set, deemphasis is enabled. Reset value is 0.
2 MU# Mute Enable:
When cleared, mute is on. Reset value is 0. Figure 7. I/O Status r eported through HDO2
4 I2S I2 S Format Enable:
PCM format. Reset value is 0.
3 PL Pol arity of DACLRCK:
4 PB Polarity of DACBCK:
1 EDAC External DAC Enable:
When set, external DAC is used. Reset value is 0.
0 EADC External ADC Enable:
When set, external ADC is used. Reset value is 0. Figure 8. I/O Status reported through HDO3 7:0 Volume The value can be 0 to 200. Figure 9. Volume reported throug h HDO4
3 ID 0: Reserved
TL7231MD decodes only layer3 bit stream.
0 PT Protection Bit:
Figure 12. Frame Header reported through HDO10 when mode is 2.
22 /37 SAMSUNG Electronics Co.
1 PD Padding Bit
0 PR Private Bit
Figure 13. Frame Header reported through HDO11 when mode is 2.
3 CR Copyright:
2 OC Original/Copy:
is needed without relation to deemphasis type. Figure 14. Frame Header reported through HDO12 when mode is 2.
24 /37 SAMSUNG Electronics Co. The value can be in the range of 0 to 6. Figure 15. Bass Boost Information reported through HDO13 when mode is 2.
0 Valid DAC Outp ut Valid:
Figure 16. DAC Output Status reported through HDO14
SAMSUNG Electronics CO. 25 /37 DAC DAC of TL7231MD employs the 1 - bit 4 th - order sigma - delta architecture with 16 - bit resolution, over - sampling of 64X. Ana log post - filter with low clock sensitivity and linear phase can filter out the shaping - noise and output analog voltage with high resolution. The characteristic of Internal DAC is shown Table 7. Table 7 . Characteristics of Internal DAC PARAMETER MIN TYP MA X UNITS Resolution 16 bits SNR 79.7 dB THD 84.9 dB SNDR 78.5 dB Reference Voltage Output (DACVREF) 0.5 × DACVDDA V Frequency Response ± 0.1 ± 0.5 dB Analog Output Voltage Range 0.5 × DACVDDA Vpp Load Impedance 10K Ω Digital Filter P ass Band Ripple ± 0.0072 dB Stop and Attenuation 62.7 dB Pass Band 0.45 Fs (DACVDDD/DACVDDA=3.0V, Temp=25 °C, Fs=44.1KHz, Signal Freq.=20~20KHz, C load of AOUTL/AOUTR = 10pF) With TL7231MD, user can configure whether the internal DAC is used or no t. The configuration of DAC can be achieved through HIP commands shown in Table 5. When using internal DAC, the following circuit in Figure 17 is recommended.
26 /37 SAMSUNG Electronics Co. Figure 17. Reference Circuit when using internal DAC
28 /37 SAMSUNG Electronics Co. ADCREFP to ADCREFN. This ADCAIN voltage follows reference voltage range fundamentally. So, if user wants to alter the input range, the voltage value of ADCREFP should be changed. But ADCREFP should be greater than 2.0V. The characteristic of internal ADC is shown Table 8. Figure 19. Reference Circuit when using internal ADC With TL7231MD, the follow ing circuit in Figure 19 is recommended to use internal ADC.
and transmitted to host MCU through the serial port. transmitted from host MCU through the serial interface. Table 9 is the summary of the relation between compression modes and code size. Table 9. Summary of Three Voic e Compression Modes High Quality (32Kbps) 4 140 min. Medium Quality (24Kbps) 3 186 min. Low Quality (16Kbps) 2 280 min.
30 /37 SAMSUNG Electronics Co. Lower Power Operation TL7231MD has low - power feature t hat makes the processor get into very low - power dormant states through hardware or software control. The power saving scheme is explained with the state diagram of TL7231MD shown in Figure 20. RUN In this state, TL7231MD decodes MP3 or compressed voice bi t stream, or encodes voice signal. Also in this state it can process other HIP commands such as 20h and 21h. HIP command 01h, 04h through 09h, and 0Fh should not be used in this state. TL7231MD consumes normal power at this state, It processes all internal functions and drives external pads. It can transit to WAIT state with HIP command 00h. When there is no job left or it waits available data, power consumption is reduced as that of WAIT state. WAIT When RESET signal becomes active, TL7231MD goes into WA IT state. There it can transit to RUN, or SLEEP state. When TL7231MD is in this state, it is ready to receive any HIP commands from host. It can go into RUN state when it receives HIP commands such as 01h, 04h though 09h. Also it can process other HIP comm ands such as volume control (21h) etc. in this state. TL7231MD goes into this state through HIP command 00h from RUN state. When TL7231MD is in this state, only peripheral interface block consumes power. That is, internally generated peripheral clock is ac tive but clock for the DSP core logic is not. When it receives HIP command 0Fh, it goes into SLEEP state in which more power is saved. SLEEP In SLEEP state, only internal analog blocks such as PLL, ADC and DAC of TL7231MD consume power. In this state, int ernal ADC and DAC are disabled. But PLL consumes normal operation power. In this state, TL7231MD can transit to PWRDOWN state when external PWRDN pin becomes active. Active WAKEUP signal changes its state from SLEEP to WAIT. PWRDOWN When TL7231MD is in S LEEP state and PWRDN signal becomes active, it transits to PWRDOWN. To make TL7231MD stay in this state, the external PWRDN signal keep its active state. When the PWRDN signal becomes inactive, TL7231MD exits from this PWRDOWN state, and then goes into SLE EP state. When it changes its state from PWRDOWN to SLEEP, this state should not be changed during minimum 150 µs until internal PLL is stabilized. TL7231MD consumes the minimum power at this state because all internal logic blocks and analog blocks are power - downed.
Figure 20. Decoder States and Power Management
32 /37 SAMSUNG Electronics Co. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (See Notes) † Symbol Parameter Rating Unit V DD DC Supply Voltage - 0.3 to 3.8 V V IN DC Input Voltage - 0.3 to 5.5 V IIN DC Input Current ± 10 mA T STG Storage Temperature - 40 to 125 ° C † Stresses beyond those listed under “ ab solute maximum rating s” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “ DC ELECTRICAL CHARACTERISTICS ” is not implied. Exposure to absolute - maximum - ra ted conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to V SS . NOTE 2: This value was obtained under specially produced worst - case test conditions for the TL7231MD , which are not sustained during nor mal device operation. DC ELECTRICAL CHARACTERISTICS (Note3) † Symbol Parameter MIN TYP MAX UNIT V DD Supply voltage 2.7 3.0 3.3 V V SS Supply voltage 0 V V IH High level input voltage 1.8 V DD +0.3 V V IL Low level input voltage - 0.3 0.6 V V OH High le vel output voltage 2 V V OL Low level output voltage 0.4 V IIH High level input leakage current without internal pull - up - 10 +10 µA IIL Low level input leakage current without internal pull - up - 10 +10 µA IRN Supply current in RUN state 61 mA IW T Supply current in WAIT state 26 mA ISL Supply current in SLEEP 12 mA IPD Supply current in PWRDOWN state 250 µA C IN Input capacitance 4 pF C OUT Output capacitance 4 pF T A Air temperature - 40 85 ° C V CPUXI High level input voltage for CPUXI 2.5 V DD +0.3 V † For TL7231MD , all typical values are at V DD = 3.0 V, T A (air temperature) = 25° C . N OTE 3: All vol tage values are with respect to V SS . All input and output voltage levels are TTL - compatible. CLKIN can be driven by CMOS clock. NOTICE: This document contains information on products in the sampling and initial production phases of development. The speci fications are subject to change without notice.
Figure 21 correspond to each number in the first column of the table.
5 T REQ Request check time, falling edge of CLKXRM
Figure 21. Timing for Serial Port in case of LSB - First Mode
34 /37 SAMSUNG Electronics Co. Host interface Port The following table defines the timing parameters for the Host Interface Port I/O pins. The numbers shown in Figure 22 correspond to each number in the first column of the table. NO. Symbol Description MIN MAX Unit 6 T HAW HALE pulse width 2.0 ns 7 T HDSU Setup time, HD address setup before HALE low 2.0 ns 8 T HDH Hold time, HD address hold after HALE low 0.8 ns 9 T HAS Start of write or read after HALE low 0.0 ns 10 T HDSU Setup time, HD data setup before end of write 0.7 ns 11 T HDH Hold time, HD data hold after end of write 2.2 ns 12 T HRW Read or write pulse width 36.2 ns 13 T HDE HD data enabled after start of read 7.8 ns 14 T HDD HD data valid after start of read 7.9 ns 15 T HRDH HD data hold after end of read 3.7 7.8 ns 16 T HRDD HD data disabled after end of read 4.2 7.9 ns
Figure 22. Timing for Host Interface Port pins
36 /37 SAMSUNG Electronics Co. PACKAGE DIMENSION
SAMSUNG Electronics CO. 37 /37 The reproduction of this datasheet is NOT allowed without approval of SEC. All in formation and data contained in this datasheet are subject to change without notice. This publication supersedes and replaces all information previously supplied. SEC has no responsibility to the consequence of using the patents described in this document. © 1999 SAMSUNG Electronics Co., – All Rights Reserved