TL3828AE10T80R

TL3828AE10T80R TELINK | Alldatasheet

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Technical content

Ver 0.8.0 2026/03/13 Keyword Two Powerful 32-bit RISC-V MCUs, 256 KB SRAM, 1536 K B Embedded NVM, Flexible IO Interfaces, Standard and Advanced Communication Interfaces Brief This datasheet is dedicated for Telink wired SoC TL3828. In this datasheet, function block diagram, key features, electrical specifications, and typical applications of the TL3828 are introduced.

Datasheet for Telink TL3828 DS-TL3828-E5 1 Ver 0.8.0 Published by Telink Semiconductor 10-11/F, Building 1, 61 Shengxia Road, Pudong District, Shanghai, China 201203 © Telink Semiconductor All Rights Reserved Legal Disclaimer This document is provided as-is. Telink Semiconductor reserves the right to make improvements without further notice to this document or any products herein. This document may contain technical inaccuracies or typographical errors. Teli nk Semiconductor disclaims any and all liability for any errors, inaccuracies or incompleteness contained herein. Copyright © 2026 Telink Semiconductor (Shanghai) Co., Ltd. Information For further information on the technology, product and business term, please contact Telink Semiconductor Company (www.telink-semi.com). For sales or technical support, please send email to the address of: telinksales@telink-semi.com telinksupport@telink-semi.com

Datasheet for Telink TL3828 DS-TL3828-E5 2 Ver 0.8.0

Revision History

Version Change Description

0.5.0 Preliminary release

0.5.1

• Section 1.4 Ordering Information: Added the number of ADC channels in the footnote
• Section 1.6 Pin Layout: Added CTB input signal description in the GPIO pin mux function tables
• Section 2.4 AC Characteristics: Updated the frequency tolerance of 32 kHz RC to 0.5% in Table 2-7
• Section 4.4 Working Mode: Added shutdown mode in Table 4-11
• Section 11.1.3 Drive Strength: Added this section to introduce the pin’s driving strength and slew rate
• Section 11.1.4 GPIO Logic Introduction: Updated the introduction of GPIO logic
• Chapter 13 Telink Rapid Keyscan Handler (TRKH): Updated the introduction of TRKH
• Chapter 15 SD ADC: Updated the SD ADC modes
• Section 17.3 Select Mode and Input Channel for Reference: Updated the configuration of the normal and low power modes
• Chapter 18 Security Solution: Updated the introduction of security 0.5.2
• Section 1.6 Pin Layout: Updated the GPIO pin mux functions of PA[3] and PA[4]
• Section 9.1.2 Watchdog: Updated the introduction of watchdog
• Section 11.1.2 Basic Configuration: Updated the GPIO pin mux functions of PA[3] and PA[4] 0.5.3
• Section 1.2.2 General Features: Added notes for GSPI and LSPI
• Section 1.2.3 Features of Power Management Module: Added a note for power supply
• Section 2.4 AC Characteristics: Updated the frequency tolerance of 24 MHz crystal to 10ppm in Table 2-6 0.8.0
• Section 1.1 Block Diagram: Updated Figure 1-1 Block Diagram of the System
• Chapter 3 Reference Design: Added instructions for the 6.8uH inductor selection
• Section 4.1 Memory: Added Table 4-1 Memory Allocation

Datasheet for Telink TL3828 DS-TL3828-E5 3 Ver 0.8.0 Table of Contents

Datasheet for Telink TL3828 DS-TL3828-E5 4 Ver 0.8.0

Datasheet for Telink TL3828 DS-TL3828-E5 5 Ver 0.8.0

Datasheet for Telink TL3828 DS-TL3828-E5 6 Ver 0.8.0

Datasheet for Telink TL3828 DS-TL3828-E5 7 Ver 0.8.0

Datasheet for Telink TL3828 DS-TL3828-E5 8 Ver 0.8.0

Datasheet for Telink TL3828 DS-TL3828-E5 9 Ver 0.8.0

Datasheet for Telink TL3828 DS-TL3828-E5 10 Ver 0.8.0

Datasheet for Telink TL3828 DS-TL3828-E5 11 Ver 0.8.0

Datasheet for Telink TL3828 DS-TL3828-E5 12 Ver 0.8.0

Datasheet for Telink TL3828 DS-TL3828-E5 13 Ver 0.8.0

Datasheet for Telink TL3828 DS-TL3828-E5 14 Ver 0.8.0

Datasheet for Telink TL3828 DS-TL3828-E5 22 Ver 0.8.0 List of Tables

Datasheet for Telink TL3828 DS-TL3828-E5 23 Ver 0.8.0

Datasheet for Telink TL3828 DS-TL3828-E5 24 Ver 0.8.0

Datasheet for Telink TL3828 DS-TL3828-E5 25 Ver 0.8.0

Datasheet for Telink TL3828 DS-TL3828-E5 26 Ver 0.8.0

Datasheet for Telink TL3828 DS-TL3828-E5 27 Ver 0.8.0

Datasheet for Telink TL3828 DS-TL3828-E5 28 Ver 0.8.0

1 Overview

The TL3828 (including TL3828A, TL3828B) integrates 2 powerful 32-bit RISC-V MCU, up to 256 KB SRAM including up to 256 KB SRAM with retention in deep sleep, and up to 1536 KB embedded NVM (Non-volatile Memory including flash and RRAM), flexible IO interfaces, standard and advanced communication interfaces, and other peripheral blocks required for wired applications. The TL3828 combi nes the features and functions needed for high quality wired equipments into a single System on Chip.

1.1 Block Diagram

The TL3828 is designed to offer high integration, ultra-low power application capabilities. The system's block diagram is as shown in Figure 1-1. Figure 1-1 Block Diagram of the System The TL3828 integrates 12-bit SAR ADC, 16-bit SD-ADC, PWM, flexible IO interfaces, standard and advanced communication interfaces: I2C, I3C, SPI, UART, hi gh-speed USB, LIN and CAN. With the high integration level of TL3828, few external components are needed to satisfy customers' ultra-low cost requirements. JTAG GPIO LSPI UART PWM USB Interfaces SWS 24MHz RC Oscillator 32kHz RC Oscillator 32.768kHz Crystal Oscillator System PLL Clock 24MHz Crystal Oscillator ADC Security Secure Engine Power Management Power-On Reset Power Management Controller Reset LDO/DCDC Timer/Watchdog 32kHz LTimer System Timer Timer Memory SRAM SSPI Core1 32-bit RISC-V MCU D25F DMA QDEC Brown Out GSPI CAN 32-bit RISC-V MCU N22 Core2 DMA I2C I3C LIN FPU Flash & RRAM Crypto Acceleration Secure Debug Port Control Key Management TRNG eFuses

Datasheet for Telink TL3828 DS-TL3828-E5 29 Ver 0.8.0

1.2 Key Features

1.2.1 CPU and Memory

1. Dual Core system:

• Andes D25F º Instruction and Data Cache controller º 8 KB Instruction Cache º 4 KB Data Cache º Maximum running speed up to 192 MHz º Supports JTAG debug interface
• Andes N22 º Instruction Cache controller º 8 KB Instruction Cache º Maximum running speed up to 96 MHz º Supports JTAG debug interface 2. Memory architecture
• Program memory: up to 1536 KB embedded NVM
• Up to 256 KB SRAM including up to 256 KB retention SRAM
• 2K bits eFuse
• ROM for Secure Boot and Secure Debug

1.2.2 General Features

General features are as follows: 1. Supports 128-bit Unique ID (UID) 2. RTC and other timers

• Clock source of 24 MHz & 32.768 kHz Crystal and 24 MHz & 32 kHz embedded RC oscillator
• Two general 32-bit timers with four selectable modes in active mode
• Three general 32-bit timers with two selectable modes in active mode
• Watchdog timer
• A low-frequency 32 kHz timer available in low power mode
• RTC soft timer 3. Security solution
• Hardware Security Module (HSM) with proprietary controller and dedicated memories º Symmetric Key Engine (SKE), supports AES-128/192/256 º Public Key Engine (PKE), supports ECC (ECDH + ECDSA, 192/224/256/521 bits), RSA (512 ~4096 bits) º Hash accelerator, supports SHA-1, SHA224/256/384/512 º True Random Number Generator (TRNG)
• Root of Trust
• Secure Boot

Datasheet for Telink TL3828 DS-TL3828-E5 30 Ver 0.8.0

• Secure OTA
• Firmware encryption
• Secure Debug Port Control
• Prevent any unauthorized or maliciously modified software from running
• Signature and verification based on RSA2048 or ECC256
• Secure Key Management
• Secure Attestation 4. A rich set of digital and analog interfaces
• Up to 64 GPIOs (differs for specific part number, refers to 1.4 Ordering Information)
• Up to 7x different SPI º 5x GSPI: General SPI – Up to 48 MHz SPI clock1 – Supports Quad/Dual/Signal data line – Supports PSRAM interface – Supports Nor-Flash interface º LSPI: LCD SPI – Up to 48 MHz SPI clock2 – Supports Quad/Dual/Signal data line – Supports TFT panel interface – Supports TFT panel interface without internal RAM º SPI Slave for external accessing
• Up to 2x I3C
• Up to 2x I2C
• Up to 5x UART
• Supports JTAG/SDP/SWS debug interface º One JTAG/SDP i nterface for RISC-V core º SWS interface for whole system
• Up to 8x capacitive touch button (CTB)
• Telink Rapid Keyscan Handler (TRKH) º Digital keyscan 8x18 º Analog keyscan
• I2S
• PDM
• USB High-speed3
• Up to 2x CAN 1. GSPI reaches 48 MHz only when the specific pins are configured as GSPI signals. Please refer to Section 11.7.1. 2. LSPI reaches 48 MHz only when the specific pins are configured as LSPI signals. Please refer to Section 11.6.1. 3. When using USB function, the supply voltage must be greater than 3.0V.

Datasheet for Telink TL3828 DS-TL3828-E5 31 Ver 0.8.0

• Up to 2x LIN
• Up to 24 channels of differential PWM º 7x Full function º 17x Normal function
• 2x Quadrature Decoder (QDEC), two-phase input selectable
• Single-channel differential AMIC (Analog MIC) and Dual-channel DMIC (Digital MIC) sharing chain
• 2x 12-bit SAR ADC with up to 16 channels input (2M sample rate)
• 16-bit auxiliary High-Resolution SD-ADC for AMIC or DC
• Low power comparator
• Supports RZ (Return to Zero)
• Supports PEM (Peri pheral Event Matrix) 5. Supports OTA upgrade and Secure Boot switch, allowing convenient product feature roll outs and upgrades 6. Operating temperature range: -40 °C ~ +85°C 7. Completely RoHS-compliant package
• TL3828A, 80-pin QFN, 9x9x0.75 mm
• TL3828B, 56-pin QFN, 7x7x0.75 mm

1.2.3 Features of Power Management Module

Features of power management module include: 1. Power supply

• VBAT (battery): 1.7 V ~ 4.5 V1
• VBUS (USB): 4.5 V ~ 5.5 V 2. Embedded LDO and DCDC
• DCDC for 1.8 V flash with bypass LDO
• DCDC for chip with bypass LDO 3. Battery monitor for low battery voltage detection 4. Brownout detection/shutdown and Power-On-Reset 5. Supports power reduction in different Clock Scenarios 6. Low power consumption:
• Deep sleep with external wakeup (without SRAM retention): 0.7 µA
• Deep sleep with 32 KB SRAM retention: 1.8 µA
• Deep sleep with 64 KB SRAM retention: 2.4 µA
• Deep sleep with 128 KB SRAM retention: 3.2 µA
• Deep sleep with 256 KB SRAM retention: 5.7 µA
• Deep sleep with 384 KB SRAM retention: 7.8 µA
• Deep sleep with external wakeup, with 32K RC oscillator on (without SRAM retention): 1.0 µA
• D eep sleep with 32 KB SRAM retention, with 32K RC oscillator on: 2.2 µA
• Deep sleep with 64 KB SRAM retention, with 32K RC oscillator on: 2.8 µA 1. For specific usage considerations, please refer to Section 17.1.

Datasheet for Telink TL3828 DS-TL3828-E5 32 Ver 0.8.0

• Deep sleep with 128 KB SRAM retention, with 32K RC oscillator on: 3.9 µA
• Deep sleep with 256 KB SRAM retention, with 32K RC oscillator on: 6.1 µA
• Deep sleep with 384 KB SRAM retention, with 32K RC oscillator on: 8.4 µA
• Shutdown with IO wakeup: 0.45 µA

1.2.4 RZ Features

1. The RZ (Return to Zero) module adopts single wire return to zero code protocol for communication transmission, and can drive serial or parallel pixel ICs 2. RZ Code Timing can be configured flexibly to match different Pixel ICs 3. There are two addressing modes for pixel ICs:

• Serial sequential addressing
• Parallel random addressing 4. The RZ module has no CPU interventi on duri ng transmission 5. DMA handling data is bounded by 8 bits 6. PCLK: 24MHz or 48MHz

1.3 Typical Applications

The TL3828 is an ideal SoC for wired applications. Its typical applications include, but are not limited to the following:

• Wired Gaming

Datasheet for Telink TL3828 DS-TL3828-E5 33 Ver 0.8.0

1.4 Ordering Information

Table 1-1 Ordering Information of TL3828 Product Series Ordering No. SRAM (KB) NVMa (KB) a. The NVM includes RRAM and flash, the details refer to 4.1 Memory. USBb b. HS stands for high speed. c. Packing method “T&R” means tape and reel. The tape and reel material DO NOT support baking. MOQd d. MOQ stands for Minimum Ordering Quantity. TL3828 TL3828A E10T80Re e. TL3828A: 5x Timer, 1x DMIC, 1x AMIC, 1x I2S, 2x SAR ADC (8+8) channels, SD ADC x1 channel, 2x I2C, 2x I3C, 5x UART, 7x SPI, 24x PWM, 2x CAN, 2x LIN, 1x JTAG 256 1536 HS 64 QFN80 9x9x0.75mm -40~+85 T&R 3000 TL3828B E10T56Rf f. TL3828B: 5x Timer, 1x DMIC, 1x AMIC, 1x I2S, 2x SAR ADC (8+8) channels, SD ADC x1 channel, 2x I2C, 2x I3C, 5 x UART, 7x SPI, 24x PWM, 2x CAN, 2x LIN 256 1536 HS 40 QFN56 7x7x0.75mm -40~+85 T&R 3000

Datasheet for Telink TL3828 DS-TL3828-E5 34 Ver 0.8.0

1.5 Package

1.5.1 Package dimensions of TL3828A

Figure 1-2 Package of TL3828A Table 1-2 Mechanical Dimension of TL3828A Symbol Millimeter Min Nom Max A 0.7 0.75 0.80 A1 0.00 0.02 0.05 A3 0.20REF b 0.15 0.20 0.25 D 8.90 9.0 9.10 E 8.90 9.0 9.10 D2 7.00 7.10 7.20

Datasheet for Telink TL3828 DS-TL3828-E5 35 Ver 0.8.0

1.5.2 Package dimensions of TL3828B

Figure 1-3 Package of TL3828B E2 7.00 7.10 7.20 e 0.40BSC H 0.35REF K 0.45 0.55 0.65 L 0.35 0.40 0.45 R 0.065 - - c1 - 0.10 - c2 - 0.10 - Symbol Millimeter Min Nom Max D E PIN 1(Laser Mark) Nd Ne h h (;326('7+(50$/ 3$'=21( be L c A 7239,(: %277209,(: 6,'(9,(: K K 6HFWLRQ$$ wsc tsc

Datasheet for Telink TL3828 DS-TL3828-E5 36 Ver 0.8.0 Table 1-3 Mechanical Dimension of TL3828B Symbol Millimeter Min Nom Max A* 0.7 0.75 0.80 A1* 0.00 0.02 0.05 b 0.15 0.20 0.25 b1 0.18REF c 0.203REF D* 6.90 7.0 7.10 D2 5.55 5.65 5.75 e 0.40BSC Nd 5.20BSC Ne 5.20BSC E* 6.90 7.0 7.10 E2 5.55 5.65 5.75 K 0.275REF L 0.35 0.40 0.45 h 0.25 0.30 0.35 Wsc 0.01 - 0.09 Tsc 0.08 - 0.18

Datasheet for Telink TL3828 DS-TL3828-E5 37 Ver 0.8.0

1.6 Pin Layout

1.6.1 Pin assignment of TL3828A

Pin assignment of TL3828A is shown below. Figure 1-4 Pin Assignment of TL3828A Functions of 80 pins of TL3828A are described in table below. Table 1-4 Pin Function of TL3828A No. Pin Name Type Description 1 PG[3] GPIO GPIO PG[3], refer to Table 1-5 for pin mux function.

2 PG[4] GPIO GPIO PG[4]

3 PG[5] GPIO GPIO PG[5]

80 79 78 77 76 75 74 73 72 71 70 69 21 22 23 24 25 26 27 28 29 30 31 32 PG[3] PG[4] PG[5] PG[6] PG[7] PH[0] PH[4] PH[3] PH[5] PE[2] PE[3] PE[4] PE[5] PE[6] PA[1] PA[2] PA[4] PA[3] PA[5] DCDC_SW VMID VDD_F VBAT VBUS PB[6] PB[7] VDDO3 PC[0] AVDD1P2 PF[0] PF[1] PF[2] PF[3] PF[4] PF[5] PF[6] PF[7] PG[0] PG[1] PG[2] TL3828A PH[6] PB[4] PB[5] PH[1] PH[2] PE[7] PA[0] 13PH[7] 14PD[7] 15PD[6] 17PD[4] 16PD[5] 18VDDIOPE 19PE[0] 20PE[1] 33PA[6] PA[7] VDECUSB VDECCORE PC[5] PC[6] PC[7] VDD3_DCDC

53 PC[1]

54 PC[2]

55 PC[3]

56 PC[4]

57 XC1

58 XC2

59 POR

PD[3] PD[2] PD[1] PD[0] PB[3] PB[2] PB[1] VLINE PB[0]

Datasheet for Telink TL3828 DS-TL3828-E5 38 Ver 0.8.0

4 PG[6] GPIO GPIO PG[6]

5 PG[7] GPIO GPIO PG[7]

6 PH[0] GPIO GPIO PH[0]

7 PH[1] GPIO GPIO PH[1]

8 PH[2] GPIO GPIO PH[2]

9 PH[3] GPIO GPIO PH[3]

10 PH[4] GPIO GPIO PH[4]

11 PH[5] GPIO GPIO PH[5]

12 PH[6] GPIO GPIO PH[6]

13 PH[7] GPIO GPIO PH[7]

14 PD[7] GPIO GPIO PD[7]

15 PD[6] GPIO GPIO PD[6]

16 PD[5] GPIO GPIO PD[5]

17 PD[4] GPIO GPIO PD[4]

18 AVDDIO_PE PWR IO voltage for PE0 ~ PE7, configurable to 3.3V or 1.8V

19 PE[0] GPIO GPIO PE[0]

20 PE[1] GPIO GPIO PE[1]

21 PE[2] GPIO GPIO PE[2]

22 PE[3] GPIO GPIO PE[3]

23 PE[4] GPIO GPIO PE[4]

24 PE[5] GPIO GPIO PE[5]

25 PE[6] GPIO GPIO PE[6]

26 PE[7] GPIO GPIO PE[7]

27 PA[0] GPIO GPIO PA[0]

28 PA[1] GPIO GPIO PA[1]

29 PA[2] GPIO GPIO PA[2]

30 PA[4] GPIO GPIO PA[4]

31 PA[3] GPIO GPIO PA[3]

No. Pin Name Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 39 Ver 0.8.0

32 PA[5] GPIO GPIO PA[5]

33 PA[6] GPIO GPIO PA[6]

34 PA[7] GPIO GPIO PA[7]

35 VDECUSB PWR Power supply for USB

36 VDECCORE PWR Digital core power supply

37 PC[5] GPIO GPIO PC[5]

38 PC[6] GPIO GPIO PC[6]

39 PC[7] GPIO GPIO PC[7]

40 VDD3_DCDC PWR 3.3V DCDC output

41 DCDC_SW Analog Connected with VDCDC via external inductor

42 AVDD1P2 PWR 1.2V analog power supply 43 VDD_F PWR Internally generated power supply to flash. Connect to GND via external capacitor

44 VBAT PWR

Lion-Battery power supply. When using VBUS power supply, the VBAT pin needs to be connected to the VDDO3 pin.

45 VBUS PWR 5V USB power supply

46 PB[4] GPIO GPIO PB[4]

47 PB[5] GPIO GPIO PB[5]

48 PB[6] GPIO GPIO PB[6]

49 PB[7] GPIO GPIO PB[7]

50 VDDO3 PWR 3.3V analog power supply

51 VMID Analog Audio pin connecting to external decap

52 PC[0] GPIO GPIO PC[0]

53 PC[1] GPIO GPIO PC[1]

54 PC[2] GPIO GPIO PC[2]

55 PC[3] GPIO GPIO PC[3]

56 PC[4] GPIO GPIO PC[4]

57 XC1 Analog Crystal oscillator pin 1

58 XC2 Analog Crystal oscillator pin 2

No. Pin Name Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 40 Ver 0.8.0 GPIO pin mux functions of TL3828A are shown in the table below. Table 1-5 GPIO Pin Mux of TL3828A

59 POR Analog Power on reset

60 NC - Not connected

61 VLINE PWR 1.2V power supply

62 PB[0] GPIO GPIO PB[0]

63 PB[1] GPIO GPIO PB[1]

64 PB[2] GPIO GPIO PB[2]

65 PB[3] GPIO GPIO PB[3]

66 PD[0] GPIO GPIO PD[0]

67 PD[1] GPIO GPIO PD[1]

68 PD[2] GPIO GPIO PD[2]

69 PD[3] GPIO GPIO PD[3]

70 PF[0] GPIO GPIO PF[0]

71 PF[1] GPIO GPIO PF[1]

72 PF[2] GPIO GPIO PF[2]

73 PF[3] GPIO GPIO PF[3]

74 PF[4] GPIO GPIO PF[4]

75 PF[5] GPIO GPIO PF[5]

76 PF[6] GPIO GPIO PF[6]

77 PF[7] GPIO GPIO PF[7]

78 PG[0] GPIO GPIO PG[0]

79 PG[1] GPIO GPIO PG[1]

80 PG[2] GPIO GPIO PG[2]

Pad Default Function4 Function3 Function2 Function1 Function0 Analog Function PA[0] GPIO All functionsa KEYS0 - PWM#1b - - PA[1] GPIO All functions KEYS1 - PWM#2 - - PA[2] GPIO All functions KEYS2 - PWM#3 - - No. Pin Name Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 41 Ver 0.8.0 PA[3] GPIO - - - - - USB0_DM (HS) PA[4] GPIO - - - - - USB0_DP (HS) PA[5] GPIO - - - - - - PA[6] GPIO - - - - - - PA[7] SWS SWM - - - SWS - PB[0] GPIO All functions KEYS5 - PWM#2 - saradc1_in/comp_in/ ctb_in PB[1] GPIO All functions KEYS6 - PWM#3 - saradc1_in/comp_in/ ctb_in PB[2] GPIO All functions KEYS7 - PWM#4 - saradc1_in/comp_in/ ctb_in PB[3] GPIO All functions KEYS8 - PWM#1 - saradc1_in/comp_in/ ctb_in PB[4] GPIO All functions KEYS9 - PWM#2 - saradc1_in/rram_test1/ comp_in/ctb_in/ sdadc_in PB[5] GPIO All functions KEYS10 - PWM#3 - saradc1_in/rram_test2/ comp_in/ctb_in/ sdadc_in PB[6] GPIO All functions KEYS11 - PWM#4 - saradc1_in/rram_test3/ comp_in/ctb_in/ sdadc_in PB[7] GPIO All functions KEYS12 - PWM#1 - saradc1_in/comp_in/ ctb_in/sdadc_in PC[0] GPIO All functions KEYS13 - PWM#2 - saradc0_in/AudioP/ ctb_in/sdadc_in PC[1] GPIO All functions KEYS14 - PWM#3 - saradc0_in/AudioN/ ctb_in/sdadc_in PC[2] GPIO All functions KEYS15 - PWM#4 - saradc0_in/32k xc1/ ctb_in/sdadc_in PC[3] GPIO All functions KEYS16 - PWM#1 - saradc0_in/32k xc2/ ctb_in/sdadc_in Pad Default Function4 Function3 Function2 Function1 Function0 Analog Function

Datasheet for Telink TL3828 DS-TL3828-E5 42 Ver 0.8.0 PC[4] GPIO All functions KEYS17 - PWM#2 - saradc0_in/ATB/ ctb_in/sdadc_in PC[5] GPIO All functions KEYS18 - PWM#3 - saradc0_in/ctb_in/ sdadc_in PC[6] GPIO All functions KEYS19 - PWM#4 - saradc0_in/ctb_in PC[7] GPIO All functions KEYS20 - PWM#1 - saradc0_in/ctb_in PD[0] SSPI_CN All functions KEYS21 - PWM#2 - - PD[1] SSPI_CK All functions KEYS22 - PWM#3 - - PD[2] SSPI_SI All functions KEYS23 - PWM#4 - - PD[3] SSPI_SO All functions KEYS24 - PWM#1 - - PD[4] TDI All functions KEYS25 TDI PWM#2 - - PD[5] TDO All functions KEYS26 TDO PWM#3 - - PD[6] TMS All functions KEYS27 TMS PWM#4 - - PD[7] TCK All functions KEYS28 TCK PWM#1 - - PE[0] GPIO All functions KEYS29 - PWM#2 - - PE[1] GPIO All functions KEYS30 - PWM#3 - - PE[2] GPIO All functions KEYS31 - PWM#4 - - PE[3] GPIO All functions KEYS0 - PWM#1 - - PE[4] GPIO All functions KEYS1 - PWM#2 - - PE[5] GPIO All functions KEYS2 - PWM#3 - - PE[6] GPIO All functions KEYS3 - PWM#4 - - PE[7] GPIO All functions KEYS4 - PWM#1 - - PF[0] GPIO All functions KEYS5 - PWM#2 - - PF[1] GPIO All functions KEYS6 - PWM#3 - - PF[2] GPIO All functions KEYS7 - PWM#4 - - PF[3] GPIO All functions KEYS8 - PWM#1 - - PF[4] GPIO All functions KEYS9 - PWM#2 - - PF[5] GPIO All functions KEYS10 - PWM#3 - - PF[6] GPIO All functions KEYS11 - PWM#4 - - Pad Default Function4 Function3 Function2 Function1 Function0 Analog Function

Datasheet for Telink TL3828 DS-TL3828-E5 43 Ver 0.8.0 PF[7] GPIO All functions KEYS12 - PWM#1 - - PG[0] GPIO All functions KEYS13 - PWM#2 - - PG[1] GPIO All functions KEYS14 - PWM#3 - - PG[2] GPIO All functions KEYS15 - PWM#4 - - PG[3] GPIO All functions KEYS16 - PWM#1 - - PG[4] GPIO All functions KEYS17 - PWM#2 - - PG[5] GPIO All functions KEYS18 - PWM#3 - - PG[6] GPIO All functions KEYS19 - PWM#4 - - PG[7] GPIO All functions KEYS20 - PWM#1 - - PH[0] GPIO All functions KEYS21 - PWM#2 - - PH[1] GPIO All functions KEYS22 - PWM#3 - - PH[2] GPIO All functions KEYS23 - PWM#4 - - PH[3] GPIO All functions KEYS24 - PWM#1 - - PH[4] GPIO All functions KEYS25 - PWM#2 - - PH[5] GPIO All functions KEYS26 - PWM#3 - - PH[6] GPIO All functions KEYS27 - PWM#4 - - PH[7] GPIO All functions KEYS28 - PWM#1 - - a. “All functions” includes 109 functions, see Table 1-8 below. b. “PWM#1” includes PWM0, PWM4, PWM8, PWM12, PWM16, PWM20, PWM0_N, PWM4_N, PWM8_N, PWM12_N, PWM16_N, PWM20_N; “PWM#2” includes PWM1, PWM5, PWM9, PWM13, PWM17, PWM21, PWM1_N, PWM5_N, PWM9_N, PWM13_N, PWM17_N, PWM21_N; “PWM#3” includes PWM2, PWM6, PWM10, PWM14, PWM18, PWM22, PWM2_N, PWM6_N, PWM10_N, PWM14_N, PWM18_N, PWM22_N; “PWM#4” includes PWM3, PWM7, PWM11, PWM15, PWM19, PWM23, PWM3_N, PWM7_N, PWM11_N, PWM15_N, PWM19_N, PWM23_N. Pad Default Function4 Function3 Function2 Function1 Function0 Analog Function

Datasheet for Telink TL3828 DS-TL3828-E5 44 Ver 0.8.0

1.6.2 Pin assignment of TL3828B

Pin assignment of TL3828B is shown below. Figure 1-5 Pin Assignment of TL3828B Functions of 56 pins of TL3828B are described in table below. Table 1-6 Pin Function of TL3828B No. Pin Name Type Description 1 PG[7] GPIO GPIO PG[7], refer to Table 1-7 for pin mux function.

2 PH[3] GPIO GPIO PH[3]

3 PH[4] GPIO GPIO PH[4]

4 PH[5] GPIO GPIO PH[5]

5 PH[6] GPIO GPIO PH[6]

PG[7] PH[3] PH[4] PH[5] PD[6] PD[7] VDDIOPE PE[1] PH[6] PH[7] PE[2] PE[3] VMID PB[6] PB[7] VDDO3 PC[0] PB[4] PB[5] PC[1] PC[2] PC[3] PC[4] XC1 PA[1] PA[2] PA[4] PA[3] PC[5] PC[6] PC[7] VDD3_DCDC DCDC_SW PA[7] VDECCORE AVDD1P2 VDD_F 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 VLINE PB[0] PB[1] PB[2] PB[3] PD[0] PF[4] PF[5] PF[6] PF[7] PG[0] NC PA[0] POR XC2 VBAT VBUS VDECUSB PE[0]

Datasheet for Telink TL3828 DS-TL3828-E5 45 Ver 0.8.0

6 PH[7] GPIO GPIO PH[7]

7 PD[7] GPIO GPIO PD[7]

8 PD[6] GPIO GPIO PD[6]

9 AVDDIO_PE PWR IO voltage for PE0 ~ PE3, configurable to 3.3V or 1.8V

10 PE[0] GPIO GPIO PE[0]

11 PE[1] GPIO GPIO PE[1]

12 PE[2] GPIO GPIO PE[2]

13 PE[3] GPIO GPIO PE[3]

14 PA[0] GPIO GPIO PA[0]

15 PA[1] GPIO GPIO PA[1]

16 PA[2] GPIO GPIO PA[2]

17 PA[4] GPIO GPIO PA[4]

18 PA[3] GPIO GPIO PA[3]

19 PA[7] GPIO GPIO PA[7]

20 VDECUSB PWR Power supply for USB

21 VDECCORE PWR Digital core power supply

22 PC[5] GPIO GPIO PC[5]

23 PC[6] GPIO GPIO PC[6]

24 PC[7] GPIO GPIO PC[7]

25 VDD3_DCDC PWR 3.3V DCDC output

26 DCDC_SW Analog Connected with VDCDC via external inductor

27 AVDD1P2 PWR 1.2V analog power supply 28 VDD_F PWR Internally generated power supply to flash. Connect to GND via external capacitor

29 VBAT PWR

Lion-Battery power supply. When using VBUS power supply,the VBAT pin needs to be connected to the VDDO3 pin.

30 VBUS PWR 5V USB power supply

31 PB[4] GPIO GPIO PB[4]

32 PB[5] GPIO GPIO PB[5]

No. Pin Name Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 46 Ver 0.8.0 GPIO pin mux functions of TL3828B are shown in the table below. Table 1-7 GPIO Pin Mux of TL3828B

33 PB[6] GPIO GPIO PB[6]

34 PB[7] GPIO GPIO PB[7]

35 VDDO3 PWR 3.3V analog power supply

36 VMID Analog Audio pin connecting to external decap

37 PC[0] GPIO GPIO PC[0]

38 PC[1] GPIO GPIO PC[1]

39 PC[2] GPIO GPIO PC[2]

40 PC[3] GPIO GPIO PC[3]

41 PC[4] GPIO GPIO PC[4]

42 XC1 Analog Crystal oscillator pin 1

43 XC2 Analog Crystal oscillator pin 2

44 POR Analog Power on reset

45 NC - Not connected

46 VLINE PWR 1.2V power supply

47 PB[0] GPIO GPIO PB[0]

48 PB[1] GPIO GPIO PB[1]

49 PB[2] GPIO GPIO PB[2]

50 PB[3] GPIO GPIO PB[3]

51 PD[0] GPIO GPIO PD[0]

52 PF[4] GPIO GPIO PF[4]

53 PF[5] GPIO GPIO PF[5]

54 PF[6] GPIO GPIO PF[6]

55 PF[7] GPIO GPIO PF[7]

56 PG[0] GPIO GPIO PG[0]

Pad Default Function4 Function3 Function2 Function1 Function0 Analog Function PA[0] GPIO All functionsa KEYS0 - PWM#1b - - No. Pin Name Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 47 Ver 0.8.0 PA[1] GPIO All functions KEYS1 - PWM#2 - - PA[2] GPIO All functions KEYS2 - PWM#3 - - PA[3] GPIO - - - - - USB0_DM (HS) PA[4] GPIO - - - - - USB0_DP (HS) PA[7] SWS SWM - - - SWS - PB[0] GPIO All functions KEYS5 - PWM#2 - saradc1_in/comp_in/ ctb_in PB[1] GPIO All functions KEYS6 - PWM#3 - saradc1_in/comp_in/ ctb_in PB[2] GPIO All functions KEYS7 - PWM#4 - saradc1_in/comp_in/ ctb_in PB[3] GPIO All functions KEYS8 - PWM#1 - saradc1_in/comp_in/ ctb_in PB[4] GPIO All functions KEYS9 - PWM#2 - saradc1_in/rram_test1/ comp_in/ctb_in/ sdadc_in PB[5] GPIO All functions KEYS10 - PWM#3 - saradc1_in/rram_test2/ comp_in/ctb_in/ sdadc_in PB[6] GPIO All functions KEYS11 - PWM#4 - saradc1_in/rram_test3/ comp_in/ctb_in/ sdadc_in PB[7] GPIO All functions KEYS12 - PWM#1 - saradc1_in/comp_in/ ctb_in/sdadc_in PC[0] GPIO All functions KEYS13 - PWM#2 - saradc0_in/AudioP/ ctb_in/sdadc_in PC[1] GPIO All functions KEYS14 - PWM#3 - saradc0_in/AudioN/ ctb_in/sdadc_in PC[2] GPIO All functions KEYS15 - PWM#4 - saradc0_in/32k xc1/ ctb_in/sdadc_in PC[3] GPIO All functions KEYS16 - PWM#1 - saradc0_in/32k xc2/ ctb_in/sdadc_in Pad Default Function4 Function3 Function2 Function1 Function0 Analog Function

Datasheet for Telink TL3828 DS-TL3828-E5 48 Ver 0.8.0 PC[4] GPIO All functions KEYS17 - PWM#2 - saradc0_in/ATB/ ctb_in/sdadc_in PC[5] GPIO All functions KEYS18 - PWM#3 - saradc0_in/ctb_in/ sdadc_in PC[6] GPIO All functions KEYS19 - PWM#4 - saradc0_in/ctb_in PC[7] GPIO All functions KEYS20 - PWM#1 - saradc0_in/ctb_in PD[0] SSPI_CN All functions KEYS21 - PWM#2 - - PD[6] TMS All functions KEYS27 TMS PWM#4 - - PD[7] TCK All functions KEYS28 TCK PWM#1 - - PE[0] GPIO All functions KEYS29 - PWM#2 - - PE[1] GPIO All functions KEYS30 - PWM#3 - - PE[2] GPIO All functions KEYS31 - PWM#4 - - PE[3] GPIO All functions KEYS0 - PWM#1 - - PF[4] GPIO All functions KEYS9 - PWM#2 - - PF[5] GPIO All functions KEYS10 - PWM#3 - - PF[6] GPIO All functions KEYS11 - PWM#4 - - PF[7] GPIO All functions KEYS12 - PWM#1 - - PG[0] GPIO All functions KEYS13 - PWM#2 - - PG[7] GPIO All functions KEYS20 - PWM#1 - - PH[3] GPIO All functions KEYS24 - PWM#1 - - PH[4] GPIO All functions KEYS25 - PWM#2 - - PH[5] GPIO All functions KEYS26 - PWM#3 - - PH[6] GPIO All functions KEYS27 - PWM#4 - - PH[7] GPIO All functions KEYS28 - PWM#1 - - a. “All functions” includes 100 functions, see Table 1-8 below. b. “PWM#1” includes PWM0, PWM4, PWM8, PWM12, PWM16, PWM20, PWM0_N, PWM4_N, PWM8_N, PWM12_N, PWM16_N, PWM20_N; “PWM#2” includes PWM1, PWM5, PWM9, PWM13, PWM17, PWM21, PWM1_N, PWM5_N, PWM9_N, PWM13_N, PWM17_N, PWM21_N; “PWM#3” includes PWM2, PWM6, PWM10, PWM14, PWM18, PWM22, PWM2_N, PWM6_N, PWM10_N, PWM14_N, PWM18_N, PWM22_N; “PWM#4” includes PWM3, PWM7, PWM11, PWM15, PWM19, PWM23, PWM3_N, PWM7_N, PWM11_N, PWM15_N, PWM19_N, PWM23_N. Pad Default Function4 Function3 Function2 Function1 Function0 Analog Function

Datasheet for Telink TL3828 DS-TL3828-E5 49 Ver 0.8.0 The functions included in the “All functions” are listed in the table below: Table 1-8 GPIO functions Register value Function Register value Function Register value Function 13 - 51 SDM0_N 89 I3C1_SDA 14 - 52 SDM1_P 90 I3C1_SCL 15 - 53 SDM1_N 91 GSPI0_CN

16 I2C_SCL 54 IR_LEARN 92 GSPI0_IO3

17 I2C_SDA 55 SSPI_CN 93 GSPI0_IO2

18 I2C1_SDA 56 SSPI_CK 94 GSPI0_MISO

19 I2C1_SCL 57 SSPI_SI 95 GSPI0_MOSI

20 UART0_CTS 58 SSPI_SO 96 GSPI0_CK

21 UART0_RTS 59 - 97 GSPI1_CN

22 UART0_TX 60 PWM_SYNC 98 GSPI1_IO3

23 UART0_RTX 61 RZ_TX 99 GSPI1_IO2

24 UART1_CTS 62 SWM 100 GSPI1_MISO

25 UART1_RTS 63 TX_CYC2PA 101 GSPI1_MOSI

26 UART1_TX 64 - 102 GSPI1_CK

27 UART1_RTX 65 - 103 GSPI2_CN

28 UART2_CTS 66 - 104 GSPI2_IO3

29 UART2_RTS 67 - 105 GSPI2_IO2

30 UART2_TX 68 - 106 GSPI2_MISO

31 UART2_RTX 69 - 107 GSPI2_MOSI

32 UART3_CTS 70 - 108 GSPI2_CK

33 UART3_RTS 71 - 109 GSPI3_CN

34 UART3_TX 72 - 110 GSPI3_IO3

35 UART3_RTX 73 RX_CYC2LNA 111 GSPI3_IO2

36 UART4_CTS 74 - 112 GSPI3_MISO

NOTE: The pins PD[0] ~ PD[7] are not suitable to be used as wakeup source.

Datasheet for Telink TL3828 DS-TL3828-E5 50 Ver 0.8.0 Descriptions of each signal are listed in the following tables. Table 1-9 PWM Signal Description Table 1-10 I2C Signal Description

37 UART4_RTS 75 - 113 GSPI3_MOSI

38 UART4_TX 76 - 114 GSPI3_CK

39 UART4_RTX 77 LIN0_RX 115 GSPI4_CN

40 CLK_7816 78 LIN0_TX 116 GSPI4_IO3

41 - 79 LIN1_RX 117 GSPI4_IO2

42 I2S2_BCK 80 LIN1_TX 118 GSPI4_IO2

43 I2S2_LR0 81 CAN0_RX 119 GSPI4_MOSI

44 I2S2_DAT0 82 CAN0_TX 120 GSPI4_CK

45 I2S2_LR1 83 CAN1_RX 121 LSPI_CN

46 I2S2_DAT1 84 CAN1_TX 122 LSPI_IO3

47 I2S2_CLK 85 I3C0_SDA_PULLUP_EN 123 LSPI_IO2

48 DMIC0_CLK 86 I3C0_SDA 124 LSPI_MISO

49 DMIC0_DAT 87 I3C0_SCL 125 LSPI_MOSI

50 SDM0_P 88 I3C1_SDA_PULLUP_EN 126 LSPI_CK

PWM#na a. #n=0 ~ 23 DO PWM channel #n output PWM#n_N DO PWM channel #n inversion output PWM_SYNC DO PWM synchronization Signal Type Description I2C_SCL DIO I2C SCL I2C_SDA DIO I2C SDA Register value Function Register value Function Register value Function NOTE: Insufficient pins will lead to lack of corresponding function.

Datasheet for Telink TL3828 DS-TL3828-E5 51 Ver 0.8.0 Table 1-11 I3C Signal Description Table 1-12 CAN Signal Description Table 1-13 LIN Signal Description Table 1-14 UART Signal Description Table 1-15 GSPI Signal Description Signal Type Description I3C_SCL DIO I3C SCL I3C_SDA DIO I3C SDA I3C_SDA_PULLUP_EN DIO I3C SDA Pull-up Signal Type Description CAN_RX DI CAN RX CAN_TX DO CAN TX Signal Type Description LIN_RX DI LIN RX LIN_TX DO LIN TX Signal Type Description UART_CTS DI UART Clear to Send signal UART_RTS DO UART Ready to Send signal UART_RTX DIO UART RTX UART_TX DO UART TX Signal Type Description GSPI_CK DIO GSPI CLK GSPI_CN DIO GSPI CN0 GSPI_MISO DIO GSPI MISO GSPI_MOSI DIO GSPI MOSI GSPI_IO2 DIO GSPI IO2 GSPI_IO3 DIO GSPI IO3

Datasheet for Telink TL3828 DS-TL3828-E5 52 Ver 0.8.0 Table 1-16 LSPI Signal Description Table 1-17 SPI Slave Signal Description Table 1-18 7816 Signal Description Table 1-19 DMIC Signal Description Table 1-20 I2S Signal Description Signal Type Description LSPI_CK DIO LSPI CLK LSPI_CN DIO LSPI CN LSPI_MISO DIO LSPI MISO LSPI_MOSI DIO LSPI MOSI LSPI_IO2 DIO LSPI IO2 LSPI_IO3 DIO LSPI IO3 Signal Type Description SSPI_CK DI SSPI CLK SSPI_CN DI SSPI CN SSPI_SI DIO SSPI SI SSPI_SO DIO SSPI SO Signal Type Description CLK_7816 DO 7816 CLK Signal Type Description DMIC_CLK DO DMIC CLK DMIC_DAT DI DMIC DATA IN Signal Type Description I2S_BCK DIO I2S bit CLK I2S_CLK DO I2S base CLK I2S_LR1 DIO I2S left and right channel SEL I2S_LR0 DIO I2S left and right channel SEL

Datasheet for Telink TL3828 DS-TL3828-E5 53 Ver 0.8.0 Table 1-21 Audio Output Signal Description Table 1-22 Swire Signal Description Table 1-23 External Power Amplifier, Low Noise Amplifier Signal Description Table 1-24 USB Signal Description Table 1-25 JTAG Signal Description I2S_DAT1 DI I2S data IN I2S_DAT0 DO I2S data OUT Signal Type Description SDM_N DO SDM diff output SDM_P DO SDM diff output Signal Type Description SWM DIO Swire Master SWS DIO Swire Slave Signal Type Description RX_CYC2LNA DO External low noise amplifier TX_CYC2PA DO External power amplifier Signal Type Description DP DIO USB DP DM DIO USB DM Signal Type Description TDI DI Test data input TDO DO Test data output TMS DIO Test mode selection TCK DI Test clock input Signal Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 54 Ver 0.8.0 Table 1-26 SDP Signal Description Table 1-27 Low Power Comparator Signal Description Table 1-28 SAR ADC Signal Description Table 1-29 SD ADC Signal Description Table 1-30 CTB Signal Description Table 1-31 Crystal Signal Description Signal Type Description TCK DI Test clock input TMS DIO Test mode selection Signal Type Description comp_in<n> AI Low power comparator channel n Signal Type Description saradc_in<n> AI SAR ADC input channel n Signal Type Description sdadc_in<n> AI SD ADC input channel n Signal Type Description ctb_in<n> AI CTB input channel n Signal Type Description xtl32k_out AO 32kHz crystal output pin xtl32k_in AI 32kHz crystal input pin NOTE:

• DI: Digital input
• DO: Digital output
• DIO: Digital input/outputAI: Analog input
• AO: Analog output
• AIO: Analog input/output

Datasheet for Telink TL3828 DS-TL3828-E5 55 Ver 0.8.0

2 Electrical Specifications

2.1 Absolute Maximum Rating

Table 2-1 Absolute Maximum Rating

2.2 Recommended Operating Conditions

Table 2-2 Recommend Operating Conditions

2.3 DC Characteristics

Unless otherwise stated, the general test condition is: V=3.3V, T = 25°C. Characteristics Sym. Min. Max. Unit Test Condition Supply voltage VBAT -0.3 4.5 V - USB voltage VBUS -0.3 5.5 V - Voltage on input pin Vin -0.3 VDD+0.3 V - Output voltage Vout 0 VDD V - Storage temperature range TStr -65 150 °C - Soldering temperature TSld - 260 °C - Maximum junction temperature TJ - 125 °C - Item Sym. Min. Typ. Max. Unit Condition Power supply voltage VBAT 1.7 3.3 4.5 V - USB supply voltage VBUS 4.5 5.0 5.5 V - Supply rise time (from 1.6 V to 1.8 V) TR - - 10 ms - Operating temperature range TOpr -40 - 85 °C - NOTE:

• Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
• VDD stands for IO voltage. NOTE: For specific usage considerations related to power supply voltage, please refer to Section 17.1.

Datasheet for Telink TL3828 DS-TL3828-E5 56 Ver 0.8.0 Table 2-3 RX/TX Current and Sleep Current Item Sym. Min Typ. Max Unit Conditions Deep sleep with 32 KB SRAM retentiona a. The SRAM works at 0.8V in deep retention mode. IDeep1 - 1.8 - µA without 32K RCb b. Without 32K RC: The wakeup source is external signal from GPIO input, the internal 32K RC is disabled. Deep sleep with 64 KB SRAM retention IDeep2 - 2.4 - µA Deep sleep with 128 KB SRAM retention IDeep3 - 3.2 - µA Deep sleep with 256 KB SRAM retention IDeep4 - 5.7 - µA Deep sleep with 384 KB SRAM retention IDeep5 - 7.8 - µA Deep sleep without SRAM retention IDeep6 - 0.7 - µA Deep sleep with 32 KB SRAM retention IDeep7 - 2.2 - µA with 32K RCc c. With 32K RC: The wakeup source is 32K RC, it is enabled. Deep sleep with 64 KB SRAM retention IDeep8 - 2.8 - µA Deep sleep with 128 KB SRAM retention IDeep9 - 3.9 - µA Deep sleep with 256 KB SRAM retention IDeep10 - 6.1 - µA Deep sleep with 384 KB SRAM retention IDeep11 - 8.4 - µA Deep sleep without SRAM retention IDeep12 - 1.0 - µA Current in shutdown mode Idown - 0.45 - µA -

Datasheet for Telink TL3828 DS-TL3828-E5 57 Ver 0.8.0 Table 2-4 Digital Inputs/Outputs

2.4 AC Characteristics

Table 2-5 RSSI Characteristics Table 2-6 Crystal Characteristics Item Sym. Min. Typ. Max. Unit Conditions Input high voltage VIH 0.7*VDD - VDD V - Input low voltage VIL VSS - 0.3*VDD V - Output high voltage VOH 0.9*VDD - VDD V - Output low voltage VOL VSS - 0.1*VDD V - Item Sym. Min. Typ. Max. Unit Conditions RSSI range - -100 - 0 dBm - Resolution - - ±1 - dB - Item Sym. Min. Typ. Max. Unit Conditions

24 MHz Crystal

(parallel resonant) fNOM - 24 - MHz - Frequency tolerance fTOL -10 - +10 ppm - Load capacitance C1/C2 5 12 18 pF Tunable capacitance range to ground at XC1/XC2 terminals (single-end cap) Equivalent series resistance ESR - 50 100 Ohm - 32.768 kHz Crystal Nominal frequency (parallel resonant) fNOM - 32.768 - kHz - Frequency tolerance fTOL -100 - +100 ppm - Load capacitance C1/C2 6 9 12.5 pF Tunable capacitance range to ground at XC1/XC2 terminals (single-end cap)

Datasheet for Telink TL3828 DS-TL3828-E5 58 Ver 0.8.0 Table 2-7 RC Oscillator Characteristics Table 2-8 SAR ADC Characteristics

2.4.1 Audio Performance

2.4.1.1 Analog Input to Digital Output

Measurement conditions: Input sine wave with a frequency of 1kHz, measurement bandwidth 20Hz– Fs / 2 for Fs = 8 to 32 kHz, measurement bandwidth 20 Hz to 20 kHz for Fs = 44.1 kHz to 96 kHz, unless otherwise specified. Table 2-9 Analog Microphone / Line Input to ADC Path Equivalent series resistance ESR - 50 80 kOhm - Item Sym. Min. Typ. Max. Unit Conditions

24 MHz RC Oscillator

Nominal frequency fNOM - 24 - MHz - Frequency tolerance fTOL - 1 - % On chip calibration 32 kHz RC Oscillator Nominal frequency fNOM - 32 - kHz - Frequency tolerance fTOL - 0.5 - % On chip calibration Calibration time - - 3 - ms - Item Sym. Min. Typ. Max. Unit Conditions Differential nonlinearity DNL - - 1.5 LSB 10-bit resolution mode Integral nonlinearity INL - - 1.5 LSB 10-bit resolution mode Signal-to-noise and distortion ratio SINAD - 65 - dB fIN = 1 kHz, fS= 16 kHz Effective number of bits ENOB - 10.5 - bits - Sampling rate Fs - - 2 Msps - Parameter Test conditions Min. Typ Max. Unit SNR 500mVp input of 1.02 kHz, 0dB PGA gain - 86.1 - dB Item Sym. Min. Typ. Max. Unit Conditions

Datasheet for Telink TL3828 DS-TL3828-E5 59 Ver 0.8.0

2.4.2 I2S Timing Performance

The I2S timing sequence in master mode is shown as below. Figure 2-1 I2S Timing - Master Mode Measurement conditions: VDD = 3.3 V, T = 25°C, I2S_BCK = 3.072 MHz, LRCLK = 48 kHz, unless otherwise specified. Table 2-10 I2S Timing Sequence THD+N normal performance - -59.7 - dB Symbol Parameter Min. Typ Max. Unit tDL I2S_LR_OUT propagation delay from BCK falling edge 3.8 - 10 ns tDDA I2S_DAT_OUT propagation delay from BCK falling edge 2.2 - 10 ns tDST I2S_DAT_IN setup time to BCK rising edge 9 - - ns tDHT I2S_DAT_IN hold time from BCK rising edge 5 - - ns Parameter Test conditions Min. Typ Max. Unit I2S_BCK I2S_LR_OUT I2S_DAT_OUT I2S_DAT_IN tDST tDHT tDDA tDL

Datasheet for Telink TL3828 DS-TL3828-E5 60 Ver 0.8.0

2.5 I2C Timing Characteristics

The I2C timing sequence in fast mode is shown as below. Figure 2-2 I2C Timing in Fast Mode The I2C timing characteristics is listed as below. Table 2-11 I2S Timing Sequence Symbol Parameter Conditions Standard mode Fast mode Unit Min. Max. Min. Max. VIL LOW level input voltage - -0.5 0.3VDD -0.5 0.3VDD V VIH HIGH level input voltage - 0.7VDD VDD+0.5 0.7VDD VDD+0.5 V tSP Pulse width of spikes that must be suppressed by input filter - - - 0 50a ns fSCL SCL clock frequency - 0 100 0 400 kHz tLOW LOW period of the SCL clock - 4.7 - 1.3 - µs tHIGH HIGH period of the SCL clock - 4.0 - 0.6 - µs tr Rise time for both SDA and SCL - - 1000 20 300 ns tf Fall time for both SDA and SCL - - 300 20xVDD 300 ns tHD;STA Hold time for a repeated START condition After this period, the first clock pulse is generated. 4.0 - 0.6 - µs 70% SDA tHIGH tf SCL continue continue tr 30% 70% 30% tHD;DAT tSU;DAT tHD;STA tf S 1/fSCL 1st clcok cycle tr tLOW 9th clock SDA SCL tSU;STA Sr tHD;STA tSP 9th clock tBUF P S tSU;STO continued continued 70% 30% 70% 30%

Datasheet for Telink TL3828 DS-TL3828-E5 61 Ver 0.8.0

2.6 Storage Conditions

The SoC series is applicable to Moisture Sensitivity Level 3 (based on JEDEC Standard). 1. Calculated shelf life in sealed moisture barrier bag (MBB): 12 months at <40 °C and <90% relative humidity (RH) 2. Peak package body temperature: 260 °C 3. After bag is opened, devices that will be subjected to reflow solder or other high temperature process must be

• Mounted within: 168 hours of factory condi tions <=30°C/60% RH, or
• Stored at <10% RH 4. Devices require bake before mounting, if:
• Humidity Indicator Card reads >10% when read at 23 ± 5°C
• Both of the conditions in 3 are not met 5. If baking is required, devices may be baked for 24 hours at 125 ±5°C Note: lf device containers cannot be subjected to high temperature or shorter bake times are desired, please refer to IPC/JEDEC J-STD-033 for bake condition. tSU;STA Set-up time for a repeated START condition - 4.7 - 0.6 - µs tHD;DATI Input data hold time I2C bus devices 0 - 0 - µs tHD;DATO Output data hold time I2C bus devices - 3.45 - 0.9 µs tSU;DAT Data set-up time - 250 - 100 - ns tSU;STO Set-up time for STOP condition - 4.0 - 0.6 - µs tBUF Bus free time between a STOP and START condition - 4.7 - 1.3 - µs a. Input filters on the SDA and SCL inpu ts suppress noise spikes of less than 50 ns. Symbol Parameter Conditions Standard mode Fast mode Unit Min. Max. Min. Max.

Datasheet for Telink TL3828 DS-TL3828-E5 62 Ver 0.8.0

3 Reference Design

3.1 Reference Schematic of TL3828A

The reference schematic of TL3828A is shown as below. Figure 3-1 Reference Schematic of TL3828A

3.2 BOM (Bill of Material) of TL3828A

The bill of material table of TL3828A is listed as below. Table 3-1 BOM Table of TL3828A Quantity Reference Value PCB Footprint Description 1 C3 2.2uF 0402 CAP CER 16V X5R,±10% 1 C4 0.1uF 0402 CAP CER 16V X5R,±10% C5, C6, C7, C9, C10, C11, C12, C13 1uF 0402 CAP CER 16V X5R,±10%

2 C8, C14 10uF 0402 CAP CER 16V X5R,±10%

1 C15 0.22uF 0402 CAP CER 16V X5R,±10% 1 C16 4.7uF 0402 CAP CER 16V X5R,±10% Crystal Note:When using VBUS power supply,the VBAT pin needs to be connected to the VDDO3 pin. TL_VDDIOPE TL_VBUS TL_VDDIOPE TL_VBUS TL_VDDO3 TL_VDD1P2 TL_VDD1P2 TL_VDDO3 TL_VBUS TL_VDDO3 TL_VDD1P2 DFE252012F-6R8M=P2(6.8uH) Debug and Download 0402C12 1uF 0402 C111uF 0402C7 1uF 0402 NC 0402 1uF 0402 C13 1uF 0402 C6 1uF 0402 NC PL_V2.0 QFN80 TL3828A NC 60 AVDD1P2 42 DCDC_SW 41 GND 81 PA027 PA128 PA229 PA331 PA430 PA532 PA633 PA734 PB0 62PB1 63PB2 64PB3 65 PB4 46PB5 47PB6 48PB7 49 PC0 52PC1 53PC2 54PC3 55PC4 56 PC537 PC638 PC739 PD0 66PD1 67PD2 68PD3 69 PD417 PD516 PD615 PD714 PE019 PE120 PE221 PE322 PE423 PE524 PE625 PE726 PF0 70PF1 71PF2 72PF3 73PF4 74PF5 75PF6 76PF7 77PG0 78PG1 79PG2 80 PG31 PG42 PG53 PG64 PG75 PH06 PH17 PH28 PH39 PH410 PH511 PH612 PH713 POR 59 VBAT 44VBUS 45 VDD3DCDC40 VDDIOPE18 VDDO3 50 VDD_F 43 VDECUSB35 VDECCORE36 VLINE 61 VMID 51 XC1 57XC2 58 0402 10uF 0402 C15 0.22uF 0402 C14 10uF 0402C16 4.7uF 0402C10 1uF 24MHz-12pF-+/-10ppm 3 4 0402 0.1uF 0402 0402 2.2uF 0402C9 1uF TL_PG2 TL_PG1 TL_PG0 TL_PF7 TL_PF6 TL_PF5 TL_PF4 TL_PF3 TL_PF2 TL_PF1 TL_PF0 TL_PD3 TL_PD2 TL_PD1 TL_PD0 TL_PB3 TL_PH0 TL_PH1 TL_PH2 TL_PA0 TL_PD0 TL_PA1 TL_PD1 TL_PA2 TL_PD2 TL_PA3_DM TL_PD3 TL_PA4_DP TL_PD4_TDI TL_PA5 TL_PD5_TDO TL_PD6_TMS TL_PD7_TCK TL_PE0 TL_PE1 TL_PE2 TL_PE3 TL_PE4 TL_PE5 TL_PE6 TL_PE7 TL_PF0 TL_PF1 TL_PF2 TL_PF3 TL_PB0 TL_PB1 TL_PB2 TL_PB3 TL_PB4 TL_PB5 TL_PB6 TL_PB7 TL_PA6 TL_PA7_SWS TL_PC0 TL_PC1 TL_PC2_32K TL_PC3_32K TL_PC4 TL_PC5 TL_PC6 TL_PC7 TL_XC2 TL_XC1 TL_PF4 TL_PF5 TL_PF6 TL_PF7 TL_PH7 TL_PH6 TL_PH5 TL_PH4 TL_PH3 TL_PH2 TL_PH1 TL_PH0 TL_PG7 TL_PG6 TL_PG5 TL_PG4 TL_PG3 TL_PG2 TL_PG1 TL_PG0 TL_PH3 TL_PH4 TL_PH5 TL_PH6 TL_PH7 TL_PD7_TCK TL_PD6_TMS TL_PD5_TDO TL_PD4_TDI TL_PE0 TL_PE1 TL_PG7 TL_PA0 TL_PA1 TL_PA2 TL_PA4_DP TL_PA3_DM TL_PA5 TL_PA6 TL_PA7_SWS TL_PA7_SWS TL_PC5 TL_PC7 TL_PC6 TL_PE7 TL_PE6 TL_PE3 TL_PE2 TL_PE5 TL_PE4 TL_PG6 TL_PG5 TL_PG4 TL_PG3 TL_PB0 TL_PB1 TL_PB2 TL_PB7 TL_PB6 TL_PB5 TL_PB4 TL_XC2 TL_XC1 TL_PC4 TL_PC3_32K TL_PC2_32K TL_PC1 TL_PC0

Datasheet for Telink TL3828 DS-TL3828-E5 63 Ver 0.8.0 1 L1 DFE252012F- 6R8M=P2 (6.8uH) 1008L IND CHK 1MHz 1.2A 20% DCR 0.33 Exp:DFE252012F-6R8M=P2

1 R1 2Ω 0402 RES MF 2R 1/16W 1% 0402

1 U1 TL3828A QFN80

1.8-4.3V 1 Y1 24MHz-12pF-+/- 10ppm OSCCC250X320X110 XTAL SMD 3225, 24 MHz, Cl=12pF, total tol.±10ppm Exp:E1SB24E001D03E Quantity Reference Value PCB Footprint Description NOTE: For the 6.8uH inductor selection, it is recommended to:

• use wire wound type instead of multilayer type because wire wound inductors have higher quality and better temperature stability.
• select lower DCR (Direct Current Resistance), less than 0.5 Ohm.
• select larger rated current, at least 500 mA, and preferably higher. º Pay attention to the difference between saturation current and temperature-ri se current; the smaller of the two is typically specified as the rated current. º Pay attention to the curves of the inductance value and current, and select an inductor with minimal inductance derating at the required rated current.
• select higher Q value (quality factor), at least 25.
• Package: Inductors in 0806L or smaller packages offer limited options, while 1008L or larger packages provide a wi der selection.
• During validation, focus on the measured inductor current waveform, load-driving capability, peak current, efficiency, and other key performance parameters.

Datasheet for Telink TL3828 DS-TL3828-E5 64 Ver 0.8.0

3.3 Reference Schematic of TL3828B

The reference schematic of TL3828B is shown as below. Figure 3-2 Reference Schematic of TL3828B

3.4 BOM (Bill of Material) of TL3828B

The bill of material table of TL3828B is listed as below. Table 3-2 BOM Table of TL3828B Quantity Reference Value PCB Footprint Description 1 C1 2.2uF 0402 CAP CER 16V X5R,±10% 1 C2 0.1uF 0402 CAP CER 16V X5R,±10% C5, C6, C7, C8, C10, C11, C13, C15 1uF 0402 CAP CER 16V X5R,±10%

2 C9, C16 10uF 0402 CAP CER 16V X5R,±10%

1 C12 0.22uF 0402 CAP CER 16V X5R,±10% 1 C14 4.7uF 0402 CAP CER 16V X5R,±10% Crystal Note:When using VBUS power supply,the VBAT pin needs to be connected to the VDDO3 pin. TL_VBUS TL_VDDIOPE TL_VDDO3 TL_VDD1P2 TL_VDD1P2 TL_VDDO3 TL_VBUS TL_VDDO3 TL_VDD1P2 TL_VDDIOPE TL_VBUS 0402 NC 0402 C12 0.22uF 0402 R1 2R 0402 C15 1uF 24MHz-12pF-+/-10ppm 3 4 0402 0.1uF 0402 C14 4.7uF 0402 C16 10uF 0402 NC 0402C8 1uF DFE252012F-6R8M=P2(6.8uH) 12 0402 1uF 0402C7 1uF 0402C10 1uF PL_V2.0 QFN56A VDDIOPE TL3828B NC 45 AVDD1P227 DCDCSW26 GND 57 PA014 PA115 PA216 PA318 PA417 PA719 PB0 47PB1 48PB2 49PB3 50 PB4 31PB5 32PB6 33PB7 34 PC0 37PC1 38PC2 39PC3 40PC4 41 PC522 PC623 PC724 PD0 51 PD68 PD77 PE010 PE111 PE212 PE313 PF4 52PF5 53PF6 54PF7 55PG0 56 PG71 PH32 PH43 PH54 PH65 PH76 POR 44 VBAT 29VBUS 30 VDD3DCDC25 VDDIOPE9 VDDO3 35 VDD_F28 VDECCORE21 VDECUSB20 VLINE 46 VMID 36 XC1 42 XC2 43 0402C13 1uF 0402 1uF 0402 C11 1uF 0402 2.2uF Debug and Download 0402C9 10uF TL_XC2 TL_XC1 TL_PA7_SWS TL_PE1 TL_PE0 TL_PH3 TL_PH4 TL_PG7 TL_PE2 TL_PH5 TL_PH6 TL_PH7 TL_PD7_TCK TL_PD6_TMS TL_PE3 TL_PA0 TL_PD0 TL_PA1 TL_PA7_SWS TL_PA2 TL_PC5 TL_PC6 TL_PC7 TL_PG0 TL_PF4 TL_PF5 TL_PF6 TL_PF7 TL_PB3 TL_PB0 TL_PB2 TL_PB1 TL_XC2 TL_PB5 TL_PB7 TL_PB6 TL_PB4 TL_XC1 TL_PC0 TL_PC1 TL_PC2 TL_PC3 TL_PC4 TL_PA4_DP TL_PA3_DM TL_PA0 TL_PA1 TL_PA2 TL_PA3_DM TL_PA4_DP TL_PA7_SWS TL_PB1 TL_PB3 TL_PB2 TL_PB5 TL_PB6 TL_PB4 TL_PB0 TL_PB7 TL_PC1 TL_PC2 TL_PC3 TL_PC4 TL_PC5 TL_PC6 TL_PC0 TL_PC7 TL_PD0 TL_PD6_TMS TL_PD7_TCK TL_PE0 TL_PE2 TL_PE1 TL_PE3 TL_PF6 TL_PF7 TL_PF4 TL_PF5 TL_PG0 TL_PG7 TL_PH3 TL_PH4 TL_PH5 TL_PH6 TL_PH7

Datasheet for Telink TL3828 DS-TL3828-E5 65 Ver 0.8.0 1 L1 DFE252012F- 6R8M=P2 (6.8uH) 1008L IND CHK 1MHz 1.2A 20% DCR 0.33 Exp:DFE252012F-6R8M=P2

1 U1 TL3828B QFN56

384KB 1.8-4.3V 1 Y1 24MHz-12pF-+/- 10ppm OSCCC250X320X110 XTAL SMD 3225, 24 MHz, Cl=12pF, total tol.±10ppm Exp:E1SB24E001D03E Quantity Reference Value PCB Footprint Description NOTE: For the 6.8uH inductor selection, it is recommended to:

• use wire wound type instead of multilayer type because wire wound inductors have higher quality and better temperature stability.
• select lower DCR (Direct Current Resistance), less than 0.5 Ohm.
• select larger rated current, at least 500 mA, and preferably higher. º Pay attention to the difference between saturation current and temperature-ri se current; the smaller of the two is typically specified as the rated current. º Pay attention to the curves of the inductance value and current, and select an inductor with minimal inductance derating at the required rated current.
• select higher Q value (quality factor), at least 25.
• Package: Inductors in 0806L or smaller packages offer limited options, while 1008L or larger packages provide a wi der selection.
• During validation, focus on the measured inductor current waveform, load-driving capability, peak current, efficiency, and other key performance parameters.

Datasheet for Telink TL3828 DS-TL3828-E5 66 Ver 0.8.0

4 Memory, MCU and PMU

4.1 Memory

The SoC embeds up to 256 KB SRAM (including up to 256 KB with retention in deep sleep), up to 1536 KB NVM (including Flash and RRAM with details as below) as program memory. Table 4-1 Memory Allocation

4.1.1 SRAM

The total SRAM size of D25F ILM, D25F DLM, N22 ILM, and N22 DLM is up to 256 KB, including up to 256 KB with retention in deep sleep. The sizes of D25F ILM, D25F DLM, N22 ILM, and N22 DLM can be flexibly adjusted vi a software by modifying the D25F_SRAM_CFG (0x8014080c) and N22_SRAM_CFG (0x8014080d) registers (details refer to the clock related registers in Table 8-2). Please be noted, ILM can store both instruction and data while DLM can only store data. The memory map is shown below. Part Number NVM (KB) = Flash +RRAM Flash (KB) RRAM (KB) SRAM (KB) TL3828AE10T80R 1536 1024 512 256 TL3828BE10T56R 1536 1024 512 256

Datasheet for Telink TL3828 DS-TL3828-E5 67 Ver 0.8.0 Figure 4-1 Memory Map 0x20000000 0x0C000000 RSVD RSVD 0x24000000 N22_ILM 0x50080000 0x50000000 TRNG 0x80104000 DMA 0x80100400 RSVD 0x80100000 0x50100000 SWIRE 0x80101000 0x80100C00 RRAM_REG ADC_DIG 0x80101C00 0x80101400 LSPI_XIP 0x08000000 0x04000000 0x80100800 APBBRG 0x80140000 RSVD 0x80140080 0x80140040 UART0 0x801400C0 UART1 0x80140100 TRACE 0x80140140 TIMER 0x80140180 ALGM 0x801401C0 RSVD 0x80140200 STIMER 0x80140240 PWM 0x80141000 I2C 0x801402C0 0x80140280 eFuse 0x80140300 GPIO 0x80140E00 0x80140340 AUDIO 0x80140000 0x80120000 RSVD 0x80200000 0x80160000 RSVD 0x80240000 0x80210000 0x80260000 RSVD 0x87FFFF00 APB1_SPACE BROM APB0_SPACE RSVD SKE MAILBOX LSPI_REG BMC N22_DLM OSR_REG QDEC RSVD GSPI_XIP RSVD D25F_DLM 0x00080000 0x00000000 D25F_ILM AUDIO 0x80141400 APB0_SPACE DMA 0x80101800 RSVD 0x80103800 0x80103000 HASH 0x80102000 RSVD PKE 0x80104400 0x80110000 0x80114000 RRAM_XIP1 0x00600000 0x00500000 0x00100000 RRAM_XIP0 0x00400000 RSVD 0x88000000 GSPI_REG 0x8C000000 0x8BFFFF00 RSVD 0xC0000000 0xA3FFFF00 PLIC 0xC4400000 0xC4000000 PLMT 0xC6100000 0xC6000000 PLIC_SW 0xC6800000 0xC6400000 RSVD RSVD RSVD RSVD RSVD PLDM 0xC68FFFFF RSVD 0x80142000 0x80141600 I3C0 PEM 0x80142400 UART3 0x802400C0 0x80240080 UART2 0x80240040 UART4 0x80240100 0x80240000 APBBRG LIN1 0x80240180 0x80240140 TIMER_N22 QDEC1 0x802401C0 APB1_SPACE I2C1 RSVD 0x10000000 0x14000000 GSPI1_XIP 0x18000000 GSPI2_XIP 0x1C000000 GSPI3_XIP GSPI4_XIP 0x80188000 RSVD ZB 0x80180000 RSVD 0x80190000 0x80280000 USB0 0x80290000 RSVD GSPI1_REG 0x94000000 0x93FFFF00 RSVD GSPI2_REG 0x98000000 0x97FFFF00 RSVD GSPI3_REG 0x9C000000 0x9BFFFF00 RSVD GSPI4_REG 0xA0000000 0x9FFFFF00 RSVD 0x80240200 RZ 0x80240280 0x80240240 IR DC 0x802402C0 RSVD 0x80244000 RSVD 0x80241200 0x80241000 I3C1 0x80247FFF CAN1 SC_N22 0x80140380 0x801403C0 RSVD LIN0 0x80140500 0x80140540 RSVD 0x80140700 RSVD KEYS 0x80140740 0x80140800 RSVD SC 0x80140A00 0x80140C00 RSVD RSVD 0x80144000 CAN0 0x80147FFF ADC1_DIG 0x80104800

Datasheet for Telink TL3828 DS-TL3828-E5 68 Ver 0.8.0

4.1.2 RRAM

The SoC embeds total 512 KB RRAM. All read, write, and configuration operations of the RRAM are managed by the RRAM_CTRL module. The RRAM_CTRL module receives bus commands from the MCU and other masters, and controls the RRAM to perform read, write, and configuration operations. The RRAM_CTRL module includes three AHB bus interfaces: AHB_0, AHB_1, and AHB_REG. AHB_0 and AHB_1 support RRAM read operati ons only, AHB_REG can be used to configure internal registers of the RRAM_CTRL to issue various commands for controlling the RRAM. The interfaces between RRAM_CTRL and the RRAM include a parallel interface (par_*) and a serial interface (spi_*). The RRAM_CTRL features include:

• AHB_0 Interface: Supports read access to RRAM with 8-bit, 16-bit, and 32-bit read operations. Supports both si ngle and burst transfers, cache line prefetching (currently supports 1 or 2 lines), and cache line invalidation.
• AHB_1 Interface: Supports read access to RRAM with 8-bit, 16-bit, and 32-bit read operations. Supports both single and burst transfers, cache line prefetching (currently supports 1 or 2 lines), and cache line invalidation.
• AHB_REG Interface – Read Operations: Supports data read from RRAM by configuring internal control regi sters via AHB_REG to send read commands. The read length must be a multiple of 16 bytes. Execution status can be monitored in real time, and operations can be canceled at any time.
• AHB_REG Interface – Write Operations: Supports data write to RRAM by configuring internal control register configuration via AHB_REG. The write length must be a multiple of 16 bytes. Execution status can be monitored in real time, and operations can be canceled at any ti me.
• AHB_REG Interface – Control Commands: Allows sending a wide range of control commands to RRAM by accessing internal control registers via AHB_REG. Most RRAM control commands are supported.
• Interface to RRAM: RRAM_CTRL can issue commands to the RRAM through either a parallel interface (par_*) or a serial SPI interface (spi_*). The SPI interface only supports command issuance through internal register confi guration.
• Interrupt Feedback: Supports two main types of interrupt feedback, error interrupts and busy timeout interrupts.
• Clock: The main control clock is synchronized with the bus clock. The parallel interface operates at a divided clock (1/2/4 of the bus clock), while the serial interface operates at 1/4, 1/8, or 1/16 of the bus clock.
• Arbitration: Supports concurrent requests from three masters: regi ster read/write (via AHB_REG), AHB bus read from AHB_0 (u0), and AHB bus read from AHB_1 (u1). Arbitration is performed in real time with fixed priority: AHB_0 (u0) > AHB_1 (u1) > AHB_REG.

4.1.2.1 Block Diagram

The RRAM CTRL diagram is shown as below:

Datasheet for Telink TL3828 DS-TL3828-E5 69 Ver 0.8.0 Figure 4-2 Block Diagram of RRAM CTRL The RRAM_CTRL module consists of five main components:

• u0_AHB_SLV: A slave interface dedicated to reading RRAM data through the AHB_0 bus.
• u1_AHB_SLV: A slave interface dedicated to reading RRAM data through the AHB_1 bus.
• REG_SLV: Provides access to RRAM_CTRL internal registers. Enables read/write operations to RRAM, RRAM configuration, and read/write access to internal control regi sters through register-based commands via the AHB_REG bus.
• Internal Arbitration and Control Logic: Includes submodules such as REQ_ARB, REQMUX, and MEMIF to manage arbitration, request routing, and memory access control among different masters.
• RRAM Interface Modules: Includes RRAM_SPI_IF (serial interface) and RRAM_PAR_IF (parallel interface) to connect with the RRAM through either SPI or parallel si gnaling.

4.1.2.2 Parallel Interface

The parallel interface can be used for writing and reading data in the MTP space of the memory, and for accessing various registers within the memory. The table below shows the address ranges of the three AHB buses: Table 4-2 Address Ranges of AHB Buses Bus Address Range Assigned by BMC Actual Valid Range MTP Valid Range Internal Usage Range AHB_SLV0 0x00400000 ~ 0x004FFFFF 0x400000 ~ 0x4863FF 0x400000 ~ 0x47FFFF 0x480000 ~ 0x4863FF AHB_SLV1 0x00500000 ~ 0x005FFFFF 0x500000 ~ 0x5863FF 0x500000 ~ 0x57FFFF 0x580000 ~ 0x5863FF ABH_IF CACHE CMD_OUT cmd_fifo addr_fifo u1_AHB_SLV ABH_REG_IF RRAM_REG CMD_OUT spi_if cmd_fifo tx_fifo rx_fifo REQ_ARB REQMUX MEMIF AHB_0 AHB_1 AHB_REG REG_SLV u0_AHB_SLV spi_* error_irq par_* grant/req

Datasheet for Telink TL3828 DS-TL3828-E5 70 Ver 0.8.0 1. AHB_SLV Read MTP Read MTP data via AHB_SLV0, with MTP address range 0x400000~0x47FFFF (D25F), or read MTP data via AHBS_LV1, with MTP address range 0x500000~0x57FFFF (N22). 2. MTP Read Step 1 Write the start address of the read operation to the PAR_AIN register. Step 2 Write the length of data to be read (in bytes) to the DATA_LEN register. Step 3 Write 5’B01011 to the PAR_MODE register. Step 4 Read the RX_READY register and ensure the value i s 1 (indicating data in rd_fifo is ready). (Optional step, requires interrupt function support) Read register 0x80101004; if the value is 0x0e22, it indicates a transmission ERROR, and the function should be aborted. Step 5 Read the data from the RDATA register. Supports 8/16/32-bit reads. For 8/16-bit reads, the address should be incremented accordingly. Step 6 Repeat Step 4 to Step 5 unti l the entire data length (DATA_LEN) has been read. 3. MTP Write Step 1 Write the target write address to the PAR_AIN register. Step 2 Write the length of data to be written (in bytes) to the DATA_LEN register. Step 3 Write 5’b00010 to the PAR_MODE register. Step 4 Write data to the RDATA register. Supports 8/16/32-bit writes. For 8/16-bit writes, the address should be incremented accordingly. Step 5 Continuously read the TX_READY regi ster and ensure the value is 1 (to confirm data in txfifo has been transmitted). (Optional step, requires interrupt function support) Read register 0x80101004; if the value is 0x0e22, it indicates a transmission ERROR, and the function should be aborted. Step 6 Repeat Step 4 to Step 5 until the entire data length (DATA_LEN) has been written. Step 7 Continuously read the CTRL_BUSY register and ensure the value i s 0, indicating the operation has completed. 4. Enter MTP Mode Step 1 Write 5’B00101 to the PAR_MODE register. Step 2 Read the CTRL_BUSY register and confirm the value is 0, indicating the command has been executed. 5. READ Status Rdgister Step 1 Write 5’B10111 to the PAR_MODE register. Step 2 Read the CTRL_BUSY register and confirm the value is 0, indicating the command has been executed. Step 3 Read the READREG_READY register and confirm the value is 1, indicating the register read i s executed. Step 4 Read the RRAM_CFG_REG_RDATA register, the value read is the result. AHB_REG 0x00101000 ~ 0x001013FF 0x101000 ~ 0x10103F - - Bus Address Range Assigned by BMC Actual Valid Range MTP Valid Range Internal Usage Range

Datasheet for Telink TL3828 DS-TL3828-E5 71 Ver 0.8.0 6. Write Status Register Step 1 Write the value to be written into the RRAM_CFG_REG_WDATA register. NOTE: Only BIT[3], BIT[4], BIT[5], BIT[6], and BIT[7] of the status register can be cleared to 0. If the corre- sponding bit is set to 0, the clear operation will be executed. If set to 1, the bit will retain its original value. Step 2 Write 5’B00001 to the PAR_MODE register. Step 3 Read the CTRL_BUSY register and confirm the value i s 0, indicating the command has been executed. 7. Write ENABLE Step 1 Write 5’B00110 to the PAR_MODE register. Step 2 Continuously read the CTRL_BUSY register until the value is 0, indicating the command has been executed. 8. Write DISABLE Step 1 Write 5’B00100 to the PAR_MODE register. Step 2 Read the CTRL_BUSY register and confirm the value is 0, indicating the command has been executed. 9. Write and Read CC/CR Registers Taking CC_LOCK as an example; for CR_LOCK, simply replace the correspondi ng PAR_MODE value. Write: Step 1 Write the value to be written into the RRAM_CFG_REG_WDATA register. Step 2 Write 5’B01010 to the PAR_MODE register (WRITE CC LOCK). Step 3 Read the CTRL_BUSY register and confirm the value is 0, indicating the command has been completed. Read: Step 1 Write 5’B11010 to the PAR_MODE register (READ CC LOCK). Step 2 Read the CTRL_BUSY register and confirm the value is 0, indicating the command has been executed. Step 3 Read the READREG_READY register and confirm the value is 1, indi cating the register read is executed. Step 4 Read the RRAM_CFG_REG_RDATA register, the value read is the result. 10. Write and Read MP Register Write: Step 1 Write the value to be written into the RRAM_CFG_REG_WDATA register. Step 2 Write 5’B01101 to the PAR_MODE register. Step 3 Read the CTRL_BUSY register and confirm the value is 0, indicating the command has been executed. Read: Step 1 Write 5’B11101 to the PAR_MODE register. Step 2 Read the READREG_READY register and confirm the value is 1, indi cating the register read is complete. Step 3 Read the RRAM_CFG_REG_RDATA register, the value read is the result. 11. Write TREG/CREG Register

Datasheet for Telink TL3828 DS-TL3828-E5 72 Ver 0.8.0 Step 1 Write the target address to the PAR_AIN register. Step 2 Write the data to be written into the RRAM_CFG_REG_WDATA register. Step 3 Write 5’h18 to the PAR_MODE register (refer to the table above for the specific command). Step 4 Read the CTRL_BUSY register and confirm the value is 0, indicating the command has been executed. 12. Read TREG/CREG Register Step 1 Write the target address to the PAR_AIN register. Step 2 Write 5’h19 to the PAR_MODE register (refer to the table above for the specific command). Step 3 Read the CTRL_BUSY register and confirm the value i s 0, indicating the command has been executed. Step 4 Read the READREG_READY register and confirm the value is 1, indicating the returned value is valid. Step 5 Read the RRAM_CFG_REG_RDATA register; the value read is the result. 13. Run MBIST Step 1 Write the target address into the PAR_AIN register. Step 2 Write 16’h0001 into the DATA_LEN register. Step 3 Write 5’b11111 into the PAR_MODE register. Step 4 Write data into the DATA register. 8/16/32-bit writes are supported. For 8/16-bit, the address must i ncrement accordingly until 128 bits are written. Step 5 Continuously read the CTRL_BUSY register until the value is 0, indicating the operation has been completed. 14. MTP Read Using DMA Step 1 Write the start address of the read operation into the PAR_AIN register. Step 2 Write the data length to be read (in bytes) into the DATA_LEN register. Step 3 Write 5’B01011 into the PAR_MODE register. Step 4 Configure the DMAC and initiate the DMA operati on. Step 5 Wait for the DMA operation to complete. Step 6 Read the RX_READY register and confirm the value is 0. If not, use RXFIFO_CLR to clear residual data in the RX FIFO. 15. MTP Write Using DMA Step 1 Write the start address of the write operation into the PAR_AIN register. Step 2 Write the data length to be written (in bytes) into the DATA_LEN register. Step 3 Write 5’b00010 into the PAR_MODE register. Step 4 Configure the DMAC and i nitiate the DMA operation. Step 5 Wait for the DMA operation to complete. Step 6 Read the CTRL_BUSY register and confirm the value is 0 (to ensure the RRAM has completed writing). Step 7 Read the TX_READY register and confirm the value is 1. If not, use TXFIFO_CLR to clear residual data in the TX FIFO.

Datasheet for Telink TL3828 DS-TL3828-E5 73 Ver 0.8.0

4.1.2.3 SPI Instruction Set

1. Read Status Register Step 1 Confirm that the SPI_ENABLE register is set to 1, indicating that the SPI interface of the RRAM controller is enabled. Step 2 Write the number of bytes required for the command into the SPI_CNT register. This number must be greater than 2 (this value is the total number of bytes to be sent and received for the command). Step 3 Write 8’h05 (i.e., the command code) into the SPI_WDATA register. Step 4 Read the SPI_TX_DONE regi ster; when the value is 1, it indicates that SPI transmission is complete. Step 5 Read SPI_RDATA (this step serves as the read trigger to start the read operation). Step 6 Read SPI_RDATA_VALID; when the value is 1, it indicates that SPI reception is complete. Step 7 Read SPI_RDATA again to get the received data. Step 8 Repeat Steps 6–7 until the number of bytes specified by SPI_CNT has been read. 2. Write Status Register Step 1 Confirm that the SPI_ENABLE register is set to 1, i ndicating that the SPI interface of the RRAM controller is enabled. Step 2 Write the number of bytes required for the command into the SPI_CNT register. This value should be Step 3 Write 8’h01 (i.e., the command code) into the SPI_WDATA register. Step 4 Read SPI_TX_DONE; when the value is 1, it indicates that SPI transmission is complete. Step 5 Write the data to be sent (i.e., the value to be written to the status register) into the SPI_WDATA register. Step 6 Read SPI_TX_DONE agai n; when the value is 1, it indicates that SPI transmission is complete. 3. Enter MTP Mode Step 1 Confirm that the SPI_ENABLE register is set to 1, indicating that the RRAM controller has enabled the SPI interface. Step 2 Write the required number of bytes for the command into the SPI_CNT register. The byte count for this command is 1. Step 3 Write 8’h17 (i.e., the command code) into the SPI_WDATA register. Step 4 Read the SPI_TX_DONE register; when the value i s 1, it indicates that SPI transmission is complete. 4. Write ENABLE Step 1 Confirm that the SPI_ENABLE register is set to 1, indicating that the RRAM controller has enabled the SPI interface. Step 2 Write the required number of bytes for the command into the SPI_CNT register. The byte count for this command is 1. Step 3 Write 8’h06 (i.e., the command code) into the SPI_WDATA register. Step 4 Read the SPI_TX_DONE register; when the value is 1, it indicates that the SPI transmi ssion is complete.

Datasheet for Telink TL3828 DS-TL3828-E5 74 Ver 0.8.0 Step 5 Perform a Read Status Register operation repeatedly until the RRAM busy bit in the status register is cleared to 0. 5. Write DISABLE Step 1 Confirm that the SPI_ENABLE register is set to 1, indicating that the RRAM controller has enabled the SPI interface. Step 2 Write the required number of bytes for the command into the SPI_CNT register. The byte count for this command is 1. Step 3 W rite 8’h04 (i.e., the command code) into the SPI_WDATA register. Step 4 Read the SPI_TX_DONE register; when the value is 1, it indicates that the SPI transmission is complete. 6. Write DATA Step 1 Confirm that the SPI_ENABLE register is set to 1, indicating that the RRAM controller has enabled the SPI interface. Step 2 Write the number of bytes required to execute the command into the SPI_CNT register. For this command, the byte count is 20. Step 3 Write 8’h02 (i.e., the command code) into the SPI_WDATA register. Step 4 Read the SPI_TX_DONE regi ster; when the value is 1, it indicates that SPI data transmission is complete. Step 5 Repeat Steps 3–4 to sequentially transmit the 24-bit write address and the 128-bit write data. Step 6 Perform the Read Status Register operation repeatedly until the RRAM busy bit in the status register is cleared to 0. 7. Read DATA Step 1 Confirm that the SPI_ENABLE register is set to 1, indicating that the RRAM controller has enabled the SPI interface. Step 2 Write the number of bytes required to ex ecute the command into the SPI_CNT register. For this command, the byte count is 20. Step 3 Write 8’h03 (i.e., the command code) into the SPI_WDATA register. Step 4 Read the SPI_TX_DONE register; when the value is 1, it indicates that SPI data transmission is complete. Step 5 Repeat Steps 3–4 to sequentially transmit the 24-bit read address. Step 6 Read SPI_RDATA (this step acts as a read trigger to start data retrieval). Step 7 Read the SPI_RDATA_VALID register; when the value is 1, it indicates that SPI data reception is complete. Step 8 Read SPI_RDATA to obtai n the data received by SPI. Step 9 Repeat Steps 7–8 until the number of bytes defined in SPI_CNT is fully received.

4.1.2.4 RRAM_CTRL Configurable Functions

1. CACHE_BYPASS

Datasheet for Telink TL3828 DS-TL3828-E5 75 Ver 0.8.0 This function corresponds to the BYPASS_CACHE register. When this register is set to 1, the CACHE will not prefetch data during AHB_SLV read operations in the CTRL. Conversely, when the register is set to 0, the CACHE will operate normally and prefetch data. 2. PAR_CLK Clock Gating This function corresponds to the CFG_PAR_CLK_GATE_EN register. When this register is set to 1, cloc k gati ng for PAR_CLK is enabled, meaning the clock will only be provided when the RRAM requires it. If the register is set to 0, clock gating is disabled, and the PAR_CLK clock will be continuously supplied. 3. AHB_SLV Ready Signal Configuration under ERROR This function corresponds to the CFG_AHB_READY_HIGHORLOW register. When an ERROR occurs in the CTRL, or when SPI is enabled, setting this register to 1 wi ll force the ready signal on the AHB_SLV bus to remain high. In this case, RDATA will return a fixed value, which can be configured via the ERROR_AHB_RDATA register (default value: DEADBEFF). When the CFG_AHB_READY_HIGHORLOW register is set to 0, the ready signal is held low. 4. WRITE/READ CMD Interrupt When executing write data or read data commands through REGSLV, to prevent system deadlock caus ed by mi smatches between the configured transfer length and the actual amount of transferred data, the operation can be interrupted by writing 1 to the TXFIFO_CLR/RXFIFO_CLR register. This will abort the execution of the write or read command and clear the corresponding FIFO data. The specific interrupt procedure is as follows: After executing a write data or read data operation, Step 1 Read TX_READY/RX_READY to confi rm the value is 1. Step 2 Write 1 to the TXFIFO_CLR/RXFIFO_CLR register. (If unsure whether the current operation is WRITE or READ, write 1 to both TX_READY and RX_READY.) Step 3 Wait until bits [2:0] (i.e., CLR_BUSY, RRAM_BUSY, CTRL_BUSY) in register 0x1C are all cleared to 0. 5. DMA WRITE/READ CMD Interrupt After performing the DMA write data or DMA read data operation: Step 1 Disable the correspondi ng DMA enable bit. Step 2 Wait until the value of register 0x1C[5] and [7] is 0. Step 3 Read TX_READY/RX_READY to confirm the value is 1. Step 4 Write 1 to the TXFIFO_CLR/RXFIFO_CLR register. (If unsure whether the current operation is WRITE or READ, write 1 to both TX_READY and RX_READY.) Step 5 Wait until the value of bits [2:0] (i.e., CLR_BUSY, RRAM_BUSY, CTRL_BUSY) in register 0x1C is 0. 6. M ulti boot Function This function ensures that programs loaded to different addresses in the RRAM can run correctly. For example, if a program is designed to start at address 0x00400000, but it is placed at the actual address 0x00410000, the program will not run correctly without the multiboot function. When the multiboot function is enabled, it allows the MCU to read from 0x00400000 and access the program at the actual address 0x 00410000. Testing the above example involves the following steps: Step 1 Write data to the RRAM address range 0x00410000~0x0041FFFF. Step 2 Configure the CORE0_SPACE_SIZE register to 8'h10.

Datasheet for Telink TL3828 DS-TL3828-E5 76 Ver 0.8.0 Step 3 Configure the CORE0_SPACE_OFFSET register to 8'h10. Step 4 Read data from RRAM address 0x00400000~0x0040FFFF, and compare it with the written data to ensure they match. In this example:

• CORE0_SPACE_SIZE indicates the size of the space to be mapped.
• CORE0_SPACE_START indicates the starting address of the space to be mapped.
• CORE0_SPACE_OFFSET indicates the offset address of the actual memory address.

4.1.2.5 Interrupt

There are two main types of interrupts related to RRAM: the RRAM ERROR interrupt, controlled by RRAM, and the busy_timeout interrupt, controlled by RRAM_CTRL. (1) RRAM ERROR Interrupt This type of interrupt is controlled by RRAM and includes five different error interrupts, as shown in the table below: Table 4-3 Status Register Interrupt Clearing Function: Step 1 First, confirm which category of interrupt it is. Read register 0x8010101d[0]. If the value i s 1, it indicates the interrupt belongs to the RRAM ERROR; if the value is 0, it indicates the interrupt belongs to the busy_timeout. Step 2 Determine if the operation before the interrupt was a large read or write operation by reading the CTRL_BUSY signal. If it is 0, go to Step 5. If it is 1, it means the REGSLV currently has an ongoing operation. If DMA is involved, stop the DMA. (Optional Operati on): Write 0x0e22 to register 0x80101004 to allow the read/write function to exit. Value Field Function Type Default State

Description

7 ERRORW Write Error Writable to 0 0

Set to 1 when write operation finishes with errors. To clear the bit write 0 using Write Status Register.

6 ERRORR Read Error Writable to 0 0

Set to 1 when read operation happens with ECC errors. To clear the bit write 0 using Write Status Register.

5 ERRORP

Set to 1 when write to a locked or protected memory region is attempted. To clear the bit, write 0 using Write Status Register.

4 ERRORA

Set to 1 when write to an unpopulated memory region is attempted. To clear the bit, write 0 using Write Status Register.

3 ERRORM MBIST Error Writable to 0 0

Set to 1 when MBIST operation finishes with errors. Set to 1 when MBIST operation finishes with errors.

Datasheet for Telink TL3828 DS-TL3828-E5 77 Ver 0.8.0 Step 3 Write 1 to the TXFIFO_CLR/RXFIFO_CLR register. Step 4 Repeatedly read CLR_BUSY and CTRL_BUSY three times and check the final reading. If all values are 0, go to Step 5. If any of the values are non-zero, go to Step 8. Step 5 Confirm the RRAM_ERROR interrupt cause by performing a Read Status Register operation to get the 8-bit return value. Check if the corresponding bit in the table i s 1 to determine the specific error cause. (For example, if [7] = 1, it indicates a Write Error.) Step 6 (Optional) Read the ERROR_ADDR register to find the address where the error occurred. Step 7 Perform a Write Status Register operation to clear the interrupt by writing 0 to the corresponding bit of the error type. Step 8 Restart the RRAM and reset the RRAM_CTRL. NOTE: To avoid while(flag){} loops i n the interrupt function, in Step 5 (Read Status Register) and Step 8 (Write Status Register), where a while loop is involved, it is recommended to execute the while loop multiple times (recommended 4 times) as a replacement or use break for exit handling. (2) BUSY_TIMEOUT Interrupt This type of interrupt is controlled by RRAM_CTRL. The CTRL internal register continuously counts during the period when the RRAM busy signal i s high. If the count exceeds a threshold, it triggers the interrupt. The threshold can be configured via the BUST_TIMEOUT_LIM register. Step 1 First, confirm which category of interrupt it is. Read register 0x8010101d[1]. If the value is 1, it indicates the interrupt belongs to the RRAM ERROR; if the value is 1, it indicates the interrupt belongs to the busy_timeout. Step 2 (Optional) Read the ERROR_ADDR regi ster to find the address where the error occurred. Step 3 (Optional) Read register 0x8010101c[1]. If the value is 0, you can clear the interrupt using the busy_timeout_irq_clr register. Step 4 Restart the RRAM and reset the RRAM_CTRL.

4.1.2.6 Register Description of RRAM_CTRL

The RRAM_CTRL related registers are listed as following, the base address of the following registers is 0x80101000. Table 4-4 Register Configuration of RRAM_CTRL Address Offset Name Type Description Reset Value 0x00 RWDATA0 R/W [7:0]: rram_read_or_write_data[7:0] 0x00 0x01 RWDATA1 R/W [7:0]: rram_read_or_write_data[15:8] 0x00 0x02 RWDATA2 R/W [7:0]: rram_read_or_write_data[23:16] 0x00 0x0 3 RWDATA3 R/W [7:0]: rram_read_or_write_data[31:24] 0x00 0x04 ERROR_AHBSLV_RDATA0 R/W [7:0]: error_ahbslv_rdata[7:0] 0xef

Datasheet for Telink TL3828 DS-TL3828-E5 78 Ver 0.8.0 0x05 ERROR_AHBSLV_RDATA1 R/W [7:0]: error_ahbslv_rdata[15:8] 0xbe 0x06 ERROR_AHBSLV_RDATA2 R/W [7:0]: error_ahbslv_rdata[23:16] 0xad 0x07 ERROR_AHBSLV_RDATA3 R/W [7:0]: error_ahbslv_rdata[31:24] 0xde 0x08 ERROR_ADDR_SAVE0 R [7:0]: error_addr_save[7:0] 0x00 0x09 ERROR_ADDR_SAVE1 R [7:0]: error_addr_save[15:8] 0x00 0x0a CORE0_SPACE_START R/W [7:0]: core0_space_start 0x00 0x0b CORE0_SPACE_SIZE R/W [7:0]: core0_space_size 0x00 0x0c CORE0_SPACE_OFFSET R/W [7:0]: core0_space_offset 0x00 0x0d CORE1_SPACE_START R/W [7:0]: core1_space_start 0x00 0x0e CORE1_SPACE_SIZE R/W [7:0]: core1_space_size 0x00 0x0f CORE1_SPACE_OFFSET R/W [7:0]: core1_space_offset 0x00 0x10 PAR_AIN0 R/W [7:0]: par_ain[7:0] 0x00 0x11 PAR_AIN1 R/W [7:0]: par_ain[15:8] 0x00 0x13 PAR_MODE R/W [4:0]: par_mode[4:0] 0x00 0x14 DATA_LEN0 R/W [7:0]: DATA_LEN[7:0] 0x00 0x15 DATA_LEN1 R/W [7:0]: DATA_LEN[15:8] 0x00 0x16 RRAM_CFG_REGISTER_R WDATA0 R/W [7:0]: read_or_write_reg[7:0] 0x00 0x17 RRAM_CFG_REGISTER_R WDATA1 R/W [7:0]: read_or_write_reg[15:8] 0x00 0x18 RRAM_CTRL_CFG R/W [0]: rram_cipher_bypass [1]: cfg_ahbslv_error_ready_highorlow [2]: cfg_par_clk_gate_en [3]: cfg_error_irq_mask [4]: cfg_busy_timeout_irq_mask 0x0 0x1a CLR W [0]: txfifo_clr [1]: rxfifo_clr [2]: u0_cache_clr [3]: u1_cache_clr 0x0 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 79 Ver 0.8.0

4.1.3 Flash

The internal flash mainly supports page program, sector/block/chip erase operations, and deep power down operation. Please refer to the corresponding SDK for flash memory operation details. Please note that for 1024 KB embedded flash, the flash area ranging from 0xF8000 to 0xFFFFF is reserved for Telink internal use. 0x1b ERROR_IRQ W [0]: busy_timeout_irq_clr 0x0 0x1c STATE_REG R [0]: ctrl_busy [1]: rram_busy [2]: clr_busy [3]: tx_ready [4]: rx_ready [6]: readreg_ready [5]: rxdma_cyc [7]: txdma_cyc 0x08 0x1d ERROR_STATE R [0]: rram_error_r [1]: rram_busy_timeout_r 0x0 0x1e BUSY_TIME_LIM0 R/W [7:0]: busy_timeout_lim[7:0] 0xff 0x1f BUSY_TIME_LIM1 R/W [3:0]: busy_timeout_lim[11:8] 0xf 0x20 RRAM_SPI_ST R/W [0]: spi_enable [1]: spi_busy 0x0 0x21 RRAM_SPI_CFG R/W [1:0]: spi_div_clk_cfg (RW) 2'b00: 4 div clk; 2'b01: 8 div clk; 2'b10: 16 div clk. [6:2]: spi_cnt (RW) [7]: spi_tx_done (R) 0x80 0x22 RRAM_SPI_WDATA W [7:0]: rram_spi_wdata[7:0] 0x00 0x24 RRAM_SPI_RDATA R/W [7:0]: rram_spi_rdata[7:0] 0x00 0x25 RRAM_SPI_READ_ST R/W [0]: rram_spi_rdata_valid [5:1]: rram_spi_rx_cnt[4:0] 0x00 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 80 Ver 0.8.0 MCU uses the separate MSPI_CLK frequency to load instructions, and adopts flash driver to access (read/write) flash with the same speed. 4.1.4 eFuse The non-volatile eFuse is defined as below: Table 4-5 eFuse Definition Name Length (Bit) Length (Byte) Description Reserved [2047:1768] 35 Reserved for Telink internal use MAC_ADDR [1767:1704] 8 64 bits Telink-Assigned MAC Address chip_id [1703:1576] 16 Chip ID, unmodifiable Reserved [1575:1256] 40 Reserved for Telink internal use Security_Feature [1255:1224] 4 [31] deep dont skip secure boot [30] reboot dont skip secure boot [29:28] pub_key_hash selection: 00: use pub_key1_hash 01: use pub_key2_hash 02/03: use pub_key3_hash [27:26] Reserved for Telink internal use [25] mode selection, 0: normal mode, 1: secure boot mode (Signature Verification) [24:15] Reserved for Telink internal use [14:0]: descriptor flash address is specified by Telink Reserved [1223:968] 32 Reserved for Telink internal use pub_key3_hash [967:712] 32 Public key hash, is the hash calculated over the public key used by customer for firmware signature verification. Once provisioned by the customer, it cannot be changed. It is used by the chip to verify that the correct public key for firmware signature verification is used. pub_key2_hash [711:456] 32 Hash public key pub_key1_hash [455:200] 32 Hash public key NOTE:

• By default, the page write is 256 bytes at a time and it is not recommended to write less than 255 bytes data. For example, if users want to rewrite 64 to 128 bytes in one page, the first step is to read total 256 bytes of a page, then replace the 64 to 128 bytes data, and rewrite the corrective 256 bytes to program again after page erase.

Datasheet for Telink TL3828 DS-TL3828-E5 81 Ver 0.8.0

4.1.5 Unique ID

For chip identification and traceability, the SoC is preloaded with 128-bit Unique ID (UID). This UID can be read via the interface in SDK.

4.2 MCU

The SoC integrates dual-core system with two powerful 32-bit RISC-V MCUs to support various new features and customization.

4.2.1 D25F Core

The main system embeds a 32-bit RISC-V micro-controller, features are listed as following: flash_key [199:160] 5 used for Firmware Encryption debug_key [159:32] 16 used to re-enable debug interface Interface functions [31:0] 4 These bits are used for function configuration on die level by HW or SW. [31:24] Reserved [23] key_lock 1'b0: key can be read 1'b1: key can't be read [22] flash_encrypt_enable, 1'b0: flash encryption disable 1'b1: flash encryption enable [21:18] Reserved for Telink internal use [17] dbg_unlock_boot_mode: 1'b0: debug ports can be unlock during anytime 1'b1: debug ports only can be un-lock during first stage bootloader. [16] Reserved for Telink internal use [15] sws_dbg_disable, SWS function disable: 1'b0: enable; 1'b1: disable. [14] jtag_dbg_disable, JTAG function disable: 1'b0: enable; 1'b1: disable. [13:0] Reserved for Telink internal use Name Length (Bit) Length (Byte) Description

Datasheet for Telink TL3828 DS-TL3828-E5 82 Ver 0.8.0 1. Maximum running speed up to 192 MHz 2. 5-stage in-order execution pipeline 3. Fast Hardware multiplier 4. Hardware divider 5. Dynamic branch prediction

• 128-entry branch target buffer (BTB) 6. Performance monitors 7. Misaligned memory accesses 8. RISC-V RV32I base integer instruction set 9. RISC-V RVC standard extension for compressed instructions 10. RISC-V RVM standard extension for integer multi plication and division 11. RISC-V RVA standard extension for atomic instructions 12. RISC-V “F” standard extensions for single-precision floating-point 13. DSP extension 14. Instruction cache 8 KB, Data cache 4 KB 15. Machine mode and User mode 16. 8 entries PMP (Physical Memory Protection)

4.2.1.1 Physical Memory Protection

To support secure processing and contain faults, it is desirable to limit the physical addresses accessible by software running on a hart (hardware thread). Physical memory protecti on (PMP) unit provides hart machine- mode control registers to allow physical memory access privileges (read, write, execute) to be specified for each physical memory region. PMP checks are applied to all accesses when the hart is running in U modes, and for loads and stores when the MPRV bit is set in the m-status register and the MPP field in the m-status register contains U. Optionally, PMP checks may addi tionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them without a system reset. PMP violations are always trapped precisely at the processor. PMP entries are described by an 8-bit configuration register and one 32 bit address register. 8 PMP entries are supported. PMP CSRs are only accessible to M-mode. NOTE: The abbreviations for the Type column of register table are summarized below:

• RO: read only
• WO: write only
• R/W: readable and writable
• W1C: write 1 to clear
• W1S: write 1 to set
• Volatile: can be modified unexpectedly

Datasheet for Telink TL3828 DS-TL3828-E5 83 Ver 0.8.0 Table 4-6 PMP Configuration Registers The 8-bit PMPiCFG is described as below. Table 4-7 PMPiCFG Description CSR Address CSR Name Bit Description 0x3A0 pmpcfg0 [31:24] PMP3CFG [23:16] PMP2CFG [15:8] PMP1CFG [7:0] PMP0CFG 0x3A1 pmpcfg1 [31:24] PMP7CFG [23:16] PMP6CFG [15:8] PMP5CFG [7:0] PMP4CFG Field Name Bit Description Type Reset L [7] Write lock and permission enforcement bit for Machine mode. 0: Machine mode writes to PMP entry registers are allowed. R/W/X permissions apply to U modes 1: For PMP entry i, writes to PMPiCFG and PMPADDRi are ignored. Additionally, if PMPiCFG.A is set to TOR, writes to pmpaddri-1 are ignored as well. As for Permission enforcement, R/W/X permissions apply to all modes. This bit can only be cleared to 0 with a system reset W1S 0 Reserved [6:5] Reserved - - A [4:3] Address matching mode. 0: OFF: Null region. 1: TOR: Top of range. For PMP entry 0, it matches any address A < pmpaddr0. For PMP entry i, it matches any address A such that pmpaddri > A >=pmpaddri-1. But the 4-byte range is not supported. 2: Reserved. 3: NAPOT: Naturally aligned power-of-2 region, >= 8 bytes. This mode makes use of the low-order bits of the associated address register to encode the size of the range. See Table 4-9 for range encoding from the value of a PMP address register. R/W 0

Datasheet for Telink TL3828 DS-TL3828-E5 84 Ver 0.8.0 Table 4-8 PMP Address Registers Each PMP address register encodes bits 33–2 of a 34-bit physical address, as shown in the register format. The encoding is described in Table 4-9. The “a” in the table represents one bit address, with arbitrary values. Table 4-9 D25 NAPOT Range Encoding in PMP Address and Configuration Registers X [2] Instruction execution control. 0: Instruction execution is not allowed. 1: Instruction execution is allowed R/W 0 W [1] Write access control. 0: Write accesses are not allowed. 1: Write accesses are allowed. R/W 0 R [0] Read access control. 0:Read accesses are not allowed 1:Read accesses are allowed. R/W 0 CSR Address CSR Name Bit Description Type Reset 0x3B0 pmpaddr0 [31:0] PMP entry 0 address register R/W 0 0x3B1 pmpaddr1 [31:0] PMP entry 1 address register R/W 0 0x3B2 pmpaddr2 [31:0] PMP entry 2 address register R/W 0 0x3B3 pmpaddr3 [31:0] PMP entry 3 address register R/W 0 0x3B4 pmpaddr4 [31:0] PMP entry 4 address register R/W 0 0x3B5 pmpaddr5 [31:0] PMP entry 5 address register R/W 0 0x3B6 pmpaddr6 [31:0] PMP entry 6 address register R/W 0 0x3B7 pmpaddr7 [31:0] PMP entry 7 address register R/W 0 Register Content Match Size (Byte) aaaa…aaa0 8 (23) aaaa…aa01 16 (24) aaaa…a011 32 (25) …… …… aa01…1111 232 Field Name Bit Description Type Reset

Datasheet for Telink TL3828 DS-TL3828-E5 85 Ver 0.8.0

4.2.2 N22 Core

The subsystem contains a 32-bit RISC-V micro-controller, features are listed as following: 1. Maximum running speed up to 96 MHz 2. 2-stage in-order execution pipeline 3. Fast Hardware multiplier 4. Hardware divider 5. Dynamic branch prediction 6. Performance monitors 7. Misaligned memory accesses 8. RISC-V RV32I base integer instruction set 9. RISC-V RVC standard extension for compressed i nstructi ons 10. RISC-V RVM standard extension for integer multiplication and division 11. RISC-V RVA standard extension for atomic instructions 12. Instruction cache 8 KB 13. Machine mode and User mode 14. 8 entries PMP (Physical Memory Protection)

4.3 Mailbox

4.3.1 Working Principle

The registers MSG_M0_TO_M1_BYTE0 ~ MSG_M0_TO_M1_BYTE7 are written by the D25F core and read by the N22 core. If mailbox_irq_mask_m0_to_m1 is set to 1, writing to MSG_M0_TO_M1_BYTE7 by D25F wi ll trigger an interrupt signal mailbox_irq_m0_to_m1 to the N22 core. N22 can check the interrupt status via mailbox_irq_status_m0_m1. The interrupt is automatically cleared when N22 reads MSG_M0_TO_M1_BYTE7. If auto_read_clr_msg is set to 1, reading MSG_M0_TO_M1_BYTE7 by N22 will also clear the contents of MSG_M0_TO_M1_BYTE0 through MSG_M0_TO_M1_BYTE7. The registers MSG_M1_TO_M0_BYTE0 ~ MSG_M1_TO_M0_BYTE7 are wri tten by the N22 core and read by the D25F core. If mailbox_irq_mask_m1_to_m0 is set to 1, writing to MSG_M1_TO_M0_BYTE7 by N22 will trigger an interrupt signal mailbox_irq_m1_to_m0 to the D25F core. D25F can check the interrupt status via mailbox_irq_status_m1_m0. The interrupt is automatically cleared when D25F reads MSG_M1_TO_M0_BYTE7. If auto_read_clr_msg is set to 1, reading MSG_M1_TO_M0_BYTE7 by D25F wi ll also clear the contents of MSG_M1_TO_M0_BYTE0 through MSG_M1_TO_M0_BYTE7. a011…1111 233 0111…1111 234 1111…1111 235 Register Content Match Size (Byte)

Datasheet for Telink TL3828 DS-TL3828-E5 86 Ver 0.8.0

4.3.2 Register Description of Mailbox

The Mailbox related registers are listed as following, the base address of the following registers is 0x80101c00. Table 4-10 Register Configuration for Mailbox Address Offset Name Type Description Reset Value 0x00 MSG_M0_TO_M1_BYTE0 R/W [7:0]: msg_m0_to_m1_byte0 msg_m0_to_m1[7:0], m0:D25, m1:N22 0x00 0x01 MSG_M0_TO_M1_BYTE1 R/W [7:0]: msg_m0_to_m1_byte1 msg_m0_to_m1[15:8] 0x00 0x02 MSG_M0_TO_M1_BYTE2 R/W [7:0]: msg_m0_to_m1_byte2 msg_m0_to_m1[23:16] 0x00 0x03 MSG_M0_TO_M1_BYTE3 R/W [7:0]: msg_m0_to_m1_byte3 msg_m0_to_m1[31:24] 0x00 0x04 MSG_M0_TO_M1_BYTE4 R/W [7:0]: msg_m0_to_m1_byte4 msg_m0_to_m1[39:32] 0x00 0x05 MSG_M0_TO_M1_BYTE5 R/W [7:0]: msg_m0_to_m1_byte5 msg_m0_to_m1[47:40] 0x00 0x06 MSG_M0_TO_M1_BYTE6 R/W [7:0]: msg_m0_to_m1_byte6 msg_m0_to_m1[55:48] 0x00 0x07 MSG_M0_TO_M1_BYTE7 R/W [7:0]: msg_m0_to_m1_byte7 msg_m0_to_m1[63:56] 0x00 0x08 MSG_M1_TO_M0_BYTE0 R/W [7:0]: msg_m1_to_m0_byte0 msg_m1_to_m0[7:0] 0x00 0x09 MSG_M1_TO_M0_BYTE1 R/W [7:0]: msg_m1_to_m0_byte1 msg_m1_to_m0[15:8] 0x00 0x0a MSG_M1_TO_M0_BYTE2 R/W [7:0]: msg_m1_to_m0_byte2 msg_m1_to_m0[23:16] 0x00 0x0b MSG_M1_TO_M0_BYTE3 R/W [7:0]: msg_m1_to_m0_byte3 msg_m1_to_m0[31:24] 0x00 0x0c MSG_M1_TO_M0_BYTE4 R/W [7:0]: msg_m1_to_m0_byte4 msg_m1_to_m0[39:32] 0x00 0x0d MSG_M1_TO_M0_BYTE5 R/W [7:0]: msg_m1_to_m0_byte5 msg_m1_to_m0[47:40] 0x00

Datasheet for Telink TL3828 DS-TL3828-E5 87 Ver 0.8.0

4.4 Working Mode

The SoC supports six working modes, including Active, Idle, Suspend, Deep Sleep with SRAM retention, Deep Sleep without SRAM retention and Shutdown.

• The Power Management (PM) module is always active in all working modes.
• For modules such as MCU, and SRAM, the state depends on working mode, as shown below. Table 4-11 Working Mode 0x0e MSG_M1_TO_M0_BYTE6 R/W [7:0]: msg_m1_to_m0_byte6 msg_m1_to_m0[55:48] 0x00 0x0f MSG_M1_TO_M0_BYTE7 R/W [7:0]: msg_m1_to_m0_byte7 msg_m1_to_m0[63:56] 0x00 0x30 MAILBOX_IRQ_MASK_0 R/W [0]: mailbox_irq_mask_m1_to_m0 0x00 0x31 MAILBOX_IRQ_MASK_1 R/W [0]: mailbox_irq_mask_m0_to_m1 0x00 0x33 MAILBOX_AUTO_CLR R/W [0]: auto_read_clr_msg 0x01 0x34 MAILBOX_IRQ_STATUS_0 R [0]: mailbox_irq_status_m1_to_m0 0x00 0x35 MAILBOX_IRQ_STATUS_1 R [0]: mailbox_irq_status_m0_to_m1 0x00 Mode Active Idle Suspend Deep Sleep With SRAM Retention De ep Sleep without SRAM Retention Shutdown MCU active stall stall off off off USB available available stall/off off off off Audio available available stall/off off off off Wakeup Time to Active Mode in LDO Mode - 0 µs 100 µs Shorter than Deep sleep without retention, almost same as Suspend 1 ms 10 ms Wakeup Time to Active Mode in DCDC Mode - - - - - - Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 88 Ver 0.8.0 Analog registers (0x35 ~ 0x3c) as shown in below table are retained in deep sleep mode and can be used to store program state information across deep sleep cycles.

• Analog registers 0x3a~0x3c are non-volatile even when chip enters deep sleep or chip is reset by watchdog or software, i.e. the contents of these registers won’t be changed by deep sleep or watchdog reset or chip software reset.
• Analog registers 0x35~0x39 are non-volatile in deep sleep, but will be cleared by watchdog reset or chi p software reset.
• After POR (Power-On-Reset), all registers will be cleared to their default values, including these analog registers. Retention SRAMs (with retention in deep sleep) full full full full off off Wakeup on RTC (32K Timer wakeup) - - available available available off Wakeup on pin (IO wakeup) - - available available available on Wakeup on interrupt - available - - - - Wakeup on reset pin (POR) - available available available available on Mode Active Idle Suspend Deep Sleep With SRAM Retention Deep Sleep without SRAM Retention Shutdown NOTE:
• active: MCU is at working state.
• stall: In Idle and Suspend mode, MCU does not work, while its clock is still running.
• available for modules: It’s selectable to be at working state, or stall/be powered down if it does not need to work.
• available/on for wakeup: Corresponding wakeup method is supported.
• off for wakeup: Corresponding wakeup method is not supported.
• full/off for SRAMs: º full: Full speed. In Active, Idle and Suspend mode, the retention SRAMs are powered on and work normally (can be accessed); i n Deep sleep with SRAM retention, the retention SRAMs are powered on, however, the contents of the retention SRAMs can be retained and cannot be accessed. º off: The retention SRAMs are powered down in Deep sleep without SRAM retention and Shutdown mode.

Datasheet for Telink TL3828 DS-TL3828-E5 89 Ver 0.8.0 User can set flag in these analog registers correspondingly, so as to check the booting source by reading the flag. Table 4-12 Retention Analog Registers in Deep Sleep

4.5 Reset

The chip supports three types of reset methods, including POR (Power-On-Reset), watchdog reset and software reset. 1. POR: After power on, the whole chip will be reset, and all registers will be cleared to their default values. 2. Watchdog reset: A programmable wa tchdog i s supported to monitor the system. If watchdog reset is triggered, registers except for the retention analog registers 0x3a~0x3c will be cleared. 3. Software reset: It is also feasible to carry out software reset for the whole chip or some modules.

• Setting address 0x2f[5] as 1’b1 is to reset the whole chip. Similar to watchdog reset, the retention analog registers 0x3a~0x3c are non-volatile, while other registers including 0x35~0x39 will be cleared by chip software reset.
• Addresses 0x20~0x23, 0x40~0x43 serve to reset individual modules: if some bit is set to logic “1”, the corresponding module is reset. The base address of the following reset related registers is 0x80140800. Address Type Description Reset Value afe_0x35 R/W buffer clean at power_on/32K_watchdog/ reset pin/watchdog/reboot 11111111 afe_0x36 R/W buffer clean at power_on/32K_watchdog/ reset pin/watchdog/reboot 00000000 afe_0x37 R/W buffer clean at power_on/32K_watchdog/ reset pin/watchdog/reboot 00000000 afe_0x38 R/W buffer clean at power_on/32K_watchdog/ reset pin/watchdog/reboot 00000000 afe_0x39 R/W buffer clean at power_on/32K_watchdog/ reset pin/watchdog/reboot 00000000 afe_0x3a R/W buffer clean at power_on/32K_watchdog/ reset pin 00000000 afe_0x3b R/W buffer clean at power_on/32K_watchdog/ reset pin 00000000 afe_0x3c R/W buffer clean at power_on/32K_watchdog/ reset pin 11111111

Datasheet for Telink TL3828 DS-TL3828-E5 90 Ver 0.8.0 Table 4-13 Register Configuration for Software Reset Address Offset Name Type Description Reset Value 0x20 RST0 R/W [0]: LSPI, reset active low, 0 for reset, 1 for disable reset [1]: I2C [2]: UART0 [3]: USB [4]: PWM [5]: timern22 [6]: UART1 [7]: Swires 0x80 0x21 RST1 R/W [0]: UART3 [1]: System Timer [2]: DMA [3]: ALGM [4]: PKE [5]: RSVD [6]: GSPI, apb spi [7]: SSPI, spi slave 0x80 0x22 RST2 R/W [0]: Timer [1]: Audio [2]: I2C1 [3]: reset MCU, 0: reset MCU [4]: MCU reset_during_suspend, 0: MCU will be reset during suspend mode [5]: LM, 0: MCU ahb slave port will be reset, dma and other master could not access ILM/ DLM [6]: TRNG [7]: RRAM 0xb8 0x23 RST3 R/W [0]: QDEC1 [1]: Trace [2]: Brom [3]: RSVD [4]: RSVD [5]: QDEC [6]: SARADC [7]: ALG, analog module reset 0x96 0x2f PWDNEN R/W [0]: suspend enable (RW) [4]: ramcrc_clren_tgl (W) [5]: rst_all (act as watchdog reset) (Volatile) [7]: stall_en_trg (stall mcu trig) (W) 0x00

Datasheet for Telink TL3828 DS-TL3828-E5 91 Ver 0.8.0

4.6 Power Management

The multiple-stage Power Management (PM) module is flexible to control power state of the whole chip or individual functional blocks such as MCU, and peripherals by the following methods: 1. Power-On-Reset (POR) and Brown-out detect 2. Working Mode Switch 3. LDO and DCDC 0x40 RST4 R/W [0]: DC [1]: RSVD [2]: UART4 [3]: RSVD [4]: SKE [5]: HASH [6]: RSVD [7]: ZB 0x04 0x41 RST5 R/W [0]: RSVD [1]: UART2 [2]: RSVD [3]: RSVD [4]: IR Learn [5]: Key Scan [6]: PEM [7]: SAR ADC1 0x00 0x42 RST6 R/W [0]: RZ [1]: GSPI1 [2]: GSPI2 [3]: GSPI3 [4]: GSPI4 [5]: LIN0 [6]: LIN1 [7]: RRAM 0x80 0x4 3 RST7 R/W [0]: RSVD [1]: CAN0 [2]: CAN1 [3]: I3C0 [4]: I3C1 [5]: N22 [6]: RSVD [7]: DMA1 0x00 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 92 Ver 0.8.0

4.6.1 Power-on-Reset (POR) and Brown-out Detect

Figure below shows the control logic of power up/down. Figure 4-3 Control Logic of Power up/down As shown in the above figure, the entire power-up and power-down process is controlled by the UVLO (Ultra- low Voltage Lockout) & PL (Power Logic) module, and the external POR pin, as illustrated in the diagram. The UVLO module takes the external power supply as input and only releases the lock when the power supply voltage ex ceeds a predetermined threshold. After the UVLO and POR signals are released, there is an additional configurable delay before the system reset signal ("Sysrst") is released. This delay can be adjusted using the analog register afe_0x3e. It is worth noting that the content of afe_0x3e is reset to its default value only after a power cycle, watchdog reset, or software reset. Therefore, any chang es made to the delay usi ng afe_0x3e will only take effect if the chip has not undergone these reset conditions. For example, after waking up from deep sleep, the setting in afe_0x3e will be effective. The related analog registers are described in table below. Table 4-14 Analog Register to Control Logic of Power Up/Down Power up and power down sequences are shown in figures below. Address Name Type Description Default Value afe_0x3e r_dly R/W base on 16KHz frequency increase counter (8ms) 10000000 UVLO & PL NAND Delay Counter POR Battery / DCDC / LDO Power up / Power Down Analog register afe_0x3e

Datasheet for Telink TL3828 DS-TL3828-E5 93 Ver 0.8.0 Figure 4-4 Initial Power-up Sequence NOTE:

• PD_XXX LDO indicates the power down signal of the LDO voltage, high level means disable LDO, low level means enable LDO. VDD3 %25UHOHDVH§ 1.7V PD_3.3V LDO PD_1.25V LDO PD_1.8V LDO POR POR:0.6*VDDO3 UVLO NAND SYSRST Power off Brownout BOR release POR Normal Tdelay system reset released 300us Crystal VBUS

Datasheet for Telink TL3828 DS-TL3828-E5 94 Ver 0.8.0 Figure 4-5 Initial Power-down Sequence Table 4-15 Characteristics of Initial Power-up/Power-down Sequence Symbol Parameter Min. Typ. Max. Unit VPOR Reset trigger level - 0.7*VDDO3 - V VBOR_high VDD voltage when VUVLO turns to high level - 1.65 - V VBOR_low VDD voltage when VUVLO turns to low level - 1.55 - V TDelay Delay counter value Configurable via analog register afe_0x3e Normal %25§99'' 3'B9/'2 3'B9/'2 3'B9/'2 POR 1$1' SYSRST Brownout Power off XV &U\\VWDO 9%86

Datasheet for Telink TL3828 DS-TL3828-E5 95 Ver 0.8.0

4.6.2 Working Mode Switch

In Active mode, MCU is active, all SRAMs are accessible, and other modules are selectable whether to be at working state. The chip can switch to Idle mode to stall the MCU. In this mode, all SRAMs are still accessible, modules such as USB are still selectable whether to be at working state. The chip can be triggered to Active mode by interrupt or POR pin, and the time to switch to Acti ve mode is negligible. To decrease power consumption to different levels, the chip can switch to power saving mode (Suspend, Deep sleep with SRAM retention, Deep sleep without SRAM retention, Shutdown) correspondingly.

• In Suspend mode, MCU stalls, all SRAMs are still accessible, the PM module is active, and modules such as USB are powered down. The chip can be triggered to Active mode by 32K Ti mer, IO pin or POR pin. It takes 100 µs or so to switch from Suspend mode to Active mode.
• In Deep sleep with SRAM retention, the PM module is active, analog and digital modules except for the retention SRAMs are powered down, while the retention SRAMs can be retained and not accessible. The chip can be triggered to Active mode by 32K Timer, IO pin or POR pin. The time to switch to Active mode is shorter than Deep sleep without SRAM retention and close to Suspend.
• In Deep sleep wi thout SRAM retention, only the PM module is active, while analog and digital modules including the retention SRAMs are powered down. The chip can be triggered to Active mode by 32K Timer, IO pin or POR pin. The time to switch to Active mode is 1 ms or so.
• In Shutdown mode, all digital and analog modules are powered down, and only the PM module is active. The chip can be triggered to Acti ve mode by POR pin only. The time to switch to Active mode is 10 ms or so. User can directly invoke corresponding library function to switch working mode of the chip. If certain module doesn’t need to work, user can power down this module in order to save power. Table 4-16 3.3 V Analog Register for Module Power up/down Control Address Type Description Reset Value afe_0x4c R/W [0]: pd_rc32k_auto, 1: auto power down 32KHz RC [1]: pd_xtal32k_auto, 1: auto power down 32KHz xtal [2]: rsvd [3]: pd_xtal24m_auto, 1: auto power down 24MHz xtal [4]: pd_pl_all_auto, 1: auto power power logic [5]: pd_dcdc auto, 1: auto power down dcdc [6]: pd_vbus_ldo_auto, 1: auto power down vbus LDO [7]: pd_ana_ldo/pd_bbpll/temp_sens auto, 1: auto power down ana/BBPLL/temp_sensor LDO 0x0

Datasheet for Telink TL3828 DS-TL3828-E5 96 Ver 0.8.0

4.6.3 LDO and DCDC

The diagram of LDO and DCDC module is shown as following. Figure 4-6 LDO and DCDC As shown in figure above, the SoC operates with two power supply modes: VBAT and VBUS (optional power supply). Please note that when using VBUS power supply, the VBAT pin needs to be connected to the VDDO3 pin. The 3.3 V LDO generate 3.3 V voltage output and supply power for Power logic module, ADC, bandgap and GPIOs; the 1.8 V LDO produces 1.8 V voltage output and supply power for Flash and CODEC modules; the afe_0x4d R/W [0]: pd_lc_comp auto, 1: auto power down low power comparator [1]: rsvd [2]: pd_uvlo_ib_auto, 1: auto power down UVLO ib [3]: pd_vbus_sw_auto, 1: auto power down vbus switch [4]: rsvd [5]: rsvd [6]: pwdn_en, 1: power down sequence enable [7]: iso_en, 1: enable isolation 0x0 Address Type Description Reset Value 3V3 LDOVBAT VBUS 3V3 1V8 1V25 Analog LDO Flash Power Logic VDDO3 Digital LDO Codec DVDD1P25 VDCDCF VDD1P25_DEC VDDO3 AVDD1P25 Digital Analog VBUS LDO ADC,Bandgap VDDIO_AMS 1V8 LDO 1V25 DCDC 1V25 LDO GPIOs AVDD3

Datasheet for Telink TL3828 DS-TL3828-E5 97 Ver 0.8.0 1.25 V LDO/DCDC generates 1.25 V voltage output that serves as input for the internal analog LDO and digital LDO; the three LDOs are responsible for supplying power to the Analog, and Digital modules respectively.

4.7 Wakeup Source

The figure below shows wake up sources of the SoC. Figure 4-7 Wake up Sources Each wake up source is detailed below: USB & QDEC & Keyscan This wakeup source can only wake up the system from suspend mode. For USB wakeup, once USB host sends out resumi ng signal, the system will be woke up. For QDEC wakeup, it is mainly used in mouse applications. For Keyscan wakeup, it is detected from keys on the keyboard. 32 kHz Timer This wakeup source is able to wake up the system from suspend mode or two deep sleep modes. Low Power Comparator This wakeup source is able to wake up the system from suspend mode or two deep sleep modes. VBUS Detect This wakeup source is able to wake up the system from suspend mode or two deep sleep modes. wakeup PM_TOP Suspend_core_wakeup 32 kHz timer Low power comparator VBUS Detect USB wakeup Wakeup_timer Wakeup_comparator Wakeup_vbus_det Pad_wakeup QDEC wakeup Keyscan wakeup CTB Wakeup_CTB

Datasheet for Telink TL3828 DS-TL3828-E5 98 Ver 0.8.0 CTB This wakeup source is able to wake up the system from suspend mode or two deep sleep modes. Pad wakeup This wakeup source is from IO signals and able to wake up the system from suspend mode or two deep sleep modes. Table 4-17 Analog Register for Wakeup Address Type Description Default Value afe_0x3f R/W [7:0] PA_polarity wakeup polarity 0: high level wakeup,1: low level wakeup 00000000 afe_0x40 R/W [7:0] PB_polarity wakeup polarity 0: high level wakeup,1: low level wakeup 00000000 afe_0x41 R/W [7:0] PC_polarity wakeup polarity 0: high level wakeup,1: low level wakeup 00000000 afe_0x42 R/W [7:0] RSVD (PD_polarity) 00000000 afe_0x43 R/W [7:0] PE_polarity wakeup polarity 0: high level wakeup,1: low level wakeup 00000000 afe_0x45 R/W [7:0] PA wakeup enable 00000000 afe_0x46 R/W [7:0] PB wakeup enable 00000000 afe_0x47 R/W [7:0] PC wakeup enable 00000000 afe_0x48 R/W [7:0] RSVD (PD wakeup enable) 00000000 afe_0x49 R/W [7:0] PE wakeup enable 00000000 afe_0x4b R/W [0] pad wakeup enable [1] dig wakeup enable [2] timer wakeup enable [3] comparator wakeup enable [4] rsvd [5] CTB wakeup enable [6] rsvd [7] shutdown wakeup enable 0x0

Datasheet for Telink TL3828 DS-TL3828-E5 99 Ver 0.8.0 afe_0x64 R write 1 to clean the status: [0]: wkup pad [1]: wkup dig [2]: wkup timer [3]: wkup cmp [4]: ctb_error_irq [5]: ctb_irq [6]: rsvd [7]: vbus on 0x0 afe_0x7f R/W [3]: vbus_detect_pol vbus detect wakup polarity, 1: low level active, 0: high level active [4]: wkup_vbus_en, vbus detect wakeup enable 0x0 Address Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 100 Ver 0.8.0

5 Trap and PLIC

5.1 Trap

5.1.1 Introduction

According to the RISC-V Privileged Architecture, a trap is a control flow change of normal instruction execution caused by an interrupt or an exception. An interrupt is a control flow change event initiated by an external source. An exception is a control flow change event generated as a by-product of instruction execution. When a trap happens, the processor stops proces si ng the current flow of instructions, disables interrupts, saves enough states for later resumption, and starts executing a trap handler. Interrupts can be local or external. The external interrupts are global interrupts that are arbitrated externally by a platform level interrupt controller (PLIC) and the selected external interrupt joins the rest of local interrupts for arbitration to take a trap. For ex ceptions, mepc is the PC (Program Counter) of the faulting instruction. For Interrupts, mepc is pointing to the interrupted instruction.

5.1.2 Interrupt

Figure 5-1 Block Diagram of Interrupt As shown in the above figure, the processor provides three interrupt inputs: platform-level machine timer (PLMT) interrupt, software platform-level interrupt controller (PLIC_SW) interrupt, and platform-level interrupt controller (PLIC) interrupt. The PLMT interrupt and PLIC_SW i nterrupt are local interrupts. External interrupts are arbitrated and distributed by PLIC to the processor. Each external interrupt source can be assigned its own priority, and the processor core could select which external interrupt sources it would handle. PLIC routes the highest priority interrupt source to the target processor.

5.1.2.1 Local Interrupts

In addition to external interrupts, the processor may generate i nternal interrupts for the following events:

Datasheet for Telink TL3828 DS-TL3828-E5 101 Ver 0.8.0

• Bus read/write transaction error
• Performance monitor overflow

5.1.2.2 Interrupt Status and Masking

The mip CSR (Control and Status Register of the processor core) contains pending bits of these interrupts, with the mie CSR contains enable bits of the respective interrupts. The processor can selectively enable interrupts by manipulating the mie CSR, or globally disable interrupts by clearing the mstatus.MIE bit.

5.1.2.3 Interrupt Priority

When multiple interrupts are taken at the same time, they are handled under the following order: Table 5-1 Interrupt Priority

5.1.3 Exception

The processor implements the following exceptions.

• Instruction address misaligned exceptions º Jump to misaligned addresses
• Instruction access faults º Bus errors caused by instruction fetches
• Illegal instructions º Unsupported instructions º Privileged instructions º Accessing non-existent CSRs (Control and Status Regi sters of the processor core) º Accessing privileged CSRs º Writing to read-only CSRs
• Breakpoint exceptions
• Load address misaligned exceptions
• Load access faults º Bus errors caused by load instructions
• Store/AMO (atomic memory operation) address misaligned exceptions
• Store/AMO access faults
• Environment calls
• Stack overflow/underflow exceptions Priority Interrupt High M-mode performance monitor overflow interrupt M-mode bus read/write transaction error interrupt M-mode external interrupt (MEI) M-mode software interrupt (MSI) Low M-mode timer interrupt (MTI)

Datasheet for Telink TL3828 DS-TL3828-E5 102 Ver 0.8.0

5.1.4 Trap Handling

5.1.4.1 Entering the Trap Handler

When a trap occurs, the following operations are applied:

• mepc is set to the current program counter.
• mstatus is updated. º The MPP field is set to the current privilege mode. º The MPIE field is set to the MIE field. º The MIE field is set to 0.
• mcause is updated.
• mtval is updated on any of address-misaligned or access-fault exceptions.
• The privilege mode is changed to M-mode.
• When mmi sc_ctl.VEC_PLIC is 0, the program counter is set to the address specified by mtvec.
• When mmisc_ctl.VEC_PLIC is 1, the mtvec register will be the base address register of a vector table with 4-byte entries storing addresses pointing to interrupt service routines. º mtvec[0] is for exceptions and non-external local interrupts. For these traps, the mcause register records the trap type based on RISC-V defi nitions. º mtvec[i] is for external PLIC interrupt source i triggered through the mip.MEIP pending condition.

5.1.4.2 Returning from the Trap Handler

After handling a trap, the MRET instruction can be executed for returning to the instruction and the privilege context before the trap happened. Alternatively, the trap handler could assign new PC, privilege level and/or interrupt enable status to mepc, mstatus.MPP and mstatus.MPIE before MRET. Speci fically, the following operations take place when an MRET instruction is executed:

• The program counter is set to mepc.
• The privilege mode is set to mstatus.MPP.
• mstatus is updated. º The MPP field is set to U-mode. º The MIE field is set to the MPIE field. º The MPIE field is set to 1.

5.1.5 Machine Trap Related CSRs

5.1.5.1 Machine Status

Mnemonic Name: mstatus Access Mode: Machine CSR Address: 0x300

Datasheet for Telink TL3828 DS-TL3828-E5 103 Ver 0.8.0 Table 5-2 Register Description of mstatus

5.1.5.2 Machine Interrupt Enable

Mnemonic Name: mie Access Mode: Machine CSR Address: 0x304 Table 5-3 Register Description of mie

5.1.5.3 Machine Trap Vector Base Address

Mnemonic Name: mtvec Access Mode: Machine CSR Address: 0x305 This register determines the base address of the trap vector. The least significant 2 bits are hardwired to zeros. When mmisc_ctl.VEC_PLIC is 0 (PLIC is not in the vector mode), this register indicates the entry points for the trap handler and it may point to any 4-byte ali gned location in the memory space. On the other hand, when mmisc_ctl.VEC_PLIC is 1 (PLIC is in the vector mode), this register will be the base address of a vector table with 4-byte entries storing addresses pointing to interrupt service routines.

• This register should be aligned to 256-byte boundary.
• mtvec[0] is for exceptions, local interrupts. Name Bits Type Description Reset MIE [3] R/W M-mode interrupt enable bit. 0 MPIE [7] R/W MPIE holds the value of the MIE bit prior to a trap. 0 MPP [12:11] R/W MPP holds the privilege mode prior to a trap. 0: User mode 1: Reserved 2: Reserved 3: Machine mode Name Bits Type Description Reset MSIE [3] R/W M-mode software interrupt enable bit. 0 MTIE [7] R/W M-mode timer interrupt enable bit. 0 M EIE [11] R/W M-mode external interrupt enable bit. 0 BWEI [17] R/W Bus write transaction error local interrupt enable bit. The processor may receive bus errors on store instructions or cache writebacks. PMOVI [18] R/W Performance monitor overflow local interrupt enable bit. 0

Datasheet for Telink TL3828 DS-TL3828-E5 104 Ver 0.8.0

• mtvec[i] is for external PLIC interrupt source i triggered through the mip.MEIP pending condition Table 5-4 Register Description of mtvec

5.1.5.4 Machine Exception Program Counter

Mnemonic Name: mepc Access Mode: Machine CSR Address: 0x341 This register is written with the virtual address of the instruction that encountered traps when these events occurred. Table 5-5 Register Description of mepc

5.1.5.5 Machine Cause Register

Mnemonic Name: mcause Access Mode: Machine CSR Address: 0x342 This register indicates the cause of trap, reset or the i nterrupt source ID of a vector interrupt. This register is updated when a trap, reset or vector interrupt occurs. When multiple events may cause a trap to be taken with the same mcause value, the value of mdcause records the exact event that causes the trap. Table 5-6 Register Description of mcause The following table shows the possible values of mcause: Table 5-7 Possible Values of mcause Name Bits Type Description Reset Base[31:2] [31:2] R/W Base address for interrupt and exception handlers. 0 Name Bits Type Description Reset EPC [31:0] R/W Exception program counter. Bit[0] is hardwired to zero. 0 Name Bits Type Description Reset Exception_code [11:0] R/W Exception code 0 Interrupt [31] R/W Interrupt 0 Interrupt Exception Code Description 1 3 Machine software interrupt 1 7 Machine timer interrupt 1 11 Machine non-vector external interrupt 1 17 Bus read/write transaction error interrupt (M-mode)

Datasheet for Telink TL3828 DS-TL3828-E5 105 Ver 0.8.0 The following tables show the possible values of mcause after reset: Table 5-8 Possible values of mcause after reset The following tables show the possible values of mcause after vector interrupt: Table 5-9 Possible values of mcause after vector interrupt

5.1.5.6 Machine Trap Value

Mnemonic Name: mtval Access Mode: Machine CSR Address: 0x343 This register is updated when a trap is taken to M-mode. The updated value is dependent on the cause of traps:

• For Hardware Breakpoint exceptions, Address Misaligned ex ceptions, or Access Fault exceptions, it is the effective faulting addresses. 1 18 Performance monitor overflow interrupt (M-mode) 0 0 Instruction address misaligned 0 1 Instruction access fault 0 2 Illegal instruction 0 3 Breakpoint 0 4 Load address misaligned 0 5 Load access fault 0 6 Store/AMO address misaligned 0 7 Store/AMO access fault 0 8 Environment call from U-mode 0 11 Environment call from M-mode 0 32 Stack overflow exception 0 33 Stack underflow exception Interrupt Exception Code Description 0 0 Initial value when the processor comes out of reset Interrupt Exception Code Description

0 Interrupt source ID Interrupt source ID when a vector interrupt occurs

Interrupt Exception Code Description

Datasheet for Telink TL3828 DS-TL3828-E5 106 Ver 0.8.0

• For illegal instruction exceptions, the updated value is the faulting instruction.
• For other exceptions, mtval is set to zero. For instruction-fetch access faults, this register will be updated with the address pointing to the portion of the instruction that caused the fault, while the mepc register will be updated with the address pointing to the beginning of the instruction. T able 5-10 Register Description of mtval

5.1.5.7 Machine Interrupt Pending

Mnemonic Name: mip Access Mode: Machine CSR Address: 0x344 Table 5-11 Register Description of mip

5.1.5.8 Machine Detailed Trap Cause

Mnemonic Name: mdcause Access Mode: Machine CSR Address: 0x7c9 Table 5-12 Register Description of mdcause Name Bits Type Description Reset mtval [31:0] R/W Exception-specific information for software trap handling 0 Name Bits Type Description Reset MSIP [3] RO M-mode software interrupt pending bit. 0 MTIP [7] RO M-mode timer interrupt pending bit. 0 MEIP [11] RO M-mode external interrupt pending bit. 0 BWEI [17] R/W Bus write transaction error local interrupt pending bit. The processor may receive bus errors on store instructions or cache writebacks. PMOVI [18] R/W Performance monitor overflow local interrupt pending bit. 0 Name Bits Type Description Reset mdcause [2:0] R/W This register further disambiguates causes of traps recorded in the mcause register. See the below for details.

Datasheet for Telink TL3828 DS-TL3828-E5 107 Ver 0.8.0 Table 5-13 Detailed mdcause meaning in different mcause condition

5.1.5.9 Machine Miscellaneous Control Register

Mnemonic Name: mmisc_ctl Access Mode: Machine CSR Address: 0x7d0 mcause condition mdcause value Meaning mcause == 1 (Instruction access fault)

0 Reserved

1 Reserved

2 PMP instruction access violation

3 Reserved

4 Reserved

mcause == 2 (Illegal instruction) 0 The actual faulting instruction is stored in the mtval CSR. mcause == 5 (Load access fault)

2 PMP load access violation

3 Bus error

4 Misaligned address

5 Reserved

6 Reserved

7 Reserved

mcause == 7 (Store access fault)

2 PMP store access violation

Datasheet for Telink TL3828 DS-TL3828-E5 108 Ver 0.8.0 Table 5-14 Register Description of mdcause

5.2 Platform-Level Interrupt Controller (PLIC)

5.2.1 Introduction

The SoC embeds a Platform-Level Interrupt Controller (PLIC) prioritizes and distributes global interrupts. It is compatible with RISC-V PLIC with the following features:

• Number of interrupts: 64
• Programmable interrupt priority: 1/2/3
• Preemptive priority interrupt extension
• Vectored interrupt extension
• Software-programmable interrupt generation Figure 5-2 Block Diagram of PLIC Name Bits Type Description Reset VEC_PLIC [1] R/W Select the operation mode of PLIC: 0: Non-Vector mode; 1: Vector mode; Please note that both this bit and PLIC_FEN.VECTORED in PLIC should be turned on for the vectored interrupt support to work correctly.

Datasheet for Telink TL3828 DS-TL3828-E5 109 Ver 0.8.0 The above figure shows the block diagram of PLIC. External interrupt sources (e.g., peripherals) send interrupt requests to PLIC through external_interrupt[N:1] signals. The signals are level-triggered, and they are converted to interrupt requests by the interrupt gateway. Interrupt requests are prioritized and routed to interrupt targets (e.g., processor core) according to interrupt setti ngs. Interrupt settings include enable bits (PLIC_IE), priorities (PLIC_PRI), and priority thresholds (PLIC_THRES), and these settings are programmable through the bus interface. Note that interrupt targets should not modify PLIC_IE, PLIC_PRI and PLIC_THRES if there are any un-serviced interrupts. The eip is an external interrupt pending notification signal to the target. It is a level si gnal summari zing the interrupt pending status of all interrupt sources (PLIC_IP) to the target. When a target takes the external interrupt, it should send an interrupt claim request (bus read request) to retrieve the interrupt ID, upon which the corresponding PLIC_IP bit will be cleared and eip will be de-asserted. The eip is guaranteed to be de- asserted for at least one cycle even if there are pendi ng i nterrupt sources still remaining. This is done to ensure that the interrupt detection logic of the target processor can see the remaining interrupt pending status. The interrupt gateway stops processing newer interrupt requests from its interrupt sources once it reports an interrupt request. When the target has serviced the interrupt, it should send the interrupt completion message (bus write request) to PLIC such that the i nterrupt gateway resumes processing newer interrupt requests. The PLIC_IP register provides a summary of all interrupt sources status. In addition, it is also writable for setting software-programmed interrupts for the corresponding interrupt sources. Figure 5-3 Detailed Block Diagram of PLIC The above figure shows a more detailed block diagram. The PLIC contains multiple interrupt gateways, one per interrupt sou rce, together wi th a PLIC core that performs interrupt prioritization and routing External

Datasheet for Telink TL3828 DS-TL3828-E5 110 Ver 0.8.0 interrupts are sent from their source to an interrupt gateway that processes the interrupt signal from each source and sends a single interrupt request to the PLIC core, which latches these in the core interrupt pending bits (PLIC_IP). Each interrupt source is assigned a separate priority (PLIC_PRI) and interrupt enable (PLIC_IE). The PLIC core will generate an interrupt notificati on to the processor core if there are any pending interrupts enabled, and the priority of the pending interrupts exceeds the target threshold (PLIC_THRES). When the target takes the external interrupt, it sends an interrupt claim request to retrieve the identifier of the highest- priority global interrupt source pending for that target from the PLIC core, which then clears the corresponding interrupt source pendi ng bit. After the target has serviced the interrupt, it sends the associated interrupt gateway an interrupt completion message and the interrupt gateway can now forward another interrupt request for the same source to the PLIC.

5.3 External Interrupt Sources

There are 64 external interrupt sources, listed in table below. Table 5-15 Interrupt Sources No. Interrupt Source No. Interrupt Source 1 stimer_d25f_irq: system timer interrupt for d25f 33 qdec0_irq 2 algm_irq: analog register master interface interrupt 34 gpio_src_irq[0] 3 timer1_irq 35 gpio_src_irq[1] 4 timer0_irq 36 gpio_src_irq[2] 5 dma0_irq 37 gpio_src_irq[3] 6 bmc_irq: ahb bus matrix controller interrupt 38 gpio_src_irq[4] 7 rsvd 39 gpio_src_irq[5] 8 rsvd 40 gpio_src_irq[6] 9 rsvd 41 gpio_src_irq[7] 10 rsvd 42 trng_irq 11 rsvd 43 hash_irq 12 timer_n22_irq 44 pm_wkup_irq: PM wakeup interrupt 13 dc_irq 45 pm_mix_irq: PM mixed interrupt 14 usb_hs_irq: high-speed usb interrupt 46 mailbox_n22_to_d25 15 zb_ble_tl_irq:BLE(TL) sub-system interrupt 47 ske 16 pwm_irq 48 uart2_irq 17 pke_irq 49 key_scan 18 uart1_irq 50 uart3_irq

Datasheet for Telink TL3828 DS-TL3828-E5 111 Ver 0.8.0

5.3.1 Support for Preemptive Priority Interrupt

The PLIC implements the preemptive priority interrupt extension which enables faster responses for high- priority interrupts. This feature is enabled by setting PLIC_FEN.PREEMPT to 1. With this extension, if a high-priority interrupt arrives and the global interrupt is enabled (i.e., mstatus.MIE is 1), the processor will stop servicing the current low-priority interrupt and begi n servicing this new high-priority interrupt. The handling of the suspended lower-priority interrupts will resume only after the handling of the higher-priority interrupt ends. Interrupts of same or lower priorities will not cause preemption to take effect and interfere the handling of the current interrupt. They have to wait until the handling of the current interrupt finishes. To support this fea ture, the PLIC core i s enhanced with a preempted priority stack. The stack saves and restores priorities of the nested/preempted interrupts. The operation of the preempted stack is implicitly performed through two regular PLIC operations (Interrupt Claim and Interrupt Completion). See the next two subsections for more information.

5.3.1.1 Interrupt Claims with Preemptive Priority

When the target sends an interrupt claim message to the PLIC core, the PLIC core wi ll atomically determine the ID of the highest-priority pending interrupt for the target and then de-assert the corresponding source’s PLIC_IP bit. The PLIC core will then return the ID to the target. 19 uart0_irq 51 saradc_dig 20 dfifo_irq: audio dma fifo interrupt 52 rz 21 i2c_irq 53 gspi1_irq 22 lspi_irq 54 gspi2_irq 23 gspi_irq 55 gspi3_irq 24 rsvd 56 gspi4_irq 25 qdec1_irq 57 lin0 26 uart4_irq 58 lin1 27 i2c1_irq 59 can0 28 soft_irq: software interrupt 60 can1 29 rsvd 61 i3c0 30 rsvd 62 i3c1 31 rsvd 63 dma1_irq 32 ir_learn_irq 64 rram No. Interrupt Source No. Interrupt Source

Datasheet for Telink TL3828 DS-TL3828-E5 112 Ver 0.8.0 At the same time, the priority number in the target’s Priority Threshold Register (PLIC_THRES) will be saved to a preempted priority stack for that target and the new priority number of the claimed interrupt will be written to PLIC_THRES.

5.3.1.2 Interrupt Completion with Preemptive Priority

When the target sends an interrupt completion message to the PLIC core, in addition to forwarding the completion message to the associated gateway, the PLIC core will restore the highest priority number in the preempted priority stack back to PLIC_THRES. N ote that out-of-order completion of interrupts is not allowed when this feature is turned on — the latest claimed interrupt should be completed first.

5.3.1.3 Programming Sequence to Allow Preemption of Interrupts

Turning on the global interrupt enable flag (mstatus.MIE) is all it takes to allow the current interrupt handler to be preempted by higher priority interrupts. However, as the preemptive priority stack operations do not allow out-of-order completion, some care should be taken to make sure that the claim and completion operations are nested properly. For the non-vectored mode si ngle-entry interrupt handler, the global interrupt enable flag could be turned on after the processor context are saved and Interrupt Claim is performed to allow preemption of the current interrupt handler. At the end of interrupt handler, an Interrupt Completion message is performed to signal that the handler has processed the interrupt and PLIC may deliver the next interrupt from the same i nterrupt source again. As both claim and completion messages are done through load/store instructions to device regions, they should automatically be ordered correctly. Compared with the vectored mode interrupt handler two paragraphs below, the global interrupt flag does not need to be disabled and no FENCE needs to be inserted after sending the completion message. In summary, below is the suggested sequence for a non-vector mode i nterrupt handler for supporting preemptive priority interrupts: 1. Save registers/CSRs to stack 2. Send Interrupt Claim message to PLIC (device-load) 3. Enable global interrupt (mstatus.MIE) 4. Handle the expected interrupt 5. Send Interrupt Completion message to PLIC (device-store) 6. Restore registers/CSRs 7. Return from interrupt For vector mode interrupt handlers, Interrupt Clai m is implicit when the external interrupt is taken. The global interrupt enable flag could be turned on as long as the processor context are saved to allow preemption of the current interrupt handler. However, the global interrupt flag should be turned off before Interrupt Completion operations are performed, since the processor will trigger the next implicit Interrupt Claim operation as soon as the global i nterrupt enable flag is turned on and cause races between Interrupt Claim and Interrupt Completion. Additionally, a FENCE io,io operation should be inserted after the Interrupt Completion operation to make sure that the completion message reaches PLIC before the interrupt handler returns, which turns on the interrupt enable flag again and cause the next Interrupt Claim to be performed. In summary, below i s the suggested sequence for a vector mode interrupt handler for supporting preemptive priority interrupts:

Datasheet for Telink TL3828 DS-TL3828-E5 113 Ver 0.8.0 1. Save registers/CSRs to stack 2. Enable global interrupt (mstatus.MIE) 3. Handle the expected interrupt 4. Disable global interrupt (mstatus.MIE) 5. Send Interrupt Completion message to PLIC (device-store) 6. Restore registers/CSRs 7. Use a FENCE io, io instruction to ensure that the completion message has reached PLIC. 8. Return from interrupt

5.3.2 Vectored Interrupts

The PLIC enhances the RISC-V PLIC functionali ty with the vector mode extension to allow the interrupt target to receive the interrupt source ID without going through the target claim request protocol. This feature can shorten the latency of interrupt handling by enabling the interrupt target to run the corresponding interrupt handler directly upon accepting the external interrupt. It is enabled by setting PLIC_FEN.VECTORED to 1.

5.3.3 Support for Software-Generated Interrupt

The PLIC also adds support for a software-generated i nterrupt feature. The interrupt pending registers (PLIC_IP) are writable and has the operation definition of “write-1-to-set”, so software can set the pending bit of an interrupt source by writing a 1 to the corresponding bit of the interrupt pending register of the interrupt source.

5.3.4 Interrupt Flow

The below figure shows the messages flowing between agents when handling interrupts via the PLIC.

Datasheet for Telink TL3828 DS-TL3828-E5 114 Ver 0.8.0 Figure 5-4 Interrupt Flow The gateway will only forward a single interrupt request at a time to the PLIC, and not forward subsequent interrupts requests until an interrupt completion is received. The PLIC will set the PLIC_IP bit once it accepts an interrupt request from the gateway, and sometime later forward an interrupt notification to the target. The target might take a while to respond to a new interrupt arri ving, but will then send an interrupt claim request to the PLIC core to obtain the interrupt ID. The PLIC core will atomically return the ID and clear the corresponding PLIC_IP bit. Once the handler has processed the interrupt, it sends an interrupt completion message to the gateway to allow a new interrupt request.

5.4 Register Description of PLIC

PLIC related register are listed in table below. The base address for the followi ng registers is 0xC4000000. Please note that PLIC supports only 32-bit. Behaviors of 8-bit and 16-bit transfers are undefined, and these transfers might be ignored as well as result in error responses or unexpected register updates.

Datasheet for Telink TL3828 DS-TL3828-E5 115 Ver 0.8.0 Table 5-16 Register Configuration for PLIC Address Offset Name Type Description Reset Value 0x00 PLIC_FEN R/W Feature Enable Register [0]: PREEMPT, Preemptive priority interrupt enable [1]: VECTORED, Vector mode enable Please note that both this bit and the mmisc_ctl.VEC_PLIC bit of the processor should be turned on for the vectored interrupt support to work correctly. 0x00 0x04*n PLIC_PRI R/W Interrupt Source Priority. This register determines the priority for interrupt source n. [1:0]: Interrupt source priority. 0: Never interrupt, 1-3: Interrupt source priority. The larger the value, the higher the priority. 0x01 0x1000 PLIC_IP R/W Interrupt sources 1~31 Pending. The registers provide the interrupt pending status of interrupt sources 1~31, and a way for software to trigger an interrupt without relying on external devices. Every interrupt source occupies 1 bit.When these registers are read, the interrupt pending status of interrupt sources are returned. The pending bits could be set by writing a bit mask that specifies the bit positions to be set, and this action would result in software-programmed interrupts of the corresponding interrupt sources. The pending bits could only be cleared through the Interrupt Claim requests. [31:1]: interrupt pending status of interrupt sources 1~31. 0x00

Datasheet for Telink TL3828 DS-TL3828-E5 116 Ver 0.8.0 0x1004 PLIC_IP_H R/W Interrupt sources 32~63 Pending. The registers provide the interrupt pending status of interrupt sources 32~63, and a way for software to trigger an interrupt without relying on external devices. Every interrupt source occupies 1 bit.When these registers are read, the interrupt pending status of interrupt sources are returned. The pending bits could be set by writing a bit mask that specifies the bit positions to be set, and this action would result in software-programmed interrupts of the corresponding interrupt sources. The pending bits could only be cleared through the Interrupt Claim requests. [31:0]: interrupt pending status of interrupt sources 32~63. 0x00 0x1008 PLIC_IP_H2 R/W Interrupt sources 64 Pending. The registers provide the interrupt pending status of interrupt sources 64, and a way for software to trigger an interrupt without relying on external devices. Every interrupt source occupies 1 bit.When these registers are read, the interrupt pending status of interrupt sources are returned. The pending bits could be set by writing a bit mask that specifies the bit positions to be set, and this action would result in software-programmed interrupts of the corresponding interrupt sources. The pending bits could only be cleared through the Interrupt Claim requests. [0]: interrupt pending status of interrupt sources 64. 0x2000 PLIC_IE R/W Interrupt Enable Bits for interrupt sources 1~31 Every interrupt source occupies 1 bit. [31:1]: Interrupt Enable Bits for interrupt sources 1~31 0x00 0x2004 PLIC_IE_H R/W Interrupt Enable Bits for interrupt sources 32~63 Every interrupt source occupies 1 bit. [31:0]: Interrupt Enable Bits for interrupt sources 32~63. 0x00 0x2008 PLIC_IE_H2 R/W Interrupt Enable Bits for interrupt sources 64 Every interrupt source occupies 1 bit. [0]: Interrupt Enable Bits for interrupt sources 64. 0x200000 PLIC_THRES R/W Priority Threshold [31:0]: THRESHOLD, Interrupt priority threshold 0x0 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 117 Ver 0.8.0

5.5 Software Platform-Level Interrupt Controller (PLIC_SW)

5.5.1 Introduction

The SoC embeds another one PLIC named PLIC_SW for Software-programmable interrupt generation.It is compatible with RISC-V PLIC with the following features:

• Number of interrupt: 1
• Software-programmable interrupt generation The below Figure shows the block diagram of PLIC_SW. PLIC_SW doesn't support handling external interrupts, only support Software-programmable interrupt. For detai led functional descriptions, please refer to PLIC. Figure 5-5 Block Diagram of PLIC_SW 0x200004 PLIC_CLAIM_COMP R/W Claim and Complete Register [9:0]: INTERRUPT_ID, On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). 0x0 0x200400 PLIC_PPSTACK R/W Preempted Priority Stack Register The register is read/writable registers for accessing the preempted priority stack. The purpose of the register is for saving and restoring priorities of the nested/preempted interrupts. [3:0]: Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. 0x00 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 118 Ver 0.8.0

5.5.2 Register Description of PLIC_SW

The PLIC_SW related register are listed in table below. The base address for the following registers is 0xC6400000. Please note that PLIC_SW supports only 32-bit. Behaviors of 8-bit and 16-bit transfers are UNDEFINED, and these transfers might be ignored as well as result in error responses or unexpected register updates. Table 5-17 Register Configuration for PLIC_SW Address Offset Name Type Description Reset Value 0x1000 PLIC_IP R/W Interrupt sources 1 Pending. The registers provide the interrupt pending status of interrupt sources 1, and a way for software to trigger an interrupt without relying on external devices.Every interrupt source occupies 1 bit.When these registers are read, the interrupt pending status of interrupt sources are returned. The pending bits could be set by writing a bit mask that specifies the bit positions to be set, and this action would result in software-programmed interrupts of the corresponding interrupt sources. The pending bits could only be cleared through the Interrupt Claim requests. [1]: interrupt pending status of interrupt sources 1. 0x00 0x2000 PLIC_IE R/W Interrupt Enable Bits for interrupt sources 1. Every interrupt source occupies 1 bit. [1]: Interrupt Enable Bits for interrupt sources 1 0x00 0x200004 PLIC_CLAIM_COMP R/W Claim and Complete Register [9:0]: INTERRUPT_ID, On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). 0x00

Datasheet for Telink TL3828 DS-TL3828-E5 119 Ver 0.8.0

6 DMA

6.1 Introduction

The SoC embeds DMA (Direct Memory Access) module with DMAC. DMAC is a direct memory access controller which transfers regions of data efficiently on bus. DMAC features include:

• Supports up to 8 DMA channels
• Supports up to 22 request/acknowledge pairs for hardware handshaking
• Supports chain transfer

6.1.1 Function Description

DMAC supports up to 8 DMA channels. Each DMA channel provides a set of regi sters to describe the intended data transfers. Multiple DMA channels can be enabled concurrently, but the DMA controller services one channel at a time. Figure 6-1 shows an illustration of data transfer timing for a channel. In this figure, R means Read, W means Write, n is related with BurstSize, for example, when BurstSize is set to 2, it means 4 DMA transfers are required, n is 3 and details refer to the SrcBurstSi ze register description in Table 6-5. The details of channel arbitration refers to the next section. To prevent channels from being starved, the DMA controller services all ready-channels alternatively, performing at most SrcBurstSize data transfers each time. Consequently, the data transfers of a channel may be split into several chunks when the total transfer size (TranSize) is la rger than the source burst si ze (SrcBurstSize). When the overall data transfers of a channel complete, the DMA controller will update the interrupt status register, IntStatus, and assert the interrupt signal if the terminal count interrupt is enabled. The peripherals that support DMA burst transfer include: Audio and GSPI. For specific supported BurstSize and direction, please refer to the relevant secti ons of the corresponding peripheral interfaces. The data transfers of a channel will be stopped when an error occurs. The data transfers of a channel can also be aborted by software. In either case, the DMA controller will disable the channel, and assert the interrupt signal if the corresponding interrupt is enabled. Figure 6-1 Example of DMA Data Transfers

Datasheet for Telink TL3828 DS-TL3828-E5 120 Ver 0.8.0

6.1.1.1 Channel Arbitration

DMA provides two priority levels for channel arbitration. Every channel is associated with a priority level by the Priority field of the channel control register, ChnCtrl. During the channel arbitration, the DMA controller selects a high priority channel first. A low priority channel is only selected if there is no high priority channel. Channels of the same priority level will be selected by the round-robi n scheme.

6.1.1.2 Chain Transfer

DMA provides the chain transfer function, with which multiple blocks of data can be transferred consecutively without the intervention of the main processor. Before a chain transfer is started, a linked list structure must be built to describe the data blocks to move and the associated control setups. The first element of the list (the head of the list) is descri bed by the channel control registers. The rest of elements of the list are specified by the linked list descriptors stored in the memory, where the linked list descriptor holds the control values to load to the channel control registers to continue the data transfer. Figure 2 shows an example of the linked list structure. When the channel is enabled, the DMA controller will first transfer data a ccordi ng to the channel control registers. After the data transfer completes, the DMA controller will continue the data transfer by following the ChnLLPointer. The content of the linked list descriptor pointed by ChnLLPointer will be loaded to the channel control registers if ChnLLPointer is not zero. The loaded descriptor becomes the new head of the list and this process repeats until the ChnLLPointer i s zero. Figure 6-2 Linked List Structure for Chain Transfers There are three modes of interrupt generation for the linked list, see the description of register Chn_llp_int_mode below for details. (1) When Chn_llp_int_mode==0, the linked list interrupt is generated under the following conditions When the terminal count interrupt (IntTCMask) of a channel is enabled, the DMA controller will generate an interrupt and disable the channel when the data transfer for the head of the li st is done. If the ChnLLPointer is not zero, the channel control registers will be preloaded with the next descriptor before the interrupt is generated. The interrupt handling software could resume the chain transfer by just re-enabling the channel. (2) When Chn_llp_int_mode==1, the linked list interrupt is generated under the following conditions When the terminal count i nterrupt (IntTCMask) of a channel i s enabled, the DMA controller will generate an interrupt and disable the channel when the data transfer for the head of the list is done. If the ChnLLPointer is not zero, the interrupt will be generated after each channel control register is completed. (3) When Chn_llp_int_mode==2, the linked list interrupt is generated under the following conditions

Datasheet for Telink TL3828 DS-TL3828-E5 121 Ver 0.8.0 When the terminal count interrupt (IntTCMask) of a channel is enabled, the DMA controller will generate an interrupt and disable the channel when the data transfer for the head of the list is done. If the ChnLLPointer is not zero, the interrupt will be generated after each channel control register is completed, and the linked list will be aborted, the software should resume the chai n transfer by re-enabling the channel. The following table shows the format of the linked list descriptor. The bit field definition of each descriptor word is the same as the corresponding channel control register except the channel enable bit, which is reserved in the linked list descriptor. Table 6-1 Format of Linked List Descriptor The peripherals supporting chain transfer include: RX of UART, and audio.

6.1.1.3 Data Order

DMA provides three address control modes: i ncrement mode, decrement mode, and fixed mode. At the increment mode, the address is increased after the DMA controller accesses a data of the source/destination. At the decrement mode, the address is decreased after the DMA controller accesses a data of the source/ destination. At the fixed mode, the address remains unchanged after the DMA controller accesses a data of the source/desti nation.

6.2 Registers

6.2.1 Register Summary

The table below shows a summary of the DMA registers. The base address of DMA is 0x80100400 Table 6-2 DMA Related Registers Name Offset Description Format Ctrl 0x00 Channel control See Table 6-5 SrcAddr 0x04 Source address See Table 6-7 DstAddr 0x08 Destination address See Table 6-8 TranSize 0x0C Total transfer size See Table 6-9 LLPointer 0x10 Linked list pointer See Table 6-10 Offset Name Description Category +0x30 IntStatus Interrupt status register Channel status register +0x38~0x3c - Reserved

Datasheet for Telink TL3828 DS-TL3828-E5 122 Ver 0.8.0

6.2.2 Interrupt Status Register (Offset 0x30)

This register contains the terminal count, error, and abort status. The terminal count status of a channel is asserted when the channel encounters the terminal counter event. The error/abort status of a channel is asserted when the channel encounters the error/abort event. There is one bit of status for each channel and the status bit is zero when the corresponding channel is not confi gured. Table 6-3 Interrupt Status Register +0x40 ChAbort Channel abort register Channel control registers +0x44 + n*0x14 Ch nCtrl Channel n control register +0x48 + n*0x14 Ch nSrcAddr Channel n source address register +0x4c + n*0x14 Ch nDstAddr Channel n destination address register +0x50 + n*0x14 Ch nTranSize Channel n transfer size register +0x54 + n*0x14 Ch nLLPointer Channel n linked list pointer register Name Bit Type Description Reset Reserved 31:24 - Reserved - TC 23:16 R/W1C The terminal count status of DMA channels, one bit per channel. The terminal count status is asserted when a channel transfer finishes without abort or error event. 0x0: channel N has no terminal count status 0x1: channel N has terminal count status 0x0 Abort 15:8 R/W1C The abort status of channel, one bit per channel. The abort status is asserted when a channel transfer is aborted. Configure the channel abort register (offset 0x40) corresponding bit to 1 to indicate abort the corresponding DMA channel. 0x0: channel N has no abort status 0x1: channel N has abort status 0x0 Offset Name Description Category

Datasheet for Telink TL3828 DS-TL3828-E5 123 Ver 0.8.0

6.2.3 Channel Abort Register (Offset 0x40)

The register controls the abortion of the DMA channel transfers, one-bit per channel. Write 1 to stop the current transfer of the corresponding channel. The abort bit is automatically cleared by hardware when the corresponding status bit in the interrupt status register is cleared. Table 6-4 Channel Abort Register

6.2.4 Channel n Control Register (Offset 0x44+n*0x14)

Table 6-5 Channel n Control Register Error 7:0 R/W1C The error status, one bit per channel. The error status is asserted when a channel transfer encounters the following error events:

• Bus error
• Unaligned address
• Unaligned transfer width
• Reserved configuration 0x0: channel N has no error status 0x1: channel N has error status 0x0 Name Bit Type Description R eset ChAbort 7:0 WO Write 1 to this field to stop the channel transfer. The bits can only be set when the corresponding channels are enabled. Otherwise, the writes will be ignored for channels that are not enabled. 0x0 Name Bit Type Description Reset Auto enable en 31 R/W BB TX RX AUTO EN 0X0 Write_num_en 30 R/W Enable write num If this register is enabled, the peripheral to SRAM will write the number of bytes received to the first 4 bytes of the destination address at the end of the process. It should be noted that when write_num_en is enabled, CHnTranSize should be set to 0xffffff. 0x0 Priority 29 R/W Channel priority level 0x0: lower priority 0x1: reserved 0x0 Name Bit Type Description Reset

Datasheet for Telink TL3828 DS-TL3828-E5 124 Ver 0.8.0 Read_num_en 28 R/W 1:tx_size from ram 0:tx_size from reg If the register is enabled, when TX enables the first data transfer, it will write the first word of the source address to the CHnTranSize register and clear rnum_en. If rnum_en is not enabled, it is needed to configure the CHnTranSize register. 0x0 SrcBurstSize 26:24 R/W Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. This is configured according to the DMA BusrtSize that can be supported by the peripheral. Total byte of a burst is SrcBurstSize * SrcWidth. 0x0: 1 transfer 0x1: 2 transfers 0x2: 4 transfers 0x3: 8 transfers 0x4: 16 transfers 0x5: 32 transfers 0x6: 64 transfers 0x7: 128 transfers 0x0 SrcWidth 23:22 R/W Source transfer width 0x0: byte transfer 0x1: half-word transfer 0x2: word transfer 0x3: reserved, setting the field with this value triggers error exception 0x2 Name Bit Type Description Reset

Datasheet for Telink TL3828 DS-TL3828-E5 125 Ver 0.8.0 DstWidth 21:20 R/W Destination transfer width. Both the total transfer byte and the total burst bytes should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to word or half-word. See SrcBurstSize field above for the definition of total burst byte for the definition of the total transfer bytes. 0x0: byte transfer 0x1: half-word transfer 0x2: word transfer 0x3: reserved, set the field as this value triggers error exception 0x2 SrcMode 19 R/W Source DMA handshake mode 0x0: normal mode 0x1: handshake mode 0x0 DstMode 18 R/W Destination DMA handshake mode 0x0: normal mode 0x1: handshake mode 0x0 SrcAddrCtrl 17:16 R/W Source address control 0x0: increment address 0x1: decrement address 0x2: fixed address 0x3: reserved, setting the field with this value triggers the error exception 0x0 DstAddrCtrl 15:14 R/W Destination address control 0x0: increment address 0x1: decrement address 0x2: fixed address 0x3: reserved, setting the field with this value triggers the error exception 0x0 SrcReqSel 13:9 R/W Source DMA request select. Select the request/ack handshake pair that the source. See Table 6-6. 0x0 Name Bit Type Description Reset

Datasheet for Telink TL3828 DS-TL3828-E5 126 Ver 0.8.0 The following table shows the labels of the request/ack handshake pair for hardware connections. The SrcReqSel and DstReqSel registers select appropriate number from this table according to the actual functional needs. Table 6-6 Request/Ack Handshake Pair for Hardware Connection DstReqSel 8:4 R/W Destination DMA request select. Select the request/ack handshake pair that the destination. See Table 6-6. 0x0 IntAbtMask 3 R/W Channel abort interrupt mask 0x0: allow the abort interrupt to be triggered 0x1: disable the abort interrupt 0x0 IntErrMask 2 R/W Channel error interrupt mask 0x0: allow the error interrupt to be triggered 0x1: disable the error interrupt 0x0 IntTCMask 1 R/W Channel terminal count interrupt mask. 0x0: allow the terminal count interrupt to be triggered 0x1: disable the terminal count interrupt 0x0 Enable 0 R/W Channel enable bit 0x0: disable 0x1: enable 0x0 Signal Name Request/Ack Selection uart0_tx 2 uart0_rx 3 gspi_tx 4 gspi_rx 5 i2c_tx 6 i2c_rx 7 zb_tx 8 zb_rx 9 pwm_tx 10 RSVD 11 algm_tx 12 Name Bit Type Description Reset

Datasheet for Telink TL3828 DS-TL3828-E5 127 Ver 0.8.0

6.2.5 Channel n Source Address Register (Offset 0x48+n*0x14)

Table 6-7 Channel n Source Address Register

6.2.6 Channel n Destination Address Register (Offset 0x4C+n*0x14)

Table 6-8 Channel n Destination Address Register Since the data width of the peripherals for DMA transfer are word, it is unified that the DMA SrcAddr and DstAddr are word-aligned.

6.2.7 Channel n Transfer Size Register (Offset 0x50+n*0x14)

Table 6-9 Channel n Transfer Size Register algm_rx 13 uart1_tx 14 uart1_rx 15 audio0_tx 16 audio0_rx 17 audio1_tx 18 audio1_rx 19 Name Bit Type Description Reset SrcAddr 31:0 R/W Source starting address. When a transfer completes, its value is updated to the ending address + sizeof(SrcWidth). This address must be aligned to the source transfer size; otherwise, an error event will be triggered. 0x0 Name Bit Type Description Reset DstAddr 31:0 R/W Destination starting address. When a transfer completes, its value is updated to the ending address + sizeof(DstWidth). This address must be aligned to the destination transfer size; otherwise the error event will be triggered. 0x0 Name Bit Type Description Reset Reserved 31:24 - - - Signal Name Request/Ack Selection

Datasheet for Telink TL3828 DS-TL3828-E5 128 Ver 0.8.0 The actual amount of data transferred is as follows. For RX, transize_idx is invalid, the actual amount of data transferred = TranSize * SrcWidth. For TX, transize_idx is valid, when transize_idx is not 0, the actual amount of data transferred = (TranSize - 1) * SrcWidth + TranSize_idx; when transize_idx is 0, the actual amount of data transferred = TranSize * SrcWidth. When the DMA transfer di rection is from peripheral to SRAM, the actual size written to SRAM is TranSize and TranSize_idx is ignored.

6.2.8 Channel n Linked List Pointer Register (Offset 0x54+n*0x14)

Table 6-10 Channel Linked List Pointer Register

6.2.9 Baseband Related Register

Baseband TX can only use channel 0 of DMA, and baseband RX can only use channel 1 of DMA. For DMA, there are specific functions for the baseband module, the detailed registers are as follows. Table 6-11 Baseband Related Registers TranSize_idx 23:22 R/W Byte size 0x0 TranSize 21:0 R/W Total transfer size from source. The total number of transferred bytes is TranSize * SrcWidth. The value is updated to zero when the DMA transfer is done. If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. 0x0 Name Bit Type Description Reset LLPointer 31:2 R/W Pointer to the next block descriptor. The pointer must be word aligned. 0x0 Reserved 1:0 - - - Name Address Bit Type Description Reset BB_TX_SIZE 0xf0~0xf1 15:0 R/W Size of each TX buffer, unit is byte. 0x0 BB_TX_CHN_DEP 0xf3 2:0 R/W Depth of TX FIFO, the actual depth is 2^BB_TX_CHN_DEP 0x0 BB_RX_WPTR 0xf4 4:0 R/W RX_WPTR pointer 0x0 Name Bit Type Description Reset

Datasheet for Telink TL3828 DS-TL3828-E5 129 Ver 0.8.0 RX_RPTR_CLR 0xf5

7 W1C Clear the RX_RPTR pointer 0x0

RX_RPTR_NXT 6 W1C Add 1 to RX_RPTR pointer 0x0 RX_RPTR_SET 5 W1C Set RX_RPTR pointer 0x0 BB_RX_RPTR 4:0 R/W Set the specific value of the RX_RPTR pointer 0x0 BB_RX_SIZE 0xf6~0xf7 15:0 R/W Size of each RX buffer, unit is byte. 0x0 TX_WPTRn 0x100+n*2, n=[0:5] 15:0 R/W TX_WPTR pointer corresponding to the baseband channel 0x0 TX_RPTRn_CLR 0x101+n*2(n =[0:5])

7 W1C

Clear the TX_WPTR pointer corresponding to the baseband channel 0x0 TX_RPTRn_NXT 6 W1C Add 1 to the TX_WPTR pointer corresponding to the baseband channel 0x0 TX_RPTRn_SET 5 W1C Set the TX_WPTR pointer corresponding to the baseband channel 0x0 TX_RPTRn 4:0 R/W TX_RPTR pointer corresponding to the baseband channel 0x0 Name Address Bit Type Description Reset

Datasheet for Telink TL3828 DS-TL3828-E5 130 Ver 0.8.0 Dma_req_d1_en 0x10c

5 R/W

Synchronize the dma_request signal to hclk domain 0x0 Ch1_rx_err_en 4 R/W DMA TC interrupt does not work if baseband rx_err occurs 0x0 Ch_1_rnum_en_bk 3 R/W ch_1_rnum_en_bk needs to be used with read_num_en because the read_num_en register is cleared to 0 after each first load of TranSize and the value of ch_1_rnum_en_bk is automatically loaded after the DMA transfer is completed 0x0 Ch_0_rnum_en_bk 2 R/W ch_0_rnum_en_bk needs to be used with read_num_en because the read_num_en register is cleared to 0 after each first load of TranSize and the value of ch_0_rnum_en_bk is automatically loaded after the DMA transfer is completed 0x1 rx_multi_en 1 R/W The role of rx_multi_en: it will automatically load the destination address register after each DMA transfer and automatically load 0xffffff into the TranSize register 0x0 Tx_multi_en 0 R/W The role of tx_multi_en: DMA will check the read/write pointer of the current baseband channel after receiving the send request from the baseband, if the FIFO of the current baseband channel is empty, DMA will read data from the default buffer. 0x0 Rx_wptr_mask 0x10d 4:0 R/W Depth of RX FIFO, the actual depth is 2^rx_wptr_mask 0x0 Name Address Bit Type Description Reset

Datasheet for Telink TL3828 DS-TL3828-E5 131 Ver 0.8.0

6.2.10 Miscellaneous Register

Table 6-12 Linked List Interrupt Mode

6.3 Usage Guide

6.3.1 From SRAM to SRAM

It is recommended to disable wnum_en, rnum_en and auto_enable_en. For SRAM, the transize_idx (only applicable to peripherals) will be invalid. If byte-unit data needs to be transferred from SRAM to SRAM, the srcwidth and dstwidth control registers need to be set. Assuming that 1023 bytes of data need to be transferred from address A to address B, B should be written to the desti nation address register, A should be written to the source address register, 1023 should be written to the transize register, and finally the Channel n Control Register (Offset 0x44+n*0x14) should be configured as the table below. Table 6-13 Register Configuration for SRAM to SRAM Name Address Bit Type Description Reset Chn_llp_int_mode 0x113~0 x114 [1+n*2: 0+n*2] R/W 0: llp continue mode, the linked list transfer is continuous, interrupt is generated only when the last chain completes 1: llp interrupt mode, the linked list does not stop, the interrupt is generated at the completion of each chain 2: llp terminal mode, the linked list stops automatically at the completion of each chain, interrupt is generated at the completion of each chain 3: rsvd 0xff Bit Name Configuration 31 auto_enable_en Set to 0. 30 wnum_en Set to 0. 29 priority Set to 0. 28 rnum_en Set to 0. 27 reserved Reserved bit 24-26 src_burst_size Set to any value stated in Table 6-5. 22-23 srcwidth Set to any value stated in Table 6-5.

Datasheet for Telink TL3828 DS-TL3828-E5 132 Ver 0.8.0

6.3.2 From SRAM to Peripherals

From SRAM to peripherals, only transferring with srcwidth and dstwidth of word is supported. Assuming that 1023 bytes of data need to be transferred from SRAM address A to peripheral address B, B should be written to the destination address register, A should be written to the source address register, (1023+3)/4 should be written to the transize register, and 1023%4 should b e wri tten to the transize_idx register. Finally, the Channel n Control Register (Offset 0x44+n*0x14) should be configured. as the table below. Table 6-14 Register Configuration for SRAM to Peripherals 20-21 dstwidth The dstwidth must be aligned with the DMA TranSize. For example, if the DMA TranSize is not aligned with a half word, it should be configured as a byte. If the DMA TranSize is neither aligned with a byte nor aligned with a word, it should be configured as a half word. 19 src_mode Set to 0. 18 dst_mode Set to 0. 16-17 src_addr_ctl Set to 0. 14-15 dst_addr_ctl Set to 0. 9-13 src_req_sel Ignore. 4-8 dst_req_sel Ignore. abort interrupt enable Enable Abort Interrupt when write 1 to the corresponding channel ChAbort Register. error interrupt enable Enable Error Interrupt when an error occurs. The detailed error description refers to Error register (Offset 0x30). tc interrupt enable Enable TC interrupt when DMA transmission completes. 0 enable Write 1 to start DMA transmission, write 0 to abort transmission. Bit Name Configuration 31 auto_enable_en Set to 0. 30 wnum_en Set to 0. 29 priority Set to 0. 28 rnum_en Set to 0. 27 reserved Reserved bit Bit Name Configuration

Datasheet for Telink TL3828 DS-TL3828-E5 133 Ver 0.8.0

6.3.3 From Peripherals to SRAM

From peripherals to SRAM, only transferring with srcwidth and dstwidth of word is supported. If transferring data from peripheral address A to SRAM address B, B should be written to the destination address register, A should be written to the source address register, 0xffffffff should be written to the transize register since the amount of bytes being transferred is unknown. Fi nally, the Channel n Control Register (Offset 0x44+n*0x14) should be configured as the table below. Table 6-15 Register Configuration for Peripherals to SRAM 24-26 src_burst_size Set to the burst size that peripheral supports. 22-23 srcwidth Set to word. 20-21 dstwidth Set to word. 19 src_mode Set to 0. 18 dst_mode Set to 1. 16-17 src_addr_ctl Set to 0. 14-15 dst_addr_ctl Set to 2. 9-13 src_req_sel Ignore. 4-8 dst_req_sel Set according to the corresponding Request/Ack Selection number of the peripheral in Table 6-6. abort interrupt enable Set to the burst size that peripheral supports. error interrupt enable Enable Error Interrupt when an error occurs. The detailed error description refers to Error register (Offset 0x30). tc interrupt enable Enable TC Interrupt when DMA transmission completes. 0 enable Write 1 to start DMA transmission, write 0 to abort transmission. Bit Name Configuration 31 auto_enable_en Set to 0. 30 wnum_en Set to 1 to write the number of data received to a word before the destination address. 29 priority Set to 0. 28 rnum_en Set to 0. Bit Name Configuration

Datasheet for Telink TL3828 DS-TL3828-E5 134 Ver 0.8.0

6.3.4 From SRAM to Baseband

The configuration method for transferring data from SRAM to baseband is the same as that from SRAM to peripheral mentioned above. However, for the previous method, after each DMA transfer, it's necessary to reconfigure the transize register, source address register, and enable control register (en). In comparison, there are some enhanced functionalities for baseband. After enabli ng tx_multi_en, DMA will automatically load the source address register. After enabling rnum_en, DMA will automatically load the transize register (also needing to set ch_0_rnum_en_bk at dma_base+0x10c to 1 since rnum_en will be cleared to 0 after every first loading of transize, and it will automatically load the value of ch_0_rnum_en_bk after completing a DMA transfer). By enabling auto_enable_ en, the en i n the enable control register will be automatically enabled depending on the requests made by baseband. The mechanism for automatic loading of the source address register works as follows: TX has a total of 6 channels (0-5), it is needed to set the FIFO depth of each chn tx_chn_dep (where 0 represents one buffer, 1 represents two buffers, and 2 represents four buffers) and set the size of each buffer buf_si ze(bb_tx_size) bytes. The channel will be fixed on the baseband side for each transfer. After enabling the tx_multi_en of DMA, DMA receives the send request from baseband and views the read/write pointer of the current channel. If the FIFO 27 reserved reserved bit 24-26 src_burst_size Set to the burst size that peripheral supports. 22-23 srcwidth Set to word. 20-21 dstwidth Set to word. 19 src_mode Set to 1. 18 dst_mode Set to 0. 16-17 src_addr_ctl Set to 2. 14-15 dst_addr_ctl Set to 0. 9-13 src_req_sel Set according to the corresponding Request/Ack Selection number of the peripheral in Table 6-6. 4-8 dst_req_sel Ignore. abort interrupt enable Enable Abort Interrupt when write 1 to the corresponding channel ChAbort Register. error interrupt enable Enable Error Interrupt when an error occurs. The detailed error description refers to Error register (Offset 0x30). tc interrupt enable Enable TC Interrupt when DMA transmission completes. 0 enable Write 1 to start DMA transmission, write 0 to abort transmission. Bit Name Configuration

Datasheet for Telink TL3828 DS-TL3828-E5 135 Ver 0.8.0 of the current channel is empty, DMA will read data from the default buff. If the current channel's FIFO is not empty, DMA will go to the corresponding rptr of the current channel to read the data. The write pointer of TX is maintained by software while the read pointer is maintained by hardware (incremented every time a tx_commit is received by baseband in multi-mode. In case the baseband does not use multi -mode, the software can neglect maintaining the write pointer, making all txfifos empty; then, the DMA automatically reads data from the default buffer during transmission). Hence, the multi-mode of DMA can be used even when the baseband is in non-multi mode.

6.3.5 From Baseband to SRAM

The same method used for peripheral to SRAM can also be applied to transfer data from baseband to SRAM. Similar to the previ ous case, after every DMA transfer, configuring destination address register, transize register, and enable control register's en becomes necessary. However, for the Rx channel of baseband, DMA has enhanced functionality. By enabling rx_multi_en, upon completing every DMA transfer, the DMA automatically loads the destination address register and sets the transize register with 0xffffff. The auto_enable_en i n the control register is activated such that when the baseband initiates an RX request, the en register in the control register is automatically enabled. The mechanism for DMA to automatically load the destination registers: Unlike TX which has 6 channels, RX has only one FIFO buffer, therefore only the RX FIFO depth rx_wptr_mask(dma_base+0x10d[4:0]) and the buffer size (bb_rx_size) i n bytes need to be set. Whenever a DMA transfer is initiated, DMA reads data from baseband and writes it to the specified address in the destination address register. After completing the transfer, if the received packet is valid, the baseband generates an rx_commit signal to the DMA, which increments the rx_wptr. The next packet of data will then be written into the buffer pointed to by rx_wptr. If the rx fifo's depth is zero, incoming data will continue to be written to the same location.

Datasheet for Telink TL3828 DS-TL3828-E5 136 Ver 0.8.0

7 Peripheral Event Matrix (PEM)

7.1 Introduction

The SoC supports the PEM (Peripheral Event Matrix) function which is to realize the interconnection between the peripherals, any peripheral A’s event signal (similar to the interrupt signal) is routed to any peripheral B’s task input, the peripheral B treats the task signal as enable or trigger signal.

7.2 Block Diagram

The block diagram of PEM is shown as below. Figure 7-1 Block Diagram of PEM n md0_event[7:0] md1_event[7:0] md2_event[7:0] mdn_event[7:0] ... ... ... reg_event_ md_sel[4:0] reg_event_ sig_sel[2:0] CH0 CH1 CH31 ... ... ... Module(0) (Timer) Module(1) (ADC) Module(2) (GSPI) md2_event [7:0] Module(n) (I2C) mdn_event [7:0] md0_event [7:0] md1_event [7:0] Module(0) (Timer) Module(1) (ADC) Module(2) (GSPI) md2_task [7:0] Module(n) (I2C) mdn_task [7:0] md0_task [7:0] md1_task [7:0] task_ch[0] reg_task_md_sel[0]=0 & reg_task_sig_sel[0]=0 task_ch[1] reg_task_md_sel[1]=0 & reg_task_sig_sel[1]=0 task_ch[31] reg_task_md_sel[31]=0 & reg_task_sig_sel[31]=0 md0_task[0] md(n)_task[7] ... ... ... ... ... ... ... ... ... ... x N Channel N PEM producer consumer Module(9) (STIMER) md9_event [7:0] ... ... ... ... Module(9) (STIMER) ... ... ... ... md9_task [7:0] event_r0 DFF cclk 2DF F cclk reg_event_ clk_sel[1:0]=3? reg_inv cclk reg_both_edge reg_event_lvl & ~reg_task_lvl p2p reg_en task_ch cclk cclk event_clk_en event _1dff event _2dff event_r1 event_inv event_r2 event_r3 event _r4 event_r5 task_clk_en event_clk_en & clk_event != clk_task DFF cclktask_clk_en reg_event_lvl event_mux _1dff event_mux task_clk_en

Datasheet for Telink TL3828 DS-TL3828-E5 137 Ver 0.8.0

7.3 Function Description

The PEM routes the event signal of peripheral A to the task signal of peripheral B, and the peripheral B treats the task signal as enable or trigger signal.

• Event signal: comes from the peripheral, similar as interrupt signal.
• Task signal: it can choose any one of the event signals, the peripheral treats task signal as enable or trigger signal. In the block diagram above, e ach peri pheral can have multiple event and task signals, the peripheral that generates the event is called producer, the peripheral that receives the task is called consumer, and the same peripheral can be both producer and consumer. By using multiple channels, different events can be routed to the same task and the same event can be routed to different tasks.

7.4 Event Task List

The Event and Task for PEM is listed as below. T able 7-1 Event Task List No. Module Sub Sel. Event No. Event Type Clock Task No. Task Type Clock

1 LSPI

0 rxf_overrun pulse hclk 0 trigger SPI transmission pulse hclk 1 txf_underrun pulse hclk - - - - 2 rxf_threshold level hclk - - - - 3 txf_threshold level hclk - - - - 4 trans_done pulse hclk - - - - 5 slave_cmd pulse hclk - - - - 6 lcd_line_done pulse hclk - - - - 7 lcd_line_lvl pulse hclk - - - - 1 0 lcd_frame_done pulse hclk - - - -

Datasheet for Telink TL3828 DS-TL3828-E5 138 Ver 0.8.0

2 GSPI

0 rxf_overrun pulse hclk 0 trigger SPI transmission pulse hclk 1 txf_underrun pulse hclk - - - - 2 rxf_threshold level hclk - - - - 3 txf_threshold level hclk - - - - 4 trans_done pulse hclk - - - - 5 slave_cmd pulse hclk - - - -

3 OSR_IP

0 pke_irq level hclk - - - - 1 trng_irq level hclk - - - - 2 hash_irq level hclk - - - - 3 ske_irq level hclk - - - - No. Module Sub Sel. Event No. Event Type Clock Task No. Task Type Clock

Datasheet for Telink TL3828 DS-TL3828-E5 139 Ver 0.8.0

4 GPIO

0 pa0_input level aclk 0 pa0_toggle pulse pclk 1 pa1_input level aclk 1 pa1_toggle pulse pclk 2 pa2_input level aclk 2 pa2_toggle pulse pclk 3 pa3_input level aclk 3 pa3_toggle pulse pclk 4 pa4_input level aclk 4 pa4_toggle pulse pclk 5 pa5_input level aclk 5 pa5_toggle pulse pclk 6 pa6_input level aclk 6 pa6_toggle pulse pclk 7 pa7_input level aclk 7 pa7_toggle pulse pclk 0 pb0_input level aclk 0 pb0_toggle pulse pclk 1 pb1_input level aclk 1 pb1_toggle pulse pclk 2 pb2_input level aclk 2 pb2_toggle pulse pclk 3 pb3_input level aclk 3 pb3_toggle pulse pclk 4 pb4_input level aclk 4 pb4_toggle pulse pclk 5 pb5_input level aclk 5 pb5_toggle pulse pclk 6 pb6_input level aclk 6 pb6_toggle pulse pclk 7 pb7_input level aclk 7 pb7_toggle pulse pclk 0 pc0_input level aclk 0 pc0_toggle pulse pclk 1 pc1_input level aclk 1 pc1_toggle pulse pclk 2 pc2_input level aclk 2 pc2_toggle pulse pclk 3 pc3_input level aclk 3 pc3_toggle pulse pclk 4 pc4_input level aclk 4 pc4_toggle pulse pclk 5 pc5_input level aclk 5 pc5_toggle pulse pclk 6 pc6_input level aclk 6 pc6_toggle pulse pclk 7 pc7_input level aclk 7 pc7_toggle pulse pclk No. Module Sub Sel. Event No. Event Type Clock Task No. Task Type Clock

Datasheet for Telink TL3828 DS-TL3828-E5 140 Ver 0.8.0 0 pd0_input level aclk 0 pd0_toggle pulse pclk 1 pd1_input level aclk 1 pd1_toggle pulse pclk 2 pd2_input level aclk 2 pd2_toggle pulse pclk 3 pd3_input level aclk 3 pd3_toggle pulse pclk 4 pd4_input level aclk 4 pd4_toggle pulse pclk 5 pd5_input level aclk 5 pd5_toggle pulse pclk 6 pd6_input level aclk 6 pd6_toggle pulse pclk 7 pd7_input level aclk 7 pd7_toggle pulse pclk 0 pe0_input level aclk 0 pe0_toggle pulse pclk 1 pe1_input level aclk 1 pe1_toggle pulse pclk 2 pe2_input level aclk 2 pe2_toggle pulse pclk 3 pe3_input level aclk 3 pe3_toggle pulse pclk 4 pe4_input level aclk 4 pe4_toggle pulse pclk 5 pe5_input level aclk 5 pe5_toggle pulse pclk 6 pe6_input level aclk 6 pe6_toggle pulse pclk 7 pe7_input level aclk 7 pe7_toggle pulse pclk 0 pf0_input level aclk 0 pf0_toggle pulse pclk 1 pf1_input level aclk 1 pf1_toggle pulse pclk 2 pf2_input level aclk 2 pf2_toggle pulse pclk 3 pf3_input level aclk 3 pf3_toggle pulse pclk 4 pf4_input level aclk 4 pf4_toggle pulse pclk 5 pf5_input level aclk 5 pf5_toggle pulse pclk 6 pf6_input level aclk 6 pf6_toggle pulse pclk 7 pf7_input level aclk 7 pf7_toggle pulse pclk No. Module Sub Sel. Event No. Event Type Clock Task No. Task Type Clock

Datasheet for Telink TL3828 DS-TL3828-E5 141 Ver 0.8.0 0 pg0_input level aclk 0 pg0_toggle pulse pclk 1 pg1_input level aclk 1 pg1_toggle pulse pclk 2 pg2_input level aclk 2 pg2_toggle pulse pclk 3 pg3_input level aclk 3 pg3_toggle pulse pclk 4 pg4_input level aclk 4 pg4_toggle pulse pclk 5 pg5_input level aclk 5 pg5_toggle pulse pclk 0 gpio_irq level aclk 0 - - - 1 gpio2risc0 level aclk 1 - - - 2 gpio2risc1 level aclk 2 - - - 0 gpio_irq_group0 level aclk 0 - - - 1 gpio_irq_group1 level aclk 1 - - - 2 gpio_irq_group2 level aclk 2 - - - 3 gpio_irq_group3 level aclk 3 - - - 4 gpio_irq_group4 level aclk 4 - - - 5 gpio_irq_group5 level aclk 5 - - - 6 gpio_irq_group6 level aclk 6 - - - 7 gpio_irq_group7 level aclk 7 - - -

5 DMA 0

0 ch0_tc pulse hclk 0 ch0_en pulse hclk 1 ch1_tc pulse hclk 1 ch1_en pulse hclk 2 ch2_tc pulse hclk 2 ch2_en pulse hclk 3 ch3_tc pulse hclk 3 ch3_en pulse hclk 4 ch4_tc pulse hclk 4 ch4_en pulse hclk 5 ch5_tc pulse hclk 5 ch5_en pulse hclk 6 ch6_tc pulse hclk 6 ch6_en pulse hclk 7 ch7_tc pulse hclk 7 ch7_en pulse hclk No. Module Sub Sel. Event No. Event Type Clock Task No. Task Type Clock

Datasheet for Telink TL3828 DS-TL3828-E5 142 Ver 0.8.0

5 DMA

0 ch0_abt pulse hclk 0 - - - 1 ch1_abt pulse hclk 1 - - - 2 ch2_abt pulse hclk 2 - - - 3 ch3_abt pulse hclk 3 - - - 4 ch4_abt pulse hclk 4 - - - 5 ch5_abt pulse hclk 5 - - - 6 ch6_abt pulse hclk 6 - - - 7 ch7_abt pulse hclk 7 - - - 0 ch0_err pulse hclk 0 - - - 1 ch1_err pulse hclk 1 - - - 2 ch2_err pulse hclk 2 - - - 3 ch3_err pulse hclk 3 - - - 4 ch4_err pulse hclk 4 - - - 5 ch5_err pulse hclk 5 - - - 6 ch6_err pulse hclk 6 - - - 7 ch7_err pulse hclk 7 - - - 0 ch0_wbufov pulse hclk 0 - - - 1 ch1_wbufov pulse hclk 1 - - - 2 ch2_wbufov pulse hclk 2 - - - 3 ch3_wbufov pulse hclk 3 - - - 4 ch4_wbufov pulse hclk 4 - - - 5 ch5_wbufov pulse hclk 5 - - - 6 ch6_wbufov pulse hclk 6 - - - 7 ch7_wbufov pulse hclk 7 - - - No. Module Sub Sel. Event No. Event Type Clock Task No. Task Type Clock

Datasheet for Telink TL3828 DS-TL3828-E5 143 Ver 0.8.0

5 DMA 4

0 ch0_pdcyc pulse hclk 0 - - - 1 ch1_pdcyc pulse hclk 1 - - - 2 ch2_pdcyc pulse hclk 2 - - - 3 ch3_pdcyc pulse hclk 3 - - - 4 ch4_pdcyc pulse hclk 4 - - - 5 ch5_pdcyc pulse hclk 5 - - - 6 ch6_pdcyc pulse hclk 6 - - - 7 ch7_pdcyc pulse hclk 7 - - -

6 MISC -

0 qdec_int_pos pulse pclk - - - - 1 qdec_wakeup level aclk - - - - 7 pm_irq level aclk - - - -

7 CPU - 0 wfi_mode level cclk - - - -

8 Timer

0 irq_mode0 pulse pclk 0 timer0_tick_clr pulse pclk 1 irq_capt0 pulse pclk 1 timer1_tick_clr pulse pclk 2 irq_comp0 pulse pclk 2 timer0_tick_add pulse pclk 3 irq_mode1 pulse pclk 3 timer1_tick_add pulse pclk 4 irq_capt1 pulse pclk 4 wd_en pulse pclk 5 irq_comp1 pulse pclk 5 wd_disable pulse pclk 6 tick0_of(overflow) pulse pclk 6 capt0 pulse pclk 7 tick1_of(overflow) pulse pclk 7 capt1 pulse pclk - - - - 0 timer0_en pulse pclk - - - - 1 timer0_disable pulse pclk - - - - 2 timer1_en pulse pclk - - - - 3 timer1_disable pulse pclk No. Module Sub Sel. Event No. Event Type Clock Task No. Task Type Clock

Datasheet for Telink TL3828 DS-TL3828-E5 144 Ver 0.8.0

9 STimer -

0 irq_trig_pos0 pulse pclk 0 stimer_en pulse pclk 1 irq_trig_pos1 - - - - - - 2 irq_cal_tgl_pul pulse pclk 1 stimer_disable pulse pclk 3 irq_capt pulse pclk 2 capt pulse pclk 4 irq_ov pulse pclk - - - -

10 SAR_ADC -

0 rx_threshold level pclk 0 sigle adc_trig pulse pclk 1 rx_data_fifo_wr pulse pclk 1 - - -

11 Audio -

0 txfifo_irq pulse pclk 0 i2s0_en/ sdm_en pulse pclk 1 rxfifo_irq pulse pclk 1 i2s0_disable/ sdm_disable pulse pclk 2 txfifo_th_irq pulse pclk 2 i2s1_en pulse pclk 3 rxfifo_th_irq pulse pclk 3 i2s1_disable pulse pclk - - - - 4 i2s2_en pulse pclk - - - - 5 i2s2_disable pulse pclk - - - - 6 codec_en pulse pclk - - - - 7 codec_disable pulse pclk

12 IR_learn -

0 irq_high pulse pclk 0 ir_learn_en pulse pclk 1 irq_cycle pulse pclk 1 ir_learn_disable pulse pclk 2 irq_timeout pulse pclk - - - - 3 irq_rxbuf pulse pclk - - - - No. Module Sub Sel. Event No. Event Type Clock Task No. Task Type Clock

Datasheet for Telink TL3828 DS-TL3828-E5 145 Ver 0.8.0

13 PWM

0 pwm0_period_start pulse pclk 0 pwm0_en pulse pclk 1 pwm1_period_start pulse pclk 1 pwm1_en pulse pclk 2 pwm2_period_start pulse pclk 2 pwm2_en pulse pclk 3 pwm3_period_start pulse pclk 3 pwm3_en pulse pclk 4 pwm4_period_start pulse pclk 4 pwm0_disable pulse pclk 5 pwm5_period_start pulse pclk 5 pwm1_disable pulse pclk 6 pwm6_period_start pulse pclk 6 pwm2_disable pulse pclk - - - - 7 pwm3_disable pulse pclk 0 pwm0_cycdone pulse pclk 0 pwm4_en pulse pclk 1 pwm1_cycdone pulse pclk 1 pwm5_en pulse pclk 2 pwm2_cycdone pulse pclk 2 pwm6_en pulse pclk 3 pwm3_cycdone pulse pclk 3 pwm4_disable pulse pclk 4 pwm4_cycdone pulse pclk 4 pwm5_disable pulse pclk 5 pwm5_cycdone pulse pclk 5 pwm6_disable pulse pclk 6 pwm6_cycdone pulse pclk - - - - 0 pwm0_done pulse pclk - - - - 1 pwm0_fifo_done pulse pclk - - - - 2 pwm0_lvl pulse pclk - - - -

15 RZ -

0 irq_txbuf pulse pclk - - - - 1 irq_txdone pulse pclk - - - - 2 tx_empty level pclk - - - - 3 seten pulse pclk - - - -

16 Algm -

0 rx_buf_irq level pclk 0 algm_en pulse pclk 1 tx_buf_irq level pclk 1 rx_fifo_clr pulse pclk 2 rx_done level pclk 2 tx_fifo_clr pulse pclk 3 tx_done level pclk - - - - 4 tx_empty level pclk - - - - No. Module Sub Sel. Event No. Event Type Clock Task No. Task Type Clock

Datasheet for Telink TL3828 DS-TL3828-E5 146 Ver 0.8.0

17 UART0 -

0 rx_buf_irq level pclk 0 uart_en pulse pclk 1 tx_buf_irq level pclk 1 uart_disable pulse pclk 2 rx_done level pclk 2 rx_fifo_clr pulse pclk 3 tx_done level pclk 3 tx_fifo_clr pulse pclk 4 rx_err level pclk 4 uart div cnt clr pulse pclk

18 UART1 -

0 rx_buf_irq level pclk 0 uart_en pulse pclk 1 tx_buf_irq level pclk 1 uart_disable pulse pclk 2 rx_done level pclk 2 rx_fifo_clr pulse pclk 3 tx_done level pclk 3 tx_fifo_clr pulse pclk 4 rx_err level pclk 4 uart div cnt clr pulse pclk

19 UART2 -

0 rx_buf_irq level pclk 0 uart_en pulse pclk 1 tx_buf_irq level pclk 1 uart_disable pulse pclk 2 rx_done level pclk 2 rx_fifo_clr pulse pclk 3 tx_done level pclk 3 tx_fifo_clr pulse pclk 4 rx_err level pclk 4 uart div cnt clr pulse pclk

20 I2C

0 rx_buf_irq level pclk 0 i2c_master_en pulse pclk 1 tx_buf_irq level pclk 1 i2c_master_disa ble pulse pclk 2 rx_done level pclk 2 i2c_slave_en pulse pclk 3 tx_done level pclk 3 i2c_slave_disabl e pulse pclk 4 rx_end level pclk 4 rx_fifo_clr pulse pclk 5 tx_end level pclk 5 tx_fifo_clr pulse pclk 6 trx_stop level pclk - - - - 7 trx_start level pclk - - - - 0 nak_irq level pclk - - - - 1 ss_rw_irq level pclk - - - - 2 ss_scl_irq level pclk - - - - No. Module Sub Sel. Event No. Event Type Clock Task No. Task Type Clock

Datasheet for Telink TL3828 DS-TL3828-E5 147 Ver 0.8.0

7.5 Register Description of PEM

The PEM related registers are listed in the following table. The base address for the following PEM related registers is 0x80142000. Table 7-2 PEM Related Registers KS (Key Scan) 0 frem_end pulse pclk 0 ks_enable pulse pclk - - - - 1 ks_disable pulse pclk

22 USB

0 reset level hclk 0 edps0_ack(8) pulse hclk 1 250us level hclk 1 edps1_ack pulse hclk 2 suspend level hclk 2 edps2_ack pulse hclk 3 sof level hclk 3 edps3_ack pulse hclk 4 setup level hclk 4 edps4_ack pulse hclk 5 data level hclk 5 edps5_ack pulse hclk 6 status level hclk 6 edps6_ack pulse hclk 7 setintf level hclk 7 edps7_ack pulse hclk 0 edps0_data_irq(8) level hclk - - - - 1 edps1_data_irq level hclk - - - - 2 edps2_data_irq level hclk - - - - 3 edps3_data_irq level hclk - - - - 4 edps4_data_irq level hclk - - - - 5 edps5_data_irq level hclk - - - - 6 edps6_data_irq level hclk - - - - 7 edps7_data_irq level hclk - - - - Address Offset Name Type Description Default Value 0x00 PEM_CH0_CTRL0 RW [4:0] event_module_sel 0x00 0x01 PEM_CH0_CTRL1 RW [4:0] task_module_sel 0x00 No. Module Sub Sel. Event No. Event Type Clock Task No. Task Type Clock

Datasheet for Telink TL3828 DS-TL3828-E5 148 Ver 0.8.0 0x02 PEM_CH0_CTRL2 RW [2:0] event_sig_sel [5:3] task_sig_sel [7:6] event_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x03 PEM_CH0_CTRL3 RW [0] both_edge [2] inv [3] ch_en [4] event_lvl [5] task_lvl [7:6] task_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x04 PEM_CH1_CTRL0 RW [4:0] event_module_sel 0x00 0x05 PEM_CH1_CTRL1 RW [4:0] task_module_sel 0x00 0x06 PEM_CH1_CTRL2 RW [2:0] event_sig_sel [5:3] task_sig_sel [7:6] event_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x07 PEM_CH1_CTRL3 RW [0] both_edge [2] inv [3] ch_en [4] event_lvl [5] task_lvl [7:6] task_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x08 PEM_CH2_CTRL0 RW [4:0] event_module_sel 0x00 0x09 PEM_CH2_CTRL1 RW [4:0] task_module_sel 0x00 0x0a PEM_CH2_CTRL2 RW [2:0] event_sig_sel [5:3] task_sig_sel [7:6] event_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x0b PEM_CH2_CTRL3 RW [0] both_edge [2] inv [3] ch_en [4] event_lvl [5] task_lvl [7:6] task_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 149 Ver 0.8.0 0x0c PEM_CH3_CTRL0 RW [4:0] event_module_sel 0x00 0x0d PEM_CH3_CTRL1 RW [4:0] task_module_sel 0x00 0x0e PEM_CH3_CTRL2 RW [2:0] event_sig_sel [5:3] task_sig_sel [7:6] event_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x0f PEM_CH3_CTRL3 RW [0] both_edge [2] inv [3] ch_en [4] event_lvl [5] task_lvl [7:6] task_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x10 PEM_CH4_CTRL0 RW [4:0] event_module_sel 0x00 0x11 PEM_CH4_CTRL1 RW [4:0] task_module_sel 0x00 0x12 PEM_CH4_CTRL2 RW [2:0] event_sig_sel [5:3] task_sig_sel [7:6] event_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x13 PEM_CH4_CTRL3 RW [0] both_edge [2] inv [3] ch_en [4] event_lvl [5] task_lvl [7:6] task_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x14 PEM_CH5_CTRL0 RW [4:0] event_module_sel 0x00 0x15 PEM_CH5_CTRL1 RW [4:0] task_module_sel 0x00 0x16 PEM_CH5_CTRL2 RW [2:0] event_sig_sel [5:3] task_sig_sel [7:6] event_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 150 Ver 0.8.0 0x17 PEM_CH5_CTRL3 RW [0] both_edge [2] inv [3] ch_en [4] event_lvl [5] task_lvl [7:6] task_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x18 PEM_CH6_CTRL0 RW [4:0] event_module_sel 0x00 0x19 PEM_CH6_CTRL1 RW [4:0] task_module_sel 0x00 0x1a PEM_CH6_CTRL2 RW [2:0] event_sig_sel [5:3] task_sig_sel [7:6] event_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x1b PEM_CH6_CTRL3 RW [0] both_edge [2] inv [3] ch_en [4] event_lvl [5] task_lvl [7:6] task_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x1c PEM_CH7_CTRL0 RW [4:0] event_module_sel 0x00 0x1d PEM_CH7_CTRL1 RW [4:0] task_module_sel 0x00 0x1e PEM_CH7_CTRL2 RW [2:0] event_sig_sel [5:3] task_sig_sel [7:6] event_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x1f PEM_CH7_CTRL3 RW [0] both_edge [2] inv [3] ch_en [4] event_lvl [5] task_lvl [7:6] task_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x20 PEM_CH8_CTRL0 RW [4:0] event_module_sel 0x00 0x21 PEM_CH8_CTRL1 RW [4:0] task_module_sel 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 151 Ver 0.8.0 0x22 PEM_CH8_CTRL2 RW [2:0] event_sig_sel [5:3] task_sig_sel [7:6] event_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x23 PEM_CH8_CTRL3 RW [0] both_edge [2] inv [3] ch_en [4] event_lvl [5] task_lvl [7:6] task_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x24 PEM_CH9_CTRL0 RW [4:0] event_module_sel 0x00 0x25 PEM_CH9_CTRL1 RW [4:0] task_module_sel 0x00 0x26 PEM_CH9_CTRL2 RW [2:0] event_sig_sel [5:3] task_sig_sel [7:6] event_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x27 PEM_CH9_CTRL3 RW [0] both_edge [2] inv [3] ch_en [4] event_lvl [5] task_lvl [7:6] task_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x28 PEM_CH10_CTRL0 RW [4:0] event_module_sel 0x00 0x29 PEM_CH10_CTRL1 RW [4:0] task_module_sel 0x00 0x2a PEM_CH10_CTRL2 RW [2:0] event_sig_sel [5:3] task_sig_sel [7:6] event_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x2b PEM_CH10_CTRL3 RW [0] both_edge [2] inv [3] ch_en [4] event_lvl [5] task_lvl [7:6] task_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 152 Ver 0.8.0 0x2c PEM_CH11_CTRL0 RW [4:0] event_module_sel 0x00 0x2d PEM_CH11_CTRL1 RW [4:0] task_module_sel 0x00 0x2e PEM_CH11_CTRL2 RW [2:0] event_sig_sel [5:3] task_sig_sel [7:6] event_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x2f PEM_CH11_CTRL3 RW [0] both_edge [2] inv [3] ch_en [4] event_lvl [5] task_lvl [7:6] task_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x30 PEM_CH12_CTRL0 RW [4:0] event_module_sel 0x00 0x31 PEM_CH12_CTRL1 RW [4:0] task_module_sel 0x00 0x32 PEM_CH12_CTRL2 RW [2:0] event_sig_sel [5:3] task_sig_sel [7:6] event_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x33 PEM_CH12_CTRL3 RW [0] both_edge [2] inv [3] ch_en [4] event_lvl [5] task_lvl [7:6] task_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x34 PEM_CH13_CTRL0 RW [4:0] event_module_sel 0x00 0x35 PEM_CH13_CTRL1 RW [4:0] task_module_sel 0x00 0x36 PEM_CH13_CTRL2 RW [2:0] event_sig_sel [5:3] task_sig_sel [7:6] event_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 153 Ver 0.8.0 0x37 PEM_CH13_CTRL3 RW [0] both_edge [2] inv [3] ch_en [4] event_lvl [5] task_lvl [7:6] task_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x38 PEM_CH14_CTRL0 RW [4:0] event_module_sel 0x00 0x39 PEM_CH14_CTRL1 RW [4:0] task_module_sel 0x00 0x3a PEM_CH14_CTRL2 RW [2:0] event_sig_sel [5:3] task_sig_sel [7:6] event_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x3b PEM_CH14_CTRL3 RW [0] both_edge [2] inv [3] ch_en [4] event_lvl [5] task_lvl [7:6] task_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x3c PEM_CH15_CTRL0 RW [4:0] event_module_sel 0x00 0x3d PEM_CH15_CTRL1 RW [4:0] task_module_sel 0x00 0x3e PEM_CH15_CTRL2 RW [2:0] event_sig_sel [5:3] task_sig_sel [7:6] event_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x3f PEM_CH15_CTRL3 RW [0] both_edge [2] inv [3] ch_en [4] event_lvl [5] task_lvl [7:6] task_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x40 PEM_CH16_CTRL0 RW [4:0] event_module_sel 0x00 0x41 PEM_CH16_CTRL1 RW [4:0] task_module_sel 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 154 Ver 0.8.0 0x42 PEM_CH16_CTRL2 RW [2:0] event_sig_sel [5:3] task_sig_sel [7:6] event_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x43 PEM_CH16_CTRL3 RW [0] both_edge [2] inv [3] ch_en [4] event_lvl [5] task_lvl [7:6] task_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x44 PEM_CH17_CTRL0 RW [4:0] event_module_sel 0x00 0x45 PEM_CH17_CTRL1 RW [4:0] task_module_sel 0x00 0x46 PEM_CH17_CTRL2 RW [2:0] event_sig_sel [5:3] task_sig_sel [7:6] event_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x47 PEM_CH17_CTRL3 RW [0] both_edge [2] inv [3] ch_en [4] event_lvl [5] task_lvl [7:6] task_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x48 PEM_CH18_CTRL0 RW [4:0] event_module_sel 0x00 0x49 PEM_CH18_CTRL1 RW [4:0] task_module_sel 0x00 0x4a PEM_CH18_CTRL2 RW [2:0] event_sig_sel [5:3] task_sig_sel [7:6] event_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x4b PEM_CH18_CTRL3 RW [0] both_edge [2] inv [3] ch_en [4] event_lvl [5] task_lvl [7:6] task_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 155 Ver 0.8.0 0x4c PEM_CH19_CTRL0 RW [4:0] event_module_sel 0x00 0x4d PEM_CH19_CTRL1 RW [4:0] task_module_sel 0x00 0x4e PEM_CH19_CTRL2 RW [2:0] event_sig_sel [5:3] task_sig_sel [7:6] event_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x4f PEM_CH19_CTRL3 RW [0] both_edge [2] inv [3] ch_en [4] event_lvl [5] task_lvl [7:6] task_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x50 PEM_CH20_CTRL0 RW [4:0] event_module_sel 0x00 0x51 PEM_CH20_CTRL1 RW [4:0] task_module_sel 0x00 0x52 PEM_CH20_CTRL2 RW [2:0] event_sig_sel [5:3] task_sig_sel [7:6] event_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x53 PEM_CH20_CTRL3 RW [0] both_edge [2] inv [3] ch_en [4] event_lvl [5] task_lvl [7:6] task_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x54 PEM_CH21_CTRL0 RW [4:0] event_module_sel 0x00 0x55 PEM_CH21_CTRL1 RW [4:0] task_module_sel 0x00 0x56 PEM_CH21_CTRL2 RW [2:0] event_sig_sel [5:3] task_sig_sel [7:6] event_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 156 Ver 0.8.0 0x57 PEM_CH21_CTRL3 RW [0] both_edge [2] inv [3] ch_en [4] event_lvl [5] task_lvl [7:6] task_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x58 PEM_CH22_CTRL0 RW [4:0] event_module_sel 0x00 0x59 PEM_CH22_CTRL1 RW [4:0] task_module_sel 0x00 0x5a PEM_CH22_CTRL2 RW [2:0] event_sig_sel [5:3] task_sig_sel [7:6] event_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x5b PEM_CH22_CTRL3 RW [0] both_edge [2] inv [3] ch_en [4] event_lvl [5] task_lvl [7:6] task_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x5c PEM_CH23_CTRL0 RW [4:0] event_module_sel 0x00 0x5d PEM_CH23_CTRL1 RW [4:0] task_module_sel 0x00 0x5e PEM_CH23_CTRL2 RW [2:0] event_sig_sel [5:3] task_sig_sel [7:6] event_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 0x5f PEM_CH23_CTRL3 RW [0] both_edge [2] inv [3] ch_en [4] event_lvl [5] task_lvl [7:6] task_clk_sel, 0:cclk; 1:hclk; 2:pclk; 3:aclk 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 157 Ver 0.8.0

8 Clock

8.1 Clock Sources

The SoC’s clock sources are a 24 MHz RC oscillator, an external 24 MHz crystal and PLL, as shown below. Figure 8-1 Clock Sources MUX RC_24M XTL_24M PLL divider rsvd divider clk_gspi0 divider clk_stimerXTL_24M clk_7816 divider XTL_24M 0x80140828[5:4] 0x80140828[3:0] 0x80140800[5:4] 0x80140800[3:0] 0x80140802[7:0] 0x80140803[1:0] 0x80140830[6:4] sys_clk MUX1/2... cclk hclk MUXdivider pclk 0x80140818[2] 0x80140818[1:0]0x80140818[1:0] divider clk_i2s0 step:{0x80140807,0x80140806} mod: {0x8014082b,0x8014082a} PLL divider clk_i2s2 step:{0x80140809,0x80140808} mod: {0x8014080b,0x8014080a} PLL divider clk_dmic step:{0x8014082d,0x8014082c} mod: {0x80140837,0x80140836} PLL divider rsvdPLL MUX RC_24M XTL_24M PLL MUX RC_24M XTL_24M PLL 0x8014083b[2:0] clk_sardig divider 0x8014081b[3:0] 0x8014081b[5:4] MUX RC_24M XTL_24M PLL clk_rram clk_lspi divider 0x80140801[3:0] 0x80140801[5:4] MUX RC_24M XTL_24M PLL clk_gspi1 divider 0x80140848[7:0] 0x80140849[1:0] MUX RC_24M XTL_24M PLL clk_gspi2 divider 0x8014084a[7:0] 0x8014084b[1:0] MUX RC_24M XTL_24M PLL clk_gspi3 divider 0x8014084c[7:0] 0x8014084d[1:0] MUX RC_24M XTL_24M PLL clk_gspi4 divider 0x8014084e[7:0] 0x8014084f[1:0] MUX RC_24M XTL_24M PLL clk_i3c0 divider 0x80140804[3:0] 0x80140804[5:4] MUX RC_24M XTL_24M PLL clk_i3c1 divider 0x80140805[3:0] 0x80140805[5:4] MUX RC_24M XTL_24M PLL divider... clk_usb0_phyXTL_24M divider hclk clk_sardig1 divider 0x80140866[3:0] 0x80140866[5:4] MUX RC_24M XTL_24M PLL clk_keyscan divider 0x80140811[4:0] 0x80140811[6:5] MUX RC_24M XTL_24M clk32k 0 0x80140812[1:0] clk32k ana_0x4e[7] MUX 32KHz RC clock 0 132.768KHz RC clock

Datasheet for Telink TL3828 DS-TL3828-E5 158 Ver 0.8.0 The clock sources of each module are shown in table below. Table 8-1 Clock Sources of Each Module Module Clock Source(s) PLDM hclk PLIC_SW hclk PLMT clk32k, hclk PLIC hclk MCU (D25F) cclk MCU (N22) hclk DC Detection pclk CAN0/1 pclk LIN0/1 pclk I3C0/1 pclk, clki3c RRAM hclk, clkrram MAILBOX hclk BROM hclk ZB clk32k, hclk AUDIO hclk, pclk, clk_i2s, clk_dmic USB0 hclk, clk_usb0 PKE hclk SKE hclk TRNG hclk, clk_ro HASH hclk SWIRE hclk OSR_REG hclk DMA0/1 hclk BMC hclk GSPI0/1/2/3/4 hclk, clk_gspi LSPI hclk, clk_lspi D25F_ILM cclk

Datasheet for Telink TL3828 DS-TL3828-E5 159 Ver 0.8.0

8.2 System Clock

There are three selectable clock sources for MCU system clock (named cclk): RC_24M derived from 24 MHz RC oscillator, 24 MHz crystal, and pll clk. The sources are selectable via register CCLK_SET.cclk_sel[1:0]. And system clock can be reduced in frequency via frequency divider which is controlled via register CCLK_SET.cclk_div[3:0]. Assuming cclk_pre_div is the clock before frequency di vision. There is the following relationship expression: Fcclk = Fcclk_pre_div/n (n=CCLK_SET.cclk_div[3:0], n=1~15)

8.3 Module Clock

Registers CLKEN0~CLKEN7 are used to enable or disable clock for various modules. By disable the clocks of unused modules, current consumption could be reduced. D25F_DLM cclk N22_ILM hclk N22_DLM hclk PEM cclk, hclk, pclk RZ pclk KEYS pclk, clk_keyscan IR_LEARN pclk PWM pclk, clk32k eFuse pclk I2C0/1 pclk QDEC0/1 pclk, clk32k STIMER pclk, clk32k, clk_stimer SAR_ADC_DIG pclk, clk_sardig ALGM pclk TIMER pclk TIMER_N22 pclk UART0/1/2/3/4 pclk SPI_SLV hclk GPIO pclk Module Clock Source(s)

Datasheet for Telink TL3828 DS-TL3828-E5 160 Ver 0.8.0 8.3.1 clk_rram Fclk_rram = Fhclk/((n+1)*2) (n=CLKRRAM_RATIO[1:0], n=0~3) 8.3.2 clk_lspi The clk_lspi is the system clock of LSPI module. There are three selectable clock sources for clk_lspi: RC_24M derived from 24 MHz RC oscillator, 24 MHz crystal, and pll clk. The sources are selectable via register LSPI_MODE.lspi_sel[1:0]. And clk_lspi can be reduced in frequency via frequency divider which is controlled vi a register LSPI_MODE.lspi_div[3:0]. Assuming clklspi_pre_div is the clock before frequency division. Then there is the following relationship expression: Fclk_lspi = Fclklspi_pre_div/n (n=LSPI_MODE.lspi_div[3:0],n=1~15) 8.3.3 clk_gspi0 The clk_gspi0 are the clock of GSPI0 module. There are three selectable clock sources for clk_gspi0: RC_24M derived from 24 MHz RC oscillator, 24 MHz crystal, and pll clk. The sources are selectable vi a register GSPI_MODE_H.gspi_sel[1:0]. And clk_gspi0 can be lowered in frequency via frequency divider which is controlled via register GSPI_MODE_L.gspi_div[7:0]. Assuming clkgspi_pre_div is the clock before frequency division. Then there is the following relationship expression: Fclk_gspi0 = Fclkgspi_pre_div/n (n=GSPI_MODE_L.gspi_div[7:0],n=1~255) 8.3.4 clk_gspi1 The clk_gspi1 are the clock of GSPI module. There are three selectable clock sources for clk_g spi1: RC_24M derived from 24 MHz RC oscillator, 24 MHz crystal, and pll clk. The sources are selectable via register GSPI1_MODE_H.gspi1_sel[1:0]. And clk_gspi1 can be lowered in frequency via frequency divider which is controlled via register GSPI1_MODE_L.gspi1_div[7:0]. Assuming clkgspi1_pre_div is the clock before frequency division. Then there i s the following relationship expression: Fclk_gspi1 = Fclkgspi1_pre_div/n (n=GSPI1_MODE_L.gspi1_div[7:0],n=1~255) 8.3.5 clk_gspi2 The clk_gspi2 are the clock of GSPI module. There are three selectable clock sources for clk_gspi2: RC_24M derived from 24 MHz RC oscillator, 24 MHz crystal, and pll clk. The sources are selectable via register GSPI2_MODE_H.gspi2_sel[1:0]. And clk_gspi2 can be lowered in frequ ency via frequency divider which is controlled via register GSPI2_MODE_L.gspi2_div[7:0]. Assuming clkgspi2_pre_div is the clock before frequency division. Then there is the following relationship expression: Fclk_gspi2 = Fclkgspi2_pre_div/n (n=GSPI2_MODE_L.gspi2_div[7:0],n=1~255)

Datasheet for Telink TL3828 DS-TL3828-E5 161 Ver 0.8.0 8.3.6 clk_gspi3 The clk_gspi3 are the clock of GSPI3 module. There are three selectable clock sources for clk_gspi3: RC_24M derived from 24 MHz RC oscillator, 24 MHz crystal, and pll clk. The sources are selectable via register GSPI3_MODE_H.gspi3_sel[1:0]. And clk_gspi3 can be lowered in frequency via frequency divider which is controlled via register GSPI3_MODE_L. gspi3_div[7:0]. Assuming clkgspi3 _pre_div is the clock before frequency division. Then there is the following relationship expression: Fclk_gspi3 = Fclkgspi3_pre_div/n (n=GSPI3_MODE_L.gspi3_div[7:0],n=1~255) 8.3.7 clk_gspi4 The clk_gspi4 is the clock of GSPI4 module. There are three selectable clock sources for clk_gspi4: RC_24M derived from 24 MHz RC oscillator, 24 MHz crystal, and pll clk. The sources are selectable via register GSPI4_MODE_H.gspi4 _sel[1:0]. And clk_gspi4 can be lowered in frequency via frequency divider which is controlled via register GSPI4_MODE_L.gspi4_div[7:0]. Assuming clkgspi4_pre_div is the clock before frequency division. Then there is the following relationship expression: Fclk_gspi4 = Fclkgspi4_pre_div/n (n=GSPI4_MODE_L.gspi4_div[7:0],n=1~255) 8.3.8 clk_sardig The clk_sardig is the system clock of SAR ADC module. There are three selectable clock sources for clk_sardi g: RC_24M derived from 24 MHz RC oscillator, 24 MHz crystal, and pll clk. The sources are selectable via register ADCDIG_MODE.adcdig_sel[5:4]. And clk_sardig can be reduced in frequency via frequency divider which is controlled via register ADCDIG_MODE.adcdig_div[3:0]. Assuming clkadcdig_pre_div is the clock before frequency division. Then there is the followi ng relationship expression: Fclk_adcdig = Fclkadcdig_pre_div/n (n=ADCDIG_MODE.adcdig_div[3:0],n=1~15) 8.3.9 clk_sardig1 The clk_sardig1 is the system clock of SAR ADC1 module. There are three selectable clock sources for clk_sardig1: RC_24M derived from 24 MHz RC oscillator, 24 MHz crystal, and pll clk. The sources are selectable via register ADCDIG1_MODE.adcdig1_sel[5:4]. And clk_sardig1 can be reduced in frequency via frequency divider which is controlled via register ADCDIG1_MODE.adcdig1_div[3:0]. Assuming clkadcdig1_pre_div is the clock before frequency division. Then there is the following relationship expression: Fclk_adcdig1 = Fclkadcdig1_pre_div/n (n=ADCDIG1_MODE.adcdig1_div[3:0],n=1~15) 8.3.10 clk_i3c0 The clk_i3c0 is the system clock of I3C0 module.

Datasheet for Telink TL3828 DS-TL3828-E5 162 Ver 0.8.0 There are three selectable clock sources for clk_i3c0: RC_24M derived from 24 MHz RC oscillator, 24 MHz crystal, and pll clk. The sources are selectable via register I3C0_MODE.i3c0_sel[1:0]. And clk_i3c0 can be reduced in frequency via frequency divider which is controlled via register I3C0_MODE.i3c0_div[3:0]. Assuming clki3c0_pre_div is the clock before frequency division. Then there i s the following relationship expression: Fclk_i3c0 = Fclki3c0_pre_div/n (n=I3C0_MODE.i3c0_div[3:0],n=1~15) 8.3.11 clk_i3c1 The clk_i3c1 is the system clock of I3C1 module. There are three selectable clock sources for clk_i3c1: RC_24M derived from 24 MHz RC oscillator, 24 MHz crystal, and pll clk. The sources are selectable via register I3C1_MODE.i3c1_sel[1:0]. And clk_i3c1 can be reduced in frequency via fr equency di vider which is controlled via register I3C1_MODE.i3c1_div[3:0]. Assuming clki3c1_pre_div is the clock before frequency division. Then there is the following relationship expression: Fclk_i3c1 = Fclki3c1_pre_div/n (n=I3C1_MODE.i3c1_div[3:0],n=1~15) 8.3.12 clk_keyscan The clk_keyscan is the system clock of Keyscan module. There are three selectable clock sources for clk_keyscan: RC_24M derived from 24 MHz RC osci llator, 24 MHz crystal, and pll clk. The sources are selectable via register CLKKS_MODE.clkks_sel[1:0]. And clk_keyscan can be reduced in frequency via frequency divider which is controlled via register CLKKS_MODE.clkks_div[3:0]. Assuming clkks_pre_div is the clock before frequency division. Then there is the following relationship expression: Fclk_keyscan = Fclkks_pre_div/n (n=CLKKS_MODE.clkks_div[3:0],n=1~15)

8.3.13 System Timer Clock

System timer clock is derived from 24 MHz crystal oscillator.

8.3.14 I2S0 Clock

I2S0 clock is generated by pll_clk via frequency divider. Register I2S0_STEP_H[7] should be set as 1’b1 to enable I2S0 clock. I2S0 clock frequency dividing factor contains step and mod. Registers I2S0_STEP_H[6:0], I2S0_STEP_L[7:0], I2S0_MOD_H[7:0] and I2S0_MOD_L[7:0] serve to set I2S0 clock step[14:0] and mod[15:0] respectively, and mod should be no less than 2*step. I2S0 clock frequency, Fi2s0_clock, equals to pllclk*I2S0_step[14:0]/I2S0_mod[15:0].

8.3.15 I2S2 Clock

I2S2 clock is generated by pll_clk via frequency divider. Register I2S2_STEP_H[7] should be set as 1’b1 to enable I2S2 clock. I2S2 clock frequency dividing factor contains step and mod. Registers I2S2_STEP_H[6:0], I2S2_STEP_L[7:0], I2S2_MOD_H[7:0] and I2S2_MOD_L[7:0] serve to set I2S2 clock step[14:0] and mod[15:0] respectively, and mod should be no less than 2*step.

Datasheet for Telink TL3828 DS-TL3828-E5 163 Ver 0.8.0 I2S2 clock frequency, Fi2s2_clock, equals to pllclk*I2S2_step[14:0]/I2S2_mod[15:0].

8.3.16 USB0 Clock

Fclk_usb0 = Fpad_24m/2

8.3.17 DMIC Clock

DMIC clock is generated by pll_clk via frequency divider. Register DMIC_STEP_H[7] should be set as 1’b1 to enable DMIC clock. DMIC clock frequency dividing factor contains step and mod. Registers DMIC_STEP_H[6:0], DMIC_STEP_L[7:0], DMIC_MOD_H[7:0] and DMIC_MOD_L[7:0] serve to set DMIC clock step[14:0] and mod[15:0] respectively, and mod should be no less than 2*step. DMIC clock frequency, Fdmi c_clock, equals to pllclk*DMIC_step[14:0]/DMIC_mod[15:0]. 8.3.18 clk_7816 Fclk_7816 = Fpad_24m/n (n=CLK_DIV[6:4], n=2~7) Fclk_7816 = Fpad_24m/16 (n=CLK_DIV[6:4], n=0)

8.4 Register Description of Clock

Clock related registers are listed in table below. The base address of the following registers is 0x80140800. Table 8-2 Clock Related Registers Address Offset Name Type Description Reset Value 0x10 LSPI_MODE R/W [3:0]: lspi_mod [5:4]: lspi_div_in_sel 0x01 0x02 GSPI_MODE_L R/W [7:0]: gspi_mod_l 0x01 0x03 GSPI_MODE_H R/W [1:0]: gspi_div_in_sel 0x00 0x04 I3C0_MODE R/W [3:0]: i3c0_mod [5:4]: i3c0_div_in_sel 0x01 0x05 I3C1_MODE R/W [3:0]: i3c1_mod [5:4]: i3c1_div_in_sel 0x01 0x06 I2S0_STEP_L R/W [7:0]: i2s0_step_l 0x01 0x07 I2S0_STEP_H R/W [6:0]: i2s0_step_h [7]: i2s0_clk_en 0x00 0x08 I2S2_STEP_L R/W [7:0]: i2s2_step_l 0x01

Datasheet for Telink TL3828 DS-TL3828-E5 164 Ver 0.8.0 0x09 I2S2_STEP_H R/W [6:0]: i2s2_step_h [7]: i2s2_clk_en 0x00 0x0a I2S2_MOD_L R/W [7:0]: i2s2_mod_l 0x02 0x0b I2S2_MOD_H R/W [7:0]: i2s2_mod_h 0x00 0x0c D25F_SRAM_CFG R/W [3:0]: d25_dlm_size 0x05 0x0d N22_SRAM_CFG R/W [3:0]: n22_dlm_size [7:4]: n22_size 0x21 0x10 CACHE_INIT R/W [3:0]: rsvd [4]: suspend_en_clk32kplmt, Turn on machin timer 32k clock when mcu is in suspend mode [5]: wfi_off_cclklm, Turn off local memory clock when mcu is in WFI mode [6]: icache_disable_init [7]: dcache_disable_init 0x00 0x11 CLKKS_MODE R/W [4:0]: clkkeys_mod [6:5]: clkkeys_div_in_sel 0x01 0x12 CLKRRAM_RATIO R/W [1:0]: clkrram_ratio 0x00 0x14 MCU_CTRL0 W [7]: mcu_reboot 0x00 0x15 MCU_RESET_VECTOR_R1 R/W [7:0]: mcu_rst_vector_r1 0x00 0x16 MCU_RESET_VECTOR_R2 R/W [7:0]: mcu_rst_vector_r2 0x20 0x17 MCU_RESET_VECTOR_R3 R/W [7:0]: mcu_rst_vector_r3 0x00 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 165 Ver 0.8.0 0x18 BUSCLK_RATIO R/W [2:0]: busclk_ratio [2]0:mcu clk is the same as hclk, 1: mcu clk is 2 times of hclk [1:0]:0: hclk is the same as pclk, 1:hclk is 2 times of pclk, 2: hclk is 4 times of pclk cclk: hclk: pclk period ratio 3'b000: 1:1:1; 3'b001: 1:1:2; 3'b010: 1:1:4; 3'b100: 1:2:2; 3'b101: 1:2:4; 0x00 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 166 Ver 0.8.0 0x1a PROBE_CLK_SEL R/W [5:0]: probe_clk_sel 0x0: clk32k 0x1: rc24m 0x2: PLL 0x3: XTL24M 0x4: cclk 0x5: hclk 0x6: pclk 0x7: clk_rram 0x8: rsvd 0x9: clk_lspi 0xa: clk_gspi 0xb: clk_gspi1 0xc: clk_gspi2 0xd: clk_gspi3 0xe: clk_gspi4 0xf: clk_i3c0 0x10: clk_i3c1 0x11: clk_stimer 0x12: clk_sardig 0x13: clk_i2s0 0x14: clk_i2s2 0x15: clk_dmic 0x16: audio_dsm_debug 0x17: codec_adc_clk_6m 0x18: codec_adc_clk_1m 0x19: clk_7816 0x1a: bb_dbg_clk 0x1b: clk_usbphy0 0x1c: 0x1d: clk_usb_phy_clk 0x1e: clk_usb_utmi 0x1f: clk_usb_pll 0x20: clk_usb_pll2 0x21: clk_usb_pll3 0x22: clk_usb_pll4 0x23: clk_sardig1 0x24: clk_ks 0x00 0x1b ADCDIG_MODE R/W [3:0]: adcdig_mod actual divdier = adcdig_mod[3:0] [5:4]: adcdig_div_in_sel clkadcdig divider input selection, 0: rc24m; 1: xtl24m; 2: pll0; 3: rsvd 0x10 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 167 Ver 0.8.0 0x24 CLKEN0 R/W [0]: lspi [1]: i2c [2]: uart0 [3]: usb [4]: pwm [5]: timern22 [6]: uart1 [7]: swires 0xa0 0x25 CLKEN1 R/W [0]: uart3 [1]: stimer [2]: dma [3]: algm [4]: pke [5]: machinetime [6]: gspi [7]: sspi 0xa0 0x26 CLKEN2 R/W [0]: timer [1]: audio [2]: i2c1 [3]: rsvd [4]: mcu [5]: lm [6]: trng [7]: rsvd 0x30 0x27 CLKEN3 R/W [0]: qdec1 [1]: trace [2]: brom [3]: efuse [4]: rsvd [5]: qdec [6]: saradc [7]: rsvd 0x1e Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 168 Ver 0.8.0 0x28 CCLK_SET R/W [3:0]: cclk_div [5:4]: cclk_sel 0x01 0x2a I2S0_MOD_L R/W [7:0]: i2s0_mod_l 0x02 0x2b I2S0_MOD_H R/W [7:0]: i2s0_mod_h 0x00 0x2c DMIC_STEP_L R/W [7:0]:dmic_step_l 0x01 0x2d DMIC_STEP_H R/W [6:0]:dmic_step_h [7]: dmic_clk_sel 0x00 0x2e WAKEUPEN R/W [0]: rsvd [1]: gpio_wakeup_i, enable wakeup from gpio [2]: qdec_wakeup_i, enable wakeup from qdec [3]: ks_wakeup_i, enable wakeup from keyscan [4]: qdec1_wakeup_i, enable wakeup from qdec [5]: usb_pwdn_i, enable wakeup from usb [6]: usb resume, enable remote wakeup from USB [7]: standby ex 0x00 0x2f PWDNEN R/W [0]: suspend_en_o [4]: ramcrc_clren_tgl [5]: rst_all [7]: stall_en_trg 0x00 0x30 CLK_DIV R/W [6:4]: r_7816_mod, 7816 clk div [7]: r_7816_clk_en, 7816 clk enable 0x60 0x32 RAM_CRC R/W [1]: ram_crc_err [4]: rst_all_status [5]: watchdog_rst_status [6]: rst_mcu_status 0x02 0x33 SEL R/W [0]: jtag_sel [1]: adc_dig_clk_sel 0x00 0x36 DMIC_MOD_L R/W [7:0]: dmic_mod_l 0x02 0x37 DMIC_MOD_H R/W [7:0]: dmic_mod_h 0x00 0x38 SC_RRAM_CTRL0 R/W [0]: reg_en_io_rram 0x01 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 169 Ver 0.8.0 0x3b USB_DIV R/W [2:0]:usb_div 0x04 0x44 CLKEN4 R/W [0]: dc [1]: rsvd [2]: uart4 [3]: rsvd [4]: ske [5]: hash [6]: cclk [7]: zb 0x44 0x45 CLKEN5 R/W [0]: rsvd [1]: uart2 [3:2]: rsvd [4]: ir_learn [5]: keyscan [6]: pem [7]: saradc1 0x00 0x46 CLKEN6 R/W [0]: rz [1]: gspi1 [2]: gspi2 [3]: gspi3 [4]: gspi4 [5]: lin0 [6]: lin1 [7]: rram 0x80 0x47 CLKEN7 R/W [0]: rsvd [1]: can0 [2]: can1 [3]: i3c0 [4]: i3c1 [5]: n22 [6]: n22plmt [7]: dma1 0x00 0x48 GSPI1_MOD_L R/W [7:0]: gspi1_mod_l 0x01 0x49 GSPI1_MOD_H R/W [1:0]: gspi1_div_in_sel clkgspi divider input selection, 0: rc24m; 1: xtl24m; 2: pll0; 3: rsvd 0x00 0x4a GSPI2_MOD_L R/W [7:0]: gspi2_mod_l 0x01 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 170 Ver 0.8.0 0x4b GSPI2_MOD_H R/W [1:0]: gspi2_div_in_sel clkgspi divider input selection, 0: rc24m; 1: xtl24m; 2: pll0; 3: rsvd 0x00 0x4c GSPI3_MOD_L R/W [7:0]: gspi3_mod_l 0x01 0x4d GSPI3_MOD_H R/W [1:0]: gspi3_div_in_sel clkgspi divider input selection, 0: rc24m; 1: xtl24m; 2: pll0; 3: rsvd 0x00 0x4e GSPI4_MOD_L R/W [7:0]: gspi4_mod_l 0x01 0x4f GSPI4_MOD_H R/W [1:0]: gspi4_div_in_sel clkgspi divider input selection, 0: rc24m; 1: xtl24m; 2: pll0; 3: rsvd 0x00 0x66 ADCDIG1_MODE R/W [3:0]: adcdig1_mod actual divdier = adcdig_mod[3:0] [5:4]: adcdig1_div_in_sel clkadcdig divider input selection: 0: rc24m; 1: xtl24m; 2: pll0; 3: rsvd 0x01 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 171 Ver 0.8.0

9 Timer

9.1 Timer0/1 and Watchdog

The SoC supports two timers: Timer0 ~ Timer1. Timer0 and Timer1 support four modes: Mode 0 (System Clock Mode), Mode 1 (GPIO Trigger Mode), Mode 2 (GPIO Pulse Width Mode) and Mode 3 (Tick Mode), which are selectable via the register TMR_CTRL0 (address 0x80140140). In addition, the Timer0 and Timer1 support Input Capture function. The Input Capture function can be used with Mode 0 and Mode 3. Watchdog could reset chi p from unexpected hang up or malfunction.

9.1.1 Timer0/1

9.1.1.1 Mode

(1) Mode 0 (System Clock Mode) In Mode 0, pclk is employed as clock source. After Timer is enabled, Timer Tick (i.e. counting value) is increased by 1 on each positive edge of pclk from preset initial Tick value. Generally the initial Tick value is set to 0. Once current Timer Tick value matches the preset Timer C ompare (i .e. timing value), an interrupt is generated, Timer re-starts counting from 0 or continues counting and Timer status is updated. Steps of setting Timer0 for Mode 0 is taken as an example. Step 1 Set initial Tick value of Timer0 Set Initial value of Tick via registers TMR_TICK0_0~TMR_TICK0_3, from lowest byte to highest byte respectively. It’s recommended to clear initial Timer Tick value to 0. Step 2 Set Compare value of Timer0 Set registers TMR_COMP0_0~TMR_COMP0_3, from lowest byte to hi ghest byte respectively. Step 3 Set Timer0 to Mode 0 and enable Timer0 Set register TMR_CTRL0[1:0 ] to 2’b00 to select Mode 0; set register TMR_CTRL0[3] to 0 to wrap the tick value; set register TMR_CTRL3[0] to 1 to enable timer0 mode interrupt mask. Meanwhile set TMR_CTRL0 [2] to 1’b1 to enable Timer0. Timer0 starts counting upward, and Tick value is increased by 1 on each positive edge of pclk. When the Tick value is equal to the target Tick value set by registers TMR_COMP0_0~TMR_COMP0_3, it ge nerates i nterrupt signal and Tick re-starts counting from 0; if the register TMR_CTRL0[3] is set to 1, the Tick continues counting. Step 4 Interrupt processing After entering the interrupt, if Timer0 is not needed to continue working, TMR_CTRL0 [2] can be set to 1'b0 to disable Timer0, and the interrupt status bit can be cleared by writing a 1 to register TMR_STATS1[0]. (2) Mode 1 (GPIO Trigger Mode) In Mode 1, GPIO is employed as clock source. The “ M0”/“M1” ” register specifies the GPIO which generates counting signal for Timer0/Timer1 (details refer to the note on Polarity above Table 11-4).

Datasheet for Telink TL3828 DS-TL3828-E5 172 Ver 0.8.0 After Timer is enabled, Timer Tick (i.e. counting value) is increased by 1 on each positive/negative edge of GPIO (The “Polarity” register specifies the GPIO edge, details refer to the note on Polarity above Table 11-4) from preset initial Tick value. Generally the initial Tick value is set to 0. Once current Timer Tick value matches the preset Timer Compare (i.e. timing value), an interrupt is generated. Timer re-starts counting from 0 or continues counting and Timer status i s updated. Steps of setting Timer1 for Mode 1 is taken as an example. Step 1 Set initial Tick value of Timer1 Set Initial value of Tick via registers TMR_TICK1_0~TMR_TICK1_3, from lowest byte to highest byte respectively. It’s recommended to clear initial Timer Tick value to 0. Step 2 Set Compare value of Timer1 Set registers TMR_COMP1_0~TMR_COMP1_3, from lowest byte to highest byte respectively. Step 3 Select GPIO source and edge for Timer1 Select certain GPIO to be the clock source via setting “M1” register (details refer to the note on Polarity above Table 11-4). S elect positive edge or negative edge of GPIO input to trigger Timer1 Tick increment via setting “Polarity” register (details refer to the note on Polarity above Table 11-4). Step 4 Set Timer1 to Mode 1 and enable Timer1 Set TMR_CTRL0 [5:4] to 2’b01 to select Mode 1; set register TMR_CTRL0[7] to 0 to wrap the tick value; set register TMR_CTRL3[3] to 1 to enable timer1 mode interrupt mask. Meanwhile set TMR_CTRL0 [6] to 1’b1 to enable Timer1. Timer1 starts counting upward, and Timer1 Tick value is increased by 1 on each positive/ negative (speci fied during the 3 rd step) edge of GPIO. When the Tick value is equal to the Tick target value set in the TMR_COMP1_0~TMR_COMP1_3 registers, an interrupt signal is generated and the Tick starts counting again from 0. The Tick continues counting if register TMR_CTRL0[7] is set to 1. Step 5 Interrupt processing After entering the interrupt, if Timer1 is not needed to continue working, TMR_CTRL0 [6] can be set to 1'b0 to di sable Timer1, and the interrupt status bit can be cleared by writing a 1 to register TMR_STATS1[3]. (3) Mode 2 (GPIO Pulse Width Mode) In Mode 2, pclk is employed as the unit to measure the width of GPIO pulse. The “M0”/“M1” register specifies the GPIO which generates control signal for Timer0/Timer1 (details refer to the note on Polarity above Table 11-4). After Timer is enabled, Timer Tick is triggered by a positive/negative edge (The “Polarity” register specifies the GPIO edge, details refer to the note on P olari ty above Table 11-4 ) of GPIO pulse. Then Timer Tick (i.e. counting value) is increased by 1 on each positive edge of system clock from preset initial Tick value. Generally the initial Tick value is set to 0. While a negative/positive edge of GPIO pulse is detected, an interrupt is generated and timer stops counting. The GPIO pulse width could be calculated in terms of tick count and period of pclk. Steps of setti ng Timer1 for Mode 2 is taken as an example. Step 1 Set initial Timer1 Tick value

Datasheet for Telink TL3828 DS-TL3828-E5 173 Ver 0.8.0 Set Initial value of Tick via registers TMR_TICK1_0~TMR_TICK1_3, from lowest byte to highest byte respectively. It’s recommended to clear initial Timer Tick value to 0. Step 2 Select GPIO source and edge for Timer1 Select certain GPIO to be the clock source via setting “M1” register (details refer to the note on Polarity above Table 11-4). Select positive edge or negative edge of GPIO input to trigger Timer1 counting start via setting “Polarity” register (details refer to the note on Polarity above Table 11-4). Step 3 Set Timer2 to Mode 2 and enable Timer1 Set TMR_CTRL0 [5:4] to 2’b10 to select Mode 2; set register TMR_CTRL3[3] to 1 to enable timer1 mode interrupt mask. Meanwhile set TMR_CTRL0 [6] to 1’b1 to enable Timer1. Timer1 Tick is triggered by a positive/ negative (specified during the 2 nd step) edge of GPIO pulse. Timer1 starts counting upward and Ti mer1 Tick value is increased by 1 on each positive edge of pclk. While a negative/positive edge of GPIO pulse is detected, an interrupt is generated and Timer1 tick stops. Step 4 Interrupt processing After entering the interrupt, if Timer1 is not needed to continue working, TMR_CTRL0 [6] can be set to 1'b0 to disable Timer1, and the interrupt status bit can be cleared by writing a 1 to register TMR_STATS1[3]. Step 5 Read current Ti mer1 Tick value to calculate GPIO pulse width Read current Timer1 Tick value. Then GPIO pulse width is calculated as follows: GPIO Pulse Width = System Clock Period *(Current Timer1 Tick - Initial Timer1 Tick) For initial Timer1 Tick value is set to the recommended value of 0, then: GPIO Pulse Width = System Clock Period * Current Timer1 Tick (4) Mode 3 (Tick Mode) In Mode 3, pclk i s employed. After Timer is enabled, Timer Tick starts counting upward, and Timer Tick value is increased by 1 on each positive edge of pclk. This mode could be used as time indicator. There will be no interrupt generated. Timer Tick keeps rolling from 0 to 0xffffffff. When Timer tick overflows, it returns to 0 and starts counting upward again. Steps of setting Timer0 for Mode 3 is taken as an example. Step 1 Set i nitial Tick value of Timer0 Set Initial value of Tick via TMR_TICK0_1 ~TMR_TICK0_3, from lowest byte to highest byte respectively. Step 2 Set Timer0 to Mode 3 and enable Timer0 Set TMR_CTRL0[1:0 ] to 2’b11 to select Mode 3, meanwhile set address TMR_CTRL0[ 2] to 1’b1 to enable Timer0. Timer0 Tick starts to roll. Step 3 Read current Timer0 Tick value Current Timer0 Tick value can be read from TMR_TICK0_1 ~TMR_TICK0_3.

Datasheet for Telink TL3828 DS-TL3828-E5 174 Ver 0.8.0

9.1.1.2 Input Capture Function

Figure 9-1 Input Capture of Timer0/1 The input signal of GPIO is used as the capture_in signal of timer0/1, and the edge of capture_in signal is selected as the trigger pulse of capture through registers TMR_CTRL1[1:0]/TMR_CTRL1[5:4]. When the capture trigger pulse is generated, the current tick value of timer0/1 is latched into the registers TMR_CCAPT0/1[31:0]. If the register TMR_CTRL3[1]/TMR_CTRL3[4] is s et to 1 before that, ti mer0/1 capture interrupt will be generated, and the interrupt status can be viewed by reading register TMR_STATS1[1]/TMR_STATS1[4], and the interrupt status can be cleared by writing 1 to TMR_STATS1[1]/TMR_STATS1[4]. Here are two examples to illustrate how input capture works: 1. case1 Configure the registers TMR_CTRL0[1:0]/TMR_CTRL0[5:4] to be 2'b00, timer0/1 works in mode0; Configure the regi sters TMR_CTRL1[1:0]/TMR_CTRL1[5:4] to 2'b00, the rising edge of capture_in signal triggers capture; After timer0/1 is enabled, it starts counting from the preset tick value and adds 1 on the rising edge of pclk; The rising edge of capture_in signal triggers capture, and the tick value is latched into registers TMR_CCAPT0/ 1[31:0]; if registers TMR_CTRL3[1]/TMR_CTRL3[4] are set to 1 befor e thi s, a timer0/1 capture interrupt is generated; The CPU handles timer0/1 capture interrupt: read the value of register TMR_CCAPT0/1[31:0], write 1 to register TMR_STATS1[1]/TMR_STATS1[4] to clear this interrupt status.

Datasheet for Telink TL3828 DS-TL3828-E5 176 Ver 0.8.0

9.1.2 Watchdog

In watchdog, pclk is employed as clock source. The watchdog target register has 24bits, which consists of WT_TARGET_1~WT_TARGET_3 as byte 1 ~byte 3. When the high 24 bits of the counter are equal to the target register, watchdog can reset the chip and TMR_STATS0[0] is set to 1, but watchdog does not work in low-power mode. Step 1 Set WT_TARGET_1~WT_TARGET_3 Set registers WT_TARGET_1~WT_TARGET_3, from lowest byte to hi ghest byte respectively. Step 2 Enable Watchdog Set TMR_WD_EN[0] to 1’b1 to enable Watchdog. During normal working condition, TMR_STATS0[1] need write 1 to clean the watchdog before the watchdog hits WT_TARGET3-1, or it will reboot the whole chip, and the TMR_STATS0[0] will be assert to 1, this bit will be clean when write 1.

9.1.3 Register Description of Timer

Timer related register are listed in table below. The base address for the followi ng registers is 0x80140140. Target register 32-bit counter Compare Clear pclk Reset

Datasheet for Telink TL3828 DS-TL3828-E5 177 Ver 0.8.0 Table 9-1 Registers for Timer 0 ~ Timer 1 Address Offset Name Type Description Reset Value 0x00 TMR_CTRL0 R/W [1:0] tmr0m_sel, 0: tmr0m0,using pclk 1: tmr0m1, count gpio2risc0 posedge 2: tmr0m2 count gpio2risc0 high width 3: tmr0m3, tick [2] tmren0, Timer0 enable [3] tm0_nowrap, Timer0 nowrap [5:4] tmr1m_sel, 0: tmr1m0, using pclk 1: tmr1m1, count gpio2risc1 posedge 2: tmr1m2 count gpio2risc1 high width 3: tmr1m3,tick [6] tmren1, Timer1 enable [7] tm1_nowrap, Timer 1 nowrap 0x00 0x01 TMR_CTRL1 R/W [1:0] tmr0_capt_mode, 0: positive edge triggers timer0 capture 1: negative edge triggers timer0 catpure 2: both edges trigger timer0 capture [5:4] tmr1_capt_mode, 0: positive edge triggers timer1 capture 1: negative edge triggers timer1 catpure 2: both edges trigger timer1 capture 0x00 0x02 TMR_CTRL2 R/W [4] tmr0_capt_en, timer0 capture function enbale [6] tmr1_capt_en, timer1 capture function enbale 0x00 0x03 TMR_CTRL3 R/W [0]: tmr0_mode_mask, mode_mask [1]: tmr0_capt_mask, capt_mask [3]: tmr1_mode_mask, mode_mask [4]: tmr1_capt_mask, tmr1_capt_mask [6]: tmr0_ov_mask, timer0 overflow mask [7]: tmr1_ov_mask, timer1 overflow mask 0x00 0x04 TMR_CAPT0_0 R/W capt0[7:0] Byte 0 of timer0 capture/compare 0x00 0x05 TMR_CAPT0_1 R/W capt0[15:8] Byte 1 of timer0 capture/compare 0x00

Datasheet for Telink TL3828 DS-TL3828-E5 178 Ver 0.8.0 0x06 TMR_CAPT0_2 R/W capt0[23:16] Byte 2 of timer0 capture/compare 0x0 0x07 TMR_CAPT0_3 R/W capt0[31:24] Byte 3 of timer0 capture/compare 0x0 0x08 TMR_CAPT1_0 R/W capt1[7:0] Byte 0 of timer1 capture/compare 0x0 0x09 TMR_CAPT1_1 R/W capt1[15:8] Byte 1 of timer1 capture/compare 0x0 0x0a TMR_CAPT1_2 R/W capt1[23:16] Byte 2 of timer1 capture/compare 0x0 0x0b TMR_CAPT1_3 R/W capt1[31:24] Byte 3 of timer1 capture/compare 0x0 0x0d WT_TARGET_1 R/W watchdog_target[15:8] Byte 1 of watchdog target value 0x0 0x0e WT_TARGET_2 R/W watchdog_target[23:16] Byte 2 of watchdog target value 0x0 0x0f WT_TARGET_3 R/W watchdog_target[31:24] Byte 3 of watchdog target value 0x0 0x10 TMR_TICK0_0 R/W tick0[7:0] Byte 0 of timer0 ticker 0x0 0x11 TMR_TICK0_1 R/W tick0[15:8] Byte 1 of timer0 ticker 0x0 0x12 TMR_TICK0_2 R/W tick0[23:16] Byte 2 of timer0 ticker 0x0 0x13 TMR_TICK0_3 R/W tick0[31:24] Byte 3 of timer0 ticker 0x0 0x14 TMR_TICK1_0 R/W tick1[7:0] Byte 0 of timer1 ticker 0x0 0x15 TMR_TICK1_1 R/W tick1[15:8] Byte 1 of timer1 ticker 0x0 0x16 TMR_TICK1_2 R/W tick1[23:16] Byte 2 of timer1 ticker 0x0 0x17 TMR_TICK1_3 R/W tick1[31:24] Byte 3 of timer1 ticker 0x0 0x18 TMR_CCAPT0_0 R cca0[7:0] Byte0 of timer0 capture register 0x0 0x19 TMR_CCAPT0_1 R cca0[15:8] Byte1 of timer0 capture register 0x0 0x1a TMR_CCAPT0_2 R cca0[23:16] Byte2 of timer0 capture register 0x0 0x1b TMR_CCAPT0_3 R cca0[31:24] Byte3 of timer0 capture register 0x0 0x1c TMR_CCAPT1_0 R cca1[7:0] Byte0 of timer1 capture register 0x0 0x1d TMR_CCAPT1_1 R cca1[15:8] Byte1 of timer1 capture register 0x0 0x1e TMR_CCAPT1_2 R cca1[23:16] Byte2 of timer1 capture register 0x0 0x1f TMR_CCAPT1_3 R cca1[31:24] Byte3 of timer1 capture register 0x0 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 179 Ver 0.8.0

9.2 Timer_n22

Timer_n22 supports three timers: Timer0_n22, Timer1_n22, Timer2_n22. Timer0_n22, Timer1_n22 and Timer2_n22 support two modes: Mode 0 (System Clock Mode) and Mode 3 (Tick Mode), which are selectable via the register TMR_CTRL0 and TMR_CTRL1 (address 0x80240100).

9.2.1 Mode 0 (System Clock Mode)

In Mode 0, system clock is employed as clock source. 0x20 TMR_STATS0 R/W [0] wd_stat, watchdog status (wd_cnt == watch_dog target) [1] wd_cnt_clr, clear wd_cnt [6:2] reserved [7] soft_irq, software_irq 0x0 0x21 TMR_STATS1 W1C [0] tmr0_mode_irq, timer0 mode0/1/2 irq [1] tmr0_capt_irq, timer0 capture irq [3] tmr1_mode_irq, timer1 mode0/1/2 irq [4] tmr1_capt_irq, timer1 capture irq [6] tmr0_ov_irq, timer0 capture overflow irq [7] tmr1_ov_irq, timer1 capture overflow irq 0x0 0x22 TMR_WD_EN R/W [0] wd_en, watch dog enable [1] pem_event_en, pem event enable [2] pem_task_sel, pem_task_sel = 0, task select {capt1, capt0, wd_dis, wd_en, tick1_add, tick0_add, tick1_clr, tick0_clr}; pem_task_sel = 1, task select {timer1_dis, timer1_en, timer0_dis, timer0_en} 0x0 0x23 TMR_PEM_TASK _EN R/W [0]: pem_task0_0_en, pem task0_bit0 enable [1]: pem_task0_1_en, pem task0_bit1 enable [2]: pem_task0_2_en, pem task0_bit2 enable [3]: pem_task0_3_en, pem task0_bit3 enable [4]: pem_task0_4_en, pem task0_bit4 enable [5]: pem_task0_5_en, pem task0_bit5 enable [6]: pem_task0_6_en, pem task0_bit6 enable [7]: pem_task0_7_en, pem task0_bit7 enable 0x0 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 180 Ver 0.8.0 After Timer is enabled, Timer Tick (i.e. counting value) is increased by 1 on each positive edge of system clock from preset initial Tick value. Generally the initial Tick value is set to 0. Once current Timer Tick value matches the preset Timer Capture (i.e. timing value), an interrupt is generated, Timer stops counting and Timer status is updated. Steps of setting Timer0_n22 for Mode 0 i s taken as an example. Step 1 Set initial Tick value of Timer0 Set Initial value of Tick via registers TMR_TICK0_0~TMR_TICK0_3, from lowest byte to highest byte respectively. It’s recommended to clear initial Timer Tick value to 0. Step 2 Set Capture value of Timer0 Set registers TMR_CAPT0_0~TMR_CAPT0_3, from lowest byte to highest byte respectively. Step 3 Set Timer0 to Mode 0 and enable Timer0 Set register TMR_CTRL0 [0] to 1’b0 to select Mode 0; Meanwhile set TMR_CTRL0 [ 1] to 1’b1 to enable Timer0_n22. Timer0_n22 starts cou nti ng upward, and Tick value is increased by 1 on each positive edge of system clock until it reaches Timer0_n22 Capture value.

9.2.2 Mode 3 (Tick Mode)

In Mode 3, system clock is employed. After Timer is enabled, Timer Tick starts counting upward, and Timer Tick value is increased by 1 on each positive edge of system clock. This mode could be used as time indicator. There will be no interrupt generated. Timer Tick keeps rolli ng from 0 to 0xffffffff. When Timer tick overflows, it returns to 0 and starts counting upward again. Steps of setting Timer0_n22 for Mode 3 is taken as an example. Step 1 Set initial Tick value of Timer0 Set Initial value of Tick via TMR_TICK0_1 ~TMR_TICK0_3, from lowest byte to highest byte respectively. Step 2 Set Timer0 to Mode 3 and enable Timer0 Set TMR_CTRL0 [0] to 1’b1 to select Mode 3, meanwhile set address TMR_CTRL0 [1] to 1’b1 to enable Timer0_n22. Timer0_n22 Tick starts to roll. Step 3 Read current Ti mer0 Tick value Current Timer0_n22 Tick value can be read from TMR_TICK0_1 ~TMR_TICK0_3.

9.2.3 Register Description of Timer_N22

Timer_n22 related register are listed in table below. The base address for the following registers is 0x80240100.

Datasheet for Telink TL3828 DS-TL3828-E5 181 Ver 0.8.0 Table 9-2 Registers for Timer_n22 Address Offset Name Type Description Reset Value 0x00 TMR_CTRL0 R/W [0]: tmr0m_sel, 0: tmr0m0, using pclk; 1: tmr0m3, tick [1]: tmren0_en, Timer0_n22 enable [2]: tm0_nowrap, Timer0_n22 nowrap [4]: tmr1m_sel, 0: tmr1m0, using pclk; 1: tmr1m3, tick [5]: tmren1_en, Timer1_n22 enable [6]: tm1_nowrap, Timer1_n22 nowrap 0x00 0x01 TMR_CTRL1 R/W [1:0]: tmr2m_sel, 0: tmr2m0, using pclk; 1: tmr2m3, tick [2]: tmren2_en, Timer2_n22 enable [3]: tm2_nowrap, Timer2_n22 nowrap 0x00 0x02 TMR_INT_MASK R/W [0]: tmr0_int_mask, timer0 mode0_irq mask [1]: tmr1_int_mask, timer1 mode0_irq mask [2]: tmr2_int_mask, timer2 mode0_irq mask 0x00 0x03 TMR_INT_STS R [0]: tmr0_int_status, timer0 mode0_irq status [1]: tmr1_int_status, timer1 mode0_irq status [2]: tmr2_int_status, timer2 mode0_irq status 0x00 0x04 TMR_CAPT0_0 R/W capt0[7:0] Byte 0 of timer0_n22 capture 0x00 0x05 TMR_CAPT0_1 R/W capt0[15:8] Byte 1 of timer0_n22 capture 0x00 0x06 TMR_CAPT0_2 R/W capt0[23:16] Byte 2 of timer0_n22 capture 0x00 0x07 TMR_CAPT0_3 R/W capt0[31:24] Byte 3 of timer0_n22 capture 0x00 0x08 TMR_CAPT1_0 R/W capt1[7:0] Byte 0 of timer1_n22 capture 0x00 0x09 TMR_CAPT1_1 R/W capt1[15:8] Byte 1 of timer1_n22 capture 0x00 0x0a TMR_CAPT1_2 R/W capt1[23:16] Byte 2 of timer1_n22 capture 0x00 0x0b TMR_CAPT1_3 R/W capt1[31:24] Byte 3 of timer1_n22 capture 0x00 0x0c TMR_CAPT2_0 R/W capt1[7:0] Byte 0 of timer2_n22 capture 0x00

Datasheet for Telink TL3828 DS-TL3828-E5 182 Ver 0.8.0 9.3 32K LTimer The SoC also supports a low frequency (32 kHz) LTIMER in suspend mode or deep sleep mode. This timer can be used as one kind of wakeup source. In order to avoid the situation of not being able to wake up in low power mode and power on error, a new ltimer_watchdog function has been added to the 32 kHz timer. And the ltimer_watchdog function is enabled by default. The 32K LTimer features i nclude:

• The frequency of the clock source is 32 KHz;
• The width of the LTimer is 32 bits;
• Supports ltimer_watchdog function;
• Can be used as one of wakeup sources 0x0d TMR_CAPT2_1 R/W capt1[15:8] Byte 1 of timer2_n22 capture 0x00 0x0e TMR_CAPT2_2 R/W capt1[23:16] Byte 2 of timer2_n22 capture 0x00 0x0f TMR_CAPT2_3 R/W capt1[31:24] Byte 3 of timer2_n22 capture 0x00 0x10 TMR_TICK0_0 R/W ticko[7:0] Byte 0 of timer0_n22 ticker 0x00 0x11 TMR_TICK0_1 R/W ticko[15:8] Byte 1 of timer0_n22 ticker 0x00 0x12 TMR_TICK0_2 R/W ticko[23:16] Byte 2 of timer0_n22 ticker 0x00 0x13 TMR_TICK0_3 R/W ticko[31:24] Byte 3 of timer0_n22 ticker 0x00 0x14 TMR_TICK1_0 R/W tick1[7:0] Byte 0 of timer1_n22 ticker 0x00 0x15 TMR_TICK1_1 R/W tick1[15:8] Byte 1 of timer1_n22 ticker 0x00 0x16 TMR_TICK1_2 R/W tick1[23:16] Byte 2 of timer1_n22 ticker 0x00 0x17 TMR_TICK1_3 R/W tick1[31:24] Byte 3 of timer1_n22 ticker 0x00 0x18 TMR_TICK2_0 R/W tick1[7:0] Byte 0 of timer2_n22 ticker 0x00 0x19 TMR_TICK2_1 R/W tick1[15:8] Byte 1 of timer2_n22 ticker 0x00 0x1a TMR_TICK2_2 R/W tick1[23:16] Byte 2 of timer2_n22 ticker 0x00 0x1b TMR_TICK2_3 R/W tick1[31:24] Byte 3 of timer2_n22 ticker 0x00 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 183 Ver 0.8.0 Figure 9-5 ltimer_watchdog The corresponding register configuration is as follows. Table 9-3 32K LTimer Related Registers Address Name Description Default Value afe_0x64 status write 1 to clean the status: [0]: wkup pad [1]: wkup dig [2]: wkup timer [3]: wkup cmp [4]: ctb_error_irq [5]: ctb_irq [6]: rsvd [7]: vbus on (this bit is set to 1 when there is voltage on vbus, write 1 for hardware reset and clear to 0 when vbus rst timer is reset.) Read only afe_0x69 pg status 1: indicate power down status [0]: zb power status [1]: usb power status [2]: audio power status [5:3]: rsvd [6]: vbus_detect [7]: wd_st; watch_dog status, write 1 to clear Read only afe_0x79 ltimer_watchdog_ en [0]: ltimer_watchdog_en [3:1] rsvd [7:4] rsvd, ltimer_watchdog_v[7:0] is 0x0 Target register 32-bit counter Compare clk32k Reset

Datasheet for Telink TL3828 DS-TL3828-E5 184 Ver 0.8.0 The afe_0x79[0] is the ltimer_watchdog enable signal, write 1 to enable the ltimer_watchdog function, write 0 to disable the ltimer_watchdog. The afe_0x7a to afe_0x7c combined into ltimer_watchdog_v[31:8] is the target value corresponding to the 32k timer reset for the entire system. The time range that can be set is: 8ms ~ 134217720 ms. The default value is 0x271, which is 0x27100 for 32k cycle, correspondi ng to 5 seconds. (After power up, if the firmware does not modify this value in time, it will reset the whole system after 5 seconds). The afe_0x69[7] is the status of watch dog, write 1 to clear the status. The difference between this watch dog and the regular watch dog is that clearing the dog is achieved by modifying the ltimer_watchdog_v value. Because the 32k timer is reused, the calculator keeps addi ng until the count reaches the maximum value and then continues from 0. When modifying the value, the enable signal needs to be disabled first.

9.4 System Timer

The SoC also supports a System Timer, the clock frequency for System Timer is fixed as 24 MHz irrespective of system clock (refers to 8.3.13 System Timer Clock). The System Timer supports Input Capture function (refers to the i nput capture function description in 9.1.1 Timer0/1). In suspend mode, both System Timer and Timer0 ~ Timer1 stop counting, and 32K Timer starts counting. When the chip restores to active mode, Timer0 ~ Timer1 will reset tick to 0; In contrast, System Timer will continue counting from an adjusted number which is a sum of the number when it stops and an offset calculated from the counting value of 32K Ti mer during suspend mode.

9.4.1 Enable Mode

There are two ways to enable sys_timer: manual mode and auto mode. Manual mode:

• enable sys_timer: SYS_TIMER_CTRL[1] is set to 1.
• disable sys_timer: SYS_TIMER_CTRL[1] is set to 0. Auto mode:
• enable sys_timer: First, set SYS_TIMER_CTRL[2] to 1, enable timer_auto. Then, when SYS_TIMER_UP[1] is set to 0, enable sys_timer automatically during write operation to SYS_TIMER0~SYS_TIMER3 regi sters. When SYS_TIMER_UP[1] is set to 1, sys_timer is automatically afe_0x7a ltimer_watchdog_ v[15:8] [7:0] ltimer_watchdog_v[15:8] 01110001 afe_0x7b ltimer_watchdog_ v[23:16] [7:0] ltimer_watchdog_v[23:16] 00000010 afe_0x7c ltimer_watchdog_ v[31:24] [7:0] ltimer_watchdog_v[31:24] 0 Address Name Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 185 Ver 0.8.0 enabled at the first rising edge of clk_32k after a write operation is performed to SYS_TIMER0~SYS_TIMER3 registers.

• disable sys_timer: first, set SYS_TIMER_CTRL[2] to 1, enable timer_auto; then, set SYS_TIMER_CTRL[2] to 1, enable timer_auto.

9.4.2 Irq_level Interrupt

There are two irq_level interrupts, one for D25F and the other for N22. The irq_level interrupt condition is: irq_level <= sys_timer < i rq_level+2^26. Irq_level Interrupt of D25F is generated in the following cases. 1. Case 1: SYS_TIMER_CTRL2[0] is set to 0 or SYS_TIMER_UP[1] is set to 0. When sys_timer meets the irq_level interrupt condition, the irq_level_pulse is generated immediately. If SYS_TIMER_IRQ_MASK[3] is set to 1 before irq_level_pulse, irq_level interrupt is triggered. If SYS_TIMER_IRQ_MASK[3] is set to 1 after irq_level_pulse, i rq_level interrupt is not triggered. 2. Case 2: SYS_TIMER_CTRL2[0] is set to 1,and SYS_TIMER_UP[1] is set to 1, but there is no write operation to SYS_TIMER0~SYS_TIMER3 registers. When sys_timer meets the irq_level interrupt condition, then irq_level_pulse is generated immediately. If SYS_TIMER_IRQ_MASK[3] is set to 1 before irq_level_pulse, irq_level interrupt is triggered. If SYS_TIMER_IRQ_MASK[3] i s set to 1 after irq_level_pulse, irq_level interrupt is not triggered. 3. Case 3: SYS_TIMER_CTRL2[0] is set to 1 and SYS_TIMER_UP[1] is set to 1. Write operation is performed to SYS_TIMER0~SYS_TIMER3 registers. Between the moment of the write operation of the SYS_TIMER0~SYS_TIMER3 registers and the moment of the rising edge of clk_32k, no irq_level_pulse is generated even if sys_timer meets the i rq_level interrupt condition. Outside this time interval, sys_timer meets the irq_level interrupt condition before generating an irq_level_pulse. An irq_level interrupt is triggered if SYS_TIMER_IRQ_MASK[3] is set to 1 before the irq_level_pulse. If SYS_TIMER_IRQ_MASK[3] is set to 1 after irq_level_pulse, irq_level interrupt is not triggered. 4. Case 4: The irq_level interrupt is a pulse trigger, that i s, irq_level_pulse triggers irq_level interrupt. In case 1 to case 3, if SYS_TIMER_IRQ_MASK[0] is set to 1 after irq_level_pulse, irq_level_pulse does not trigger irq_level interrupt, even if the irq_level interrupt condition is met after SYS_TIMER_IRQ_MASK[0] is set to 1. Therefore, when sys_timer is in the above situation, you can set SYS_TIMER_CTRL2[0] to 1, and then change the value of i rq_level. If the changed value of irq_level meets the condition of irq_level interrupt, it will generate an irq_level_pulse again, which will trigger the irq_level interrupt. level interrupt.

9.4.3 Calibration Function

Since the RC32k clock is not accurate, it is needed to calculate the actual RC32k frequency by using the accurate system timer clock. The Calibration process is as follows: SYS_TIMER_CTRL[3] is set to 1, wait for the fi rst clk_32k rising edge, and then enable the calibration; After calibration is enabled, at the rising edge of system timer clock, the counter cal_cnt will be added 1; at the rising edge of clk_32k, the counter ccnt will be added 1; When ccnt equals to 2^(16-SYS_TIMER_CTRL[7:4]), ccnt is reset to 0, cal_cnt is reset to 1, and the value of cal_cnt at this time is latched into CAL_LATCH0~CAL_LATCH3 regi sters, that is

Datasheet for Telink TL3828 DS-TL3828-E5 186 Ver 0.8.0 2^(16 - SYS_TIMER_CTRL[7:4]) × TRC32K = cal_latch × T(system_timer_clock); irq_cal interrupt: After SYS_TIMER_IRQ_MASK[0] is set to 1, and calibration is enabled, irq_cal interrupt is generated when ccnt equals 2^(16-SYS_TIMER_CTRL[7:4]). 9.4.4 32K_Timer Set/Read Function 32k_Timer set flow: After SYS_TIMER_CTRL[0] is set to 1, SYS_TIMER_ST[3] is set to 1 to start the 32k_Timer set, during which the system timer module synchronizes the contents of the 32K_TIMER_SET0~32K_TIMER_SET3 regi sters to the 32ktimer counter; Reading SYS_TIMER_ST[3] as 1 indicates that the 32k_Timer set is in progress; Reading SYS_TIMER_ST[3] as 0 indicates that the 32k_Timer set is finished. 32k_Timer read flow: First SYS_TIMER_ST[5] is set to 1 to clear the state of this bit; After SYS_TIMER_CTRL[0] is set to 0, wait for the first clk_32k rising edge to arrive, then start 32k_Timer read, during this period, the system ti mer module synchronizes the 32ktimer counter value to the 32K_TIMER_READ0~32K_TIMER_READ3 registers. Reading SYS_TIMER_ST[6] as 1 indicates that the 32k_Timer read is in progress; Reading SYS_TIMER_ST[6] as 0 indicates that the 32k_Timer read is finished;

9.4.5 Update on 32K clock

When SYS_TIMER_UP[0] is set to 0: whenever sys_timer[2:0] is read as 0, the tick value of sys_timer will be latched into SYS_TIMER0~SYS_TIMER3 regi sters, sys_timer[2:0] are fixed to 0. When SYS_TIMER_UP[0] is set to 1: whenever the rising edge of clk_32k, the tick value of sys_timer is latched to SYS_TIMER0~SYS_TIMER3 registers.

9.4.6 Register Description of System Timer

System timer related registers are listed in table below. The base address for the registers is 0x80140200. Table 9-4 System Timer Related Registers Address Offset Name Type Description Reset Value 0x00 SYS_TIMER0 R/W [7:0]: sys_timer0 when reading this byte, the lower 3bits are fixed to 0 0x00 0x01 SYS_TIMER1 R/W [7:0]: sys_timer1 0x00 0x02 SYS_TIMER2 R/W [7:0]: sys_timer2 0x00 0x03 SYS_TIMER3 R/W [7:0]: sys_timer3 0x00

Datasheet for Telink TL3828 DS-TL3828-E5 187 Ver 0.8.0 0x04 IRQ_LEVEL0 R/W [7:0]: irq_level0, irq_level[7:0] 0xf0 0x05 IRQ_LEVEL1 R/W [7:0]: irq_level1, irq_level[15:8] 0x0f 0x06 IRQ_LEVEL2 R/W [7:0]: irq_level2, irq_level[23:16] 0x0f 0x07 IRQ_LEVEL3 R/W [7:0]: irq_level3, irq_level[31:24] 0x0e 0x08 STIMER_IRQ_MASK R/W [0]: cal_irq_mask [1]: capt_irq_mask [2]: ov_irq_mask, capture overfolw irq mask [3]: d25f_level_irq_mask, d25f stimer_level_irq mask 0x00 0x09 CAL_IRQ W1C [0]: d25f stimer_level_irq, write 1 to clear d25f stimer_level_irq flag [1]: cal_irq, write 1 to clear calibration irq flag [2]: capt_irq, write 1 to clear capture irq flag [3]: ov_irq, write 1 to clear capture overflow irq flag 0x00 0x0a SYS_TIMER_CTRL R/W [0]: wr_32k, 1: 32k write mode; 0: 32k read mode [1]: timer_en, system timer enable [2]: timer_auto [3]: cal_32k_en, 32k calibration enable [7:4]: cal_32k_mode, 32k calibration mode (2^(16- cal_32k_mode)) cycles of 32k clock 0xc1 0x0b SYS_TIMER_ST R/W [1]: cmd_stop, write 1, stop system timer when using auto mode [3]: cmd_sync, write 1, start 32k count write; R:st_list3(wr_busy) [4]: clk_32k, 32k clock read [5]: clr_rd_done, clear read 32k update flag; R:st_list5(rd_done) [6]: rd_busy, 32k read busy status [7]: cmd_set_dly_done, system timer set done status upon next 32k posedge 0x00 0x0c TIMER_SET0_32K R/W [7:0]: timer_set0_32k, 32k_timer_set[7:0] 0x00 0x0d TIMER_SET1_32K R/W [7:0]: timer_set1_32k, 32k_timer_set[15:8] 0x00 0x0e TIMER_SET2_32K R/W [7:0]: timer_set2_32k, 32k_timer_set[23:16] 0x00 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 188 Ver 0.8.0 0x0f TIMER_SET3_32K R/W [7:0]: timer_set3_32k, 32k_timer_set[31:24] 0x00 0x10 TIMER_READ0_32K R [7:0]: timer_read0_32k, 32k_timer_read[7:0] 0x00 0x11 TIMER_READ1_32K R [7:0]: timer_read1_32k, 32k_timer_read[15:8] 0x00 0x12 TIMER_READ2_32K R [7:0]: timer_read2_32k, 32k_timer_read[23:16] 0x00 0x13 TIMER_READ3_32K R [7:0]: timer_read3_32k, 32k_timer_read[31:24] 0x00 0x14 CAL_LATCH0_32K R [7:0]: cal_latch0_32k, cal_latch[7:0] 0x00 0x15 CAL_LATCH1_32K R [7:0]: cal_latch1_32k, cal_latch[15:8] 0x00 0x16 CAL_LATCH2_32K R [7:0]: cal_latch2_32k, cal_latch[23:16] 0x00 0x17 CAL_LATCH3_32K R [7:0]: cal_latch3_32k, cal_latch[31:24] 0x00 0x18 SYSTIMER_UP_32K R/W [0]: update_upon_32k [1]: run_upon_nxt_32k 0x00 0x19 SYS_TIMER_CTRL1 R/W [1:0]: capt_mode, capture mode [2]: capt_en, capture enable [3]: pem_event_en, pem event enable [4]: pem_task_0_en, pem task0 enable [5]: pem_task_1_en, pem task1 enable [6]: pem_task_2_en, pem task2 enable 0x00 0x1a SYS_TIMER_CTRL2 R/W [0]: d25f_irq_wait [4]: td25f_rig_past_en 0x00 0x1c SYS_TIMER_CAPT_0 R [7:0]: capt_0, capt[7:0], Byte 0 of sys_timer capture 0x00 0x1d SYS_TIMER_CAPT_1 R [7:0]: capt_1, capt[15:8], Byte 1 of sys_timer capture 0x00 0x1e SYS_TIMER_CAPT_2 R [7:0]: capt_2, capt[23:16], Byte 2 of sys_timer capture 0x00 0x1f SYS_TIMER_CAPT_3 R [7:0]: capt_3, capt[31:24], Byte 3 of sys_timer capture 0x00 0x20 IRQ1_LEVEL0 R/W [7:0]: irq1_level0, irq1_level[7:0] 0xff 0x21 IRQ1_LEVEL1 R/W [7:0]: irq1_level1, irq1_level[15:8] 0xf 0x22 IRQ1_LEVEL2 R/W [7:0]: irq1_level2, irq1_level[23:16] 0x00 0x23 IRQ1_LEVEL3 R/W [7:0]: irq1_level3, irq1_level[31:24] 0x00 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 189 Ver 0.8.0

9.5 Platform-Level Machine Timer of D25F

9.5.1 Introduction

The RISC-V architecture defines a machine timer that provides a real-time counter and generates timer interrupts. Platform-Level Machine Timer (PLMT) is an implementation of the machine timer. PLMT supports the following features:

• Supports 64-bit mtime and mtimecmp
• Supports timer interrupt generation when mtime >= mtimecmp The PLMT block diagram is shown in the figure below. F igure 9-6 Block Diagram of PLMT PLMT primarily consists of these memory-mapped registers: mtime and mtimecmp. The mtime register is a 64-bit real-time counter clocked by mtime_clk. The source of mtime_clk is clk32k. The mtimecmp register stores a 64-bit value for comparing with mtime. When the value in mtime is greater than or equal to the value in mtimecmp, the mtip signal is asserted for generating a timer interrupt. When mtimecmp i s written, the interrupt is cleared and the mtip signal is deasserted. The mtime register is driven by mtime_clk, which is assumed to be slower than hclk. The mtime_shadow shadow register is maintained in the hclk domain to reduce the latency of accessing the mtime register in the slow clock domain. The values of mtime and mtime_shadow registers are constantly synchronized such that mtime_shadow mai ntains the most up-to-date values of mtime. The value in mtime_shadow is instantly 0x28 STIMER_IRQ1_MASK - [0]: n22_level_irq_mask, n22 stimer_level_irq mask [1]: n22_irq_wait [2]: n22_trig_past_en 0x00 0x29 STIMER_IRQ1 W1C [0]: n22 stimer_level_irq, write 1 to clear n22 stimer_level_irq 0x00 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 190 Ver 0.8.0 returned when reading the mtime register. When writing the mtime register, bus write transactions finish when the values are written to the mtime_shadow register, and PLMT handles the synchronization to mtime in the background.

9.5.2 Access To Mtime

The mtime counter is a 64-bit value and it increments non-stop on every machine timer clock except the first few cycles after its control register updates. But i t can only be accessed as two separate 32-bit registers by 32- bit width bus. So, please follow the following programming sequence to make sure the access to mtime is correct. For Write Mtime sequence: 1. Write zero to mtime[31:0]. 2. Write high part of the intended value to mtime[63:32]. 3. Write low part of the intended value to mtime[31:0]. For Read Mtime sequence: 1. Read mtime[63:32] and save it to i nteger variable hi0. 2. Read mtime[31:0] and save it to integer variable lo0. 3. Read mtime[63:32] and save it to integer variable hi1. 4. If hi1 is not equal to hi0, jump to step 1. Otherwise, return ((unsigned long long)hi0 << 32) | lo0;

9.5.3 Access To Mtimecmp

The mtimecmp register is a 64-bit value. But it can only be accessed as two separate 32-bit registers by 32-bit width bus.So, please follow the following programmi ng sequence to avoid spuriously generating an interrupt due to the intermediate value of the mtimecmp register. For Write Mtimecmp sequence: 1. Write 0xFFFFFFFF to mtimecmp[31:0]. 2. Write high part of the intended value to mtimecmp[63:32]. 3. Write low part of the intended value to mtimecmp[31:0].

9.5.4 Register Description of PLMT

The PLMT related registers are listed in table below. The base address for the following registers is 0xC6000000. Please note that PLMT supports only 32-bit. Behavi ors of 8-bit and 16-bit transfers are UNDEFINED, and these transfers might be ignored as well as result in error responses or unexpected register updates. Table 9-5 PLMT Related Registers Offset Name Type Description Reset Value 0x00 mtime_low R/W low part of mtime [31:0]: mtime[31:0] 0x00

Datasheet for Telink TL3828 DS-TL3828-E5 191 Ver 0.8.0

9.6 Integrated Machine Timer of N22

9.6.1 Introduction

The Integrated Machine Timer (IMT) supports the following features:

• Supports 64-bit mtime and mtimecmp
• Supports timer interrupt generation when mtime >= mtimecmp
• Supports mtimestop register that enables programs running on the processor to stop the machine timer by writing 1 to it
• Supports adding the msip register to the list of programmable machine timer registers to control the software i nterrupt generation The IMT block diagram is shown in the figure below. Figure 9-7 Block Diagram of IMT IMT primarily consists of these memory-mapped registers: mtime and mtimecmp. The mtime register is a 64- bit real-time counter clocked by mtime_clk x 2. The source of mtime_clk is clk32k. The machine timer implements two additional memory-mapped registers: mtimestop and msip.

9.6.2 Access To Mtime

The mtime counter is a 64-bit value and i t increments non-stop on every machine timer clock except the first few cycles after its control register updates. But it can only be accessed as two separate 32-bit registers by 32- 0x04 mtime_high R/W high part of mtime [31:0]: mtime[63:32] 0x00 0x08 mtimecmp_low R/W low part of mtimecmp [31:0]: mtimecmp[31:0] 0xFFFFFFFF 0x0c mtimecmp_high R/W high part of mtimecmp [31:0]: mtimecmp[63:32] 0xFFFFFFFF Offset Name Type Description Reset Value Processor Core IMT mtime mtimecmp mtimestop msip MSIP (software interrupt) MTIP (mtime interrupt) Stop mtime clk32k

Datasheet for Telink TL3828 DS-TL3828-E5 192 Ver 0.8.0 bit width bus. So, please follow the following programming sequence to make sure the access to mtime is correct. For Write Mtime sequence: 1. Write zero to mtime[31:0]. 2. Write high part of the intended value to mtime[63:32]. 3. Write low part of the intended value to mtime[31:0]. For Read Mtime sequence: 1. Read mtime[63:32] and save it to integer variable hi0. 2. Read mtime[31:0] and save i t to integer variable lo0. 3. Read mtime[63:32] and save it to integer variable hi1. 4. If hi1 is not equal to hi0, jump to step 1. Otherwise, return ((unsigned long long)hi0 << 32) | lo0

9.6.3 Access To Mtimecmp

The mtimecmp register is a 64-bit value. But it can only be accessed as two separate 32-bit registers by 32-bit width bus.So, please follow the following programming sequence to avoid spuriously generating an interrupt due to the i ntermediate value of the mtimecmp register. For Write Mtimecmp sequence: 1. Write 0xFFFFFFFF to mtimecmp[31:0]. 2. Write high part of the intended value to mtimecmp[63:32]. 3. Write low part of the intended value to mtimecmp[31:0].

9.6.4 Register Description of IMT

The IMT related registers are listed in table below. The base address for the following registers is 0xe6000000. Please note that these registers should only be accessed through word si zed load/stores. Behaviors of byte and half-word sized accesses are UNDEFINED, and these kinds of accesses might be ignored as well as result in unexpected register updates or errors. Table 9-6 IMT Related Registers Offset Name Type Description Reset Value 0x00 mtime_low R/W low part of mtime [31:0]: mtime[31:0] 0x0 0x04 mtime_high R/W high part of mtime [31:0]: mtime[63:32] 0x0 0x08 mtimecmp_low R/W low part of mtimecmp [31:0]: mtimecmp[31:0] 0xffffffff 0x0c mtimecmp_high R/W high part of mtimecmp [31:0]: mtimecmp[63:32] 0xffffffff

Datasheet for Telink TL3828 DS-TL3828-E5 193 Ver 0.8.0 0xff8 mtimestop R/W [0]: mtimestop 0x0 0xffc msip R/W [0]: msip 0x0 Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 194 Ver 0.8.0

10 Audio

This chapter includes audio architecture, system clock, SDM (Sigma-Delta Modulation), ASCL (Asynchronous Sample rate Conversion with Linear interpolation), CODEC, FIFO (First-In-First-Out), MUX, and Interrupt.

10.1 Introduction

The figure below shows the audio architecture. Figure 10-1 Audio Architecture The audio features:

• Include one I2S which supports TDM (Time Division Multiplexing) mode and 2-line mode
• Supports 1-group stereo SDM
• The i nternal CODEC supports 1-channel ADC or 1-group stereo DMIC
• Supports 4-channel DMA transmission (2-channel RX + 2-channel TX)
• I2S and TX of SDM support adjusting transmitting sample rate via ASCL ASCL-32bit SDML SDMR CODEC DIG_GAIN I2S (L&R) USB_RX_ISO Rxfifo0 Rxfifo1 16/20/24 16/20 fifo_wr0/1 fifo_rd0/1 fifo_rdata fifo_wdata fififofo w_wdadatata Ahb2fifo ARX_MUX ASCL-32bit ATX_MUX txfifo0 txfifo1 USB TX ISO ASYNCR 16/20/24 conversion USB_sync

Datasheet for Telink TL3828 DS-TL3828-E5 195 Ver 0.8.0

10.2 Audio System Clock

Figure 10-2 Audio System Clock There are 3 types of clocks in this audio system: audio_clk, sdm_clk and i2s_clk, as well as hclk and pclk.

• audio_clk: This clock is the master clock of the audio system, the modules of MUX, ASCL, CODEC, DIG_GAIN in the audio_arch architecture diagram is using this clock. The audio_clk needs to be fixed to 24MHz (22.5792 MHz, 24.576 MHz, 33.8688 MHz, 36.864 MHz in some speci al cases), and in the CODEC, 2 divisions are performed to get 12 MHz (11.2896 MHz, 12.288 MHz, 16.9344 MHz, 18.432 MHz in some special cases) as the master clock of the CODEC.
• i2s_clk: This clock is used as the clock for the I2S module.
• sdm_clk: This clock is used as the clock for the SDM module, with a maximum frequency of 4 MHz (when the main clock is 22.5792 MHz, the maximum supported is 3.5 MHz).
• h clk: This clock is used for DMA and usb_iso.
• pclk: This clock is used for configuring registers.

10.3 I2S

10.3.1 Introduction

I2S features include:

• Supports master and slave mode
• I2S supports TDM mode, TDM mode supports 2/4/6/8 channel, the slot of TDM mode supports 16/24/

32 BCLK wide

• Supports 16 bits / 20 bits / 24 bits / 32 bits data width
• Supports sampling rate of less than or equal to 192 kHz
• TDM supports sampli ng rate of less than or equal to 48 kHz (8 channels on simultaneously)
• Supports 2-line mode, two data lines in or out at the same time PLL audio_system (24MHz) codec_clk (12MHz) sdm_clk i2s_clk divider divider-2 divider divider PLL PLL step: {0x8014082d, 0x8014082c} mod: {0x80140837, 0x80140836} step: {0x80140807, 0x80140806} mod: {0x8014082b, 0x8014082a} step: {0x80140809, 0x80140808} mod: {0x8014080b, 0x8014080a}

Datasheet for Telink TL3828 DS-TL3828-E5 196 Ver 0.8.0

10.3.2 I2S Protocol

The I2S protocols include: I2S format, Left Justified (LJ) format, Right Justified (RJ) format, DSP format (mode A and mode B), and TDM mode. The frame clock and MSB position of each format are listed as below. Table 10-1 Frame Clock and MSB Position Since the function and register offset address of I2S are the same except TDM, here describes the function configuration of I2S.

• The supported I2S, LJ, RJ and DSP format i s set by configuring register i2s_format (I2S_TDM_BASE+0x01[6:5]);
• The data bit width of 16 bits, 20 bits, 24 bits, 32 bits is selected by configuring register i2s_wl (I2S_TDM_BASE+0x01[4:3]);
• The register i2s_lrp (I2S_TDM_BASE+0x02[6]) is used to switch mode A and mode B in DSP format, and to reverse LRCLK in other format;
• The register i2s_lrswap (I2S_TDM_BASE+0x02[0]) is used to reverse the data of left and ri ght channels;
• The I2S module supports slave and master mode, by configuring register i2s_adc_dci_ms and i2s_dac_dci_ms (I2S_TDM_BASE+0x00[6:5]) these two bits to control the ADC/DAC master or slave mode;
• The I2S supports four/five wire mode, four wire refers to the ADC and DAC channel share a SLRCLK, configure i2s_mode (I2S_TDM_BASE+0x03[1:0]) to 2'b01 to set ADC and DAC paths to share the SLRCLK of DAC, confi gure i2s_mode (I2S_TDM_BASE+0x03[1:0]) for 2'b10 to set ADC and DAC paths to share the SLRCLK of ADC.
• The I2S supports dual-line mode which shares bclk and lrc. Configure i2s_rx_2line_enable (I2S_TDM_BASE+0x02[1]) to enable rx_2line, configure i2s_tx_2line_enable (I2S_TDM_BASE+0x02[2]) to enable tx_2line, however, rx_2line and tx_2line should not be enabled at the same ti me. Format Frame Clock Mode MSB Position from Start of Frame Clock I2S 50% duty cycle One bit clock delay Left Justified 50% duty cycle No delay Right Justified 50% duty cycle 16bit mode (Delay by 16bit clocks) 20bit mode (Delay by 12bit clocks) 24bit mode (Delay by 8bit clocks) Note: config 32bit bclks for fclk DSP mode A Single bit clock wide pulse No delay DSP mode B Single bit clock wide pulse One bit clock delay TDM mode 1 Single bit clock wide pulse No delay TDM mode 2 Single bit clock wide pulse One bit clock delay TDM mode 3 50% duty cycle No delay

Datasheet for Telink TL3828 DS-TL3828-E5 197 Ver 0.8.0

10.3.2.1 I2S mode

The timing sequence of I2S mode is shown as below. Figure 10-3 Timing Diagram of I2S Mode

10.3.2.2 Left Justified mode

The timing sequence of LJ mode is shown as below. Figure 10-4 Timing Diagram of LJ Mode

10.3.2.3 Right Justified mode

The timing sequence of RJ mode is shown as below. 23 22 98 54 1 0 54 1 0 1015 14 19 18 MSB 24Bit Mode 20Bit Mode 16Bit Mode LSB 23 22 9 8 54 1 0 54 10 1015 14 19 18 MSB 24Bit Mode 20Bit Mode 16Bit Mode LSB MSCLK SLRCLK Left Channel Right Channel

32 Clocks32 Clocks

2-Channel I2S (PHILIPS Format) Stereo Input 23 22 98 54 10 MSB

24 Bit Mode

20 Bit Mode

16 Bit Mode

2-Channel Left Justified Stereo Input 18 54 10 1014 23 22 98 54 10 MSB

Datasheet for Telink TL3828 DS-TL3828-E5 198 Ver 0.8.0 Figure 10-5 Timing Diagram of RJ Mode

10.3.2.4 DSP mode A

The timing sequence of DSP mode A is shown as below. Figure 10-6 Timing Diagram of DSP Mode A

10.3.2.5 DSP mode B

The timing sequence of DSP mode B is shown as below. 23 22 98 54 10 MSB 2-Channel Right Justified (Sony Format) Stereo Input 18 54 10 1014 MSCLK 23 22 98 54 10 MSB Left Channel Right Channel

64 Clocks

2-Channel Left Justified Stereo Input 23 22 98 54 10 MSB LSB

Datasheet for Telink TL3828 DS-TL3828-E5 199 Ver 0.8.0 Figure 10-7 Timing Diagram of DSP Mode B

10.3.2.6 TDM mode A

The timing sequence of TDM mode A is shown as below. Figure 10-8 Timing Diagram of TDM Mode A

10.3.2.7 TDM mode B

The timing sequence of TDM mode B is shown as below. 23 22 98 54 10 MSB Left Channel Right Channel 2-Channel Left Justified Stereo Input 23 22 98 54 10 MSB LSB

Datasheet for Telink TL3828 DS-TL3828-E5 200 Ver 0.8.0 Figure 10-9 Timing Diagram of TDM Mode B

10.3.2.8 TDM mode C

The timing sequence of TDM mode C is shown as below. Figure 10-10 Timing Diagram of TDM Mode C

10.3.3 I2S Clock

The clock tree is shown in the figure below, in which clk_i2s is divided from pll (Phase Locked Loop).

Datasheet for Telink TL3828 DS-TL3828-E5 201 Ver 0.8.0 Figure 10-11 Clock Tree of I2S Module

• The i2s_clk_en (I2S_TDM_BASE+0x00[2]) is the I2S clock switch;
• We can choose whether to divide frequency for clk_i2s by configuring i2s_clk_div2 (I2S_TDM_BASE+0x00[3]);
• clk_i2s is derived by dividing the PLL clock using i2s_step {SC_BASE (0x80140800) + 0x08~0x09} and i2s_mod {SC_BASE (0x80140800) + 0x0a~0x0b}. The division formula is: clk_i2s = PLL / (i2s_mod / i2s_step). Note: i 2s_mod must be greater than 2 times i2s_step.
• When I2S module works as master, we can configure i2s_pcm_clk_num (I2S_TDM_BASE+0x08) to divide the frequency of clk_i2s to get bclk, which currently only supports even divisions (0, 2, 4...);
• By configuring i2s_int_pcm_num (I2S_TDM_BASE+0x04~0x05) and i2s_dec_pcm_num (I2S_TDM_BASE+0x06~0x07), we can get the dac_lrclk and adc_lrclk which are di vided down by the adc_bclk_out adc_dci_ms 0adc_bclk_in bclkinv pcm_clkpcm_num divide Divide_2 mclk_div2outclk_i2s0 dec_pcm_num divide adc_lrclk_out adc_dci_ms frm_inv adc_lrclk_in dac_bclk_out dac_dci_ms 0dac_bclk_in bclkinv int_pcm_num divide dac_lrclk_out dac_dci_ms frm_inv dac_lrclk_in mclk_real

Datasheet for Telink TL3828 DS-TL3828-E5 202 Ver 0.8.0 bclk. For example, if bclk is 12MHz, dac_lrclk and adc_lrclk are both 48KHz, then configure i2s_int_pcm_num and i2s_dec_pcm_num to 249, that is, 48K = 12M/(249+1).

10.3.4 I2S TDM Mode

Configuring I2S to TDM mode requires i2s_format (I2S_TDM_BASE+0x01[7:5]) to be configured to 3'b100. The specific choice of which TDM format needs to be configured i2s_tdm_mode (I2S_TDM_BASE+0x11[5:4]); the tx and rx channels of TDM can be configured separately, the relevant registers are i2s_tdm_rx_ch_num (I2S_TDM_BASE+0x11[1:0]) and i2s_tdm_tx_ch_num (I2S_TDM_BASE+0x11[3:2]); the slot width of each channel can be selected by register i2s_tdm_slot (I2S_TDM_BASE+0x11[7:6]), and 16/24/32 bclk width is optional.

10.3.5 Register Description of I2S

The I2S_TDM related registers are listed as following, the base address of the following registers is 801410f0. Table 10-2 I2S_TDM Related Registers Address offset Name Type Description Default value 0x00 I2S_CFG1 RW [1:0]: i2s_bcm_bits [2]: i2s_clk_en, i2s2 clk enable: 1'b1: enable 1'b0: disable [3]: i2s_clk_div2, i2s clk divide2 enable: 1'b1: enable 1'b0: disable [4]: i2s_bclkinv, bclk invert [5]: i2s_adc_dci_ms, i2s2 adc as master [6]: i2s_dac_dci_ms, i2s2 dac as master [7]: i2s_adc_frm_loop, adc frm loop from pad 0x00

Datasheet for Telink TL3828 DS-TL3828-E5 203 Ver 0.8.0 0x01 I2S_CFG2 RW [0]: i2s_adc_mbclk_loop 1'b0: i2s_adc_bclk 1'b1: i2s_adc_bclk loop GPIO [1]: i2s_dac_mbclk_loop 1'b0: i2s_dac_bclk 1'b1: i2s_dac_bclk loop GPIO [2]: i2s_frm_inv, 0: frm 1:frm inv [4:3]: i2s_wl, i2s word length: 2'b00: 16 2'b01: 20 2'b10: 24 2’b11: 32 [7:5]: i2s_format, i2s format: 3'b000: RJ 3'b001: LJ 3'b010: I2S 3'b011: DSP 3'b100: TDM 0x00 Address offset Name Type Description Default value

Datasheet for Telink TL3828 DS-TL3828-E5 204 Ver 0.8.0 0x02 I2S_CFG3 RW [0]: i2s_lrswap i2s l channel and r channel data swap. [1]: i2s_rx_2line_enable 0: i2s 2line rx disbale; 1: i2s 2line rx enable [2]: i2s_tx_2line_enable 0: i2s 2line tx disable; 1: i2s 2line tx enable [3]: i2s_dac_frm_enable 0: i2s dac frm disable 1: i2s dac frm enable [4]: i2s_adc_frm_enable 0: i2s adc frm disable 1: i2s adc frm enable [5]: i2_tx_dat_sel 0: sel i2s tx data low bits 1: sel i2s tx dat high bits [6]: i2s_lrp DSP mode select when i2s DSP format or LRCLK invert operation: 1'b1: dsp mode A 1'b0: dsp mode B 1'b1: LRCLK invert 1'b0: not invert [7]: i2s_dac_frm_loop, dac frm loop from pad 0x00 Address offset Name Type Description Default value

Datasheet for Telink TL3828 DS-TL3828-E5 205 Ver 0.8.0 0x03 I2S_ROUTE RW [1:0]: i2s_mode 2'b00: i2s 5line mode 2'b01: i2s 4line dac mode 2'b10: i2s 4line adc mode [2]: i2s_pad_bclk_sel 0:adc bclk; 1: dac bclk [3]: i2s_rec_bit_sel 0: low byte; 1: high byte [4]: i2s_schedule_en, schedule enable [5]: i2s_ascl_bypass 0: enable ascl 1:ascl bypass [6]: i2s_pem_trig_en 1: trig i2s via pem [7]: i2s_pem_dis_en 1: disable i2s via pem 0x00 0x04 I2S_INT_PCM_NU RW [7:0]: i2s_int_pcm_num0 dac i2s LRCLK counter low byte. Even div 0x00 0x05 I2S_INT_PCM_NU RW [4:0]: i2s_int_pcm_num1 dac i2s LRCLK counter high byte. 0x00 0x06 I2S_DEC_PCM_N UM0 RW [7:0]: i2s_dec_pcm_num0 adc i2s LRCLK counter low byte. Even div 0x00 0x07 I2S_DEC_PCM_N UM1 RW [4:0]: i2s_dec_pcm_num1 dac i2s LRCLK counter high byte. 0x00 0x08 I2S_PCM_CLK_N UM RW [7:0]: i2s_pcm_clk_num bclk division factor, num*2 div 0x00 0x09 I2S_DACTUNE RW [3:0]: i2s_dactune_l1 [7:4]: i2s_dactune_l2 0x00 0x0a I2S_ADCTUNE RW [3:0]: i2s_adctune_l1 [7:4]: i2s_adctune_l2 0x00 Address offset Name Type Description Default value

Datasheet for Telink TL3828 DS-TL3828-E5 206 Ver 0.8.0 0x0b I2S_FIFO_CONFI G RW [0]: txfifo_less_l1 [1]: txfifo_less_l2 [2]: txfifo_more_l1 [3]: txfifo_more_l2 [4]: rxfifo_less_l1 [5]: rxfifo_less_l2 [6]: rxfifo_more_l1 [7]: rxfifo_more_l2 0x00 0x0c I2S_STIMER_TAR GET0 RW [7:0]: i2s_stimer_target[7:0] i2s stimer for schedule 0x00 0x0d I2S_STIMER_TAR GET1 RW [7:0]: i2s_stimer_target[15:8] i2s stimer for schedule 0x00 0x0e I2S_STIMER_TAR GET2 RW [7:0]: i2s_stimer_target[23:16] i2s stimer for schedule 0x00 0x0f I2S_STIMER_TAR GET3 RW [7:0]: i2s_stimer_target[31:24] i2s stimer for schedule 0x00 0x10 I2S_ALIGN_CFG RW [6]: rx_dsp_start_sel fix pad2reg timing in i2s_slv mode 0x00 0x11 I2S_TDM_CFG RW [1:0]: i2s_tdm_rx_ch_num configure the number of i2s tdm rx channel 2'b00 2channel, 2'b01 4channel,2'b10 6channel,2'b11 8channel [3:2]: i2s_tdm_tx_ch_num configure the number of i2s tdm tx channel 2'b00 2channel, 2'b01 4channel,2'b10 6channel,2'b11 8channel [5:4]: i2s_tdm_mode i2s TDM mode: 2'b00: TDM_mode_a 2'b01: TDM_mode_b 2'b10: TDM_mode_c [7:6]: i2s_tdm_slot 2'b00: 16 BCLK wide 2'b01: 24 BCLK wide 2'b10: 32 BCLK wide 0x00 Address offset Name Type Description Default value

Datasheet for Telink TL3828 DS-TL3828-E5 207 Ver 0.8.0

10.4 SDM (Sigma-Delta Modulation)

The SDM takes 16-bit audio data from SRAM and provides 1-bit modulated output. Only a simple passive filter network is needed to drive audio device directly. Dither control can be added to the SDM to avoid spurs in output data. There are three dithering options: PN sequence, PN sequence with Shapping, and DC constant; only one type of input is allowed any time. The following i s the block diagram of SDM. Figure 10-12 Audio SDM

10.4.1 Left Channel

For left channel, (1) If selecting DC input for SDM, configure const_sel_l (ASCL0_SDM_BASE+0x0b[5]) to be 1, const_l (ASCL0_SDM_BASE+0xc~0xd) to configure constant value of input. (2) If select PN generator for SDM, configuring const_sel_l to 0 means use PN generator, shap_l (ASCL0_SDM_BASE+0x03[5]) is the enable of dither shapping module. There are two PN generators to generate random number sequence, pn_sel_l (ASCL0_SDM_BASE+0x 08[6:5]) is the enable for two PN generators.

• When the PN sequence is selected as input, const_sel_l and shap_l are configured as 0 and pn_sel_l is configured as 1.
• When PN sequence with Shapping is selected as input, const_sel_l is configured as 0 and shap_l and pn_sel_l are configured as 1. When PN sequence or PN sequence with Shapping is selected, pn1_bi ts_l (ASCL0_SDM_BASE+0x08[4:0]) and pn2_bits_l (ASCL0_SDM_BASE+0x09[4:0]) determines the number of bits to be used in the PN1/PN2 generator (range 0-16).

10.4.2 Right Channel

For right channel, (1) If selecting DC input for SDM, configure const_sel_r (ASCL0_SDM_BASE+0x0b[6]) as 1, const_r (ASCL0_SDM_BASE+0xe~0xf) configure input constant value; (2) If selecting PN generator for SDM, configuring const_sel_r to 0 i ndicates that PN generator is used, shap_r (ASCL0_SDM_BASE+0x03[6]) is the enable of dither shapping module, there are two PN generators to generate random number sequence, pn_sel_r (ASCL0_SDM_BASE+0x09[6:5]) is the enable for two PN generators.

Datasheet for Telink TL3828 DS-TL3828-E5 208 Ver 0.8.0

• When PN sequence is selected as input, const_sel_r and shap_r are configured as 0 and pn_sel_r is configured as 1.
• When PN sequence with Shapping is selected as input, const_sel_r is configured as 0 and shap_r and pn_sel_r are configured as 1. When PN sequence or PN sequence with Shapping is selected, pn1_bits_r (ASCL0_SDM_BASE+0x0a[4:0]) and pn2_bits_r (ASCL0_SDM_BASE+0x0b[4:0]) determi ne the number of bits to be used in the PN1/PN2 generator (range 0-16).

10.5 ASCL

The ASCL (Asynchronous Sample rate Conversion with Linear interpolation) module performs sample rate conversion. It supports processing 16-bit data only. The input data is obtained from SRAM via DMA or MCU, and the output data is output to SDM/I2S at a specific sample rate. For example, if the sample rate of input ASCL i s SmpIn and the sample rate of output ASCL is SmpOut, ASCL can be configured according to the following formula: Linear interpolation or delay interpolation is used as shown below: Figure 10-13 Linear interpolation Figure 10-14 Delay interpolation The Audio_arch has 2 ASCLs, ASCL0, and ASCL1. The following is an example of ASCL0 to illustrate the function configuration of ASCL. The mono (ASCL0_SDM_BASE+0x00[0]) is set to 1 to select the mono output, the hpf (ASCL0_SDM_BASE+0x 00[7]) is HPF enable. The VOL_CTRL (ASCL0_SDM_BASE+0x02[6:0]) adjusts the volume. The line (ASCL0_SDM_BASE+0x03[2]) selects Linear interpolation or Delay interpolation. The step_i is configured through registers ASCL0_SDM_BASE+05[4:0]~07. SmpIn

Datasheet for Telink TL3828 DS-TL3828-E5 209 Ver 0.8.0

10.5.1 Register Description of ASCL

The ASCL0 SDM related registers are listed in the table below. The base address for the following registers is 0x80141110. Table 10-3 ASCL0 SDM Related Registers Address Offset Name Type Description Reset Value 0x00 AUD_EN RW [0]: mono, mono enable [2]: sdmpen, sdm enable [3]: isopen, ISO enable [4]: pem_trig_en, [5]: pem_dis_en, [6]: sdmgrp, enable grp [7]: hpf, enable HPF 0x0 0x01 GRPMID RW [7:0]: gprmid, middle of GRP 0x00 0x02 AUD_VOL RW [6:0]: vol, audio sound volumn.[0]:add a quarter;[1]add a half;[6:2]:shift left [7]: mute, mute enable 0x03 AUD_CTRL RW [0]: nox2, 1'b1:not multiply 2 when PWM;1'b0:multiply 2 [1]: pwm, PWM enable [2]: line, line enable [3]: ysel_l, 1'b1:4 bit output; 1'b0:1 bit output [4]: ysel_r, 1'b1:4 bit output; 1'b0:1 bit output [5]: shap_l, left shapping enable [6]: shap_r, right shapping enable 0x04 TUNE RW [7:0]: tune, tune step for rate mathing block,to adjust step value when fifo almost full or empty 0x00 0x05 STEP_L RW [0]: sdm_afifo_clr, sdm afifo clr (W1C) [1]: sdm_afifo_overrun, sdm afifo overrun (R) [2]: sdmfifo_empty, sdm fifo empty (R) [3]: sdm_data_sync_sel, 1: sdm_data from afifo [7:4]: step_l, step[3:0] 0x4 0x06 STEP_M RW step[11:4] 0x0 0x07 STEP_H RW step[19:12] 0x00

Datasheet for Telink TL3828 DS-TL3828-E5 210 Ver 0.8.0 The ASCL1 related registers are listed in the table below. The base address for the following registers is 0x80141128. Table 10-4 ASCL1 Related Registers 0x08 AUD_PN1L RW [4:0]: pn1_bits_l, bits used in pn1 of left channel,range from 0 to 16. [6:5]: pn_sel_l, [5]:pn2 of left enable; [6]:pn1 of left enable. 0x0 0x09 AUD_PN2 RW [4:0]: pn2_bits_l, bits used in pn2 of left channel,range from 0 to 16. [6:5]: pn_sel_r, [5]:pn2 of right enable; [6]:pn1 of right enable. 0x0 0x0a AUD_PN1R RW [4:0]: pn1_bits_r, bits used in pn1 of right channel,range from 0 to 16. [5]: channel_chg, 1'b1:exchange data in between SDMs. [7:6]: ascl0_format_sel, 0: sel [15:0]; 1: sel [19:4]; 2: sel 0x0 0x0b CONST_SEL RW [4:0]: pn2_bits_r, bits used in pn2 of right channel,range from 0 to 16. [5]: const_sel_l, 1'b1:left channel use const value [6]: const_sel_r, 1'b1:right channel use const value 0x00 0x0c CONST_LL RW const_l[7:0] 0x00 0x0d CONST_LH RW const_l[15:8] 0x00 0x0e CONST_RL RW const_r[7:0] 0x00 0x0f CONST_RH RW const_r[15:8] 0x00 Address Offset Name Type Description Reset Value 0x00 ASCL_CONFIG RW [0]: mono, mono enable [1]: ascl_format_sel, 0: sel [15:0] from [31:0]; 1: sel [31:16] from [31:0] [7]: hpf, enable HPF 0x0 0x02 AUD_VOL RW [6:0]: vol, audio sound volumn.[0]:add a quarter;[1]add a half;[6:2]:shift left [7]: mute, mute enable Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 211 Ver 0.8.0

10.6 CODEC

The CODEC features include:

• Supports 1-channel ADC
• Supports 2-mono or 1-stereo DMIC
• Supports sampling rate of 8k, 11.0259k, 12k, 16k, 22.0588k, 24k, 32k, 44.118k, and 48k.
• MCLK=24MHz

10.6.1 CODEC Input Path

The CODEC input path is illustrated in figure below. Figure 10-15 CODEC Input Path The CODEC input consists of one group of stream (dec), and includes two data paths. The stream is utilized for a single-channel AMIC input. To enable the AMIC i nput, the dec_en_ch (AUDIO_DFIFO_BASE+0x11[7:6]) should be set to 1 to enable the MIC interface module switch, and the mic_sel (AUDIO_DFIFO_BASE+0x12[7]) should be configured as 0 to select the input source as AMIC. The CODEC supports dual-channel DMIC inputs. To use DMIC, simply set mic_sel to 1. The PGAVOL_IN is controlled via Ana_0x8d[6:4] with a range of 0 ~ 45.2db. 0x03 LINE RW [2]: line, line enable 0x1 x04 TUNE RW [7:0]: tune, tune step for rate mathing block,to adjust step value when fifo almost full or empty 0x00 0x05 STEP_L RW [7:4]: step_l, step[3:0] 0x00 0x06 STEP_M RW step[11:4] 0x0 0x07 STEP_H RW step[19:12] 0x00 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 212 Ver 0.8.0 Table 10-5 PGA Gain for Different Configurations

10.6.2 Decimation Data Path

The following figure shows the data path of the CODEC decimation of this chip. The sampling filter consists of a Cascaded Integrator-Comb (CIC) filter, two half-band filters, a compensation filter, and a High Pass Filter (HPF). The HPF serves the purpose of filtering out any DC bias generated by the input source. The switch is hpf_en(AUDIO_CODEC_BASE+0x00[0]). There are two formats for deci mation output, one is 20-bit, the other is 16-bit, Set dec_ain0_mode(AUDIO_DFIFO_BASE+0x3b[0]) or dec_ain1_mode(AUDIO_DFIFO_BASE+0x3b[2]) to 0 to make output as 16-bit format. Code (4 bits) PGA Gain (dB) 0000 45.2 0001 43.5 0010 42.1 0011 40.5 0100 39.1 0101 37.4 0110 36.0 0111 34.6 1000 33.0 1001 30.1 1010 27.0 1011 24.0 1100 21.0 1101 15.0 1110 9.0 1111 0

Datasheet for Telink TL3828 DS-TL3828-E5 213 Ver 0.8.0 Figure 10-16 Audio CODEC Decimation The DIG_GAIN is a gain range of -48dB ~ +42dB, 6dB/step while controlling the digital gain of the left and right channels. The digital gain of the left and right channels of the dec is controlled by configuring dec_vol (AUDIO_DFIFO_BASE+0x12[5:0]). Table 10-6 Digital Gain for Different Configurations Gain Coded -48dB 0x00 -42dB 0x04 -36dB 0x08 -30dB 0x0c -24dB 0x10 -18dB 0x14 -16dB 0x15 -12dB 0x18 -6dB 0x1c 0dB 0x20 +6dB 0x24 +12dB 0x28 +18dB 0x2c +24dB 0x30 +30dB 0x34 +36dB 0x38 +42dB 0x3c

Datasheet for Telink TL3828 DS-TL3828-E5 214 Ver 0.8.0

10.6.3 ALC

The Automatic Level control (ALC) path is shown below and consists of a down-sampling filter, ALC & Noise Gate (NG), and adjustable gain. Figure 10-17 Audio ALC Path The structure of Average filter is shown below and is used to detect the envelope value of the input data. The parameter α=2^(-K1), K1 (AUDIO_CODEC_BASE+0x05[7:4]) can be adjusted to regulate the speed of detecting the following envelope. F igure 10-18 Structure of Average Filter The ALC_SEL (AUDIO_CODEC_BASE+0x21[6:5]) switch is used to enable ALC for both the left and right paths. The ALC module compares the detected envelope value with the configured reference threshold ALCL (AUDIO_CODEC_BASE+0x20[3:0]). If the envelope value exceeds the reference threshold, the gain is reduced, and vice versa. To adjust the gain increase/decrease rate, the ATK (AUDIO_CODEC_BASE+0x22[3:0]) and DCY (AUDIO_CODEC_BASE+0x 22[7:4]) parameters can be modified. These parameters control the rate at which the gain increases or decreases. Configure ALC_HLD (AUDIO_CODEC_BASE+0x21[3:0]) when the gain needs to be reduced to make the gain have a hysteresis time in reducing. For dynamic adjustable gain, if it exceeds the MAXGAIN (AUDIO_CODEC_BASE+0x20[7:4]) value, it will be capped at the maximu m gai n. Similarly, if the gain falls below MINGAIN (AUDIO_CODEC_BASE+0x24[2:0]), it will be capped at the minimum gain. Noise gating is used to prevent noise from entering during recording when there is no useful signal. The NGAT (AUDIO_CODEC_BASE+0x23[0]) switch controls the noise gating functionality, while the NGTH (AUDIO_CODEC_BASE+0x23[7:3]) parameter sets the noise threshold. When the detected i nput si gnal amplitude falls below the set threshold, it is considered noise. Configuring NGG (AUDIO_CODEC_BASE+0x23[2:1]) as 2'b01 activates signal soft mute in this case.

Datasheet for Telink TL3828 DS-TL3828-E5 215 Ver 0.8.0 Figure 10-19 Signals before and after ALC

10.6.3.1 Sample Rate of CODEC Input

The master clock mclk of CODEC is divided from pll, the mclk frequency is 24 MHz (22.5792MHz, 24.576MHz, 33.8688MHz, 36.864MHz in some special cases). Configure codec clk div2 (AUDIO_CODEC_BASE+0x0a[6]) to 1 to make codec master clock 12 MHz (11.2896MHz, 12.288MHz, 16.9344MHz, 18.432MHz in some special cases). The input path of CODEC supports sampling rate of 8 kHz ~ 48 kH z, obtai ned by configuring dec_clk_sr (AUDIO_CODEC_BASE+0x0a[5:1]). The Dmic_clk is generated as dec_clk/2. The clock named amic_6M is the same as dmic_clk. The clock named amic_1M can be configured through r_ck_sel (AUDIO_CODEC_BASE + 0x00[1]), r_sel_2m (AUDIO_CODEC_BASE + 0x00[1]), and adc_clk_div (AUDIO_CODEC_BASE + 0x05[1:0]):

• If r_ck_sel is set to 1, the clock is the same as dmic_clk (dec_clk / 2).
• If r_sel_2m i s set to 1, the output is dec_clk / 6.
• Otherwise, the clock is determined by adc_clk_div, with the formula: amic_1M = dec_clk / 2 / (adc_clk_div × 2). DMIC sampling rates are configured according to Table 10-7 and Table 3. AMIC sampling rates are configurable based on four tables, depending on the analog front-end clock requirements. Table 10-7 Sample Rate of CODEC Input - Part 1 MCLK Mclk_real CODEC input sample rate Coded dec_clk dec_clk/2 dec_clk/12 USB MODE: (AUDIO_CODEC_BASE + 0x0a[0]) is set to 1 NOTE:
• Save the right channel data at DMIC rising edge, save the left channel data at DMIC falling edge.

Datasheet for Telink TL3828 DS-TL3828-E5 216 Ver 0.8.0 Table 10-8 Sample Rate of CODEC Input - Part 2 Table 10-9 Sample Rate of CODEC Input - Part 3 24.000MHz 12.000MHz 8KHz (Mclk_real/(2*6*125)) 00110, 00100 mclk/12 1MHz 0.167MHz 11.025KHz (Mclk_real/(2*4*136)) 11001 mclk/8 1.5MHz 0.25MHz 12KHz (Mclk_real/(2*4*125)) 01000 mclk/8 1.5MHz 0.25MHz 16KHz (Mclk_real/(2*3*125)) 01010 mclk/6 2MHz 0.333MHz 22.05KHz (Mclk_real/(2*2*136)) 11011 mclk/4 3MHz 0.5MHz 24KHz (Mclk_real/(2*2*125)) 11100 mclk/4 3MHz 0.5MHz 32KHz (Mclk_real/(2*1.5*125)) 01101 mclk/6 2MHz - 44.1KHz (Mclk_real/((2*1*136)) 11111 mclk/4 3MHz - 48KHz (Mclk_real/(2*1*125)) 11110 mclk/4 3MHz - MCLK Mclk_real CODEC input sample rate Coded dec_clk dec_clk/2 dec_clk/12 USB MODE: (AUDIO_CODEC_BASE + 0x0a[0]) is set to 1 24.000MHz 12.000MHz 32KHz (Mclk_real/(2*1.5*125)) 01100 mclk/3 4MHz 0.667MHz 44.1KHz (Mclk_real/(2*1*136)) 10011 10001 mclk/2 6MHz 1MHz 48KHz (Mclk_real/(2*1*125)) 00000 00010 mclk/2 6MHz 1MHz MCLK Mclk_real CODEC input sample rate Coded dec_clk dec_clk/2 dec_clk/12 USB MODE: (AUDIO_CODEC_BASE + 0x0a[0]) is set to 0 24.000MHz 12.000MHz 32KHz (Mclk_real/(2*1.5*125)) 01101 mclk/6 2MHz - 44.1KHz (Mclk_real/((2*1*136)) 11111 mclk/4 3MHz - 48KHz (Mclk_real/(2*1*125)) 11110 mclk/4 3MHz - MCLK Mclk_real CODEC input sample rate Coded dec_clk dec_clk/2 dec_clk/12

Datasheet for Telink TL3828 DS-TL3828-E5 217 Ver 0.8.0 Table 10-10 Sample Rate of CODEC Input - Part 4

10.6.4 Register Description of CODEC

The CODEC related registers are listed in the table below. The base address for the following registers is 0x80141080. 24.576MHz 12.288MHz 8KHz (Mclk_real/(2*6*128)) 00110, 00100 mclk/12 1.024MHz 0.171MHz 12KHz (Mclk_real/(2*4*128)) 01000 mclk/8 1.536MHz 0.256MHz 16KHz (Mclk_real/(2*3*128)) 01010 mclk/6 2.048MHz 0.341MHz 24KHz (Mclk_real/(2*2*128)) 11100 mclk/4 3.072MHz 0.512MHz 22.5792MHz 11.2896MHz 11.025KHz (Mclk_real/(2*4*128)) 11000 mclk/8 1.4112MHz 0.2352MHz 22.05KHz (Mclk_real/(2*2*128)) 11010 mclk/4 2.8224MHz 0.4704MHz 36.864MHz 18.432MHz 8KHz (Mclk_real/(2*9*128)) 00111, 00101 mclk/12 1.536MHz 0.256MHz 12KHz (Mclk_real/(2*6*128)) 01001 mclk/8 2.304MHz 0.384MHz 16KHz (Mclk_real/(2*4.5*128)) 01011 mclk/6 3.072MHz 0.512MHz 24KHz (Mclk_real/(2*3*128)) 11101 mclk/4 4.608MHz 0.768MHz 33.8688MHz 16.9344MHz 11.025KHz (Mclk_real/(2*6*128)) 11001 mclk/8 2.1168MHz 0.3528MHz 22.05KHz (Mclk_real/(2*3*128)) 11011 mclk/4 4.2336MHz 0.7056MHz MCLK Mclk_real CODEC input sample rate Coded dec_clk dec_clk/2 dec_clk/12 USB MODE: (AUDIO_CODEC_BASE + 0x0a[0]) is set to 0 24.576MHz 12.288MHz 48KHz (Mclk_real/(2*1*128)) 00000 00010 mclk/2 6.144MHz 1.024MHz 22.5792MHz 11.2896MHz 44.1KHz (Mclk_real/(2*1*128)) 10010 10000 mclk/2 5.6448MHz 0.9408MHz 36.864MHz 18.432MHz 48KHz (Mclk_real/(2*1.5*128)) 00001 00011 mclk/2 9.216MHz 1.536MHz MCLK Mclk_real CODEC input sample rate Coded dec_clk dec_clk/2 dec_clk/12

Datasheet for Telink TL3828 DS-TL3828-E5 218 Ver 0.8.0 Table 10-11 CODEC Related Registers Address Offset Name Type Description Reset Value 0X00 CODEC_CFG1 RW [0]: hpf_en, high-pass filter enable [1]: r_ck_sel, 1'b1: dmic clk;1'b0:1M; [3]: sram_ce_manual, sram enable, 1'b1: sram always active [4]: dati_soft_mute, mic input softmute enable [5]: dato_soft_mute, alc output data softmute enable [6]: r_sel_2m, 1'b1: 2M, 1'b0: 1M 0X05 CODEC_K1 RW [1:0]: adc_clk_div, 6M/(adc_clk_div*2) [7:4]: k1, coef for ALC 0x53 0x0a CODEC_CLKC FG RW [0]: clk_usb, 1'b1:clk usb mode. [5:1]: clk_sr, sample rate. 5'b00110: 8k; 5'b11001: 11.0259; 5'b01000: 12k; 5'b01010: 16k; 5'b11011: 22.0588; 5'b11100: 24k; 5'b01100: 32k; 5'b01101: 32k@2Mhz; 5'b10001: 44.118; 5'b00000: 48k; 5'b11110: 48k@3MHz; 5'b11111: 44.118k@3MHz. [6]: clk_div2, clk div2 enable [7]: clk_en, clk enable 0x00 0x0b CODEC_RST RW [0]: en_dec, codec rst disable [6:4]: r_sft_zc, 0x00 0x20 CODEC_ALC RW [3:0]: alcl, decide the ref: 1.5db/step. [6:4]: maxgain, maxgain for ALC:6db/step 0x21 CODEC_ALCS EL RW [3:0]: hld, hold time: x2 step. [6:5]: alcsel, alc select. 2'b00: no alc; 2'b01: right only; 2'b10: left only; 2'b11: stereo 0x00 0x22 CODEC_ATK RW [3:0]: atk, Change the rate of gain increase,X2 step. [7:4]: dcy, Change the gain reduction rate,X2 step. 4'b0000: 24ms...4'b1111: 24.576s 0x32

Datasheet for Telink TL3828 DS-TL3828-E5 219 Ver 0.8.0 0x23 CODEC_NOISE RW [0]: ngat, Noise gate enable [2:1]: ngg, Noise gate type. 2'b00: hold PGA gain constant; 2'b01: mute output; 2'b10: softmute/unmute output; 2'b11: reserve [7:3]: ngth, Noise gate threshold value, 1.5db step; 0x00 0x24 CODEC_MING AIN RW [2:0]: mingain, mingain, 6db step: 3'b000: -72db...3'b111: -30db [4]: dmic_clk_sel, dmic clk sel. [5]: codec_trig_en, 1: trig codec via pem [6]: codec_dis_en, 1: disable codec via pem [7]: codec_schdl_en, codec schedule enable 0x02 0x25 SOFTMUTE_E N RW [0]: softmute_l, softmute of left channel [1]: softmute_r, softmute of right channel [2]: softmute_mode_sel, 1'b1: config step. 1'b0: step is 1; [4]: bypass_softmute, bypass softmute 0x26 SOFTMUTE_S TEP_SEL RW [7:0]: softmte_step, when softmute sel is 1, softmute's step - 0x27 DMIC_DAT RW [3:0]: dmic_dat_pos, dmic pos data [7:4]: dmic_dat_neg, dmic neg data 0x28 CODEC_STIME R_TARGET0 RW [7:0]: codec_stimer_target[7:0] codec stimer for schedule 0x00 0x29 CODEC_STIME R_TARGET1 RW [7:0]: codec_stimer_target[15:8] codec stimer for schedule 0x00 0x2a CODEC_STIME R_TARGET2 RW [7:0]: codec_stimer_target[23:16] codec stimer for schedule 0x00 0x2b CODEC_STIME R_TARGET3 RW [7:0]: codec_stimer_target[31:24] codec stimer for schedule 0x00 0x2c SOFTMMUT_P GA_GAIN_L_L RW [7:0]: softmmute_pga_gain_l[7:0] softmmute_pga_gain_l low byte 0x00 0x2d SOFTMMUT_P GA_GAIN_L_H RW [2:0]: softmmute_pga_gain_l[10:8] softmmute_pga_gain_l high byte 0x4 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 220 Ver 0.8.0

10.7 Soft Mute

10.7.1 Features

To avoid audible pop noise caused by direct mute operations, a soft mute function is provided. This function allows the signal amplitude to ramp smoothly up from 0 or down to 0, as shown in the timing sequence below. Figure 10-20 Timing Sequence of Soft Mute The chip provides two soft mute paths: one for the CODEC and one for the SDM. The usage method is essentially the same for both. The following example focuses on the CODEC for ex planation. If soft mute is not required, it can be bypassed by setting bypass_softmute (AUDIO_CODEC_BASE + 0x25[4]) to 1.

10.7.2 Soft Mute Usage in ADC

There are two main scenarios where adc_soft_mute is used: 1. Start of Recording Software procedure:

• When softmute_mode_sel (AUDIO_CODEC_BASE + 0x25[2]) is set to 0, the soft mute duration is fixed at 1024 / fs (for SDM, t = 32768 / fs) 0x2e SOFTMMUT_P GA_GAIN_R_L RW [7:0]: softmmute_pga_gain_r[7:0] softmmute_pga_gain_r low byte 0x00 0x2f SOFTMMUT_P GA_GAIN_R_H RW [2:0]: softmmute_pga_gain_r[10:8] softmmute_pga_gain_r high byte 0x4 Address Offset Name Type Description Reset Value adc_soft_mute adc_soft_mute_in_progress adc_data Leave soft_mute enter soft_mute leave_mute_success_irq enter_mute_success_irq

Datasheet for Telink TL3828 DS-TL3828-E5 221 Ver 0.8.0

• If softmute_mode_sel is set to 1, the soft mute duration can be controlled via mute_step_sel (AUDIO_CODEC_BASE + 0x26): t = 1024 / step / fs (for SDM: t = 32768 / step / fs), at 48 kHz, the default soft mute time is approximately 21.2 ms.
• Set adc_soft_mute_l (AUDIO_CODEC_BASE + 0x25[0]) to 1 to initiate soft mute for the left channel.
• Then: codec_en -> delay (until pop disappears) -> adc_soft_mute_l = 0 (to di sable soft mute)
• Configure mute_step_sel to control ramp-up time from mute to normal. Timing uses the same formula as above. 2. End of Recording Software procedure:
• adc_soft_mute = 1
• Wait until adc_soft_mute_in_progress = 0
• Then disable the codec: codec_disable

10.8 Audio FIFO

10.8.1 Introduction

Figure 10-21 Block Diagram of Audio FIFO The above figure shows the general block diagram of Audio First-In-First-Out (FIFO), the input pa th i ncludes I2S, USB, and CODEC. Data is written to the RX_FIFO buffer upon selection through a Multiplexer (MUX). When the source address is either 0x120000 or 0x120040, the DMA controller transfers data from FIFO to a user-specified SRAM location. Conversely, when the destination address is 0x120000 or 0x120040, the DMA controller moves data from SRAM to TXFIFO, then select output path according to the MUX. The output path includes SDM, I2S and USB. Taking 16bit stereo i2s, RXFIFO0 and TXFIFO1 as an example, configure ain0_sel (AUDIO_DFIFO_BASE+0x33[2:0]) to 2'b0, i2s_ain0_mode(AUDIO_DFIFO_BASE+0x36[1:0]) to 2'b10, i2s_aout_sel (AUDIO_DFIFO_BASE+0x42[5:4]) to 2'b10. Input Path Output Path RXFIFO TXFIFO DMA BUFF MUX MUX

Datasheet for Telink TL3828 DS-TL3828-E5 222 Ver 0.8.0

10.8.2 RXFIFO Selection

The following figure shows the input structure of RXFIFO. The RXFIFO input supports a variety of different source multiplexing channels, and the configuration registers can be used to select the channel and data format to meet different requirements. Figure 10-22 RXFIFO Input Select the input source for the RXFIFO0 path by configuring ain0_sel (AUDIO_DFIFO_BASE+0x33[1:0]). Select the input source for the RXFIFO1 path by confi guring ain1_sel (AUDIO_DFIFO_BASE+0x34[1:0]). Table 10-12 Register of ain0_sel, ain1_sel and ain2_sel Register Description ain0_sel Rxfifo0 input source select: 2'b00: i2s. 2'b01: dec. 2'b10: usb. ain1_sel Rxfifo1 input source select: 2'b000: i2s2. 2'b001: dec. 2'b010: usb. RXFIFO0 DMA ain0_sel i2s_rx0 dec_rx0 USB_aiso RXFIFO1 ain1_sel i2s_rx1 dec_rx1

Datasheet for Telink TL3828 DS-TL3828-E5 223 Ver 0.8.0

10.8.3 I2S Data Transfer in RXFIFO

Figure 10-23 I2S Data Transfer in RXFIFO When I2S is used as the input source for RXFIFO 0, the TDM mode has higher priority than the standard I2S mode.

• To select 20/24/32-bit TDM mode, configure i2s_tdm_ain_mode (AUDIO_DFIFO_BASE + 0x47[1]) to 1.
• To select 16-bit TDM mode, configure i2s_tdm_ain_mode (AUDIO_DFIFO_BASE + 0x47[0]) to 1.
• The number of TDM channels is determined by i2s_tdm_rx_ch_num (I2S_TDM_BASE + 0x 11[1:0]). TDM Data Format Behavior:
• In 20/24/32-bit TDM mode, the 20/24/32-bit data is transmitted sequentially by channel: Channel 0, Channel 1, etc.
• In 16-bit TDM mode, every two consecutive 16-bit channel data are combined into a single 32-bit word: º Channels 0, 2, 4, 6 occupy the lower 16 bits º Channels 1, 3, 5, 7 occupy the upper 16 bits If i2s_tdm_ain_mode (AUDIO_DFIFO_BASE + 0x47[1:0]) is co nfi gured to 0, standard I2S mode is used. The data format of I2S is selected by configuring i2s_ain0_mode (AUDIO_DFIFO_BASE+0x3a[1:0]), as shown in the following table. Table 10-13 Data Format of i2s0_ain0_come
• When i2s_ain0_mode selects 16bit mono, at the same time configuring i2s_leftdat_rxfifo_sel (AUDIO_DFIFO_BASE+0x36[0]) to 1’b0, it will input two consecutive strokes of data from the left channel of i2s into RXFIFO0 as 32-bit, and the first stroke is located at the lower 16-bit of 32-bit, and Register Description i2s_ain0_come Rxfifo0 input mode select: 2'b00: 16-bit mono 2'b01: 20/24/32-bit mono 2'b10: 16-bit stereo 2'b11: 20/24/32-bit stereo. {i2s_l_post[15:0], i2s_l_pre[15:0]} I2s_ain0_mode {i2s_r_post[15:0], i2s_r_pre[15:0]} i2s_l[31:0] i2s_rx0i2s_r[31:0]

Datasheet for Telink TL3828 DS-TL3828-E5 224 Ver 0.8.0 the second stroke is the higher 16-bit of 32-bit; configure i2s_rightdat_rxfifo_sel (AUDIO_DFIFO_BASE+0x36[1]) to 1’b0, it will input two consecutive strokes of data from the right channel of i2s into RXFIFO0.

• When i2s_ain0_mode selects 20/24/32-bit mono, at the same time configuring i2s_leftdat_rxfifo_sel with 1'b0 will expand the left channel data symbols into 32-bit input into rxfifo0, similarly if i2s_rightdat_rxfifo_sel is configured wi th 1'b0 will input the i2s right channel data into rxfifo0;
• When i2s_ain0_mode selects 16bit stereo, the 16-bit data of the left and right channels will be spliced into 32-bit and input into FIFO, where the left channel data is the lower 16-bit of 32-bit;
• When i2s_ain0_mode selects 20/24/32-bit stereo, it will input the data into FIFO in two strokes, first transmitting the 32-bit data of the left channel, and then transmi tting the 32-bit data of the right channel. When configuring i2s_rx_2line_enable (I2S_TDM_BASE+0x02[1]), i.e., rx 2line mode is selected, the data splicing of the input FIFO is equivalent to two consecutive data strokes. Taking 20/24/32-bit stereo as an example, it will be divided into four data strokes to be inputted into rxfifo0, which will transmit the first stroke 32-bi t data of the left channel of i2s, the first stroke 32-bit data of the right channel of i2s, then the second stroke 32-bit data of the left channel of i2s, and finally the second stroke 32-bit data of the right channel of i2s. See the following table for other types: Table 10-14 RX 2line Mode Data Type Code Mode Data Type i2s_ain0_mode==2'b00 & i2s_leftdat_rxfifo_sel==1'b0 16-bit mono {i2s_l_post_line0[15:0],i2s_l_pre_line0[15:0]} {i2s_l_post_line1[15:0],i2s_l_pre_line1[15:0]} i2s_ain0_mode==2'b00 & i2s_rightdat_rxfifo_sel==1'b0 16-bit mono {i2s_r_post_line0[15:0],i2s_r_pre_line0[15:0]} {i2s_r_post_line1[15:0],i2s_r_pre_line1[15:0]} i2s_ain0_mode==2'b01 & i2s_leftdat_rxfifo_sel==1'b0 20/24/32-bit mono i2s_l_line0[31:0] i2s_l_line1[31:0] i2s_ain0_mode==2'b01 & i2s_rightdat_rxfifo_sel==1'b0 20/24/32-bit mono i2s_r_line0[31:0] i2s_r_line1[31:0] i2s_ain0_mode==2'b10 16-bit stereo {i2s_r_line0[15:0],i2s_l_line0[15:0]} {i2s_r_line1[15:0],i2s_l_line1[15:0]} i2s_ain0_mode==2'b11 20/24/32-bit stereo i2s_l_line0[31:0] i2s_r_line0[31:0] i2s_l_line1[31:0] i2s_r_line1[31:0]

Datasheet for Telink TL3828 DS-TL3828-E5 225 Ver 0.8.0

10.8.4 CODEC Data Transfer in RXFIFO

Figure 10-24 CODEC Data Transfer in RXFIFO When dec is used as the input source of RXFIFO 0, the data format of dec is selected by configuring dec_ain0_mode (AUDIO_DFIFO_BASE+0x3b[1:0]) as shown in the following table. Table 10-15 Data format of dec0_ain0_come and dec1_ain0_come

• When dec_ain0_mode selects 16bit mono, and configure the dec_leftdat_rxfifo_sel (AUDIO_DFIFO_BASE+0x35[0]) as 1'b0 will input two consecutive strokes of data from the left channel of the dec as 32bi t into RXFIFO0 and the first stroke is in the lower 16bit of 32bit and the second stroke is the higher 16bit of 32bit. If dec_rightdat_rxfifo_sel (AUDIO_DFIFO_BASE+0x35[1]) is configured 1'b0 will scramble the two consecutive strokes of data from the dec right channel into the 32bit inputs into RXFIFO0. Note: dec_leftdat_rxfifo_sel (AUDIO_DFIFO_BASE + 0x35[0]) and dec_rightdat_rxfifo_sel (AUDIO_DFIFO_BASE + 0x 35[1]) must be configured with different values.
• When dec_ain0_mode selects 20/24bit mono, and configure dec_leftdat_rxfifo_sel as 1'b0 to expand the left channel data symbols into 32bit to input into RXFIFO0, similarly if configuring dec_rightdat_rxfifo_sel as 1'b0 it will expand the dec right channel data symbols into 32bit input to RXFIFO0;
• When dec_ain0_mode selects 16bit stereo i t will splice the 16bit data of the left and right channels into 32bit and input it into RXFIFO0, where the left channel data is the lower 16bit of 32bit;
• When dec_ain0_mode selects 20/24bit stereo, the data will be written into RXFIFO0 in two strokes, first transferring the 32bit data of the left channel's symbol expansion, and then transferring the 32bit data of the right channel's symbol expansi on. In addition, when the I2S and CODEC data is used as the input source for RXFIFO1, it is consistent with RXFIFO0. Register Description dec_ain0_mode Rxfifo0 input mode select: 2'b00: 16bit mono 2'b01: 20bit mono 2'b10: 16bit stereo 2'b11: 20bit stereo.

Datasheet for Telink TL3828 DS-TL3828-E5 226 Ver 0.8.0

10.8.5 TXFIFO

The following figure shows the output structure of TXFIFO in normal mode. The txfifo output in normal mode has fixed channels. The SDM and USB are fixed to output from txfifo0, and I2S is fixed to output from txfifo2. Figure 10-25 TXFIFO Output Structure When sdm_2fifo mode (AUDIO_DFIFO_BASE+0x4b[0]) is configured, the left data of sdm is output from txfifo0 and the right data of sdm is output from txfifo1; when i 2s_2fifo mode (AUDIO_DFIFO_BASE+0x4b[1]) is configured, the left data of i2s is output from txfif00 and the right data of i2s is output from txfifo00.

10.8.6 Register Description of Audio FIFO

The Audio DFIFO related registers are listed in the table below. The base address for the following registers is 0x80141000. Table 10-16 Audio DFIFO Related Registers Address Offset Name Type Description Reset Value 0x00 SDM_SOFTMUTE RW [0]: sdm_softmute_l, sdm left softmute enable [1]: sdm_softmute_r, sdm right softmute enable [2]: sdm_softmute_l_mode_sel, sdm left softmute mode sel [3]: sdm_softmute_r_mode_sel, sdm right softmute mode sel [4]: sdm_bypass_softmute, sdm_softmute bypass enable 0x02 RXFIFO0_MAXL RW [7:0]: rxfifo0_max[7:0] RXFIFO0 wptr max low byte 0x00 0x03 RXFIFO0_MAXH RW [7:0]: rxfifo0_max[15:8] RXFIFO0 wptr max high byte 0x00 0x04 SDM_MUTE_STEP_L L RW [7:0]: sdm_mute_step_l_sel[7:0] sdm left mute setp low byte 0xa TXFIFO0 DMA i2s0_aout_mode sdm_tx usb TXFIFO1 i2s1_aout_mode i2s_tx

Datasheet for Telink TL3828 DS-TL3828-E5 227 Ver 0.8.0 0x05 SDM_MUTE_STEP_L H RW [7:0]: sdm_mute_step_l_sel[15:8] sdm left mute setp high byte 0x0 0x06 RXFIFO1_MAXL RW [7:0]: rxfifo1_max[7:0] RXFIFO1 wptr max low byte 0x00 0x07 RXFIFO1_MAXH RW [7:0]: rxfifo1_max]15:8] RXFIFO1 wptr max high byte 0x00 0x08 SDM_PGA_GAIN_L0 RW [7:0]: sdm_pga_gain_l[7:0] left sdm pga gain low byte 0x00 0x09 SDM_PGA_GAIN_L1 RW [7:0]: sdm_pga_gain_l[15:8] left sdm pga gain high byte 0x80 0x0a SDM_PGA_GAIN_R0 RW [7:0]: sdm_pga_gain_r[7:0] right sdm pga gain low byte 0x00 0x0b SDM_PGA_GAIN_R1 RW [7:0]: sdm_pga_gain_r[15:8] right sdm pga gain high byte 0x80 0x0c SDM_MUTE_IRQ_EN RW [0]: sdm_enter_mute_l_irq_en, sdm [1]: sdm_enter_mute_r_irq_en [2]: sdm_leave_mute_l_irq_en [3]: sdm_leave_mute_r_irq_en 0x0e SDM_MUTE_STEP_R L RW [7:0]: sdm_mute_step_r_sel[7:0] sdm right mute setp low byte 0x0f SDM_MUTE_STEP_R H RW [7:0]: sdm_mute_step_r_sel[15:8] sdm right mute setp high byte 0x10 RXFIFO_EN RW [0]: rxfifo0_ainen, enable audio input of rxfifo0 [1]: rxfifo1_ainen, enable audio input of rxfifo1 [5:4]: rxfifo_irq_en fifo interrupt enable, [4]: fifo0 enable; [5]: fifo1 enable 0x00 0x11 CODEC_CFG RW [1:0]: r_if, change sampling point, set 2'b01 [5]: r_neg [7:6]: r_ch_en, mic channel enable;[6]:mic l channel enable;[7]:mic r channel enable 0x01 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 228 Ver 0.8.0 0x12 CODEC_VOL RW [5:0]: dec_vol mic vol control: 6'h00:-48db 6'h04:-42db 6'h08:-36db 6'h0c:-30db 6'h10:-24db 6'h14:-18db 6'h18:-12db 6'h1c:-6db 6'h20:0db 6'h24:6db 6'h28:12db 6'h2c:18db 6'h30:24db 6'h34:30db 6'h38:36db 6'h3c:42db [7]: mic_sel, 0:amic 1:dmic 0x20 0x13 RSTN_EN RW [0]: rst_sdm_n, rst_sdm enable [1]: rst_i2s_n, rst_i2s enable [2]: rst_codec_n, rst_codec enable [3]: rst_ascl0_n, rst ascl0 enable [4]: rst_ascl1_line0_n, rst_ascl1_line0 enable [5]: rst_ascl1_line1_n, rst_ascl1_line1 enable [6]: rst_i2s_aclk_n, rst_i2s_aclk enable 0x1 0x14 TXFIFO0_RPTR_L W [7:0]: txfifo0_rptr[7:0] txfifo0 read ptr low byte 0x00 0x15 TXFIFO0_RPTR_H W [7:0]: txfifo0_rptr[15:8] txfifo0 read ptr high byte 0x00 0x16 RXFIFO0_WPTR_L W [7:0]: rxfifo0_wptr[7:0] rxfifo0 write ptr low byte 0x00 0x17 RXFIFO0_WPTR_H W [7:0]: rxfifo0_wptr[15:8] rxfifo0 write ptr high byte 0x00 0x18 TXFIFO1_RPTR_L W [7:0]: txfifo1_rptr[7:0] txfifo1 read ptr low byte 0x00 0x19 TXFIFO1_RPTR_H W [7:0]: txfifo1_rptr[15:8] txfifo1 read ptr high byte 0x00 0x1a RXFIFO1_WPTR_L W [7:0]: rxfifo1_wptr[7:0] rxfifo1 write ptr low byte 0x00 0x1b RXFIFO1_WPTR_H W [7:0]: rxfifo1_wptr[15:8] rxfifo1 write ptr high byte 0x00 0x20 RXFIFO0_NUM R [3:0]: rxfifo0_num, rxfifo0 data number 0x00 0x24 RXFIFO1_NUM R [3:0]: rxfifo1_num, rxfifo1 data number 0x00 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 229 Ver 0.8.0 0x33 FIFO0IN_SEL RW [1:0]: ain0_sel, rxfifo0 input sel 0:i2s; 1:codec; 2:usb 0x0 0x34 FIFO1IN_SEL RW [1:0]: ain1_sel, rxfifo1 input 0:i2s; 1:codec; 2:usb 0x1 0x35 RXFIFO_SEL RW [0]: i2s0_leftdat_rxfifo_sel, mono mode left fifo sel. 0: fifo0; 1: fifo1 [1]: i2s0_rightdat_rxfifo_sel, mono mode right fifo sel. 0: fifo0; 1: fifo1 0x36 I2S_RXFIFO_SEL RW [0]: i2s_leftdat_rxfifo_sel, i2s mono mode left fifo sel. 0: fifo0; 1: fifo1 [1]: i2s_right_rxfifo_sel, i2s mono mode right fifo sel. 0: fifo0; 1: fifo1 0x3a I2S_AIN_MODE RW [1:0]: i2s_ain0_mode, i2s fifo0 mode sel. 0: 16bit mono; 1: 20bit/24bit mono; 2: 16bit stereo; 3: 20bit/24bit stereo [3:2]: i2s_ain1_mode, i2s fifo1 mode sel. 0: 16bit mono; 1:20bit/24bit mono; 2: 16bit stereo; 3: 20bit/24bit stereo 0x0 0x3b DEC_AIN_MODE RW [1:0]: dec_ain0_mode, dec fifo0 mode sel. 0: 16bit mono; 1: 20bit mono; 2: 16bit stereo; 3: 20bit stereo [3:2]: dec_ain1_mode, dec fifo1 mode sel. 0: 16bit mono; 1:20bit mono; 2: 16bit stereo; 3: 20bit stereo [4]: dec_16b_h_o, 1'b1: high 16bit when wl is 16bit 0x3c RXFIFO0_TRIG_NU M RW [3:0]: rxfifo0_trig_num, rxfifo0 trig number 0x0 0x3d RXFIFO1_TRIG_NUM RW [3:0]: rxfifo1_trig_num, rxfifo1 trig number 0x0 0x3f RX_WPTR_EN RW [0]: rx0_wptr_en, rx0 wptr enable [1]: rx1_wptr_en, rx1 wptr enable [4]: tx0_rptr_en, tx0 rptr enable [5]: tx1_rptr_en, tx1 rptr enable 0x1 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 230 Ver 0.8.0 0x40 FIFO_CLR RW [0]: rxfifo0_clr, write a rxfifo0 clr pulse in pclk domain, read rxfifo0 clr in hclk domain [1]: rxfifo1_clr, write a rxfifo1 clr pulse in pclk domain, read rxfifo1 clr in hclk domain [4]: txfifo0_clr, write a txfifo0 clr pulse in pclk domain, read txfifo0 clr in hclk domain [5]: txfifo1_clr, write a txfifo1 clr pulse in pclk domain, read txfifo1 clr in hclk domain 0x0 0x41 FIFO_OUTEN RW [0]: txfifo0_aouten, enable audio output of rxfifo0 [1]: txfifo1_aouten, enable audio output of rxfifo1 [5:4]: txfifo_irq_en, txfifo interrupt enable. [4]: fifo0 enable; [5]: fifo1 enable 0x0 0x42 I2S_AOUT_MODE RW [1:0]: sdm_aout_mode, sdm out mode sel. 0: 16bit mono; 1: 20bit/24bit mono; 2: 16bit stereo; 3: 20bit/24bit stereo [5:4]: i2s_aout_mode, i2s out mode sel. 0: 16bit mono; 1:20bit/24bit mono; 2: 16bit stereo; 3: 20bit/24bit stereo 0x0 0x43 TXFIFO0_TRIG_NUM RW [3:0]: txfifo0_trig_num, txfifo0 trig number 0x1 0x44 TXFIFO1_TRIG_NUM RW [3:0]: txfifo1_trig_num, txfifo1 trig number 0x1 0x46 FIFO_ST R [0]: rxfifo0_overrun, write when rxfifo0 full [1]: rxfifo1_overrun, write when rxfifo1 full [4]: txfifo0_underrun, read when txfifo0 empty [5]: txfifo1_underrun, read when txfifo1 empty 0x0 0x47 I2S2_TDM_MODE_S EL RW [1:0]: i2s2_tdm_ain_mode, [0]:16bit TDM enable; [1]:20/24bit TDM enable [3:2]: i2s2_tdm_aout_mode, [2]:16bit TDM enable; [3]:20/24bit TDM enable 0x0 0x4b I2S_2FIFO_MODE RW [0]: sdm_2fifo_mode, sdm_2fifo_mode enable [1]: i2s_2fifo_mode, i2s_2fifo_mode enable 0x0 0x4c ascl0_aful_aemp RW [3:0]: txfifo0_numl, txfifo0 min num for ascl empty [7:4]: txfifo0_numh, txfifo0 max num for ascl empty 0x80 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 231 Ver 0.8.0 0x4d ascl1_aful_aemp RW [3:0]: txfifo1_numl, txfifo1 min num for ascl empty [7:4]: txfifo1_numh, txfifo1 max num for ascl empty 0x80 0x50 TXFIFO0_NUM R [3:0]: txfifo0_num, txfifo0 data number 0x00 0x51 TXFIFO1_NUM R [3:0]: txfifo1_num, txfifo1 data number 0x00 0x56 TXFIFO0_L RW [7:0]: txfifo0_h[7:0] TXFIFO0 low level when irq 0x00 0x57 TXFIFO0_H RW [7:0]: txfifo0_h[15:8] TXFIFO0 high level when irq 0x00 0x58 TXFIFO1_L RW [7:0]: txfifo1_h[7:0] TXFIFO1 low level when irq 0x00 0x59 TXFIFO1_H RW [7:0]: txfifo1_h[15:8] TXFIFO1 high level when irq 0x00 0x5c RXFIFO0_L RW [7:0]: rxfifo0_h[7:0] RXFIFO0 low level when irq 0x00 0x5d RXFIFO0_H RW [7:0]: rxfifo0_h[15:8] RXFIFO0 high level when irq 0x00 0x5e RXFIFO1_L RW [7:0]: rxfifo1_h[7:0] RXFIFO1 low level when irq 0x00 0x5f RXFIFO1_H RW [7:0]: rxfifo1_h[15:8] RXFIFO1 high level when irq 0x00 0x62 TXFIFO0_MAXL RW [7:0]: txfifo0_max[7:0] txfifo0 max num low byte for rptr 0x00 0x63 TXFIFO0_MAXH RW [7:0]: txfifo0_max[15:8] txfifo0 max num high byte for rptr 0x00 0x64 TXFIFO1_MAXL RW [7:0]: txfifo1_max[7:0] txfifo1 max num low byte for rptr 0x00 0x65 TXFIFO1_MAXH RW [7:0]: txfifo1_max[15:8] txfifo1 max num high byte for rptr 0x00 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 232 Ver 0.8.0 0x66 SOFTMUTE_IRQ_PC LK RW [0]: enter_mute_l_pclk [1]: enter_mute_r_pclk [2]: leave_mute_l_pclk [3]: leave_mute_r_pclk [4]: sdm_enter_mute_l_pclk [5]: sdm_enter_mute_r_pclk [6]: sdm_leave_mute_l_pclk [7]: sdm_leave_mute_r_pclk 0x0 0x68 FIFO_IRQ W1C [0]: rxfifo0_irq [1]: rxfifo1_irq [2]: txfifo0_irq [3]: txfifo1_irq [4]: sdm_enter_mute_l_irq [5]: sdm_enter_mute_r_irq [6]: sdm_leave_mute_l_irq [7]: sdm_leave_mute_r_irq 0x0 0x69 FIFO_TH_IRQ W1C [0]: rxfifo0_th_irq [1]: rxfifo1_th_irq [2]: txfifo0_th_irq [3]: txfifo1_th_irq [4]: enter_mute_l_irq [5]: enter_mute_r_irq [6]: leave_mute_l_irq 0x0 0x6a FIFO_TH_EN RW [0]: rxfifo0_th_irq_en, rxfifo0_th_irq enable [1]: rxfifo1_th_irq_en, rxfifo1_th_irq enable [2]: txfifo0_th_irq_en, txfifo0_th_irq enable [3]: txfifo1_th_irq_en, txfifo1_th_irq enable [4]: enter_mute_l_irq_en, enter_mute_l_irq_enable [5]: enter_mute_r_irq_en, enter_mute_r_irq_enable [6]: leave_mute_l_irq_en, leave_mute_l_irq_enable [7]: leave_mute_r_irq_en, leave_mute_r_irq_enable 0x0 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 233 Ver 0.8.0

10.9 Audio MUX

The AUDIO_MUX is divided into ATX_MUX and ARX_MUX. In which, ATX_MUX is the route from txfifo to each module and ARX_MUX is the route from each module to rxfifo. The output modules of ATX_MUX are SDML, SDMR, I2S, USB_TX. The ARX_MUX input modules are I2S, CODEC, USB_RX. For the details on how to route and how to select data format, please contact Telink FAE.

10.10 Schedule Mode

The schedule mode i ndicates that the relevant module can be enabled at a set point in time. The modules that support schedule mode are CODEC and I2S. The software configuration sequence is shown as below. 0x6b ACLK_DBG RW [0]: aclk_dbg_open, 1'b1:dsm_output_clk=aclk.for debug. [1]: sdm_clk_dbg, 1'b1:dsm_output_clk=i2s0.for debug. [3]: i2s_clk_dbg, 1'b1:dsm_output_clk=i2s2.for debug. [4]: adc_clk6m_dbg, 1'b1:dsm_output_clk=6M.for debug. [5]: adc_clk1m_dbg, 1'b1:dsm output clk=1M for debug [6]: codec_clk_dbg, 1'b1:dsm output clk=codec_clk for debug 0x0 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 234 Ver 0.8.0 Figure 10-26 CODEC Data Transfer in RXFIFO Taking I2S as an example, schedule mode requires additional registers to be configured:

• system_timer needs to be enabled first.
• I2s_schedule_en: I2S_TDM_BASE+0x03[4]
• I2S_stimer_target: I2S_TDM_BASE+0x0c~0x0f (need to configure by word)

10.11 Audio Interrupt

There are three audio interrupts: audio FIFO interrupt, audio FIFO DMA interrupt and soft mute interrupt.

10.11.1 Audio FIFO Interrupt

Audio fifo interrupt has 4 interrupts: tx fifo0_irq, txfifo1_irq, rxfifo0_irq, rxfifo1_irq. For txfifo*_irq, the interrupt is triggered when the total number of DMA write FIFO's reaches the set threshold. For rxfifo*_irq, the interrupt is triggered when the total number of DMA read FIFO’s reaches the set threshold. Take txfifo0_irq as an example, the write counter register of enable TXFIFO0 is AUDIO_DFIFO_BASE+0x3f[4], and you can set the initial value of the wri te counter (AUDIO_DFIFO_BASE+0x14~0x15), and the address of the txfifo0_threshold register is AUDIO_DFIFO_BASE+0x62~0x63, the status register of txfifo0_irq is AUDIO_DFIFO_BASE+0x68[2], writing 1 to AUDIO_DFIFO_BASE+0x69[2] means clear txfifo0_irq, the interrupt enable register of txfifo0_irq is AUDIO_DFIFO_BASE+0x6a[2].

10.11.2 Audio FIFO DMA Interrupt

Audio FIFO DMA interrupt has 4 interrupts: txfifo0_dma_irq, txfifo1_dma_irq, rx fifo0_dma_irq, rxfifo1_dma_irq. Configure adc/dac dma enable them Configure stimer_schedule Enable codec_en_trig During this time, start moving data from dac_dma to txfifo for temporary storage

Datasheet for Telink TL3828 DS-TL3828-E5 235 Ver 0.8.0 For txfifo*_dma_irq, the interrupt is triggered when txfifo_num < txfifo_threshold, then MCU can write data to TXFIFO. For rxfifo*_dma_irq, the interrupt is triggered when rxfifo_num > rxfifo_threshold, at this time MCU can read Data from RXFIFO.

10.11.3 Soft Mute Interrupt

Soft mute interrupt has 4 interrupts: enter_mute_l, enter_mute_r, leave_mute_l, leave_mute_r. For enter_mute_*, the interrupt is triggered when the CODEC transi tions from normal audio output to a mute state. For leave_mute_*, the interrupt is triggered when the codec transitions from mute back to normal audio output. Taking enter_mute_l as an example. When the CODEC enters the soft mute state and enter_mute_l_en (at AUDIO_DFIFO_BASE + 0x6a[4]) is set to 1, an interrupt is generated. The status register for enter_mute_l is located at AUDIO_DFIFO_BASE + 0x 69[4]. Writing 1 to this bit clears the enter_mute_l interrupt. To check whether the CODEC has completed entering the mute state, read AUDIO_DFIFO_BASE + 0x66[0].

Datasheet for Telink TL3828 DS-TL3828-E5 236 Ver 0.8.0

11 Interface

11.1 GPIO

The TL3828A supports up to 64 GPIOs. The TL3828B supports up to 40 GPIOs.All digital IOs can be used as general purpose IOs.

11.1.1 GPIO Main Features

The GPIO main features include:

• Up to 8 GPIO pins per GPIO port
• Configurable output drive strength
• Output data from output data register or peripheral
• Input data to input data register or peripheral
• Internal pull-up and pull-down resistors
• Trigger i nterrupt on state changes on any pins
• Wake-up from high or low level triggers on all pins

11.1.2 Basic Configuration

All GPIOs can be configured with related registers, as described as following. Table 11-1 GPIO Pad Function Mux Pad Default Register = [13:126]a Register = 59 Register = 41 Register = [1:12] Register = 0 Registerb PA[0] GPIO All functionsc KEYS0 - PWM#1d - 0x80140cb0[6:0] PA[1] GPIO All functions KEYS1 - PWM#2 - 0x80140cb1[6:0] PA[2] GPIO All functions KEYS2 - PWM#3 - 0x80140cb2[6:0] PA[3] GPIO - - - - - 0x80140cb3[6:0] PA[4] GPIO - - - - - 0x80140cb4[6:0] PA[5] GPIO - - - - - - PA[6] GPIO - - - - - - PA[7] SWS SWMe - - - SWS 0x80140cb7[6:0] PB[0] GPIO All functions KEYS5 - PWM#2 - 0x80140cb8[6:0] PB[1] GPIO All functions KEYS6 - PWM#3 - 0x80140cb9[6:0] PB[2] GPIO All functions KEYS7 - PWM#4 - 0x80140cba[6:0] PB[3] GPIO All functions KEYS8 - PWM#1 - 0x80140cbb[6:0]

Datasheet for Telink TL3828 DS-TL3828-E5 237 Ver 0.8.0 PB[4] GPIO All functions KEYS9 - PWM#2 - 0x80140cbc[6:0] PB[5] GPIO All functions KEYS10 - PWM#3 - 0x80140cbd[6:0] PB[6] GPIO All functions KEYS11 - PWM#4 - 0x80140cbe[6:0] PB[7] GPIO All functions KEYS12 - PWM#1 - 0x80140cbf[6:0] PC[0] GPIO All functions KEYS13 - PWM#2 - 0x80140cc0[6:0] PC[1] GPIO All functions KEYS14 - PWM#3 - 0x80140cc1[6:0] PC[2] GPIO All functions KEYS15 - PWM#4 - 0x80140cc2[6:0] PC[3] GPIO All functions KEYS16 - PWM#1 - 0x80140cc3[6:0] PC[4] GPIO All functions KEYS17 - PWM#2 - 0x80140cc4[6:0] PC[5] GPIO All functions KEYS18 - PWM#3 - 0x80140cc5[6:0] PC[6] GPIO All functions KEYS19 - PWM#4 - 0x80140cc6[6:0] PC[7] GPIO All functions KEYS20 - PWM#1 - 0x80140cc7[6:0] PD[0] SSPI_CN All functions KEYS21 - PWM#2 - 0x80140cc8[6:0] PD[1] SSPI_CK All functions KEYS22 - PWM#3 - 0x80140cc9[6:0] PD[2] SSPI_SI All functions KEYS23 - PWM#4 - 0x80140cca[6:0] PD[3] SSPI_SO All functions KEYS24 - PWM#1 - 0x80140ccb[6:0] PD[4] TDI All functions KEYS25 TDI PWM#2 - 0x80140ccc[6:0] PD[5] TDO All functions KEYS26 TDO PWM#3 - 0x80140ccd[6:0] PD[6] TMS All functions KEYS27 TMS PWM#4 - 0x80140cce[6:0] PD[7] TCK All functions KEYS28 TCK PWM#1 - 0x80140ccf[6:0] PE[0] GPIO All functions KEYS29 - PWM#2 - 0x80140cd0[6:0] PE[1] GPIO All functions KEYS30 - PWM#3 - 0x80140cd1[6:0] PE[2] GPIO All functions KEYS31 - PWM#4 - 0x80140cd2[6:0] PE[3] GPIO All functions KEYS0 - PWM#1 - 0x80140cd3[6:0] PE[4] GPIO All functions KEYS1 - PWM#2 - 0x80140cd4[6:0] PE[5] GPIO All functions KEYS2 - PWM#3 - 0x80140cd5[6:0] PE[6] GPIO All functions KEYS3 - PWM#4 - 0x80140cd6[6:0] Pad Default Register = [13:126]a Register = 59 Register = 41 Register = [1:12] Register = 0 Registerb

Datasheet for Telink TL3828 DS-TL3828-E5 238 Ver 0.8.0 PE[7] GPIO All functions KEYS4 - PWM#1 - 0x80140cd7[6:0] PF[0] GPIO All functions KEYS5 - PWM#2 - 0x80140cd8[6:0] PF[1] GPIO All functions KEYS6 - PWM#3 - 0x80140cd9[6:0] PF[2] GPIO All functions KEYS7 - PWM#4 - 0x80140cda[6:0] PF[3] GPIO All functions KEYS8 - PWM#1 - 0x80140cdb[6:0] PF[4] GPIO All functions KEYS9 - PWM#2 - 0x80140cdc[6:0] PF[5] GPIO All functions KEYS10 - PWM#3 - 0x80140cdd[6:0] PF[6] GPIO All functions KEYS11 - PWM#4 - 0x80140cde[6:0] PF[7] GPIO All functions KEYS12 - PWM#1 - 0x80140cdf[6:0] PG[0] GPIO All functions KEYS13 - PWM#2 - 0x80140ce0[6:0] PG[1] GPIO All functions KEYS14 - PWM#3 - 0x80140ce1[6:0] PG[2] GPIO All functions KEYS15 - PWM#4 - 0x80140ce2[6:0] PG[3] GPIO All functions KEYS16 - PWM#1 - 0x80140ce3[6:0] PG[4] GPIO All functions KEYS17 - PWM#2 - 0x80140ce4[6:0] PG[5] GPIO All functions KEYS18 - PWM#3 - 0x80140ce5[6:0] PG[6] GPIO All functions KEYS19 - PWM#4 - 0x80140ce6[6:0] PG[7] GPIO All functions KEYS20 - PWM#1 - 0x80140ce7[6:0] PH[0] GPIO All functions KEYS21 - PWM#2 - 0x80140ce8[6:0] PH[1] GPIO All functions KEYS22 - PWM#3 - 0x80140ce9[6:0] PH[2] GPIO All functions KEYS23 - PWM#4 - 0x80140cea[6:0] PH[3] GPIO All functions KEYS24 - PWM#1 - 0x80140ceb[6:0] PH[4] GPIO All functions KEYS25 - PWM#2 - 0x80140cec[6:0] PH[5] GPIO All functions KEYS26 - PWM#3 - 0x80140ced[6:0] PH[6] GPIO All functions KEYS27 - PWM#4 - 0x80140cee[6:0] PH[7] GPIO All functions KEYS28 - PWM#1 - 0x80140cef[6:0] a. Exclude register = [41], [59]; register = [74:76] are reserved. b. The bit width of the register is [6:0], and the default value is 0x00. c. “All functions” include 100 functions, see Table 11-2 below. Pad Default Register = [13:126]a Register = 59 Register = 41 Register = [1:12] Register = 0 Registerb

Datasheet for Telink TL3828 DS-TL3828-E5 239 Ver 0.8.0 The functions included in the “All functions” are listed in the table below: Table 11-2 GPIO functions d. “PWM#1” include PWM0, PWM4, PWM8, PWM12, PWM16, PWM20, PWM0_N, PWM4_N, PWM8_N, PWM12_N, PWM16_N, PWM20_N; “PWM#2” include PWM1, PWM5, PWM9, PWM13, PWM17, PWM21, PWM1_N, PWM5_N, PWM9_N, PWM13_N, PWM17_N, PWM21_N; “PWM#3” include PWM2, PWM6, PWM10, PWM14, PWM18, PWM22, PWM2_N, PWM6_N, PWM10_N, PWM14_N, PWM18_N, PWM22_N; “PWM#4” include PWM3, PWM7, PWM11, PWM15, PWM19, PWM23, PWM3_N, PWM7_N, PWM11_N, PWM15_N, PWM19_N, PWM23_N. e. Only when 0x80140cb7[6:0] is 0x3e, the function of PA[7] is SWM. Register value Function Register value Function Register value Function 13 - 51 SDM0_N 89 I3C1_SDA 14 - 52 SDM1_P 90 I3C1_SCL 15 - 53 SDM1_N 91 GSPI0_CN

21 UART0_RTS 59 See Table 11-1 97 GSPI1_CN

Datasheet for Telink TL3828 DS-TL3828-E5 240 Ver 0.8.0

41 See Table 11-1 79 LIN1_RX 117 GSPI4_IO2

Datasheet for Telink TL3828 DS-TL3828-E5 241 Ver 0.8.0 The configuration registers for the GPIOs are listed in the table below: Table 11-3 GPIO Setting Pad Input IE OEN Polarity output set/ output clear Act as GPIO/ output toggle SR/DS0/DS1 PA[0] 0x80140c0 0 [0] 0x80140c0 1 [0] 0x80140c0 2 [0] 0x80140c0 3 [0] 0x80140c04[0]/ 0x80140c05[0] 0x80140c06[0]/ 0x80140c07[0] 0x80140c08[0]/ 0x80140c09[0] /0x80140c0a[0] PA[1] 0x80140c0 0 [1] 0x80140c0 1 [1] 0x80140c0 2 [1] 0x80140c0 3 [1] 0x80140c04[1]/ 0x80140c05[1] 0x80140c06[1]/ 0x80140c07[1] 0x80140c08[1]/ 0x80140c09[1]/ 0x80140c0a[1] PA[2] 0x80140c0 0 [2] 0x80140c0 1 [2] 0x80140c0 2 [2] 0x80140c0 3 [2] 0x80140c04[2]/ 0x80140c05[2] 0x80140c06[2]/ 0x80140c07[2] 0x80140c08[2]/ 0x80140c09[2]/ 0x80140c0a[2] PA[3] 0x80140c0 0 [3] 0x80140c0 1 [3] 0x80140c0 2 [3] 0x80140c0 3 [3] 0x80140c04[3]/ 0x80140c05[3] 0x80140c06[3]/ 0x80140c07[3] 0x80140c08[3]/ 0x80140c09[3]/ 0x80140c0a[3] PA[4] 0x80140c0 0 [4] 0x80140c0 1 [4] 0x80140c0 2 [4] 0x80140c0 3 [4] 0x80140c04[4]/ 0x80140c05[4] 0x80140c06[4]/ 0x80140c07[4] 0x80140c08[4]/ 0x80140c09[4]/ 0x80140c0a[4] PA[5] 0x80140c0 0 [5] 0x80140c0 1 [5] 0x80140c0 2 [5] 0x80140c0 3 [5] 0x80140c04[5]/ 0x80140c05[5] 0x80140c06[5]/ 0x80140c07[5] 0x80140c08[5]/ 0x80140c09[5]/ 0x80140c0a[5] NOTE: For GPIO Multiple Function Switching,

• The default function is GPIO, user need to configure the desired function MUX first and then disable the GPIO function.
• The default is the function IO, which needs to be changed to GPIO output, user need to set the output value and OEN of the corresponding IO first, and then enable GPIO function.
• The default is the function IO, which needs to be changed to GPIO i nput, º The IO needs to be pulled up: – Case 1 (digital pull-up): set the pullup to 1, OEN to 1; – Case 2 (analog pull-up): Set the analog register for pullup. º No need to be pulled up: – Case 1 (digital pull-up): set the pullup to 0, OEN to 1; – case 2 (analog pull-up): Set the analog register for pullup. º Finally enable GPIO function.

Datasheet for Telink TL3828 DS-TL3828-E5 242 Ver 0.8.0 PA[6] 0x80140c0 0 [6] 0x80140c0 1 [6] 0x80140c0 2 [6] 0x80140c0 3 [6] 0x80140c04[6]/ 0x80140c05[6] 0x80140c06[6]/ 0x80140c07[6] 0x80140c08[6]/ 0x80140c09[6]/ 0x80140c0a[6] PA[7] 0x80140c0 0 [7] 0x80140c0 1 [7] 0x80140c0 2 [7] 0x80140c0 3 [7] 0x80140c04[7]/ 0x80140c05[7] 0x80140c06[7]/ 0x80140c07[7] 0x80140c08[7]/ 0x80140c09[7]/ 0x80140c0a[7] PB[0] 0x80140c1 0 [0] 0x80140c1 1 [0] 0x80140c1 2 [0] 0x80140c1 3 [0] 0x80140c14[0]/ 0x80140c15[0] 0x80140c16[0]/ 0x80140c17[0] 0x80140c18[0]/ 0x80140c19[0]/ 0x80140c1a[0] PB[1] 0x80140c1 0 [1] 0x80140c1 1 [1] 0x80140c1 2 [1] 0x80140c1 3 [1] 0x80140c14[1]/ 0x80140c15[1] 0x80140c16[1]/ 0x80140c17[1] 0x80140c18[1]/ 0x80140c19[1]/ 0x80140c1a[1] PB[2] 0x80140c1 0 [2] 0x80140c1 1 [2] 0x80140c1 2 [2] 0x80140c1 3 [2] 0x80140c14[2]/ 0x80140c15[2] 0x80140c16[2]/ 0x80140c17[2] 0x80140c18[2]/ 0x80140c19[2]/ 0x80140c1a[2] PB[3] 0x80140c1 0 [3] 0x80140c1 1 [3] 0x80140c1 2 [3] 0x80140c1 3 [3] 0x80140c14[3]/ 0x80140c15[3] 0x80140c16[3]/ 0x80140c17[3] 0x80140c18[3]/ 0x80140c19[3]/ 0x80140c1a[3] PB[4] 0x80140c1 0 [4] ana_0x120 [4] 0x80140c1 2 [4] 0x80140c1 3 [4] 0x80140c14[4]/ 0x80140c15[4] 0x80140c16[4]/ 0x80140c17[4] ana_0x121[4]/ ana_0x122[4]/ ana_0x123[4] PB[5] 0x80140c1 0 [5] ana_0x120 [5] 0x80140c1 2 [5] 0x80140c1 3 [5] 0x80140c14[5]/ 0x80140c15[5] 0x80140c16[5]/ 0x80140c17[5] ana_0x121[5]/ ana_0x122[5]/ ana_0x123[5] PB[6] 0x80140c1 0 [6] ana_0x120 [6] 0x80140c1 2 [6] 0x80140c1 3 [6] 0x80140c14[6]/ 0x80140c15[6] 0x80140c16[6]/ 0x80140c17[6] ana_0x121[6]/ ana_0x122[6]/ ana_0x123[6] PB[7] 0x80140c1 0 [7] ana_0x120 [7] 0x80140c1 2 [7] 0x80140c1 3 [7] 0x80140c14[7]/ 0x80140c15[7] 0x80140c16[7]/ 0x80140c17[7] ana_0x121[7]/ ana_0x122[7]/ ana_0x123[7] PC[0] 0x80140c2 0 [0] ana_0x124 [0] 0x80140c2 2 [0] 0x80140c2 3 [0] 0x80140c24[0]/ 0x80140c25[0] 0x80140c26[0]/ 0x80140c27[0] ana_0x125[0]/ ana_0x126[0]/ ana_0x127[0] Pad Input IE OEN Polarity output set/ output clear Act as GPIO/ output toggle SR/DS0/DS1

Datasheet for Telink TL3828 DS-TL3828-E5 243 Ver 0.8.0 PC[1] 0x80140c2 0 [1] ana_0x124 [1] 0x80140c2 2 [1] 0x80140c2 3 [1] 0x80140c24[1]/ 0x80140c25[1] 0x80140c26[1]/ 0x80140c27[1] ana_0x125[1]/ ana_0x126[1]/ ana_0x127[1] PC[2] 0x80140c2 0 [2] ana_0x124 [2] 0x80140c2 2 [2] 0x80140c2 3 [2] 0x80140c24[2]/ 0x80140c25[2] 0x80140c26[2]/ 0x80140c27[2] ana_0x125[2]/ ana_0x126[2]/ ana_0x127[2] PC[3] 0x80140c2 0 [3] ana_0x124 [3] 0x80140c2 2 [3] 0x80140c2 3 [3] 0x80140c24[3]/ 0x80140c25[3] 0x80140c26[3]/ 0x80140c27[3] ana_0x125[3]/ ana_0x126[3]/ ana_0x127[3] PC[4] 0x80140c2 0 [4] ana_0x124 [4] 0x80140c2 2 [4] 0x80140c2 3 [4] 0x80140c24[4]/ 0x80140c25[4] 0x80140c26[4]/ 0x80140c27[4] ana_0x125[4]/ ana_0x126[4]/ ana_0x127[4] PC[5] 0x80140c2 0 [5] ana_0x124 [5] 0x80140c2 2 [5] 0x80140c2 3 [5] 0x80140c24[5]/ 0x80140c25[5] 0x80140c26[5]/ 0x80140c27[5] ana_0x125[5]/ ana_0x126[5]/ ana_0x127[5] PC[6] 0x80140c2 0 [6] ana_0x124 [6] 0x80140c2 2 [6] 0x80140c2 3 [6] 0x80140c24[6]/ 0x80140c25[6] 0x80140c26[6]/ 0x80140c27[6] ana_0x125[6]/ ana_0x126[6]/ ana_0x127[6] PC[7] 0x80140c2 0 [7] ana_0x124 [7] 0x80140c2 2 [7] 0x80140c2 3 [7] 0x80140c24[7]/ 0x80140c25[7] 0x80140c26[7]/ 0x80140c27[7] ana_0x125[7]/ ana_0x126[7]/ ana_0x127[7] PD[0] 0x80140c3 0 [0] 0x80140c3 1 [0] 0x80140c3 2 [0] 0x80140c3 3 [0] 0x80140c34[0]/ 0x80140c35[0] 0x80140c36[0]/ 0x80140c37[0] 0x80140c38[0]/ 0x80140c39[0]/ 0x80140c3a[0] PD[1] 0x80140c3 0 [1] 0x80140c3 1 [1] 0x80140c3 2 [1] 0x80140c3 3 [1] 0x80140c34[1]/ 0x80140c35[1] 0x80140c36[1]/ 0x80140c37[1] 0x80140c38[1]/ 0x80140c39[1]/ 0x80140c3a[1] PD[2] 0x80140c3 0 [2] 0x80140c3 1 [2] 0x80140c3 2 [2] 0x80140c3 3 [2] 0x80140c34[2]/ 0x80140c35[2] 0x80140c36[2]/ 0x80140c37[2] 0x80140c38[2]/ 0x80140c39[2]/ 0x80140c3a[2] PD[3] 0x80140c3 0 [3] 0x80140c3 1 [3] 0x80140c3 2 [3] 0x80140c3 3 [3] 0x80140c34[3]/ 0x80140c35[3] 0x80140c36[3]/ 0x80140c37[3] 0x80140c38[3]/ 0x80140c39[3]/ 0x80140c3a[3] Pad Input IE OEN Polarity output set/ output clear Act as GPIO/ output toggle SR/DS0/DS1

Datasheet for Telink TL3828 DS-TL3828-E5 244 Ver 0.8.0 PD[4] 0x80140c3 0 [4] 0x80140c3 1 [4] 0x80140c3 2 [4] 0x80140c3 3 [4] 0x80140c34[4]/ 0x80140c35[4] 0x80140c36[4]/ 0x80140c37[4] 0x80140c38[4]/ 0x80140c39[4]/ 0x80140c3a[4] PD[5] 0x80140c3 0 [5] 0x80140c3 1 [5] 0x80140c3 2 [5] 0x80140c3 3 [5] 0x80140c34[5]/ 0x80140c35[5] 0x80140c36[5]/ 0x80140c37[5] 0x80140c38[5]/ 0x80140c39[5]/ 0x80140c3a[5] PD[6] 0x80140c3 0 [6] 0x80140c3 1 [6] 0x80140c3 2 [6] 0x80140c3 3 [6] 0x80140c34[6]/ 0x80140c35[6] 0x80140c36[6]/ 0x80140c37[6] 0x80140c38[6]/ 0x80140c39[6]/ 0x80140c3a[6] PD[7] 0x80140c3 0 [7] 0x80140c3 1 [7] 0x80140c3 2 [7] 0x80140c3 3 [7] 0x80140c34[7]/ 0x80140c35[7] 0x80140c36[7]/ 0x80140c37[7] 0x80140c38[7]/ 0x80140c39[7]/ 0x80140c3a[7] PE[0] 0x80140c4 0 [0] 0x80140c4 1 [0] 0x80140c4 2 [0] 0x80140c4 3 [0] 0x80140c44[0]/ 0x80140c45[0] 0x80140c46[0]/ 0x80140c47[0] 0x80140c48[0]/ 0x80140c49[0]/ 0x80140c4a[0] PE[1] 0x80140c4 0 [1] 0x80140c4 1 [1] 0x80140c4 2 [1] 0x80140c4 3 [1] 0x80140c44[1]/ 0x80140c45[1] 0x80140c46[1]/ 0x80140c47[1] 0x80140c49[1]/ 0x80140c49[1]/ 0x80140c4a[1] PE[2] 0x80140c4 0 [2] 0x80140c4 1 [2] 0x80140c4 2 [2] 0x80140c4 3 [2] 0x80140c44[2]/ 0x80140c45[2] 0x80140c46[2]/ 0x80140c47[2] 0x80140c49[2]/ 0x80140c49[2]/ 0x80140c4a[2] PE[3] 0x80140c4 0 [3] 0x80140c4 1 [3] 0x80140c4 2 [3] 0x80140c4 3 [3] 0x80140c44[3]/ 0x80140c45[3] 0x80140c46[3]/ 0x80140c47[3] 0x80140c48[3]/ 0x80140c49[3]/ 0x80140c4a[3] PE[4] 0x80140c4 0 [4] 0x80140c4 1 [4] 0x80140c4 2 [4] 0x80140c4 3 [4] 0x80140c44[4]/ 0x80140c45[4] 0x80140c46[4]/ 0x80140c47[4] 0x80140c48[4]/ 0x80140c49[4]/ 0x80140c4a[4] PE[5] 0x80140c4 0 [5] 0x80140c4 1 [5] 0x80140c4 2 [5] 0x80140c4 3 [5] 0x80140c44[5]/ 0x80140c45[5] 0x80140c46[5]/ 0x80140c47[5] 0x80140c48[5]/ 0x80140c49[5]/ 0x80140c4a[5] PE[6] 0x80140c4 0 [6] 0x80140c4 1 [6] 0x80140c4 2 [6] 0x80140c4 3 [6] 0x80140c44[6]/ 0x80140c45[6] 0x80140c46[6]/ 0x80140c47[6] 0x80140c48[6]/ 0x80140c49[6]/ 0x80140c4a[6] Pad Input IE OEN Polarity output set/ output clear Act as GPIO/ output toggle SR/DS0/DS1

Datasheet for Telink TL3828 DS-TL3828-E5 245 Ver 0.8.0 PE[7] 0x80140c4 0 [7] 0x80140c4 1 [7] 0x80140c4 2 [7] 0x80140c4 3 [7] 0x80140c44[7]/ 0x80140c45[7] 0x80140c46[7]/ 0x80140c47[7] 0x80140c48[7]/ 0x80140c49[7]/ 0x80140c4a[7] PF[0] 0x80140c5 0 [0] 0x80140c5 1 [0] 0x80140c5 2 [0] 0x80140c5 3 [0] 0x80140c54[0]/ 0x80140c55[0] 0x80140c56[0]/ 0x80140c57[0] 0x80140c58[0]/ 0x80140c59[0]/ 0x80140c5a[0] PF[1] 0x80140c5 0 [1] 0x80140c5 1 [1] 0x80140c5 2 [1] 0x80140c5 3 [1] 0x80140c54[1]/ 0x80140c55[1] 0x80140c56[1]/ 0x80140c57[1] 0x80140c58[1]/ 0x80140c59[1]/ 0x80140c5a[1] PF[2] 0x80140c5 0 [2] 0x80140c5 1 [2] 0x80140c5 2 [2] 0x80140c5 3 [2] 0x80140c54[2]/ 0x80140c55[2] 0x80140c56[2]/ 0x80140c57[2] 0x80140c58[2]/ 0x80140c59[2]/ 0x80140c5a[2] PF[3] 0x80140c5 0 [3] 0x80140c5 1 [3] 0x80140c5 2 [3] 0x80140c5 3 [3] 0x80140c54[3]/ 0x80140c55[3] 0x80140c56[3]/ 0x80140c57[3] 0x80140c58[3]/ 0x80140c59[3]/ 0x80140c5a[3] PF[4] 0x80140c5 0 [4] 0x80140c5 1 [4] 0x80140c5 2 [4] 0x80140c5 3 [4] 0x80140c54[4]/ 0x80140c55[4] 0x80140c56[4]/ 0x80140c57[4] 0x80140c58[4]/ 0x80140c59[4]/ 0x80140c5a[4] PF[5] 0x80140c5 0 [5] 0x80140c5 1 [5] 0x80140c5 2 [5] 0x80140c5 3 [5] 0x80140c54[5]/ 0x80140c55[5] 0x80140c56[5]/ 0x80140c57[5] 0x80140c58[5]/ 0x80140c59[5]/ 0x80140c5a[5] PF[6] 0x80140c5 0 [6] 0x80140c5 1 [6] 0x80140c5 2 [6] 0x80140c5 3 [6] 0x80140c54[6]/ 0x80140c55[6] 0x80140c56[6]/ 0x80140c57[6] 0x80140c58[6]/ 0x80140c59[6]/ 0x80140c5a[6] PF[7] 0x80140c5 0 [7] 0x80140c5 1 [7] 0x80140c5 2 [7] 0x80140c5 3 [7] 0x80140c54[7]/ 0x80140c55[7] 0x80140c56[7]/ 0x80140c57[7] 0x80140c58[7]/ 0x80140c59[7]/ 0x80140c5a[7] PG[0] 0x80140c6 0 [0] 0x80140c6 1 [0] 0x80140c6 2 [0] 0x80140c6 3 [0] 0x80140c64[0]/ 0x80140c65[0] 0x80140c66[0]/ 0x80140c67[0] 0x80140c68[0]/ 0x80140c69[0]/ 0x80140c6a[0] PG[1] 0x80140c6 0 [1] 0x80140c6 1 [1] 0x80140c6 2 [1] 0x80140c6 3 [1] 0x80140c64[1]/ 0x80140c65[1] 0x80140c66[1]/ 0x80140c67[1] 0x80140c68[1]/ 0x80140c69[1]/ 0x80140c6a[1] Pad Input IE OEN Polarity output set/ output clear Act as GPIO/ output toggle SR/DS0/DS1

Datasheet for Telink TL3828 DS-TL3828-E5 246 Ver 0.8.0 PG[2] 0x80140c6 0 [2] 0x80140c6 1 [2] 0x80140c6 2 [2] 0x80140c6 3 [2] 0x80140c64[2]/ 0x80140c65[2] 0x80140c66[2]/ 0x80140c67[2] 0x80140c68[2]/ 0x80140c69[2]/ 0x80140c6a[2] PG[3] 0x80140c6 0 [3] 0x80140c6 1 [3] 0x80140c6 2 [3] 0x80140c6 3 [3] 0x80140c64[3]/ 0x80140c65[3] 0x80140c66[3]/ 0x80140c67[3] 0x80140c68[3]/ 0x80140c69[3]/ 0x80140c6a[3] PG[4] 0x80140c6 0 [4] 0x80140c6 1 [4] 0x80140c6 2 [4] 0x80140c6 3 [4] 0x80140c64[4]/ 0x80140c65[4] 0x80140c66[4]/ 0x80140c67[4] 0x80140c68[4]/ 0x80140c69[4]/ 0x80140c6a[4] PG[5] 0x80140c6 0 [5] 0x80140c6 1 [5] 0x80140c6 2 [5] 0x80140c6 3 [5] 0x80140c64[5]/ 0x80140c65[5] 0x80140c66[5]/ 0x80140c67[5] 0x80140c68[5]/ 0x80140c69[5]/ 0x80140c6a[5] PG[6] 0x80140c6 0 [6] 0x80140c6 1 [6] 0x80140c6 2 [6] 0x80140c6 3 [6] 0x80140c64[6]/ 0x80140c65[6] 0x80140c66[6]/ 0x80140c67[6] 0x80140c68[6]/ 0x80140c69[6]/ 0x80140c6a[6] PG[7] 0x80140c6 0 [7] 0x80140c6 1 [7] 0x80140c6 2 [7] 0x80140c6 3 [7] 0x80140c64[7]/ 0x80140c65[7] 0x80140c66[7]/ 0x80140c67[7] 0x80140c68[7]/ 0x80140c69[7]/ 0x80140c6a[7] PH[0] 0x80140c7 0 [0] 0x80140c7 1 [0] 0x80140c7 2 [0] 0x80140c7 3 [0] 0x80140c74[0]/ 0x80140c75[0] 0x80140c76[0]/ 0x80140c77[0] 0x80140c78[0]/ 0x80140c79[0]/ 0x80140c7a[0] PH[1] 0x80140c7 0 [1] 0x80140c7 1 [1] 0x80140c7 2 [1] 0x80140c7 3 [1] 0x80140c74[1]/ 0x80140c75[1] 0x80140c76[1]/ 0x80140c77[1] 0x80140c78[1]/ 0x80140c79[1]/ 0x80140c7a[1] PH[2] 0x80140c7 0 [2] 0x80140c7 1 [2] 0x80140c7 2 [2] 0x80140c7 3 [2] 0x80140c74[2]/ 0x80140c75[2] 0x80140c76[2]/ 0x80140c77[2] 0x80140c78[2]/ 0x80140c79[2]/ 0x80140c7a[2] PH[3] 0x80140c7 0 [3] 0x80140c7 1 [3] 0x80140c7 2 [3] 0x80140c7 3 [3] 0x80140c74[3]/ 0x80140c75[3] 0x80140c76[3]/ 0x80140c77[3] 0x80140c78[3]/ 0x80140c79[3]/ 0x80140c7a[3] PH[4] 0x80140c7 0 [4] 0x80140c7 1 [4] 0x80140c7 2 [4] 0x80140c7 3 [4] 0x80140c74[4]/ 0x80140c75[4] 0x80140c76[4]/ 0x80140c77[4] 0x80140c78[4]/ 0x80140c79[4]/ 0x80140c7a[4] Pad Input IE OEN Polarity output set/ output clear Act as GPIO/ output toggle SR/DS0/DS1

Datasheet for Telink TL3828 DS-TL3828-E5 247 Ver 0.8.0 Table 11-4 GPIO Function Mux Configuration Registers PH[5] 0x80140c7 0 [5] 0x80140c7 1 [5] 0x80140c7 2 [5] 0x80140c7 3 [5] 0x80140c74[5]/ 0x80140c75[5] 0x80140c76[5]/ 0x80140c77[5] 0x80140c78[5]/ 0x80140c79[5]/ 0x80140c7a[5] PH[6] 0x80140c7 0 [6] 0x80140c7 1 [6] 0x80140c7 2 [6] 0x80140c7 3 [6] 0x80140c74[6]/ 0x80140c75[6] 0x80140c76[6]/ 0x80140c77[6] 0x80140c78[6]/ 0x80140c79[6]/ 0x80140c7a[6] PH[7] 0x80140c7 0 [7] 0x80140c7 1 [7] 0x80140c7 2 [7] 0x80140c7 3 [7] 0x80140c74[7]/ 0x80140c75[7] 0x80140c76[7]/ 0x80140c77[7] 0x80140c78[7]/ 0x80140c79[7]/ 0x80140c7a[7] Address Type Description Default Value 0x80140cb0 RW [6:0]: function control bits of PA0_FS 0x00 0x80140cb1 RW [6:0]: function control bits of PA1_FS 0x00 0x80140cb2 RW [6:0]: function control bits of PA2_FS 0x00 0x80140cb3 RW [6:0]: function control bits of PA3_FS 0x00 0x80140cb4 RW [6:0]: function control bits of PA4_FS 0x00 0x80140cb5 R [6:0]: function control bits of PA5_FS 0x00 0x80140cb6 R [6:0]: function control bits of PA6_FS 0x00 Pad Input IE OEN Polarity output set/ output clear Act as GPIO/ output toggle SR/DS0/DS1 NOTE:

• IE: Input enable, high active. 1: enable input, 0: disable input.
• OEN: Output enable, low active. 0: enable output, 1: disable output.
• Output set, Output clear and Output toggle: configure GPO output.
• Input: Read GPI input.
• DS0/DS1/SR: Drive strength and slew rate.
• Act as GPIO: Enable (1) or disable (0) GPIO function.
• Polarity: By configuring “Polarity” registers, user can determine GPIO edges in Timer modes. In Timer Mode 1, it determines GPIO edge when Timer Tick counting increases. In Ti mer Mode 2, it determines GPIO edge when Timer Tick starts counting. Users can read addresses to see which GPIO asserts counting signals (Mode 1) / control signal (Mode 2) for Timers.
• ana_0x120 ~ ana_0x127 are analog registers; others are digital registers.
• For all unused GPIOs, corresponding “IE” must be set as 0.
• To use SD ADC pin function, please refer to the corresponding module section.

Datasheet for Telink TL3828 DS-TL3828-E5 248 Ver 0.8.0 0x80140cb7 RW [6:0]: function control bits of PA7_FS 0x00 0x80140cb8 RW [6:0]: function control bits of PB0_FS 0x00 0x80140cb9 RW [6:0]: function control bits of PB1_FS 0x00 0x80140cba RW [6:0]: function control bits of PB2_FS 0x00 0x80140cbb RW [6:0]: function control bits of PB3_FS 0x00 0x80140cbc RW [6:0]: function control bits of PB4_FS 0x00 0x80140cbd RW [6:0]: function control bits of PB5_FS 0x00 0x80140cbe RW [6:0]: function control bits of PB6_FS 0x00 0x80140cbf RW [6:0]: function control bits of PB7_FS 0x00 0x80140cc0 RW [6:0]: function control bits of PC0_FS 0x00 0x80140cc1 RW [6:0]: function control bits of PC1_FS 0x00 0x80140cc2 RW [6:0]: function control bits of PC2_FS 0x00 0x80140cc3 RW [6:0]: function control bits of PC3_FS 0x00 0x80140cc4 RW [6:0]: function control bits of PC4_FS 0x00 0x80140cc5 RW [6:0]: function control bits of PC5_FS 0x00 0x80140cc6 RW [6:0]: function control bits of PC6_FS 0x00 0x80140cc7 RW [6:0]: function control bits of PC7_FS 0x00 0x80140cc8 RW [6:0]: function control bits of PD0_FS 0x37 0x80140cc9 RW [6:0]: function control bits of PD1_FS 0x38 0x80140cca RW [6:0]: function control bits of PD2_FS 0x39 0x80140ccb RW [6:0]: function control bits of PD3_FS 0x3a 0x80140ccc RW [6:0]: function control bits of PD4_FS 0x29 0x80140ccd RW [6:0]: function control bits of PD5_FS 0x29 0x80140cce RW [6:0]: function control bits of PD6_FS 0x29 0x80140ccf RW [6:0]: function control bits of PD7_FS 0x29 0x80140cd0 RW [6:0]: function control bits of PE0_FS 0x00 0x80140cd1 RW [6:0]: function control bits of PE1_FS 0x00 0x80140cd2 RW [6:0]: function control bits of PE2_FS 0x00 Address Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 249 Ver 0.8.0 0x80140cd3 RW [6:0]: function control bits of PE3_FS 0x00 0x80140cd4 RW [6:0]: function control bits of PE4_FS 0x00 0x80140cd5 RW [6:0]: function control bits of PE5_FS 0x00 0x80140cd6 RW [6:0]: function control bits of PE6_FS 0x00 0x80140cd7 RW [6:0]: function control bits of PE7_FS 0x00 0x80140cd8 RW [6:0]: function control bits of PF0_FS 0x00 0x80140cd9 RW [6:0]: function control bits of PF1_FS 0x00 0x80140cda RW [6:0]: function control bits of PF2_FS 0x00 0x80140cdb RW [6:0]: function control bits of PF3_FS 0x00 0x80140cdc RW [6:0]: function control bits of PF4_FS 0x00 0x80140cdd RW [6:0]: function control bits of PF5_FS 0x00 0x80140cde RW [6:0]: function control bits of PF6_FS 0x00 0x80140cdf RW [6:0]: function control bits of PF7_FS 0x00 0x80140ce0 RW [6:0]: function control bits of PG0_FS 0x00 0x80140ce1 RW [6:0]: function control bits of PG1_FS 0x00 0x80140ce2 RW [6:0]: function control bits of PG2_FS 0x00 0x80140ce3 RW [6:0]: function control bits of PG3_FS 0x00 0x80140ce4 RW [6:0]: function control bits of PG4_FS 0x00 0x80140ce5 RW [6:0]: function control bits of PG5_FS 0x00 0x80140ce6 RW [6:0]: function control bits of PG6_FS 0x00 0x80140ce7 RW [6:0]: function control bits of PG7_FS 0x00 0x80140ce8 RW [6:0]: function control bits of PH0_FS 0x00 0x80140ce9 RW [6:0]: function control bits of PH1_FS 0x00 0x80140cea RW [6:0]: function control bits of PH2_FS 0x00 0x80140ceb RW [6:0]: function control bits of PH3_FS 0x00 0x80140cec RW [6:0]: function control bits of PH4_FS 0x00 0x80140ced RW [6:0]: function control bits of PH5_FS 0x00 0x80140cee RW [6:0]: function control bits of PH6_FS 0x00 Address Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 250 Ver 0.8.0

11.1.2.1 Multiplexed Functions

Each pin listed in Table 11-1 acts as the function in the “Default Function” column by default.

• PA[7] acts as SWS function by default.
• PD[0] acts as SSPI_CN function by default.
• PD[1] acts as SSPI_CK function by default.
• PD[2] acts as SSPI_SI function by default.
• PD[3] acts as SSPI_SO function by default.
• PD[4] acts as TDI function by default.
• PD[5] acts as TDO function by default.
• PD[6] acts as TMS function by default.
• PD[7] acts as TCK functi on by default.
• The other digital IOs act as GPIO function by default. If a pin with multiplexed functions does not act as GPIO function by default, to use it as GPIO, first set the bit in “Act as GPIO” column in as 1’b1. After GPIO function is enabled, if the pin is used as output, the bits “OE” columns should be set as 1’b1, then set the register value in the “Output” column; if the pin is used as input, the bits in “IE” columns should be set as 1’b1, and the input data can be read from the register in the “Input” column. To use a pin as certain multiplexed function (neither the default function nor GPIO function), first clear the bit in “Act as GPIO” column to disable GPIO function, and then configure “Register” column to enable multiplexed function correspondingly.

11.1.3 Drive Strength

The registers in the “DS0”, “DS1” and “SR” columns are used to configure the corresponding pin’s driving strength and slew rate. The “DS” configuration will take effect when the pin is used as output. It’s set as the strongest driving level by default. In actual applications, dri ving strength can be decreased to lower level if necessary . Table 11-5 Drive Strength 0x80140cef RW [6:0]: function control bits of PH7_FS 0x00 DS0 DS1 SR Drive strength (3.3 V) Slew rate 0 0 0 2 mA Fast 0 1 0 4 mA Fast 1 0 0 8 mA Fast 1 1 0 12 mA Fast 0 0 1 2 mA Slow Address Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 251 Ver 0.8.0

11.1.4 GPIO Logic Introduction

Figure 11-1 GPIO Logic Diagram In the figure above, 1. DS0/DS1/SR: drive strength and slew rate 2. OEN: output enable, 1: high Z; 0: output 3. O: output value, when OEN is 0, output this value 4. I: input value 5. IE: input enable, if IE is 0, C is always zero 6. 1M, 10K pull up and 100K pull down resistors are controlled by analog 3.3V register controller 0 1 1 4 mA Slow 1 0 1 8 mA Slow 1 1 1 12 mA Slow DS0 DS1 SR Drive strength (3.3 V) Slew rate VDD100K ohm OEN O I IE(reg_ana/reg_dig) DS0/DS1/SR(reg_ana/reg_dig) PAD Mux_I GPIO_OEN Mux_OEN GPIO_O Mux_O AS_GPIO GPIO_I 30K~70K ohm 1M ohm 10K ohm

Datasheet for Telink TL3828 DS-TL3828-E5 252 Ver 0.8.0

11.1.5 Connection Relationship between GPIO and Related Modules

GPIO can be used to generate GPIO interrupt signal for interrupt system, counting or control signal for Timer/ Counter module. For the “Exclusive Or (XOR)” operation result for input signal from any GPIO pin s and respective “Polarity” value. It takes “And” operation with “irq 0~7” and generates GPIO interrupt request signal (gpio_irq0~7_or). gpio_irq1 and gpio_irq2 also are counting signal in Mode 1 or control signal in Mode 2 for Timer0/Timer1.

• gpio_irq#n: GPIO interrupt request signal = | ((Input ^ Polarity) & IRQ#n), it is the interrupt request signal generated from GPIO;
• tim er0_irq: Counting (Mode 1) or control (Mode 2) signal for Timer0 = | ((Input ^ Polarity) & IRQ1), it is the interrupt request signal generated from GPIO, IRQ1 and Timer0;
• timer1_irq: Counting (Mode 1) or control (Mode 2) signal for Timer1 = | ((input ^ polarity) & IRQ2), it is the interrupt request signal generated from GPIO, IRQ2 and Timer1; The logic relationship is shown in figure below. NOTE:
• When PAD is set as functional IO, no need to configure GPIO_OEN as the functional IO will enable Mux- _OEN.
• When PAD is input, IE should be enabled regardless of functional IO or GPIO, and output to I, AS_GPIO is 1, Mux_I is 1.
• There are two methods to configure digital pull-up of 30k~70k ohm: º PC group and PD group (may vary for different chips), pad can configure analog register PE and enable digital pull-up. º Other group of pad, when GPIO_OEN=1 and GPIO_I=1, it enables digital pull-up.
• Analog pull-up has two options: 1M, 10k ohm; analog pull-down has only 100k ohm. They can be con- figured via corresponding analog registers.
• The GPIO configuration sequence should be: configure the MUX function, and then disable GPIO function. If disable GPIO first and then set function, the default function of the pad may be enabled and will cause false output level.

Datasheet for Telink TL3828 DS-TL3828-E5 254 Ver 0.8.0 signals take OR operation to get one gpio_irq#n_or signal. The output of this part is gpio_irq#n_or which is the 1 bit signal. Figure 11-4 Detailed Circuit for Part B For the detailed digital circuit of gpio_irq1_or ~ gpio_irq7_or, the operations are similar with the detailed circuit of part B.

11.1.6 GPIO Interrupt Signals

11.1.6.1 GPIO IRQ Signal

Select GPIO interrupt trigger edge (positive edge or negative edge) via configuring “Polarity”, and set corresponding GPIO interrupt enabling bit “Irq0 ~ Irq7”.

11.1.6.2 GPIO Interrupt Table

Pad Input Polarity irq0/irq1 irq2/irq3 irq4/irq5 irq6/irq7 PA[0] 0x80140c00[0] 0x80140c03[0] 0x80140d08[0]/ 0x80140d09[0] 0x80140d0a[0]/ 0x80140d0b[0] 0x80140d0c[0]/ 0x80140d0d[0] 0x80140d0e[0]/ 0x80140d0f[0] PA[1] 0x80140c00[1] 0x80140c03[1] 0x80140d08[1]/ 0x80140d09[1] 0x80140d0a[1]/ 0x80140d0b[1] 0x80140d0c[1]/ 0x80140d0d[1] 0x80140d0e[1]/ 0x80140d0f[1] PA[2] 0x80140c00[2] 0x80140c03[2] 0x80140d08[2]/ 0x80140d09[2] 0x80140d0a[2]/ 0x80140d0b[2] 0x80140d0c[2]/ 0x80140d0d[2] 0x80140d0e[2]/ 0x80140d0f[2] PA[3] 0x80140c00[3] 0x80140c03[3] 0x80140d08[3]/ 0x80140d09[3] 0x80140d0a[3]/ 0x80140d0b[3] 0x80140d0c[3]/ 0x80140d0d[3] 0x80140d0e[3]/ 0x80140d0f[3] PA[4] 0x80140c00[4] 0x80140c03[4] 0x80140d08[4]/ 0x80140d09[4] 0x80140d0a[4]/ 0x80140d0b[4] 0x80140d0c[4]/ 0x80140d0d[4] 0x80140d0e[4]/ 0x80140d0f[4] PA[5] 0x80140c00[5] 0x80140c03[5] 0x80140d08[5]/ 0x80140d09[5] 0x80140d0a[5]/ 0x80140d0b[5] 0x80140d0c[5]/ 0x80140d0d[5] 0x80140d0e[5]/ 0x80140d0f[5] IRQ0[0] B details gpio_irq0_p[63]IRQ0[63] gpio_p[63] gpio_irq0_p[62]IRQ0[62] gpio_p[62] gpio_irq0_p[0] gpio_p[0] gpio_irq0_or

Datasheet for Telink TL3828 DS-TL3828-E5 255 Ver 0.8.0 PA[6] 0x80140c00[6] 0x80140c03[6] 0x80140d08[6]/ 0x80140d09[6] 0x80140d0a[6]/ 0x80140d0b[6] 0x80140d0c[6]/ 0x80140d0d[6] 0x80140d0e[6]/ 0x80140d0f[6] PA[7] 0x80140c00[7] 0x80140c03[7] 0x80140d08[7]/ 0x80140d09[7] 0x80140d0a[7]/ 0x80140d0b[7] 0x80140d0c[7]/ 0x80140d0d[7] 0x80140d0e[7]/ 0x80140d0f[7] PB[0] 0x80140c10[0] 0x80140c13[0] 0x80140d18[0]/ 0x80140d19[0] 0x80140d1a[0]/ 0x80140d1b[0] 0x80140d1c[0]/ 0x80140d1d[0] 0x80140d1e[0]/ 0x80140d1f[0] PB[1] 0x80140c10[1] 0x80140c13[1] 0x80140d18[1]/ 0x80140d19[1] 0x80140d1a[1]/ 0x80140d1b[1] 0x80140d1c[1]/ 0x80140d1d[1] 0x80140d1e[1]/ 0x80140d1f[1] PB[2] 0x80140c10[2] 0x80140c13[2] 0x80140d18[2]/ 0x80140d19[2] 0x80140d1a[2]/ 0x80140d1b[2] 0x80140d1c[2]/ 0x80140d1d[2] 0x80140d1e[2]/ 0x80140d1f[2] PB[3] 0x80140c10[3] 0x80140c13[3] 0x80140d18[3]/ 0x80140d19[3] 0x80140d1a[3]/ 0x80140d1b[3] 0x80140d1c[3]/ 0x80140d1d[3] 0x80140d1e[3]/ 0x80140d1f[3] PB[4] 0x80140c10[4] 0x80140c13[4] 0x80140d18[4]/ 0x80140d19[4] 0x80140d1a[4]/ 0x80140d1b[4] 0x80140d1c[4]/ 0x80140d1d[4] 0x80140d1e[4]/ 0x80140d1f[4] PB[5] 0x80140c10[5] 0x80140c13[5] 0x80140d18[5]/ 0x80140d19[5] 0x80140d1a[5]/ 0x80140d1b[5] 0x80140d1c[5]/ 0x80140d1d[5] 0x80140d1e[5]/ 0x80140d1f[5] PB[6] 0x80140c10[6] 0x80140c13[6] 0x80140d18[6]/ 0x80140d19[6] 0x80140d1a[6]/ 0x80140d1b[6] 0x80140d1c[6]/ 0x80140d1d[6] 0x80140d1e[6]/ 0x80140d1f[6] PB[7] 0x80140c10[7] 0x80140c13[7] 0x80140d18[7]/ 0x80140d19[7] 0x80140d1a[7]/ 0x80140d1b[7] 0x80140d1c[7]/ 0x80140d1d[7] 0x80140d1e[7]/ 0x80140d1f[7] PC[0] 0x80140c20[0] 0x80140c23[0] 0x80140d28[0]/ 0x80140d29[0] 0x80140d2a[0]/ 0x80140d2b[0] 0x80140d2c[0]/ 0x80140d2d[0] 0x80140d2e[0]/ 0x80140d2f[0] PC[1] 0x80140c20[1] 0x80140c23[1] 0x80140d28[1]/ 0x80140d29[1] 0x80140d2a[1]/ 0x80140d2b[1] 0x80140d2c[1]/ 0x80140d2d[1] 0x80140d2e[1]/ 0x80140d2f[1] PC[2] 0x80140c20[2] 0x80140c23[2] 0x80140d28[2]/ 0x80140d29[2] 0x80140d2a[2]/ 0x80140d2b[2] 0x80140d2c[2]/ 0x80140d2d[2] 0x80140d2e[2]/ 0x80140d2f[2] PC[3] 0x80140c20[3] 0x80140c23[3] 0x80140d28[3]/ 0x80140d29[3] 0x80140d2a[3]/ 0x80140d2b[3] 0x80140d2c[3]/ 0x80140d2d[3] 0x80140d2e[3]/ 0x80140d2f[3] PC[4] 0x80140c20[4] 0x80140c23[4] 0x80140d28[4]/ 0x80140d29[4] 0x80140d2a[4]/ 0x80140d2b[4] 0x80140d2c[4]/ 0x80140d2d[4] 0x80140d2e[4]/ 0x80140d2f[4] PC[5] 0x80140c20[5] 0x80140c23[5] 0x80140d28[5]/ 0x80140d29[5] 0x80140d2a[5]/ 0x80140d2b[5] 0x80140d2c[5]/ 0x80140d2d[5] 0x80140d2e[5]/ 0x80140d2f[5] Pad Input Polarity irq0/irq1 irq2/irq3 irq4/irq5 irq6/irq7

Datasheet for Telink TL3828 DS-TL3828-E5 256 Ver 0.8.0 PC[6] 0x80140c20[6] 0x80140c23[6] 0x80140d28[6]/ 0x80140d29[6] 0x80140d2a[6]/ 0x80140d2b[6] 0x80140d2c[6]/ 0x80140d2d[6] 0x80140d2e[6]/ 0x80140d2f[6] PC[7] 0x80140c20[7] 0x80140c23[7] 0x80140d28[7]/ 0x80140d29[7] 0x80140d2a[7]/ 0x80140d2b[7] 0x80140d2c[7]/ 0x80140d2d[7] 0x80140d2e[7]/ 0x80140d2f[7] PD[0] 0x80140c30[0] 0x80140c33[0] 0x80140d38[0]/ 0x80140d39[0] 0x80140d3a[0]/ 0x80140d3b[0] 0x80140d3c[0]/ 0x80140d3d[0] 0x80140d3e[0]/ 0x80140d3f[0] PD[1] 0x80140c30[1] 0x80140c33[1] 0x80140d38[1]/ 0x80140d39[1] 0x80140d3a[1]/ 0x80140d3b[1] 0x80140d3c[1]/ 0x80140d3d[1] 0x80140d3e[1]/ 0x80140d3f[1] PD[2] 0x80140c30[2] 0x80140c33[2] 0x80140d38[2]/ 0x80140d39[2] 0x80140d3a[2]/ 0x80140d3b[2] 0x80140d3c[2]/ 0x80140d3d[2] 0x80140d3e[2]/ 0x80140d3f[2] PD[3] 0x80140c30[3] 0x80140c33[3] 0x80140d38[3]/ 0x80140d39[3] 0x80140d3a[3]/ 0x80140d3b[3] 0x80140d3c[3]/ 0x80140d3d[3] 0x80140d3e[3]/ 0x80140d3f[3] PD[4] 0x80140c30[4] 0x80140c33[4] 0x80140d38[4]/ 0x80140d39[4] 0x80140d3a[4]/ 0x80140d3b[4] 0x80140d3c[4]/ 0x80140d3d[4] 0x80140d3e[4]/ 0x80140d3f[4] PD[5] 0x80140c30[5] 0x80140c33[5] 0x80140d38[5]/ 0x80140d39[5] 0x80140d3a[5]/ 0x80140d3b[5] 0x80140d3c[5]/ 0x80140d3d[5] 0x80140d3e[5]/ 0x80140d3f[5] PD[6] 0x80140c30[6] 0x80140c33[6] 0x80140d38[6]/ 0x80140d39[6] 0x80140d3a[6]/ 0x80140d3b[6] 0x80140d3c[6]/ 0x80140d3d[6] 0x80140d3e[6]/ 0x80140d3f[6] PD[7] 0x80140c30[7] 0x80140c33[7] 0x80140d38[7]/ 0x80140d39[7] 0x80140d3a[7]/ 0x80140d3b[7] 0x80140d3c[7]/ 0x80140d3d[7] 0x80140d3e[7]/ 0x80140d3f[7] PE[0] 0x80140c40[0] 0x80140c43[0] 0x80140d48[0]/ 0x80140d49[0] 0x80140d4a[0]/ 0x80140d4b[0] 0x80140d4c[0]/ 0x80140d4d[0] 0x80140d4e[0]/ 0x80140d4f[0] PE[1] 0x80140c40[1] 0x80140c43[1] 0x80140d48[1]/ 0x80140d49[1] 0x80140d4a[1]/ 0x80140d4b[1] 0x80140d4c[1]/ 0x80140d4d[1] 0x80140d4e[1]/ 0x80140d4f[1] PE[2] 0x80140c40[2] 0x80140c43[2] 0x80140d48[2]/ 0x80140d49[2] 0x80140d4a[2]/ 0x80140d4b[2] 0x80140d4c[2]/ 0x80140d4d[2] 0x80140d4e[2]/ 0x80140d4f[2] PE[3] 0x80140c40[3] 0x80140c43[3] 0x80140d48[3]/ 0x80140d49[3] 0x80140d4a[3]/ 0x80140d4b[3] 0x80140d4c[3]/ 0x80140d4d[3] 0x80140d4e[3]/ 0x80140d4f[3] PE[4] 0x80140c40[4] 0x80140c43[4] 0x80140d48[4]/ 0x80140d49[4] 0x80140d4a[4]/ 0x80140d4b[4] 0x80140d4c[4]/ 0x80140d4d[4] 0x80140d4e[4]/ 0x80140d4f[4] PE[5] 0x80140c40[5] 0x80140c43[5] 0x80140d48[5]/ 0x80140d49[5] 0x80140d4a[5]/ 0x80140d4b[5] 0x80140d4c[5]/ 0x80140d4d[5] 0x80140d4e[5]/ 0x80140d4f[5] Pad Input Polarity irq0/irq1 irq2/irq3 irq4/irq5 irq6/irq7

Datasheet for Telink TL3828 DS-TL3828-E5 257 Ver 0.8.0 PE[6] 0x80140c40[6] 0x80140c43[6] 0x80140d48[6]/ 0x80140d49[6] 0x80140d4a[6]/ 0x80140d4b[6] 0x80140d4c[6]/ 0x80140d4d[6] 0x80140d4e[6]/ 0x80140d4f[6] PE[7] 0x80140c40[7] 0x80140c43[7] 0x80140d48[7]/ 0x80140d49[7] 0x80140d4a[7]/ 0x80140d4b[7] 0x80140d4c[7]/ 0x80140d4d[7] 0x80140d4e[7]/ 0x80140d4f[7] PF[0] 0x80140c50[0] 0x80140c53[0] 0x80140d58[0]/ 0x80140d59[0] 0x80140d5a[0]/ 0x80140d5b[0] 0x80140d5c[0]/ 0x80140d5d[0] 0x80140d5e[0]/ 0x80140d5f[0] PF[1] 0x80140c50[1] 0x80140c53[1] 0x80140d58[1]/ 0x80140d59[1] 0x80140d5a[1]/ 0x80140d5b[1] 0x80140d5c[1]/ 0x80140d5d[1] 0x80140d5e[1]/ 0x80140d5f[1] PF[2] 0x80140c50[2] 0x80140c53[2] 0x80140d58[2]/ 0x80140d59[2] 0x80140d5a[2]/ 0x80140d5b[2] 0x80140d5c[2]/ 0x80140d5d[2] 0x80140d5e[2]/ 0x80140d5f[2] PF[3] 0x80140c50[3] 0x80140c53[3] 0x80140d58[3]/ 0x80140d59[3] 0x80140d5a[3]/ 0x80140d5b[3] 0x80140d5c[3]/ 0x80140d5d[3] 0x80140d5e[3]/ 0x80140d5f[3] PF[4] 0x80140c50[4] 0x80140c53[4] 0x80140d58[4]/ 0x80140d59[4] 0x80140d5a[4]/ 0x80140d5b[4] 0x80140d5c[4]/ 0x80140d5d[4] 0x80140d5e[4]/ 0x80140d5f[4] PF[5] 0x80140c50[5] 0x80140c53[5] 0x80140d58[5]/ 0x80140d59[5] 0x80140d5a[5]/ 0x80140d5b[5] 0x80140d5c[5]/ 0x80140d5d[5] 0x80140d5e[5]/ 0x80140d5f[5] PF[6] 0x80140c50[6] 0x80140c53[6] 0x80140d58[6]/ 0x80140d59[6] 0x80140d5a[6]/ 0x80140d5b[6] 0x80140d5c[6]/ 0x80140d5d[6] 0x80140d5e[6]/ 0x80140d5f[6] PF[7] 0x80140c50[7] 0x80140c53[7] 0x80140d58[7]/ 0x80140d59[7] 0x80140d5a[7]/ 0x80140d5b[7] 0x80140d5c[7]/ 0x80140d5d[7] 0x80140d5e[7]/ 0x80140d5f[7] PG[0] 0x80140c60[0] 0x80140c63[0] 0x80140d68[0]/ 0x80140d69[0] 0x80140d6a[0]/ 0x80140d6b[0] 0x80140d6c[0]/ 0x80140d6d[0] 0x80140d6e[0]/ 0x80140d6f[0] PG[1] 0x80140c60[1] 0x80140c63[1] 0x80140d68[1]/ 0x80140d69[1] 0x80140d6a[1]/ 0x80140d6b[1] 0x80140d6c[1]/ 0x80140d6d[1] 0x80140d6e[1]/ 0x80140d6f[1] PG[2] 0x80140c60[2] 0x80140c63[2] 0x80140d68[2]/ 0x80140d69[2] 0x80140d6a[2]/ 0x80140d6b[2] 0x80140d6c[2]/ 0x80140d6d[2] 0x80140d6e[2]/ 0x80140d6f[2] PG[3] 0x80140c60[3] 0x80140c63[3] 0x80140d68[3]/ 0x80140d69[3] 0x80140d6a[3]/ 0x80140d6b[3] 0x80140d6c[3]/ 0x80140d6d[3] 0x80140d6e[3]/ 0x80140d6f[3] PG[4] 0x80140c60[4] 0x80140c63[4] 0x80140d68[4]/ 0x80140d69[4] 0x80140d6a[4]/ 0x80140d6b[4] 0x80140d6c[4]/ 0x80140d6d[4] 0x80140d6e[4]/ 0x80140d6f[4] PG[5] 0x80140c60[5] 0x80140c63[5] 0x80140d68[5]/ 0x80140d69[5] 0x80140d6a[5]/ 0x80140d6b[5] 0x80140d6c[5]/ 0x80140d6d[5] 0x80140d6e[5]/ 0x80140d6f[5] Pad Input Polarity irq0/irq1 irq2/irq3 irq4/irq5 irq6/irq7

Datasheet for Telink TL3828 DS-TL3828-E5 258 Ver 0.8.0

11.1.7 GPIO Interrupt Configuration Process

The GPIO_IRQ0~7 interrupt configuration process is as follows: Step 1 Set the “Act as GPIO” register of the corresponding pin to 1 to configure the pin for GPIO function. For example, set PA0 to GPIO function: 0x80140c06[0] = 1'b1. Step 2 Configure the pull-up and pull-down function of the pin according to the trigger types: if it is triggered by high level/rising edge, configure the pin to pull down; if it is triggered by low level/falling edge, configure the pin to pull up, and enable the i nput function at the same time. For example, set PA0 to 1M ohm pull up: AFE_0X17[1:0] = 2'b01; enable the input function of PA0: 0x80140c01 [0] = 1'b1. Step 3 Set IRQ0~7 of the pin to 1. For example, set PA0 as IRQ0 interrupt: 0x80140d08[0] = 1'b1. Step 4 Configure gpio_irq0_lvl_mode (GPIO_IRQ_LVL_MODE[0]) and the corresponding Polarity of the pins according to the trigger types. For example, set PA0 as a ri sing edge interrupt: 0x80140c03[0]=1'b0, Step 5 Set IRQ_CTRL1 to 1 (0x80140d02[1]=1'b1) If it is an IRQ0 interrupt. If it is a IRQ1~7 interrupt, there is no need to configure. PG[6] 0x80140c60[6] 0x80140c63[6] 0x80140d68[6]/ 0x80140d69[6] 0x80140d6a[6]/ 0x80140d6b[6] 0x80140d6c[6]/ 0x80140d6d[6] 0x80140d6e[6]/ 0x80140d6f[6] PG[7] 0x80140c60[7] 0x80140c63[7] 0x80140d68[7]/ 0x80140d69[7] 0x80140d6a[7]/ 0x80140d6b[7] 0x80140d6c[7]/ 0x80140d6d[7] 0x80140d6e[7]/ 0x80140d6f[7] PH[0] 0x80140c70[0] 0x80140c73[0] 0x80140d78[0]/ 0x80140d79[0] 0x80140d7a[0]/ 0x80140d7b[0] 0x80140d7c[0]/ 0x80140d7d[0] 0x80140d7e[0]/ 0x80140d7f[0] PH[1] 0x80140c70[1] 0x80140c73[1] 0x80140d78[1]/ 0x80140d79[1] 0x80140d7a[1]/ 0x80140d7b[1] 0x80140d7c[1]/ 0x80140d7d[1] 0x80140d7e[1]/ 0x80140d7f[1] PH[2] 0x80140c70[2] 0x80140c73[2] 0x80140d78[2]/ 0x80140d79[2] 0x80140d7a[2]/ 0x80140d7b[2] 0x80140d7c[2]/ 0x80140d7d[2] 0x80140d7e[2]/ 0x80140d7f[2] PH[3] 0x80140c70[3] 0x80140c73[3] 0x80140d78[3]/ 0x80140d79[3] 0x80140d7a[3]/ 0x80140d7b[3] 0x80140d7c[3]/ 0x80140d7d[3] 0x80140d7e[3]/ 0x80140d7f[3] PH[4] 0x80140c70[4] 0x80140c73[4] 0x80140d78[4]/ 0x80140d79[4] 0x80140d7a[4]/ 0x80140d7b[4] 0x80140d7c[4]/ 0x80140d7d[4] 0x80140d7e[4]/ 0x80140d7f[4] PH[5] 0x80140c70[5] 0x80140c73[5] 0x80140d78[5]/ 0x80140d79[5] 0x80140d7a[5]/ 0x80140d7b[5] 0x80140d7c[5]/ 0x80140d7d[5] 0x80140d7e[5]/ 0x80140d7f[5] PH[6] 0x80140c70[6] 0x80140c73[6] 0x80140d78[6]/ 0x80140d79[6] 0x80140d7a[6]/ 0x80140d7b[6] 0x80140d7c[6]/ 0x80140d7d[6] 0x80140d7e[6]/ 0x80140d7f[6] PH[7] 0x80140c70[7] 0x80140c73[7] 0x80140d78[7]/ 0x80140d79[7] 0x80140d7a[7]/ 0x80140d7b[7] 0x80140d7c[7]/ 0x80140d7d[7] 0x80140d7e[7]/ 0x80140d7f[7] Pad Input Polarity irq0/irq1 irq2/irq3 irq4/irq5 irq6/irq7

Datasheet for Telink TL3828 DS-TL3828-E5 259 Ver 0.8.0 Step 6 Clear the corresponding interrupt trigger flag bit in GPIO_IRQ_STATUS (write 1 to clear), this is a necessary operation, otherwise an interrupt will be triggered by mistake, and this flag in the interrupt handler function also needs to be manually set to 1. Step 7 Set the register IRQ_CTRL to enable the corresponding mask. For example, set the pin as IRQ0 interrupt: 0x80140d06[0]=1'b1. Step 8 Enable pli c correspondence bit. Step 9 Enable the general interrupt.

11.1.8 GPIO Interrupt Considerations

11.1.8.1 Mechanism

As shown in the figure below, the GPIO is set to trigger at rising edge. The mechanism of MCU is that the level signal of GPIO is used as the signal to generate interrupt and trigger the interrupt at rising edge. Figure 11-5 GPIO Set to Trigger at Rising Edge As shown in the figure below, the GPIO is set to trigger at falling edge. The mechanism of MCU is to i nvert the level signal of GPIO and then use the inverted signal as the signal for interrupt generation, and trigger the interrupt at rising edge. Figure 11-6 GPIO Set to Trigger at Falling Edge As shown in the figure below, if two GPIOs are set as one kind of interrupt, trigger at rising edge, the mechanism of MCU is that the level signal of two GPIOs will be or operation, and then use the obtained signal

Datasheet for Telink TL3828 DS-TL3828-E5 261 Ver 0.8.0 That is, finally MCU is using the final signal to trigger the interrupt at rising edge. In the figure, only GPIO1 triggers the interrupt. Figure 11-9 GPIO0 Set Trigger at Rising Edge, GPIO1 Set Trigger at Falling Edge

11.1.8.2 Conclusion

Two or more GPIOs set as one kind of interrupt, depending on the timing of input GPIO, triggering interrupts is uncertain and not recommended. However, the mechanisms of different GPIO interrupts are independent of each other. If one GPIO i s set to one kind of interrupt, the interrupts of both GPIOs can be triggered.

11.1.8.3 Attentions

If setting the trigger type as high or trigger at rising edge, pull-down resistor should be set; if setting the trigger type as low or trigger at falling edge, pull-up resistor should be set. When setting trigger at falling edge, you need to clear the interrupt bit after setting the polarity of GPIO, and then enable mask. Otherwi se, when setting GPIO to trigger at falling edge, a non-falling edge caused interrupt trigger is generated at the moment of enabling GPIO interrupt.

11.1.9 GPIO Interrupt Related Registers

The GPIO interrupt related registers are listed as following, the base address of the following registers is 0x80140C00. Table 11-7 GPIO Interrupt Related Registers Address Offset Name Type Description Reset Value 0x102 IRQ_CTRL RW [0]: r_wakeup_en 1: enable, 0: disable, use in suspend mode [1]: r_irq_en 1: gpio irq enable, 0: gpio irq disable [4]: r_pem_event_en 0x00

Datasheet for Telink TL3828 DS-TL3828-E5 262 Ver 0.8.0

11.1.10 Pull-up/Pull-down Resistors

All GPIOs support configurable pull-up resistor of rank x1 and x100 or pull-down resistor of rank x10 which are all disabled by default. 0x104 GPIO_IRQ_LVL_MODE RW [7:0]: gpio_irq_lvl_mode 0: edge trigger 1: level trigger There are four triggering methods for GPIO_IRQ can be configured by setting this bit and the polarity bit of the corresponding pin. RISING_EDGE: polarity: 0, irq_lvl_gpio_irq to: 0 FALLING_EDGE: polarity: 1, irq_lvl_gpio_irq to: 0 HIGH_EDGE: polarity: 0, irq_lvl_gpio_irq to: 1 LOW_EDGE: polarity: 1, irq_lvl_gpio_irq to: 1 0x00 0x105 GPIO_IRQ_STATUS W1C GPIO_IRQ_status Interrupt flag bit, which will be automatically set by hardware to 1 when an interrupt occurs, user needs to manually write 1 to clear flag status. [0]: gpio_irq0_status [1]: gpio_irq1_status [2]: gpio_irq2_status [3]: gpio_irq3_status [4]: gpio_irq4_status [5]: gpio_irq5_status [6]: gpio_irq6_status [7]: gpio_irq7_status 0x00 0x106 GPIO_IRQ_MASK RW 1:enable,0:disable [0]: gpio_irq0_mask [1]: gpio_irq1_mask [2]: gpio_irq2_mask [3]: gpio_irq3_mask [4]: gpio_irq4_mask [5]: gpio_irq5_mask [6]: gpio_irq6_mask [7]: gpio_irq7_mask 0x00 Address Offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 263 Ver 0.8.0 Analog registers afe_0x17<7:0> ~ afe_0x26<5:0> serve to control the pull-up/pull-down resistor for each GPIO, as shown in table below. Table 11-8 Analog Registers for Pull-up/Pull-down Resistor Control Address Type Description Default Value 0x17 R/W GPIO_A<3:0> pull up and down select: 00: Null 01: 1M pull up 10: 100K pull down 11: 10K pull up 00000000 0x18 R/W GPIO_A<7:4> pull up and down select: 00: Null 01: 1M pull up 10: 100K pull down 11: 10K pull up 00000000 0x19 R/W GPIO_B<3:0> pull up and down select: 00: Null 01: 1M pull up 10: 100K pull down 11: 10K pull up 00000000 0x1a R/W GPIO_B<7:4> pull up and down select: 00: Null 01: 1M pull up 10: 100K pull down 11: 10K pull up 00000000 0x1b R/W GPIO_C<3:0> pull up and down select: 00: Null 01: 1M pull up 10: 100K pull down 11: 10K pull up 00000000 NOTE: The GPIO pull-up/pull-down resistance is a simulation result by the internal MOSFET and affected by the IO voltage VDDO3. The lower the IO voltage of GPIO, the higher the pull-up/pull-down resistance of GPIO.

Datasheet for Telink TL3828 DS-TL3828-E5 264 Ver 0.8.0 0x1c R/W GPIO_C<7:4> pull up and down select: 00: Null 01: 1M pull up 10: 100K pull down 11: 10K pull up 00000000 0x1d R/W GPIO_D<3:0> pull up and down select: 00: Null 01: 1M pull up 10: 100K pull down 11: 10K pull up 00000000 0x1e R/W GPIO_D<7:4> pull up and down select: 00: Null 01: 1M pull up 10: 100K pull down 11: 10K pull up 00000000 0x1f R/W GPIO_E<3:0> pull up and down select: 00: Null 01: 1M pull up 10: 100K pull down 11: 10K pull up 00000000 0x20 R/W GPIO_E<7:4> pull up and down select: 00: Null 01: 1M pull up 10: 100K pull down 11: 10K pull up 00000000 0x21 R/W GPIO_F<3:0> pull up and down select: 00: Null 01: 1M pull up 10: 100K pull down 11: 10K pull up 00000000 Address Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 265 Ver 0.8.0

11.1.11 GPIO Driving LED Description

The LED for RGB (Red, Green, Blue) can be driven by GPIO, the application principle is as follows. 1. Through the three states of output high / output low / input high resistance of the GPIO to drive the LED on and off respectively (no simultaneous bright state); 2. Control LED brightness by 2 resistors. 0x22 R/W GPIO_F<7:4> pull up and down select: 00: Null 01: 1M pull up 10: 100K pull down 11: 10K pull up 00000000 0x23 R/W GPIO_G<3:0> pull up and down select: 00: Null 01: 1M pull up 10: 100K pull down 11: 10K pull up 00000000 0x24 R/W GPIO_G<7:4> pull up and down select: 00: Null 01: 1M pull up 10: 100K pull down 11: 10K pull up 00000000 0x25 R/W GPIO_H<3:0> pull up and down select: 00: Null 01: 1M pull up 10: 100K pull down 11: 10K pull up 00000000 0x26 R/W GPIO_H<7:4> pull up and down select: 00: Null 01: 1M pull up 10: 100K pull down 11: 10K pull up 00000000 Address Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 266 Ver 0.8.0 Figure 11-10 One GPIO drives two LEDs

11.2 Swire

The SoC supports Single Wire Slave interface. SWM (Single Wire Master) and SWS (Single Wire Slave) represent the master and slave device of the single wire communication system developed by Telink. The maximum data rate can be up to 2 Mbps. SWS usage is not supported in power-saving mode (deep sleep or suspend). SWS related registers are listed as following, the base address of the followi ng registers is 0x80100C00. Table 11-9 Swire Related Registers Address Offset Name Type Description Default Value 0x00 SWIRE_DATA R [7:0]: swire_data 0x00 0x01 SWIRE_CTL RW [0]: swire_wr [1]: swire_rd [2]: swire_cmd [3]: swire_err_flag [4]: swire_eop [6]: swire_usb_det [7]: swire_usb_en 0x80 0x02 SWIRE_CTL2 RW [6:0]: swire_clk_div 0x05 0x03 SWIRE_ID RW [4:0]: id_valid [7]: fifo_mode 0x00 LED1 LED2 VDD_IO VDD(3V3)

Datasheet for Telink TL3828 DS-TL3828-E5 267 Ver 0.8.0

11.3 JTAG and SDP

This SoC has debug interfaces of JTAG and SDP. JTAG (Joint Test Action Group) is an interface used for debugging and programming the chip, and it includes four wires (TDI, TDO, TMS and TCK) for this SoC. SDP is a two-wire serial debug interface, which is multiplexed with TCK and TMS. The specific GPIOs used as JTAG and SDP can be referred to the Table 11-1 GPIO Pad Function Mux. The bootstrap pi n for switching between JTAG and SDP is PB[0] with the following definition:

• PB[0] is high (with pull-up): SDP is enabled;
• PB[0] is low (with pull-down): JTAG is enabled. When power on after wake up from deep sleep mode, the SoC will read the voltage level of bootstrap pin and decide the debug port. This bootstrap pin cannot be modified through the init process or register.

11.4 Inter-Integrated Circuit (I2C)

11.4.1 Introduction

The SoC embeds I2C to i mplement half-duplex transmission and reception via I2C SDA (serial data line) and SCL (serial clock line) interface. It can be configured to transmit or receive data as master or slave. The I2C1M can only be configured as the master. Each device is recognized by a unique address (ID). Master device is the device which initiates a data transfer on the bus and generates the clock si gnals to permit that transfer. Slave device is the device addressed via a Master. The I2C and I2C1M restriction is that pclk must be at least 10x of data rate. The I2C features include:

• Supports Standard-mode (100 kbps), Fast-mode (400 kbps) and Fast-mode Plus (1 Mbps)
• Half-duplex operation
• Supports models: Master transmitter, Master receiver, Slave transmitter and Slave receiver
• Supports 7-bit addressi ng mode
• Supports general call address
• Auto clock stretching
• 8 bytes of transmit/receive FIFOs
• Supports DMA function (RX supports DMA Linked List Pointer)
• 2 x I2C (I2C/I2C1M, The I2C1M supports only the master)

11.4.2 Block Diagram

The following features show the block diagram of I2C and I2C1M respectively.

Datasheet for Telink TL3828 DS-TL3828-E5 268 Ver 0.8.0 Figure 11-11 I2C Block Diagram Figure 11-12 I2C1M Block Diagram

11.4.3 Function Description

11.4.3.1 Pin Configuration

The I2C bidirectional communications require a minimum of two pins: SDA (serial data line) and SCL (serial clock line): The two wires, SDA and SCL carry information between Master device and Slave device connected to the bus. Both SDA and SCL are bidirectional lines connected to a positive supply voltage via a pull-up resister. It’s

Datasheet for Telink TL3828 DS-TL3828-E5 269 Ver 0.8.0 recommended to use external 3.3 kOhm pull-up resistor. For standard mode, the internal pull-up resistor of rank x1 can be used instead of the external 3.3 kOhm pull-up. When the bus is released, both lines are HIGH. It is noted that the data on the SDA line must be stable during the high period of the clock (SCL), and the high or low state of the data line can only change when the clock signal on the SCL li ne is low. Figure 11-13 I2C Bus Protocol

11.4.3.2 I2C Master Mode

Register I2CSCT0[1] should be set to 1’b1 to enable I2C master mode. Register I2CSP sets I2C Master clock: FI2C = (pclk / (4 *clock speed configured in register I2CSP). A complete I2C protocol contains START, Slave Address, R/W bit, data, ACK and STOP. Slave address could be configured via I2C_ID (address 0x01) [7:1]. I2C Master could send START, Slave Address, R/W bit, data and STOP cycle by configuring I2CSCT1. The state machi ne starts running and transfer data in the correct sequence. Register I2CMST serves to indicate whether Master/Master packet is busy, as well as Master received status. Bit[0] will be set to 1 when other states are running except IDLE, and the bit can be automatically cleared after a start signal/ address byte/acknowledge signal/data /stop signal is sent. Bit[1] is set to 1 when the start condition si gnal is sent, and the bit will be automatically cleared after the stop condition signal is sent. Bit[2] indicates whether the response was successful.

Datasheet for Telink TL3828 DS-TL3828-E5 270 Ver 0.8.0 Figure 11-14 I2C Master State The controller (Master state) provides an efficient way to initiate I2C transactions. Every transaction can be delineated by four phases: Start, Address, Data and Stop. At the Start phase, a START condition is generated. At the Address phase, an address is sent. At the Data phase, one or more data bytes are transferred. At the Stop phase, a STOP condition is generated. The existence of each phase can be controlled i ndependently.

11.4.3.3 I2C Slave Mode

I2C module acts as Slave mode by default. I2C slave address can be configured via register I2C_ID (address 0x01) [7:1], as shown below. Figure 11-15 Byte Consisted of Slave Address and R/W Flag Bit I2C slave mode supports two sub modes including Direct Memory Access (DMA) mode and No Direct Memory Access (NDMA). In I2C Slave mode, Master could initiate transaction anytime. I2C slave module will reply wit h ACK automati cally. To monitor the start of I2C transaction, user could set interrupt from GPIO for SDA or SCL. Read and write format of Slave modes are shown as below.

Datasheet for Telink TL3828 DS-TL3828-E5 271 Ver 0.8.0 Figure 11-16 Read Format in Slave Mode Figure 11-17 Write Format in Slave Mode DMA and NDMA access buffer through DMA and APB, respectively. Figure 11-18 I2C Slave State The controller is addressed when the address byte of an I2C transaction matches the Address Register I2C_ID. An ss_rw_irq interrupt can be generated for the software to prepare for the subsequent operations. Note: The address match of the chip needs to be optimized. The I2C slave replies ACK if the ID matches, But the data i s still stored to the RX FIFO, and an interrupt is asserted. If one master corresponds to multiple slave applications, the recommended solution for I2C slave is as follows:

• If the PAD is sufficient, select a pad as our slave indicator signal, read the status through GPIO. We will deal with I2C interrupt or configure DMA when the PAD is pulled up.
• If the PAD is not enough, we can only modi fy the communication protocol, and the Master needs to send another data as the software ID, and deal with I2C interrupt or configure DMA when the software ID is received.

11.4.3.4 I2C Master Transmitter

(1) NDMA Operation The transmitter comprises a Transmitter FIFO (TX FIFO), a Transmitter Shift, and a Controller (Master controller). The TX FIFO holds data to be transferred through the serial interface. The TX FIFO can store up to 8 characters dependi ng on hardware configurations and programming settings. The user can determine whether the pointer of the current TX FIFO is less than 8 via the register I2C_BUFCNT[7:4], if less than 8, continue to fill the data to TX FIFO until the end of sending. The Transmitter Shift reads a character from the DATA ACK 8 bits START ID R 8 bits ACK NAK STOP START ID W 8 bits ACK DATA ACK STOP 8 bits

Datasheet for Telink TL3828 DS-TL3828-E5 272 Ver 0.8.0 TX FIFO for the next transmission. The Transmitter Shift functions as a parallel-to-serial data converter, converting the outgoing character to serial bit streams. For each character transmission, the Controller generates a START bit, some number of Slave address bits, some number of data bits, and a STOP bit. The TX FIFO is by default a 8-byte buffer called Transmitter Buffer Regi ster. For example, to implement an I2C write transfer with 4-byte data, which contains START, Slave Address (ID), Write bit, ACK from Slave, 1st byte, ACK from slave, 2nd byte, ACK from slave, 3rd byte, ACK from slave,4th byte, ACK from slave and STOP. User needs to configure I2C slave address to I2C_ID[7:1]. To start I2C write transfer, After the register I2CSCT1 is configured to 0x11 (0001 0001 ), I2C Master wi ll launch START, Slave address (ID). The data to TX FIFO and register I2CSCT1 is configured to 0x24 (0000 0024), I2C Master will send TX FIFO data, load ACK to I2CMST[2] and then STOP sequentially. Note: Address state is optional. (2) DMA Operation When the TX FIFO under the threshold 4 characters, the master controller will assert dma_tx_req to request a data transfer. The DMA controller should then transfer data to the TX FIFO followed by asserti ng dma_tx_ack. Next, the master controller de-asserts dma_tx_req and the DMA controller de-asserts dma_tx_ack. The master controller will assert dma_tx_req again unless the TX FIFO is full or the DMA transmission length is reached. For example, The data to be sent is put into SRAM, set the TX DMA configuration (For details about TX DMA configurati on, refer to the DMA chapter), DMA transfers 4 bytes of data to TX FIFO at a time. User needs to configure I2C slave address to I2C_ID[7:1]. After the register I2CSCT1 is configured to 0x11 (0001 0001), I2C Master will launch START and Slave address. Register I2CSCT1 is configured to 0x24 (0000 0024), I2C Master will send TX FIFO data, load ACK to I2CMST[2], and then STOP sequentially. I2C supports a si ngle write of maximum length supported for a single DMA transfer.

11.4.3.5 I2C Master Receiver

(1) NDMA Operation The receiver comprises a Receiver FIFO (RX FIFO), Receiver Shift, and a Controller (Master Controller). The received bits are shifted into the Receiver Shift for serial-to-parallel data conversion and the received character is stored into the RX FIFO. The RX FIFO is by default a 8byte buffer called the Receiver Buffer Regi ster. The user can via the register I2C_BUFCNT[3:0] to determine whether the pointer to the current RX FIFO is greater than 0, and if it is greater than 0, the data can be read until the end of receiving. For example, to implement an I2C read transfer with 4 byte data, which contains START, Slave Address (ID), Read bit, Ack from Slave, 4 byte data from Slave, Ack from master and STOP. User needs to confi gure I2C slave address to I2C_ID [7:1]. To start I2C read transfer, After the register I2CSCT1 is configured to 0x79 (0111 1001), I2C Master will launch START, Slave address (ID), Read bit, load ACK to I2CMST [2], load data to RX FIFO, reply ACK and then STOP sequentially. Note: Address state is optional. (2) DMA Operation When the RX FIFO reaches the threshold 4 characters, the master controller wi ll assert dma_rx_req to request a data transfer. The DMA controller should then transfer data from the RX FIFO followed by asserting dma_rx_ack. Next, the controller de-asserts dma_rx_req and the DMA controller de-asserts dma_rx_ack. The controller will assert dma_rx_req again unless the RX FIFO is empty. DMA relies on rxdone to read parts of the data below 4 characters.

Datasheet for Telink TL3828 DS-TL3828-E5 273 Ver 0.8.0 For example, set the RX DMA configuration (For details about RX DMA configuration, refer to the DMA chapter), user needs to configure I2C slave address to I2C_ID[7:1]. After the register I2CSCT1 is configured to 0x79 (0111 1001), I2C Master will launch START, Slave address, Read bit, load ACK to I2CMST [2], load data to RX FIFO, reply ACK and then STOP sequentially. I2C supports a si ngle read of maximum length supported for a single DMA transfer.

11.4.3.6 I2C Slave Transmitter/Receiver

The operating principle of I2C Slave and Master is similar, the difference is that the Master mode can control the transmission time, But slave mode needs to be ready at any time. Whether to use the stretch function(I2CCTRL3[0] and I2C_IRQ_STATUS[0]) in the I2C slave mode can be used in two ways:

• If stretch function is used (the master must support stretch functi on), the slave can determine the R/W bit of the master and corresponding operations.
• If stretch function is not used, the slave needs to fill data or configure DMA in advance when sending data and configure DMA in advance when receiving data.

11.4.3.7 General Call Address

The General Call Address is a special address to address all slave devices on the I2C-bus. The controller at the slave mode wi ll respond with an ACK to the general call address and set the ID field of the I2C_ID Register.

11.4.3.8 I2C Master Restart

The I2C master supports the restart function. After data transmission is complete, start can be sent instead of stop for the next data transmission. Figure 11-19 I2C Master Restart Condition

11.4.3.9 Auto Clock Stretch

(1) Slave Stretch Clock stretching pauses a transaction by holding the SCL Line LOW. The I2C can automatically pause bus transactions by stretching clocks on the I2C-bus when the software i s not ready for the next byte of data or when the RX FIFO is full or the TX FIFO is empty. When configuring register I2CCTRL3[0], Auto Clock Stretch is supported at the slave mode. (2) Master Stretch When configuring register I2CCTRL2[1], The master transaction cannot continue until the line is released high again.

Datasheet for Telink TL3828 DS-TL3828-E5 274 Ver 0.8.0

11.4.3.10 Auto-ACK

With Auto-ACK, the I2C automatically generates proper acknowledgements for each byte received. Every received byte will be responded with an ACK, except for the last byte, which should be responded with a NAK according to the I2C-bus protocol. On the other hand, if the software needs to determine last byte acknowledgement status, Auto-NAK can be turned off by disabling the resi ster I2CCTRL3[2]. The interrupt I2C_IRQ_STATUS[1] and register I2CSCT2[4] are used for the master. When the master detects nak, it will send a stop condition to end the current data transmission. In master mode and DMA is used to send data. The following processing needs to be done when NAK is detected: Disable DMA and clear TX FIFO (I2C_IRQ_STATUS[3])

11.4.4 Register Description of I2C

The I2C related registers are listed as followi ng, the base address of the following registers is 0x80140280. Table 11-10 I2C Related Registers Offset Name Type Description Defaul t Value 0x00 I2CSP RW I2C master clock speed: pclk*1000*1000/ (4*I2C_CLK_SPEED) 0x1f 0x01 I2C_ID RW I2C id: [7:1] I2C slave address + [0] R/W flag bit 0x5c

Datasheet for Telink TL3828 DS-TL3828-E5 275 Ver 0.8.0 0x02 I2CMST Volatile/R [0]: mst_busy master busy The status is asserted when the master state machine is not idle. (volatile) [1]: mst_scs_n master packet busy The status is asserted when the start status and Invalid when the stop state. This status is used to indicate that data is being transmitted. (volatile) [2]: mst_ack_in master received status 0: ack, 1: nak (volatile) [5:3]: mst_p master state machine 0-ID 1-Address 2-Dataw 3-Datar 4-Start 5-Stop 6-Idle (R) [7:6]: ss slave state machine 0-ID 1-Dataw 2-Datar (R) Note: The Master and Slave state machines are independent of each other. 0x30 Offset Name Type Description Defaul t Value

Datasheet for Telink TL3828 DS-TL3828-E5 276 Ver 0.8.0 0x03 I2CSCT0 RW [0]: mask_ss_wr I2C mask_slave_wr [1]: mask_ms_nak I2C mask_master_nak [2]: mask_rx rx interrupt enable [3]: mask_tx tx interrupt enable [4]: mask_rxdone [5]: mask_txdone [6]: maks_rxend [7]: maks_txend 0x00 0x04 I2CSCT1 RW [0]: ls_id launch ID [1]: ls_addr launch address [2]: ls_dataw launch data write [3]: ls_datar launch data read [4]: ls_start launch start [5]: ls_stop launch stop [6]: ls_id_r enable read ID [7]: ls_ack enable ACK in read command 0x00 0x05 I2CTRIG RW [3:0]: rx_irq_trig level Trigger rx_buf_irq interrupt when the RX FIFO reaches the threshold [7:4]: tx_irq_trig level Trigger tx_buf_irq interrupt when the TX FIFO under the threshold 0x44 Offset Name Type Description Defaul t Value

Datasheet for Telink TL3828 DS-TL3828-E5 277 Ver 0.8.0 0x06 I2CCTRL2 RW [0]: i2c_master I2C master enable Configure this device as a master or a slave. 1: Master mode, 0: Slave mode [1]: r_clk_stretch_en clk stretch enable The suspend transmission (Master) via pulling down SCL (Slave) to low level, and continue transmission (Master) after SCL (Slave) is released to high level. 1: enabled, 0: disabled [2]: manual_tx_stop_en Enter the STOP (transmitter) state via manually enabled [3]: manual_rx_stop_en Enter the STOP (receiver) state via manually enabled [4]: nak_stop_en The enable of the state machine to enter IDLE, when master detected the NAK [5]: tx_stretch_sel 0: id stretch, 1: id and slave read data stretch (tx_stretch_sel set 1, Register tx_length needs to be configured) [6]: mask_stretch Enable slave stretch interrupt [7]: r_stretch_pos_sel 0:stretch in ack/nak, 1: stretch in any negedge position 0x00 Offset Name Type Description Defaul t Value

Datasheet for Telink TL3828 DS-TL3828-E5 278 Ver 0.8.0 0x07 I2CCTRL3 RW [0]: r_clk_stretch_sen Slave auto stretch clk enable [1]: r_id_nmatch_stop_en Slave ID does not mastch the stop ss enable, the ss is in the SS_ID and may be error trigger by data. [2]: r_ms_nak_en master nak enable The last byte data read is automatically returned to nak [3]: manual_sda_delay Delay releasing the SDA and OEN wire before ack (ID, ADDRESS, DATAW) [4]: ndma_rxdone_en The rxdone function was enabled in NDMA mode. 1:enable, 0:disable, DMA mode needs to be disabled [5]: auto_rxclr_en DMA and NDMA mode: auto clear function enable 1:enable, 0:disable [6]: r_hs_mode standard mode and system clocl 48M, maintain ss_scl setup time Max [7]: r_fast_mode fast mode: ss_scl setup time Min 0x30 0x08 I2C_DATA_BUF0 Volatile Write/read buffer[7:0] 0x00 0x09 I2C_DATA_BUF1 Volatile Write/read buffer[15:8] 0x00 0x0a I2C_DATA_BUF2 Volatile Write/read buffer[23:16] 0x00 0x0b I2C_DATA_BUF3 Volatile Write/read buffer[31:24] 0x00 Offset Name Type Description Defaul t Value

Datasheet for Telink TL3828 DS-TL3828-E5 279 Ver 0.8.0 0x0c I2C_BUFCNT Volatile [3:0]: rx_bufcnt This register is increased when there are incoming received data in the Receiver Buffer Register. When there is read data in the Receiver Buffer Register, this register is decremented. [7:4]: tx_bufcnt This register is decremented when there are outgoing sent data in the Transmitter Buffer Register. When there is write data in the Transmitter Buffer Register, this register is increased. 0x00 0x0d I2C_STATUS Volatile [2:0]: rbcnt When there is read data in the Receiver Buffer Register, this register is decremented. [0]: W: write 1 to manual clear slave stretch [1]: W: write 1 to manual trigger slave stretch clk [2]: W: write 1 to manual clear master ack [3]: i2c_irq_o irq, total interruption of I2C. [6:4]: wbcnt When there is write data in the Transmitter Buffer Register, this register is increased. [7]: rxdone Similar to the rxdone irq interrupt, but rxdone is automatically cleared by the I2C. 0x00 Offset Name Type Description Defaul t Value

Datasheet for Telink TL3828 DS-TL3828-E5 280 Ver 0.8.0 0x0e I2C_STATUS1 Volatile [0]: ss_read This status is used to indicate the slave's read or write status. [1]:ss_scl Slave stretch the indication [2]: tx_empty The flag bit that the TX FIFO pointer to 0. [3]: rx_full The flag bit that the RX FIFO pointer to 8(FIFO maximum depth). [4]: trx_start [5]: trx_stop [6]: ss_scl_irq Slave stretch interrupt flag When data is transferred, RX FIFO pointer to 8(rx_full), or TX FIFO pointer to 0(tx_empty), the I2C controller will assert ss_scl_irq interrupt. W: write 1 to clear ss_scl_irq 0x06 Offset Name Type Description Defaul t Value

Datasheet for Telink TL3828 DS-TL3828-E5 281 Ver 0.8.0 0x0f I2C_CLR W1C [0]: ss_rw_clr, ss_rw_clr [1]:ms_nak_clr, manual clear master nak_irq [2]: rx_clr W: write 1 to clear RX FIFO pointer, and so on. Note: When RX FIFO is below the threshold set by the rx_irq_trig Register, the rx_clr interrupt clears automatically. [3]: tx_clr W: write 1 to clear TX FIFO pointer, and so on. Note: When TX FIFO is greater than the threshold set by the tx_irq_trig Register, the tx_clr interrupt clears automatically. [4]: rxdone_irq_clr When the receiver ends(the RX FIFO length counter increase to register I2CLEN), the I2C controller will assert rxdone_irq interrupt. W:write 1 to clear rxdone_irq [5]: txdone_clr When the transmitter ends(the TX FIFO length counter increase to register I2CLEN), the I2C controller will assert txdone interrupt. W: write 1 to clear txdone [6]: rx_end_clr When the STOP (receiver) is triggered, the I2C controller will assert rx_end interrupt. W:write 1 to clear rx_end [7]: tx_end_clr When the STOP (transmitter) is triggered, the I2C controller will assert tx_end interrupt. W: write 1 to clear tx_end 0x00 0x10 I2CLENL RW [7:0]: I2CLEN bit7-0 of configure the number (bytes) of Transmits or receives, default 1 byte 0x01 0x11 I2CLENM RW [7:0]: I2CLEN bit15-8 of configure the number(bytes) of Transmits or receives 0x00 Offset Name Type Description Defaul t Value

Datasheet for Telink TL3828 DS-TL3828-E5 282 Ver 0.8.0 The I2C1M related registers are listed as following, the base address of the following registers is 0x802401C0. Table 11-11 I2C1M Related Registers 0x12 I2CLENH RW [7:0]: I2CLEN bit23-16 of configure the number(bytes) of Transmits or receives 0x00 0x13 I2C_CTRL1 RW [0]: pem_event_en [1]: reserved [2]: pem_event_sel [3]: reserved [4]: mask_trx_start [5]: mask_trx_stop [6]: r_stretch_auto_clr_dis, 1'b1: The automatic clearing function of slave Stretch is disabled [7]: reserved 0x14 I2C_MST_STATUS R [0]: ss_busy, i2c slave busy flag [1]: ss_id, i2c slave id flag [2]: ss_dataw, i2c slave wdata flag [3]: ss_datar, i2c slave rdata flag [4]: id_busy, nak function id flag [5]: addr_busy, addr_busy [6]: dataw_busy, nak function wdata flag [7]: datar_busy, nak function rdata flag (RW) 0x00 0x15 I2C_CTRL2 R [5:0]: pem_event_en 0x00 Offset Name Type Description Defaul t Value 0x00 I2C1SP RW [7:0] I2C1M master clock speed: pclk*1000*1000/ (4*I2C1M_CLK_SPEED) 0x1f 0x01 I2C1_ID RW [7:0]: I2C1M ID [7:1] I2C1M slave address(7-bit addressing) + [0] R/W flag bit 0x5c Offset Name Type Description Defaul t Value

Datasheet for Telink TL3828 DS-TL3828-E5 283 Ver 0.8.0 0x02 I2C1MST Volatile/R [0]: mst_busy master busy The status is asserted when the master state machine is not idle. (volatile) [1]: mst_scs_n master packet busy The status is asserted when the start status and Invalid when the stop state. This status is used to indicate that data is being transmitted. (volatile) [2]: mst_ack_in master received status 0: ack, 1: nak (volatile) [5:3]: mst_p master state machine 0-ID 1-Address 2-Dataw 3-Datar 4-Start 5-Stop 6-Idle (R) [7:6]: ss slave state machine 0-ID 1-Dataw 2-Datar (R) Note: The Master and Slave state machines are independent of each other. 0x00 Offset Name Type Description Defaul t Value

Datasheet for Telink TL3828 DS-TL3828-E5 284 Ver 0.8.0 0x03 I2CSCT0 RW [0]: mask_ss_wr I2C mask_slave_wr [1]: mask_ms_nak I2C mask_master_nak [2]: mask_rx rx interrupt enable [3]: mask_tx tx interrupt enable [4]: mask_rxdone [5]: mask_txdone [6]: maks_rxend [7]: maks_txend 0x00 0x04 I2CSCT1 RW [0]: ls_id launch ID [1]: ls_addr launch address [2]: ls_dataw launch data write [3]: ls_datar launch data read [4]: ls_start launch start [5]: ls_stop launch stop [6]: ls_id_r enable read ID [7]: ls_ack enable ACK in read command 0x00 0x05 I2CTRIG RW [3:0]: rx_irq_trig level Trigger rx_buf_irq interrupt when the RX FIFO reaches the threshold [7:4]: tx_irq_trig level Trigger tx_buf_irq interrupt when the TX FIFO under the threshold 0x44 Offset Name Type Description Defaul t Value

Datasheet for Telink TL3828 DS-TL3828-E5 285 Ver 0.8.0 0x06 I2CCTRL2 RW [0]: i2c_master I2C master enable Configure this device as a master or a slave. 1: Master mode, 0: Slave mode [1]: r_clk_stretch_en clk stretch enable The suspend transmission (Master) via pulling down SCL (Slave) to low level, and continue transmission (Master) after SCL (Slave) is released to high level. 1: enabled, 0: disabled [2]: manual_tx_stop_en Enter the STOP (transmitter) state via manually enabled [3]: manual_rx_stop_en Enter the STOP (receiver) state via manually enabled [4]: nak_stop_en The enable of the state machine to enter IDLE, when master detected the NAK [5]: tx_stretch_sel 0: id stretch, 1: id and slave read data stretch (tx_stretch_sel set 1, Register tx_length needs to be configured) [6]: mask_stretch Enable slave stretch interrupt [7]: r_stretch_pos_sel 0:stretch in ack/nak, 1: stretch in any negedge position 0x00 Offset Name Type Description Defaul t Value

Datasheet for Telink TL3828 DS-TL3828-E5 286 Ver 0.8.0 0x07 I2CCTRL3 RW [0]: r_clk_stretch_sen Slave auto stretch clk enable [1]: r_id_nmatch_stop_en Slave ID does not mastch the stop ss enable, the ss is in the SS_ID and may be error trigger by data. [2]: r_ms_nak_en master nak enable The last byte data read is automatically returned to nak [3]: manual_sda_delay Delay releasing the SDA and OEN wire before ack (ID, ADDRESS, DATAW) [4]: ndma_rxdone_en The rxdone function was enabled in NDMA mode. 1:enable, 0:disable, DMA mode needs to be disabled [5]: auto_rxclr_en DMA and NDMA mode: auto clear function enable 1:enable, 0:disable [6]: r_hs_mode standard mode and system clocl 48M, maintain ss_scl setup time Max [7]: r_fast_mode fast mode: ss_scl setup time Min 0x30 0x08 I2C_DATA_BUF0 Volatile Write/read buffer[7:0] 0x00 0x09 I2C_DATA_BUF1 Volatile Write/read buffer[15:8] 0x00 0x0a I2C_DATA_BUF2 Volatile Write/read buffer[23:16] 0x00 0x0b I2C_DATA_BUF3 Volatile Write/read buffer[31:24] 0x00 Offset Name Type Description Defaul t Value

Datasheet for Telink TL3828 DS-TL3828-E5 287 Ver 0.8.0 0x0c I2C_BUFCNT Volatile [3:0]: rx_bufcnt This register is increased when there are incoming received data in the Receiver Buffer Register. When there is read data in the Receiver Buffer Register, this register is decremented. [7:4]: tx_bufcnt This register is decremented when there are outgoing sent data in the Transmitter Buffer Register. When there is write data in the Transmitter Buffer Register, this register is increased. 0x00 0x0d I2C_STATUS Volatile [2:0]: rbcnt When there is read data in the Receiver Buffer Register, this register is decremented. [0]: W: write 1 to manual clear slave stretch [1]: W: write 1 to manual trigger slave stretch clk [2]: W: write 1 to manual clear master ack [3]: i2c_irq_o irq, total interruption of I2C. [6:4]: wbcnt When there is write data in the Transmitter Buffer Register, this register is increased. [7]: rxdone Similar to the rxdone irq interrupt, but rxdone is automatically cleared by the I2C. 0x00 Offset Name Type Description Defaul t Value

Datasheet for Telink TL3828 DS-TL3828-E5 288 Ver 0.8.0 0x0e I2C_STATUS1 Volatile [0]: ss_read This status is used to indicate the slave's read or write status. [1]:ss_scl Slave stretch the indication [2]: tx_empty The flag bit that the TX FIFO pointer to 0. [3]: rx_full The flag bit that the RX FIFO pointer to 8(FIFO maximum depth). [4]: trx_start [5]: trx_stop [6]: ss_scl_irq Slave stretch interrupt flag When data is transferred, RX FIFO pointer to 8(rx_full), or TX FIFO pointer to 0(tx_empty), the I2C controller will assert ss_scl_irq interrupt. W: write 1 to clear ss_scl_irq 0x06 Offset Name Type Description Defaul t Value

Datasheet for Telink TL3828 DS-TL3828-E5 289 Ver 0.8.0 0x0f I2C_CLR W1C [0]: ss_rw_clr, ss_rw_clr [1]:ms_nak_clr, manual clear master nak_irq [2]: rx_clr W: write 1 to clear RX FIFO pointer, and so on. Note: When RX FIFO is below the threshold set by the rx_irq_trig Register, the rx_clr interrupt clears automatically. [3]: tx_clr W: write 1 to clear TX FIFO pointer, and so on. Note: When TX FIFO is greater than the threshold set by the tx_irq_trig Register, the tx_clr interrupt clears automatically. [4]: rxdone_irq_clr When the receiver ends(the RX FIFO length counter increase to register I2CLEN), the I2C controller will assert rxdone_irq interrupt. W:write 1 to clear rxdone_irq [5]: txdone_clr When the transmitter ends(the TX FIFO length counter increase to register I2CLEN), the I2C controller will assert txdone interrupt. W: write 1 to clear txdone [6]: rx_end_clr When the STOP (receiver) is triggered, the I2C controller will assert rx_end interrupt. W:write 1 to clear rx_end [7]: tx_end_clr When the STOP (transmitter) is triggered, the I2C controller will assert tx_end interrupt. W: write 1 to clear tx_end 0x00 0x10 I2CLENL RW [7:0]: I2CLEN bit7-0 of configure the number (bytes) of Transmits or receives, default 1 byte 0x01 0x11 I2CLENM RW [7:0]: I2CLEN bit15-8 of configure the number(bytes) of Transmits or receives 0x00 Offset Name Type Description Defaul t Value

Datasheet for Telink TL3828 DS-TL3828-E5 290 Ver 0.8.0

11.5 Improved Inter-Integrated Circuit (I3C)

11.5.1 Introduction

The SoC embeds two Improved Inter-Integrated Circuit (I3C) modules, each of which supports all required features of the MIPI Alliance Specification for I3C. The I3C block diagram is shown as below: 0x12 I2CLENH RW [7:0]: I2CLEN bit23-16 of configure the number(bytes) of Transmits or receives 0x00 0x13 I2C_CTRL1 RW [0]: pem_event_en [1]: reserved [2]: pem_event_sel [3]: reserved [4]: mask_trx_start [5]: mask_trx_stop [6]: r_stretch_auto_clr_dis, 1'b1: The automatic clearing function of slave Stretch is disabled [7]: reserved 0x14 I2C_MST_STATUS R [0]: ss_busy, i2c slave busy flag [1]: ss_id, i2c slave id flag [2]: ss_dataw, i2c slave wdata flag [3]: ss_datar, i2c slave rdata flag [4]: id_busy, nak function id flag [5]: addr_busy, addr_busy [6]: dataw_busy, nak function wdata flag [7]: datar_busy, nak function rdata flag (RW) 0x00 0x15 I2C_CTRL2 R [5:0]: pem_event_en 0x00 Offset Name Type Description Defaul t Value

Datasheet for Telink TL3828 DS-TL3828-E5 291 Ver 0.8.0 Figure 11-20 I3C Block Diagram

11.5.2 I3C Features

The I3C features including:

• Supports master and secondary master modes
• Supports slave mode
• Supports for an I2C-style static address so that the I3C controller can connect to an I2C bus
• Supports Standard Data Rate (SDR) mode data transfers
• Up to three I3C group addresses
• In-Band Interrupts (IBI) with or without data payload
• Hot-Join capability
• Controller request (secondary master)
• Support I3C Ti ming Control Asynchronous Mode 0
• Support Common Command Codes (CCC)
• Support up to 4 mapped addresses to support I3C virtual targets
• Support DMA transfers to/from the application

11.5.3 I3C Functional Description

11.5.3.1 I3C Master Mode

When operating in master mode, the I3C implements the following functions:

• Generating the SCL clock signal, with application-specified frequencies and duty cycles for I3C push- pull, open-drain, and I2C mode operati on
• Performing dynamic address assignment (DAA) under application control
• Responding to IBIs, Hot-Join requests, and master requests I3C Chip I3C_Reset_Detector I3C Bus SCL SDA Interrupt DMA interface I3C Core APB-BUS

Datasheet for Telink TL3828 DS-TL3828-E5 292 Ver 0.8.0

• Generating read/write messages
• Control of SDA input/output, including I3C open-drain and push-pull requirements 1. SCL Generation When operating in master mode, the I3C is responsible for generating the bus clock, SCL. Through the MCONFIG register, you can configure the SCL frequency and duty cycle for each of the following bus conditions:
• I3C push-pull operation (SDA is driven wi th push-pull drive)
• I3C open-drain operation (SDA is driven low for logic 0 and is Hi-Z with pull-up for logic 1)
• I2C mode (1) SCL Waveform for Push-Pull The following MCONFIG register fields define the SCL frequency and duty cycle for pushpull operation:
• MCONFIG.PPBAUD – Sets the width of the SCL high period for push-pull operation.
• MCONFIG.PPLOW – Sets the width of the SCL low period for push-pull operation. The I3C uses input clock fclk as the base clock for generating SCL. For push-pull operation:
• The SCL high period is (PPBAUD + 1) fclk cycles.
• The SCL low peri od is (PPBAUD + 1 + PPLOW) fclk cycles. (2) SCL Waveform for I3C Open-Drain The following MCONFIG register fields define the SCL frequency and duty cycle for I3C open-drain operation:
• MCONFIG.PPBAUD – Sets the width of the SCL high period for push-pull operation.
• MCONFIG.ODBAUD – Sets the width of the SCL low period for open-drain operation in units of the SCL push-pull high period set by PPBAUD.
• MCONFIG.ODHPP – Sets the width of the SCL high period for open-drain operation. The I3C uses input clock fclk as the base clock for generating SCL. For I3C open-drain operation:
• The SCL low period is (PPBAUD + 1) x (ODBAUD + 1) fclk cycles. For ex ample, if PPBAUD = 0 and ODBAUD = 1, the SCL push-pull high period is one fclk cycle and the SCL open-drain low period is two fclk cycles.
• The SCL high period depends on the ODHPP value: º If ODHPP = 0, the SCL high period is the same as the SCL low period. º If ODHPP = 1, the SCL open-drain high period is the same as the SCL push-pull high period, as set by PPBAUD. 2. Assigning Dynamic Addresse s To assi gn dynamic addresses to all I3C bus slaves at I3C bus initialization, the I3C main bus master uses the Dynamic Address Assignment (DAA) process. To perform DAA through the I3C: Step 1 Enable the following interrupts: º MCTRLDONE – Interrupt goes active when the I3C is waiting for the application to provide a dynamic address for a slave that has just sent its 48-bit Provisioned ID. º COMPLETE – Interrupt goes active when DAA is complete. º RXPEND – Interrupt goes active when Provisioned ID data from a slave is available the application to read. º IBIWON – Interrupt goes active if an IBI, master request, or Hot-Join request occurs on the I3C bus.

Datasheet for Telink TL3828 DS-TL3828-E5 293 Ver 0.8.0 º ERRWARN – Interrupt goes active if an error occurs. Step 2 Write to the MCTRL register: º MCTRL.REQUEST = 4 (Process DAA) º MCTRL.IBIRESP = The response you want to use if an IBI occurs during DAA. Step 3 When an RXPEND interrupt occurs, begin reading data (Provisioned ID from slave). Step 4 When an MCTRLDONE interrupt occurs, check the MSTATUS register: º If MSTATUS.STATE = 5 (DAA) and MSTATUS.BETWEEN = 1, the I3C is waiting for the appli cation to provide a dynamic address for a slave that has just sent its Provisioned ID. Write the appropriate 7- bit dynamic address to MWDATAB[6:0]. Then, write 4 to MCTRL.REQUEST (Process DAA) again to assign the dynamic address and continue DAA. º If MSTATUS.STATE = 0 (IDLE) and MSTATUS.COMPLETE = 1, all slaves have been assigned dynamic addresses and DAA is complete. º If MSTATUS.NACKED = 1 after assi gning a dynamic address to a slave, the slave did not accept the dynamic address. The application can either set, – MCTRL.REQUEST to 2 (Emit Stop), then start DAA over again or set 3. MCTRL.REQUEST to 4 (Process DAA) to continue DAA.Generating Messages with MCTRL The application can use either message mode or the MCTRL register to generate I2C or I3C SDR read/write messages. (1) Generating I2C Mode Messages wi th MCTRL To generate an I2C mode message using MTCTRL: Step 1 Enable the following interrupts: º COMPLETE – Interrupt goes active when message is complete. º RXPEND – If the message is a read, enable RXPEND to trigger reading data from the receive buffer/ FIFO. º TXNOTFULL – If the message is a write, enable TXNOTFULL to trigger writing data to the transmit buffer/FIFO. º IBIWON – Interrupt goes active if an IBI, master request, or Hot-Join request occurs on the I3C bus. º ERRWARN – Interrupt goes active if an error occurs. Step 2 Write to the MCTRL register: º REQUEST = 1 (Emit Start Addr) º TYPE = 1 (I2C) º IBIRESP = The response you want to use if an IBI occurs. º DIR = 1 for read or 0 for write. º ADDR = The static address of the I2C slave. º RDTERM – For a read, set the RDTERM to the number of bytes to be read. Step 3 If the message is a write, write the data to the transmi t buffer/FIFO through MWDATAB/H(E). You can use the TXNOTFULL interrupt to trigger processor writes, or trigger a DMA transfer. NOTE: Transmit data can be written to the transmit buffer/FIFO before step 1. Step 4 If the message is a read, wait for the RXPEND interrupt, then read the data from MRDATAB/H. Or, trigger a DMA transfer.

Datasheet for Telink TL3828 DS-TL3828-E5 294 Ver 0.8.0 Step 5 When the COMPLETE interrupt occurs, write a new value to MCTRL.REQUEST: º To emit a STOP, write REQUEST = 2 (Emit Stop) and TYPE = 1 (I2C). º To start another I2C mode message with a repeated START, repeat steps 2 through 4. (2) Generating I3C SDR Messages with MCTRL To generate an I3C SDR mode message using MCTRL: Step 1 Enable the following interrupts: º COMPLETE – Interrupt goes active when message is complete. º RXPEND – If the message is a read, enable RXPEND to trigger reading data from the receive buffer/ FIFO. º TXNOTFULL – If the message is a write, enable TXNOTFULL to trigger writing data to the transmit buffer/FIFO. º I BIWON – Interrupt goes active if an IBI, master request, or Hot-Join request occurs on the I3C bus. º ERRWARN – Interrupt goes active if an error occurs. Step 2 Optionally, emit the I3C broadcast address from the stopped state in SDR mode, then wait for the MCTRLDONE interrupt. Emitting the I3C broadcast address before the slave dynamic address enables any I3C bus slave to generate an IBI and allows the slave dynamic address to be sent at push-pull speed. To emit the I3C broadcast address, enable the MCTRLDONE interrupt, then write to the MCTRL regi ster: º REQUEST = 1 (Emit Start Addr) º TYPE = 0 (I3C SDR) º IBIRESP = The response you want to use if an IBI occurs. º DIR = 0 º ADDR = 0x7E When the MCTRLDONE interrupt occurs, disable the MCTRLDONE interrupt and continue to step 3. Step 3 Write to the MCTRL register: º REQUEST = 1 (Emit Start Addr) º TYPE = 0 (I3C SDR) º IBIRESP = The response you want to use if an IBI occurs. º DIR = 1 for read or 0 for write. º ADDR = The dynami c address of the I3C slave. º RDTERM – To limit the number of bytes to be returned for a read message, set the RDTERM to the maximum number of bytes to be read. If the addressed slave does not end the read before RDTERM is reached, the I3C terminates the read. If RDTERM = 0, the I3C allows the read to continue until ended by the slave. Step 4 If the message is a write, write the data to the transmit buffer/FIFO through MWDATAB/H(E). You can use the TXNOTFULL interrupt to trigger processor wri tes, or trigger a DMA transfer. NOTE: Transmit data can be written to the transmit buffer/FIFO before step 3. Step 5 If the message is a read, wait for the RXPEND interrupt, then read the data from MRDATAB/H. Or, trigger a DMA transfer. Step 6 When the COMPLETE interrupt occurs, write a new value to MCTRL.REQUEST:

Datasheet for Telink TL3828 DS-TL3828-E5 295 Ver 0.8.0 º To emit a STOP after an SDR mode message, write REQUEST = 2 (Emit Stop) and TYPE = 0 (I3C SDR). º To start another SDR mode message with a repeated START, repeat steps 3through 5. 4. Generating an Read SDR Message in Message Mode To generate a read SDR message using message mode: Step 1 Enable the following interrupts: º COMPLETE – Interrupt goes active when message is complete. º RXPEND – If the message is a read, enable RXPEND to trigger reading data from the receive buffer/ FIFO. º TXNOTFULL – If the message is a write, enable TXNOTFULL to trigger writing data to the transmit buffer/FIFO. º IBIWON – Interrupt goes active if an IBI, master request, or Hot-Join request occurs on the I3C bus. Step 2 Write the message control informati on to the MWMSG_SDR register: º LEN = Message length in bytes º I2C = 0 for I3C or 1 for I2C º END = How you want to end the message º ADDR = Destination address of the message º DIR = 1 for read Step 3 Wait for the DMA read trigger or RXPEND interrupt, then read the data from MRMSG_SDR. Step 4 When the COMPLETE interrupt occurs, the SDR mode message has completed on the I3C bus. The state of the I3C bus depends on the MWMSG_SDR.END value that was wri tten for the message: º If END = 1, the message ends with a STOP. The next message initiated with either message mode or MCTRL begins with a START. º If END = 0, the message ends with the I3C bus paused. The next message initiated with either message mode or MCTRL begins with a repeated START. 5. Generating CCCs The I3C automatically generates the following CCCs when the respecti ve conditions occur:

• ENTDAA when the application requests DAA mode by setting MCTRL_0.REQUEST to 4 (Process DAA) Any other CCC sent to any or all slaves must be generated by the application using either MCTRL or message mode, in a manner similar to normal I3C write/read messages. For example, to send broadcast CCC ENEC, use either MCTRL or message mode to generate a write message wi th the following controls and data:
• Address = 0x7E
• Direction = Write
• First data byte = 0x00 (ENEC)
• Second data byte = ENEC data byte (for example, 0x02 to enable bus master requests)
• End condition = STOP or repeated START To send direct CCC SETDASA to a specific slave, use either MCTRL or message mode to generate write messages with the following controls and data:
• Message 1: º Address = 0x7E

Datasheet for Telink TL3828 DS-TL3828-E5 296 Ver 0.8.0 º Direction = Write º Data byte = 0x87 (SETDASA) º End condition = Repeated START

• Message 2 º Address = Static address of slave º Direction = Write º Data byte = 7-bit dynamic address (LSb = 0) º End condition = STOP or repeated START 6. I3C slave Reset To generate the I3C slave Reset Pattern when the I3C is operating as an I3C bus master:
• Use either MCTRL or message mode to emit a RSTACT CCC speci fying what the connected slave(s) are to do in response to the I3C slave Reset Pattern.
• Write following values to the MCTRL register to emit the I3C slave Reset Pattern: º TYPE = 10 º REQUEST = 110 7. Handling IBIs An I3C slave device can generate an IBI in either of two ways: When the I3C bus master issues a START, the I3C bus slave emits its own dynamic address on SDA and wins address arbitratio n. The MSTATUS.IBIWON bi t is then set (and interrupt generated if enabled), MSTATUS.IBIADDR contains the address of the slave that generated the IBI (or 0x02 if the IBI is a Hot-Join request), and MSTATUS.IBITYPE indicates the IBI type (IBI, Hot-Join request, or master request). For an IBI, I3C responds according to the value in MCTRL.IBIRESP. For a Hot-Join request or master request, the application must deci de whether to ACK or NACK the request. From the Bus Available state, the I3C bus slave pulls SDA low to initiate a START. The application can use either of the following methods to respond to the slave initiated START:
• If MCTRL.REQUEST = 7 (Auto IBI), the I3C automatically emits address 0x7E when the slave initiates the START condition. When the slave wins address arbitration, MSTATUS.IBIWON i s set, MSTATUS.IBIADDR contains the address of the slave that generated the IBI, and MSTATUS.IBITYPE indicates the IBI type. The I3C responds according to the value in MCTRL.IBIRESP.
• If MCTRL.REQUEST is set to another value (for example, 0), the application can use the TGTSTART interrupt as notification that an I3C slave has initiated a START. The application then uses MCTRL to emit a START with address 0x 7E. When the slave wins address arbitration, MSTATUS.IBIWON is set, MSTATUS.IBIADDR contains the address of the slave that generated the IBI, and MSTATUS.IBITYPE indicates the IBI type. The I3C responds according to the value in MCTRL.IBIRESP.For an IBI, the I3C responds according to the value in MCTRL.IBIRESP. For a Hot-Join request or master request, the application must decide whether to ACK or NACK the request. (1) IBI Response For an i ncoming IBI, MCTRL.IBIRESP determines how the I3C responds after the slave emits its dynamic address and wins address arbitration:
• If IBIRESP = 00, the I3C ACKs the IBI and uses the IBIRULES register to determine whether the IBI includes a mandatory byte.

Datasheet for Telink TL3828 DS-TL3828-E5 297 Ver 0.8.0

• If IBIRESP = 01, the I3C NACKs the IBI.
• If IBIRESP = 10, the I3C ACKs the IBI and reads the mandatory byte. Use IBIRESP = 10 only if all IBI- capable bus slaves provide a mandatory byte.
• If IBIRESP = 11, the I3C waits for application to make the ACK/NACK decision by writing 3 (IBI Ack Nack) to MCTRL.REQUEST along with a new value to MCTRL.IBIRESP. When MCTRL.REQUEST = 3 (IBI Ack Nack), MCTRL.IBIRESP i s interpreted as:
• 00: ACK with no mandatory byte
• 01: NACK
• 10: ACK with mandatory byte
• 11: Reserved (2) IBI Complete The I3C sets MSTATUS.COMPLETE (and generates an interrupt if enabled) when the IBI is complete:
• For an IBI without a mandatory byte, the I3C sets MSTATUS.COMPLETE in the same cycle as MSTATUS.IBIWON.
• For an IBI with a mandatory byte, the I3C set MSTATUS.COMPLETE when the mandatory byte and any addi tional bytes have been read by the application. If the I3C bus slave that emits the IBI continues sending data bytes after the mandatory data byte, the I3C continues read the IBI data bytes until one of the following conditions occurs: º The I3C bus slave indicates end-of-data. º If the I3C bus slave does not end-of-data before the number of data bytes reaches 7, the I3C termi nates the IBI data read after the eighth data byte (mandatory data byte plus seven additional data bytes), if the I3C bus slave has not already indicated end-of-data. The application can then take further action depending on which I3C slave generated the IBI and the content of the mandatory byte (if provided). (3) IBI Rules Bit 2 of each I3C bus slave’s BCR value indicates whether the slave provides a mandatory byte when generating an IBI. The application uses this information to wr ite to the IBIRULES regi ster the dynamic address of up to five I3C bus slaves that either do or do not provide an IBI. When MCTRL.IBIRESP = 00, the I3C uses the IBIRULES register to determine whether the I3C bus slave that is currently generating an IBI also provides a mandatory byte with the IBI. 8. Responding to Hot-Join Requests An I3C bus slave can join an already-configured I3C bus by issuing a Hot-Joi n request. A Hot-Join request is an IBI with reserved address 0x02 and the RnW bit set to 0 (write). When the I3C bus has been in the Bus Available state for at least 200 ?s, the slave can emit the IBI either by pulling SDA low or waiting for the I3C bus master to issue a START. When the incoming Hot-Join request wins arbitration, MSTATUS.IBIWON is set and MSTATUS.IBITYPE is 11, indicating that the i ncoming IBI event is a Hot-Join request. It is up to the application to either ACK or NACK the request. If the application is ready to assign a dynamic address to the slave, then the application should:
• ACK the Hot-Join request by writing 011 (IBI Ack Nack) to MCTRL.REQUEST and 00 (ACK) to IBIRESP.

Datasheet for Telink TL3828 DS-TL3828-E5 298 Ver 0.8.0

• Issue a STOP on the I3C bus by writing 010 (Emit Stop) to MCTRL.REQUEST.
• Issue broadcast CCC ENTDAA, then continue to use the DAA procedure to assign the slave a dynamic address. If the application is not ready to assign a dynamic address to the slave, then the application should:
• ACK the Hot-Join request by writing 011 (IBI Ack Nack) to MCTRL.REQUEST and 00 (ACK) to IBIRESP.
• Issue broadcast CCC DISEC to disable Hot-Joi n requests until it is ready to assign a dynamic address. The application can instead NACK the request by writing 011 (IBI Ack Nack) to MCTRL.REQUEST and 01 (NACK) to IBIRESP, in which case the slave initiates another Hot-Join request at the next START. 9. Transferring Bus Control When the I3C is acting as the I3C bus current master, the application can transfer bus control to a master- capable slave (secondary bus master) by i ssuing a GETACCCR CCC, either directly or in response to an IBI of type master request. If the bus slave accepts the request by returning its own dynamic address in bits [7:1] and the negative parity of the dynamic address in bit [0], the application should:
• Issue a STOP by writing 2 (Emit Stop) to MCTRL.REQUEST.
• Write 10 to MCONFIG.CTRENA to transi tion to master-capable slave mode (secondary master).
• To enable operation as an I3C bus slave, write 1 to CONFIG.TGTENA. NOTE: If the application does not want to operate as an I3C bus slave after transferring bus control (for exam- ple, if the application is to enter a deep-sleep mode), either set or leave CONFIG.TGTENA set to 0.

11.5.3.2 I3C Slave Mode

When operating in slave mode, the I3C implements the followi ng functions:

• Dynamic address assignment
• Recognition of its assigned dynamic address and the I3C broadcast address
• Responding to CCCs
• I3C Slave Reset
• Extracting write data from I3C/I2C write frames and providing the data to the application
• Responding to I3C/I2C read frames with data supplied by the application
• Responding to I3C ENTHDRn mode commands and recognizing the I3C HDR Exit Pattern
• Control of SDA i nput/output, including I3C open-drain and push-pull requirements
• Generation of IBIs, with or without data
• Generation of master requests
• Generation of Hot-Join requests
• I2C-style static address 1. Timing Control Asynchronous Mode 0Hot-Join Request An I3C slave device can join an already configured I3C bus by generating a Hot-Join request. A Hot-Join request can be used in either of the followi ng conditions:
• The I3C slave device is physically connected to the I3C bus, but is powered on after the I3C bus has been configured.
• The I3C slave device is physically connected to the I3C bus after the I3C bus has been configured. For example, a board is inserted into a system that is already powered on and configured.

Datasheet for Telink TL3828 DS-TL3828-E5 299 Ver 0.8.0 The I3C bus master can disable/enable Hot-Join requests using DISEC and ENEC CCCs. The I3C automatically handles DISEC and ENEC CCCs and the STATUS.HJDIS bit indicates whether Hot-Join requests are currently disabled. If STATUS.HJDIS = 1, Hot-Join requests are disabled and the I3C will not generate a Hot-Join request. To generate a Hot-Join request, write the Hot-Join request to CONFIG.EVENT before enabli ng the I3C. Use the following sequence: Step 1 Make sure CONFIG.TGTENA is 0. Step 2 If I3C is configured to use CONFIG.BAMATCH as the match value for the 1us Bus Available time counter, write the appropriate value to CONFIG.BAMATCH. Step 3 Write 11 to CTRL.EVENT. Step 4 Write 1 to CONFIG.TGTENA. After the 200us Bus Idle time elapses, the I3C generates a Hot-Join request. The STAT US.EVENT bi t is set to indicate that the I3C has requested an event and STATUS.EVDET indicates the status of the event. When the I3C bus master assigns the I3C a valid dynamic address, the DYNADDR.DVALID and STATUS.DVALID bits are set and the I3C functions as a normal I3C bus slave. 2. Offline Operation The application can disable the I3C from participating as an I3C bus slave, after it has been assigned a dynami c address, by setting the CONFIG_0.TGTENA (I3C_BASE + 0x04[0]) bit to 0. The offline state occurs when the I3C has a valid dynamic address in DYNADDR and CONFIG_0.TGTENA is set to 0. The I3C can then re-join the I3C bus using its previously assigned dynamic address, and not have to use a Hot- Join request. Figure 11-21 shows the sequence of operation for disabling, then re-enabling the I3C on the I3C bus wi th its previously assigned dynamic address. When re-enabling the I3C the I3C with a valid value in DYNADDR, set the CONFIG.OFFLINE bit when setting the CONFIG.TGTENA bit. The I3C then waits for either an HDR Exit Pattern or 60us of I3C bus inactivity, then re-joins the I3C bus using the dynamic address stored in DYNADDR and monitors the bus for START or STOP. If the application needs to generate an IBI after re-enabli ng the I3C with a valid dynamic address in DYNADDR, the application should wait until either a STOP occurs on the I3C bus or the I3C bus is inactive for at least 200us before requesting the IBI.

Datasheet for Telink TL3828 DS-TL3828-E5 300 Ver 0.8.0 Figure 11-21 Returning From Offline State with Valid Dynamic Address 3. Using Mapped slave Addresses The I3C supports up to 4 mapped addresses to support I3C virtual slaves.

• MAPCTRL0 – Read-only register associated with the primary dynamic address.
• One read-write MAPCTRLn register for each configured mapped address slot.
• MSGLAST – Contains the index numbers of the most recent mapped address slots that matched an incoming dynamic or static address. For each mapped address slot, there is a corresponding MAPCTRLn register. One mapped address (mapped address slot 1) can be an I2C 10-bit static address. Each mapped address has an associ ated index number. Index 0 corresponds to the primary I3C dynamic address assigned to the I3C by the I3C bus master. An address match occurs when an incoming message on the I3C or I2C bus matches any of the valid mapped addresses. When a match occurs, the MSGLAST register holds the index of the matching mapped address. Mapped address indexes (slots) 1–4 can be enabled with static or dynamic addresses written directly by the application and/or can be configured to support autom ati c assignment of dynamic address using any combination of the following methods: SETDASA CCC, SETAASA CCC or ENTDAA CCC. Each mapped address slot can also be configured to have a unique DCR value and a configurable number of unique PID bits to return for the ENTDAA CCC. For details about the associated parameter and register bit settings. To use mapped addresses, write the mapped address configuratio n to the MAPCTRLn regi sters before setting CONFIG.TGTENA. NOTE: When both mapped addresses and the I3C group addressing feature are supported, mapped addresses can be assigned to I3C slave address groups. (1) Enabling a Mapped Address Slot with a Dynamic Address I3C is enabled on I3C bus and has valid dynamic address Write 0 to CONFIG.TGTENA I3C is offline. DYNADDR contains valid dynamic address. Write 1 to CONFIG.TGTENA and write 1 to CONFIG.OFFLINE. I3C waits for either an HDR Exit Pattern or 60 us of I3C bus inactivity, then re-joins the I3C bus using the dynamic address stored in DYNADDR.

Datasheet for Telink TL3828 DS-TL3828-E5 301 Ver 0.8.0 To enable mapped address slot n with an application-assigned dynamic address, write to the following values to the respective fields of register MAPCTRLn:

• ADDR = The application-assigned dynamic address
• MAPSA = 0
• ENA = 1 Mapped address slot n is then enabled on the I3C bus with dynamic address ADDR and does not participate in dynamic address assignment through ENTDAA regardless of the value of MAPCTRLn.AUTO. (2) Enabli ng a Mapped Address Slot with a Static Address To enable mapped address slot n with an application-assigned static address, write to the following values to the respective fields of register MAPCTRLn:
• ADDR = The application-assigned static address
• MAPSA = 1
• ENA = 1
• SA10B (slot 1 only) = Upper 3 bits of 10-bit static address for slot 1, or 000 if slot 1 is assi gned a 7-bit static address. Mapped address slot n is then enabled as an I2C slave with static address ADDR and does not participate in I3C dynamic address assignment through ENTDAA regardless of the value of MAPCTRLn.AUTO. Each mapped address slot enabled with a static address responds to an incoming SETDASA CCC by updating its MAPCTRLn.ADDR field to the assigned dynamic address and deasserting the MAPCTRLn.MAPSA bi t. Each mapped address slot enabled with a static address responds to an incoming SETAASA CCC by deasserting the MAPCTRLn.MAPSA bit to indicate that the MAPCTRLn.ADDR field now contains a dynamic address. (3) Enabling a Mapped Address Slot for ENTDAA Each mapped address slot can be individually enabled to participate in dynamic address assignment through the ENTDAA CCC. The following confi guration parameters determine ENTDAA characteristics for all mapped address slots:
• AUTO_MAP_DCR_SWAPPED – Determines whether each slot has its own DCR value or all slots use the primary DCR value.
• AUTO_MAP_PID_CNT – The number of unique PID bits each slot has.
• AUTO_MAP_PID_AS_REG – Determines whether mapped address slots use unique DCR values and unique PID bits from hardware parameters or MAPCTRLn registers. For example, to use unique DCR values and unique PID bits [9:0] for each mapped address slot and use MAPCTRLn registers to enable each slot for ENTDAA and provide the unique DCR and PID bits, the respective settings are:
• AUTO_MAP_DCR_SWAPPED = 1
• AUTO_MAP_PID_CNT = 10
• AUTO_MAP_PID_AS_REG = 1 To enable mapped slot n for ENTDAA wi th its unique DCR and PID bits, write the following values to MAPCTRLn:
• MAPCTRLn[31:24] = DCR value for slot n
• MAPCTRLn[23:14] = PID bits [9:0] slot n

Datasheet for Telink TL3828 DS-TL3828-E5 302 Ver 0.8.0

• MAPCTRLn[13] (AUTO) = 1 (enable slot n for ENTDAA)
• MAPCTRLn[12] (NACK) = 0 (ACK incoming messages for slot n)
• MAPCTRLn[11:9] (SA10B) = 000
• MAPCTRLn[8] (MAPSA) = 0
• MAPCTRLn[7:1] (ADDR) = 0x00
• MAPCTRLn[0] (ENA) = 0 When the ENTDAA process is complete for mapped address slot n, the MAPCTRLn register is automatically updated as follows:
• MAPCTRLn[7:1] (ADDR) = Dynamic address assigned to mapped address slot n
• MAPCTRLn[0] (ENA) = Mapped address slot n i s enabled with dynamic address ADDR. (4) Determining which Mapped Address Slot had an Address Match When an incoming message header matches either the primary dynamic (or static) address, or the dynamic or static address for any enabled mapped address slot, the I3C sets the STATUS.MATCHED bit and generates an interrupt if enable d. The appli cation can then read the MSGLAST register to determine which address was matched:
• MSGLAST.MAPLAST contains the index of the matching mapped address slot 0x0 for the primary dynamic or static address).
• MSGLAST.LASTSTATIC indicates whether the matching address was a dynamic or static address. 4. Reading Data When there is data available to be read in the I3C receive (from-bus) buffer, the ST ATUS_1.RXPEND (I3C_BASE + 0x 09[3]) bit is set and the current data byte or half-word can be read from the RDATAB or RDATAH register. The source of the data is the current I3C or I2C bus master and the data can of be any of the following types:
• An I3C SDR mode write message that matched this device’s I3C dynamic address
• A broadcast CCC issued by the I3C bus master and that the I3C does not handle automatically
• A direct CCC issued by the I3C bus master that matched this device’s I3C dynamic address and that the I3C does not handle automatically
• A write from an I2C bus master that matched this device’s I2C static address (if the I3C is configured to support I2C mode) When STATUS.RXPEND = 1, the appli cation should read the current data byte(s) from appropriate register:
• RDATAB to read a single byte.
• If a half-word of data is available, the application can read the current half-word from RDATAH. The DATACTRL.RXCOUNT value indicates the number of receive buffer/FIFO entries available for reading. 5. Writing Data When there is space available in the transmit (to-bus) buffer, the STATUS_1.TXNOTFULL (I3C_BASE + 09[4]) bit is set and the application can write the next entry of transmit data to the transmit buffer/FIFO through the appropriate register:
• If the byte being written is the last byte to be returned in response to a read from the I3C bus master, write the byte to the WDATABE register, or to the WDATAB register with the WDATAB.END bit also set.

Datasheet for Telink TL3828 DS-TL3828-E5 303 Ver 0.8.0

• If the byte being written is any byte other than the last byte to be returned in response to a read from the I3C bus master, write the byte to the WDATAB register with the WDATAB.END bit not set.
• If there are two bytes of space available in the transmit buffer, the application can write the next two bytes of transmit data to WDATAH or WDATAHE. The DATACTRL_2.TXCOUNT (I3C_BASE + 0x 2e[5:0]) value indicates the number of bytes of data currently in the transmit buffer. NOTE: To use only APB data bits [7:0] when writing bytes other than the last byte of a transmit message, use WDATAB1 instead of WDATAB. When using data from WDATAB1, the I3C does not check bits [15] and [8] for the END (final data byte) indication. Use WDATABE to write the last byte of the transmit message. 6. CCC Handling The I3C automatically handles CCCs related to I3C dynamic address assignment. Handling of other CCCs such as ENEC/DISEC depends on how the I3C is configured. When the I3C receives a CCC that it does not handle automatically, it passes the CCC to the application and sets the STATUS_1.CCC (I3C_BASE + 0x09[6]) bit. This applies to both broadcast CCCs and direct CCCs that match the I3C’s dynamic address. STATUS.CCC is set in the same cycle as STATUS_1.RXPEND (I3C_BASE + 0x09[3]) and the first byte of the recei ved data is the CCC command. Table 11-12 CCC Support Command Code CCC Type Command Name Handled by I3C 0x00 Broadcast ENEC: Enable Events Command Yes 0x01 Broadcast DISEC: Disable Events Command 0x02 Broadcast ENTAS0: Enter Activity State 0 0x03 Broadcast ENTAS1: Enter Activity State 1 0x04 Broadcast ENTAS2: Enter Activity State 2 0x05 Broadcast ENTAS3: Enter Activity State 3 0x06 Broadcast RSTDAA: Reset Dynamic Address Assignment 0x07 Broadcast ENTDAA: Enter Dynamic Address Assignment 0x08 Broadcast DEFTGTS: Define List of Targets Passed to application 0x0b Broadcast ENTTM: Enter Test Mode Passed to application 0x0c Broadcast SETBUSCON: Set Bus Context Passed to application 0x0d-0x11 - MIPI Reserved Passed to application 0x12 Broadcast ENDXFR: Data Transfer Ending Procedure Control Passed to application 0x13-0x1f - MIPI Reserved Passed to application 0x28 Broadcast SETXTIME: Exchange Timing Information Yes 0x29 Broadcast SETAASA: Set Dynamic Address as Static Address Yes

Datasheet for Telink TL3828 DS-TL3828-E5 304 Ver 0.8.0 0x2a Broadcast RSTACT: Target Reset Action Yes 0x2b Broadcast DEFGRPA: Define List of Group Addresses Passed to application 0x2c Broadcast RSTGRPA: Reset Group Address Yes 0x2e--0x60 - MIPI Reserved Passed to application 0x61-0x7f Broadcast Vendor Extension – Broadcast CCCs Passed to application 0x80 Direct ENEC: Enable Events Command Yes 0x81 Direct DISEC: Disable Events Command Yes 0x82 Direct ENTAS0: Enter Activity State 0 Yes 0x83 Direct ENTAS1: Enter Activity State 1 Yes 0x84 Direct ENTAS2: Enter Activity State 2 Yes 0x85 Direct ENTAS3: Enter Activity State 3 Yes 0x86 Direct RSTDAA: Reset Dynamic Address Assignment NACKed 0x87 Direct Set SETDASA: Set Dynamic Address from Static Address Yes 0x88 Direct Set SETNEWDA: Set New Dynamic Address Yes 0x8d Direct Get GETPID: Get Provisioned ID Yes 0x8e Direct Get GETBCR: Get Bus Characteristics Register Yes 0x8f Direct Get GETDCR: Get Device Characteristics Register Yes 0x90 Direct Get GETSTATUS: Get Device Status Yes 0x91 Direct Set GETACCCR: Get Accept Controller Role Yes 0x92 Direct ENDXFR: Data Transfer Ending Procedure Control Passed to application 0x93 Direct Set SETBRGTGT: Set Bridge Targets Passed to application 0x95 Direct Get GETCAPS: Get Optional Feature Capabilities Yes 0x97 Direct D2DXFER: Device to Device(s) Tunneling Control Passed to application 0x98 Direct SETXTIME: Set Exchange Timing Information Yes 0x99 Direct GETXTIME: Get Exchange Timing Information Yes 0x9a Direct RSTACT: Target Reset Action Yes 0x9b Direct SETGRPA: Set Group Address Yes Command Code CCC Type Command Name Handled by I3C

Datasheet for Telink TL3828 DS-TL3828-E5 305 Ver 0.8.0 7. Generating an IBI The I3C supports generation of I3C In-Band Interrupts (IBIs). The IBI includes the slave’s dynamic address and, one or more bytes of payload data. To generate an IBI, the following conditions must be met:

• If the I3C is configured to use CONFIG.BAMATCH as the match value for the 1us Bus Available time counter, the appropriate value must be written to CONFIG.BAMATCH.
• The I3C must have a valid I3C dynamic address. The I3C automatically disables generation of IBIs until i t has been assigned a dynamic address.
• IBIs must be enabled in the I3C bus. The I3C bus master can disable/enable IBIs using DISEC and ENEC CCCs. The I3C automatically handles DISEC and ENEC CCCs and the STATUS.IBIDIS bit indicates whether IBIs are currently disabled. If STATUS.IBIDIS = 1, IBIs are disabled and the I3C will not generate an IBI. The I3C generates IBIs with payload, either the mandatory byte only or wi th extended IBI data bytes after the mandatory byte. To request an IBI with only the mandatory byte, write the mandatory byte to CTRL.IBIDATA and 01 to CTRL.EVENT. NOTE: User can generate the IBI for a mapped address slot by writing the mapped address slot index number to CTRL.MAPIDX when writing 01 to CTRL.EVENT. When CTRL.MAPIDX = 0x0, the IBI is generated with the primary dynami c address assigned to the I3C. To request an IBI with the mandatory data byte and extended IBI data bytes, the extended data bytes can be sent from any of the following sources:
• Transmit buffer/FIFO. Bytes written to the transmit buffer/FIFO are transmitted (after the mandatory byte and any timing control bytes) until either the END indicator is reached or the transmit buffer/FIFO becomes empty.
• IBIEXT1 regi ster and IBIEXT2 register . The IBIEXT1.CNT value controls how many extended IBI data bytes are sent from the IBIEXT1 and IBIEXT2 registers. To request the I3C to generate an IBI with extended IBI data bytes: Step 1 Load the extended IBI data bytes into either the transmit buffer/FIFO or IBIEXT1/IBIEXT2 registers. If you are using the IBIEXT1/IBIEXT2 registers, also set IBIEXT1.CNT to the number of ex tended IBI data bytes that you want to send with the IBI. Step 2 Write the following values to the CTRL register: º CTRL.IBIDATA = Mandatory IBI data byte º CTRL.EXTDATA = 1 º CTRL.EVENT = 01 The I3C generates the IBI at the next START condition on the I3C bus. If the I3C bus remains in the stopped state for more than 1us, the I3C generates a START condition and sends the IBI. The STATUS.EVENT bit i s set to indicate that the I3C has requested an event and STATUS.EVDET indicates the status of the event. 8. Switching to Bus master Role The I3C bus current master can transfer bus control to a master-capable slave by issuing a GETACCCR CCC, either independently or in response to a slave that issues a master request. For the I3C to receive a GETACCCR CCC and respond by switching to master mode, the followi ng conditions must be met:

Datasheet for Telink TL3828 DS-TL3828-E5 306 Ver 0.8.0

• The I3C must be operating in slave mode (CONFIG.TGTENA = 1) and have a valid dynamic address assigned.
• The MCONFIG.CTRENA value must be 10. In addition, the NOWCNTLR interrupt should be enabled in the MINTSET register so that an interrupt is generated when the I3C switches to master mode. Upon receipt of a GETACCCR CCC, the I3C automatically responds by returning its own dynami c address in bits [7:1] and the negative parity of the dynamic address in bit [0]. The I3C bus current master then issues a STOP and the I3C becomes the I3C bus current master and sets the MSTATUS.NOWCNTLR bit. The MCONFIG.CTRENA value automatically changes to 01. Software should then disable slave mode by clearing CONFIG.TGTENA. 9. Requesting Bus Control The I3C supports generation of I3C bus master requests. The I3C can i ssue a bus master request when it is operating in slave mode and the MCONFIG.CTRENA value is 10. The I3C bus master can disable/enable master requests using DISEC and ENEC CCCs. The I3C automatically handles DISEC and ENEC CCCs and the STATUS.MRDIS bit indicates whether master requests are currently disabled. If STATUS.MRDIS = 1, master requests are disabled and the I3C will not generate a master request. To request bus control: Step 1 If I3C i s configured to use CONFIG.BAMATCH as the match value for the 1us Bus Available time counter, write the appropriate value to CONFIG.BAMATCH. Step 2 Enable the NOWCNTLR interrupt in the MINTSET register so that an interrupt is generated when the I3C becomes the I3C bus master. Step 3 Write 10 to CTRL.EVENT to generate the master request. Step 4 The I3C generates a master request at the nex t START event or after the 1us Bus Available time elapses. The STATUS.EVENT bit is set to indicate that the I3C has requested an event and STATUS.EVDET indicates the status of the event. Step 5 When the I3C bus current master issues a GETACCCR CCC to the I3C, the I3C automatically responds by returning its own dynamic address in bits [7:1] and the negati ve parity of the dynamic address in bit [0]. Step 6 The I3C bus current master then issues a stop and the I3C becomes the I3C bus current master and sets the MSTATUS.NOWCNTLR bit. Step 7 Software should then disable slave mode by clearing CONFIG.TGTENA. 10. I3C Timing Control The I3C support Asynchronous Mode 0. In Asynchronous Mode 0, the I3C slave timestamps data so that the master knows when the dat a was sampled even i f there is a delay in delivering the sampled data to the master. When receiving a SETXTIME CCC with the Defining Byte value set to 0xDF (Enter Async Mode 0), the I3C enters Timing Control Asynchronous Mode 0. Subsequent IBIs generated by the I3C include the mandatory payload byte, the meaning of which is established between the I3C slave and master devices. Following the mandatory payload byte, the I3C sends addi tional bytes containing the SC1 and SC2 timestamp data as defined by MIPI Alliance Specification for I3C.

Datasheet for Telink TL3828 DS-TL3828-E5 307 Ver 0.8.0

11.5.4 Register Description of I3C

The I3C related registers are listed as following. For I3C0 related register, the base address is 0x80141400; For I3C1 related register, the base address is 0x80241000. Table 11-13 I3C Related Registers Offset Name Type Description Default Value 0x00 MCONFIG_0 RW [1:0]: CTRENA, Controller device enable: 00: Controller mode off. 01: Controller mode on. 10: Controller mode capable. 11: Reserved [3]: DISTO, Disable timeout error: 1: Disable the timeout error (MERRWARN.TIMEOUT) that occurs when the controller remains in a state other than stopped for more than 100 us. 0: Enable timeout error. [5:4]: HKEEP, High-keeper implementation: 00: No high-keeper support. 01: On-chip high-keeper support. 10: External high-keeper support for SDA. 11: External high-keeper support for SCL and SDA. [6]: ODSTOP, Use open-drain speed for STOP [7]: Reserved 0x00 0x01 MCONFIG_1 RW [3:0]: PPBAUD SCL frequency for push-pull drive [7:4]: PPLOW Number of fclk periods to add to the base SCL low period (set by PPBAUD) for push-pull operation. PPLOW can be used to extend the low period of SCL by up to fifteen fclk periods, thereby altering the SCL duty cycle and the SCL base frequency for push-pull operation as set by PPBAUD. 0x00 0x02 MCONFIG_2 RW [7:0]: ODBAUD Number of PPBAUD periods (minus 1) to make one SCL low period for I3C open-drain operation. 0x00

Datasheet for Telink TL3828 DS-TL3828-E5 308 Ver 0.8.0 0x03 MCONFIG_3 RW [0]: ODHPP, Controls SCL high period for I3C open-drain operation: 1: One PPBAUD period. 0: SCL high period is the same as the SCL low period for I3C open_x005fdrain operation, as set by ODBAUD. [3:1]: SKEW, Number of fclk periods to delay the SDA value change from the SCL edge for I3C push-pull operation. [7:4]: I2CBAUD, Determines SCL high and low periods for I2C mode, in units of ODBAUD period 0x00 0x04 CONFIG_0 RW [0]: TGTENA, Target device enable [1]: Reserved, only write 0 [2]: MATCHSS, Match STOP and START [3]: S0IGNORE, Ignore TE0 and TE1 errors 0x00 0x05 CONFIG_1 RW [1]: OFFLINE Re-join I3C bus with existing dynamic address. When re- enabling the I3C on an I3C bus on which the I3C has already been assigned an I3C dynamic address, set OFFLINE simultaneously with CONFIG.TGTENA. When the OFFLINE bit is set with TGTENA, the I3C waits for either an HDR Exit Pattern or 60 us of I3C bus inactivity, then re-joins the I3C bus using the dynamic address stored in DYNADDR. 0x00 0x06 CONFIG_2 RW [7:0]: BAMATCH The value to be compared with the clk_slow counter value to determine when the 1-us Bus Available time has elapsed for event generation. 0x18 0x07 CONFIG_3 RW [7:1]: SADDR, the 7-bit I2C-style static address 0x00 0x08 STATUS_0 R [0]: STNOTSTOP, Not stopped [1]: STMSG, Message [2]: STCCCH, CCC is being handled [3]: STREQRD, SDR read [4]: STREQWR, SDR write [5]: STDAA, DAA mode 0x00 Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 309 Ver 0.8.0 0x09 STATUS_1 W1C/R [0]: START_DTC, START detected (W1C) [1]: MATCHED, Address matched (W1C) [2]: STOP_DTC, STOP detected (W1C) [3]: RXPEND, Receive (from-bus) data ready (R) [4]: TXNOTFULL, Ready for to-bus (transmit) data (R) [5]: DACHG, Dynamic address changed (W1C) [6]: CCC, CCC received (W1C) [7]: ERRWARN, Error/warning (R) 0x10 0x0a STATUS_2 W1C/R [1]: CHANDLED, CCC handled (W1C) [2]: EVENT_REQ, Event requested: 1: The I3C requested an IBI, Hot-Join, or bus control. 0: The I3C has not requested an IBI, Hot-Join, or bus control since the EVENT bit was last cleared. (W1C) [3]: TGTRST, I3C Target Reset. (W1C) [5:4]: EVDET, Holds the status of the current (when EVENT = 1) or pending event: 00: None. 01: Request not yet sent. Either no START has occurred or the I3C is waiting for Bus Available or Bus Idle. 10: Request was sent and NACKed and will be tried again. 11: Request was sent and ACKed. (R) 0x00 Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 310 Ver 0.8.0 0x0b STATUS_3 R [0]: IBIDIS, Indicates whether IBI events are disabled [1]: MRDIS, Indicates whether bus controller request events are disabled [3]: HJDIS, Indicates whether Hot-Join events are disabled [5:4]: ACTSTATE, Holds the current activity state, as set by most recent ENTASn CCC from the I3C bus controller: 00: No latency; normal bus operation. 01: 1 ms latency. 10: 100 ms latency. 11: 10 s latency. [7:6]: TIMECTRL, TIMECTRL holds the currently enabled timing control mode: 00: No timing control mode is enabled. 01: Timing Control Synchronous Mode is enabled. 10: Timing Control Asynchronous Mode 0 is enabled. 11: Both Synchronous Mode and Asynchronous Mode 0 are enabled. 0x00 0x0c CTRL_0 RW [1:0]: EVENT_REQ, Setting EVENT to a non-zero value directs the I3C to generate the respective event request on the I3C bus: 00: Normal mode (no event requested) 01: IBI – Generate an IBI on the I3C bus. 10: Controller request – Request control of the I3C bus. 11: Hot-Join – Generate a Hot-Join request. [3]: EXTDATA, • EXTDATA = 1 indicates that there are extended IBI data bytes data to be sent when generating an IBI, in addition to the one mandatory byte. EXTDATA = 0 indicates that there is no additional data to be sent when generating an IBI other than the mandatory byte and any timing control bytes. [7:4]: MAPIDX, MAPIDX indicates the index of the dynamic address for the current IBI request. 0x00 0x0d CTRL_1 RW [7:0]: IBIDATA, IBIDATA contains the mandatory data byte to be sent when generating an IBI. 0x00 Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 311 Ver 0.8.0 0x0e CTRL_2 RW [3:0]: PENDINT, PENDINT contains the value to be returned in the Pending Interrupt field of a GETSTATUS CCC. [5:4]: ACTSTATE, ACTSTATE contains the value to be returned in the Activity Mode field of a GETSTATUS CCC 0x00 0x11 INTSET_1 RW [0]: START_DTC, START detected interrupt enable [1]: MATCHED, Address matched interrupt enable [2]: STOP_DTC, STOP detected interrupt enable [3]: RXPEND, Receive (from-bus) data ready interrupt enable [4]: TXNOTFULL, Ready for to-bus (transmit) data interrupt enable [5]: DACHG, Dynamic address changed interrupt enable [6]: CCC, CCC received interrupt enable [7]: ERRWARN, Error/warning interrupt enable 0x00 0x12 INTSET_2 RW [1]: CHANDLED, CCC handled interrupt enable [2]: EVENT_REQ, Event requested interrupt enable [3]: TGTRST, I3C Target Reset interrupt enable 0x08 0x15 INTCLR_1 W [0]: START_DTC, START detected interrupt disable [1]: MATCHED, Address matched interrupt disable [2]: STOP_DTC, STOP detected interrupt disable [3]: RXPEND, Receive (from-bus) data ready interrupt disable [4]: TXNOTFULL, Ready for to-bus (transmit) data interrupt disable [5]: DACHG, Dynamic address changed interrupt disable [6]: CCC, CCC received interrupt disable [7]: ERRWARN, Error/warning interrupt disable 0x00 0x16 INTCLR_2 W [1]: CHANDLED, CCC handled interrupt disable [2]: EVENT_REQ, Event requested interrupt disable [3]: TGTRST, I3C Target Reset interrupt disable 0x00 Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 312 Ver 0.8.0 0x19 INTMASKED_1 R [0]: START_DTC, INTSET_1[0] && STATUS_1[0] [1]: MATCHED, INTSET_1[1] && STATUS_1[1] [2]: STOP_DTC, INTSET_1[2] && STATUS_1[2] [3]: RXPEND, INTSET_1[3] && STATUS_1[3] [4]: TXNOTFULL, INTSET_1[4] && STATUS_1[4] [5]: DACHG, INTSET_1[5] && STATUS_1[5] [6]: CCC, INTSET_1[6] && STATUS_1[6] [7]: ERRWARN, INTSET_1[7] && STATUS_1[7] 0x00 0x1a INTMASKED_2 R [1]: CHANDLED, INTSET_2[1] && STATUS_2[1] [2]: EVENT_REQ, INTSET_2[2] && STATUS_2[2] [3]: TGTRST, INTSET_2[3] && STATUS_2[3] 0x00 0x1c ERRWARN_0 W1C [0]: ORUN, Overrun: 1: The internal from-bus buffer or FIFO was overrun because the application did not drain data fast enough. 0: The internal from-bus buffer or FIFO was not overrun. [1]: URUN, Underrun: 1: The internal to-bus buffer or FIFO was underrun when sending read data because the application did not supply data fast enough. 0: The internal to-bus buffer or FIFO was not underrun when sending read data. [2]: URUNNACK, Underrun caused NACK: 1: The internal to-bus buffer or FIFO was underrun when receiving the address header for a read, so the I3CNACKed the address header. 0: No NACK occurred due to to-bus underrun. [3]: TERM, Controller terminated read [4]: INVSTART, Invalid START 0x00 0x1d ERRWARN_1 W1C [0]: SPAR, SDR parity error [3]: S0S1, TE0 or TE1 error 0x00 Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 313 Ver 0.8.0 0x1e ERRWARN_2 W1C [0]: OREAD, Read data underrun: 1: The RDATAB or RDATAH or RDATAW register was read when empty. 0: The RDATAB or RDATAH or RDATAW register was not read when empty. [1]: OWROTE, Write data overrun: 1: The WDATAB(E) or WDATAH(E) or WDATAW register was written to when full. 0: The WDATAB(E) or WDATAH(E) or WDATAW register was not written to when full. 0x00 0x20 DMACTRL_0 RW [1:0]: DMAFB, DMA read (from-bus) enable: 11: Reserved 10: Enable DMA until DMA is disabled by setting DMAFB to 00. 01: Enable DMA for one frame in SDR mode. When the I3C is operating in SDR mode, DMAFB is automatically cleared on detection of a STOP or START while STATUS.MATCHED is set. To use DMAFB = 01, CONFIG.MATCHSS must first be set to 1 00: Disable DMA. [3:2]: DMATB, DMA write (to-bus) enable: 11: Reserved 10: Enable DMA until DMA is disabled by setting DMATB to 00. 01: Enable DMA for one frame in SDR mode. When the I3C is operating in SDR mode, DMATB is automatically cleared on detection of a STOP or START while STATUS.MATCHED is set. To use DMATB = 01, CONFIG.MATCHSS must first be set to 1. 00: Disable DMA. [5:4]: DMAWIDTH, DMA transfer data width: 11: Reserved 10: Half-word 01: Byte 00: Byte 0x10 Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 314 Ver 0.8.0 0x2c DATACTRL_0 RW [0]: FLUSHTB, Flush transmit FIFO [1]: FLUSHFB, Flush receive FIFO [3]: UNLOCK, Unlock FIFO triggers: 1: Enable writing to bits [7:4] in the current write cycle. 0: Disable writing to bits [7:4] in the current write cycle. [5:4]: TXTRIG, TXTRIG holds the transmit (to-bus) FIFO trigger level: 00: Trigger when empty (not supported for target mode). 01: Trigger when 1/4 full or less. 10: Trigger when 1/2 full or less. 11: Trigger when 1 less than full or less. [7:6]: RXTRIG, RXTRIG holds the receive (from-bus) FIFO trigger level: 00: Trigger when not empty. 01: Trigger when 1/4 full or more. 10: Trigger when 1/2 full or more. 11: Trigger when 3/4 full or more. 0x30 0x2e DATACTRL_2 R [5:0]: TXCOUNT, Number of entries in transmit (to-bus) FIFO. 0x00 0x2f DATACTRL_3 R [5:0]: RXCOUNT, Number of entries in receive (from-bus) FIFO. [6]: TXFULL, Transmit fifo full [7]: RXEMPTY, Receive fifo empty 0x80 0x30 WDATAB_0 W [7:0]: WDATA_B, Data byte to be sent to the I3C or I2C bus controller. 0x00 0x31 WDATAB_1 W [0]: WEND1, End-of-data: 1: The byte in the DATA field is the last data byte of the message. 0: The byte in the DATA field is not the last data byte of the message. Note: Either bit [16] or bit [8] (or both) can be set to indicate end-of-data 0x00 Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 315 Ver 0.8.0 0x32 WDATAB_2 W [0]: WEND2, End-of-data: 1: The byte in the DATA field is the last data byte of the message. 0: The byte in the DATA field is not the last data byte of the message. Note: Either bit [16] or bit [8] (or both) can be set to indicate end-of-data 0x00 0x34 WDATABE_0 W [7:0]: WDATA_BE, The last data byte to be sent to the I3C bus controller for the current message. 0x00 0x38 WDATAH_0 W [7:0]: WDATA_H0, First data byte to be sent to the I3C or I2C bus controller. 0x00 0x39 WDATAH_1 W [7:0]: WDATA_H1, Second data byte to be sent to the I3C or I2C bus controller. 0x00 0x3a WDATAH_2 W [0]: WEND1, End-of-data: 1: The byte in the DATA field is the last data byte of the message. 0: The byte in the DATA field is not the last data byte of the message. 0x00 0x3c WDATAHE_0 W [7:0]: WDATA_HE0, First data byte to be sent to the I3C or I2C bus controller. 0x00 0x3d WDATAHE_1 W [7:0]: WDATA_HE1, Second data byte to be sent to the I3C or I2C bus controller. The I3C sets the End-of-Data bit when transmitting DATA1 on the I3C bus 0x00 0x40 RDATAB_0 R [7:0]: RDATA_B, Read data byte from receive FIFO. 0x00 0x48 RDATAH_0 R [7:0]: RDATA_H0, Read data byte from receive FIFO. 0x00 0x49 RDATAH_1 R [7:0]: RDATA_H1, Second read data byte from receive FIFO. 0x00 0x54 WDATAB1 W [7:0]: WDATA_B1, Data byte to be sent to the I3C bus controller. 0x00 0x5c CAPABILITIES2_0 R [3:0]: MAPCNT, Number of mapped target addresses supported [4]: I2C10B, I2C 10-bit address support 0x14 Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 316 Ver 0.8.0 0x5d CAPABILITIES2_1 R [0]: IBIEXT, support extended IBI data [1]: IBIXREG, support extended IBI data register IBIEXT1 and IBIEXT2 [5:4]: SMLINE, Single-lane only 0x3 0x5e CAPABILITIES2_2 R [0]: V1_1, support GETCAPS ccc [1]: TGTRST, support target reset [3:2]: GROUP, support group address and group address count = 3 [5]: AASA, support SETAASA ccc 0x2f 0x60 CAPABILITIES_0 R [1:0]: IDENA, Provisioned ID implementation [5:2]: IDREG, Provisioned ID, BCR, DCR implementation 0x01 0x61 CAPABILITIES_1 R [1]: CNTLR, Controller mode capable. [3:2]: SADDR, I2C-style static address implementation [7:4]: CCCHANDLE, CCCs handled by I3C (in addition to the minimum set of CCCs required for basic I3C operation) 0x5e 0x62 CAPABILITIES_2 R [4:0]: IBI_MR_HJ, Supported events: [4]: Use BAMATCH field of CONFIG register to measure 1- us Bus Available timing [3]: Hot-Join support [2]: Controller request support [1]: IBI has payload [0]: IBI support [5]: TIMECTRL, Timing Control support 0x3f 0x63 CAPABILITIES_3 R [3:2]: FIFOTX, Internal transmit (to-bus) FIFO configuration: [5:4]: FIFORX, Internal receive (from-bus) FIFO configuration [6]: INT_SUPPORT, Interrupt support [7]: DMA_SUPPORT, DMA support 0xfd Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 317 Ver 0.8.0 0x64 DYNADDR_0 R [0]: DAVALID, Address valid: 1: The address in the DADDR field is valid. 0: The address in the DADDR field is not valid. [7:1]: DADDR, The dynamic address assigned to this I3C target device. 0x00 0x65 DYNADDR_1 R [2:0]: CAUSE, CAUSE indicates how the last primary dynamic address (DA) value change occurred: 0: No change to DA. 1: Primary DA was last assigned by ENTDAA. 2: Primary DA was last assigned by SETDASA, SETAASA, or SETNEWDA. 3: Primary DA was cleared by RSTDAA. 4: Primary DA was changed due to a mapped address related operation. 0x00 0x78 TCCLOCK_0 RW [7:0]: ACCURACY, Maximum variation of the Timing Control clock source in 0.1% units. 0x00 0x79 TCCLOCK_1 RW [7:0]: FREQ, Frequency of the Timing Control clock source in 0.5-MHz units. 0x30 0x7c MSGLAST_0 R [3:0]: MAPLAST, Index or group number of last matched address [4]: LASTSTATIC, Last matched address was a static address [5]: LASTGROUP, the last matched address was a group address 0x00 0x7d MSGLAST_1 R [3:0]: MAPLASTM1, Index or group of previously matched address – Similar to MAPLAST, but applies to previously matched address. [5]: LASTGROUPM1, Group address indicator of previous access – Similar to LASTGROUP, but applies to previous access. 0x00 Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 318 Ver 0.8.0 0x7e MSGLAST_2 R [3:0]: MAPLASTM2, Index or group of second previously matched address – Similar to MAPLAST, but applies to second previously matched address. [5]: LASTGROUPM2, Group address indicator of second previous access – Similar to LASTGROUP, but applies to second previous access. 0x00 0x84 MCTRL_0 RW [2:0]: REQUEST, Requests an I3C or I2C bus operation: 000: None. 001: EmitStartAddr. 010: EmitStop. 011: IBIAckNack. 100: ProcessDAA. 101: Reserved 110: ForceExit/Target Reset: 111: AutoIBI. [5:4]: CTRL_TYPE, Controls type of operation when REQUEST = EmitStartAddr ForceExit/Target Reset. [7:6]: IBIRESP, Response to use when an IBI occurs. 0x00 0x85 MCTRL_1 RW [0]: DIR, Direction of the transfer: 1: Read 0: Write [7:1]: ADDR, Address to send with START 0x00 0x86 MCTRL_2 RW [7:0]: RDTERM, Termination count for read: For I2C mode read, the I3C NACKs the read after receiving RDTERM bytes. For I3C SDR mode read, the I3C aborts the read after RDTERM bytes if the target has not yet sent End-of-Data. 0x00 Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 319 Ver 0.8.0 0x88 MSTATUS_0 RW [2:0]: STATE, Indicates the current working state of the I3C: 000: IDLE. The I3C bus is stopped. 001: TGTREQ. The I3C bus is stopped and a target is holding SDA low. If MCTRL.REQUEST = AutoIBI, IBI processing starts automatically and the I3C does not remain in the TGTREQ state. 010: MSGSDR. The I3C is in SDR message mode initiated using MWMSG_SDR. 011: NORMACT. The I3C is in SDR message mode, using MCTRL and MWDATAB/H(E) and MRDATAB/H. The I3C remains in NORMACT mode until STOP is issued. 101: DAA. The I3C is in DAA mode. 110: IBIACK: The I3C is waiting for the application to provide an ACK/NACK decision. 111: IBIRCV. The I3C is receiving an IBI. [4]: BETWEEN, When STATE = MSGSDR, BETWEEN is 1 when the I3C is between messages and is waiting for the next message to be initiated. When STATE = DAA, BETWEEN is 1 when the I3C is waiting for the application to provide a dynamic address for the target for which the Provisioned ID was just read. When STATE = NORMACT, BETWEEN is 1 when the I3C is stalled waiting for the transmit buffer to be not-empty or the receive buffer to be not-full. [5]: NACKED, Address NACKed [7:6]: IBITYPE, The type of event for which arbitration was last won: 00: None 01: IBI 10: Controller request 11: Hot-Join request 0x00 Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 320 Ver 0.8.0 0x89 MSTATUS_1 W1C/R [0]: TGTSTART, Target START detected (W1C) [1]: MCTRLDONE, MCTRL request completed (W1C) [2]: COMPLETE, Message completed (W1C) [3]: RXPEND, Receive (from-bus) data ready (R) [4]: TXNOTFULL, Ready for to-bus (transmit) data (R) [5]: IBIWON, IBI arbitration won (W1C) [7]: ERRWARN, Error/warning (R) 0x10 0x8a MSTATUS_2 W1C [3]: NOWCNTLR, I3C transitioned from I3C bus target to I3C bus controller 0x00 0x8b MSTATUS_3 R [6:0]: IBIADDR, The address of a received IBI (when IBITYPE = 1) or controller request (when IBITYPE = 2), or 7’h2 for a Hot-Join request (IBITYPE = 3). 0x00 0x8c IBIRULES_0 RW [5:0]: ADDR0, Target 0 dynamic address. [7:6]: ADDR1_0, Target 1 dynamic address[1:0] 0x00 0x8d IBIRULES_1 RW [3:0]: ADDR1_1, Target 1 dynamic address[5:2] [7:4]: ADDR2_0, Target 2 dynamic address[3:0] 0x00 0x8e IBIRULES_2 RW [1:0]: ADDR2_1, Target 2 dynamic address[5:4] [7:2]: ADDR3, Target 3 dynamic address. 0x00 0x8f IBIRULES_3 RW [5:0]: ADDR4, Target 4 dynamic address. [6]: MSB0, Implementation of MSb for I3C dynamic addresses: 1: All I3C dynamic addresses have MSb = 0. 0: I3C dynamic addresses may have MSb = 0 or MSb = 1. [7]: NOBYTE, Specifies the function of ADDR0–ADDR4: 1: ADDR0–ADDR4 are dynamic addresses of I3C targets that do not provide a mandatory byte when sending an IBI. 0: ADDR0–ADDR4 are dynamic addresses of I3C targets that provide a mandatory byte when sending an IBI. 0x00 Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 321 Ver 0.8.0 0x91 MINTSET_1 RW [0]: TGTSTART, Target START detected interrupt enable [1]: MCTRLDONE, MCTRL request completed interrupt enable [2]: COMPLETE, Message complete interrupt enable [3]: RXPEND, Receive data ready interrupt enable [4]: TXNOTFULL, Ready for transmit data interrupt enable [5]: IBIWON, IBI arbitration won interrupt enable [7]: ERRWARN, Error/warning interrupt enable 0x00 0x92 MINTSET_2 RW [3]: NOWCNTLR, Now controller interrupt enable 0x00 0x95 MINTCLR_1 W [0]: TGTSTART, Target START detected interrupt disable [1]: MCTRLDONE, MCTRL request completed interrupt disable [2]: COMPLETE, Message complete interrupt disable [3]: RXPEND, Receive data ready interrupt disable [4]: TXNOTFULL, Ready for transmit data interrupt disable [5]: IBIWON, IBI arbitration won interrupt disable [7]: ERRWARN, Error/warning interrupt disable 0x00 0x96 MINTCLR_2 W [3]: NOWCNTLR, Now controller interrupt disable 0x00 0x99 MINTMASKED_1 R [0]: TGTSTART, MINTSET_1[0] && MSTATUS_1[0] [1]: MCTRLDONE, MINTSET_1[1] && MSTATUS_1[1] [2]: COMPLETE, MINTSET_1[2] && MSTATUS_1[2] [3]: RXPEND, MINTSET_1[3] && MSTATUS_1[3] [4]: TXNOTFULL, MINTSET_1[4] && MSTATUS_1[4] [5]: IBIWON, MINTSET_1[5] && MSTATUS_1[5] [7]: ERRWARN, MINTSET_1[7] && MSTATUS_1[7] 0x00 0x9a MINTMASKED_2 R [3]: NOWCNTLR, MINTSET_2[7] && MSTATUS_2[7] 0x00 0x9c MERRWARN_0 W1C [2]: NACK, Address NACKed [3]: WRABT, Write aborted due to data NACK [4]: TERM, Controller terminated read in message mode 0x00 Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 322 Ver 0.8.0 0x9e MERRWARN_2 W1C [0]: OREAD, Read data underrun [1]: OWRITE, Write data overrun [2]: MSGERR, Message mode error [3]: INVREQ, Invalid use of request: 1: The application wrote a request to MCTRL.REQUEST that is not allowed in the current state of the I3C. 0: The application did not write an invalid request to MCTRL.REQUEST [4]: TIMEOUT, Controller timeout. [5]: WRONGSIZE, Wrong data register used for current transfer mode 0x00 Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 323 Ver 0.8.0 0xa0 MDMACTRL_0 RW [1:0]: DMAFB, DMA read (from-bus) enable: 11: Reserved 10: Enable DMA until DMA is disabled by setting DMAFB to 00. 01: Enable DMA for one frame in SDR mode. When the I3C is operating in SDR mode, DMAFB is automatically cleared on detection of a STOP or START while STATUS.MATCHED is set. To use DMAFB = 01, CONFIG.MATCHSS must first be set to 1 00: Disable DMA. [3:2]: DMATB, DMA write (to-bus) enable: 11: Reserved 10: Enable DMA until DMA is disabled by setting DMATB to 00. 01: Enable DMA for one frame in SDR mode. When the I3C is operating in SDR mode, DMATB is automatically cleared on detection of a STOP or START while STATUS.MATCHED is set. To use DMATB = 01, CONFIG.MATCHSS must first be set to 1. 00: Disable DMA. [5:4]: DMAWIDTH, DMA transfer data width: 11: Reserved 10: Half-word 01: Byte 00: Byte Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 324 Ver 0.8.0 0xac MDATACTRL_0 W/RW [0]: FLUSHTB, Flush transmit FIFO [1]: FLUSHFB, Flush receive FIFO [3]: UNLOCK, Unlock FIFO triggers: 1: Enable writing to bits [7:4] in the current write cycle. 0: Disable writing to bits [7:4] in the current write cycle." [5:4]: TXTRIG, TXTRIG holds the transmit (to-bus) FIFO trigger level: 00: Trigger when empty (not supported for target mode). 01: Trigger when 1/4 full or less. 10: Trigger when 1/2 full or less. 11: Trigger when 1 less than full or less. [7:6]: RXTRIG, RXTRIG holds the receive (from-bus) FIFO trigger level: 00: Trigger when not empty. 01: Trigger when 1/4 full or more. 10: Trigger when 1/2 full or more. 11: Trigger when 3/4 full or more. 0xae MDATACTRL_2 R [5:0]: TXCOUNT, Number of entries in transmit (to-bus) FIFO. 0x00 0xaf MDATACTRL_3 R [5:0]: RXCOUNT, Number of entries in receive (from-bus) FIFO. [6]: TXFULL, Transmit fifo full [7]: RXEMPTY, Receive fifo empty 0x80 0xb0 MWDATAB W [7:0]: MWDATA_B, Data byte to be sent to the I3C or I2C bus controller. 0x00 0xb1 MWDATAB_1 W [0]: MWEND1, End-of-data: 1: The byte in the DATA field is the last data byte of the message. 0: The byte in the DATA field is not the last data byte of the message. Note: Either bit [16] or bit [8] (or both) can be set to indicate end-of-data 0x00 Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 325 Ver 0.8.0 0xb2 MWDATAB_2 W [0]: MWEND2, End-of-data: 1: The byte in the DATA field is the last data byte of the message. 0: The byte in the DATA field is not the last data byte of the message. Note: Either bit [16] or bit [8] (or both) can be set to indicate end-of-data 0x00 0xb4 MWDATABE_0 W [7:0]: MWDATA_BE, The last data byte to be sent to the I3C bus controller for the current message. 0x00 0xb8 MWDATAH_0 W [7:0]: MWDATA_H0, First data byte to be sent to the I3C or I2C bus controller. 0x00 0xb9 MWDATAH_1 W [7:0]: MWDATA_H1, Second data byte to be sent to the I3C or I2C bus controller. 0x00 0xba MWDATAH_2 W [0]: MWEND1, End-of-data: 1: The byte in the DATA field is the last data byte of the message. 0: The byte in the DATA field is not the last data byte of the message. 0x00 0xbc MWDATAHE_0 W [7:0]: MWDATA_HE0, First data byte to be sent to the I3C or I2C bus controller. 0x00 0xbd MWDATAHE_1 W [7:0]: MWDATA_HE1, Second data byte to be sent to the I3C or I2C bus controller. The I3C sets the End-of-Data bit when transmitting DATA1 on the I3C bus 0x00 0xc0 MRDATAB_0 R [7:0]: MRDATA_B, Read data byte from receive FIFO. 0x00 0xc8 MRDATAH_0 R [7:0]: MRDATA_H0, Read data byte from receive FIFO. 0x00 0xc9 MRDATAH_1 R [7:0]: MRDATA_H1, Second read data byte from receive FIFO. 0x00 0xcc MWDATAB1 W [7:0]: MWDATA_B1, Data byte to be sent to the I3C bus controller. 0x00 Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 326 Ver 0.8.0 0xd0 MWMSG_SDR_0 W [0]: DIR, Control information – Direction: 1: Read 0: Write [7:1]: ADDR, Control information – Destination address of message 0x00 0xd1 MWMSG_SDR_1 W [0]: MWEND, Control information – How to end message: 1: End by emitting STOP. 0: End waiting for new SDR message. The I3C issues a repeated START for the new message. The I3C sets STATUS.COMPLETE when the message is complete. The message may complete before LEN bytes are written/ read in the following cases: An I2C target NACKs write data before LEN bytes are written. An I3C target sends End-of-Data before LEN bytes are read [2]: I2C, Control information – I2C mode: 1: I2C mode 0: I3C mode [7:3]: MWLEN, Control information – Message length in bytes. 0x00 0xd4 MRMSG_SDR_0 R [7:0]: DATA_0, RDATA[7:0] 0x00 0xd5 MRMSG_SDR_1 R [7:0]: DATA_1, RDATA[15:8] 0x00 0xe4 MDYNADDR_0 RW [0]: DAVALID, Address valid: 1: The address in the DADDR field is valid. 0: The address in the DADDR field is not valid. [7:1]: DADDR, The dynamic address assigned to this I3C target device. 0x00 0x100 RSTACTTIME_0 RW [7:0]: PERRSTTIM, Value of the I3C peripheral reset time to be returned in response to an RSTACT CCC. 0x01 0x114 GROUPDEF_0 R [0]: GRP0ENA, Group address 0 enabled: [7:1]: GRP0DA, The assigned address for group address 0, valid when GRP0ENA = 1. 0x00 Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 327 Ver 0.8.0 0x115 GROUPDEF_1 R [0]: GRP1ENA, Group address 1 enabled: [7:1]: GRP1DA, The assigned address for group address 1, valid when GRP1ENA = 1. 0x00 0x116 GROUPDEF_2 R [0]: GRP2ENA, Group address 2 enabled: [7:1]: GRP2DA, The assigned address for group address 2, valid when GRP2ENA = 1. 0x00 0x11c MAPTRL0_0 R [0]: DAVALID, Address valid: 1: The address in the DADDR field is valid. 0: The address in the DADDR field is not valid. [7:1]: DADDR, The dynamic address assigned to this I3C target device. 0x00 0x11d MAPTRL0_1 R [2:0]: CAUSE, CAUSE indicates how the last primary dynamic address (DA) value change occurred: 0: No change to DA. 1: Primary DA was last assigned by ENTDAA. 2: Primary DA was last assigned by SETDASA, SETAASA, or SETNEWDA. 3: Primary DA was cleared by RSTDAA. 4: Primary DA was changed due to a mapped address related operation. 0x00 0x120 MAPTRL1_0 RW [0]: ENA, Slot enable [7:1]: ADDR, the ADDR field contains the static or dynamic address assigned to this mapped address slot. 0x00 Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 328 Ver 0.8.0 0x121 MAPTRL1_1 RW [0]: MAPSA, Static address: 1: When ENA = 1, the ADDR field contains an I2C static address. 0: When ENA = 1, the ADDR field contains an I3C dynamic address. [3:1]: SA10B, For MAPCTRL1, SA10B contains the upper 3 bits of a 10-bit I2C static address [4]: NACK, NACK incoming addresses that match this mapped address [5]: AUTO, Enable slot for automatic dynamic address assignment using ENTDAA CCC [7:6]: PID_1, Slot-specific PID replacement bits [1:0]. 0x00 0x122 MAPTRL1_2 RW [7:0]: PID_2, Slot-specific PID replacement bits [9:2]. 0x00 0x123 MAPTRL1_3 RW [7:0]: DCR, the DCR field, containing the slot-specific DCR value. 0x00 0x124 MAPTRL2_0 RW [0]: ENA, Slot enable [7:1]: ADDR, the ADDR field contains the static or dynamic address assigned to this mapped address slot. 0x00 0x125 MAPTRL2_1 RW [0]: MAPSA, Static address: 1: When ENA = 1, the ADDR field contains an I2C static address. 0: When ENA = 1, the ADDR field contains an I3C dynamic address. [4]: NACK, NACK incoming addresses that match this mapped address [5]: AUTO, Enable slot for automatic dynamic address assignment using ENTDAA CCC [7:6]: PID_1, Slot-specific PID replacement bits [1:0]. 0x00 0x126 MAPTRL2_2 RW [7:0]: PID_2, Slot-specific PID replacement bits [9:2]. 0x00 0x127 MAPTRL2_3 RW [7:0]: DCR, the DCR field, containing the slot-specific DCR value. 0x00 Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 329 Ver 0.8.0 0x128 MAPTRL3_0 RW [0]: ENA, Slot enable [7:1]: ADDR, the ADDR field contains the static or dynamic address assigned to this mapped address slot. 0x00 0x129 MAPTRL3_1 RW [0]: MAPSA, Static address: 1: When ENA = 1, the ADDR field contains an I2C static address. 0: When ENA = 1, the ADDR field contains an I3C dynamic address. [4]: NACK, NACK incoming addresses that match this mapped address [5]: AUTO, Enable slot for automatic dynamic address assignment using ENTDAA CCC [7:6]: PID_1, Slot-specific PID replacement bits [1:0]. 0x00 0x12a MAPTRL3_2 RW [7:0]: PID_2, Slot-specific PID replacement bits [9:2]. 0x00 0x12b MAPTRL3_3 RW [7:0]: DCR, the DCR field, containing the slot-specific DCR value. 0x00 0x12c MAPTRL4_0 RW [0]: ENA, Slot enable [7:1]: ADDR, the ADDR field contains the static or dynamic address assigned to this mapped address slot. 0x00 0x12d MAPTRL4_1 RW [0]: MAPSA, Static address: 1: When ENA = 1, the ADDR field contains an I2C static address. 0: When ENA = 1, the ADDR field contains an I3C dynamic address. [4]: NACK, NACK incoming addresses that match this mapped address [5]: AUTO, Enable slot for automatic dynamic address assignment using ENTDAA CCC [7:6]: PID_1, Slot-specific PID replacement bits [1:0]. 0x00 0x12e MAPTRL4_2 RW [7:0]: PID_2, Slot-specific PID replacement bits [9:2]. 0x00 Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 330 Ver 0.8.0

11.6 LSPI

11.6.1 LSPI Diagram

LSPI module is a controller which serves as a SPI master to access external LCD. Features of LSPI are listed as following:

• Supports SPI Master/Slave mode
• Supports Dual line, Quad line and 3 line I/O SPI interface
• Supports XIP function
• Supports DMA transmission
• Supports DMA burst transmission, tx_dma up to burst4, rx_dma up to burst2
• Supports LCD driving with SPI ports 0x12f MAPTRL4_3 RW [7:0]: DCR, the DCR field, containing the slot-specific DCR v alue. 0x00 0x140 IBIEXT1_0 RW [2:0]: CNT, The number of extended IBI data bytes to send from the IBIEXT1 and IBIEXT2 registers. [6:4]: MAX_NUM, The maximum number of extended IBI data bytes that can be sent using the IBIEXT1 and IBIEXT2 registers. 0x70 0x141 IBIEXT1_1 RW [7:0]: EXT1, EXT1 stores the first extended IBI data byte to send with an IBI. 0x00 0x142 IBIEXT1_2 RW [7:0]: EXT2, EXT2 stores the second extended IBI data byte to send with an IBI. 0x00 0x143 IBIEXT1_3 RW [7:0]: EXT3, EXT3 stores the third extended IBI data byte to send with an IBI. 0x00 0x144 IBIEXT2_0 RW [7:0]: EXT4, EXT4 stores the fourth extended IBI data byte to send with an IBI. 0x70 0x145 IBIEXT2_1 RW [7:0]: EXT5, EXT5 stores the fifth extended IBI data byte to send with an IBI. 0x00 0x146 IBIEXT2_2 RW [7:0]: EXT6, EXT6 stores the sixth extended IBI data byte to send with an IBI 0x00 0x147 IBIEXT2_3 RW [7:0]: EXT7, EXT7 stores the seventh extended IBI data byte to send with an IBI 0x00 Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 331 Ver 0.8.0

• Up to 48 MHz SPI clock. However, to achieve 48 MHz, specific pin configurations must be used as follows: Table 11-14 LSPI Specific Pin Configurations The LSPI diagram is shown as below: Figure 11-22 LSPI Diagram As shown in the diagram, AHB_BUS is used to configure the direct address mapping of registers and XIP. DMA_BUS is the bus between the SPI module and the DMA module. SPI_BUS is the SPI interface connected to the pad. The spi_regif is to parse the AHB protocol and send i t to the spi_reg module for register configuration. The spi_ctrl module selects the state and mode according to the value of the register configuration, and controls the format of the transmitted data. Pin LSPI Signal PA[0] LSPI_CK PA[1] LSPI_IO3 PA[2] LSPI_IO2 PB[1] LSPI_MISO PB[2] LSPI_MOSI txfifo rxfifo spi_fifo xip_ctrl spi_regif spi_reg spi_dmaif spi_ctrl rxshift[7:0] spi_cn spi_dat[3:0] hclk spi_if LSPI sync sclk txshift[25:0] SPI_FSM hslv AHB Bus SPI_OSD LCD_FSM spi_ck

Datasheet for Telink TL3828 DS-TL3828-E5 332 Ver 0.8.0 The spi_if module adjusts the characteristics of the SPI rate or polarity of transmission and reception according to the configuration. The XIP module takes effect when it is configured in XIP mode, and its role is to directly map ahb_bus to SPI_BUS. The spi_fifo serves as a buffer for sending and receiving data.

11.6.2 Register Description of LSPI

The LSPI related registers are listed as below. The base address of the followi ng registers is 0x87FFFF00. Table 11-15 LSPI Related Registers Address Offset Name Type Description Default Value 0x00 LSPI_WR_RD_DATA0 RW [7:0]: data[7:0] to transmit or received 0x00 0x01 LSPI_WR_RD_DATA1 RW [7:0]: data[15:8] to transmit or received 0x00 0x02 LSPI_WR_RD_DATA2 RW [7:0]: data[23:16] to transmit or received 0x00 0x03 LSPI_WR_RD_DATA3 RW [7:0]: data[31:24] to transmit or received 0x00 0x04 LSPI_CMD RW [7:0]: SPI Command 0x00 0x05 LSPI_CTRL0 RW [0]: rxf_overrun_int_en, enable the SPI Receive FIFO Overrun interrupt, SLAVE ONLY [1]: txf_underrun_int_en, enable the SPI Transmit FIFO Underrun interrupt, SLAVE ONLY [2]: rxf_thres_int_en, enable the SPI Receive FIFO Threshold interrupt [3]: txf_thres_int_en, enable the SPI Transmit FIFO Threshold interrupt [4]: trans_end_int_en, enable the End of SPI Transfer interrupt [5]: slave_cmd_int_en, enable the Slave Command Interrupt, SLAVE ONLY [6]: rx_dma_en, RX DMA enable [7]: tx_dma_en, TX DMA enable 0x00 0x06 LSPI_REG_CMD1 RW [7:0] reg_cmd1 0x00

Datasheet for Telink TL3828 DS-TL3828-E5 333 Ver 0.8.0 0x07 LSPI_TIMING RW [2:0] cs2sclk, the minimum time between the edge of SPI_CS and the edges of SPI_CLK. The actual duration is (SPI_CLK period*(cs2sclk+1)), MASTER ONLY [7:3] csht_low, the minimum time that SPI CS should stay HIGH. The actual duration is (SPI_CLK period*(csht+1)), MASTER ONLY actual_csht[6:0] = {csht_high, csht_low} 0x09 0x08 LSPI_CTRL1 RW [1:0] data_lane, data lane, MASTER ONLY 0: single, 1: dual, 2: quad, 3: quad [3:2] addr_len, 2'b00:1bye; 2'b01:2bytes; 2'b10:3bytes; 2'b11:4bytes, MASTER ONLY [4] addr_fmt, 0:single mode 1:the format of addr phase is the same as the data phase(Dual/Quad), MASTER ONLY [5] addr_en, 1:enabel addr phase, MASTER ONLY [6] cmd_fmt, 0: single mode 1: the format of the cmd phase is the same as the data phase(Dual/ Quad), MASTER ONLY [7] cmd_en, the spi commnd phase enable, MASTER ONLY 0xa9 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 334 Ver 0.8.0 0x09 LSPI_CTRL2 RW [3:0] dummy_cnt, dummy number = {dummy_cnt_add, dummy_cnt} + 1 [7:4] transmode, the transfer mode the transfer sequence could be: 0x0:write and read at the same time (must enable CmdEn) 0x1:write only 0x2:read only (must enable CmdEn) 0x3:write,read 0x4:read,write 0x5:write,dummy,read 0x6:read,dummy,write (must enable CmdEn) 0x7:None Data (must enable CmdEn) 0x8:Dummy,write 0x9:Dummy,read 0xa:Dummy, write and read 0xb~0xf:reserved 0x77 0x0a LSPI_REG_CTRL0 RW [0] cmd1_en [1] reg_token_val_sel. 1:8'h69, 0:8'h00 [2] reg_token_en [3] reg_ddr_mode [5:4] csht_high 0x0 0x0b LSPI_XIP_WR_TCEM_SET RW [7:0] xip_wr_tcem_set 0x0 0x0c LSPI_ADDR0 RW [7:0] spi_addr0, spi address byte0/ lcd_porch_line_time[7:0] 0x0 0x0d LSPI_ADDR1 RW [7:0] spi_addr1, spi address byte1/ lcd_porch_line_time[15:8] 0x0 0x0e LSPI_ADDR2 RW [7:0] spi_addr2, spi address byte2/ lcd_display_line_time[7:0] 0x0 0x0f LSPI_ADDR3 RW [7:0] spi_addr3, spi address byte3/ lcd_display_line_time[15:8] 0x0 0x10 LSPI_TX_CNT0 RW [7:0] tx_cnt0, transfer count for write data, byte0/ lcd_pixel_per_line[7:0] 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 335 Ver 0.8.0 0x11 LSPI_TX_CNT1 RW [7:0] tx_cnt1, transfer count for write data, byte1/ {lcd_line_per_frame[5:0], lcd_pixel_per_line[9:8]} 0x00 0x12 LSPI_TX_CNT2 RW [7:0] tx_cnt2, transfer count for write data, byte2/ {4'h0, lcd_line_per_frame[9:6]} 0x00 0x14 LSPI_RX_CNT0 RW [7:0] rx_cnt0, transfer count for read data, byte0 0x00 0x15 LSPI_RX_CNT1 RW [7:0] rx_cnt1, transfer count for read data, byte1 0x00 0x16 LSPI_RX_CNT2 RW [7:0] rx_cnt2, transfer count for read data, byte2 0x00 0x18 LSPI_CTRL3 RW [0] spi_lsb, transfer data with least significant bit first [1] spi_3line, MOSI is bi-directional signal in regular mode [3:2] spi_mode, spi_mode[0]:SPI_CLK Phase; spi_mode[1]:SPI_CLK Polarity [4] spi_master, SPI master mode selection [5] dmatx_sof_clrtxfifo_en, auto clr txfifo when txdma start [6] dmarx_eof_clrrxfifo_en, auto clr rxfifo when rxdma end [7] auto_hready_en, auto control hready while access data register 0x90 0x19 LSPI_TXFIFO_THRES RW [5:0] txfifo threshold 0x00 0x1a LSPI_RXFIFO_THRES RW [5:0] rxfifo threshold 0x00 0x1b LSPI_PEM_CTRL0 RW [0] reg_event_en [1] reg_task_en [2] reg_pem_event_sel 0x00 0x1c LSPI_CTRL4 RW [0] dma_trig_spi_en [1] txdma_req_after_cmd [2] xip_stop, stop xip [3] xip_enable, enable xip [4] dummy_cnt_add 0x0a 0x1d LSPI_XIP_PAGE_SIZE RW [7:0] page_size, page boundary size = 2^page_size 0x00 0x1e LSPI_XIP_TIMEOUT_CNT RW [7:0] timeout_cnt, timeout time sel 0x20 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 336 Ver 0.8.0 0x1f LSPI_XIP_RD_TCEM_SET RW [7:0] xip_rd_tcem_set 0x00 0x22 LSPI_XIP_ADDR_OFFSET RW [7:0] xip_addr_offset, address offset = xip_addr_offset << 24 0x00 0x24 LSPI_TXFIFO_STATUS R [6:0] txfifo_entries [7] txfifo_full 0x0 0x25 LSPI_RXFIFO_STATUS R [6:0] rxfifo_entries [7] rxfifo_empty 0x0 0x28 LSPI_STATUS RW/R [0] set_slave_ready(RW), set this bit to indicate that spi as salve is ready for data transaction [1] clr_slave_ready(RW), clear spi slave ready [2] spi_soft_reset(RW), spi soft reset, high valid [3] xip_reg_arb_err(R), xip mode and reg mode conflict flag [4] rxfifo_clr_level(RW), rxfifo is in clear status [5] txfifo_clr_level(RW), txfifo is in clear status [6] osd_ahbmst_busy(R), osd ahbmster is in busy status [7] busy(R), SPI is transferring 0x0 0x29 LSPI_SLV_TRANS_MODE RW [3:0] slv_trans_mode 0x07 0x2a LSPI_INT_STATUS0 W1C [0] rxf_overrun_int_stus, RX FIFO Overrun interrupt, SLAVE ONLY [1] txf_underrun_int_stus, TX FIFO Underrun interrupr, SLAVE ONLY [2] rxf_thres_int_stus, RX FIFO Threshold interrupt [3] txf_thres_int_stus, TX FIFO Threshold interrupt [4] trans_end_int_stus, End of SPI Transfer interrupt [5] slave_cmd_int_stus, Slave Command Interrupt, SLAVE ONLY 0x00 0x2b LSPI_INT_STATUS1 W1C [0] lcd_line_int_stus, lcd line interrupt status [1] lcd_lvl_int_stus, lcd line level interrupt status [2] lcd_frame_int_stus, lcd frame interrupt status 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 337 Ver 0.8.0 0x2f LSPI_LCD_CTRL2 RW [0] lcd_single_color_mode, 1: single color mode, use lut1 [1] lcd_rgb_big_endian_mode, 1:big endian mode; 0:little endian mode [2] lcd_ram_4bit_mode [5:3] lcd_int_mask, lcd interrupt mask, [3]: lcd_line_irq_mask [4]: lcd_line_lvl_irq_mask [5]: lcd_frame_irq_mask [6] lcd_off_bimage [7] lcd_off_fimage 0x00 0x30 LSPI_LCD_CTRL RW [0] lcd_scan_en, scan lcd enable [2:1] lcd_rgb_mode, 0:rsvd; 1:565; 2:666; 3:888 [3] lcd_2lane_en, 1: 2 data lane enable in ram lcd mode [6] line3_dcx_en, 1:enable 3line mode [7] dcx, 1:set dcx filed to 1 0x00 0x31 LSPI_LCD_VBP_CNT RW [7:0] lcd_vbp_cnt, lcd vertical porch line number, actual num=lcd_vbp_cnt 0x00 0x32 LSPI_LCD_VFP_CNT RW [7:0] lcd_vfp_cnt, lcd front porch line number, actual num=lcd_vbp_cnt 0x00 0x33 LSPI_LCD_LINE_LVL RW [7:0] lcd_line_lvl, lcd line threshold to trig interrupt 0x00 0x34 LSPI_LCD_BIMAGE_ADDR0 RW [7:5] lcd_bimage_start_addr0, background image data start address byte0 0x00 0x35 LSPI_LCD_BIMAGE_ADDR1 RW [7:0] lcd_bimage_start_addr1, background image data start address byte1 0x00 0x36 LSPI_LCD_BIMAGE_ADDR2 RW [7:0] lcd_bimage_start_addr2, background image data start address byte2 0x00 0x37 LSPI_LCD_BIMAGE_ADDR3 RW [6:0] lcd_bimage_start_addr3, background image data start address byte3 0x00 0x38 LSPI_LCD_FIMAGE_ADDR0 RW [7:4] lcd_fimage_start_addr0, front image data start address byte0 0x00 0x39 LSPI_LCD_FIMAGE_ADDR1 RW [7:0] lcd_fimage_start_addr0, front image data start address byte1 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 338 Ver 0.8.0 0x3a LSPI_LCD_FIMAGE_ADDR2 RW [7:0] lcd_fimage_start_addr0, front image data start address byte2 0x00 0x3b LSPI_LCD_FIMAGE_ADDR3 RW [6:0] lcd_fimage_start_addr0, front image data start address byte3 0x00 0x3e LSPI_LCD_LINE_CNT0 R [7:0] lcd_line_cnt_l, lcd_line_cnt[7:0] 0x00 0x3f LSPI_LCD_LINE_CNT1 R [1:0] lcd_line_cnt_l, lcd_line_cnt[9:8] 0x00 0x40 LSPI_LCD_LUT_DATA0_BYTE0 RW [7:0] lcd_lut_data0_byte0, lcd lut address0 data byte0 0x00 0x41 LSPI_LCD_LUT_DATA0_BYTE1 RW [7:0] lcd_lut_data0_byte1, lcd lut address0 data byte1 0x00 0x42 LSPI_LCD_LUT_DATA0_BYTE2 RW [7:0] lcd_lut_data0_byte2, lcd lut address0 data byte2 0x00 0x44 LSPI_LCD_LUT_DATA1_BYTE0 RW [7:0] lcd_lut_data1_byte0, lcd lut address1 data byte0 0x00 0x45 LSPI_LCD_LUT_DATA1_BYTE1 RW [7:0] lcd_lut_data1_byte1, lcd lut address1 data byte1 0x00 0x46 LSPI_LCD_LUT_DATA1_BYTE2 RW [7:0] lcd_lut_data1_byte2, lcd lut address1 data byte2 0x00 0x48 LSPI_LCD_LUT_DATA2_BYTE0 RW [7:0] lcd_lut_data2_byte0, lcd lut address2 data byte0 0x00 0x49 LSPI_LCD_LUT_DATA2_BYTE1 RW [7:0] lcd_lut_data2_byte0, lcd lut address2 data byte1 0x00 0x4a LSPI_LCD_LUT_DATA2_BYTE2 RW [7:0] lcd_lut_data2_byte0, lcd lut address2 data byte2 0x00 0x4c LSPI_LCD_LUT_DATA3_BYTE0 RW [7:0] lcd_lut_data3_byte0, lcd lut address3 data byte0 0x00 0x4d LSPI_LCD_LUT_DATA3_BYTE1 RW [7:0] lcd_lut_data3_byte0, lcd lut address3 data byte1 0x00 0x4e LSPI_LCD_LUT_DATA3_BYTE2 RW [7:0] lcd_lut_data3_byte0, lcd lut address3 data byte2 0x00 0x50 LSPI_LCD_LUT_DATA4_BYTE0 RW [7:0] lcd_lut_data4_byte0, lcd lut address4 data byte0 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 339 Ver 0.8.0 0x51 LSPI_LCD_LUT_DATA4_BYTE1 RW [7:0] lcd_lut_data4_byte0, lcd lut address4 data byte1 0x00 0x52 LSPI_LCD_LUT_DATA4_BYTE2 RW [7:0] lcd_lut_data4_byte0, lcd lut address4 data byte2 0x00 0x54 LSPI_LCD_LUT_DATA5_BYTE0 RW [7:0] lcd_lut_data5_byte0, lcd lut address5 data byte0 0x00 0x55 LSPI_LCD_LUT_DATA5_BYTE1 RW [7:0] lcd_lut_data5_byte0, lcd lut address5 data byte1 0x00 0x56 LSPI_LCD_LUT_DATA5_BYTE2 RW [7:0] lcd_lut_data5_byte0, lcd lut address5 data byte2 0x00 0x58 LSPI_LCD_LUT_DATA6_BYTE0 RW [7:0] lcd_lut_data6_byte0, lcd lut address6 data byte0 0x00 0x59 LSPI_LCD_LUT_DATA6_BYTE1 RW [7:0] lcd_lut_data6_byte0, lcd lut address6 data byte1 0x00 0x5a LSPI_LCD_LUT_DATA6_BYTE2 RW [7:0] lcd_lut_data6_byte0, lcd lut address6 data byte2 0x00 0x5c LSPI_LCD_LUT_DATA7_BYTE0 RW [7:0] lcd_lut_data7_byte0, lcd lut address7 data byte0 0x00 0x5d LSPI_LCD_LUT_DATA7_BYTE1 RW [7:0] lcd_lut_data7_byte0, lcd lut address7 data byte1 0x00 0x5e LSPI_LCD_LUT_DATA7_BYTE2 RW [7:0] lcd_lut_data7_byte0, lcd lut address7 data byte2 0x00 0x60 LSPI_LCD_LUT_DATA8_BYTE0 RW [7:0] lcd_lut_data8_byte0, lcd lut address8 data byte0 0x00 0x61 LSPI_LCD_LUT_DATA8_BYTE1 RW [7:0] lcd_lut_data8_byte0, lcd lut address8 data byte1 0x00 0x62 LSPI_LCD_LUT_DATA8_BYTE2 RW [7:0] lcd_lut_data8_byte0, lcd lut address8 data byte2 0x00 0x64 LSPI_LCD_LUT_DATA9_BYTE0 RW [7:0] lcd_lut_data9_byte0, lcd lut address9 data byte0 0x00 0x65 LSPI_LCD_LUT_DATA9_BYTE1 RW [7:0] lcd_lut_data9_byte0, lcd lut address9 data byte1 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 340 Ver 0.8.0 0x66 LSPI_LCD_LUT_DATA9_BYTE2 RW [7:0] lcd_lut_data9_byte0, lcd lut address9 data byte2 0x00 0x68 LSPI_LCD_LUT_DATA10_BYTE RW [7:0] lcd_lut_data10_byte0, lcd lut address10 data byte0 0x00 0x69 LSPI_LCD_LUT_DATA10_BYTE RW [7:0] lcd_lut_data10_byte0, lcd lut address10 data byte1 0x00 0x6a LSPI_LCD_LUT_DATA10_BYTE RW [7:0] lcd_lut_data10_byte0, lcd lut address10 data byte2 0x00 0x6c LSPI_LCD_LUT_DATA11_BYTE RW [7:0] lcd_lut_data11_byte0, lcd lut address11 data byte0 0x00 0x6d LSPI_LCD_LUT_DATA11_BYTE RW [7:0] lcd_lut_data11_byte0, lcd lut address11 data byte1 0x00 0x6e LSPI_LCD_LUT_DATA11_BYTE RW [7:0] lcd_lut_data11_byte0, lcd lut address11 data byte2 0x00 0x70 LSPI_LCD_LUT_DATA12_BYTE RW [7:0] lcd_lut_data12_byte0, lcd lut address12 data byte0 0x00 0x71 LSPI_LCD_LUT_DATA12_BYTE RW [7:0] lcd_lut_data12_byte0, lcd lut address12 data byte1 0x00 0x72 LSPI_LCD_LUT_DATA12_BYTE RW [7:0] lcd_lut_data12_byte0, lcd lut address12 data byte2 0x00 0x74 LSPI_LCD_LUT_DATA13_BYTE RW [7:0] lcd_lut_data13_byte0, lcd lut address13 data byte0 0x00 0x75 LSPI_LCD_LUT_DATA13_BYTE RW [7:0] lcd_lut_data13_byte0, lcd lut address13 data byte1 0x00 0x76 LSPI_LCD_LUT_DATA13_BYTE RW [7:0] lcd_lut_data13_byte0, lcd lut address13 data byte2 0x00 0x78 LSPI_LCD_LUT_DATA14_BYTE RW [7:0] lcd_lut_data14_byte0, lcd lut address14 data byte0 0x00 0x79 LSPI_LCD_LUT_DATA14_BYTE RW [7:0] lcd_lut_data14_byte0, lcd lut address14 data byte1 0x00 0x7a LSPI_LCD_LUT_DATA14_BYTE RW [7:0] lcd_lut_data14_byte0, lcd lut address14 data byte2 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 341 Ver 0.8.0 0x7c LSPI_LCD_LUT_DATA15_BYTE RW [7:0] lcd_lut_data15_byte0, lcd lut address15 data byte0 0x00 0x7d LSPI_LCD_LUT_DATA15_BYTE RW [7:0] lcd_lut_data15_byte0, lcd lut address15 data byte1 0x00 0x7e LSPI_LCD_LUT_DATA15_BYTE RW [7:0] lcd_lut_data15_byte0, lcd lut address15 data byte2 0x00 0x88 LSPI_REG_XIP_ERR_ADDR_B0 RW [7:0] spi reg and xip mode conflict err address byte0 0x00 0x89 LSPI_REG_XIP_ERR_ADDR_B1 RW [7:0] spi reg and xip mode conflict err address byte1 0x00 0x8a LSPI_REG_XIP_ERR_ADDR_B2 RW [7:0] spi reg and xip mode conflict err address byte2 0x00 0x8b LSPI_REG_XIP_ERR_ADDR_B3 RW [7:0] spi reg and xip mode conflict err address byte3 0x00 0x8c LSPI_REG_XIP_ERR_STATUS R [0] reg_xip_err_status, spi reg and xip mode conflict err flag [1] xip_reg_err_status, spi xip and reg mode conflict err flag 0x00 0x90 LSPI_XIP_RD_FMT RW [1:0] xip0_rd_data_lane, xip0 read data lane 0: single, 1: dual, 2: quad, 3: octal [3:2] xip0_rd_addr_len, 2'b00:1bye 2'b01:2bytes 2'b10:3bytes 2'b11:4bytes [4] xip0_rd_addr_fmt, 0:single mode 1:the format of addr phase is the same as the data phase (Dual/ Quad) [5] xip0_rd_addr_en, 1:enable addr phase, MASTER ONLY [6] xip0_rd_cmd_fmt, 0: single mode 1: the format of the cmd phase is the same as the data phase (Dual/Quad), MASTER ONLY [7] xip0_rd_cmd_en, the spi command phase enable, MASTER ONLY 0xa9 0x91 LSPI_XIP_RD_TRANSMODE RW [3:0] xip0_rd_dummy_cnt, dummy number = dummy_cnt + 1 [7:4] xip0_rd_transmode, xip read transmode/lcd display transmode 0x97 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 342 Ver 0.8.0 0x92 LSPI_XIP_RD_CTRL0 RW [0] cmd1_en [1] xip_token_val_sel, 1:8'h69; 0:8'h00 [2] xip_token_en [3] xip0_rd_dummy_cnt_add [4] xip0_ddr_mode [5] xip0_page_mode_en [6] xip0_timeout_mode_en [7] xip0_tcem_mode_en 0x40 0x93 LSPI_XIP_RD_CMD RW [7:0] xip0_rd_cmd, read command used for xip 0x3b 0x94 LSPI_XIP_WR_FMT RW [1:0] xip0_wr_data_lane, xip0 write data lane 0: single, 1: dual, 2: quad, 3: octal [3:2] xip0_wr_addr_len, 2'b00:1bye 2'b01:2bytes 2'b10:3bytes 2'b11:4bytes [4] xip0_wr_addr_fmt, 0:single mode 1:the format of addr phase is the same as the data phase (Dual/ Quad), MASTER ONLY [5] xip0_wr_addr_en, 1:enabel addr phase, MASTER ONLY [6] xip0_wr_cmd_fmt, 0: single mode 1: the format of the cmd phase is the same as the data phase (Dual/Quad), MASTER ONLY [7] xip0_wr_cmd_en, the spi command phase enable, MASTER ONLY 0xa8 0x95 LSPI_XIP_WR_TRANSMODE RW [3:0] xip0_wr_dummy_cnt dummy number = {dummy_cnt_add, dummy_cnt} + [7:4] xip0_wr_transmode, xip write transmode/lcd porch transmode 0x10 0x96 LSPI_XIP_WR_CTRL0 RW [0] cmd1_en 0x0 0x97 LSPI_XIP_WR_CMD RW [7:0] xip0_wr_cmd, write command used for xip/ lcd_cmd 0x02 0xb4 LSPI_XIP_RD_CMD1 RW [7:0] xip_rd_cmd1, SPI Command1 0x00 0xb5 LSPI_XIP_WR_CMD1 RW [7:0] xip_wr_cmd1, SPI Command1 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 343 Ver 0.8.0

11.7 GSPI

11.7.1 GSPI Diagram

The GSPI module is a controller which serves as a SPI master to access other general SPI interfaces. Features of GSPI are listed as following:

• Supports SPI Master/Slave mode
• Supports Dual line and 3 line I/O SPI interface
• Supports XIP function
• Supports DMA transmission
• Supports multi-chip selection function
• 5-channel GSPI (GSPI0, GSPI1, GSPI2, GSPI3, GSPI4)
• Up to 48 MHz SPI clock. However, to achi eve 48 MHz, specific pin configurations must be used as follows: Table 11-16 GSPI Specific Pin Configurations 0xe2 LSPI_XIP_TOKEN_VAL RW [7:0] xip_token_val 0x00 0xe3 LSPI_REG_TOKEN_VAL RW [7:0] reg_token_val 0x00 GSPI Pin GSPI Signal GSPI0 PE[7] GSPI0_CK PF[0] GSPI0_IO3 PF[1] GSPI0_IO2 PF[2] GSPI0_MISO PF[3] GSPI0_MOSI GSPI1 PF[4] GSPI1_CK PF[5] GSPI1_IO3 PF[6] GSPI1_IO2 PF[7] GSPI1_MISO PG[0] GSPI1_MOSI Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 344 Ver 0.8.0 The GSPI diagram is shown as following: GSPI2 PG[1] GSPI2_CK PG[2] GSPI2_IO3 PG[3] GSPI2_IO2 PG[4] GSPI2_MISO PG[5] GSPI2_MOSI GSPI3 PG[6] GSPI3_CK PG[7] GSPI3_IO3 PH[0] GSPI3_IO2 PH[1] GSPI3_MISO PH[2] GSPI3_MOSI GSPI4 PH[3] GSPI4_CK PH[4] GSPI4_IO3 PH[5] GSPI4_IO2 PH[6] GSPI4_MISO PH[7] GSPI4_MOSI GSPI Pin GSPI Signal

Datasheet for Telink TL3828 DS-TL3828-E5 345 Ver 0.8.0 Figure 11-23 GSPI Diagram As shown in the diagram, the bus between the SPI module and the DMA module. SPI_BUS is the SPI interface connected to the pad. The spi_regif is to parse the APB protocol and send it to the spi_reg module for register configuration. The spi_ctrl module selects the state and mode according to the value of the register configuration, and controls the format of the transmitted data. The spi _if module adjusts the characteristics of the SPI rate or polarity of transmission and reception according to the configuration. The spi_fifo serves as a buffer for sending and receiving data.

11.7.2 Register Description of GSPI

The GSPI related registers are listed as below. For GSPI0 related register, the base address is 0x8BFFFF00; For GSPI1 related register, the base address is 0x93FFFF00; For GSPI2 related register, the base address i s 0x97FFFF00; For GSPI3 related register, the base address is 0x9BFFFF00; For GSPI4 related register, the base address is 0x9FFFFF00. Table 11-17 GSPI Related Registers Address Offset Name Type Description Default Value 0x00 GSPI_WR_RD_DATA0 RW [7:0]: wr_rd_data0, data[7:0] to transmit or received 0x00 0x01 GSPI_WR_RD_DATA1 RW [7:0]: wr_rd_data1, data[15:8] to transmit or received 0x00 txfifo rxfifo spi_fifo xip_ctrl spi_regif spi_reg spi_dmaif spi_ctrl rxshift[7:0] spi_cn[3:0] spi_dat[3:0] hclk spi_if GSPI sync sclk txshift[7:0] SPI_FSM hslv spi_ck AHB Bus

Datasheet for Telink TL3828 DS-TL3828-E5 346 Ver 0.8.0 0x02 GSPI_WR_RD_DATA2 RW [7:0]: wr_rd_data2, data[23:16] to transmit or received 0x00 0x03 GSPI_WR_RD_DATA3 RW [7:0]: wr_rd_data3, data[31:24] to transmit or received 0x00 0x04 GSPI_CMD RW [7:0]: SPI Command 0x00 0x05 GSPI_CTRL0 RW [0]: RXFIFOORIntEn, enable the SPI Receive FIFO Overrun interrupt, SLAVE ONLY [1]: TXFIFOURIntEn, enable the SPI Transmit FIFO Underrun interrupt, SLAVE ONLY [2]: RXFIFOIntEn, enable the SPI Receive FIFO Threshold interrupt [3]: TXFIFOIntEn, enable the SPI Transmit FIFO Threshold interrupt [4]: EndIntEn, enable the End of SPI Transfer interrupt [6]: rx_dma_en, RX DMA enable [7]: tx_dma_en, TX DMA enable 0x00 0x06 GSPI_REG_CMD1 RW [7:0]: reg_cmd1, SPI Command1 0x07 GSPI_TIMING RW [2:0]: cs2sclk, the minimum time between the edge of SPI_CS and the edges of SPI_CLK. The actual duration is (SPI_CLK period*(cs2sclk+1)), MASTER ONLY [7:3]: csht_low the minimum time that SPI CS should stay HIGH.the actual duration is (SPI_CLK period*(csht+1)),MASTER ONLY actual_csht[6:0] = {csht_high, csht_low} 0x09 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 347 Ver 0.8.0 0x08 GSPI_CTRL1 RW [1:0]: reg_data_lane, reg data lane 0: single, 1: dual, 2: quad, 3: octal [3:2]: reg_addr_len, 2'b00:1bye, 2'b01:2bytes, 2'b10:3bytes, 2'b11:4bytes, MASTER ONLY [4]: reg_addr_fmt, 0:single mode 1:the format of addr phase is the same as the data phase(Dual/Quad), MASTER ONLY [5]: reg_addr_en, 1:enabel addr phase, MASTER ONLY [6]: reg_cmd_fmt, 0: single mode 1: the format of the cmd phase is the same as the data phase(Dual/Quad), MASTER ONLY [7]: reg_cmd_en, the spi commnd phase enable, MASTER ONLY 0xa9 0x09 GSPI_CTRL2 RW [3:0]: dummy_cnt, dummy number = {dummy_cnt_add, dummy_cnt} + 1 [7:4]: transmode, the transfer mode the transfer sequence could be: 0x0:write and read at the same time (must enable CmdEn) 0x1:write only 0x2:read only (must enable CmdEn) 0x3:write,read 0x4:read,write 0x5:write,dummy,read 0x6:read,dummy,write (must enable CmdEn) 0x7:None Data (must enable CmdEn) 0x8:Dummy,write 0x9:Dummy,read 0xa:Dummy, write and read 0xb~0xf:reserved 0x77 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 348 Ver 0.8.0 0x0a GSPI_REG_CTRL0 RW [0]: cmd1_en_ [1]: reg_token_val_sel, 1:8'h69, 0:8'h00 [2]: reg_token_en [3]: reg_ddr_mode_ [5:4]: csht_high 0x00 0x0b GSPI_XIP_WR_TCEM_S ET RW [7:0]: xip_wr_tcem_set, actual = xip_wr_tcem_set * 4 0x0c GSPI_ADDR0 RW [7:0]: spi_addr0, spi address byte0, MASTER ONLY 0x00 0x0d GSPI_ADDR1 RW [7:0]: spi_addr1, spi address byte1, MASTER ONLY 0x00 0x0e GSPI_ADDR2 RW [7:0]: spi_addr2, spi address byte2, MASTER ONLY 0x00 0x0f GSPI_ADDR3 RW [7:0]: spi_addr3, spi address byte3, MASTER ONLY 0x00 0x10 GSPI_TX_CNT0 RW [7:0]: tx_cnt0, transfer count for write data, byte0 0x00 0x11 GSPI_TX_CNT1 RW [7:0]: tx_cnt1, transfer count for write data, byte1 0x00 0x12 GSPI_TX_CNT2 RW [7:0]: tx_cnt2, transfer count for write data, byte2 0x00 0x14 GSPI_RX_CNT0 RW [7:0]: rx_cnt0, transfer count for read data, byte0 0x00 0x15 GSPI_RX_CNT1 RW [7:0]: rx_cnt1, transfer count for read data, byte1 0x00 0x16 GSPI_RX_CNT2 RW [7:0]: rx_cnt2, transfer count for read data, byte2 0x00 0x18 GSPI_CTRL3 RW [0]: spi_lsb, transfer data with least significant bit first [1]: spi_3line, MOSI is bi-directional signal in regular mode [3:2]: spi_mode, spi_mode[0]:SPI_CLK Phase; spi_mode[1]:SPI_CLK Polarity [4]: spi_master, SPI master mode selection [5]: dmatx_sof_clrtxfifo_en, auto clr txfifo when txdma start [6]: dmarx_eof_clrrxfifo_en, auto clr rxfifo when rxdma end [7]: auto_hready_en, auto control hready while access data register 0x90 0x19 GSPI_TXFIFO_THRES RW [5:0]: txfifo threshold 0x00 0x1a GSPI_RXFIFO_THRES RW [5:0]: rxfifo threshold 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 349 Ver 0.8.0 0x1b GSPI_PEM_CTRL0 RW [0]: reg_event_en [1]: reg_task_en [2]: reg_pem_event_sel 0x1c GSPI_CTRL4 RW [0]: dma_trig_spi_en [1]: txdma_req_after_cmd [2]: xip_stop, stop xip [3]: xip_enable, enable xip [7:4]: dummy_cnt_add 0x0a 0x1d GSPI_XIP_PAGE_SIZE RW [7:0]: page_size, page boundary size = 2^page_size 0x00 0x1e GSPI_XIP_TIMEOUT_C NT RW [7:0]: timeout_cnt, timeout time sel 0x60 0x1f GSPI_XIP_RD_TCEM_S ET RW [7:0]: xip_rd_tcem_set 0x00 0x22 GSPI_XIP_ADDR_OFFS ET RW [7:0]: xip_addr_offset, address offset = xip_addr_offset << 24 0x00 0x24 GSPI_TXFIFO_STATUS R [6:0]: txfifo_entries [7]: txfifo_full 0x0 0x25 GSPI_RXFIFO_STATUS R [6:0]: rxfifo_entries [7]: rxfifo_empty 0x0 0x28 GSPI_STATUS RW/R [0]: set_slave_ready(RW), set this bit to indicate that spi as salve is ready for data transaction [1]: clr_slave_ready(RW), clear spi slave ready [2]: spi_soft_reset(RW), spi soft reset, high valid [3]: xip_reg_arb_err(R), xip mode and reg mode conflict flag [4]: rxfifo_clr_level(RW), rxfifo is in clear status [5]: txfifo_clr_level(RW), txfifo is in clear status [7]: busy(R), SPI is transferring 0x0 0x29 GSPI_SLV_TRANS_MO DE RW [3:0]: slv_trans_mode Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 350 Ver 0.8.0 0x2a GSPI_INT_STATUS0 W1C [0]: rxf_overrun_int_stus, RX FIFO Overrun interrupt, SLAVE ONLY [1]: txf_underrun_int_stus, TX FIFO Underrun interrupr,SLAVE ONLY [2]: rxf_thres_int_stus, RX FIFO Threshold interrupt [3]: txf_thres_int_stus, TX FIFO Threshold interrupt [4]: trans_end_int_stus, End of SPI Transfer interrupt [5]: slave_cmd_int_stus, Slave Command Interrupt, SLAVE ONLY 0x00 0x88 GSPI_REG_XIP_ERR_A DDR_B0 RW [7:0]: spi reg and xip mode conflict err address byte0 0x00 0x89 GSPI_REG_XIP_ERR_A DDR_B1 RW [7:0]: spi reg and xip mode conflict err address byte1 0x00 0x8a GSPI_REG_XIP_ERR_A DDR_B2 RW [7:0]: spi reg and xip mode conflict err address byte2 0x00 0x8b GSPI_REG_XIP_ERR_A DDR_B3 RW [7:0]: spi reg and xip mode conflict err address byte3 0x00 0x8c GSPI_REG_XIP_ERR_ST ATUS R [0]: reg_xip_err_status, spi reg and xip mode conflict err flag [1]: xip_reg_err_status, spi xip and reg mode conflict err flag 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 351 Ver 0.8.0 0x90 GSPI_XIP_RD_FMT RW [0]: xip0_rd_data_dual, spi dual I/O mode, MASTER ONLY [1]: xip0_rd_data_quad, spi quad I/O mode, MASTER ONLY [3:2]: xip0_rd_addr_len, 2'b00:1bye 2'b01:2bytes 2'b10:3bytes 2'b11:4bytes [4]: xip0_rd_addr_fmt, 0:single mode 1:the format of addr phase is the same as the data phase (Dual/Quad) [5]: xip0_rd_addr_en, 1:enable addr phase, MASTER ONLY [6]: xip0_rd_cmd_fmt, 0: single mode 1: the format of the cmd phase is the same as the data phase (Dual/ Quad), MASTER ONLY [7]: xip0_rd_cmd_en, the spi command phase enable, MASTER ONLY 0xa9 0x91 GSPI_XIP_RD_TRANSM ODE RW [3:0]: xip0_rd_dummy_cnt, dummy number = dummy_cnt + 1 [7:4]: xip0_rd_transmode 0x97 0x92 GSPI_XIP_RD_CTRL0 RW [0]: cmd1_en [1]: xip_token_val_sel, 1:8'h69, 0:8'h00 [2]: xip_token_en [3]: xip0_rd_dummy_cnt_add [4]: xip0_ddr_mode [5]: xip0_page_mode_en [6]: xip0_timeout_mode_en 0:xip timeout disable 1:xip timeout enable [7]: xip0_tcem_mode_en 0:xip tcem disable 1:xip tcem enable 0x40 0x93 GSPI_XIP_RD_CMD RW [7:0]: xip0_rd_cmd, read command used for xip 0x3b Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 352 Ver 0.8.0

11.8 SPI Slave (SPI_SLV)

11.8.1 Diagram

SPI_SLV diagram is shown as below. As shown in the diagram, SPI_SLAVE_Interface is used to analyze the protocol of the SPI interface, which is in spi_clk_i domain. SPI_SLAVE_Control is used to synchronize the data of spi_clk_i domain to sclk domain, and parse out the address and data segment to AHB_MASTER module. The AHB_MASTER module synchronizes the data from the sclk domai n to the ahb clk domain and sends the parsed address and data to form the AHB bus. 0x94 GSPI_XIP_WR_FMT RW [1:0]: xip0_wr_data_lane, xip0 write data lane 0: single, 1: dual, 2: quad, 3: octal [3:2]: xip0_wr_addr_len, 2'b00:1bye 2'b01:2bytes 2'b10:3bytes 2'b11:4bytes [4]: xip0_wr_addr_fmt, 0:single mode 1:the format of addr phase is the same as the data phase (Dual/Quad), MASTER ONLY [5]: xip0_wr_addr_en, 1:enabel addr phase, MASTER ONLY [6]: xip0_wr_cmd_fmt, 0: single mode 1: the format of the cmd phase is the same as the data phase (Dual/ Quad), MASTER ONLY [7]: xip0_wr_cmd_en, the spi command phase enable, MASTER ONLY 0xa8 0x95 GSPI_XIP_WR_TRANS MODE RW [3:0]: xip0_wr_dummy_cnt dummy number = {dummy_cnt_add, dummy_cnt} + 1 [7:4]: xip0_wr_transmode 0x10 0x96 GSPI_XIP_WR_CTRL0 RW [7:0]: cmd1_en 0x97 GSPI_XIP_WR_CMD RW [7:0]: xip0_wr_cmd, write command used for xip 0x02 0xb4 GSPI_XIP_RD_CMD1 RW [7:0]: xip_rd_cmd1, SPI Command1 0x00 0xb5 GSPI_XIP_WR_CMD1 RW [7:0]: xip_wr_cmd1, SPI Command1 0x00 0xe2 GSPI_XIP_TOKEN_VAL RW [7:0]: xip_token_val 0x00 0xe3 GSPI_REG_TOKEN_VAL RW [7:0]: reg_token_val 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 353 Ver 0.8.0 Figure 11-24 SPI_SLV Diagram

11.8.2 Features

The SoC embeds SPI_SLV interface for debugging, features of SPI_SLV are listed as following:

• Supports SPI Slave mode
• Supports Dual I/O SPI interface

11.8.3 Function Description

This module converts SPI timing to AHB Master request. SPI Master data should be read and written in formats specified by SPI_SLV, shown as following: Figure 11-25 SPI_SLV Write Format Figure 11-26 SPI_SLV Read Format SPI_SLV determines the format and operation by parsing the commands, shown i n the following table. SPI SLAVE Interface SPI SLAVE Control CDC sync AHB MASTER SPI BUS AHB BUS spi_clk_i domain sclk domain ahb clk domain Cmd(8bit) Addr(32bit) Data0(1byte) Data1(1byte) Data Cmd(8bit) Addr(32bit) Dummy(8/4cycle) Data0(1byte) Data1(1byte) Data

Datasheet for Telink TL3828 DS-TL3828-E5 354 Ver 0.8.0 Table 11-18 SPI_SLV Commands Address auto increase does not support ahb word/half word transfer. SPI_CLK_in supported frequencies: When read_dummy is 8, SPI_CLK_in frequency <= (1/2)*hclk frequency. When read_dummy is 4, SPI_CLK_in frequency <= (1/4)*hclk frequency.

11.9 UART

11.9.1 Introduction

The SoC embeds UART (Universal Asynchronous Receiver/Transmitter) to implement full-duplex transmission and reception via UART TX and RX i nterface. The UART module also supports ISO7816 protocol to enable communication with ISO/IEC 7816 integrated circuit card, especially smart card. In this mode, half-duplex communication (transmission or reception) is supported via the shared 7816_TRX interface. UART features include:

• Full-duplex operation
• Automatic flow control via RTS and CTS
• 8-bit UART mode, variable baud rate
• Optional even parity bi t checking and generation
• Supports 1, 1.5 and 2 STOP bits
• Supports line breaks, parity errors, framing errors
• 8 bytes of transmit/receive FIFOs
• Supports ISO7816 protocol
• Supports DMA function (RX supports DMA Linked List Pointer)
• Up to 3 Mbps baud rate
• 5-channel UART (UART0, UART1, UART2, UART3, UART4) Name Description Default Cmd[7:0] Cmd[7]: value 0:spi write, value 1:spi read Cmd[6]: value 0:addr single i/o, value 1:addr dual i/o cmd[5]: value 0:data single i/o, value 1:data dual i/o cmd[4]: value 0:addr auto increase, value 1:disable addr auto increase cmd[3]:value0:read dummy 8 cycle, value1:read dummy 4 cycle cmd[2]: value1:ahb word transfer cmd[1]: value1: ahb half word transfer cmd[0]: reserved 8’b0000_0000: spi slave write with addr single i/o and data single i/o in the addr auto increasing mode.

Datasheet for Telink TL3828 DS-TL3828-E5 355 Ver 0.8.0

11.9.2 Block Diagram

The figure below shows the block diagram of UART. Figure 11-27 Block Diagram of UART

11.9.3 Function Description

11.9.3.1 Pin Configuration

The UART bidirectional communications require a minimum of two pins: Receive Data In (RX) and Transmit Data Out (TX):

• RX (Receive Data Input) RX is the serial data input. Oversampling techniques are used for data recovery. In ISO7816 modes, this I/O is used to transmit and receive data.
• TX (Transmit Data Output) When the transmi tter is disabled, the output pin returns to its I/O port configuration. When the transmitter is enabled and no data needs to be transmitted, the TX pin is High. The following pins are required in Hardware flow control mode:
• CTS (Clear To Send) When driven low (optional), this signal blocks the data transmission at the end of the current transfer.
• RTS (Request To Send) When it is low, this signal indi cates that the UART is ready to receive data.

11.9.3.2 Transmitter

(1) NDMA Operation The transmitter comprises a Transmitter FIFO (TX FIFO), a Transmitter Shift, and a Transmitter Controller (TX controller). The TX FIFO holds data to be transferred through the serial interface. The TX FIFO can store up to 8 characters depending on hardware configurations and programming settings. The Transmitter Shift reads a character from the TX FIFO for the nex t transmission. The Transmitter Shift functions as a parallel-to-serial data converter, converting the outgoing character to serial bit streams. For each character transmission, the TX

Datasheet for Telink TL3828 DS-TL3828-E5 356 Ver 0.8.0 Controller generates a START bit, an optional parity bit, and some number of STOP bits. The generation of parity bit and STOP bit can be configured by the uart_ctrl1 register. The TX FIFO is by default a 8-byte buffer called Transmitter Buffer Register. (2) DMA Operation When the TX FIFO under the threshold 4 characters, the UART controller will assert dma_tx_req to request a data transfer. The DMA controller should then transfer data to the TX FIFO followed by asserti ng dma_tx_ack. Next, the UART controller de-asserts dma_tx_req and the DMA controller de-asserts dma_tx_ack. The UART controller will assert dma_tx_req again unless the TX FIFO is full or the DMA transmission length is reached.

11.9.3.3 Receiver

(1) NDMA Operation The receiver comprises a Receiver FIFO (RX FIFO), Receiver Shift, and a Recei ver Controller (RX Controller). The RX Controller uses the oversampling clock generated by Baud Rate Generator to perform sampling at the center of each bit transmission. The received bits are shifted into the Receiver Shift for serial-to-parallel data conversion and the received character is stored into the RX FIFO. The RX FIFO is by default a 8byte buffer called the Receiver Buffer Reg ister. The RX controller also detects some error condi tions for each data transmission including parity error, framing error, or line break. (2) DMA Operation When the RX FIFO reaches the threshold 4 characters, the UART controller will assert dma_rx_req to request a data transfer. The DMA controller should then transfer data from the RX FIFO followed by asserting dma_rx_ack. Next, the UART controller de-asserts dma_rx _req and the DMA controller de-asserts dma_rx_ack. The UART controller will assert dma_rx_req again unless the RX FIFO is empty. DMA relies on rxdone to read parts of the data below 4 characters.

11.9.3.4 Baud Rate Generator

The Baud Rate Generator takes the UART clock as the source clock (pclk) and divides it with a divisor. The divisor consists of uart_clk_div and bpwc register. The uart_clk_div value is 15-bit i n size and stored in two separate registers. The formula for the divisor value is as follows: uart_sclk = pclk/(uart_clk_div[14:0]+1) Baudrate = uart_sclk/(bpwc+1), bpwc > 2 Suppose that:

• T1 is the period of one bit transmission as perceived by the Rx Controller.
• T2 is the period of one bit transmission of the transmitter.
• N is the bit number for one frame of data – the START bit, data bits, parity bit, and the STOP bit(s).

Datasheet for Telink TL3828 DS-TL3828-E5 357 Ver 0.8.0 Figure 11-28 UART Protocol Formats and Sampling Point Then, the clock period tolerance for is as follows: The calculation formula is obtained by conversion: Since T is the inverse of the baud rate, the actual baud rate generated by this controller in relation to the actual baud rate of the transmitter (the tolerance factor) can be within the range below: If the character has one START bit, 8 data bits, one parity bit and one STOP bi t, then N is 11 (1 + 8 + 1 + 1). The tolerance factor is from 0.9602 to 1.05. The table below shows clock tolerance factors as percentage of the actual Transmitter Baud Rates for typical values of N and bpwc register. Table 11-19 Clock Variation Tolerance Factor

11.9.3.5 Loopback Mode

The UART provides a loopback mode for diagnostic testing without connecting an external device. When the loopback mode is enabled, the behavior of the controller is as follows:

• The output si gnals (TX, RTS) are disconnected from the TX/RX Controller and driven HIGH to avoid confusing the other end of the serial connection in case the connection exists.
• The input signals (RX, CTS) are disconnected from the TX/RX Controller and ignored.
• The TX Controller output values originally intended for the TX output signals are routed internally to replace the input signal of RX for the RX Controller, so every bi t sent by the TX Controller is looped back and received by the RX controller. Note that CTS and RTS are similar. Typical Register Value N = 10 N = 11 Conditions bpwc = 15, uart_clk_div = 12 0.9563 - 1.056 0.9602 - 1.05 pclk: 24MHz baud rate: 115200bpsbpwc = 7, uart_clk_div = 25 0.9625 - 1.056 0.9659 - 1.05 N T1 N 0.5 1   T2 0.5 1             T2 T1 N 0.5– 0.5 1             Actual baud rate   

Datasheet for Telink TL3828 DS-TL3828-E5 358 Ver 0.8.0

11.9.3.6 Error Conditions

An ERROR event, in the form of a framing error, will be generated if a valid stop bit is not detected in a frame. Second ERROR event, in the form of a break condition, will be generated if the RX line is held active low for longer than the length of a data frame. Another ERROR event, Parity check bit error. The above ERROR event generates an rx_err interrupt. When an rx err interrupt i s detected, perform the following operations: Disable DMA and clear RX FIFO(irq_sts[2])

11.9.3.7 Hardware Flow Control

It is possible to control the serial data flow between 2 devices by using the CTS input and the RTS output. The figure below shows how to connect 2 devices in this mode: Figure 11-29 Hardware Flow Control between 2 UARTs If RX buffer of the UART is close to threshold, the UART will send a signal (configurable high or low level) via pin RTS to inform other devi ce that it should stop sending data. Similarly, if the UART receives a signal from pin CTS, it indicates that RX buffer of other device is close to full and the UART should stop sending data. The threshold can be configured using the register uart_ctrl2[3:0]. If the flow control is not enabled, the interface will behave as if the CTS and RTS lines are kept active all the time. The RTS has two modes of control: manual and automati c. In Manual mode, it is controlled via the register uart ctrl[6:5]. Automatic hardware flow control can be triggered in two ways:

• Automatic trigger RTS when the RX FIFO reaches the threshold(uart_ctrl2[3:0]).
• If rxdone_rts_en is configured to 1 and the rxdone is triggered at the same time, causing the RTS to be triggered. Please refer to Register uart_ctrl2 for the use of the flow control functi on. If rts_en is 0, rts function is off, rxdone_rts_en/rxtimeout_rts_en are both off (rxtimeout_rts_en is off to avoid rxdone_irq generation).

Datasheet for Telink TL3828 DS-TL3828-E5 359 Ver 0.8.0 If rts_en is 1, the rts function is on, and rxdone_rts_en/rxtimeout_rts_en are both enabled. (The rxtimeout_rts_en is enabled to stop sending data when the sender's CTS pin receives an active level on the RTS pin; If this is turned off at this time, no data will be sent, resulting in an rxdone interrupt, and when rxdone_irq is cleared, the rx_fifo data will be cleared, resulting i n an rts failure. The rxdone_rts_en enable is to prevent the two sets of data from being so close that the software can't handle them.)

11.9.3.8 Receiver Timeout

Receiver timeout is used to handle when the data received per frame does not reach the threshold. Because data read from the Receiver Buffer Register is a multiple of 4 at a time, The rxdone interrupt is required to process the remaining data below the threshold. F igure 11-30 Timeout Flag Used for Data Transmission The Time out counter inside the UART is updated at the STOP bit, and when receiving data stops, the Timeout counter decreases to 0 and generates a rxdone interrupt. Note: If the register uart ctrl0[6] is configured to 1 and the RTS is triggered at the same time, causing the timeout counter to pause. The configurable total timeout is determined via registers r_rxtimeout_l and r_rxtimeout_h[1:0]. Total ti meout = r_rxtimeout_l * (r_rxtimeout_h + 1 )

• The r_rxtimeout_l register: The setting is transfer one bytes need cycles base on uart_clk. For example, if transfer one bytes (1start bit+8bits data+1 priority bit+2stop bits) total 12 bits, this register setting should be (register uart ctrl0[3:0]+1)*12.
• The r_rxtimeout_h[1:0] register: 2’b00: rx timeout time is r_rxtimeout[7:0] 2’b01: rx timeout time is r_rxtimeout[7:0]*2 2’b10: rx timeout time is r_rxtimeout[7:0]*3 3’b11: rx timeout time is r_rxtimeout[7:0]*4 The register r_rxtimeout (r_rxtimeout_l and r_rxtimeout_h) is for rx dma to decide the end of each transaction. Supposed the i nterval between each byte in one transaction is very short. NOTE:
• The DMA Operation threshold is fixed at 4.
• The NDMA Operation threshold can be configured through the register uart_ctrl3[3:0].

Datasheet for Telink TL3828 DS-TL3828-E5 360 Ver 0.8.0 The minimum time supported via function timeout the time required for a single transmission of 1byte data, The maximum time is the maximum value supported via register r_rxtimeout. But registers r_rxtimeout_l and r_rxtimeout_h[1:0] still expect to follow our recommended approach.

11.9.4 Register Description of UART

UART related registers are listed in tables below. The base address of UART0 is 0x80140080, the base address of UART1 i s 0x801400C0, the base address of UART2 is 0x80240040, the base address of UART3 is 0x80240080, the base address of UART4 is 0x802400C0. Table 11-20 UART Related Registers Offset Name Type Description Defaul t Value 0x00 UART_DATA_BUF0 Volatile [7:0]: buf0, Bit7-0 of Transmitter/Receiver Buffer Register (TX/RX FIFO) 0x00 0x01 UART_DATA_BUF1 Volatile [7:0]: buf1, Bit15-8 of Transmitter/Receiver Buffer Register (TX/RX FIFO) 0x00 0x02 UART_DATA_BUF2 Volatile [7:0]: buf2, Bit23-16 of Transmitter/Receiver Buffer Register (TX/RX FIFO) 0x00 0x03 UART_DATA_BUF3 Volatile [7:0]: buf3, Bit31-24 of Transmitter/Receiver Buffer Register (TX/RX FIFO) 0x00 0x04 UART_CLK_DIV_L RW [7:0]: clk_div_l, uart_cli_div[7:0]:uart clk div register 0xff 0x05 UART_CLK_DIV_H RW [7:0]: clk_div_h uart_cli_div[15:8]: uart_sclk = sclk/(uart_clk_div[14:0]+1) uart_clk_div[15]: 1:enable clock divider,0: disable. 0x0f

Datasheet for Telink TL3828 DS-TL3828-E5 361 Ver 0.8.0 0x06 UART_CTRL0 RW [3:0]: bpwc_o bpwc, bit width should be larger than 2 Baudrate = uart_sclk/(bpwc+1) [4]: auto_rxclr_en Auto clear function enable of DMA and NDMA mode; 1:enable, 0:disable [5]: ndma_rxdone_en rxdone (timeout) function enable in NDMA mode; 1:enable, 0:disable; The DMA mode must disabled. [6]: rxtimeout_rts_en RTS controls timeout stop enabled; 1:enable, 0:disable If rxtimeout_rts_en is configured to 1 and the RTS is triggered at the same time, causing the timeout counter to pause. [7]: p7816_en_o 7816 enable; 1:enable, 0:disable 0x7f 0x07 UART_CTRL1 RW [0]: tx_cts_polarity Polarity of CTS 0: Active low (0 - End of transmission) 1: Active high (1 - End of transmission) [1]: tx_cts_enable CTS enable, 1: enable, 0: disable [2]: parity_enable Parity enable When this bit is set, a parity bit is generated in transmitted data before the first STOP bit and the parity bit would be checked for the received data. [3]: parity_polarity Even parity select, 1: old parity; 0: even parity (an even number of logic-1 is in the data and parity bits). [5:4]: stop_sel stop bit, 00: STOP bit is 1 bit; 01: STOP bit is 1.5 bits; 1x: STOP bit is 2 bits [6]: ttl_enable TX and RX polarity selection, 0: Non-inverting; 1: Inverting [7]: loopback_o Enable loopback mode, 1: enable; 0: disable 0x0e Offset Name Type Description Defaul t Value

Datasheet for Telink TL3828 DS-TL3828-E5 362 Ver 0.8.0 0x08 UART_CTRL2 RW [3:0]: rts_triq_lev RTS trig level. Trigger RTS when the RX FIFO reaches the threshold. [4]: rts_polarity Polarity of RTS 0: Active high (0-ready for receiving) 1: Active low (1-ready for receiving) [5]: rts_manul_v RTS manual value [6]: rts_manul_m RST manual enable [7]: rts_en RTS enable, 1: enable; 0: disable 0xa5 0x09 UART_CTRL3 RW [3:0]: rx_irq_trig level. Trigger rx_buf_irq interrupt when the RX FIFO reaches the threshold. [7:4]: tx_irq_trig level. Trigger tx_buf_irq interrupt when the TX FIFO under the threshold. 0x44 0x0a UART_RXTIMEOUT _O_L RW [7:0]: rx_timeout_l Least significant byte of the r_rxtimeout_o register: The setting is transfer one bytes need cycles base on uart_clk. For example, if transfer one byte (1start bit+8bits data+1 priority bit+2stop bits) total 12 bits, this register setting should be (bpwc+1)*12. 0xc0 Offset Name Type Description Defaul t Value

Datasheet for Telink TL3828 DS-TL3828-E5 363 Ver 0.8.0 0x0b UART_RXTIMEOUT _O_H RW [1:0]: r_rxtimeout_o Most significant byte of the r_rxtimeout register 2’b00: rx timeout time is r_rxtimeout[7:0] 2’b01: rx timeout time is r_rxtimeout[7:0]*2 2’b10: rx timeout time is r_rxtimeout[7:0]*3 3’b11: rx timeout time is r_rxtimeout[7:0]*4 r_rxtimeout is for rx dma to decide the end of each transaction. Supposed the interval between each byte in one transaction is very short. [2]: mask_rx_irq Enable rx_buf_irq interrupt [3]: mask_tx_irq Enable tx_buf_irq interrupt [4]: mask_rxdone Enable rxdone_irq interrupt [5]: mask_txdone Enable txdone interrupt [6]: mask_err_irq Enable rx_err interrupt [7]: reserved 0x01 0x0c UART_BUFCNT Volatile [3:0]: rx_bufcnt This register is increased when there are incoming received data in the Receiver Buffer Register. When there is read data in the Receiver Buffer Register, this register is decremented. [7:4]: tx_bufcnt This register is decremented when there are outgoing sent data in the Transmitter Buffer Register. When there is write data in the Transmitter Buffer Register, this register is increased. 0x00 0x0d UART_STATUS Volatile [2:0]: rcnt. When there is read data in the Receiver Buffer Register, this register is decremented. [3]: irq. Total interruption of UART. [6:4]: wbcnt. When there is write data in the Transmitter Buffer Register, this register is increased. [7]: rxdone. Similar to the rxdone irq interrupt, but rxdone is automatically cleared by the UART. 0x00 Offset Name Type Description Defaul t Value

Datasheet for Telink TL3828 DS-TL3828-E5 364 Ver 0.8.0 0x0e UART_TXRX_STAT US Volatile [1:0]: rx_rem_cnt_d. This register is increased when there are incoming received data in the Receiver Buffer Register. Gets incoming received data in the Receiver Buffer Register less than 1word. [2]: rx_buf_irq. When the RX FIFO reaches the threshold set by the rx_irq_trig Register, the UART controller will assert rx_buf_irq interrupt. W: write 1 to clear RX FIFO pointer, rx err, and so on. Note: When RX FIFO is below the threshold set by the rx_irq_trig Register, the rx_buf_irq interrupt clears automatically. [3]: tx_buf_irq When the TX FIFO under the threshold set by the tx_irq_trig register, the UART controller will assert tx_buf_irq interrupt. W: write 1 to clear TX FIFO pointer, and so on. Note: When TX FIFO is greater than the threshold set by the tx_irq_trig register, the tx_buf_irq interrupt clears automatically. [4]: rxdone_irq When the receiver ends (the timeout counter decays to 0), the UART controller will assert rxdone_irq interrupt. W: write 1 to clear rxdone_irq [5]: txdone. When the transmitter ends, the UART controller will assert txdone interrupt. W: write 1 to clear txdone [6]: rx_err. The error status is asserted when the following error events: parity errors framing errors, line breaks [7]: timeout The flag bit that the timeout counter decays to 0. 0x00 Offset Name Type Description Defaul t Value

Datasheet for Telink TL3828 DS-TL3828-E5 365 Ver 0.8.0 0x0f UART_STATE Volatile [2:0]: tstate_i tx state machine 0-idle 1-Start 2-Byte 3-Parity 4-Stop 5-pop byte [3]: rx_full (R) [7:4]: rstate_i rx state machine 0 -idle 1-Start 2-Bit 3-Parity 4-Stop 5-check parity 6-Prepare 7-end bit 8-lc parity 9-Wait 10-push 0x00 Offset Name Type Description Defaul t Value

Datasheet for Telink TL3828 DS-TL3828-E5 366 Ver 0.8.0 0x10 UART_CTRL4 RW [0]: rxdone_rts_en 1: rxdone enables the RTS 0: rxdone disables the RTS If rxdone_rts_en is configured to 1 and the rxdone is triggered at the same time, causing the RTS to be triggered. [1]: timeout_en 1: enable rxtimeout 0: disable rxtimeout [2]: rx_timeout_reload_sel 0: wr_o 1: REC_PREPARE state pulse [3]: rts_stop_timeout_en, Enables the counter to stop by rts [4]: pem_event_en, pem event enable [5]: reserved [6]: uart_en, uart enable [7]: reserved 0x4b 0x11 UART_RXTIMEOUT _O_EXP RW [7:0]: r_rxtimeout_exp r_rxtimeout_o[9:8]: R_rxtimeout 2’b00:rx timeout time is r_rxtimeout[7:0] * r_rxtimeout_exp 2’b01:rx timeout time is r_rxtimeout[7:0]*2 * r_rxtimeout_exp 2’b10:rx timeout time is r_rxtimeout[7:0]*3 * r_rxtimeout_exp 3’b11: rx timeout time is r_rxtimeout[7:0]*4 * r_rxtimeout_exp R_rxtimeout is for rx dma to decide the end of each transaction. Supposed the interval between each byte in one transaction is very short. 0x00 0x12 UART_PEM_CTRL RW [4:0]: pem_task_en 0x00 Offset Name Type Description Defaul t Value

Datasheet for Telink TL3828 DS-TL3828-E5 367 Ver 0.8.0

11.10 Return to Zero (RZ)

The RZ module uses a single-wire return-to-zero code protocol to communicate and transmit, and can drive pixel ICs in series or parallel; Both the data and the feature code of the zeroing code consist of a segment of high level and a segment of low level; The pixel ICs are addressed in two ways:

• Serial sequential addressing;
• Parallel random addressing.

11.10.1 Mechanism of Serial Sequential Addressing

11.10.1.1 Diagram of series connection of Pixel ICs

Figure 11-31 Series Connection of Pixel ICs As shown in the above fi gure, three Pixel ICs work in series, D1 is the data sent by the RZ module, and D2, D3, and D4 are the RZ code data forwarded by the series chips. Assuming that the data required by each chip is 24 bits, the data transmission can be obtained as shown below. The RZ module sends multiple frames of data, each of which contains 3 bits of 24-bit data, and a RESET code is sent immediately after each frame of data. F igure 11-32 RZ Data Transmission RZ Pixel IC1 DIN DOUT Pixel IC3 DIN DOUT Pixel IC2 DOUTDIN D1 D2 D3 D4 OUTPUT Data of Frame N Data of Frame N+1 3rd 24bits 3rd 24bits2nd 24bits 3rd 24bits2nd 24bits1st 24bits 3rd 24bits 3rd 24bits2nd 24bits 3rd 24bits2nd 24bits1st 24bitsD1 RESET RESET RESET RESET RESET RESET RESET RESET

Datasheet for Telink TL3828 DS-TL3828-E5 368 Ver 0.8.0

11.10.1.2 Timing Sequence of RZ

Figure 11-33 Timing Sequence of RZ for Serial Sequential Addressing As shown in the figure above, the RZ code protocol for driving a series-operated Pixel IC consists of three code elements: code 0, code 1, and RESET code, and the three code elements are differentiated by the duration of the high and low levels, which can be configured through registers T0H and T0L for the duration of the high and low levels of code 0, through registers T1H and T1L for the durati on of the high and low levels of code 1, and through registers TSRH and TSRL for the duration of the high and low levels of the RESET code.

11.10.1.3 Example of Mechanism of the RZ module to Drive series Pixel ICs

1. No global data in the data sent by the RZ module Assuming that there is no global data in the data to be sent by the RZ module, the RZ module drives a total of two Pixel ICs connected in series, and the data required to be ground for each Pi xel IC is 36bits; therefore, register RZ_CTRL1[7] is configured as 0, register GLOBAL_DATA_NUM is configured as 0, register PIXEL_NUM is configured as 1, and register PIXEL_DATA_NUM is configured as 35. (1) Case1 Assuming that the data stored in memory is aligned at 8 bits, the MSB method is used to read the data in memory; therefore, register RZ_CTRL[5] is configured as 0, and both registers RZ_C TRL[4] and RZ_CTRL[3] are confi gured as 1. Then, the diagram of the data filling in memory and the timing sequence of the data output from the RZ module are as the following two figures: Figure 11-34 Data filling in memory for case 1 T0H T0L T1H T1L Trst Code 0 Code 1 RESET code

Datasheet for Telink TL3828 DS-TL3828-E5 375 Ver 0.8.0

11.10.2 Mechanism of Parallel Random Addressing

11.10.2.1 Diagram of parallel connection of Pixel ICs

Figure 11-58 Parallel Connection of Pixel ICs As shown in the figure above, 6 Pixel ICs are working in parallel, all the chips can receive the data sent by the RZ module. When the RZ module drives the chips working in parallel, the data format of each frame sent by the RZ is shown in the figure below. Each frame contains Control Code, Address Code, RGB data and Stop Code, so each chip can recognize whether the current RGB data belongs to i t or not by Address Code. Figure 11-59 Frame data format sent by RZ module

11.10.2.2 Timing Sequence of RZ

Figure 11-60 Timing Sequence of RZ for Parallel Random Addressing As shown in the figure above, the RZ code protocol that drives the parallel operation Pixel IC contains three code elements: code 0, code 1 and STOP code, and the three code elements are distinguished by the duration of the high and low levels, which can be configured through registers T0H and T0L for the duration of the high and low levels of the code 0, through regi sters T1H and T1L for the duration of the high and low levels of the code 1, and through registers TSRH and TSRL for the duration of the high and low levels of the STOP code. RZ Pixel IC1 DIN DATA OUTPUT Pixel IC2 DIN Pixel IC3 DIN Pixel IC4 DIN Pixel IC5 DIN Pixel IC6 DIN Control Code Address Code RGB Data Stop Code Control Code Address Code RGB Data Stop Code The Nth frame of data The (N+1)th frame of data T0H T0L T1H T1L Code 0 Code 1 STOP code TSH TSL

Datasheet for Telink TL3828 DS-TL3828-E5 376 Ver 0.8.0

11.10.2.3 Example of Mechanism of the RZ module to Drive Parallel Pixel ICs

Because there is no global data in the frame data of the parallel mode, the register GLOBAL_DATA_NUM is configured as 0. Also, the sum of the bit numbers of Control Code, Address Code, and RGB data is counted as the PIXEL_DATA_NUM of each chip.Assuming that the RZ module drives a total of two Pixel ICs in parallel. Each frame contains 2 bits of Control Code, 9 bits of Address Code, and 36 bi ts of RGB data; therefore, register RZ_CTRL1[7] is configured as 1, register PIXEL_NUM is configured as 1, and register PIXEL_DATA_NUM is configured as 46. (1) Case1 Assuming that the data stored in memory is aligned at 8 bits, the MSB method is used to read the data in memory; therefore, register RZ_CTRL[5] is configured as 0, and both registers RZ_CTRL[4] and RZ_CTRL[3] are configured as 1. Then, the di agram of the data filling in memory and the timing sequence of the data output from the RZ module are as the following two figures: Figure 11-61 Data filling in memory for case 1 Figure 11-62 Data output sequence of from RZ module for case 1 (2) Case2 Assuming that the data stored in memory is aligned at 8 bits, the LSB method is used to read the data in memory; therefore, register RZ_CTRL[5] is configured to 0, and registers RZ_CTRL[4] and RZ_CTRL[3] are both configured to 0. Then the d iagram of the data fi lling in memory and the timing sequence of the data output from the RZ module are as the following two figures: A A

0 ADDR0[8:0] PIX0CH0[11:0] PIX0CH1[11:0] PIX0CH2[11:0] STOP A

A

0 ADDR1[8:0] PIX1CH0[11:0] PIX1CH1[11:0] PIX1CH2[11:0] STOP

Datasheet for Telink TL3828 DS-TL3828-E5 377 Ver 0.8.0 Figure 11-63 Data filling in memory for case 2 Figure 11-64 Data output sequence of from RZ module for case 2 (3) Case3 Assuming that the data stored in memory is aligned at 32 bits, the MSB method is used to read the data in memory; therefore, register RZ_CTRL[5] is configured to 1, and registers RZ_CTRL[4] and RZ_CTRL[3] are both configured to 1. Then the diagram of the data filling in memory and the timing sequence of the data output from the RZ module are as the following two figures: F igure 11-65 Data filling in memory for case 3 Figure 11-66 Data output sequence of from RZ module for case 3 (4) Case4 Assuming that the data stored in memory is aligned at 32 bits, the LSB method is used to read the data in memory; therefore, register RZ_CTRL[5] is configured as 1, and registers RZ_CTRL[4] and RZ_CTRL[3] are both configured as 0. Then, the diagram of the data filling in memory and the timing sequence of the data output from the RZ module are as the following two figures: A A

1 ADDR0[0:8] PIX0CH0[0:11] PIX0CH1[0:11] PIX0CH2[0:11] STOP A

A

1 ADDR1[0:8] PIX1CH0[0:11] PIX1CH1[0:11] PIX1CH2[0:11] STOP

A A A

Datasheet for Telink TL3828 DS-TL3828-E5 378 Ver 0.8.0 Figure 11-67 Data filling in memory for case 4 Figure 11-68 Data output sequence of from RZ module for case 4

11.10.3 Variable Symbol Timing (Jitters on T0L & T1L or T0H & T1H)

An example of the working mechanism of Variable symbol timing Jitter_mag is a random number generated by the random number generator, and the range of variation of the random number is selected by configuring register RZ_CTRL2[2:0]. (1) Case1 Assuming that the jitter on T0L and T1L is enabled, the random number varies from 0 to 31; therefore, register RZ_CTRL[0] is configured as 1 and regi ster RZ_CTRL2[2:0] is configured as 4. Assuming that registers T0H, T0L, T1H, and T1L are configured to be 30, 90, 60, and 60, respectively, and that the data required to be sent is 4 'b1101, the timing sequence shown below can be obtained. Figure 11-69 Variable Symbol Timing for case 1 (2) Case2 Assuming that jitter on T0L and T1L and T0H and T1H is enabled, the random number varies from 0 to 7; therefore, registers RZ_CTRL[0] a nd RZ_CTRL[1] are both confi gured as 1, and register RZ_CTRL2[2:0] is configured as 2. Assuming that registers T0H, T0L, T1H, and T1L have been configured to be 30, 90, 60, and 60, respectively. The data to be sent is 4'b1101, the timing sequence shown below can be obtained. A A A 60 60+0 60 60+5 30 90+10 60+2 bit1 bit1 bit0 bit1

Datasheet for Telink TL3828 DS-TL3828-E5 379 Ver 0.8.0 Figure 11-70 Variable Symbol Timing for case 2

11.10.4 Output Polarity

reg_Jitter_L_en = 1, reg_Jitter_H_en = 1 Figure 11-71 RZ Output Polarity

11.10.5 Register Description of RZ

The RZ related registers are listed in the following table. The base address for the following RZ related registers is 0x80240240. Table 11-21 RZ Related Registers Address Offset Name Type Description Default Value 0x00 RZ_CTRL0 W [0]: tx_clr, clear tx_fifo 0x00 symbol 0 2 1 60+3 60+3 60 60+0 30 90+10 60 60+2 bit1 bit1 bit0 bit1

Datasheet for Telink TL3828 DS-TL3828-E5 380 Ver 0.8.0 0x01 RZ_CTRL1 R/W [0]: Jitter_L_en 1: enable jitter on T0L&T1L 0: disable jitter on T0L&T1L [1]: Jitter_H_en 1: enable jitter on T0H&T1H 0: disable jitter on T0H&T1H [2]: pola, rz output wire polarity [3]: bit_msb 1: MSB of bit in byte first on rz output wire 0: LSB of bit in byte first on rz output wire [4]: big_endian_mode 1: MSB of byte in word first on rz output wire 0: LSB of byte in word first on rz output wire [5] align_32bits_mode 1: each pixel data at 32bits boundary 0: each pixel data at 8bits boundary [6] global_data_mode 1: global data is after the pixel data of all pixel data 0: global data is after the pixel data of each pixel data [7] addr_mode 1: random addressing mode 0: sequential addressing mode 0x00 0x02 RZ_CTRL2 R/W [2:0] Jitter range, units: Tpclk 0: Jitter range is 0~1 1: Jitter range is 0~3 2: Jitter range is 0~7 3: Jitter range is 0~15 4: Jitter range is 0~31 5: Jitter range is 0~63 6: Jitter range is 0~127 7: Jitter range is 0~255 [5:3]: fifo_lvl [7]: auto_txclr_en, enable auto clear txfifo 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 381 Ver 0.8.0 0x03 RZ_FIFO_STS R [3:0]: tx_buf_cnt [4]: tx_empty [5]: tx_full [6]: rz_en, rz module enable status 0x00 0x04 RZ_T0H_L R/W [7:0]: T0H[7:0] 0x00 0x05 RZ_T0H_H R/W [2:0]: T0H[10:8] 0x00 0x06 RZ_T0L_L R/W [7:0]: T0H[7:0] 0x00 0x07 RZ_T0L_H R/W [2:0]: T0H[10:8] 0x00 0x08 RZ_T1H_L R/W [7:0]: T0H[7:0] 0x00 0x09 RZ_T1H_H R/W [2:0]: T0H[10:8] 0x00 0x0a RZ_T1L_L R/W [7:0]: T0H[7:0] 0x00 0x0b RZ_T1L_H R/W [2:0]: T0H[10:8] 0x00 0x0c RZ_TSRH_L R/W [7:0]: tsrh[7:0], tsrh: tstoph/treseth 0x00 0x0d RZ_TSRH_H R/W [7:0]: tsrh[15:8], tsrh: tstoph/treseth 0x00 0x0e RZ_TSRL_L R/W [7:0]: tsrl[7:0], tsrl: tstopl/tresetl 0x00 0x0f RZ_TSRL_H R/W [7:0]: tsrl[15:8], tsrh: tstopl/tresetl 0x00 0x10 RZ_PIXEL_NUM_L R/W [7:0]: pixel_num[7:0] 0x00 0x11 RZ_PIXEL_NUM_H R/W [0]: pixel_num[8] 0x00 0x12 RZ_GLOBAL_DATA_N UM_L R/W [7:0]: global_data_num[7:0] 0x00 0x13 RZ_GLOBAL_DATA_N UM_H R/W [0]: global_data_num[8] 0x00 0x14 RZ_DATA_BIT_NUM_ PER_PIXEL_L R/W [7:0]: pixel_data_num[7:0] 0x00 0x15 RZ_DATA_BIT_NUM_ PER_PIXEL_H R/W [0]: pixel_data_num[8] 0x00 0x16 RZ_MASK R/W [0]: mask_lvl [1]: mask_txdone [2]: mask_error [3]: pem_event_en 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 382 Ver 0.8.0

11.11 Quadrature Decoder (QDEC)

The SoC embeds two identical Quadrature Decoders (QDEC), QDEC0 and QDEC1, which are designed mainly for applications such as wheel. The QDECs implement debounce function to filter out jitter on the two phase inputs, and generates smooth square waves for the two phase.

11.11.1 Input Pin Selection

Both QDEC0 and QDEC1 support two phase input; each input is selectable from the 8 pins of PortD, PortC, PortB and PortA vi a setting address 0x02[2:0] (for channel a)/0x03[2:0] (for channel b). Table 11-22 Input Pin Selection

11.11.2 Common Mode and Double Accuracy Mode

The QDEC embeds an internal hardware counter, which is not connected with bus. 0x17 RZ_INT W1C [0]: clr_int_lvl [1]: clr_int_txdone [2]: clr_int_error 0x00 0x18 RZ_TX_DAT_0 R/W [7:0]: tx_wdat[7:0] w:tx_wdat[7:0], r:tx_rdat 0x00 0x19 RZ_TX_DAT_1 W [7:0]: tx_wdat[15:8] 0x00 0x1a RZ_TX_DAT_2 W [7:0]: tx_wdat[23:16] 0x00 0x1b RZ_TX_DAT_3 W [7:0]: tx_wdat[31:24] 0x00 Address offset 0x02[2:0]/0x03[2:0] Pin

0 PA[2]

1 PA[3]

2 PB[6]

3 PB[7]

4 PC[2]

5 PC[3]

6 PD[6]

7 PD[7]

NOTE: To use corresponding IO as QDEC input pin, it's needed first to enable GPIO function, enable "IE" (1) and disable "OEN" (1) for this IO.

Datasheet for Telink TL3828 DS-TL3828-E5 383 Ver 0.8.0 Address 0x07 serves to select common mode or double accuracy mode. For each wheel rolling step, two pulse edges (rising edge or falling edge) are generated. If address 0x07 is cleared to select common mode, the QDEC Counter value (real time counting value) is increased/decreased by 1 only when the same rising/falling edges are detected from the two phase signals. Figure 11-72 Common Mode If address 0x07[0] is set to 1’b1 to select double accuracy mode, the QDEC Counter value (real time counting value) is i ncreased/decreased by 1 on each rising/falling edge of the two phase signals; the COUNT0 will be increased/decreased by 2 for one wheel rolling. One wheel rolling COUNT0 value increased by 1 Another wheel rolling COUNT0 value increased by 1 One wheel rolling COUNT0 value decreased by 1 Another wheel rolling COUNT0 value decreased by 1

Datasheet for Telink TL3828 DS-TL3828-E5 384 Ver 0.8.0 Figure 11-73 Double Accuracy Mode

11.11.3 Read Real Time Counting Value

Neither can Hardware Counter value be read directly via software, nor can the counting value in address 0x00 be updated automatically. To read real time counting value, first write address 0x08[0] with 1’b1 to load Hardware Counter data into the QDEC_COUNT register, then read address 0x00. One wheel rolling COUNT0 value increased by 1 Another wheel rolling COUNT0 value increased by 1 COUNT0 value increased by 1 COUNT0 value increased by 1 One wheel rolling COUNT0 value decreased by 1 Another wheel rolling COUNT0 value decreased by 1 COUNT0 value decreased by 1 COUNT0 value decreased by 1

Datasheet for Telink TL3828 DS-TL3828-E5 385 Ver 0.8.0 Figure 11-74 Read Real Time Counting Value

11.11.4 QDEC Reset

Address 0x80140823[5] serves to reset the QDEC0, address 0x80140823[0] serves to reset the QDEC0. The QDEC Counter value is cleared to zero.

11.11.5 Other Configuration

The QDEC supports hardware debouncing. Address 0x01[2:0] serves to set filtering window duration. All jitter with period less than the value will be filtered out and thus does not trigger count change. Address 0x01[4] serves to set input si gnal initial polarity. Address 0x01[5] serves to enable shuttle mode. Shuttle mode allows non-overlapping two phase signals as shown in the following figure. Figure 11-75 Shuttle Mode Hardware Counter Digital Register QDEC_COUNT (address 0xd0) 1) Write “1” to address 0xd8[0] to load data QDEC 2) Read

Datasheet for Telink TL3828 DS-TL3828-E5 386 Ver 0.8.0

11.11.6 Timing Sequence

Figure 11-76 Timing Sequence Chart Table 11-23 Timing Interval and Minimum Value The QDEC module works based on 32 kHz clock to ensure it can work in suspend mode. QDEC module supports debouncing function, and any signal with width lower than the threshold (i.e. “2^(n+1) *clk_32kHz *3 (n=0x01[2:0])) will be regarded as jitter. Therefore, effective signals input from Channel A and B should contain high/low level with width Thpw/Tlpw more than the threshold. The 2^n *clk_32kHz clock is used to synchronize input signal of QDEC module, so the interval between t wo adjacent ri sing/falling edges from Channel A and B, which are marked as Triw and Tfiw, should exceed “2^(n+1) *clk_32kHz”. Only when the timing requirements above are met, can QDEC module recognize wheel rolling times correctly. Time Interval Min Value Thpw (High-level pulse width) 2^(n+1) *clk_32kHz *3 (n=0x41[2:0]) Tlpw (Low-level pulse width) 2^(n+1) *clk_32kHz *3 (n=0x41[2:0]) Triw (Interval width between two rising edges) 2^(n+1) *clk_32kHz (n=0x41[2:0]) Tfiw (Interval width between two falling edges) 2^(n+1) *clk_32kHz (n=0x41[2:0]) One wheel rolling Another wheel rolling Thpw Tlpw A channel B channel One wheel rolling Another wheel rolling Triw Tfiw A channel B channel

Datasheet for Telink TL3828 DS-TL3828-E5 387 Ver 0.8.0

11.11.7 Register Description of QDEC

The QDEC related registers are listed in the following table. For QDEC0 related register, the base address is 0x80140240, for QDEC1 related register, the base address is 0x80140180. Table 11-24 QDEC Related Registers

11.12 PWM

The SoC supports 24-channel PWM (Pulse-Width-Modulation) output, including 7 full channels and 17 simple channels. Each PWM#n (n=0~23) has its corresponding inverted output at PWM#n_N pin. Each PWM channel h as independent counter and 3 status including “Phase”, “Pulse” and “Remaining”. There are two waveforms for the 7 full channels PWM#n (n=0~6). When register PWM_phase_mode#n (n=0~6) is set to 1, the Phase state is located in every PWM cycle, and when register PWM_phase_mode#n (n=0~6) is set to 0, the Phase state is located in before all PWM cycles. Additionally, the PWM#n (n=0~6) of the 7 full channels support extra features such as dead time, enhanced resolution w ith di thering, and deep dimming synchronization.

11.12.1 Enable PWM

The register PWM_EN_B0 ~ PWM_EN_B3 serve to enable PWM0 ~ PWM23 respectively via writing “1” for the corresponding bits. Address offset Name Type Description Reset Value 0x00 QDEC_COUNT0 R [7:0] QDEC Counting value (read to clear): Pulse edge number 0x00 0x01 QDEC_DBNTIME RW [2:0]: dbntime, dbntime=r01[2:0] [4]: pola, pola=r01[4] [5]: shuttle0, shuttle0=r01[5] 0x00 0x02 QDEC_CHANNEL_A0 RW [2:0]: channel_a0, channel_a0=r02[3:0] 0x00 0x03 QDEC_CHANNEL_B0 RW [2:0]: channel_b0, channel_b0=r03[3:0] 0x01 0x04 QDEC_MASK RW [0] mask, mask=r04[0] 0x00 0x05 QDEC_INT0 W1C [0] int0, r05[0]=int0 0x00 0x06 QDEC_READ R [7:0] dat_o 0x00 0x07 QDEC_DOUBLE0 RW [0]: double0 [1]: pem_event_en 0x01 0x08 QDEC_COUNT0_RELOAD RW [0]: count0_reload, r08[0]=count0_reload 0x00

Datasheet for Telink TL3828 DS-TL3828-E5 388 Ver 0.8.0

11.12.2 Set PWM Clock

PWM clock derives from system clock. Register PWM_CTRL_B0[7:0] serves to set the frequency dividing factor for PWM clock. Formula below applies: FPWM= FSystem_clock / (clkdiv+1)

11.12.3 PWM Waveform, Polarity and Output Inversion

11.12.3.1 Waveform of Signal Frame

For the 17 simple channels, as well as when the PWM_phase_mode#n (n=0~6) of the 7 full channels is set to 1'b0, the Phase state is before all PWM cycles, so each PWM cycle consists of the Pulse state and the Remai ning state. When PWM#n is enabled, the counter of PWM#n starts counting, and PWM#n enters the Phase state and outputs a low signal by default. When 'counter == PWM_PHASE#n', the counter will be reset to 0, PWM#n completes the output of the Phase state signal, PWM#n enters into the Pulse state, and outputs high level signal by default. When 'counter == PWM_TCMP#n', PWM#n enters the Remaini ng state and outputs low level signal by default. When 'counter == PWM_TMAX#n', the counter will be reset to 0, PWM#n completes one cycle of signal output, enters the Pulse state of the next cycle, and outputs a high level signal by default, and so on. If 'PWM_PHASE#n == 0', there is no Phase state before all PWM cycles; if 'PWM_PHASE#n > 0', there is Phase state before all PWM cycles. If 'PWM_TCMP#n == 0', there i s no Pulse state for every PWM cycle. If 'PWM_TCMP#n >= PWM_TMAX#n', there is no Remaining state for every PWM cycle. If '0 < PWM_TCMP#n < PWM_TMAX#n', there are Pulse state and Remaining state for every PWM cycle. The detailed waveform format is shown as below.

Datasheet for Telink TL3828 DS-TL3828-E5 389 Ver 0.8.0 Figure 11-77 PWM Waveform 1 When PWM_phase_mode#n (n=0~6) is 1'b1, the Phase state is located in every PWM cycle, therefore every PWM cycle consists of Phase state, Pulse state and Remaining state. When PWM#n is enabled, the counter of PWM#n starts counting, and PWM#n enters the Phase state and outputs a low signal by default. When 'counter == PWM_PHASE#n', PWM#n enters the Pulse state and outputs high level si gnal by default. When 'counter == (PWM_PHASE#n + PWM_TCMP#n)', PWM#n enters the Remaining state, and outputs low level signal by default. When 'counter == PWM_TMAX#n', the counter will be reset to 0, PWM#n completes one cycle of signal output, and enters the Phase state of the next cycle, and outputs a low level signal by default. If 'PWM_TCMP#n == 0', there is no Phase state and Pulse state for each PWM cycle.

Datasheet for Telink TL3828 DS-TL3828-E5 390 Ver 0.8.0 If 'PWM_TCMP#n >= PWM_TMAX#n', there is no Phase state and Remaining state for every PWM cycle. When '0 < PWM_TCMP#n < PWM_TMAX#n', if 'PWM_PHASE#n >= PWM_TMAX#n', there is no Pulse state and no Remaining state for every PWM cycle. When '0 < PWM_TCMP#n < PWM_TMAX#n', if 'PWM_PHASE#n < PWM_TMAX#n' and '(PWM_PHASE#n + PWM_TCMP#n) < PWM_TMAX#n', there are Phase state, Pulse state and Remai ning state for each PWM cycle. When '0 < PWM_TCMP#n < PWM_TMAX#n', if 'PWM_PHASE#n < PWM_TMAX#n', and '(PWM_PHASE#n + PWM_TCMP#n) >= PWM_TMAX#n', then there is no Remaining state for each PWM cycle. It is worth noting that at this time, the Pulse state of the previous cycle will overwrite the part of the Phase state of the next cycle. The detailed waveform format is shown as below. Figure 11-78 PWM Waveform 2

Datasheet for Telink TL3828 DS-TL3828-E5 391 Ver 0.8.0

11.12.3.2 Invert PWM Output

The PWM#n and PWM#n_N output could be inverted independently via register PWM_inv#n (n=0~23) and PWM_pos#n (n=0~23). When the inversion bit is enabled, waveform of the corresponding PWM channel will be inverted completely.

11.12.3.3 Polarity for Signal Frame

By default, the PWM#n outputs High level at Pulse status and Low level at Remaining status. When the corresponding polarity bit is enabled via register PWM_pola#n (n=0~23), PWM#n wi ll output Low level at Pulse status and High level at Remaining status. The output of PWM#n at Phase status is not affected by the corresponding polarity bit. The corresponding polarity bit can only be enabled when PWM_phase_mode#n (n=0~6) is set to 1'b0. The PWM output waveform is shown as below. Figure 11-79 PWM Output Waveform Chart

Datasheet for Telink TL3828 DS-TL3828-E5 392 Ver 0.8.0

11.12.4 PWM Mode

11.12.4.1 Select PWM Modes

The PWM0 supports five modes, including Continuous mode (normal mode, default), Counting mode, IR mode, IR FIFO mode, IR DMA FIFO mode. However, when the PWM0 phase_mode is 1’b1, the PWM0 only support Continuous mode. PWM1 ~ PWM23 only support Continuous mode. Register PWM_CTRL_B1[3:0] serves to select PWM0 mode.

11.12.4.2 Continuous Mode

PWM0~PWM23 all support Continuous mode. In this mode, PWM#n continuously sends out signal frames. PWM#n should be disabled via PWM_EN_B0 ~ PWM_EN_B3 to stop i t; when stopped, the PWM output will turn low immediately. When the PWM_phase_mode#n is 1’b0, during Continuous mode, waveform could be changed freely via PWM_TCMP#n and PWM_TMAX#n. New configuration for PWM_TCMP#n and PWM_TMAX#n will take effect when 'counter == PWM_TMAX#n'. After each signal frame is finished, corresponding PWM cycle done interrupt flag bit (PWM_CYC_INT_B0 ~ PWM_CYC_INT_B2) will be automatically set to 1’b1. If the interrupt is enabled by setting PWM_irq_cycdone_mask#n (n=0~23) as 1’b1, a frame interruption will be generated. User needs to write 1’b1 to the flag bit to manually clear it. Figure 11-80 Continuous Mode (PWM_PHASE_MODE#n = 1'b0) When PWM_PHASE_MODE#n is 1, during Continuous mode, the waveform could be c hanged vi a PWM_PHASE#n, PWM_TCMP#n and PWM_TMAX#n. New configuration for PWM_PHASE#n, PWM_TCMP#n and PWM_TMAX#n will take effect when 'counter == PWM_TMAX#n' and 'PWM_CLR_TXFIFO[1] == 1'b1'. After the new configuration takes effect, PWM_CLR_TXFIFO[1] is reset to 1'b0. After each signal frame is finished, corresponding PWM cycle done interrupt flag bit (PWM_CYC_INT_B0 ~ PWM_CYC_INT_B2) will be automatically set to 1'b1. If the i nterrupt is enabled by setting PWM_irq_cycdone_mask#n (n=0~23) as 1'b1, a frame interruption will be generated. User needs to write 1'b1 to the flag bit to manually clear it. NOTE: When '0 < PWM_TCMP#n < PWM_TMAX#n', 'PWM_PHASE#n < PWM_TMAX#n', and '(PWM_PHASE#n + PWM_TCMP#n) >= PWM_TMAX#n', PWM Output Waveform is special, as detailed in 11.12.6 PWM Load.

Datasheet for Telink TL3828 DS-TL3828-E5 393 Ver 0.8.0 Figure 11-81 Continuous Mode (PWM_PHASE_MODE#n = 1'b1)

11.12.4.3 Counting Mode

Only PWM0 supports Counting mode. PWM_CTRL_B1[3:0] should be set as 4’b0001 to select PWM0 counting mode. In this mode, PWM0 sends out specified number of signal frames which is defined as a pulse group. The number is configured via register PWM0_PNUM. When a group of signals are transmitted, PWM0_EN will be automatically disabled, PWM0 will immediately toggle the transmission signal to low. Write PWM1_CFG_B6[6] to 1 to enable interrupt. At the end of each cycle, set P WM_CYC_INT_B0[0] to 1 to generate i nterrupt. Write PWM_CYC_INT_B0[0] to 1 to clear the interrupt. Write PWM_CTRLB2[0] to 1 to enable the pnum interrupt. After transmitting a group of signals, set PWM_ INT[0] to 1 to generate interrupt. Write PWM_ INT[0] to 1 to clear the interrupt. Counting mode also serves to stop IR mode gracefully. Figure 11-82 Counting Mode

11.12.4.4 IR Mode

Only PWM0 supports IR mode. PWM_CTRL_B1[3:0] should be set as 4’b0011 to select PWM0 IR mode. In this mode, specified number of frames is defined as one pulse group. In contrast to Counti ng mode where PWM0 stops after first pulse group is finished, PWM0 will constantly send pulse groups in IR mode. During IR mode, PWM0 output waveform could also be changed freely via PWM_TCMP0, PWM_TMAX0 and PWM_PNUM0. New configuration for PWM_TCMP0, PWM_TMAX0 and PWM_PNUM0 will take effect in the next pulse group.

Datasheet for Telink TL3828 DS-TL3828-E5 394 Ver 0.8.0 To stop IR mode and complete current pulse group, user can switch PWM0 from IR mode to Counting mode so that PWM0 will stop after current pulse group is finished. If PWM0 is disabled directly via PWM_EN0[0], PWM0 output will turn Low immediately despite of current pulse group. After each signal frame/pulse group is finished, PWM0 cycle done interrupt flag bit (PWM_CYC_INT_B0[0 ])/ P WM0 pnum interrupt flag bit (PWM_INT[0]) will be automatically set to 1’b1. A frame interruption/Pnum interruption will be generated. Figure 11-83 IR Mode

11.12.4.5 IR FIFO Mode

IR FIFO mode is designed to allow IR transmission of long code patterns without the continued intervention of MCU, and it is designed as a selectable working mode on PWM0. The IR carrier frequency is divided down from the system clock and can be configured as any normal IR frequencies, e.g. 36 kHz, 38 kHz, 40 kHz, or 56 kHz. Only PWM0 supports IR FIFO mode. PWM_CTRL_B1[3:0] should be set as 4’b0111 to select PWM0 IR FIFO mode. An element (“FIFO CFG Data”) is defined as basic unit of IR waveform, and written into FIFO. This element consists of 16 bits, including:

• bit[13:0] defi nes PWM cycles of current group.
• bit[14] determines the source of cmp and max value of the PWM signal in current group. º 1: use configuration of PWM_TCMP_FSK_L/PWM_TCMP_FSK_H and PWM_TMAX_FSK_L/ PWM_TMAX_FSK_H. º 0: use configuration of TCMP0 and TMAX0.
• bit[15] determines whether current PWM pulse group is used as carrier, i.e. whether PWM will output pulse (1) or low level (0). User should use PWM_RDAT_L0, PWM_RDAT_H0, PWM_RDAT_L1, PWM_RDAT_H1 to write the 16-bit “FIFO CFG Data” into FIFO by byte or half word or word.
• To wri te by byte, user should successively write 0x00, 0x01, 0x02 and 0x03.
• To write by half word, user should successively write 0x00 and 0x02.
• To write by word, user should write 0x00. The FIFO depth is 8 bytes. User can read the register PWM_FIFO_STS in 0x14 to view FIFO empty/full status and check FIFO data number.

Datasheet for Telink TL3828 DS-TL3828-E5 395 Ver 0.8.0 Figure 11-84 IR Format Examples When “FIFO CFG Data” is configured in FIFO and PWM0 is enabled via PWM1_CFG_B6[6], the configured waveforms will be output from PWM0 in sequence. As long as FIFO doesn’t overflow, user can continue to add waveforms during IR waveforms sending process, and long IR code that exceeds the FIFO depth can be implemented this way. After all waveforms are sent, FIFO becomes empty, PWM0 will be disabled automatically. The FIFO_CLR register serves to clear data in FIFO. Writing 1 to this register will clear all data in the FIFO. Note that the FIFO can only be cleared when not in active transmi ssion.

11.12.4.6 IR DMA FIFO Mode

IR DMA FIFO mode is designed to allow IR transmission of long code patterns without occupation of MCU, and it is designed as a selectable working mode on PWM0. The IR carrier frequency is divided down from the system clock and can be configured as any normal IR frequencies, e.g. 36 kHz, 38 kHz, 40 kHz, or 56 kHz. Only PWM0 supports IR DMA FIFO mode. PWM_CTRL_B1[3:0] should be set as 4’b1111 to select PWM0 IR DMA FIFO mode. This mode is similar to IR FIFO mode, except that “FIFO CFG Data” is written into FIFO by DMA instead of MCU. User should write the configuration of “FIFO CFG Data” into RAM, and then enable DMA channel 5. DMA will automatically write the configuration into FIFO.

11.12.5 PWM Interrupt

There are 27 i nterrupt sources from PWM function. After each signal frame, PWM#n (n = 0 ~ 23) will generate a frame-done IRQ (Interrupt Request) signal. In Counting mode and IR mode, PWM0 will generate a Pnum IRQ signal after completing a pulse group. NOTE: In this mode, when DMA channel 5 is enabled, PWM will automatically output configured waveform, without the need to manually enable PWM0 via PWM1_CFG_B6[6] (i.e. PWM1_CFG_B6[6] will be set as 1’b1 automatically).

Datasheet for Telink TL3828 DS-TL3828-E5 396 Ver 0.8.0 In IR FIFO mode, PWM0 will generate a FIFO mode count IRQ signal when the tx_buf_cnt value is less than the FIFO_LVL, and will generate a FIFO mode stop IRQ signal after FIFO becomes empty. In IR DMA FIFO mode, PWM0 will generate an IR waveform send done IRQ signal, after DMA has sent all configuration data, FIFO becomes empty and final waveform is sent.

11.12.6 PWM Load

When PWM_phae_mode#n is 1, duri ng Continuous mode, waveform could be changed via PWM_PHASE#n, PWM_TCMP#n and PWM_TMAX#n. New configuration for PWM_PHASE#n, PWM_TCMP#n and PWM_TMAX#n will take effect when 'counter == PWM_TMAX#n' and 'PWM_LOAD == 1'b1'. After the new configuration takes effect, PWM_LOAD is reset to 1'b0. Assume the register value of current cycle are: PWM_PHASE#n_old, PWM_TCMP#n_old and PWM_TMAX#n_old; The regi ster value of PWM load are PWM_PHASE#n_new, PWM_TCMP#n_new and PWM_TMAX#n_new. When '0 < PWM_TCMP#n_old < PWM_TMAX#n_old', 'PWM_PHASE#n_old < PWM_TMAX#n_old', and '(PWM_PHASE#n_old + PWM_TCMP#n_old) >= PWM_TMAX#n_old', PWM Output Waveform is special, the details are as follows. When 'PWM_TCMP#n_new == 0', there is no Phase state and Pulse state for every PWM cycle after the load. Figure 11-85 PWM cycle after load 1 When 'PWM_TCMP#n_new >= PWM_TMAX#n_new', there i s no Phase state and Remaining state for every PWM cycle after the load. Figure 11-86 PWM cycle after load 2 When '0 < PWM_TCMP#n_new < PWM_TMAX#n_new' and 'PWM_PHASE#n_new >= PWM_TMAX#n_new', there is no Remaining state for each PWM cycle after the load. It is worth noting that the Pulse state of the cycle before the load overwrites the portion of the Phase state of the cycle after the load.

Datasheet for Telink TL3828 DS-TL3828-E5 398 Ver 0.8.0 Figure 11-90 PWM cycle after load 6

11.12.7 PWM Center Align Mode

The PWM#n (n=0~23) support center align mode. Since the PWM#n (n=0~6) is divided into two waveforms according to PWM_phase_mode#n, the PWM center align mode can also be divided into two waveforms according to PWM_phase_mode#n. When PWM_phase_mode#n == 1'b0, the waveform in center align mode is shown as below. Figure 11-91 PWM Center Align Mode 1 When PWM_phase_mode#n == 1'b1, the waveform in center align mode i s shown as below.

Datasheet for Telink TL3828 DS-TL3828-E5 399 Ver 0.8.0 Figure 11-92 PWM Center Align Mode 2

11.12.8 PWM Dead Time

The working principle of Dead Time is: when configuring PWM_dead_time#n to zero, the waveform of PWM#n and PWM_N#n are inverted as shown below:

Datasheet for Telink TL3828 DS-TL3828-E5 400 Ver 0.8.0 Figure 11-93 PWM_Dead_TIME#n is zero When configuring PWM_dead_time#n to a non-zero value, the pulse rising edge of PWM#n and PWM_N#n is delayed for a period of time td, and the falling edge of pulse remains unchanged, so as to avoid the overlap between the pulses of PWM#n and PWM_N#n, as shown in the following figure: Figure 11-94 PWM_Dead_TIME#n is non-zero

11.12.9 Enhanced Resolution with Dithering

Enhanced resolution with dithering only supports 'PWM_phase_mode#n == 1'b1'. Enhanced resoluti on with dithering supports center align mode.

11.12.9.1 Lookup Table

The lookup table is used to indicate the presence of jitter in the Pulse state for the current cycle. In the lookup table, 5LSB is register PWM_resol#n[4:0] and SLOT is the PWM cycle number. From the lookup table, we can

Datasheet for Telink TL3828 DS-TL3828-E5 401 Ver 0.8.0 see that 32 PWM cycles are a group, that is, 32 SLOTs are a group, and when register PWM_resol#n[4:0] is set in the current group, it takes effect in the next group. Figure 11-95 Lookup Table

11.12.9.2 Principle of enhanced resolution with dithering

The default value of PWM_resol#n[4:0] (n=0~6) is 5'b00000, that is, Enhanced resolution with dithering is not enabled by default; The following takes example to illustrate the working principle of Enhanced resoluti on with dithering.

• Case1: When 'PWM_resol#n[4:0] == 5'b00000', from the lookup table, we can see that the dither corresponding to all SLOTs is 0, so there is no dithering in the Pulse state in every cycle, that is, in every cycle, when 'counter == PWM_TCMP#n', PWM#n enters Remaining state.
• Case2: When 'PWM_resol#n[4:0] == 5'b00001', from the lookup table, 'SLOT == 0', the corresponding dither is 1, and the other SLOT correspondi ng dither are 0, so there is jitter in the Pulse state in the 1st cycle, that is, PWM#n enters Remaining state in the 1st cycle when 'counter == PWM_TCMP#n+ 1'. The Pulse state in all other cycles is not jittered, that is, in the 2nd to 32nd cycle, PWM#n enters Remaining state when 'counter == PWM_TCMP#n'. If register PWM_resol#n[4:0] is not reset in the current group, the waveform of PWM#n output i n the next group of 32 cycles is the same as the waveform of PWM#n output in the current group of 32 cycles. If register PWM_resol#n[4:0] is reset in the current group, the waveform output by PWM#n in the next set of 32 cycles is the same as the waveform output by PWM#n in the current set of 32 cycles according to the new PWM_resol#n[4:0].
• Case3: When 'PWM_resol#n[4:0] == 5'b00010', from the lookup table, 'SLOT == 0' and ' SLOT == 16', the correspondi ng dither is 1, and the dither corresponding to all other SLOTs is 0. Therefore, there is jitter in the Pulse state in the 1st and 17th cycles, that is, in the 1st and 17th cycles, 'counter == PWM_TCMP#n + 1 ' when PWM#n enters the Remaining state. There is no jitter in the Pulse state in any of the other cycles, that i s, in the other cycles, PWM#n enters the Remaining state when 'counter == PWM_TCMP#n'. SLOT 5SLB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 00000 00001 1 00010 1 1 00011 111 00100 1111 00101 111 1 1 00110 111 111 00111 1111111 01000 11111111 01001 1 1 1111111 01010 1 1 1111 1 111 01011 111 111 111 1 1 01100 111 111 111 111 01101 1111111 111 111 01110 1111111 1111111 01111 111111111111111 10000 1111111111111111 10001 1 1 111111111111111 10010 1 1 11111111 1 1111111 10011 1 1 1111 1 1111 1 1111111 10100 1 1 1111 1 1111 1 1111 1 111 10101 1 1 11 1 11 1 1111 1 1111 1 111 10110 111 111 111 1 1 111 111 111 1 1 10111 111 111 111 111 111 111 111 1 1 11000 111 111 111 111 111 111 111 111 11001 1111111 111 111 111 111 111 111 11010 1111111 111 111 1111111 111 111 11011 1111111 1111111 1111111 111 111 11100 1111111 1111111 1111111 1111111 11101 111111111111111 1111111 1111111 11110 111111111111111 111111111111111 11111 1111111111111111111111111111111

Datasheet for Telink TL3828 DS-TL3828-E5 402 Ver 0.8.0

• and so forth.

11.12.10 Deep Diming Synchronization

Deep Diming Synchronization only supports 'PWM_phase_mode#n == 1'b1'. Deep Diming Synchronization does not support center align mode.

11.12.10.1 Principle of Deep Diming Synchronization

Deep Diming Synchronization means that in every cycle, the moment PWM#n enters Pulse state from Phase state needs to be aligned with the effective edge of the input signal outside the chip (PWM_sync_edge#n == 1'b0, the effective edge i s the rising edge; PWM_sync_edge#n == 1'b1, the effective edge is the falling edge). All PWM#n (n = 0~6) from Phase state into Pulse state are aligned only with the edges of the input signals external to the same chip. Deep Diming Synchronization does not affect the duration of the Pulse state per cycle. When 'PWM_phase_mode#n == 1'b1' and 'PWM_sync_en#n == 1'b1', Deep Diming Synchronization is enabled. When PWM#n i s enabled, PWM#n's counter starts counting and PWM#n enters Phase state. When 'counter == PWM_PHASE#n', PWM#n will not enter Pulse state immediately, and needs to wait for the valid edge of the input signal outside the chip. When the valid edge of the input signal from outside the chip arrives, PWM#n will enter the Pulse state and record the value of counter as CNT_SYNC#n at this moment. When 'counter == (PWM_TCMP#n + CNT_SYNC#n)', PWM#n enters i nto the Remaining state as shown below. Figure 11-96 PWM#n Cycle for Deep Diming Synchronization 1 If after 'counter == PWM_PHASE#n' and before 'counter == PWM_TMAX#n', there is no waiting for a valid edge of the input signal from outside the chip, the current cycle PWM#n always outputs a low level, as shown in the following figure.

Datasheet for Telink TL3828 DS-TL3828-E5 403 Ver 0.8.0 Figure 11-97 PWM#n Cycle for Deep Diming Synchronization 2

11.12.11 Register Description of PWM

The PWM related registers are listed as following. The base address for below registers is 0x80140E00. Table 11-25 PWM Registers Address Offset Name Type Description Default Value 0x00 PWM_RDAT_L0 RW [7:0]: tx_dat_num0_l, tx_rdat0[7:0] 0x00 0x01 PWM_RDAT_H0 RW [5:0]: tx_dat_num0_h, tx_rdat0[13:8] [6]: fsk_sel0, tx_rdat0[14] [7]: carryb0, tx_rdat0[15] 0x00 0x02 PWM_RDAT_L1 W [7:0]: tx_dat_num1_l 0x00 0x03 PWM_RDAT_H1 W [5:0]: tx_dat_num1_h [6]: fsk_sel1 [7]: carryb1 0x00 0x04 PWM_TCMP_FSK_L RW [7:0]: tcmp_fsk_l, tcmpb_fsk[7:0] 0x00 0x05 PWM_TCMP_FSK_H RW [7:0]: tcmp_fsk_h, tcmpb_fsk[15:8] 0x00 0x06 PWM_TMAX_FSK_L RW [7:0]: tmax_fsk_l, tmaxb_fsk[7:0] 0x00 0x07 PWM_TMAX_FSK_H RW [7:0]: tmax_fsk_h, tmaxb_fsk[15:8] 0x00 0x08 PWM_PHASE_FSK_L RW [7:0]: phase_fsk_l, phase_fsk[7:0] 0x00 0x09 PWM_PHASE_FSK_H RW [7:0]: phase_fsk_h, phase_fsk[15:8] 0x00 0x0a PWM0_PNUM_L RW [7:0]: pnum_l, pwm0 num[7:0] 0x00 0x0b PWM0_PNUM_H RW [5:0]: pnum_h, pwm0 num[13:8] 0x00 0x0c PWM0_NCNT_L R [7:0]: pwm0_numcnt_l, pwm0 num cnt value[7:0] 0x00 0x0d PWM0_NCNT_H R [5:0]: pwm0_numcnt_h, pwm0 num cnt value[13:8] 0x00

Datasheet for Telink TL3828 DS-TL3828-E5 404 Ver 0.8.0 0x10 PWM_CTRL_B0 RW [7:0]: clkdiv 0x0 0x11 PWM_CTRL_B1 RW [0]: crun_o [1]: catch_o [2]: fifio_mode_en [3]: txdma_en [4]: out2ana_en_o, 1: ir2ana = pwm0, 0: ir2ana = 0 [5]: auto_txclr_off, auto_txclr_off [6]: txf_nempty_en, txf_nempty_en 0x0 0x12 PWM_CTRL_B2 RW [0]: irq_pwm_num_mask, mask irq_pwm_num [1]: irq_fifo_mask, mask irq_fifo_done [2]: irq_lvl_mask, mask irq_lvl [7:4]: out2ana_en_o, the fifo level of generating irq_lvl 0x0 0x13 PWM_CTRL_B3 RW [1: 0]: pem_event_sel 0: {1’b0, period_start} 1: {1'b0, cycdone} 2: {5'h0, hit_lvl, fifo_done, pwmdone} [2]: pem_event_en, pem event enable [3]: pem_task_sel 0: task[3:0] to set pwm0~3 enable, task[7:4] to set pwm0~3 disable 1: task[2:0] to set pwm4~6 enable, task[5:3] to set pwm4~6 disable [4]: rsvd [5]: resol_up_mode_o 1: resol updates after the current cycle is completed 0: resol updates after 32 cycles are completed [6]: dith_mode_o 1: dithering does not affect the update criteria, but only the high time 0: dithering affects the update criteria and the high time 0x0 0x14 PWM_FIFO_STS R [3:0]: tx_buf_cnt [4]: tx_empty [5]: tx_full 0x10 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 405 Ver 0.8.0 0x15 PWM_CLR_TXFIFO W [0]: tx_clr, clear: write 1; normal(default): write 0 [1]: reload_pul_o, reload_cfg 0x0 0x16 PWM_INT W1C [0]: irq_pwm_num, pwm_num done irq [1]: irq_fifo_done, fifo_done irq [2]: irq_lvl, fifo level hit irq 0x00 0x17 PWM_TASK_EN RW [7:0]: pem_task_en, pem task enable 0x00 0x18 PWM_CYC_INT_B0 W1C [7:0]: irq_cycdone0_7, pwm0_7 cycdone irq 0x00 0x19 PWM_CYC_INT_B1 W1C [7:0]: irq_cycdone8_15, pwm8_15 cycdone irq 0x00 0x1a PWM_CYC_INT_B2 W1C [7:0]: irq_cycdone16_23, pwm16_23 cycdone irq 0x00 0x1c PWM_EN_B0 RW [7:1]: pwm_en1_7, pwm1_7 enable 0x00 0x1d PWM_EN_B1 RW [7:0]: pwm_en8_15, pwm8_15 enable 0x00 0x1e PWM_EN_B2 RW [7:0]: pwm_en16_23, pwm16_23 enable 0x00 0x1f PWM_EN_B3 RW [7:0]: pwm_en0, pwm0 enable 0x00 0x20 PWM0_CFG_B0 RW [7:0]: tcmp_l, pwm tcmp[7:0] 0x00 0x21 PWM0_CFG_B1 RW [7:0]: tcmp_h, pwm tcmp[15:8] 0x00 0x22 PWM0_CFG_B2 RW [7:0]: tmax_l, pwm tmax[7:0] 0x00 0x23 PWM0_CFG_B3 RW [7:0]: tmax_h, pwm tmax[15:8] 0x00 0x24 PWM0_CFG_B4 RW [7:0]: phase_l, pwm phase[7:0] 0x00 0x25 PWM0_CFG_B5 RW [7:0]: phase_h, pwm phase[15:8] 0x00 0x26 PWM0_CFG_B6 RW [0]: resvd [1]: inv, invert PWM output [2]: pos, invert PWM_INV output [3]: pola, PWM pola [4]: mode32k, PWM_mode32k_o [5]: center_align, center align enable [6]: irq_cycdone_mask, mask irq_cycdone 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 406 Ver 0.8.0 0x27 PWM0_CFG_B7 RW [0]: sync_en, sync_en_o, sync_en_o ==1: enable deep Diming Synchronization sync_en_o ==0: disable deep Diming Synchronization [1]: sync_edge, sync_edge_o, sync_edge ==1: negative edge of pulse triggers synchronization sync_edge ==0: positive edge of pulse triggers synchronization [2]: phase_mode, phase_mode_o, phase_mode_o ==1: phase is in every cycle phase_mode_o ==0: phase is in first cycle 0x00 0x28 PWM0_CFG_B8 RW [4:0]: resol, extra resolution of PWM 0x00 0x29 PWM0_CFG_B9 RW [7:0]: dead_time, dead time value 0x00 0x2a PWM0_CNT_L R [7:0]: pwm_cnt_l, PWM cnt value[7:0] 0x00 0x2b PWM0_CNT_H R [7:0]: pwm_cnt_h, PWM cnt value[15:8] 0x00 0x30 PWM1_CFG_B0 RW [7:0]: tcmp_l, pwm tcmp[7:0] 0x00 0x31 PWM1_CFG_B1 RW [7:0]: tcmp_h, pwm tcmp[15:8] 0x00 0x32 PWM1_CFG_B2 RW [7:0]: tmax_l, pwm tmax[7:0] 0x00 0x33 PWM1_CFG_B3 RW [7:0]: tmax_h, pwm tmax[15:8] 0x00 0x34 PWM1_CFG_B4 RW [7:0]: phase_l, pwm phase[7:0] 0x00 0x35 PWM1_CFG_B5 RW [7:0]: phase_h, pwm phase[15:8] 0x00 0x36 PWM1_CFG_B6 RW [0]: resvd [1]: inv, invert PWM output [2]: pos, invert PWM_INV output [3]: pola, PWM pola [4]: mode32k, PWM_mode32k_o [5]: center_align, center align enable [6]: irq_cycdone_mask, mask irq_cycdone 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 407 Ver 0.8.0 0x37 PWM1_CFG_B7 RW [0]: sync_en, sync_en_o, sync_en_o ==1: enable deep Diming Synchronization sync_en_o ==0: disable deep Diming Synchronization [1]: sync_edge, sync_edge_o, sync_edge ==1: negative edge of pulse triggers synchronization sync_edge ==0: positive edge of pulse triggers synchronization [2]: phase_mode, phase_mode_o, phase_mode_o ==1: phase is in every cycle phase_mode_o ==0: phase is in first cycle 0x00 0x38 PWM1_CFG_B8 RW [4:0]: resol, extra resolution of PWM 0x00 0x39 PWM1_CFG_B9 RW [7:0]: dead_time, dead time value 0x00 0x3a PWM1_CNT_L R [7:0]: pwm_cnt_l, PWM cnt value[7:0] 0x00 0x3b PWM1_CNT_H R [7:0]: pwm_cnt_h, PWM cnt value[15:8] 0x00 0x40 PWM2_CFG_B0 RW [7:0]: tcmp_l, pwm tcmp[7:0] 0x00 0x41 PWM2_CFG_B1 RW [7:0]: tcmp_h, pwm tcmp[15:8] 0x00 0x42 PWM2_CFG_B2 RW [7:0]: tmax_l, pwm tmax[7:0] 0x00 0x43 PWM2_CFG_B3 RW [7:0]: tmax_h, pwm tmax[15:8] 0x00 0x44 PWM2_CFG_B4 RW [7:0]: phase_l, pwm phase[7:0] 0x00 0x45 PWM2_CFG_B5 RW [7:0]: phase_h, pwm phase[15:8] 0x00 0x46 PWM2_CFG_B6 RW [0]: resvd [1]: inv, invert PWM output [2]: pos, invert PWM_INV output [3]: pola, PWM pola [4]: mode32k, PWM_mode32k_o [5]: center_align, center align enable [6]: irq_cycdone_mask, mask irq_cycdone 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 408 Ver 0.8.0 0x47 PWM2_CFG_B7 RW [0]: sync_en, sync_en_o, sync_en_o ==1: enable deep Diming Synchronization sync_en_o ==0: disable deep Diming Synchronization [1]: sync_edge, sync_edge_o, sync_edge ==1: negative edge of pulse triggers synchronization sync_edge ==0: positive edge of pulse triggers synchronization [2]: phase_mode, phase_mode_o, phase_mode_o ==1: phase is in every cycle phase_mode_o ==0: phase is in first cycle 0x00 0x48 PWM2_CFG_B8 RW [4:0]: resol, extra resolution of PWM 0x00 0x49 PWM2_CFG_B9 RW [7:0]: dead_time, dead time value 0x00 0x4a PWM2_CNT_L R [7:0]: pwm_cnt_l, PWM cnt value[7:0] 0x00 0x4b PWM2_CNT_H R [7:0]: pwm_cnt_h, PWM cnt value[15:8] 0x00 0x50 PWM3_CFG_B0 RW [7:0]: tcmp_l, pwm tcmp[7:0] 0x00 0x51 PWM3_CFG_B1 RW [7:0]: tcmp_h, pwm tcmp[15:8] 0x00 0x52 PWM3_CFG_B2 RW [7:0]: tmax_l, pwm tmax[7:0] 0x00 0x53 PWM3_CFG_B3 RW [7:0]: tmax_h, pwm tmax[15:8] 0x00 0x54 PWM3_CFG_B4 RW [7:0]: phase_l, pwm phase[7:0] 0x00 0x55 PWM3_CFG_B5 RW [7:0]: phase_h, pwm phase[15:8] 0x00 0x56 PWM3_CFG_B6 RW [0]: resvd [1]: inv, invert PWM output [2]: pos, invert PWM_INV output [3]: pola, PWM pola [4]: mode32k, PWM_mode32k_o [5]: center_align, center align enable [6]: irq_cycdone_mask, mask irq_cycdone 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 409 Ver 0.8.0 0x57 PWM3_CFG_B7 RW [0]: sync_en, sync_en_o, sync_en_o ==1: enable deep Diming Synchronization sync_en_o ==0: disable deep Diming Synchronization [1]: sync_edge, sync_edge_o, sync_edge ==1: negative edge of pulse triggers synchronization sync_edge ==0: positive edge of pulse triggers synchronization [2]: phase_mode, phase_mode_o, phase_mode_o ==1: phase is in every cycle phase_mode_o ==0: phase is in first cycle 0x00 0x58 PWM3_CFG_B8 RW [4:0]: resol, extra resolution of PWM 0x00 0x59 PWM3_CFG_B9 RW [7:0]: dead_time, dead time value 0x00 0x5a PWM3_CNT_L R [7:0]: pwm_cnt_l, PWM cnt value[7:0] 0x00 0x5b PWM3_CNT_H R [7:0]: pwm_cnt_h, PWM cnt value[15:8] 0x00 0x60 PWM4_CFG_B0 RW [7:0]: tcmp_l, pwm tcmp[7:0] 0x00 0x61 PWM4_CFG_B1 RW [7:0]: tcmp_h, pwm tcmp[15:8] 0x00 0x62 PWM4_CFG_B2 RW [7:0]: tmax_l, pwm tmax[7:0] 0x00 0x63 PWM4_CFG_B3 RW [7:0]: tmax_h, pwm tmax[15:8] 0x00 0x64 PWM4_CFG_B4 RW [7:0]: phase_l, pwm phase[7:0] 0x00 0x65 PWM4_CFG_B5 RW [7:0]: phase_h, pwm phase[15:8] 0x00 0x66 PWM4_CFG_B6 RW [0]: resvd [1]: inv, invert PWM output [2]: pos, invert PWM_INV output [3]: pola, PWM pola [4]: mode32k, PWM_mode32k_o [5]: center_align, center align enable [6]: irq_cycdone_mask, mask irq_cycdone 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 410 Ver 0.8.0 0x67 PWM4_CFG_B7 RW [0]: sync_en, sync_en_o, sync_en_o ==1: enable deep Diming Synchronization sync_en_o ==0: disable deep Diming Synchronization [1]: sync_edge, sync_edge_o, sync_edge ==1: negative edge of pulse triggers synchronization sync_edge ==0: positive edge of pulse triggers synchronization [2]: phase_mode, phase_mode_o, phase_mode_o ==1: phase is in every cycle phase_mode_o ==0: phase is in first cycle 0x00 0x68 PWM4_CFG_B8 RW [4:0]: resol, extra resolution of PWM 0x00 0x69 PWM4_CFG_B9 RW [7:0]: dead_time, dead time value 0x00 0x6a PWM4_CNT_L R [7:0]: pwm_cnt_l, PWM cnt value[7:0] 0x00 0x6b PWM4_CNT_H R [7:0]: pwm_cnt_h, PWM cnt value[15:8] 0x00 0x70 PWM5_CFG_B0 RW [7:0]: tcmp_l, pwm tcmp[7:0] 0x00 0x71 PWM5_CFG_B1 RW [7:0]: tcmp_h, pwm tcmp[15:8] 0x00 0x72 PWM5_CFG_B2 RW [7:0]: tmax_l, pwm tmax[7:0] 0x00 0x73 PWM5_CFG_B3 RW [7:0]: tmax_h, pwm tmax[15:8] 0x00 0x74 PWM5_CFG_B4 RW [7:0]: phase_l, pwm phase[7:0] 0x00 0x75 PWM5_CFG_B5 RW [7:0]: phase_h, pwm phase[15:8] 0x00 0x76 PWM5_CFG_B6 RW [0]: resvd [1]: inv, invert PWM output [2]: pos, invert PWM_INV output [3]: pola, PWM pola [4]: mode32k, PWM_mode32k_o [5]: center_align, center align enable [6]: irq_cycdone_mask, mask irq_cycdone 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 411 Ver 0.8.0 0x77 PWM5_CFG_B7 RW [0]: sync_en, sync_en_o, sync_en_o ==1: enable deep Diming Synchronization sync_en_o ==0: disable deep Diming Synchronization [1]: sync_edge, sync_edge_o, sync_edge ==1: negative edge of pulse triggers synchronization sync_edge ==0: positive edge of pulse triggers synchronization [2]: phase_mode, phase_mode_o, phase_mode_o ==1: phase is in every cycle phase_mode_o ==0: phase is in first cycle 0x00 0x78 PWM5_CFG_B8 RW [4:0]: resol, extra resolution of PWM 0x00 0x79 PWM5_CFG_B9 RW [7:0]: dead_time, dead time value 0x00 0x7a PWM5_CNT_L R [7:0]: pwm_cnt_l, PWM cnt value[7:0] 0x00 0x7b PWM5_CNT_H R [7:0]: pwm_cnt_h, PWM cnt value[15:8] 0x00 0x80 PWM6_CFG_B0 RW [7:0]: tcmp_l, pwm tcmp[7:0] 0x00 0x81 PWM6_CFG_B1 RW [7:0]: tcmp_h, pwm tcmp[15:8] 0x00 0x82 PWM6_CFG_B2 RW [7:0]: tmax_l, pwm tmax[7:0] 0x00 0x83 PWM6_CFG_B3 RW [7:0]: tmax_h, pwm tmax[15:8] 0x00 0x84 PWM6_CFG_B4 RW [7:0]: phase_l, pwm phase[7:0] 0x00 0x85 PWM6_CFG_B5 RW [7:0]: phase_h, pwm phase[15:8] 0x00 0x86 PWM6_CFG_B6 RW [0]: resvd [1]: inv, invert PWM output [2]: pos, invert PWM_INV output [3]: pola, PWM pola [4]: mode32k, PWM_mode32k_o [5]: center_align, center align enable [6]: irq_cycdone_mask, mask irq_cycdone 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 412 Ver 0.8.0 0x87 PWM6_CFG_B7 RW [0]: sync_en, sync_en_o, sync_en_o ==1: enable deep Diming Synchronization sync_en_o ==0: disable deep Diming Synchronization [1]: sync_edge, sync_edge_o, sync_edge ==1: negative edge of pulse triggers synchronization sync_edge ==0: positive edge of pulse triggers synchronization [2]: phase_mode, phase_mode_o, phase_mode_o ==1: phase is in every cycle phase_mode_o ==0: phase is in first cycle 0x00 0x88 PWM6_CFG_B8 RW [4:0]: resol, extra resolution of PWM 0x00 0x89 PWM6_CFG_B9 RW [7:0]: dead_time, dead time value 0x00 0x8a PWM6_CNT_L R [7:0]: pwm_cnt_l, PWM cnt value[7:0] 0x00 0x8b PWM6_CNT_H R [7:0]: pwm_cnt_h, PWM cnt value[15:8] 0x00 0x90 PWM7_CFG_B0 RW [7:0]: tcmp_l, pwm tcmp[7:0] 0x00 0x91 PWM7_CFG_B1 RW [7:0]: tcmp_h, pwm tcmp[15:8] 0x00 0x92 PWM7_CFG_B2 RW [7:0]: tmax_l, pwm tmax[7:0] 0x00 0x93 PWM7_CFG_B3 RW [7:0]: tmax_h, pwm tmax[15:8] 0x00 0x94 PWM7_CFG_B4 RW [7:0]: phase_l, pwm phase[7:0] 0x00 0x95 PWM7_CFG_B5 RW [7:0]: phase_h, pwm phase[15:8] 0x00 0x96 PWM7_CFG_B6 RW [0]: resvd [1]: inv, invert PWM output [2]: pos, invert PWM_INV output [3]: pola, PWM pola [4]: mode32k, PWM_mode32k_o [5]: center_align, center align enable [6]: irq_cycdone_mask, mask irq_cycdone 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 413 Ver 0.8.0 0x97 PWM7_CFG_B7 RW [0]: sync_en, sync_en_o, sync_en_o ==1: enable deep Diming Synchronization sync_en_o ==0: disable deep Diming Synchronization [1]: sync_edge, sync_edge_o, sync_edge ==1: negative edge of pulse triggers synchronization sync_edge ==0: positive edge of pulse triggers synchronization [2]: phase_mode, phase_mode_o, phase_mode_o ==1: phase is in every cycle phase_mode_o ==0: phase is in first cycle 0x00 0x98 PWM7_CFG_B8 RW [4:0]: resol, extra resolution of PWM 0x00 0x99 PWM7_CFG_B9 RW [7:0]: dead_time, dead time value 0x00 0x9a PWM7_CNT_L R [7:0]: pwm_cnt_l, PWM cnt value[7:0] 0x00 0x9b PWM7_CNT_H R [7:0]: pwm_cnt_h, PWM cnt value[15:8] 0x00 0xa0 PWM8_CFG_B0 RW [7:0]: tcmp_l, pwm tcmp[7:0] 0x00 0xa1 PWM8_CFG_B1 RW [7:0]: tcmp_h, pwm tcmp[15:8] 0x00 0xa2 PWM8_CFG_B2 RW [7:0]: tmax_l, pwm tmax[7:0] 0x00 0xa3 PWM8_CFG_B3 RW [7:0]: tmax_h, pwm tmax[15:8] 0x00 0xa4 PWM8_CFG_B4 RW [7:0]: phase_l, pwm phase[7:0] 0x00 0xa5 PWM8_CFG_B5 RW [7:0]: phase_h, pwm phase[15:8] 0x00 0xa6 PWM8_CFG_B6 RW [0]: resvd [1]: inv, invert PWM output [2]: pos, invert PWM_INV output [3]: pola, PWM pola [4]: mode32k, PWM_mode32k_o [5]: center_align, center align enable [6]: irq_cycdone_mask, mask irq_cycdone 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 414 Ver 0.8.0 0xa7 PWM8_CFG_B7 RW [0]: sync_en, sync_en_o, sync_en_o ==1: enable deep Diming Synchronization sync_en_o ==0: disable deep Diming Synchronization [1]: sync_edge, sync_edge_o, sync_edge ==1: negative edge of pulse triggers synchronization sync_edge ==0: positive edge of pulse triggers synchronization [2]: phase_mode, phase_mode_o, phase_mode_o ==1: phase is in every cycle phase_mode_o ==0: phase is in first cycle 0x00 0xa8 PWM8_CFG_B8 RW [4:0]: resol, extra resolution of PWM 0x00 0xa9 PWM8_CFG_B9 RW [7:0]: dead_time, dead time value 0x00 0xaa PWM8_CNT_L R [7:0]: pwm_cnt_l, PWM cnt value[7:0] 0x00 0xab PWM8_CNT_H R [7:0]: pwm_cnt_h, PWM cnt value[15:8] 0x00 0xb0 PWM9_CFG_B0 RW [7:0]: tcmp_l, pwm tcmp[7:0] 0x00 0xb1 PWM9_CFG_B1 RW [7:0]: tcmp_h, pwm tcmp[15:8] 0x00 0xb2 PWM9_CFG_B2 RW [7:0]: tmax_l, pwm tmax[7:0] 0x00 0xb3 PWM9_CFG_B3 RW [7:0]: tmax_h, pwm tmax[15:8] 0x00 0xb4 PWM9_CFG_B4 RW [7:0]: phase_l, pwm phase[7:0] 0x00 0xb5 PWM9_CFG_B5 RW [7:0]: phase_h, pwm phase[15:8] 0x00 0xb6 PWM9_CFG_B6 RW [0]: resvd [1]: inv, invert PWM output [2]: pos, invert PWM_INV output [3]: pola, PWM pola [4]: mode32k, PWM_mode32k_o [5]: center_align, center align enable [6]: irq_cycdone_mask, mask irq_cycdone 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 415 Ver 0.8.0 0xb7 PWM9_CFG_B7 RW [0]: sync_en, sync_en_o, sync_en_o ==1: enable deep Diming Synchronization sync_en_o ==0: disable deep Diming Synchronization [1]: sync_edge, sync_edge_o, sync_edge ==1: negative edge of pulse triggers synchronization sync_edge ==0: positive edge of pulse triggers synchronization [2]: phase_mode, phase_mode_o, phase_mode_o ==1: phase is in every cycle phase_mode_o ==0: phase is in first cycle 0x00 0xb8 PWM9_CFG_B8 RW [4:0]: resol, extra resolution of PWM 0x00 0xb9 PWM9_CFG_B9 RW [7:0]: dead_time, dead time value 0x00 0xba PWM9_CNT_L R [7:0]: pwm_cnt_l, PWM cnt value[7:0] 0x00 0xbb PWM9_CNT_H R [7:0]: pwm_cnt_h, PWM cnt value[15:8] 0x00 0xc0 PWM10_CFG_B0 RW [7:0]: tcmp_l, pwm tcmp[7:0] 0x00 0xc1 PWM10_CFG_B1 RW [7:0]: tcmp_h, pwm tcmp[15:8] 0x00 0xc2 PWM10_CFG_B2 RW [7:0]: tmax_l, pwm tmax[7:0] 0x00 0xc3 PWM10_CFG_B3 RW [7:0]: tmax_h, pwm tmax[15:8] 0x00 0xc4 PWM10_CFG_B4 RW [7:0]: phase_l, pwm phase[7:0] 0x00 0xc5 PWM10_CFG_B5 RW [7:0]: phase_h, pwm phase[15:8] 0x00 0xc6 PWM10_CFG_B6 RW [0]: resvd [1]: inv, invert PWM output [2]: pos, invert PWM_INV output [3]: pola, PWM pola [4]: mode32k, PWM_mode32k_o [5]: center_align, center align enable [6]: irq_cycdone_mask, mask irq_cycdone 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 416 Ver 0.8.0 0xc7 PWM10_CFG_B7 RW [0]: sync_en, sync_en_o, sync_en_o ==1: enable deep Diming Synchronization sync_en_o ==0: disable deep Diming Synchronization [1]: sync_edge, sync_edge_o, sync_edge ==1: negative edge of pulse triggers synchronization sync_edge ==0: positive edge of pulse triggers synchronization [2]: phase_mode, phase_mode_o, phase_mode_o ==1: phase is in every cycle phase_mode_o ==0: phase is in first cycle 0x00 0xc8 PWM10_CFG_B8 RW [4:0]: resol, extra resolution of PWM 0x00 0xc9 PWM10_CFG_B9 RW [7:0]: dead_time, dead time value 0x00 0xca PWM10_CNT_L R [7:0]: pwm_cnt_l, PWM cnt value[7:0] 0x00 0xcb PWM10_CNT_H R [7:0]: pwm_cnt_h, PWM cnt value[15:8] 0x00 0xd0 PWM11_CFG_B0 RW [7:0]: tcmp_l, pwm tcmp[7:0] 0x00 0xd1 PWM11_CFG_B1 RW [7:0]: tcmp_h, pwm tcmp[15:8] 0x00 0xd2 PWM11_CFG_B2 RW [7:0]: tmax_l, pwm tmax[7:0] 0x00 0xd3 PWM11_CFG_B3 RW [7:0]: tmax_h, pwm tmax[15:8] 0x00 0xd4 PWM11_CFG_B4 RW [7:0]: phase_l, pwm phase[7:0] 0x00 0xd5 PWM11_CFG_B5 RW [7:0]: phase_h, pwm phase[15:8] 0x00 0xd6 PWM11_CFG_B6 RW [0]: resvd [1]: inv, invert PWM output [2]: pos, invert PWM_INV output [3]: pola, PWM pola [4]: mode32k, PWM_mode32k_o [5]: center_align, center align enable [6]: irq_cycdone_mask, mask irq_cycdone 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 417 Ver 0.8.0 0xd7 PWM11_CFG_B7 RW [0]: sync_en, sync_en_o, sync_en_o ==1: enable deep Diming Synchronization sync_en_o ==0: disable deep Diming Synchronization [1]: sync_edge, sync_edge_o, sync_edge ==1: negative edge of pulse triggers synchronization sync_edge ==0: positive edge of pulse triggers synchronization [2]: phase_mode, phase_mode_o, phase_mode_o ==1: phase is in every cycle phase_mode_o ==0: phase is in first cycle 0x00 0xd8 PWM11_CFG_B8 RW [4:0]: resol, extra resolution of PWM 0x00 0xd9 PWM11_CFG_B9 RW [7:0]: dead_time, dead time value 0x00 0xda PWM11_CNT_L R [7:0]: pwm_cnt_l, PWM cnt value[7:0] 0x00 0xdb PWM11_CNT_H R [7:0]: pwm_cnt_h, PWM cnt value[15:8] 0x00 0xe0 PWM12_CFG_B0 RW [7:0]: tcmp_l, pwm tcmp[7:0] 0x00 0xe1 PWM12_CFG_B1 RW [7:0]: tcmp_h, pwm tcmp[15:8] 0x00 0xe2 PWM12_CFG_B2 RW [7:0]: tmax_l, pwm tmax[7:0] 0x00 0xe3 PWM12_CFG_B3 RW [7:0]: tmax_h, pwm tmax[15:8] 0x00 0xe4 PWM12_CFG_B4 RW [7:0]: phase_l, pwm phase[7:0] 0x00 0xe5 PWM12_CFG_B5 RW [7:0]: phase_h, pwm phase[15:8] 0x00 0xe6 PWM12_CFG_B6 RW [0]: resvd [1]: inv, invert PWM output [2]: pos, invert PWM_INV output [3]: pola, PWM pola [4]: mode32k, PWM_mode32k_o [5]: center_align, center align enable [6]: irq_cycdone_mask, mask irq_cycdone 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 418 Ver 0.8.0 0xe7 PWM12_CFG_B7 RW [0]: sync_en, sync_en_o, sync_en_o ==1: enable deep Diming Synchronization sync_en_o ==0: disable deep Diming Synchronization [1]: sync_edge, sync_edge_o, sync_edge ==1: negative edge of pulse triggers synchronization sync_edge ==0: positive edge of pulse triggers synchronization [2]: phase_mode, phase_mode_o, phase_mode_o ==1: phase is in every cycle phase_mode_o ==0: phase is in first cycle 0x00 0xe8 PWM12_CFG_B8 RW [4:0]: resol, extra resolution of PWM 0x00 0xe9 PWM12_CFG_B9 RW [7:0]: dead_time, dead time value 0x00 0xea PWM12_CNT_L R [7:0]: pwm_cnt_l, PWM cnt value[7:0] 0x00 0xeb PWM12_CNT_H R [7:0]: pwm_cnt_h, PWM cnt value[15:8] 0x00 0xf0 PWM13_CFG_B0 RW [7:0]: tcmp_l, pwm tcmp[7:0] 0x00 0xf1 PWM13_CFG_B1 RW [7:0]: tcmp_h, pwm tcmp[15:8] 0x00 0xf2 PWM13_CFG_B2 RW [7:0]: tmax_l, pwm tmax[7:0] 0x00 0xf3 PWM13_CFG_B3 RW [7:0]: tmax_h, pwm tmax[15:8] 0x00 0xf4 PWM13_CFG_B4 RW [7:0]: phase_l, pwm phase[7:0] 0x00 0xf5 PWM13_CFG_B5 RW [7:0]: phase_h, pwm phase[15:8] 0x00 0xf6 PWM13_CFG_B6 RW [0]: resvd [1]: inv, invert PWM output [2]: pos, invert PWM_INV output [3]: pola, PWM pola [4]: mode32k, PWM_mode32k_o [5]: center_align, center align enable [6]: irq_cycdone_mask, mask irq_cycdone 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 419 Ver 0.8.0 0xf7 PWM13_CFG_B7 RW [0]: sync_en, sync_en_o, sync_en_o ==1: enable deep Diming Synchronization sync_en_o ==0: disable deep Diming Synchronization [1]: sync_edge, sync_edge_o, sync_edge ==1: negative edge of pulse triggers synchronization sync_edge ==0: positive edge of pulse triggers synchronization [2]: phase_mode, phase_mode_o, phase_mode_o ==1: phase is in every cycle phase_mode_o ==0: phase is in first cycle 0x00 0xf8 PWM13_CFG_B8 RW [4:0]: resol, extra resolution of PWM 0x00 0xf9 PWM13_CFG_B9 RW [7:0]: dead_time, dead time value 0x00 0xfa PWM13_CNT_L R [7:0]: pwm_cnt_l, PWM cnt value[7:0] 0x00 0xfb PWM13_CNT_H R [7:0]: pwm_cnt_h, PWM cnt value[15:8] 0x00 0x100 PWM14_CFG_B0 RW [7:0]: tcmp_l, pwm tcmp[7:0] 0x00 0x101 PWM14_CFG_B1 RW [7:0]: tcmp_h, pwm tcmp[15:8] 0x00 0x102 PWM14_CFG_B2 RW [7:0]: tmax_l, pwm tmax[7:0] 0x00 0x103 PWM14_CFG_B3 RW [7:0]: tmax_h, pwm tmax[15:8] 0x00 0x104 PWM14_CFG_B4 RW [7:0]: phase_l, pwm phase[7:0] 0x00 0x105 PWM14_CFG_B5 RW [7:0]: phase_h, pwm phase[15:8] 0x00 0x106 PWM14_CFG_B6 RW [0]: resvd [1]: inv, invert PWM output [2]: pos, invert PWM_INV output [3]: pola, PWM pola [4]: mode32k, PWM_mode32k_o [5]: center_align, center align enable [6]: irq_cycdone_mask, mask irq_cycdone 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 420 Ver 0.8.0 0x107 PWM14_CFG_B7 RW [0]: sync_en, sync_en_o, sync_en_o ==1: enable deep Diming Synchronization sync_en_o ==0: disable deep Diming Synchronization [1]: sync_edge, sync_edge_o, sync_edge ==1: negative edge of pulse triggers synchronization sync_edge ==0: positive edge of pulse triggers synchronization [2]: phase_mode, phase_mode_o, phase_mode_o ==1: phase is in every cycle phase_mode_o ==0: phase is in first cycle 0x00 0x108 PWM14_CFG_B8 RW [4:0]: resol, extra resolution of PWM 0x00 0x109 PWM14_CFG_B9 RW [7:0]: dead_time, dead time value 0x00 0x10a PWM14_CNT_L R [7:0]: pwm_cnt_l, PWM cnt value[7:0] 0x00 0x10b PWM14_CNT_H R [7:0]: pwm_cnt_h, PWM cnt value[15:8] 0x00 0x110 PWM15_CFG_B0 RW [7:0]: tcmp_l, pwm tcmp[7:0] 0x00 0x111 PWM15_CFG_B1 RW [7:0]: tcmp_h, pwm tcmp[15:8] 0x00 0x112 PWM15_CFG_B2 RW [7:0]: tmax_l, pwm tmax[7:0] 0x00 0x113 PWM15_CFG_B3 RW [7:0]: tmax_h, pwm tmax[15:8] 0x00 0x114 PWM15_CFG_B4 RW [7:0]: phase_l, pwm phase[7:0] 0x00 0x115 PWM15_CFG_B5 RW [7:0]: phase_h, pwm phase[15:8] 0x00 0x116 PWM15_CFG_B6 RW [0]: resvd [1]: inv, invert PWM output [2]: pos, invert PWM_INV output [3]: pola, PWM pola [4]: mode32k, PWM_mode32k_o [5]: center_align, center align enable [6]: irq_cycdone_mask, mask irq_cycdone 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 421 Ver 0.8.0 0x117 PWM15_CFG_B7 RW [0]: sync_en, sync_en_o, sync_en_o ==1: enable deep Diming Synchronization sync_en_o ==0: disable deep Diming Synchronization [1]: sync_edge, sync_edge_o, sync_edge ==1: negative edge of pulse triggers synchronization sync_edge ==0: positive edge of pulse triggers synchronization [2]: phase_mode, phase_mode_o, phase_mode_o ==1: phase is in every cycle phase_mode_o ==0: phase is in first cycle 0x00 0x118 PWM15_CFG_B8 RW [4:0]: resol, extra resolution of PWM 0x00 0x119 PWM15_CFG_B9 RW [7:0]: dead_time, dead time value 0x00 0x11a PWM15_CNT_L R [7:0]: pwm_cnt_l, PWM cnt value[7:0] 0x00 0x11b PWM15_CNT_H R [7:0]: pwm_cnt_h, PWM cnt value[15:8] 0x00 0x120 PWM16_CFG_B0 RW [7:0]: tcmp_l, pwm tcmp[7:0] 0x00 0x121 PWM16_CFG_B1 RW [7:0]: tcmp_h, pwm tcmp[15:8] 0x00 0x122 PWM16_CFG_B2 RW [7:0]: tmax_l, pwm tmax[7:0] 0x00 0x123 PWM16_CFG_B3 RW [7:0]: tmax_h, pwm tmax[15:8] 0x00 0x124 PWM16_CFG_B4 RW [7:0]: phase_l, pwm phase[7:0] 0x00 0x125 PWM16_CFG_B5 RW [7:0]: phase_h, pwm phase[15:8] 0x00 0x126 PWM16_CFG_B6 RW [0]: resvd [1]: inv, invert PWM output [2]: pos, invert PWM_INV output [3]: pola, PWM pola [4]: mode32k, PWM_mode32k_o [5]: center_align, center align enable [6]: irq_cycdone_mask, mask irq_cycdone 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 422 Ver 0.8.0 0x127 PWM16_CFG_B7 RW [0]: sync_en, sync_en_o, sync_en_o ==1: enable deep Diming Synchronization sync_en_o ==0: disable deep Diming Synchronization [1]: sync_edge, sync_edge_o, sync_edge ==1: negative edge of pulse triggers synchronization sync_edge ==0: positive edge of pulse triggers synchronization [2]: phase_mode, phase_mode_o, phase_mode_o ==1: phase is in every cycle phase_mode_o ==0: phase is in first cycle 0x00 0x128 PWM16_CFG_B8 RW [4:0]: resol, extra resolution of PWM 0x00 0x129 PWM16_CFG_B9 RW [7:0]: dead_time, dead time value 0x00 0x12a PWM16_CNT_L R [7:0]: pwm_cnt_l, PWM cnt value[7:0] 0x00 0x12b PWM16_CNT_H R [7:0]: pwm_cnt_h, PWM cnt value[15:8] 0x00 0x130 PWM17_CFG_B0 RW [7:0]: tcmp_l, pwm tcmp[7:0] 0x00 0x131 PWM17_CFG_B1 RW [7:0]: tcmp_h, pwm tcmp[15:8] 0x00 0x132 PWM17_CFG_B2 RW [7:0]: tmax_l, pwm tmax[7:0] 0x00 0x133 PWM17_CFG_B3 RW [7:0]: tmax_h, pwm tmax[15:8] 0x00 0x134 PWM17_CFG_B4 RW [7:0]: phase_l, pwm phase[7:0] 0x00 0x135 PWM17_CFG_B5 RW [7:0]: phase_h, pwm phase[15:8] 0x00 0x136 PWM17_CFG_B6 RW [0]: resvd [1]: inv, invert PWM output [2]: pos, invert PWM_INV output [3]: pola, PWM pola [4]: mode32k, PWM_mode32k_o [5]: center_align, center align enable [6]: irq_cycdone_mask, mask irq_cycdone 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 423 Ver 0.8.0 0x137 PWM17_CFG_B7 RW [0]: sync_en, sync_en_o, sync_en_o ==1: enable deep Diming Synchronization sync_en_o ==0: disable deep Diming Synchronization [1]: sync_edge, sync_edge_o, sync_edge ==1: negative edge of pulse triggers synchronization sync_edge ==0: positive edge of pulse triggers synchronization [2]: phase_mode, phase_mode_o, phase_mode_o ==1: phase is in every cycle phase_mode_o ==0: phase is in first cycle 0x00 0x138 PWM17_CFG_B8 RW [4:0]: resol, extra resolution of PWM 0x00 0x139 PWM17_CFG_B9 RW [7:0]: dead_time, dead time value 0x00 0x13a PWM17_CNT_L R [7:0]: pwm_cnt_l, PWM cnt value[7:0] 0x00 0x13b PWM17_CNT_H R [7:0]: pwm_cnt_h, PWM cnt value[15:8] 0x00 0x140 PWM18_CFG_B0 RW [7:0]: tcmp_l, pwm tcmp[7:0] 0x00 0x141 PWM18_CFG_B1 RW [7:0]: tcmp_h, pwm tcmp[15:8] 0x00 0x142 PWM18_CFG_B2 RW [7:0]: tmax_l, pwm tmax[7:0] 0x00 0x143 PWM18_CFG_B3 RW [7:0]: tmax_h, pwm tmax[15:8] 0x00 0x144 PWM18_CFG_B4 RW [7:0]: phase_l, pwm phase[7:0] 0x00 0x145 PWM18_CFG_B5 RW [7:0]: phase_h, pwm phase[15:8] 0x00 0x146 PWM18_CFG_B6 RW [0]: resvd [1]: inv, invert PWM output [2]: pos, invert PWM_INV output [3]: pola, PWM pola [4]: mode32k, PWM_mode32k_o [5]: center_align, center align enable [6]: irq_cycdone_mask, mask irq_cycdone 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 424 Ver 0.8.0 0x147 PWM18_CFG_B7 RW [0]: sync_en, sync_en_o, sync_en_o ==1: enable deep Diming Synchronization sync_en_o ==0: disable deep Diming Synchronization [1]: sync_edge, sync_edge_o, sync_edge ==1: negative edge of pulse triggers synchronization sync_edge ==0: positive edge of pulse triggers synchronization [2]: phase_mode, phase_mode_o, phase_mode_o ==1: phase is in every cycle phase_mode_o ==0: phase is in first cycle 0x00 0x148 PWM18_CFG_B8 RW [4:0]: resol, extra resolution of PWM 0x00 0x149 PWM18_CFG_B9 RW [7:0]: dead_time, dead time value 0x00 0x14a PWM18_CNT_L R [7:0]: pwm_cnt_l, PWM cnt value[7:0] 0x00 0x14b PWM18_CNT_H R [7:0]: pwm_cnt_h, PWM cnt value[15:8] 0x00 0x150 PWM19_CFG_B0 RW [7:0]: tcmp_l, pwm tcmp[7:0] 0x00 0x151 PWM19_CFG_B1 RW [7:0]: tcmp_h, pwm tcmp[15:8] 0x00 0x152 PWM19_CFG_B2 RW [7:0]: tmax_l, pwm tmax[7:0] 0x00 0x153 PWM19_CFG_B3 RW [7:0]: tmax_h, pwm tmax[15:8] 0x00 0x154 PWM19_CFG_B4 RW [7:0]: phase_l, pwm phase[7:0] 0x00 0x155 PWM19_CFG_B5 RW [7:0]: phase_h, pwm phase[15:8] 0x00 0x156 PWM19_CFG_B6 RW [0]: resvd [1]: inv, invert PWM output [2]: pos, invert PWM_INV output [3]: pola, PWM pola [4]: mode32k, PWM_mode32k_o [5]: center_align, center align enable [6]: irq_cycdone_mask, mask irq_cycdone 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 425 Ver 0.8.0 0x157 PWM19_CFG_B7 RW [0]: sync_en, sync_en_o, sync_en_o ==1: enable deep Diming Synchronization sync_en_o ==0: disable deep Diming Synchronization [1]: sync_edge, sync_edge_o, sync_edge ==1: negative edge of pulse triggers synchronization sync_edge ==0: positive edge of pulse triggers synchronization [2]: phase_mode, phase_mode_o, phase_mode_o ==1: phase is in every cycle phase_mode_o ==0: phase is in first cycle 0x00 0x158 PWM19_CFG_B8 RW [4:0]: resol, extra resolution of PWM 0x00 0x159 PWM19_CFG_B9 RW [7:0]: dead_time, dead time value 0x00 0x15a PWM19_CNT_L R [7:0]: pwm_cnt_l, PWM cnt value[7:0] 0x00 0x15b PWM19_CNT_H R [7:0]: pwm_cnt_h, PWM cnt value[15:8] 0x00 0x160 PWM20_CFG_B0 RW [7:0]: tcmp_l, pwm tcmp[7:0] 0x00 0x161 PWM20_CFG_B1 RW [7:0]: tcmp_h, pwm tcmp[15:8] 0x00 0x162 PWM20_CFG_B2 RW [7:0]: tmax_l, pwm tmax[7:0] 0x00 0x163 PWM20_CFG_B3 RW [7:0]: tmax_h, pwm tmax[15:8] 0x00 0x164 PWM20_CFG_B4 RW [7:0]: phase_l, pwm phase[7:0] 0x00 0x165 PWM20_CFG_B5 RW [7:0]: phase_h, pwm phase[15:8] 0x00 0x166 PWM20_CFG_B6 RW [0]: resvd [1]: inv, invert PWM output [2]: pos, invert PWM_INV output [3]: pola, PWM pola [4]: mode32k, PWM_mode32k_o [5]: center_align, center align enable [6]: irq_cycdone_mask, mask irq_cycdone 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 426 Ver 0.8.0 0x167 PWM20_CFG_B7 RW [0]: sync_en, sync_en_o, sync_en_o ==1: enable deep Diming Synchronization sync_en_o ==0: disable deep Diming Synchronization [1]: sync_edge, sync_edge_o, sync_edge ==1: negative edge of pulse triggers synchronization sync_edge ==0: positive edge of pulse triggers synchronization [2]: phase_mode, phase_mode_o, phase_mode_o ==1: phase is in every cycle phase_mode_o ==0: phase is in first cycle 0x00 0x168 PWM20_CFG_B8 RW [4:0]: resol, extra resolution of PWM 0x00 0x169 PWM20_CFG_B9 RW [7:0]: dead_time, dead time value 0x00 0x16a PWM20_CNT_L R [7:0]: pwm_cnt_l, PWM cnt value[7:0] 0x00 0x16b PWM20_CNT_H R [7:0]: pwm_cnt_h, PWM cnt value[15:8] 0x00 0x170 PWM21_CFG_B0 RW [7:0]: tcmp_l, pwm tcmp[7:0] 0x00 0x171 PWM21_CFG_B1 RW [7:0]: tcmp_h, pwm tcmp[15:8] 0x00 0x172 PWM21_CFG_B2 RW [7:0]: tmax_l, pwm tmax[7:0] 0x00 0x173 PWM21_CFG_B3 RW [7:0]: tmax_h, pwm tmax[15:8] 0x00 0x174 PWM21_CFG_B4 RW [7:0]: phase_l, pwm phase[7:0] 0x00 0x175 PWM21_CFG_B5 RW [7:0]: phase_h, pwm phase[15:8] 0x00 0x176 PWM21_CFG_B6 RW [0]: resvd [1]: inv, invert PWM output [2]: pos, invert PWM_INV output [3]: pola, PWM pola [4]: mode32k, PWM_mode32k_o [5]: center_align, center align enable [6]: irq_cycdone_mask, mask irq_cycdone 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 427 Ver 0.8.0 0x177 PWM21_CFG_B7 RW [0]: sync_en, sync_en_o, sync_en_o ==1: enable deep Diming Synchronization sync_en_o ==0: disable deep Diming Synchronization [1]: sync_edge, sync_edge_o, sync_edge ==1: negative edge of pulse triggers synchronization sync_edge ==0: positive edge of pulse triggers synchronization [2]: phase_mode, phase_mode_o, phase_mode_o ==1: phase is in every cycle phase_mode_o ==0: phase is in first cycle 0x00 0x178 PWM21_CFG_B8 RW [4:0]: resol, extra resolution of PWM 0x00 0x179 PWM21_CFG_B9 RW [7:0]: dead_time, dead time value 0x00 0x17a PWM21_CNT_L R [7:0]: pwm_cnt_l, PWM cnt value[7:0] 0x00 0x17b PWM21_CNT_H R [7:0]: pwm_cnt_h, PWM cnt value[15:8] 0x00 0x180 PWM22_CFG_B0 RW [7:0]: tcmp_l, pwm tcmp[7:0] 0x00 0x181 PWM22_CFG_B1 RW [7:0]: tcmp_h, pwm tcmp[15:8] 0x00 0x182 PWM22_CFG_B2 RW [7:0]: tmax_l, pwm tmax[7:0] 0x00 0x183 PWM22_CFG_B3 RW [7:0]: tmax_h, pwm tmax[15:8] 0x00 0x184 PWM22_CFG_B4 RW [7:0]: phase_l, pwm phase[7:0] 0x00 0x185 PWM22_CFG_B5 RW [7:0]: phase_h, pwm phase[15:8] 0x00 0x186 PWM22_CFG_B6 RW [0]: resvd [1]: inv, invert PWM output [2]: pos, invert PWM_INV output [3]: pola, PWM pola [4]: mode32k, PWM_mode32k_o [5]: center_align, center align enable [6]: irq_cycdone_mask, mask irq_cycdone 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 428 Ver 0.8.0 0x187 PWM22_CFG_B7 RW [0]: sync_en, sync_en_o, sync_en_o ==1: enable deep Diming Synchronization sync_en_o ==0: disable deep Diming Synchronization [1]: sync_edge, sync_edge_o, sync_edge ==1: negative edge of pulse triggers synchronization sync_edge ==0: positive edge of pulse triggers synchronization [2]: phase_mode, phase_mode_o, phase_mode_o ==1: phase is in every cycle phase_mode_o ==0: phase is in first cycle 0x00 0x188 PWM22_CFG_B8 RW [4:0]: resol, extra resolution of PWM 0x00 0x189 PWM22_CFG_B9 RW [7:0]: dead_time, dead time value 0x00 0x18a PWM22_CNT_L R [7:0]: pwm_cnt_l, PWM cnt value[7:0] 0x00 0x18b PWM22_CNT_H R [7:0]: pwm_cnt_h, PWM cnt value[15:8] 0x00 0x190 PWM23_CFG_B0 RW [7:0]: tcmp_l, pwm tcmp[7:0] 0x00 0x191 PWM23_CFG_B1 RW [7:0]: tcmp_h, pwm tcmp[15:8] 0x00 0x192 PWM23_CFG_B2 RW [7:0]: tmax_l, pwm tmax[7:0] 0x00 0x193 PWM23_CFG_B3 RW [7:0]: tmax_h, pwm tmax[15:8] 0x00 0x194 PWM23_CFG_B4 RW [7:0]: phase_l, pwm phase[7:0] 0x00 0x195 PWM23_CFG_B5 RW [7:0]: phase_h, pwm phase[15:8] 0x00 0x196 PWM23_CFG_B6 RW [0]: resvd [1]: inv, invert PWM output [2]: pos, invert PWM_INV output [3]: pola, PWM pola [4]: mode32k, PWM_mode32k_o [5]: center_align, center align enable [6]: irq_cycdone_mask, mask irq_cycdone 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 429 Ver 0.8.0

11.13 Controller Area Network (CAN)

11.13.1 Introduction

The CAN protocol is primarily designed to be used as a vehicle serial data bus. The CAN module is a full implementation of the CAN protocol specification, the CAN with Flexible Data rate (CAN FD) protocol, and the CAN 2.0 Part B protocol, supporting both standard and extended message frames and long payloads up to 64 bytes, transferred at rates up to 8 Mbps. The features of the Teli nk CAN module are as follows:

• Supports CAN FD protocol and CAN Specification 2.0, Part B º Standard data frames º Extended data frames º Zero to sixty-four bytes data length º Programmable bit rate º Content-related addressing
• Compliant with the ISO 11898-1 standard
• Conform with ISO 16845-1:2016
• Flexible mailboxes configurable to store 0 to 8, 16, 32, or 64 bytes data length
• Full-featured Legacy Rx FIFO wi th storage capacity for up to 6 CAN frames and automatic internal pointer handling with DMA support 0x197 PWM23_CFG_B7 RW [0]: sync_en, sync_en_o, sync_en_o ==1: enable deep Diming Synchronization sync_en_o ==0: disable deep Diming Synchronization [1]: sync_edge, sync_edge_o, sync_edge ==1: negative edge of pulse triggers synchronization sync_edge ==0: positive edge of pulse triggers synchronization [2]: phase_mode, phase_mode_o, phase_mode_o ==1: phase is in every cycle phase_mode_o ==0: phase is in first cycle 0x00 0x198 PWM23_CFG_B8 RW [4:0]: resol, extra resolution of PWM 0x00 0x199 PWM23_CFG_B9 RW [7:0]: dead_time, dead time value 0x00 0x19a PWM23_CNT_L R [7:0]: pwm_cnt_l, PWM cnt value[7:0] 0x00 0x19b PWM23_CNT_H R [7:0]: pwm_cnt_h, PWM cnt value[15:8] 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 430 Ver 0.8.0

• Full-featured Enhanced Rx FIFO with storage capacity for up to 6 CAN FD frames and automatic internal pointer handling with DMA support
• Supports transmission abort
• Flexible message buffers, totaling 128 message buffers of 8 bytes data length each, configurable as Rx or Tx
• Time stamp based on 16-bit free-running timer with an optional external time tick or high-resolution 32-bi t on-chip timer
• Supports listen-only mode
• Maskable interrupts
• Short latency time due to an arbitration scheme for high-priority messages
• Low-power modes, with programmable wakeup on bus activity or matching with received frames (Pretended Networking)
• Transceiver Delay Compensation feature when transmitting CAN FD messages at faster data rates
• Remote request frames may be managed automatically or by software
• Supports powerful legacy (cannot be used i n CAN FD mode) and enhanced Rx FIFO ID filtering, up to 128 filter elements
• Supports Pretended Networking functionality in low-power modes: Doze mode, Stop mode
• Supports 2x CAN (CAN0, CAN1)

11.13.2 Block Diagram

The figure below shows the block diagram of the CAN Module. Figure 11-98 Block Diagram of CAN Module The Protocol Engine (PE) submodule manages the serial communication on the CAN bus: Tx Arbitration RAM Message Buffers (MBs) Rx Matching Registers CAN Transceiver Bus Interface Unit Controller Host Interface Protocol Engine CAN Tx CAN Rx Chip CAN Bus Peripheral Bus Interface Address, Data, Clocks, Interrupts

Datasheet for Telink TL3828 DS-TL3828-E5 431 Ver 0.8.0

• Requesting RAM access for receiving and transmitting message frames
• Validating received messages
• Performing error handling
• Detecting CAN FD messages The Controller Host Interface (CHI) submodule handles message buffer selection for reception and transmission, including arbitration and ID matching algorithms for both CAN FD and non-CAN FD message formats. The Bus Interface Unit (BIU) submodule controls the access to and from the i nternal interface bus to establish connection to the CPU and to other blocks. Clocks, address and data buses, interrupt outputs, DMA, and test signals are accessed through the BIU.

11.13.3 Functional Description

The CAN module is a CAN protocol engine with a very flexible mailbox system for transmitting and receiving CAN frames. The mailbox system consists of a set of message buffers (MBs) that store confi guration and control data, time stamp, message ID and data. The memory corresponding to the first 38 MBs can be configured to support a Legacy Rx FIFO reception scheme with a powerful ID filtering mechanism, capable of checking incoming frames against a table of IDs (up to 128 extended IDs or 256 standard IDs or 512 8-bit ID slices), with individual mask register for up to 32 ID Fi lter Table elements. For Classical CAN frames, simultaneous reception through the Legacy Rx FIFO and mailbox is supported. For CAN FD frames, reception is supported through mailboxes and the Enhanced Rx FIFO. For mailbox reception, a matching algorithm makes it possible to store received frames only into MBs that have the same ID programmed in the ID field. A masking scheme makes it possible to match the ID programmed on the MB wi th a range of IDs on received CAN frames. For transmission, an arbitration algorithm decides the prioritization of MBs to be transmitted based on the message ID (optionally augmented by 3 local priority bits) or the MB ordering. A message buffer is said to be active at a given time if it can participate in both the matching and arbitration processes. An Rx MB with a 0b0000 code i s inactive. Similarly, a Tx MB with a 0b1000 or 0b1001 code is also inactive. The CAN module can also receive and transmit messages in CAN FD format. The MBs are sized to adequately store the quantity of data bytes selected in the MBDSRn fields of the CAN_FDCTRL register.

11.13.4 Operating Modes

11.13.4.1 Normal Operation

The CAN module has the following functional modes: (1) Normal mode In Normal mode, the CAN operates receiving and/or transmitting message frames, errors are managed normally, and all CAN protocol functi ons are enabled. (2) Freeze mode The freeze mode is enabled when the register CAN_MCR3. FRZ (CAN_BASE+0x03[6]) is set. If enabled, Freeze mode is entered when CAN_MCR3. HALT (CAN_BASE+0x03[4]) is set or when debug mode is requested at

Datasheet for Telink TL3828 DS-TL3828-E5 432 Ver 0.8.0 chip level and CAN_MCR3. FRZACK (CAN_BASE+0x03[0]) is set by the CAN module. In Freeze mode, no transmission or reception of frames is done and synchronicity to the CAN bus is lost. (3) Loop-Back mode The CAN enters Loop-Back mode when CAN_CTRL1_1. LPB (CAN_BASE+0x05[4]) is asserted. In Loop- Back mode, the CAN performs an internal loop back that can be used for self-test operation. The bit stream output of the transmi tter is internally fed back to the receiver input. The Rx CAN input pin is ignored and the Tx CAN output goes to the recessive state (logic ‘1’). The CAN behaves as it normally does when transmitting and treats its own transmitted message as a message received from a remote node. In Loop-Back mode, the CAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field to ensure proper reception of its own message. Both transmit and receive interrupts are generated. (4) Listen-Only mode The CAN enters Li sten-Only mode when CAN_CTRL1_0. LOM (CAN_BASE+0x04[4]) is asserted. In Listen-Only mode, transmission is disabled, all error counters are frozen, and the CAN operates in a CAN Error Passive mode. Only messages acknowledged by another CAN station are received. If the CAN detects a message that has not been acknowledged, it flags a BIT0 error (without changing the receive error counter), as i f it were trying to acknowledge the message.

11.13.4.2 Low-power Operation

For low-power operation, the CAN module has: (1) Module Disable mode The module disable mode is entered when CAN_MCR3.MDIS (CAN_BASE+0x03[7]) is asserted by the CPU and CAN_MCR2.LPMACK (CAN_BASE+0x02[4]) is asserted by the CAN. When disabled, the CAN issues a request to disable the clocks to the PE and CHI submodules. Exit from module disable mode is done by negating CAN_MCR3.MDIS. The CAN module wi ll enter module disable mode by default once the chip is reset. (2) Doze mode The doze mode is entered when CAN_MCR2.DOZE (CAN_BASE+0x02[2]) is asserted, CAN_MCR0.DOZE_REQ (CAN_BASE+0x00[7]) is asserted by the CPU, and CAN_MCR2.LPMACK (CAN_BASE+0x02[4]) is asserted by the CAN. When in doze mode, the CAN issues a request to disable the clocks to the PE and the CHI submodules. Exit from doze mode occurs when CAN_MCR2.DOZE i s negated, when the chip is removed from doze mode, or when activity is detected on the CAN bus and the Self Wake Up mechanism is enabled. (3) Stop mode The stop mode is entered when CAN_MCR1.STOP_REQ (CAN_BASE+0x01[2]) is asserted by the CPU and CAN_MCR2.LPMACK (CAN_BASE+0x02[4]) is asserted by the CAN. When in stop mode, the CAN puts itself in an inactive state, then informs the CPU that the clocks can be shut down globally. Ex it from stop mode occurs when the stop mode request is removed, or when activity is detected on the CAN bus and the Self Wake Up mechanism is enabled. (4) Pretended Networking mode The pretended networking can be selected to operate together with doze mode or stop mode. Before entering doze mode or stop mode, CAN_MCR1.PNET_EN (CAN_BASE+0x01[6]) must be asserted. Once in low power mode, the CHI submodule clocks are shut down and the PE submodule i s kept clocked, so that the receive process is still active to filter incoming messages. Upon detecting a wakeup event, a Wake Up interrupt is

Datasheet for Telink TL3828 DS-TL3828-E5 433 Ver 0.8.0 issued to the system. When CAN_MCR1.PNET_EN is asserted, the CPU must disable the Self Wake Up feature by negating CAN_MCR2.SLFWAK (CAN_BASE+0x02[6]).

11.13.4.3 CAN FD Active mode

In CAN FD Active mode, the CAN is capable of transmitting and receiving all messages formatted according to the CAN FD protocol and CAN 2.0 (Classical CAN) protocol in an interleaved fashion. The CPU can set the CAN into CAN FD Acti ve mode by setting the CAN_MCR1. FDEN (CAN_BASE+0x01[3]) when the CAN is in Freeze Mode. Table 11-26 summarizes the differences in CAN feature availability in CAN FD Active mode (CAN_MCR1. FDEN = 1) and Classical CAN mode (CAN_MCR1. FDEN = 0). Table 11-26 CAN feature availability in Classical CAN and CAN FD modes

11.13.5 Interrupts

The CAN module has many interrupt sources: interrupts due to MBs and interrupts due to the OR interrupts from MBs, Bus Off, Bus Off Done, Error, Error Fast (errors detected i n the data phase of CAN FD format messages with the BRS bit set), Wake Up, Wake Up Match, Wake Up Timeout, Tx Warning, and Rx Warning. Each one of the MBs can be an interrupt source if its corresponding IMASK bit is set. There is no distinction between Tx and Rx interrupts for a particular buffer, under the assumption that the buffer is initialized for either transmission or recepti on. Each of the buffers has an assigned flag bit in the CAN_IFLAG registers. The bit is set when the corresponding buffer completes a successful transfer and is cleared when the CPU writes ‘1’ to it (unless another interrupt is generated at the same time). If the Legacy Rx FIFO is enabled (CAN_MCR3.RFEN (CAN_BASE+0x03[5]) = 1) and DMA is disabled (CAN_MCR1.DMA (CAN_BASE+0x01[7]) = 0), the interrupts corresponding to MBs 0 to 7 have different meanings:

• Bit 7 of the CAN_IFLAG1 register becomes the “Legacy Rx FIFO Overflow” flag.
• Bit 6 becomes the “Legacy Rx FIFO Warning” flag.
• Bit 5 becomes the “Frames Available in Legacy Rx FIFO” flag.
• Bit 4-0 are unused. If both Legacy Rx FIFO and DMA are enabled (CAN_MCR3.RFEN (CAN_BASE+0x 03[5]) =1 and CAN_MCR1.DMA (CAN_BASE+0x01[7]) = 1), the CAN does not generate any Legacy Rx FIFO interrupt. Bit 5 of the CAN_IFLAG1 register still indicates “Frames Available in Legacy Rx FIFO” and generates a DMA request. Bits 7, 6, and 4–0 are unused. Feature Classical CAN CAN FD Legacy Rx FIFO Yes No Legacy Rx FIFO DMA Yes No Enhanced Rx FIFO No Yes Enhanced Rx FIFO DMA No Yes Pretended Networking Yes No

Datasheet for Telink TL3828 DS-TL3828-E5 434 Ver 0.8.0 NOTE: NOTE: The Legacy Rx FIFO cannot be enabled when CAN FD feature is enabled. For a combined interrupt where multiple MB interrupt sources are OR together, the interrupt is generated when any of the associated MBs (or FIFO, if applicable) generates an interrupt. In this case, the CPU must read the CAN_IFLAG registers to determine which MB or FIFO source caused the interrupt. The i nterrupt sources for Bus Off, Bus Off Done, Error, Error Fast, Wake Up, Tx Warning and Rx Warning generate interrupts like the MB interrupt sources, and can be read from CAN_ESR1 register. The Bus Off, Error, Tx Warning, and Rx Warning interrupt mask bits are located in the CAN_CTRL1 register; the Wake Up interrupt mask bit is located in CAN_MCR. The interrupt sources for Pretended Networking (Wake up by Match Flag and Wake Up by Ti meout Flag) can be read in the CAN_WU_MTC register and the respective interrupts masks bits are located in CAN_CTRL1_PN register.

11.13.6 Enhanced Rx FIFO

As an alternative to the 6-message Legacy Rx FIFO, the CAN supports an Enhanced Rx FIFO, which can store up to 32 CAN FD messages. The region 0x2000–0x204F contains the output of the Enhanced Rx FIFO, which should be read by the CPU. The Enhanced Rx FIFO is enabled by setting CAN_EFRCR.ERFEN. The Legacy Rx FIFO and Enhanced Rx FIFO cannot be enabled at the same ti me. CAN_ERFSR.ERFDA is asserted when there is at least one frame available to be read from the Enhanced Rx FIFO. An interrupt is generated if it is enabled by setting CAN_ERFIER.ERFDAIE. Upon receiving the interrupt, the CPU can read the message (accessing the output of the Enhanced Rx FIFO), then clear the interrupt. If there are more messages in the Enhanced Rx FIFO, the act of cleari ng the interrupt updates the output of the FIFO with the next message, reissuing the interrupt to the CPU. Otherwise, the flag remains negated. The output of the Enhanced Rx FIFO is only valid while CAN_ERFSR.ERFDA is asserted. The Enhanced Rx FIFO has a watermark length, which is configured by setting CAN_EFRCR.ERFWM. The CPU can be notified if only a minimum number of messages is stor ed i n the FIFO. When the number of stored messages is greater than the value in CAN_ERFCR.ERFWM, CAN_ERFSR.ERFWMI is set by the hardware. If CAN_ERFCR.ERFWM is set to 0, then CAN_ERFSR.ERFWMI is always asserted together with CAN_ERFSR.ERFDA. An interrupt can be triggered by setting CAN_ERFIER.ERFWMIIE. A DMA transfer can be triggered by setting CAN_MCR.DMA. For the Enhanced Rx FIFO to receive, the CPU must ex ecute the following configuration procedure:

• Enter Freeze mode.
• Enable the Enhanced Rx FIFO (if it is not already enabled) by setting ERFCR.ERFEN. NOTE: CAN_MCR.RFEN must be 0 when enabling the Enhanced Rx FIFO.
• Write 1 to CAN_ERFSR.ERFCLR to reset Enhanced Rx FIFO engine.
• Clear CAN_EFRSR.ERFUFW, CAN_EFRSR.ERFOVF, CAN_EFRSR.ERFWMI, and CAN_EFRSR.ERFDA, if they are set.
• Write to CAN_EFRCR.NFE to confi gure the total number of Enhanced Rx FIFO filter elements to be used in Enhanced Rx FIFO reception.
• Write to CAN_ERFCR.NEXIF to configure the number of extended ID and standard ID filter elements to be used in Enhanced Rx FIFO reception. CAN_ERFCR.NEXIF must be less than or equal to EFRCR.NFE + 1.

Datasheet for Telink TL3828 DS-TL3828-E5 435 Ver 0.8.0

• Configure the Enhanced Rx FIFO watermark by writing CAN_ERFCR.ERFWM.
• If interrupts are to be used, set the interrupt enables in the ERIER register.
• If DMA is to be used, set CAN_MCR.DMA to enable DMA operation and write CAN_ERFCR.DMALW to configure the number of words to transfer for each Enhanced Rx FIFO data element.
• Configure the filter elements by writing to the CAN_ERFFELn regi sters. NOTE: The CAN_ERFFELn registers are in RAM and need to be explicitly initialized before any reception.
• Exit Freeze mode. The above procedure must be done if the CPU needs to change any of the configuration of the Enhanced Rx FIFO.

11.13.7 Register Description of CAN

The CAN related registers are listed as following. For CAN0 related register, the base address is 0x80144000; For CAN1 related register, the base address is 0x 80244000. Table 11-27 CAN Related Registers Bit Range Field Type Description Address offset: 0x00 Name: CAN_MCR0 Reset Value: 0x0f [6:0] MAXMB RW Number of the Last Message Buffer – Defines the number of the last message buffer that will take part in the matching and arbitration processes. The reset value (0×0F) is equivalent to a 16 message buffer configuration. MAXMB can be written only in Freeze mode because it is blocked by hardware in other modes. Number of the last MB = MAXMB Note: MAXMB must be programmed with a value smaller than or equal to the number of available message buffers. Additionally, the definition of MAXMB value must take into account the region of MBs occupied by the Legacy Rx FIFO and its ID filters table space defined by CAN_CTRL2.RFFN. MAXMB also impacts the minimum number of peripheral clocks per CAN bit as described in the CAN Integration Guide. [7] DOZE_REQ RW Doze Mode Request – Controls whether the CAN Doze mode is requested at chip level: 1: CAN is requested to enter low-power mode when Doze mode is enabled. 0: CAN is not requested to enter low-power mode when Doze mode is enabled.

Datasheet for Telink TL3828 DS-TL3828-E5 436 Ver 0.8.0 Address offset: 0x01 Name: CAN_MCR1 Reset Value: 0x00 [1:0] IDAM RW ID Acceptance Mode – Identifies the format of the Legacy Rx FIFO ID Filter Table elements: 00: Format A – One full ID (standard and extended) per ID Filter Table element. 01: Format B – Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element. 10: Format C – Four partial 8-bit standard IDs per ID Filter Table element. 11: Format D – All frames rejected. All elements of the table are configured at the same time by IDAM (they are all the same format). IDAM can be written only in Freeze mode because it is blocked by hardware in other modes. [2] STOP_REQ RW STOP Mode Request – Controls whether the CAN STOP mode is requested at chip level: 1: CAN is requested to enter Stop mode. 0: CAN is not requested to enter Stop mode. [3] FDEN RW CAN FD Operation Enable – Enables CAN with Flexible Data rate (CAN FD) operation: 1: CAN FD is enabled. The CAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats. 0: CAN FD is disabled. The CAN is able to receive and transmit messages in CAN 2.0 format. FDEN can be written in Freeze mode only. Note: The Legacy Rx FIFO Enable (RFEN) bit cannot be set if FDEN is asserted. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 437 Ver 0.8.0 [4] AEN RW Abort Enable – Enables the Tx abort mechanism: 1: Enable abort. 0: Disable abort. The Tx abort mechanism ensures a safe procedure for aborting a pending transmission, so that no frame is sent on the CAN bus without notification. AEN can be written only in Freeze mode because it is blocked by hardware in other modes. Note: When AEN is asserted, the abort mechanism must only be used for updating mailboxes configured for transmission. Caution: Writing the Abort code into Rx mailboxes can cause unpredictable results when AEN is asserted. [5] LPRIOEN RW Local Priority Enable: 1: Enable Local Priority. 0: Disable Local Priority. The LPRIOEN bit is provided for backward compatibility with legacy applications. LPRIOEN controls whether the Local Priority feature is enabled or not. Local Priority is used to expand the ID used during the arbitration process. With this expanded ID concept, the arbitration process is done based on the full 32-bit word, but the actual transmitted ID still has 11 bits for standard frames and 29 bits for extended frames. LPRIOEN can be written only in Freeze mode because it is blocked by hardware in other modes. [6] PNET_EN RW Pretended Networking Enable – Enables the Pretended Networking functionality: 1: Enable Pretended Networking mode. 0: Disable Pretended Networking mode. When Pretended Networking is enabled, the PE submodule is kept operational in Doze mode and Stop mode, so that it is able to process Rx message filtering as defined by the Pretended Networking configuration registers. PNET_EN can be written in Freeze mode only. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 438 Ver 0.8.0 [7] DMA RW DMA Enable: 1: Enable DMA feature for Rx FIFO. 0: Disable DMA feature for Rx FIFO. The DMA bit enables or disables the DMA feature. The DMA feature can only be used with the Legacy Rx FIFO or the Enhanced Rx FIFO; consequently, either CAN_MCR.RFEN or CAN_ERFCR.ERFEN must be asserted. When DMA and RFEN are both set, CAN_IFLAG1.BUF5I generates the DMA request and no Rx FIFO interrupt is generated. The DMA bit can be written in Freeze mode only as it is blocked by hardware in other modes. Address offset: 0x02 Name: CAN_MCR2 Reset Value: 0x90 [0] IRMQ RW Individual Rx Masking And Queue Enable: 1: Enable individual Rx masking and queue feature. 0: Disable individual Rx masking and queue feature. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY. IRMQ controls whether Rx matching process is based on individual masking and queue or on masking scheme with CAN_RXMGMASK, CAN_RX14MASK, CAN_RX15MASK, and CAN_RXFGMASK. IRMQ can be written in Freeze mode only because it is blocked by hardware in other modes. IRMQ cannot be set to 1 if LOCK_IRMQ is 1. [1] SRXDIS RW Self Reception Disable: 1: Disable self-reception. 0: Enable self-reception. SRXDIS controls whether the CAN is allowed to receive frames transmitted by itself. If SRXDIS is asserted, frames transmitted by the CAN are not stored in any MB, regardless of whether the MB is programmed with an ID that matches the transmitted frame, and no interrupt flag or interrupt signal is generated due to the frame reception. SRXDIS can be written only in Freeze mode because it is blocked by hardware in other modes. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 439 Ver 0.8.0 [2] DOZE RW Doze Mode Enable – Controls whether the CAN is allowed to enter low-power mode when Doze mode is requested at chip level: 1: CAN is enabled to enter low-power mode when Doze mode is requested. 0: CAN is not enabled to enter low-power mode when Doze mode is requested. DOZE is automatically reset when the CAN wakes up from Doze mode upon detecting activity on the CAN bus (Self Wake Up enabled). [3] WAKSRC RW Wake Up Source – Controls whether the integrated low-pass filter is applied to protect the Rx CAN input from spurious wakeup: 1: CAN uses the filtered Rx input to detect recessive-to- dominant edges on the CAN bus. 0: CAN uses the unfiltered Rx input to detect recessive-to- dominant edges on the CAN bus. WAKSRC can be written only in Freeze mode because it is blocked by hardware in other modes. [4] LPMACK R Low-Power Mode Acknowledge: 1: CAN is in a low-power mode. 0: CAN is not in a low-power mode. LPMACK is a read-only bit that indicates that the CAN is in a low-power mode (Module Disable, Doze, or Stop). A low-power mode cannot be entered until all current transmission or reception processes have finished. Therefore, the CPU can poll LPMACK to know when the CAN has actually entered low-power mode. LPMACK is not affected by soft reset. Note: LPMACK is asserted within 180 CAN bits from the low-power mode request by the CPU, and negated within 2 CAN bits after the low-power mode request removal. When the CAN is in Pretended Networking mode, LPMACK is negated within 180 CAN bits after the low-power mode request removal. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 440 Ver 0.8.0 [5] WRNEN RW Warning Interrupt Enable: 1: TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. 0: TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. Assertion of WRNEN enables the generation of the TWRNINT and RWRNINT flags in the Error and Status Register 1 (CAN_ESR1). If WRNEN is negated, the TWRNINT and RWRNINT flags will always be zero, independent of the values of the error counters, and no warning interrupt will ever be generated. WRNEN can be written only in Freeze mode because it is blocked by hardware in other modes. [6] SLFWAK RW Self Wake Up – Enables the Self Wake Up feature when the CAN is in a low-power mode other than Module Disable: 1: Enable CAN Self Wake Up feature. 0: Disable CAN Self Wake Up feature. When the Self Wake Up feature is enabled, the CAN module monitors the bus for wakeup event (a recessive-to-dominant transition). If a wakeup event is detected during Doze mode, the CAN requests to resume its clocks and, if enabled to do so, generates a Wake Up interrupt to the CPU. If a wakeup event is detected during Stop mode, the CAN, if enabled to do so, generates a Wake Up interrupt to the CPU so that it can exit Stop mode globally and the CAN can request to resume the clocks. When CAN is in a low-power mode other than Module Disable, SLFWAK cannot be written as it is blocked by hardware. When Pretended Networking mode is set, Self Wake Up must be disabled. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 441 Ver 0.8.0 [7] SUPV RW Supervisor Mode – Configures the CAN to be either in Supervisor or User mode: 1: CAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location. 0: CAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses. The registers affected by SUPV are marked as S/U in the Access Type column of Table 1 on page 13 in the CAN Controller User Guide. The SUPV reset value is 1, so the affected registers start with Supervisor access only. SUPV can be written only in Freeze mode because it is blocked by hardware in other modes. Address offset: 0x03 Name: CAN_MCR3 Reset Value: 0xd8 [0] FRZACK R Freeze Mode Acknowledge: 1: CAN in Freeze mode, prescaler stopped. 0: CAN not in Freeze mode, prescaler running. FRZACK is a read-only bit that indicates that the CAN is in Freeze mode and its prescaler is stopped. A Freeze mode request cannot be granted until current transmission or reception processes have finished. Therefore, software can poll FRZACK to know when the CAN has actually entered Freeze mode. If the Freeze mode request is negated, FRZACK is negated after the CAN prescaler is running again. If Freeze mode is requested when the CAN is in a low-power mode, FRZACK will be set only when the low-power mode is exited. FRZACK is not affected by soft reset. Note: FRZACK is asserted within 178 CAN bits from the Freeze mode request by the CPU, and negated within 2 CAN bits after the Freeze mode request removal. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 442 Ver 0.8.0 [1] SOFTRST RW Soft Reset: 1: Reset the registers affected by soft reset. 0: No reset request. When SOFTRST is asserted, the CAN resets its internal state machines and some of the memory-mapped registers. SOFTRST can be asserted directly by the CPU by writing to CAN_MCR. SOFTRST is also asserted when global soft reset is requested at chip level. Because soft reset is synchronous and has to follow a request/acknowledge procedure across clock domains, it may take some time to fully propagate its effect. The SOFTRST bit remains asserted while reset is pending, and is automatically negated when reset completes. Therefore, software can poll SOFTRST to know when the soft reset has completed. Soft reset cannot be applied when clocks are shut down in a low-power mode. The CAN should be first removed from low-power mode, then soft reset can be applied. SOFTRST is not affected by soft reset. [2] WAKMSK RW Wake Up Interrupt Mask – Enables Wake Up interrupt generation under the Self Wake Up mechanism: 1: Enable Wake Up interrupt. 0: Disable Wake Up interrupt. [3] NOTRDY R CAN Not Ready: 1: CAN is either in Module Disable, Doze, Stop, or Freeze mode. 0: CAN is either in Normal, Listen-Only, or Loop-Back mode. NOTRDY is a read-only bit that indicates that the CAN is either in Module Disable, Doze, Stop, or Freeze mode. NOTRDY is negated when the CAN has exited these modes. NOTRDY bit is not affected by soft reset. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 443 Ver 0.8.0 [4] HALT RW Halt CAN: 1: Enter Freeze mode if the FRZ bit is asserted. 0: No Freeze mode request. Assertion of HALT puts the CAN module into Freeze mode. The CPU should clear HALT after initializing the message buffers and the control registers CAN_CTRL1 and CAN_CTRL2. No reception or transmission is performed by the CAN before HALT is cleared. Freeze mode cannot be entered when the CAN is in a low-power mode. The HALT bit is set by hardware when a non-correctable error is detected and CAN_MECR.NCEFAFRZ is asserted. [5] RFEN RW Legacy Rx FIFO Enable – Enables or disables the Legacy Rx FIFO feature: 1: Enable Legacy Rx FIFO. 0: Disable Legacy Rx FIFO. When RFEN is set, MBs 0–5 cannot be used for normal reception and transmission because the corresponding memory region (0×80–0xDC) is used by the FIFO engine and additional MBs (up to 32, depending on CAN_CTRL2.RFFN setting), which are used as Legacy Rx FIFO ID Filter Table elements. RFEN also impacts the minimum number of peripheral clocks per CAN bit as described in the CAN Controller Integration Guide. RFEN can be written in Freeze mode only because it is blocked by hardware in other modes. Note: RFEN cannot be set when CAN FD operation is enabled (see FDEN bit). [6] FRZ RW Freeze Enable: 1: Enabled to enter Freeze mode. 0: Not enabled to enter Freeze mode. The FRZ bit specifies the CAN behavior when CAN_MCR.HALT is set or when Debug mode is requested at chip level. When FRZ is asserted, the CAN is enabled to enter Freeze mode. Negation of FRZ causes the CAN to exit from Freeze mode. FRZ is set by hardware when a non-correctable error is detected and CAN_MECR.NCEFAFRZ is asserted. [7] MDIS RW Module Disable – Disables or enables the CAN module: 1: Disable the CAN module. 0: Enable the CAN module. When disabled, the CAN disables the clocks to the PE and CHI submodules. MDIS is not affected by soft reset. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 444 Ver 0.8.0 Address offset: 0x04 Name: CAN_CTRL1_0 Reset Value: 0x00 [2:0] PROPSEG RW Propagation Segment – Defines the length of the propagation segment in the bit time. The valid programmable values are 0–7. PROPSEG can be written only in Freeze mode because it is blocked by hardware in other modes. Propagation segment time = (PROPSEG + 1) × time-quanta. Time-quantum = one Sclock period. [3] LOM RW Listen-Only Mode – Configures the CAN to operate in Listen-Only mode: 1: CAN module operates in Listen-Only mode. 0: Listen-Only mode is deactivated. In Listen-Only Mode mode, transmission is disabled, all error counters described in CAN_ECR are frozen and the CAN module operates in a CAN Error Passive mode. Only messages acknowledged by another CAN station will be received. If the CAN detects a message that has not been acknowledged, it flags a BIT0 error without changing the receive error counter (RXERRCNT) in CAN_ECR, as if it were trying to acknowledge the message. Listen-Only mode is acknowledged by the state of the CAN_ESR1.FLTCONF field indicating Passive Error. There can be some delay between the Listen-Only mode request and acknowledge. LOM can be written in Freeze mode only because it is blocked by hardware in other modes. [4] LBUF RW Lowest Buffer Transmitted First – Defines the ordering mechanism for message buffer transmission: 1: Lowest number buffer is transmitted first. 0: Buffer with highest priority is transmitted first. When LBUF is asserted, the CAN_MCR.LPRIOEN bit does not affect the priority arbitration. LBUF can be written only in Freeze mode because it is blocked by hardware in other modes. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 445 Ver 0.8.0 [5] TSYN RW Timer Sync – Enables a mechanism that resets the free-running timer each time a message is received in message buffer 0: 1: Timer Sync feature enabled. 0: Timer Sync feature disabled. The Timer Sync feature provides a means to synchronize multiple CAN stations with a special “SYNC” message (global network time). If CAN_MCR.RFEN is set (Legacy Rx FIFO enabled), the first available mailbox, according to the CAN_CTRL2.RFFN setting, is used for timer synchronization instead of MB0. TSYN can be written in Freeze mode only because it is blocked by hardware in other modes. [6] BOFFREC RW Bus Off Recovery – Defines how the CAN recovers from Bus Off state: 0: Automatic recovering from Bus Off state enabled. 1: Automatic recovering from Bus Off state disabled. If BOFFREC is negated, automatic recovering from Bus Off state occurs according to the CAN Specification 2.0B. If BOFFREC is asserted, automatic recovering from Bus Off is disabled and the CAN module remains in Bus Off state until BOFFREC is negated by software. If the negation occurs before 128 sequences of 11 recessive bits are detected on the CAN bus, then Bus Off recovery happens as if the BOFFREC bit had never been asserted. If the negation occurs after 128 sequences of 11 recessive bits occurred, then the CAN will re-synchronize to the bus by waiting for 11 recessive bits before joining the bus. After negation, BOFFREC can be re-asserted again during Bus Off, but it will be effective only the next time the CAN module enters Bus Off. If BOFFREC was negated when the CAN module entered Bus Off, asserting BOFFREC during Bus Off will not be effective for the current Bus Off recovery. [7] SMP RW CAN Bit Sampling – Defines the sampling mode of CAN bits at the Rx input: 0: One sample is used to determine the bit value. 1: Three samples are used to determine the value of the received bit: the regular sample (sample point) and two preceding samples; a majority rule is used. SMP can be written only in Freeze mode because it is blocked by hardware in other modes. Note: For proper operation, to assert SMP it is necessary to guarantee a minimum value of two time quanta in CAN_CTRL1.PSEG1 (or CAN_CBT.EPSEG1). SMP cannot be asserted when CAN FD is enabled (CAN_MCR.FDEN = 1). Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 446 Ver 0.8.0 Address offset: 0x05 Name: CAN_CTRL1_1 Reset Value: 0x00 [1] DMA_ADDR_C TRL RW DMA source address control – Defines the access output port address mode of Legacy/Enhanced Rx FIFO during DMA operation. 0x0: increment address mode 0x1: fixed address mode DMA_ADDR_CTRL can be written only in Freeze mode because it is blocked by hardware in other modes. [2] RWRNMSK RW Rx Warning Interrupt Mask – Provides a mask for the Rx Warning interrupt (CAN_ESR1.RWRNINT): 1: Rx Warning interrupt enabled. 0: Rx Warning interrupt disabled. RWRNMSK is read as zero when CAN_MCR.WRNEN is negated. RWRNMSK can bewritten only if CAN_MCR.WRNEN is asserted. [3] TWRNMSK RW Tx Warning Interrupt Mask – Provides a mask for the Tx Warning interrupt (CAN_ESR1.TWRNINT): 1: Tx Warning interrupt enabled. 0: Tx Warning interrupt disabled. TWRNMSK is read as zero when CAN_MCR.WRNEN is negated. TWRNMSK can be written only if CAN_MCR.WRNEN is asserted. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 447 Ver 0.8.0 [4] LPB RW Loop-Back Mode – Configures the CAN to operate in Loop-Back mode: 1: Loop-Back enabled. 0: Loop-Back disabled. In Loop-Back mode, the CAN performs an internal loop back that can be used for self-test operation. The bit stream output of the transmitter is fed back internally to the receiver input. The Rx CAN input pin is ignored and the Tx CAN output goes to the recessive state (logic 1). The CAN behaves as it normally does when transmitting, and treats its own transmitted message as a message received from a remote node. In Loop-Back mode, the CAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field, generating an internal acknowledge bit to ensure proper reception of its own message. Both transmit and receive interrupts are generated. LPB can be written only in Freeze mode because it is blocked by hardware in other modes. Note: In Loop-Back mode, CAN_MCR.SRXDIS cannot be asserted because it would impede the self-reception of a transmitted message. Note: CAN_FDCTRL.TDCEN must be 0 (Transceiver Delay Compensation feature disabled) when LPB is asserted. [5] CLKSRC RW CAN Engine Clock Source – Selects the clock source to the PE submodule to be either the peripheral clock or the oscillator clock: 1: The PE clock source is the peripheral clock. 0: The PE clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the peripheral clock frequency. The selected clock is fed to the prescaler to generate the serial clock (Sclock). To ensure reliable operation, CLKSRC can be written only in Disable mode. In other modes, writing to CLKSRC is blocked by hardware. [6] ERRMSK RW Error Interrupt Mask – Provides a mask for the Error interrupt (CAN_ESR1.ERRINT). 0: Error interrupt disabled. 1: Error interrupt enabled. [7] BOFFMSK RW Bus Off Interrupt Mask – Provides a mask for the Bus Off interrupt (CAN_ESR1.BOFFINT): 1: Bus Off interrupt enabled. 0: Bus Off interrupt disabled. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 448 Ver 0.8.0 Address offset: 0x06 Name: CAN_CTRL1_2 Reset Value: 0x00 [2:0] PSEG2 RW Phase Segment 2 – Defines the length of phase segment 2 in the bit time. The valid programmable values are 1–7. PSEG2 can be written only in Freeze mode because it is blocked by hardware in other modes. Phase Buffer Segment 2 = (PSEG2 + 1) × Time-Quanta [5:3] PSEG1 RW Phase Segment 1 – Defines the length of phase segment 1 in the bit time. The valid programmable values are 0–7. PSEG1 can be written only in Freeze mode because it is blocked by hardware in other modes. Phase Buffer Segment 1 = (PSEG1 + 1) × Time-Quanta [7:6] RJW RW Resync Jump Width – Defines the maximum number of time quanta that a bit time can be changed by one re-synchronization. One time quantum is equal to the Sclock period. The valid programmable values for RJW are 0–3. RJW can be written only in Freeze mode because it is blocked by hardware in other modes. Resync Jump Width = RJW + 1 Address offset: 0x07 Name: CAN_CTRL1_3 Reset Value: 0x00 [7:0] PRESDIV RW Prescaler Division Factor – Defines the ratio between the PE clock frequency and the serial clock (Sclock) frequency. The Sclock period defines the time quantum of the CAN protocol. For the reset value, the Sclock frequency is equal to the PE clock frequency. The maximum value of PRESDIV is 0xFF, which gives a minimum Sclock frequency equal to the PE clock frequency divided by 256. PRESDIV can be written only in Freeze mode because it is blocked by hardware in other modes. Sclock frequency = PE clock frequency / (PRESDIV + 1) Address offset: 0x08 Name: CAN_TIMER0 Reset Value: 0x00 [7:0] TIMER[7:0] RW Timer Value – Contains the free-running counter value. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 449 Ver 0.8.0 Address offset: 0x09 Name: CAN_TIMER1 Reset Value: 0x00 [7:0] TIMER[15:8] RW Timer Value – Contains the free-running counter value. Address offset: 0x10 Name: CAN_RXMGMASK0 Reset Value: 0x00 [7:0] MG[7:0] RW Rx Mailboxes Global Mask Bits: 0: The corresponding bit in the filter is “don’t care”. 1: The corresponding bit in the filter is checked. The MG bits mask the mailbox filter bits. Note that the alignment with the ID word of the mailbox is not perfect as the two most significant MG bits affect the fields RTR and IDE, which are located in the Control and Status (C/S) word of the mailbox. Table 7 in the user guide shows in detail which MG bits mask each mailbox filter field. Address offset: 0x11 Name: CAN_RXMGMASK1 Reset Value: 0x00 Address offset: 0x12 Name: CAN_RXMGMASK2 Reset Value: 0x00 Address offset: 0x13 Name: CAN_RXMGMASK3 Reset Value: 0x00 Address offset: 0x14 Name: CAN_RX14MASK_0 Reset Value: 0x00 Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 450 Ver 0.8.0 [7:0] RX14M[7:0] RW Rx Buffer 14 Mask Bits: 0: The corresponding bit in the filter is “don’t care”. 1: The corresponding bit in the filter is checked. Each mask bit masks the corresponding mailbox 14 filter field in the same way that CAN_RXMGMASK masks other mailboxes’ filters. See the description of the CAN_RXMGMASK register. Address offset: 0x15 Name: CAN_RX14MASK_1 Reset Value: 0x00 Address offset: 0x16 Name: CAN_RX14MASK_2 Reset Value: 0x00 Address offset: 0x17 Name: CAN_RX14MASK_3 Reset Value: 0x00 Address offset: 0x18 Name: CAN_RX15MASK_0 Reset Value: 0x00 [7:0] RX15M[7:0] RW Rx Buffer 15 Mask Bits: 0: The corresponding bit in the filter is “don’t care”. 1: The corresponding bit in the filter is checked. Each mask bit masks the corresponding mailbox 15 filter field in the same way that CAN_RXMGMASK masks other mailboxes’ filters. See the description of the CAN_RXMGMASK register. Address offset: 0x19 Name: CAN_RX15MASK_1 Reset Value: 0x00 Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 451 Ver 0.8.0 Address offset: 0x1a Name: CAN_RX15MASK_2 Reset Value: 0x00 Address offset: 0x1b Name: CAN_RX15MASK_3 Reset Value: 0x00 Address offset: 0x1c Name: CAN_ECR_0 Reset Value: 0x00 [7:0] TXERRCNT RW Transmit Error Counter – Transmit error counter for all errors detected in transmitted messages. The TXERRCNT counter is read-only except in Freeze mode, in which it can be written by the CPU. Address offset: 0x1d Name: CAN_ECR_1 Reset Value: 0x00 [7:0] RXERRCNT RW Receive Error Counter – Receive error counter for all errors detected in received messages. The RXERRCNT counter is read-only except in Freeze mode, in which it can be written by the CPU. Address offset: 0x1e Name: CAN_ECR_2 Reset Value: 0x00 [7:0] TXERRCNT_FA ST RW Transmit Error Counter for Fast Bits – Transmit error counter for errors detected in the Data Phase of transmitted CAN FD messages with the BRS bit set. The TXERRCNT_FAST counter is read-only except in Freeze mode, in which the CPU can write a 8-bit zero value only. Address offset: 0x1f Name: CAN_ECR_3 Reset Value: 0x00 Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 452 Ver 0.8.0 [7:0] RXERRCNT_FA ST RW Receive Error Counter for Fast Bits – Receive error counter for errors detected in the Data Phase of received CAN FD messages with the BRS bit set. The RXERRCNT_FAST counter is read-only except in Freeze mode, in which the CPU can write an 8-bit zero value only. Address offset: 0x20 Name: CAN_ESR1_0 Reset Value: 0x00 [0] WAKINT W1C Wake Up Interrupt – Applies when the CAN is in low-power mode under Self Wake Up mechanism, either Doze mode or Stop mode: 1: Indicates a recessive-to-dominant transition was received on the CAN bus. 0: No such occurrence. When a recessive-to-dominant transition is detected on the CAN bus and the CAN_MCR.WAKMSK bit is set, an interrupt is generated to the CPU. This bit is cleared by writing it to 1. When CAN_MCR.SLFWAK is negated, the WAKINT flag is masked. The CPU must clear the WAKINT flag before negating the CAN_MCR.SLFWAK bit. Otherwise, WAKINT will be set when CAN_MCR.SLFWAK is set again. Writing 0 has no effect. WAKINT is cleared by writing 1 to it. Writing 0 has no effect. [1] ERRINT W1C Error Interrupt: 1: Indicates setting of any error bit in CAN_ESR1. 0: No such occurrence. ERRINT indicates that at least one of the error bits (BIT1ERR, BIT0ERR, ACKERR, CRCERR, FRMERR, or STFERR) is set. If the corresponding mask bit (CAN_CTRL1.ERRMSK) is set, an interrupt is generated to the CPU. ERRINT is cleared by writing 1 to it. Writing 0 has no effect. [2] BOFFINT W1C Bus Off Interrupt: 1: CAN module entered Bus Off state. 0: No such occurrence. BOFFINT is set when the CAN enters the Bus Off state. If the corresponding mask bit (CAN_CTRL1.BOFFMSK) is set, an interrupt is generated to the CPU. BOFFINT is cleared by writing 1 to it. Writing 0 has no effect. [3] RX R CAN in Reception – Indicates if the CAN is receiving a message: 1: CAN is receiving a message. 0: CAN is not receiving a message. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 453 Ver 0.8.0 [5:4] FLTCONF R Fault Confinement State – Indicates the fault confinement state of the CAN module: 00: Error Active 01: Error Passive 1x: Bus Off If CAN_CTRL1.LOM is asserted, after a delay that depends on the CAN bit timing, the FLTCONF field will indicate Error Passive. The same delay affects how FLTCONF reflects an update to the CAN_ECR register by the CPU. It may take up to one CAN bit time to get them coherent again. FLTCONF is affected by soft reset. However, if CAN_CTRL1.LOM is asserted, the FLTCONF reset value lasts just one CAN bit. After this time, FLTCONF indicates Error Passive. [6] TX R CAN in Transmission – Indicates if the CAN is transmitting a message: 1: CAN is transmitting a message. 0: CAN is not transmitting a message. [7] IDLE R IDLE – Indicates when the CAN bus is in the IDLE state: 1: CAN bus is now IDLE. 0: No such occurrence. Address offset: 0x21 Name: CAN_ESR1_1 Reset Value: 0x00 [0] RXWRN R Rx Error Warning – Indicates when repetitive errors are occurring during message reception: 1: RXERRCNT is greater than or equal to 96. 0: No such occurrence. RXWRN is affected by the value of CAN_ECR.RXERRCNT only. RXWRN is not updated during Freeze mode. RXWRN is updated when the CAN returns to Normal mode from Pretended Networking mode. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 454 Ver 0.8.0 [1] TXWRN R TX Error Warning – Indicates when repetitive errors are occurring during message transmission: 1: TXERRCNT is greater than or equal to 96. 0: No such occurrence. TXWRN is affected by the value of CAN_ECR.TXERRCNT only. TXWRN is not updated during Freeze mode. [2] STFERR R Stuffing Error – Indicates that a stuffing error was detected by the receiver node in a non-FD message or in a CAN FD message arbitration or Data Phase: 1: A stuffing error occurred since last read of this register. 0: No such occurrence. STFERR is updated when the CAN returns to Normal mode from Pretended Networking mode. [3] FRMERR Form Error – Indicates that a form error was detected by the receiver node in a non-FD message or in a CAN FD message arbitration or Data Phase (that is, a fixed-form bit field contains at least one illegal bit): 1: A form error occurred since last read of this register. 0: No such occurrence. FRMERR is updated when the CAN returns to Normal mode from Pretended Networking mode. [4] CRCERR R Cyclic Redundancy Check Error – Indicates that a CRC error was detected by the receiver node either in a non-FD message or in the arbitration or Data Phase of a frame in CAN FD format (that is, the calculated CRC is different from the received CRC): 1: A CRC error occurred since last read of this register. 0: No such occurrence. CRCERR is updated when the CAN returns to Normal mode from Pretended Networking mode. [5] ACKERR R Acknowledge Error – Indicates that an Acknowledge error was detected by the transmitter node (that is, a dominant bit was detected during the ACK SLOT): 1: An ACK error occurred since last read of this register. 0: No such occurrence. ACKERR is updated when the CAN returns to Normal mode from Pretended Networking mode. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 455 Ver 0.8.0 [6] BIT0ERR R Bit0 Error – Indicates when an inconsistency occurs between the transmitted and the received bit in a non-CAN FD message or in the arbitration or Data Phase of a CAN FD message: 1: At least one bit sent as dominant is received as recessive. 0: No such occurrence. BIT0ERR is updated when the CAN returns to Normal mode from Pretended Networking mode. [7] BIT1ERR R Bit1 Error – Indicates when an inconsistency occurs between the transmitted and the received bit in a non-CAN FD message or in the arbitration or Data Phase of a CAN FD message: 1: At least one bit sent as recessive is received as dominant. 0: No such occurrence. BIT1ERR is updated when the CAN returns to Normal mode from Pretended Networking mode. Note: BIT1ERR is not set by a transmitter in case of arbitration field or ACK slot, or in case of a node sending a passive error flag that detects dominant bits. Address offset: 0x22 Name: CAN_ESR1_2 Reset Value: 0x00 [0] RWRNINT W1C Rx Warning Interrupt Flag: 1: The Rx error counter transitioned from less than 96 to greater than or equal to 96. 0: No such occurrence. If CAN_MCR.WRNEN is asserted, the RWRNINT bit is set when the RXWRN flag transitions from 0 to 1, meaning that the Rx error counters reached 96. If the corresponding mask bit (CAN_CTRL1.RWRNMSK) is set, an interrupt is generated to the CPU. RWRNINT is cleared by writing it to 1 to it. Writing 0 has no effect. When CAN_MCR.WRNEN is negated, the RWRNINT flag is masked. The CPU must clear the RWRNINT flag before negating CAN_MCR.WRNEN. Otherwise, RWRNINT will be set when CAN_MCR.WRNEN is set again. RWRNINT is not updated during Freeze mode. When the CAN returns to Normal mode from Pretended Networking mode, RWRNINT is updated to reflect the Rx error counter state. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 456 Ver 0.8.0 [1] TWRNINT W1C Tx Warning Interrupt Flag: 1: The Tx error counter transitioned from less than 96 to greater than or equal to 96. 0: No such occurrence. If CAN_MCR.WRNEN is asserted, the TWRNINT bit is set when the TXWRN flag transitions from 0 to 1, meaning that the Tx error counter reached 96. If the corresponding mask bit (CAN_CTRL1.TWRNMSK) is set, an interrupt is generated to the CPU. TWRNINT is cleared by writing 1 to it. Writing 0 has no effect. When CAN_MCR.WRNEN is negated, the TWRNINT flag is masked. The CPU must clear the TWRNINT flag before negating CAN_MCR.WRNEN. Otherwise, TWRNINT will be set when CAN_MCR.WRNEN is set again. TWRNINT is not generated during the Bus Off state and is not updated during Freeze mode. When the CAN returns to Normal mode from Pretended Networking mode, TWRNINT is not updated. [2] SYNCH R CAN Synchronization Status: 1: CAN is synchronized to the CAN bus. 0: CAN is not synchronized to the CAN bus. SYNCH is a read-only flag that indicates whether the CAN is synchronized to the CAN bus and able to participate in the communication process. It is set and cleared by the CAN. [3] BOFFDONEINT W1C Bus Off Done Interrupt: 1: CAN module has completed Bus Off process. 0: No such occurrence. BOFFDONEINT is set when the Tx Error Counter (TXERRCNT) has finished counting 128 occurrences of 11 consecutive recessive bits on the CAN bus and is ready to leave Bus Off. If the corresponding mask bit (CAN_CTRL2.BOFFDONEMSK) is set, an interrupt is generated to the CPU. BOFFDONEINT is cleared by writing 1 to it. Writing 0 has no effect. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 457 Ver 0.8.0 [4] ERRINT_FAST W1C Error Interrupt for Errors Detected in the Data Phase of CAN FD Frames with the BRS Bit Set: 1: Indicates setting of any error bit detected in the Data Phase of CAN FD frames with the BRS bit set. 0: No such occurrence. ERRINT_FAST indicates that at least one of the error bits detected in the Data Phase of CAN FD frames with the BRS bit set (BIT1ERR_FAST, BIT0ERR_FAST, CRCERR_FAST, FRMERR_FAST, or STFERR_FAST) is set. If the corresponding mask bit (CAN_CTRL2.ERRMSK_FAST) is set, an interrupt is generated to the CPU. ERRINT_FAST is cleared by writing 1 to it. Writing 0 has no effect. [5] ERROVR W1C Error Overrun – Indicates that an error condition occurred when any error flag is already set: 1: Overrun has occurred. 0: Overrun has not occurred. ERROVR is cleared by writing 1 to it. Address offset: 0x23 Name: CAN_ESR1_3 Reset Value: 0x00 [2] STFERR_FAST R Stuffing Error in the Data Phase of CAN FD Frames with the BRS Bit Set STFERR_FAST indicates that a stuffing error has been detected in the Data Phase of CAN FD frames with the BRS bit set: 1: A stuffing error occurred since last read of this register. 0: No such occurrence. [3] FRMERR_FAST R Form Error in the Data Phase of CAN FD Frames with the BRS Bit Set FRMERR_FAST indicates that a form error has been detected by the receiver node in the Data Phase of CAN FD frames with the BRS bit set; that is, a fixed-form bit field contains at least one illegal bit: 1: A form error occurred since last read of this register. 0: No such occurrence. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 458 Ver 0.8.0 [4] CRCERR_FAST R Cyclic Redundancy Check Error in the CRC field of CAN FD Frames with the BRS Bit Set CRCERR_FAST indicates that a CRC error has been detected by the receiver node in the CRC field of CAN FD frames with the BRS bit set; that is, the calculated CRC is different from the received CRC: 1: A CRC error occurred since last read of this register. 0: No such occurrence. [6] BIT0ERR_FAST R Bit0 Error in the Data Phase of CAN FD Frames with the BRS Bit Set BIT0ERR_FAST indicates when an inconsistency occurs between the transmitted and the received bit in the Data Phase of CAN FD frames with the BRS bit set: 1: At least one bit sent as dominant is received as recessive. 0: No such occurrence. [7] BIT1ERR_FAST R Bit1 Error in the Data Phase of CAN FD Frames with the BRS Bit Set BIT1ERR_FAST indicates when an inconsistency occurs between the transmitted and the received bit in the Data Phase of CAN FD frames with the BRS bit set: 1: At least one bit sent as recessive is received as dominant. 0: No such occurrence. Address offset: 0x24 Name: CAN_IMASK2_0 Reset Value: 0x00 [7:0] BUF63TO32M [7:0] RW Buffer MB i Mask Each bit enables or disables the corresponding CAN Message Buffer Interrupt for MB63 to MB32: 1: The corresponding buffer interrupt is enabled. 0: The corresponding buffer interrupt is disabled. Note: Setting or clearing a bit in CAN_IMASK2 can assert or negate an interrupt request if the corresponding CAN_IFLAG2 bit is set. Address offset: 0x25 Name: CAN_IMASK2_1 Reset Value: 0x00 [7:0] BUF63TO32M [15:8] RW - Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 459 Ver 0.8.0 Address offset: 0x26 Name: CAN_IMASK2_2 Reset Value: 0x00 [7:0] BUF63TO32M [23:16] RW - Address offset: 0x27 Name: CAN_IMASK2_3 Reset Value: 0x00 [7:0] BUF63TO32M [31:16] RW - Address offset: 0x28 Name: CAN_IMASK1_0 Reset Value: 0x00 [7:0] BUF31TO0M [7:0] RW Buffer MB i Mask Each bit enables or disables the corresponding CAN Message Buffer Interrupt for MB31 to MB0: 1: The corresponding buffer interrupt is enabled. 0: The corresponding buffer interrupt is disabled. Note: Setting or clearing a bit in CAN_IMASK1 can assert or negate an interrupt request if the corresponding CAN_IFLAG1 bit is set. Address offset: 0x29 Name: CAN_IMASK1_1 Reset Value: 0x00 [7:0] BUF31TO0M [15:8] RW - Address offset: 0x2a Name: CAN_IMASK1_2 Reset Value: 0x00 [7:0] BUF31TO0M [23:16] RW - Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 460 Ver 0.8.0 Address offset: 0x2b Name: CAN_IMASK1_3 Reset Value: 0x00 [7:0] BUF31TO0M [31:16] RW - Address offset: 0x2c Name: CAN_IFLAG2_0 Reset Value: 0x00 [7:0] BUF63TO32I [7:0] W1C Buffer MB i Interrupt Each bit flags the corresponding CAN Message Buffer Interrupt for MB63 to MB32: 1: The corresponding buffer has successfully completed transmission or reception. 0: The corresponding buffer has no occurrence of successfully completed transmission or reception. Address offset: 0x2d Name: CAN_IFLAG2_1 Reset Value: 0x00 [7:0] BUF63TO32I [15:8] W1C - Address offset: 0x2e Name: CAN_IFLAG2_2 Reset Value: 0x00 [7:0] BUF63TO32I [23:16] W1C - Address offset: 0x2f Name: CAN_IFLAG2_3 Reset Value: 0x00 [7:0] BUF63TO32I [31:16] W1C - Address offset: 0x30 Name: CAN_IFLAG1_0 Reset Value: 0x00 Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 461 Ver 0.8.0 [0] BUF0I W1C Buffer MB0 Interrupt or Clear FIFO bit When CAN_MCR.RFEN is cleared (Legacy Rx FIFO disabled), BUF0I flags the interrupt for MB0: 1: MB0 has successfully completed transmission or reception when CAN_MCR.RFEN=0. 0: MB0 has no occurrence of successfully completed transmission or reception when CAN_MCR.RFEN=0. When CAN_MCR.RFEN is set (Legacy Rx FIFO enabled), BUF0I is used to trigger the clear FIFO operation. This operation empties FIFO contents. Before performing this operation, the CPU must service all FIFO related IFLAGs. When CAN_MCR.DMA is set (DMA is enabled), this operation also clears the BUF5I flag and consequently aborts the DMA request. The clear FIFO operation occurs when the CPU writes 1 to BUF0I, which is only allowed in Freeze mode and is blocked by hardware in other conditions. [4:1] BUF4TO1I W1C Buffer MB Interrupt or Reserved: 1: The corresponding buffer has successfully completed transmission or reception when CAN_MCR.RFEN=0. 0: The corresponding buffer has no occurrence of successfully completed transmission or reception when CAN_MCR.RFEN=0. When CAN_MCR.RFEN is cleared (Legacy Rx FIFO disabled), BUF4TO1I flag the interrupts for MB4 to MB1. When CAN_MCR.RFEN is set (Legacy Rx FIFO enabled), BUF4TO1I flags are reserved. Note: BUF4TO1I are cleared by the CAN whenever CAN_MCR.RFEN is changed by a CPU write. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 462 Ver 0.8.0 [5] BUF5I W1C Buffer MB5 Interrupt or Frames Available in Legacy Rx FIFO: 1: MB5 completed transmission/reception when CAN_MCR.RFEN=0, or frame(s) available in the Legacy Rx FIFO when CAN_MCR.RFEN=1. BUF5I generates a DMA request when both CAN_MCR.RFEN and CAN_MCR.DMA are set. 0: No occurrence of MB5 completing transmission/reception when CAN_MCR.RFEN=0, or of frame(s) available in the FIFO, when CAN_MCR.RFEN=1. When CAN_MCR.RFEN is cleared (Legacy Rx FIFO disabled), BUF5I flags the interrupt for MB5. When CAN_MCR.RFEN is set (Legacy Rx FIFO enabled), BUF5I represents Frames Available in Legacy Rx FIFO and indicates that at least one frame is available to be read from the Legacy Rx FIFO. When CAN_MCR.DMA is set, BUF5I generates a DMA request and the CPU must not clear BUF5I by writing 1 to it. Note: BUF5I is cleared by the CAN whenever CAN_MCR.RFEN is changed by a CPU write. [6] BUF6I W1C Buffer MB6 Interrupt or Legacy Rx FIFO Warning: 1: MB6 completed transmission/reception when CAN_MCR.RFEN=0, or Legacy Rx FIFO almost full when CAN_MCR.RFEN=1. 0: No occurrence of MB6 completing transmission/reception when CAN_MCR.RFEN=0, or of Legacy Rx FIFO almost full when CAN_MCR.RFEN=1. When CAN_MCR.RFEN is cleared (Legacy Rx FIFO disabled), BUF6I flags the interrupt for MB6. When CAN_MCR.RFEN is set (Legacy Rx FIFO enabled), BUF6I represents Legacy Rx FIFO Warning. In this case, BUF6I indicates when the number of unread messages in the Legacy Rx FIFO increases from 4 to 5 due to the reception of a new message, meaning that the Legacy Rx FIFO is almost full. Note that if BUF6I is cleared when the number of unread messages is greater than 4, BUF6I is not asserted again until the number of unread messages in the Legacy Rx FIFO decreases to 4 or less. Note: BUF6I is cleared by the CAN whenever CAN_MCR.RFEN is changed by a CPU write. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 463 Ver 0.8.0 [7] BUF7I W1C Buffer MB7 Interrupt or Legacy Rx FIFO Overflow: 1: MB7 completed transmission/reception when CAN_MCR.RFEN=0, or Legacy Rx FIFO overflow when CAN_MCR.RFEN=1. 0: No occurrence of MB7 completing transmission/reception when CAN_MCR.RFEN=0, or of Legacy Rx FIFO overflow when CAN_MCR.RFEN=1. When CAN_MCR.RFEN is cleared (Legacy Rx FIFO disabled), BUF71 flags the interrupt for MB7. When CAN_MCR.RFEN is set (Legacy Rx FIFO enabled), BUF7I represents Legacy Rx FIFO Overflow. In this case, BUF7I indicates that a message was lost because the Legacy Rx FIFO is full. Note that BUF7I is not asserted when the Legacy Rx FIFO is full and the message was captured by a mailbox. Note: BUF7I is cleared by the CAN whenever CAN_MCR.RFEN is changed by a CPU write. Address offset: 0x31 Name: CAN_IFLAG1_1 Reset Value: 0x00 [7:0] BUF15TO8I W1C Buffer MBi Interrupt Each bit flags the corresponding CAN Message Buffer Interrupt for MB15 to MB8: 1: The corresponding buffer has successfully completed transmission or reception. 0: The corresponding buffer has no occurrence of successfully completed transmission or reception. Address offset: 0x32 Name: CAN_IFLAG1_2 Reset Value: 0x00 [7:0] BUF31TO16I [7:0] W1C Buffer MBi Interrupt Each bit flags the corresponding CAN Message Buffer Interrupt for MB23 to MB16: 1: The corresponding buffer has successfully completed transmission or reception. 0: The corresponding buffer has no occurrence of successfully completed transmission or reception. Address offset: 0x33 Name: CAN_IFLAG1_3 Reset Value: 0x00 Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 464 Ver 0.8.0 [7:0] BUF31TO16I [15:8] W1C Buffer MBi Interrupt Each bit flags the corresponding CAN Message Buffer Interrupt for MB31 to MB24: 1: The corresponding buffer has successfully completed transmission or reception. 0: The corresponding buffer has no occurrence of successfully completed transmission or reception. Address offset: 0x34 Name: CAN_CTRL2_0 Reset Value: 0x00 [7:6] TSTAMPCAP RW Time Stamp Capture Point TSTAMPCAP configures the point in time at which a 32-bit time base is captured during a CAN frame and stored in the high-resolution time stamp register (CAN_HR_TIME_STAMPn). For Classical CAN frames, capture points can be the start of frame (SOF) bit or the point in time when a CAN frame is considered valid, which is the 7th bit of end of frame for transmission and the 6th bit of the end of frame for reception. For CAN FD frames, the high-resolution time stamp can be captured at SOF, the point in time when a CAN FD frame is considered valid, or the res bit. The TSTAMPCAP encoding is: 00: The high-resolution time stamp capture is disabled. 01: The high-resolution time stamp is captured at the end of the CAN frame. 10: The high-resolution time stamp is captured at the start of the CAN frame. 11: The high-resolution time stamp is captured at the start of frame for classical CAN frames and at the res bit for CAN FD frames. TSTAMPCAP is writable only in Freeze mode. Address offset: 0x35 Name: CAN_CTRL2_1 Reset Value: 0x00 Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 465 Ver 0.8.0 [1:0] MBTSBASE RW Message Buffer Time Stamp Base MBTSBASE selects which time base is used for capturing the 16-bit TIME STAMP field of the message buffer: 00: Message buffer time stamp base is CAN_TIMER. 01: Message buffer time stamp base is lower 16 bits of high- resolution timer. 10: Message buffer time stamp base is upper 16 bits of high-resolution timer. 11: Reserved. MBTSBASE is writable only in Freeze mode. [3] EDFLTDIS RW Edge Filter Disable – Disables the edge filter used during the bus integration state: 1: Edge filter is disabled. 0: Edge filter is enabled. When the edge filter is enabled, two consecutive nominal time quanta with dominant bus state are required to detect an edge that causes synchronization. When synchronization occurs, the counting of the sequence of eleven consecutive recessive bits is restarted. The edge filter prevents the dominant pulses that are shorter than a nominal bit time (present during the data phase of an FD Frame) from being mistaken for an idle condition. EDFLTDIS is writable only in Freeze mode. [4] ISOCANFDEN RW ISO CAN FD Enable 1: Enable ISO CAN FD compliant operation. 0: Disable ISO CAN FD specific features (non-ISO CAN FD operation). ISOCANFDEN enables ISO CAN FD compliant operation by enabling the following features, which are part of the ISO 11898 standard and not included in the original (Bosch) CAN FD protocol specification: The count of variable stuff bits inserted from the Start of Frame bit to the last bit of Data field. Also, the modulo 8 count of variable stuff bits plus the respective parity bit (even parity calculated over the 3-bit modulo 8 count) are combined as the 4-bit Stuff Count field and inserted before the CRC Sequence field. CRC calculation extends beyond the end of Data field and takes the Stuff Count field bits into account. ISOCANFDEN is writable only in Freeze mode. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 466 Ver 0.8.0 [5] BTE RW Bit Timing Expansion Enable – Enables the use of the CAN_EPRS, CAN_EDCBT, and CAN_ENCBT registers to configure the CAN bit timing segments, instead of using the bit timing fields of the CAN_CBT, CAN_FDCBT, and CAN_CTRL1 registers: 1: CAN bit timing expansion is enabled. 0: CAN bit timing expansion is disabled. When BTE = 1: Registers CAN_EPRS, CAN_EDCBT, and CAN_ENCBT are used to specify the CAN bit timing. The PRESDIV, PROPSEG, PSEG1, PSEG2, and RJW fields in the CAN_CTRL1 register are read as zero, and a write operation to them has no effect. The EPRESDIV, ERJW, EPROPSEG, EPSEG1, and EPSEG2 fields in the CAN_CBT register are read as zero and a write operation to them has no effect. The CAN_FDCBT register is read as zero and a write operation to it has no effect. The TDCOFF, TDCEN, TDCFAIL, and TDCVAL fields in the CAN_FDCTRL register are read as zero and a write operation to them has no effect. The ETDCOFF, ETDCEN, ETDCFAIL, and ETDCVAL fields of the CAN_ETDC register are used for transceiver delay compensation. CAN_ETDC.TDMDIS can be used to disable transceiver delay measurement. [6] PREXCEN RW Protocol Exception Enable – Enables the protocol exception feature: 1: Protocol exception is enabled. 0: Protocol exception is disabled. PREXCEN is writable only in Freeze mode. [7] TIMER_SRC RW Timer Source – Selects the time tick source used for incrementing the free-running timer counter: 1: The free-running timer is clocked by an external time tick. The period can be either adjusted to be equal to the baud rate on the CAN bus or a different value as required. 0: The free-running timer is clocked by the CAN bit clock, which defines the baud rate on the CAN bus. TIMER_SRC can be written in Freeze mode only. Address offset: 0x36 Name: CAN_CTRL2_2 Reset Value: 0x10 Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 467 Ver 0.8.0 [0] EACEN RW Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes: 1: Enables the comparison of both the IDE and RTR bits of an Rx mailbox filter with the corresponding bits of the incoming frame. Mask bits do apply. 0: Rx mailbox filter’s IDE bit is always compared and RTR is never compared, regardless of mask bits. EACEN controls the comparison of IDE and RTR bits within Rx mailboxes filters with their corresponding bits in the incoming frame by the matching process. EACEN does not affect matching for Legacy Rx FIFO. EACEN can be written only in Freeze mode because it is blocked by hardware in other modes. [1] RRS RW Remote Request Storing: 1: Remote Request Frame is stored. 0: Remote Response Frame is generated. If RRS is asserted, a Remote Request Frame is submitted to a matching process and stored in the corresponding message buffer in the same fashion as a Data Frame. No automatic Remote Response Frame will be generated. If RRS is negated, the Remote Request Frame is submitted to a matching process and an automatic Remote Response Frame is generated if a message buffer with CODE=0b1010 is found with the same ID. RRS can be written only in Freeze mode because it is blocked by hardware in other modes. [2] MRP RW Mailboxes Reception Priority: 1: Matching starts from mailboxes and continues on Legacy Rx FIFO. 0: Matching starts from Legacy Rx FIFO and continues on mailboxes. If MRP is set, the matching process starts from the mailboxes and if no match occurs the matching continues on the Legacy Rx FIFO. MRP can be written only in Freeze mode because it is blocked by hardware in other modes. [7:3] TASD RW Tx Arbitration Start Delay – Indicates how many CAN bits the Tx arbitration process start point can be delayed from the first bit of CRC field on CAN bus. TASD can be written only in Freeze mode because it is blocked by hardware in other modes. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 468 Ver 0.8.0 Address offset: 0x37 Name: CAN_CTRL2_3 Reset Value: 0x00 [3:0] RFFN RW Number of Legacy Rx FIFO Filters – Defines the number of Legacy Rx FIFO filters, as shown in Table 18. The maximum selectable number of filters is a function of configuration parameter NUMBER_OF_MB. RFFN must not be programmed with values that cause the number of message buffers occupied by Legacy Rx FIFO and ID Filter to exceed the number of mailboxes present, defined by CAN_MCR.MAXMB. Each group of eight filters occupies a memory space equivalent to two message buffers, which means that as more filters are implemented fewer mailboxes are available. Considering that the Legacy Rx FIFO occupies the memory space originally reserved for MB0–5, RFFN should be programmed with a value corresponding to a number of filters not greater than the number of available memory words, which can be calculated as follows: (SETUP_MB – 6) × 4 where SETUP_MB is the lower value between parameter NUMBER_OF_MB and register field CAN_MCR.MAXMB. The number of remaining mailboxes available will be: (SETUP_MB – 8) – (RFFN × 2) If the number of Legacy Rx FIFO filters programmed through RFFN exceeds the SETUP_MB value (memory space available), the exceeding ones will not be functional. Note: The number of the last remaining available mailbox is defined by the least value between (NUMBER_OF_MB – 1) and the CAN_MCR.MAXMB field. If Rx Individual Mask registers are not enabled, all Legacy Rx FIFO filters are affected by the Legacy Rx FIFO Global Mask. RFFN can only be written in Freeze mode as it is blocked by hardware in other modes. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 469 Ver 0.8.0 [4] WRMFRZ RW Write-Access To Memory In Freeze Mode – Enable unrestricted write access to CAN memory in Freeze mode: 0: Maintain the write access restrictions. 1: Enable unrestricted write access to CAN memory. WRMFRZ can only be written in Freeze mode and has no effect out of Freeze mode. CAN_MCR.RFEN bit must not be set during CAN memory initialization. [5] ECRWRE RW Error-Correction Configuration Register Write Enable – Enables the CAN_MECR register to be updated: 1: Enable update. 0: Disable update. ECRWRE is automatically set to 0 if the protocol described in section “Detection and Correction of Memory Errors” of the CAN Controller User Guide is not followed. [6] BOFFDONEMS K RW Bus Off Done Interrupt Mask – Provides a mask for the Bus Off done interrupt in CAN_ESR1: 1: Bus Off done interrupt enabled. 0: Bus Off done interrupt disabled. [7] ERRMSK_FAST RW Error Interrupt Mask for errors detected in the Data Phase of fast CAN FD frames ERRMSK_FAST provides a mask for the ERRINT_FAST Interrupt in CAN_ESR1: 1: ERRINT_FAST error interrupt enabled. 0: ERRINT_FAST error interrupt disabled. Address offset: 0x39 Name: CAN_ESR2_1 Reset Value: 0x00 Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 470 Ver 0.8.0 [5] IMB R Inactive Mailbox If CAN_ESR2.VPS is asserted, IMB indicates whether there is any inactive mailbox (CODE field is either 0b1000 or 0b0000): 1: If CAN_ESR2.VPS is asserted, there is at least one inactive mailbox. CAN_ESR2.LPTM content is the number of the first one. 0: If CAN_ESR2.VPS is asserted, CAN_ESR2.LPTM is not an inactive mailbox. IMB is asserted in the following cases: During arbitration, if a CAN_ESR2.LPTM is found and it is inactive. If CAN_ESR2.MB is not asserted and a frame is transmitted successfully. IMB is always cleared at start of arbitration. Note: If an MB is successfully transmitted and CAN_ESR2.IMB=0 (no inactive mailbox), then CAN_ESR2.VPS and CAN_ESR2.IMB are asserted and the index related to the MB just transmitted is loaded into CAN_ESR2.LPTM. [6] VPS R Valid Priority Status – Indicates whether CAN_ESR2.IMB and CAN_ESR2.LPTM contents are currently valid or not: 1: Contents of IMB and LPTM are valid. 0: Contents of IMB and LPTM are invalid. VPS is asserted upon every complete Tx arbitration process unless the CPU writes to the C/S word of a mailbox that has already been scanned (is behind Tx Arbitration Pointer during the Tx arbitration process). If there is no inactive mailbox and only one Tx mailbox that is being transmitted, then VPS is not asserted. VPS is negated upon the start of every Tx arbitration process or upon a write to the C/S word of any mailbox. Note: VPS is not affected by any CPU write into the C/S of an MB that is blocked by the abort mechanism. When CAN_MCR.AEN is asserted, the abort code write into the C/S of an MB that is being transmitted (pending abort), or any write attempt into a Tx MB with CAN_IFLAG set is blocked. [7] TWAMSK RW Timer Wraparound Interrupt Mask – Provides a mask for the Timer Wraparound interrupt (CAN_ESR2.TWAINT): 1: Timer Wraparound interrupt enabled. 0: Timer Wraparound interrupt disabled. Address offset: 0x3a Name: CAN_ESR2_2 Reset Value: 0x00 Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 471 Ver 0.8.0 [6:0] LPTM R Lowest Priority Tx Mailbox If CAN_ESR2.VPS is asserted, LPTM indicates the lowest number inactive mailbox (see the CAN_ESR2.IMB bit description). If there is no inactive mailbox, then the mailbox indicated depends on the CAN_CTRL1.LBUF bit value: If CAN_CTRL1.LBUF is negated, the mailbox indicated is the one that has the greatest arbitration value. If CAN_CTRL1.LBUF is asserted, the mailbox indicated is the highest number active Tx mailbox. If a Tx mailbox is being transmitted, it is not considered in LPTM calculation. If CAN_ESR2.IMB is not asserted and a frame is transmitted successfully, LPTM is updated with its mailbox number." Address offset: 0x3b Name: CAN_ESR2_3 Reset Value: 0x00 [7] TWAINT W1C Timer Wraparound Interrupt Flag: 1: The internal timer has wrapped around from 65535 to 0. 0: No such occurrence. If the corresponding mask bit (CAN_ESR2.TWAMSK) is set, an interrupt is generated to the CPU. TWAINT is cleared by writing 1 to it. Writing 0 has no effect. Address offset: 0x44 Name: CAN_CRCR_0 Reset Value: 0x00 [7:0] TXCRC[7:0] R Transmitted CRC Value – Indicates the CRC value of the last transmitted message for non-FD frames. Address offset: 0x45 Name: CAN_CRCR_1 Reset Value: 0x00 [6:0] TXCRC[14:8] R - Address offset: 0x46 Name: CAN_CRCR_2 Reset Value: 0x00 Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 472 Ver 0.8.0 [6:0] MBCRC R CRC Mailbox – Indicates the number of the mailbox corresponding to the value in the CAN_CRCR.TXCRC field. Address offset: 0x48 Name: CAN_RXFGMASK_0 Reset Value: 0x00 [7:0] FGM[7:0] RW Legacy Rx FIFO Global Mask Bits These bits mask the ID Filter Table elements bits in a perfect alignment: 1: The corresponding bit in the filter is checked. 0: The corresponding bit in the filter is “don’t care”. Address offset: 0x49 Name: CAN_RXFGMASK_1 Reset Value: 0x00 [7:0] FGM[15:8] RW - Address offset: 0x4a Name: CAN_RXFGMASK_2 Reset Value: 0x00 Address offset: 0x4b Name: CAN_RXFGMASK_3 Reset Value: 0x00 Address offset: 0x4c Name: CAN_RXFIR_0 Reset Value: 0x00 [7:0] IDHIT[7:0] R Identifier Acceptance Filter Hit Indicator – Indicates which Identifier Acceptance Filter was hit by the received message that is in the output of the Legacy Rx FIFO. If multiple filters match the incoming message ID, the first matching IDAF found (lowest number) by the matching process is indicated. IDHIT is valid only when CAN_IFLAG1.BUF5I is asserted. Address offset: 0x4d Name: CAN_RXFIR_1 Reset Value: 0x00 Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 473 Ver 0.8.0 [0] FGM[8] R - Address offset: 0x50 Name: CAN_CBT_0 Reset Value: 0x00 [4:0] EPSEG2 RW Extended Phase Segment 2 When CAN_CBT.BTF is asserted, EPSEG2 defines the length of Phase Segment 2 in the bit time. EPSEG2 extends the CAN_CTRL1.PSEG2 value range. Phase Buffer Segment 1 = (EPSEG2 + 1) × Time-Quanta Time-Quantum = one Sclock period When CAN_CBT.BTF is negated, EPSEG2 has no effect. EPSEG2 can be written only in Freeze mode because it is blocked by hardware in other modes. [7:5] EPSEG1[2:0] RW Extended Phase Segment 1 When CAN_CBT.BTF is asserted, EPSEG1 defines the length of Phase Segment 1 in the bit time. EPSEG1 extends the CAN_CTRL1.PSEG1 value range. Phase Buffer Segment 1 = (EPSEG1 + 1) × Time-Quanta Time-Quantum = one Sclock period When CAN_CBT.BTF is negated, EPSEG1 has no effect. EPSEG1 can be written only in Freeze mode because it is blocked by hardware in other modes. Address offset: 0x51 Name: CAN_CBT_1 Reset Value: 0x00 [1:0] EPSEG1[4:3] RW Extended Propagation Segment When CAN_CBT.BTF is asserted, EPROPSEG defines the length of the Propagation Segment in the bit time. EPROPSEG extends the CAN_CTRL1.PROPSEG value range. Propagation Segment Time = (EPROPSEG + 1) × Time-Quanta Time-Quantum = one Sclock period When CAN_CBT.BTF is negated, EPROPSEG has no effect. EPROPSEG can be written only in Freeze mode because it is blocked by hardware in other modes. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 474 Ver 0.8.0 [7:2] EPROPSEG RW Extended Propagation Segment When CAN_CBT.BTF is asserted, EPROPSEG defines the length of the Propagation Segment in the bit time. EPROPSEG extends the CAN_CTRL1.PROPSEG value range. Propagation Segment Time = (EPROPSEG + 1) × Time-Quanta Time-Quantum = one Sclock period When CAN_CBT.BTF is negated, EPROPSEG has no effect. EPROPSEG can be written only in Freeze mode because it is blocked by hardware in other modes. Address offset: 0x52 Name: CAN_CBT_2 Reset Value: 0x00 [4:0] ERJW RW Extended Resync Jump Width When CAN_CBT.BTF is asserted, ERJW defines the maximum number of time quanta that a bit time can be changed by one re-synchronization. ERJW extends the CAN_CTRL1.RJW value range. Resync Jump Width = ERJW + 1 One time quantum is equal to the Sclock period. When CAN_CBT.BTF is negated, ERJW has no effect. ERJW can be written only in Freeze mode because it is blocked by hardware in other modes. [7:5] EPRESDIV [2:0] RW Extended Prescaler Division Factor When CAN_CBT.BTF is asserted, EPRESDIV defines the ratio between the PE clock frequency and the Serial Clock (Sclock) frequency. EPRESDIV extends the CAN_CTRL1.PRESDIV value range. Sclock frequency = PE clock frequency / (EPRESDIV + 1) The Sclock period defines the time quantum of the CAN protocol. For the reset value, the Sclock frequency is equal to the PE clock frequency. When CAN_CBT.BTF is negated, EPRESDIV has no effect. EPRESDIV can be written only in Freeze mode because it is blocked by hardware in other modes. Address offset: 0x53 Name: CAN_CBT_3 Reset Value: 0x00 [6:0] EPRESDIV[9:3] RW - Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 475 Ver 0.8.0 [7] BTF RW Bit Timing Format Enable – Enables the use of extended CAN bit timing fields EPRESDIV, EPROPSEG, EPSEG1, EPSEG2, and ERJW, replacing the CAN bit timing variables defined in CAN_CTRL1: 1: Extended bit time definitions enabled. 0: Extended bit time definitions disabled. BTF can be written in Freeze mode only. Address offset: 0x68 Name: CAN_IMASK4_0 Reset Value: 0x00 [7:0] BUF127TO96M [7:0] RW Buffer MB i Mask Each bit enables or disables the corresponding CAN Message Buffer Interrupt for MB127 to MB96: 1: The corresponding buffer interrupt is enabled. 0: The corresponding buffer interrupt is disabled. When CAN FD is enabled, the MB range is defined according to the MBDSRn bit fields of the CAN_FDCTRL register. Note: Setting or clearing a bit in CAN_IMASK4 can assert or negate an interrupt request if the corresponding CAN_IFLAG4 bit is set. Address offset: 0x69 Name: CAN_IMASK4_1 Reset Value: 0x00 [7:0] BUF127TO96M [15:8] RW - Address offset: 0x6a Name: CAN_IMASK4_2 Reset Value: 0x00 [7:0] BUF127TO96M [23:16] RW - Address offset: 0x6b Name: CAN_IMASK4_3 Reset Value: 0x00 [7:0] BUF127TO96M [31:24] RW - Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 476 Ver 0.8.0 Address offset: 0x6c Name: CAN_IMASK3_0 Reset Value: 0x00 [7:0] BUF95TO64M [7:0] RW Buffer MB i Mask Each bit enables or disables the corresponding CAN Message Buffer Interrupt for MB95 to MB64: 1: The corresponding buffer interrupt is enabled. 0: The corresponding buffer interrupt is disabled. When CAN FD is enabled, the MB range is defined according to the MBDSRn bit fields of the CAN_FDCTRL register. Note: Setting or clearing a bit in CAN_IMASK3 can assert or negate an interrupt request if the corresponding CAN_IFLAG3 bit is set. Address offset: 0x6d Name: CAN_IMASK3_1 Reset Value: 0x00 [7:0] BUF95TO64M [15:8] RW - Address offset: 0x6e Name: CAN_IMASK3_2 Reset Value: 0x00 [7:0] BUF95TO64M [23:16] RW - Address offset: 0x6f Name: CAN_IMASK3_3 Reset Value: 0x00 [7:0] BUF95TO64M [31:24] RW - Address offset: 0x70 Name: CAN_IFLAG4_0 Reset Value: 0x00 Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 477 Ver 0.8.0 [7:0] BUF127TO96I [7:0] W1C Buffer MB i Interrupt Each bit flags the corresponding CAN Message Buffer Interrupt for MB127 to MB96: 1: The corresponding buffer has successfully completed transmission or reception. 0: The corresponding buffer has no occurrence of successfully completed transmission or reception. When CAN FD is enabled, the MB range is defined according to the MBDSRn bit fields of the CAN_FDCTRL register. Address offset: 0x71 Name: CAN_IFLAG4_1 Reset Value: 0x00 [7:0] BUF127TO96I [15:8] W1C - Address offset: 0x72 Name: CAN_IFLAG4_2 Reset Value: 0x00 [7:0] BUF127TO96I [23:16] W1C - Address offset: 0x73 Name: CAN_IFLAG4_3 Reset Value: 0x00 [7:0] BUF127TO96I [31:24] W1C - Address offset: 0x74 Name: CAN_IFLAG3_0 Reset Value: 0x00 [7:0] BUF95TO64I [7:0] W1C Buffer MB i Interrupt Each bit flags the corresponding CAN Message Buffer Interrupt for MB95 to MB64: 1: The corresponding buffer has successfully completed transmission or reception. 0: The corresponding buffer has no occurrence of successfully completed transmission or reception. When CAN FD is enabled, the MB range is defined according to the MBDSRn bit fields of the CAN_FDCTRL register. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 478 Ver 0.8.0 Address offset: 0x75 Name: CAN_IFLAG3_1 Reset Value: 0x00 [7:0] BUF95TO64I [15:8] W1C - Address offset: 0x76 Name: CAN_IFLAG3_2 Reset Value: 0x00 [7:0] BUF95TO64I [23:16] W1C - Address offset: 0x77 Name: CAN_IFLAG3_3 Reset Value: 0x00 [7:0] BUF95TO64I [31:24] W1C - Address offset: 0xb00 Name: CAN_CTRL1_PN_0 Reset Value: 0x00 [1:0] FCS RW Filtering Combination Selection – Selects the filtering criteria to be applied when CAN is under Pretended Networking mode: 00: Message ID filtering only. 01: Message ID filtering and payload filtering. 10: Message ID filtering occurring a specified number of times. 11: Message ID filtering and payload filtering a specified number of times. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 479 Ver 0.8.0 [3:2] IDFS RW ID Filtering Selection – Selects the level of ID filtering to be applied when CAN is under Pretended Networking mode: 00: Match upon a ID contents against an exact target value. 01: Match upon a ID value greater than or equal to a specified target value. 10: Match upon a ID value smaller than or equal to a specified target value. 11: Match upon a ID value inside a range, greater than or equal to a specified lower limit, and smaller than or equal to a specified upper limit. In ID filtering, the IDE and RTR bits are also considered as part of the reception filter if the IDE_MSK and RTR_MSK bits in the CAN_FLT_ID2_IDMASK register are set. [5:4] PLFS RW Payload Filtering Selection – Selects the level of payload filtering to be applied when CAN is under Pretended Networking mode: 00: Match upon a payload contents against an exact target value. 01: Match upon a payload value greater than or equal to a specified target value. 10: Match upon a payload value smaller than or equal to a specified target value. 11: Match upon a payload value inside a range, greater than or equal to a specified lower limit, and smaller than or equal to a specified upper limit. Filtering does not accept remote messages (RTR=1) when payload filtering is active. Address offset: 0xb01 Name: CAN_CTRL1_PN_1 Reset Value: 0x01 [7:0] NMATCH RW Number of Messages Matching the Same Filtering Criteria NMATCH defines the number of times a given message must match the predefined filtering criteria for ID and/or PL before generating a wakeup event. This quantity can be configured in the 1 to 255 range by using values from 0×01 to 0xFF, respectively: 00000001: Received message must match the predefined filtering criteria for ID and/or PL once before generating a wakeup event. 00000010: Received message must match the predefined filtering criteria for ID and/or PL twice before generating a wakeup event. 11111111: Received message must match the predefined filtering criteria for ID and/ or PL 255 times before generating a wakeup event. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 480 Ver 0.8.0 Address offset: 0xb02 Name: CAN_CTRL1_PN_2 Reset Value: 0x00 [0] WUMF_MSK RW Wake Up by Match Flag Mask Bit – Masks the generation of a wakeup event originated by a successful filtered Rx message: 1: Wakeup match event is enabled. 0: Wakeup match event is disabled. [1] WTOF_MSK RW Wake Up by Timeout Flag Mask Bit – Masks the generation of a wakeup event originated by a timeout: 1: Timeout wakeup event is enabled. 0: Timeout wakeup event is disabled. Address offset: 0xb04 Name: CAN_CTRL2_PN_0 Reset Value: 0x00 [7:0] MATCHTO [7:0] RW Timeout for No Message Matching the Filtering Criteria MATCHTO defines a timeout value that generates a wakeup event if CAN_MCR.PNET_EN is asserted. If the timeout counter reaches the target value when the CAN is under Pretended Networking mode, a wakeup event is generated. The timeout limit can be configured from 1 to 65535 to control an internal 16-bit up-count timer to produce a trigger upon reaching this configured value. The internal timer is incremented based on periodic time ticks, of which the period is 64 times the CAN Bit Time unit. When MATCHTO is 0×0000, the timeout is disabled. Address offset: 0xb05 Name: CAN_CTRL2_PN_1 Reset Value: 0x00 [7:0] MATCHTO [15:8] RW - Address offset: 0xb09 Name: CAN_WU_MTC_1 Reset Value: 0x00 Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 481 Ver 0.8.0 [7:0] MCOUNTER R Number of Matches while in Pretended Networking MCOUNTER reports the number of times a given message has matched the predefined filtering criteria for ID and/or PL before a wakeup event. MCOUNTER is reset by the CAN when it enters in Pretended Networking mode, and is not affected by soft reset. Address offset: 0xb0a Name: CAN_WU_MTC_2 Reset Value: 0x00 [0] WUMF W1C Wake Up by Match Flag Bit – Indicates whether the CAN has detected a matching Rx incoming message that passed the filtering criteria specified in CAN_CTRL1_PN: 1: Wakeup by match event detected. 0: No wakeup by match event detected. WUMF generates a wakeup event if CAN_CTRL1_PN.WUMF_MSK is asserted. [1] WTOF W1C Wake Up by Timeout Flag Bit – Indicates whether the CAN has detected a timeout event during a time interval defined by CAN_CTRL2_PN.MATCHTO: 1: Wakeup by timeout event detected. 0: No wakeup by timeout event detected. WTOF generates a wakeup event if CAN_CTRL1_PN.WTOF_MSK is asserted. Address offset: 0xb0c Name: CAN_FLT_ID1_0 Reset Value: 0x00 [7:0] FLT_ID1[7:0] RW ID Filter 1 for Pretended Networking Filtering – Defines either the 29 bits of an extended frame format, considering all bits, or the 11 bits of a standard frame format, considering just the 11 leftmost bits. Address offset: 0xb0d Name: CAN_FLT_ID1_1 Reset Value: 0x00 [7:0] FLT_ID1[15:8] RW - Address offset: 0xb0e Name: CAN_FLT_ID1_2 Reset Value: 0x00 Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 482 Ver 0.8.0 [7:0] FLT_ID1 [23:16] RW - Address offset: 0xb0f Name: CAN_FLT_ID1_3 Reset Value: 0x00 [4:0] FLT_ID1 [28:24] RW - [5] FLT_RTR RW Remote Transmission Request Filter – Identifies whether the frame is remote or not: 1: Accept remote frame. 0: Reject remote frame (accept data frame). FLT_RTR is used as part of the ID reception filter. [6] FLT_IDE RW ID Extended Filter – Identifies whether the frame format is standard or extended: 1: Accept extended frame format. 0: Accept standard frame format. FLT_IDE is used as part of the ID reception filter. Address offset: 0xb10 Name: CAN_FLT_DLC_0 Reset Value: 0x08 [3:0] FLT_DLC_HI RW Upper Limit for Length of Data Bytes Filter – Specifies the upper limit for the number of data bytes considered valid for payload comparison. FLT_DLC_HI is used as part of payload reception filter. Address offset: 0xb12 Name: CAN_FLT_DLC_2 Reset Value: 0x08 [3:0] FLT_DLC_LO RW Lower Limit for Length of Data Bytes Filter – Specifies the lower limit for the number of data bytes considered valid for payload comparison. FLT_DLC_LO is used as part of payload reception filter. Address offset: 0xb14 Name: CAN_PL1_LO_0 Reset Value: 0x00 Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 483 Ver 0.8.0 [7:0] DATA_BYTE_3 RW Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 3. Address offset: 0xb15 Name: CAN_PL1_LO_1 Reset Value: 0x00 [7:0] DATA_BYTE_2 RW Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 2. Address offset: 0xb16 Name: CAN_PL1_LO_2 Reset Value: 0x00 [7:0] DATA_BYTE_1 RW Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 1. Address offset: 0xb17 Name: CAN_PL1_LO_3 Reset Value: 0x00 [7:0] DATA_BYTE_0 RW Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 0. Address offset: 0xb18 Name: CAN_PL1_HI_0 Reset Value: 0x00 [7:0] DATA_BYTE_7 RW Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 7. Address offset: 0xb19 Name: CAN_PL1_HI_1 Reset Value: 0x00 [7:0] DATA_BYTE_6 RW Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 6. Address offset: 0xb1a Name: CAN_PL1_HI_2 Reset Value: 0x00 [7:0] DATA_BYTE_5 RW Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 5. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 484 Ver 0.8.0 Address offset: 0xb1b Name: CAN_PL1_HI_3 Reset Value: 0x00 [7:0] DATA_BYTE_4 RW Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to data byte 4. Address offset: 0xb1c Name: CAN_FLT_ID2_IDMASK_0 Reset Value: 0x00 [7:0] FLT_ID2_IDMA SK[7:0] RW ID Filter 2 for Pretended Networking Filtering / ID Mask Bits for Pretended Networking ID Filtering FLT_ID2_IDMASK is used as FLT_ID2 in range of ID filtering to define the ID filter value in either: Extended frame format (29 bits), considering the FLT_ID2[28:0], or Standard frame format (11 bits), considering the FLT_ID2[28:18]. Other bits in the [17:0] range have no meaning. FLT_ID2_IDMASK can also be used as IDMASK in exact ID filtering to define the mask value for either: Extended frame format (29 bits), considering the IDMASK[28:0], or Standard frame format (11 bits), considering the IDMASK[28:18]. Other bits in the [17:0] range have no meaning. Address offset: 0xb1d Name: CAN_FLT_ID2_IDMASK_1 Reset Value: 0x00 [7:0] FLT_ID2_IDMA SK[15:8] RW - Address offset: 0xb1e Name: CAN_FLT_ID2_IDMASK_2 Reset Value: 0x00 [7:0] FLT_ID2_IDMA SK[23:16] RW - Address offset: 0xb1f Name: CAN_FLT_ID2_IDMASK_3 Reset Value: 0x00 Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 485 Ver 0.8.0 [4:0] FLT_ID2_IDMA SK[28:24] RW - [5] RTR_MSK RW Remote Transmission Request Mask Bit – Indicates whether the frame type (data/ remote) is part of the ID reception filter: 1: The corresponding bit in the filter is checked. 0: The corresponding bit in the filter is “don’t care”. [6] IDE_MSK RW ID Extended Mask Bit – Indicates whether the frame format (standard/extended) is used as part of the ID reception filter: 1: The corresponding bit in the filter is checked. 0: The corresponding bit in the filter is “don’t care”. Address offset: 0xb20 Name: CAN_PL2_PLMASK_LO_0 Reset Value: 0x00 [7:0] DATA_BYTE_3 RW Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to data byte 3. Address offset: 0xb21 Name: CAN_PL2_PLMASK_LO_1 Reset Value: 0x00 [7:0] DATA_BYTE_2 RW Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to data byte 2. Address offset: 0xb22 Name: CAN_PL2_PLMASK_LO_2 Reset Value: 0x00 [7:0] DATA_BYTE_1 RW Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to data byte 1. Address offset: 0xb23 Name: CAN_PL2_PLMASK_LO_3 Reset Value: 0x00 [7:0] DATA_BYTE_0 RW Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to data byte 0. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 486 Ver 0.8.0 Address offset: 0xb24 Name: CAN_PL2_PLMASK_HI_0 Reset Value: 0x00 [7:0] DATA_BYTE_7 RW Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to data byte 7. Address offset: 0xb25 Name: CAN_PL2_PLMASK_HI_1 Reset Value: 0x00 [7:0] DATA_BYTE_6 RW Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to data byte 6. Address offset: 0xb26 Name: CAN_PL2_PLMASK_HI_2 Reset Value: 0x00 [7:0] DATA_BYTE_5 RW Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to data byte 5. Address offset: 0xb27 Name: CAN_PL2_PLMASK_HI_3 Reset Value: 0x00 [7:0] DATA_BYTE_4 RW Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to data byte 4. Address offset: 0xb42 Name: CAN_WMB0_CS Reset Value: 0x00 [3:0] DLC R Length of Data in Bytes – Length (in bytes) of the Rx data received when CAN is in Pretended Networking mode. DLC is written by the CAN module, copied from the DLC (Data Length Code) field of the received frame. The DLC field indicates which data bytes are valid. [4] RTR R Remote Transmission Request Bit – Identifies whether the frame is remote or not: 1: Frame is a remote frame. 0: Frame is data frame (not remote). Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 487 Ver 0.8.0 [5] IDE R ID Extended Bit – Identifies whether the frame format is standard or extended: 1: Frame format is extended. 0: Frame format is standard. [6] SRR R Substitute Remote Request – Can be received either recessive or dominant. Address offset: 0xb44 Name: CAN_WMB0_ID_0 Reset Value: 0x00 [7:0] ID[7:0] R Received ID under Pretended Networking Mode – Stores the received ID as either: The 29 bits of the extended frame format (considering the ID[28:0] field), or The 11 bits of the standard frame format (considering the ID[28:18] field only. The remaining bits in the ID[17:0] range have no meaning. Address offset: 0xb45 Name: CAN_WMB0_ID_1 Reset Value: 0x00 [7:0] ID[15:8] R - Address offset: 0xb46 Name: CAN_WMB0_ID_2 Reset Value: 0x00 Address offset: 0xb47 Name: CAN_WMB0_ID_3 Reset Value: 0x00 Address offset: 0xb48 Name: CAN_WMB0_D03_0 Reset Value: 0x00 [7:0] DATA_BYTE_3 R Received payload corresponding to data byte 3 under Pretended Networking mode. Address offset: 0xb49 Name: CAN_WMB0_D03_1 Reset Value: 0x00 Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 488 Ver 0.8.0 [7:0] DATA_BYTE_2 R Received payload corresponding to data byte 2 under Pretended Networking mode. Address offset: 0xb4a Name: CAN_WMB0_D03_2 Reset Value: 0x00 [7:0] DATA_BYTE_1 R Received payload corresponding to data byte 1 under Pretended Networking mode. Address offset: 0xb4b Name: CAN_WMB0_D03_3 Reset Value: 0x00 [7:0] DATA_BYTE_0 R Received payload corresponding to data byte 0 under Pretended Networking mode. Address offset: 0xb4c Name: CAN_WMB0_D47_0 Reset Value: 0x00 [7:0] DATA_BYTE_7 R Received payload corresponding to data byte 7 under Pretended Networking mode. Address offset: 0xb4d Name: CAN_WMB0_D47_1 Reset Value: 0x00 [7:0] DATA_BYTE_6 R Received payload corresponding to data byte 6 under Pretended Networking mode. Address offset: 0xb4e Name: CAN_WMB0_D47_2 Reset Value: 0x00 [7:0] DATA_BYTE_5 R Received payload corresponding to data byte 5 under Pretended Networking mode. Address offset: 0xb4f Name: CAN_WMB0_D47_3 Reset Value: 0x00 [7:0] DATA_BYTE_4 R Received payload corresponding to data byte 4 under Pretended Networking mode. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 489 Ver 0.8.0 Address offset: 0xb52 Name: CAN_WMB1_CS Reset Value: 0x00 [3:0] DLC R - [4] RTR R - [5] IDE R - [6] SRR R - Address offset: 0xb54 Name: CAN_WMB1_ID_0 Reset Value: 0x00 [7:0] ID[7:0] R - Address offset: 0xb55 Name: CAN_WMB1_ID_1 Reset Value: 0x00 [7:0] ID[15:8] R - Address offset: 0xb56 Name: CAN_WMB1_ID_2 Reset Value: 0x00 Address offset: 0xb57 Name: CAN_WMB1_ID_0 Reset Value: 0x00 Address offset: 0xb58 Name: CAN_WMB1_D03_0 Reset Value: 0x00 [7:0] DATA_BYTE_3 R Received payload corresponding to data byte 3 under Pretended Networking mode. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 490 Ver 0.8.0 Address offset: 0xb59 Name: CAN_WMB1_D03_1 Reset Value: 0x00 [7:0] DATA_BYTE_2 R Received payload corresponding to data byte 2 under Pretended Networking mode. Address offset: 0xb5a Name: CAN_WMB1_D03_2 Reset Value: 0x00 [7:0] DATA_BYTE_1 R Received payload corresponding to data byte 1 under Pretended Networking mode. Address offset: 0xb5b Name: CAN_WMB1_D03_3 Reset Value: 0x00 [7:0] DATA_BYTE_0 R Received payload corresponding to data byte 0 under Pretended Networking mode. Address offset: 0xb5c Name: CAN_WMB1_D47_0 Reset Value: 0x00 [7:0] DATA_BYTE_7 R Received payload corresponding to data byte 7 under Pretended Networking mode. Address offset: 0xb5d Name: CAN_WMB1_D47_1 Reset Value: 0x00 [7:0] DATA_BYTE_6 R Received payload corresponding to data byte 6 under Pretended Networking mode. Address offset: 0xb5e Name: CAN_WMB1_D47_2 Reset Value: 0x00 [7:0] DATA_BYTE_5 R Received payload corresponding to data byte 5 under Pretended Networking mode. Address offset: 0xb5f Name: CAN_WMB1_D47_3 Reset Value: 0x00 Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 491 Ver 0.8.0 [7:0] DATA_BYTE_4 R Received payload corresponding to data byte 4 under Pretended Networking mode. Address offset: 0xb62 Name: CAN_WMB2_CS Reset Value: 0x00 [3:0] DLC R - [4] RTR R - [5] IDE R - [6] SRR R - Address offset: 0xb64 Name: CAN_WMB2_ID_0 Reset Value: 0x00 [7:0] ID[7:0] R - Address offset: 0xb65 Name: CAN_WMB2_ID_1 Reset Value: 0x00 [7:0] ID[15:8] R - Address offset: 0xb66 Name: CAN_WMB2_ID_2 Reset Value: 0x00 Address offset: 0xb67 Name: CAN_WMB2_ID_0 Reset Value: 0x00 Address offset: 0xb68 Name: CAN_WMB2_D03_0 Reset Value: 0x00 [7:0] DATA_BYTE_3 R Received payload corresponding to data byte 3 under Pretended Networking mode. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 492 Ver 0.8.0 Address offset: 0xb69 Name: CAN_WMB2_D03_1 Reset Value: 0x00 [7:0] DATA_BYTE_2 R Received payload corresponding to data byte 2 under Pretended Networking mode. Address offset: 0xb6a Name: CAN_WMB2_D03_2 Reset Value: 0x00 [7:0] DATA_BYTE_1 R Received payload corresponding to data byte 1 under Pretended Networking mode. Address offset: 0xb6b Name: CAN_WMB2_D03_3 Reset Value: 0x00 [7:0] DATA_BYTE_0 R Received payload corresponding to data byte 0 under Pretended Networking mode. Address offset: 0xb6c Name: CAN_WMB2_D47_0 Reset Value: 0x00 [7:0] DATA_BYTE_7 R Received payload corresponding to data byte 7 under Pretended Networking mode. Address offset: 0xb6d Name: CAN_WMB2_D47_1 Reset Value: 0x00 [7:0] DATA_BYTE_6 R Received payload corresponding to data byte 6 under Pretended Networking mode. Address offset: 0xb6e Name: CAN_WMB2_D47_2 Reset Value: 0x00 [7:0] DATA_BYTE_5 R Received payload corresponding to data byte 5 under Pretended Networking mode. Address offset: 0xb6f Name: CAN_WMB2_D47_3 Reset Value: 0x00 Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 493 Ver 0.8.0 [7:0] DATA_BYTE_4 R Received payload corresponding to data byte 4 under Pretended Networking mode. Address offset: 0xb72 Name: CAN_WMB3_CS Reset Value: 0x00 [3:0] DLC R - [4] RTR R - [5] IDE R - [6] SRR R - Address offset: 0xb74 Name: CAN_WMB3_ID_0 Reset Value: 0x00 [7:0] ID[7:0] R - Address offset: 0xb75 Name: CAN_WMB3_ID_1 Reset Value: 0x00 [7:0] ID[15:8] R - Address offset: 0xb76 Name: CAN_WMB3_ID_2 Reset Value: 0x00 Address offset: 0xb77 Name: CAN_WMB3_ID_0 Reset Value: 0x00 Address offset: 0xb78 Name: CAN_WMB3_D03_0 Reset Value: 0x00 [7:0] DATA_BYTE_3 R Received payload corresponding to data byte 3 under Pretended Networking mode. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 494 Ver 0.8.0 Address offset: 0xb79 Name: CAN_WMB3_D03_1 Reset Value: 0x00 [7:0] DATA_BYTE_2 R Received payload corresponding to data byte 2 under Pretended Networking mode. Address offset: 0xb7a Name: CAN_WMB3_D03_2 Reset Value: 0x00 [7:0] DATA_BYTE_1 R Received payload corresponding to data byte 1 under Pretended Networking mode. Address offset: 0xb7b Name: CAN_WMB3_D03_3 Reset Value: 0x00 [7:0] DATA_BYTE_0 R Received payload corresponding to data byte 0 under Pretended Networking mode. Address offset: 0xb7c Name: CAN_WMB3_D47_0 Reset Value: 0x00 [7:0] DATA_BYTE_7 R Received payload corresponding to data byte 7 under Pretended Networking mode. Address offset: 0xb7d Name: CAN_WMB3_D47_1 Reset Value: 0x00 [7:0] DATA_BYTE_6 R Received payload corresponding to data byte 6 under Pretended Networking mode. Address offset: 0xb7e Name: CAN_WMB3_D47_2 Reset Value: 0x00 [7:0] DATA_BYTE_5 R Received payload corresponding to data byte 5 under Pretended Networking mode. Address offset: 0xb7f Name: CAN_WMB3_D47_3 Reset Value: 0x00 Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 495 Ver 0.8.0 [7:0] DATA_BYTE_4 R Received payload corresponding to data byte 4 under Pretended Networking mode. Address offset: 0xbf0 Name: CAN_EPRS_0 Reset Value: 0x00 [7:0] ENPRESDIV [7:0] RW Extended Nominal Phase Prescaler Division Factor ENPRESDIV defines the ratio between the PE clock frequency and the Serial Clock (Sclock) frequency for the nominal bit rate when CAN_CTRL2.BTE is set. The Sclock period defines the time quantum of the CAN protocol for the nominal phase. Sclock frequency = PE clock frequency / (ENPRESDIV + 1). Address offset: 0xbf1 Name: CAN_EPRS_1 Reset Value: 0x00 [1:0] ENPRESDIV [9:8] RW - Address offset: 0xbf2 Name: CAN_EPRS_2 Reset Value: 0x00 [7:0] EDPRESDIV [7:0] RW Extended Data Phase Prescaler Division Factor EDPRESDIV defines the ratio between the PE clock frequency and the Serial Clock (Sclock) frequency in the data bit rate portion of a CAN FD message when CAN_CTRL2.BTE is set. The Sclock period defines the time quantum of the CAN FD protocol for the data bit rate. Sclock frequency = PE clock frequency / (EDPRESDIV + 1). Note: To minimize errors when processing FD frames, use the same value for ENPRESDIV and EDPRESDIV. Address offset: 0xbf3 Name: CAN_EPRS_3 Reset Value: 0x00 [1:0] ENPRESDIV [9:8] RW - Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 496 Ver 0.8.0 Address offset: 0xbf4 Name: CAN_ENCBT_0 Reset Value: 0x00 [7:0] NTSEG1 RW Nominal Time Segment 1 NTSEG1 defines the length of Time Segment 1 in the nominal bit time when CAN_CTRL2.BTE = 1. When CAN_CTRL2.BTE = 0, NTSEG1 has no effect. Nominal Time Segment 1 = (NTSEG1 + 1) × Time-Quanta Time-Quantum = one Sclock period Address offset: 0xbf5 Name: CAN_ENCBT_1 Reset Value: 0x00 [7:4] NTSEG2[3:0] RW Nominal Time Segment 2 NTSEG2 defines the length of Time Segment 2 in the nominal bit time when CAN_CTRL2.BTE = 1. When CAN_CTRL2.BTE = 0, NTSEG2 has no effect. Nominal Time Segment 2 = (NTSEG2 + 1) × Time-Quanta Time-Quantum = one Sclock period Address offset: 0xbf6 Name: CAN_ENCBT_2 Reset Value: 0x00 [2:0] NTSEG2[6:4] RW - [7:6] NTSEG2[6:4] RW Nominal Resynchronization Jump Width NRJW defines the maximum number of time quanta that a nominal bit time can be changed by one resynchronization when CAN_CTRL2.BTE = 1. When CAN_CTRL2.BTE = 0, NRJW has no effect. One time quantum is equal to one Sclock period. Nominal Resynchronization Jump Width = NRJW + 1. Address offset: 0xbf7 Name: CAN_ENCBT_3 Reset Value: 0x00 [4:0] NRJW[6:2] RW - Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 497 Ver 0.8.0 Address offset: 0xbf8 Name: CAN_EDCBT_0 Reset Value: 0x00 [4:0] DTSEG1 RW Data Phase Time Segment 1 DTSEG1 defines the length of Time Segment 1 in the data phase bit time when CAN_CTRL2.BTE = 1. When CAN_CTRL2.BTE = 0, DTSEG1 has no effect. Data Phase Time Segment 1 = (DTSEG1 + 1) × Time-Quanta Time-Quantum = one Sclock period Address offset: 0xbf9 Name: CAN_EDCBT_1 Reset Value: 0x00 [7:4] DTSEG2 RW Data Phase Time Segment 2 DTSEG2 defines the length of Time Segment 2 in the data phase bit time when CAN_CTRL2.BTE = 1. When CAN_CTRL2.BTE = 0, DTSEG2 has no effect. Data Phase Time Segment 2 = (DTSEG2 + 1) × Time-Quanta Time-Quantum = one Sclock period Address offset: 0xbfa Name: CAN_EDCBT_2 Reset Value: 0x00 [7:6] DRJW[1:0] RW Data Phase Resynchronization Jump Width DRJW defines the maximum number of time quanta that a data phase bit time can be changed by one resynchronization when CAN_CTRL2.BTE = 1. When CAN_CTRL2.BTE = 0, DRJW has no effect. One time quantum is equal to one Sclock period. Data Phase Resynchronization Jump Width = DRJW + 1. Address offset: 0xbfb Name: CAN_EDCBT_3 Reset Value: 0x00 [1:0] DRJW[3:2] RW - Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 498 Ver 0.8.0 Address offset: 0xbfc Name: CAN_ETDC_0 Reset Value: 0x00 [7:0] ETDCVAL R Enhanced Transceiver Delay Compensation Value ETDCVAL contains the ETDCOFF field added to the measured value of the transceiver loop delay in the latest transmitted CAN FD frame with BRS equal to recessive. ETDCVAL is only updated by the hardware if the ETDCEN bit is set. ETDCVAL is affected by soft reset. Note: If TDMDIS is set, ETDCVAL stores ETDCOFF only. Address offset: 0xbfd Name: CAN_ETDC_1 Reset Value: 0x00 [7] ETDCFAIL W1C Transceiver Delay Compensation Fail ETDCFAIL indicates when the Transceiver Delay Compensation (TDC) mechanism is out of range, unable to compensate the transceiver’s loop delay and successfully compare the delayed received bits to the transmitted ones: 1: Measured loop delay is out of range. 0: Measured loop delay is in range. ETDCFAIL is set the first time the CAN detects the out of range condition. To clear ETDCFAIL, write 1 to it. See “Transceiver Delay Compensation”. Address offset: 0xbfe Name: CAN_ETDC_2 Reset Value: 0x00 Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 499 Ver 0.8.0 [6:0] ETDCOFF RW Enhanced Transceiver Delay Compensation Offset ETDCOFF contains the offset value to be added to the measured transceiver’s loop delay in order to define the position of the delayed comparison point when bit rate switching is active. See “Transceiver Delay Compensation” for additional details on how the loop delay measurement is performed. ETDCOFF can be written in Freeze mode only. Its value is defined in protocol engine (PE) clock periods and must be selected to be smaller than the CAN bit duration in the data phase bit rate for proper operation. ETDCOFF must not be configured as zero. Note: If CAN_CTRL2.BTE is set after a chip-level hard reset, ETCDOFF is read as 0×1. Address offset: 0xbff Name: CAN_ETDC_3 Reset Value: 0x00 [6] TDMDIS RW Transceiver Delay Measurement Disable – Disables or enables transceiver delay measurement: 1: TDC measurement is disabled. 0: TDC measurement is enabled. When TDC measurement is disabled, the secondary sample point position is determined only by the enhanced TDC offset (ETDCOFF) field. Otherwise, if TCD measurement is enabled, then the secondary sample point position is determined by the sum of the transceiver delay measurement plus the enhanced TDC offset. TDMDIS is not affected by soft reset. TDMDIS can be enabled only if CAN_CTRL2.BTE is set. [7] ETDCEN RW Transceiver Delay Compensation Enable – Enables or disables the TDC feature: 1: TDC is enabled. 0: TDC is disabled. ETDCEN can be written in Freeze mode only. Note: TDC must be disabled when Loop-Back mode is enabled (see CAN_CTRL1.LPB). Address offset: 0xc00 Name: CAN_FDCTRL_0 Reset Value: 0x00 Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 500 Ver 0.8.0 [5:0] TDCVAL RW Transceiver Delay Compensation Value TDCVAL contains the value of the transceiver loop delay measured from the transmitted EDL to R0 transition edge to the respective received one added to the TDCOFF value. This value is an integer multiple of the PE clock period. Note: If CAN_CTRL2.BTE = 1, TDCVAL is read as zero. Address offset: 0xc01 Name: CAN_FDCTRL_1 Reset Value: 0x01 [4:0] TDCOFF RW Transceiver Delay Compensation Offset TDCOFF contains the offset value to be added to the measured transceiver’s loop delay in order to define the position of the delayed comparison point when bit rate switching is active. TDCOFF can be written in Freeze mode only. Its value can be defined in PE clock periods and must be selected to be smaller than the CAN bit duration in the data bit rate for proper operation. Note: It is not recommended to use TDCOFF equal to zero. Note: If CAN_CTRL2.BTE = 1, TDCOFF is read as zero and a write operation has no effect. [6] TDCFAIL W1C Transceiver Delay Compensation Fail TDCFAIL indicates when the Transceiver Delay Compensation (TDC) mechanism is out of range, unable to compensate the transceiver’s loop delay, and successfully compare the delayed received bits to the transmitted ones: 1: Measured loop delay is out of range. 0: Measured loop delay is in range. TDCFAIL is set the first time the CAN detects the out of range condition. To clear TDCFAIL, write 1 to it. Note: If CAN_CTRL2.BTE = 1, TDCFAIL is read as zero and a write operation has no effect. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 501 Ver 0.8.0 [7] TDCEN RW Transceiver Delay Compensation Enable – Enables or disables the TDC feature: 1: TDC is enabled. 0: TDC is disabled. TDCEN can be written in Freeze mode only. Note: TDC must be disabled when Loop-Back mode is enabled (see CAN_CTRL1.LPB). Note: If CAN_CTRL2.BTE = 1, TDCEN is read as zero and a write operation has no effect. Address offset: 0xc02 Name: CAN_FDCTRL_2 Reset Value: 0x00 [1:0] MBDSR0 RW Message Buffer Data Size for Region 0 – Selects the data size for region R0 of message buffers allocated in RAM: 00: Selects 8 bytes per message buffer. 01: Selects 16 bytes per message buffer. 10: Selects 32 bytes per message buffer. 11: Selects 64 bytes per message buffer. MBDSR0 can be written in Freeze mode only. [4:3] MBDSR1 RW Message Buffer Data Size for Region 1 – Selects the data size for region R1 of message buffers allocated in RAM: 00: Selects 8 bytes per message buffer. 01: Selects 16 bytes per message buffer. 10: Selects 32 bytes per message buffer. 11: Selects 64 bytes per message buffer. MBDSR1 can be written in Freeze mode only. [7:6] MBDSR2 RW Message Buffer Data Size for Region 2 – Selects the data size for region R2 of message buffers allocated in RAM: 00: Selects 8 bytes per message buffer. 01: Selects 16 bytes per message buffer. 10: Selects 32 bytes per message buffer. 11: Selects 64 bytes per message buffer. MBDSR2 can be written in Freeze mode only. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 502 Ver 0.8.0 Address offset: 0xc03 Name: CAN_FDCTRL_3 Reset Value: 0x00 [2:1] MBDSR3 RW Message Buffer Data Size for Region 3 – Selects the data size for region R3 of message buffers allocated in RAM: 00: Selects 8 bytes per message buffer. 01: Selects 16 bytes per message buffer. 10: Selects 32 bytes per message buffer. 11: Selects 64 bytes per message buffer. MBDSR3 can be written in Freeze mode only. [7] FDRATE RW Bit Rate Switch Enable – Enables the effect of the Bit Rate Switch (BRS bit) during the data phase of Tx messages: 1: Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive. 0: Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect. The CPU can write the FDRATE bit any time. However, its effect becomes active only when the CAN bus is in the Wait for Bus Idle, Bus Idle, or Bus Off state, or when the current frame under reception or transmission reaches the interframe space. By negating FDRATE, the CPU can force all bits in CAN FD messages to be transmitted in nominal bit rate, regardless of the value of the BRS bit of the Tx MBs. Address offset: 0xc04 Name: CAN_FDCBT_0 Reset Value: 0x00 [2:0] FPSEG2 RW Fast Phase Segment 2 FPSEG2 defines the length of Phase Segment 2 in the data bit rate portion of a CAN FD message with the BRS bit set. Phase Segment 2 = (FPSEG2 + 1) × Time-Quanta Time-Quantum = one Sclock period FPSEG2 can be written only in Freeze mode because it is blocked by hardware in other modes. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 503 Ver 0.8.0 [7:5] FPSEG1 RW Fast Phase Segment 1 FPSEG1 defines the length of Phase Segment 1 in the bit time in the data bit rate portion of a CAN FD message with the BRS bit set. Phase Segment 1 = (FPSEG1 + 1) × Time-Quanta Time-Quantum = one Sclock period FPSEG1 can be written only in Freeze mode because it is blocked by hardware in other modes. Address offset: 0xc05 Name: CAN_FDCBT_1 Reset Value: 0x00 [6:2] FPROPSEG RW Fast Propagation Segment FPROPSEG defines the length of the Propagation Segment in the bit time in the data bit rate portion of a CAN FD message with the BRS bit set. Propagation Segment Time = FPROPSEG × Time-Quanta Time-Quantum = one Sclock period FPROPSEG can be written only in Freeze mode because it is blocked by hardware in other modes. Address offset: 0xc06 Name: CAN_FDCBT_2 Reset Value: 0x00 [2:0] FRJW RW Fast Resync Jump Width FRJW defines the maximum number of time quanta that a bit time can be changed by one re-synchronization in the data bit rate portion of a CAN FD message with the BRS bit set. Resync Jump Width = FRJW + 1. One time quantum is equal to the Sclock period. FRJW can be written only in Freeze mode because it is blocked by hardware in other modes. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 504 Ver 0.8.0 [7:4] FPRESDIV [3:0] RW Fast Prescaler Division Factor FPRESDIV defines the ratio between the PE clock frequency and the Serial Clock (Sclock) frequency in the data bit rate portion of a CAN FD message with the BRS bit set. The Sclock period defines the time quantum of the CAN FD protocol for the data bit rate. Sclock frequency = PE clock frequency / (FPRESDIV + 1). Note: To minimize errors when processing FD frames, use the same value for FPRESDIV and PRESDIV (in CAN_CBT or CAN_CTRL1). FPRESDIV can be written only in Freeze mode because it is blocked by hardware in other modes. Address offset: 0xc07 Name: CAN_FDCBT_3 Reset Value: 0x00 [5:0] FPRESDIV[9:4] RW - Address offset: 0xc08 Name: CAN_FDCRC_0 Reset Value: 0x00 [7:0] FD_TXCRC [7:0] R Extended Transmitted CRC value FD_TXCRC contains the CRC value calculated over the most recent transmitted message. Different CRC polynomials are used for different frame formats. A 15-bit polynomial, CRC_15, is used for all frames in CAN format. The second 17-bit polynomial, CRC_17, is used for frames in CAN FD format with a data field up to sixteen bytes long. The third 21-bit polynomial, CRC_21, is used for frames in CAN FD format with a data field longer than sixteen bytes. For CRC_15 and CRC_17, the 6 most significant bits and the 4 most significant bits are reported as zeros, respectively. For CRC_15, this register has the same content as CAN_CRCR. Address offset: 0xc09 Name: CAN_FDCRC_1 Reset Value: 0x00 [7:0] FD_TXCRC [15:8] R - Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 505 Ver 0.8.0 Address offset: 0xc0a Name: CAN_FDCRC_2 Reset Value: 0x00 [4:0] FD_TXCRC [20:16] R - Address offset: 0xc0b Name: CAN_FDCRC_3 Reset Value: 0x00 [6:0] FD_MBCRC R CRC Mailbox Number for FD_TXCRC FD_MBCRC indicates the number of the mailbox corresponding to the value in the FD_TXCRC field, for both FD and non-FD frames. FD_MBCRC reports the same information as in the CAN_CRCR.MBCRC bit field. Address offset: 0xc0c Name: CAN_ERFCR_0 Reset Value: 0x00 [4:0] ERFWM RW Enhanced Rx FIFO Watermark – Defines the minimum number of CAN messages stored in the Enhanced Rx FIFO. Minimum number of CAN messages = ERFWM + 1. When ERFWM + 1 is reached, ERFSR.ERFWMI is set. ERFWM can be written only in Freeze mode because it is blocked by hardware in other modes. Address offset: 0xc0d Name: CAN_ERFCR_1 Reset Value: 0x00 Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 506 Ver 0.8.0 [5:0] NFE RW Number of Enhanced Rx FIFO Filter Elements – Defines the total number of filter elements used during the Enhanced Rx FIFO matching process. With NEXIF = 0, the maximum number of standard ID filter elements can be determined by the following equation: Maximim Number of Standard ID Filter Elements = 2 x (NFE + 1) The maximum number of extended ID filter elements can be determined by the following equation: Maximum Number of Extended ID Filter Elements = NFE + 1 NFE can be written only in Freeze mode because it is blocked by hardware in other modes. Address offset: 0xc0e Name: CAN_ERFCR_2 Reset Value: 0x00 [6:0] NEXIF RW Number of Extended ID Filter Elements – Defines the number of extended ID filter elements used during the Enhanced Rx FIFO matching process. NEXIF must be less than or equal to NFE + 1. The number of standard ID filter elements can be determined by the following equation: Number of Standard ID Filter Elements = 2 x (NFE – NEXIF + 1) NEXIF can be written only in Freeze mode because it is blocked by hardware in other modes. Address offset: 0xc0f Name: CAN_ERFCR_3 Reset Value: 0x00 [6:2] DMALW RW DMA Last Word – Defines the last DMA address for each Enhanced Rx FIFO element. Number of 32-bit words transferred = DMALW + 1 Last FIFO Addresss = 0×2000 + DMALW x 4 DMALW must be less than or equal to 19. Values greater than 19 are reserved. DMALW can be written only in Freeze mode because it is blocked by hardware in other modes. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 507 Ver 0.8.0 [7] ERFEN RW Enhanced Rx FIFO Enable – Enables or disables the Enhanced Rx FIFO: 1: Enable Enhanced Rx FIFO. 0: Disable Enhanced Rx FIFO. ERFEN can be written only in Freeze mode because it is blocked by hardware in other modes. Note: ERFEN must not be set if CAN_MCR.RFEN is set. Address offset: 0xc13 Name: CAN_ERFIER Reset Value: 0x00 [4] ERFDAIE RW Enhanced Rx FIFO Data Available Interrupt Enable – Enables or disables the interrupt for Enhanced Rx FIFO data available (ERFSR.ERFDA): 1: Enable Enhanced Rx FIFO data available interrupt. 0: Disable Enhanced Rx FIFO data available interrupt. [5] ERFWMIIE RW Enhanced Rx FIFO Watermark Indication Interrupt Enable – Enables or disables the interrupt for Enhanced Rx FIFO watermark (ERFSR.ERFWMI): 1: Enable Enhanced Rx FIFO watermark interrupt. 0: Disable Enhanced Rx FIFO watermark interrupt. [6] ERFOVFIE RW Enhanced Rx FIFO Overflow Interrupt Enable – Enables or disables the interrupt for Enhanced Rx FIFO overflow (ERFSR.ERFOVF): 1: Enable Enhanced Rx FIFO overflow interrupt. 0: Disable Enhanced Rx FIFO overflow interrupt. [7] ERFUFWIE RW Enhanced Rx FIFO Underflow Interrupt Enable – Enables or disables the interrupt for Enhanced Rx FIFO underflow (ERFSR.ERFUFW): 1: Enable Enhanced Rx FIFO underflow interrupt. 0: Disable Enhanced Rx FIFO underflow interrupt. Address offset: 0xc14 Name: CAN_ERFSR_0 Reset Value: 0x00 [5:0] ERFEL R Enhanced Rx FIFO Elements – Indicates the number of CAN messages stored in the Enhanced Rx FIFO. Address offset: 0xc16 Name: CAN_ERFSR_2 Reset Value: 0x00 Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 508 Ver 0.8.0 [0] ERFF R Enhanced Rx FIFO Full: 1: The Enhanced Rx FIFO is full. 0: The Enhanced Rx FIFO is not full. [1] ERFE R Enhanced Rx FIFO Empty: 1: The Enhanced Rx FIFO is empty. 0: The Enhanced Rx FIFO is not empty. Address offset: 0xc17 Name: CAN_ERFSR_3 Reset Value: 0x00 [3] ERFCLR W Enhanced Rx FIFO Clear Writing 1 to ERFCLR when the CAN is in Freeze mode clears the Enhanced Rx FIFO content. Writing 0 to ERFCLR or writing 1 to ERFCLR when the CAN is not in Freeze mode has no effect. [4] ERFDA W1C Enhanced Rx FIFO Data Available – Set by hardware if there is at least one message stored in the Enhanced Rx FIFO: 1: There is at least one message stored in the Enhanced Rx FIFO. Interrupt ipi_int_erfda is asserted if CAN_ERFIER.ERFDAIE = 1. 0: There is no message stored in the Enhanced Rx FIFO. ERFDA is cleared by writing 1 to it. [5] ERFWMI W1C Enhanced Rx FIFO Watermark Indication – Set by hardware if the number of messages in the Enhanced Rx FIFO is greater than the watermark defined in CAN_ERFCR.ERFWM: 1: The number of messages in the Enhanced Rx FIFO is greater than the watermark. Interrupt ipi_int_erfwm is asserted if CAN_ERFIER.ERFWMIIE = 1. 0: The number of messages in the Enhanced Rx FIFO is not greater than the watermark. ERFWMI is cleared by writing 1 to it. [6] ERFOVF W1C Enhanced Rx FIFO Overflow – Indicates that an overflow condition occurred in the Enhanced Rx FIFO: 1: Enhanced Rx FIFO overflow has occurred. Interrupt ipi_int_erfovf is asserted if CAN_ERFIER.ERFOVFIE = 1. 0: Enhanced Rx FIFO overflow has not occurred. ERFOVF is cleared by writing 1 to it. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 509 Ver 0.8.0

11.14 Local Interconnect Network (LIN)

11.14.1 Introduction

The LIN-BUS is used for reliable, low-speed asynchronous serial communication in the automotive field. To construct a standard LIN network, it is also necessary to integrate a physical layer chip that complies with the LIN protocol requirements. This chip enables the conversion of the two Tx/Rx pins on the LIN controller interface into a single pin for connection to the LIN-BUS. The features of the Teli nk LIN controller module are as follows:

• Compatible with LIN protocol versions 1.3, 2.0, 2.1, and 2.2
• Supports optional LIN Commander and Responder mode
• Supports adjustable baud rates from 1 kbps to 20 kbps
• Supports the Filtered PID function with a filter list of up to 16 PIDs
• Supports Classic/Enhanced checksum calculation and check
• Supports DMA transmission
• Supports basi c UART mode (without flow control)
• 8-byte FIFO for transmission/reception
• LIN abnormal status detection
• 2x LIN (LIN0, LIN1)

11.14.2 Block Diagram

The figure below shows the block diagram of LIN controller. [7] ERFUFW W1C Enhanced Rx FIFO Underflow – Indicates that an underflow condition occurred in the Enhanced Rx FIFO: 1: Enhanced Rx FIFO underflow has occurred. Interrupt ipi_int_erfufw is asserted if CAN_ERFIER.ERFUFWIE = 1. 0: Enhanced Rx FIFO underflow has not occurred. ERFUFW is cleared by writing 1 to it. Bit Range Field Type Description

Datasheet for Telink TL3828 DS-TL3828-E5 510 Ver 0.8.0 Figure 11-99 Block Diagram of LIN Controller

11.14.3 Baud Rate

The Baud Rate Generator takes the LIN clock as the source clock (pclk) and divides it with a divisor. The divisor consists of uart_clk_div and bpwc register. The uart_clk_div value is 15-bit in size and stored in two separate registers. The formula for the divisor value is as follows: uart_sclk = pclk/(uart_clk_div[14:0]+1) Baudrate = uart_sclk/(bpwc+1), bpwc > 2 For example: T able 11-28 Baud Rate

11.14.4 LIN Transmission/Reception

To activate the LIN module, lin_st_cmd must be set to 1, and lin_resp_en must be enabled. When lin_resp_en is set to 0, the LIN module functions as a UART module but without UART flow control, as a standard LIN module does not include RTS/CTS pins. In Commander (Master) mode, the LIN module can transmit and receive both the header and response of a LIN frame. In Responder (Slave) mode, the module can only transmi t and receive responses after receiving a LIN frame header. Baud Rate uart_clk_div bpwc pclk 9600 249 9 24 MHz 19200 124 9 24 MHz 20000 99 11 24 MHz LIN Controller LIN_CTRL LIN_COMM LIN_RESP Baud Rate GEN UART_TX UART_RX REGs FIFO Buf Status & IRQ APB-BUS DMA-intf

Datasheet for Telink TL3828 DS-TL3828-E5 511 Ver 0.8.0 Figure 11-100 LIN Controller Interface Signal Diagram

11.14.5 LIN Master Mode (Commander Mode)

11.14.5.1 Header Transmission

To enable Commander mode, lin_comm_en must be set. The break field in the header is configured by setting lin_break_len and lin_break_1_len. The PID field is automatically generated by hardware after setting lin_pid, including the parity check bits. The sync field is fixed at 0x55, as required by the protocol, and is automatically filled by hardware. Once the header data is i nitialized, writing 1 to comm_header_act will trigger the LIN module to transmit the header data through the Tx pin.

11.14.5.2 LIN Frame Timing

The Commander mode also controls the overall LIN-BUS timing. It requires configuring T_base and the number of T_base units assigned to each frame slot. The T_base time can be set to 5ms using lin_t_base_cnt. For a 10ms T_base time, set lin_t_base_sel to 1. lin_t_base_cnt is configured based on uart_sclk, whi ch is derived from pclk using uart_clk_div. The frame slot is set using lin_comm_frame_cnt. When a frame slot ends, the lin_comm_tx_wait_cnt register can be adjusted to configure the interval before the next header transmission.

11.14.6 LIN Slave Mode (Responder Mode)

11.14.6.1 Response Transmission/Reception

When lin_comm_en is set to 0 and lin_resp_en is set to 1, the LIN module operates in Responder mode. Upon receiving the break-field, the Responder mode state machi ne begins operation, sequentially receiving the sync-field and PID-field. After the header is fully received, the received PID can be obtained from the lin_pid register to determine whether this frame should be responded to. If a response needs to be transmitted:

• Set lin_frame_direction to 1.

Datasheet for Telink TL3828 DS-TL3828-E5 512 Ver 0.8.0

• Configure the response length using lin_frame_len and lin_frame_len_trig.
• By default, the hardware automatically calculates the checksum field, and the computed checksum can be read from the lin_checksum register. If a response needs to be received:
• Set lin_frame_direction to 0.
• Configure the response length using lin_frame_len and lin_frame_len_trig. If the Filter PID buffer functi on is used, manual configuration of the response length is not required.

11.14.6.2 Filter PID Function

The LIN module’s Filter PID list can store up to 16 PIDs, along with their corresponding PID lengths and whether they should trigger an automatic response transmission upon reception. When flt_pid_buf_wr_en is set to 1, the filter group0 ~ group3 can be selected using flt_pid_buf_grp_sel[1:0]. The corresponding PID and filtered_pid_tx can be written into LIN_PID_FILTER0 ~ LIN_PID_FILTER3, while the frame lengths of the four PIDs can be wri tten into flt_pid0_len to flt_pid3_len. For example:

• If flt_pid_buf_grp_sel is 0, writing to LIN_PID_FILTER3 stores data in the 3rd buffer.
• If flt_pid_buf_grp_sel is 1, writing to LIN_PID_FILTER2 stores data in the 6th buffer. To clear the PID buffer, set fil_pid_buf_wr_en to 0 and write 1 to flt_pid_buf_clr. Each filter entry can be enabled or disabled using flt_pid_en0 ~ flt_pid_en15, correspondi ng to filters 0 ~ 15.

11.14.7 Register Description of LIN

The LIN related registers are listed as following. For LIN0 related register, the base address is 0x80140500; For LIN1 related register, the base address is 0x80240140. Table 11-29 LIN Related Registers Address offset Name Type Description Reset Value 0x00 LIN0_UART_DATA_BUF0 Volatile [7:0]: buf0, write/read buffer[7:0] 0x00 0x01 LIN0_UART_DATA_BUF1 Volatile [7:0]: buf1, write/read buffer[15:8] 0x00 0x02 LIN0_UART_DATA_BUF2 Volatile [7:0]: buf2, write/read buffer[23:16] 0x00 0x03 LIN0_UART_DATA_BUF3 Volatile [7:0]: buf3, write/read buffer[31:24] 0x00 0x04 LIN0_UART_CLK_DIV_L RW [7:0]: clk_div_l, uart_cli_div[7:0]: uart clk div register 0xff 0x05 LIN0_UART_CLK_DIV_H RW [7:0]: clk_div_h, uart_cli_div[15:8]: uart_sclk = sclk/(uart_clk_div[14:0]+1) uart_clk_div[15]: 1:enable clock divider,0: disable. 0x0f

Datasheet for Telink TL3828 DS-TL3828-E5 513 Ver 0.8.0 0x06 LIN0_UART_CTRL0 RW [3:0]: bpwc_o, bpwc, bit width, should be larger than 2 Buadrate = uart_sclk/(bpwc+1) [4]: auto_rxclr_en, DMA and ndmamode: auto clr function switch; 1:enable,0:disable [5]: ndma_rxdone_en, NDMA mode: rxdone(timeout) function switch; 1:enable,0:disable;dma mode must disable [6]: rxtimeout_rts_en, RTS controls timeout stop enabling signal [7]: p7816_en_o, 7816 enable 0x7f 0x07 LIN0_UART_CTRL1 RW [0]: tx_cts_polarity, cts select, 0: cts_i, 1: cts _i inverter [1]: tx_cts_enable, cts enable, 1: enable, 0, disable [2]: parity_enable, Parity, 1: enable, 0 :disable [3]: parity_polarity, even Parity or odd [5:4]: stop_sel, stop bit 00: 1 bit, 01, 1.5bit 1x: 2bits [6]: ttl_enable, ttl enable [7]: loopback_o, uart tx, rx loopback 0x08 0x08 LIN0_UART_CTRL2 RW [3:0]: rts_triq_lev, rts trig level [4]: rts_polarity, rts Parity [5]: rts_manul_v, rts manual value [6]: rts_manul_m, rts manual enable [7]: rts_en, rts enable 0x25 0x09 LIN0_UART_CTRL3 RW [3:0]: rx_irq_triq_lev, rx_irq_trig level [7:4]: tx_irq_triq_lev, tx_irq_trig level 0x44 0x0a LIN0_UART_RXTIMEOUT_ O_L RW [7:0]: rx_timeout_l, r_rxtimeout_o[7:0]:The setting is transfer one bytes need cycles base on uart_clk. For example, if transfer one bytes (1start bit+8bits data+1 priority bit+2stop bits) total 12 bits, this register setting should be (bpwc+1)*12. 0xc0 Address offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 514 Ver 0.8.0 0x0b LIN0_UART_RXTIMEOUT_ O_H RW [1:0]: r_rxtimeout_o, r_rxtimeout_o[9:8]:R_rxtimeout 2’b00:rx timeout time is r_rxtimeout[7:0] 2’b01:rx timeout time is r_rxtimeout[7:0]*2 2’b10:rx timeout time is r_rxtimeout[7:0]*3 3’b11: rx timeout time is r_rxtimeout[7:0]*4 R_rxtimeout is for rx dma to decide the end of each transaction. Supposed the interval between each byte in one transaction is very short. [2]: mask_rx_irq, rx interrupt enable [3]: mask_tx_irq, tx interrupt enable [4]: mask_rxdone, mask_rxdone [5]: mask_txdone, mask_txdone [6]: mask_err_irq, mask_err [7]: reserved 0x01 0x0c LIN0_UART_BUFCNT Volatile [3:0]: rx_bufcnt, r_buf_cnt [7:4]: tx_bufcnt, t_buf_cnt 0x00 0x0d LIN0_UART_STATUS Volatile [2:0]: rbcnt, rbcnt [3]: irq_o, irq [6:4]: wbcnt, R: wbcnt, [7]: rxdone, rxdone 0x00 0x0e LIN0_UART_TXRX_STATU S Volatile [1:0]: rx_rem_cnt_d, R: rx_rem_cnt_d [2]: rx_buf_irq, rxbuf_irq; W: [2] write 1 to clear rx [3]: tx_buf_irq, txbuf_irq; W:[3] write 1 to clear tx [4]: rxdone_irq, R: rxdone_irq; W:[4] write 1 to clear rxdone_irq [5]: txdone, txdone; W:[5] write 1 to clear txdone [6]: rx_err, R: rx_err [7]: Timeout, R: Timeout 0x00 0x0f LIN0_UART_STATE Volatile [2:0]: tstate_i, tx state machine; 0-idle; 1-start; 2-byte; 3-parity; 4-stop; 5-pop byte; [3]: rx_full [7:4]: rstate_i, rx state machine; W:[6] write 1 to clear sclk_cnt; 0-idle; 1-start; 2-bit; 3-parity; 4-stop; 5-check parity; 6-prepare; 7-end bit; 8-lc parity; 9-wait; 10-push 0x00 Address offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 515 Ver 0.8.0 0x10 LIN0_UART_CTRL4 RW [0]: rxdone_rts_en, 1'b1:rxdone work on rts; 1'b0:rxdone doesn't work on rts [1]: timeout_en, 1'b1:enable rxtimeout; 1'b0 disable rxtimeout [2]: rx_timeout_reload_sel 1'b0: wr_o; 1'b1: REC_PREPARE state pulse [3]: rts_stop_timeout_en Enables the counter to stop by rts [4]: pem_event_en, pem event enable [5]: reservede [6]: uart_en, uart enable [7]: reserved 0x4b 0x11 LIN0_UART_RXTIMEOUT_ O_EXP RW [7:0]: r_rxtimeout_exp, r_rxtimeout_o[9:8]:R_rxtimeout 2’b00: rx timeout time is r_rxtimeout[7:0] * r_rxtimeout_exp 2’b01: rx timeout time is r_rxtimeout[7:0]*2 * r_rxtimeout_exp 2’b10: rx timeout time is r_rxtimeout[7:0]*3 * r_rxtimeout_exp 3’b11: rx timeout time is r_rxtimeout[7:0]*4 * r_rxtimeout_exp R_rxtimeout is for rx dma to decide the end of each transaction. Supposed the interval between each byte in one transaction is very short. 0x00 0x12 LIN0_UART_PEM_CTRL RW [4:0]: pem_task_en 0x00 Address offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 516 Ver 0.8.0 0x13 LIN_CTRL0 RW [0]: lin_comm_en [1]: lin_resp_en [2]: rsvd [3]: lin_pid_reg_en, 1:usgin reg pid, 0:using txbuf pid [4]: lin_bus_txbk_check_en, 1:lin node check tx data by rx lin-bus [5]: lin_pid_put_fifo, 1:lin rx-pid put-into rx-fifo [6]: lin_checksum_put_fifo, 1:lin rx checksum put-into rx- fifo [7]: tx_fifo_buf_auto_clr 0x9e 0x14 LIN_CTRL1 RW [1:0]: lin_break_len, 0:12 1:13 2:14 3:15 [3:2]: lin_break_1_len, 0:1 1:2 2:3 [4]: lin_t_base_sel, 1:10ms 0:5ms [5]: comm_tx_loop, 1:comm tx loop, 0:comm tx once [6]: lin_schedule_flt_pid_en, using schedule_cnt buf mode [7]: lin_schedule_dly_talbe_en, using schedule_cnt buf mode 0x5 0x15 LIN_CMD RW/W [1:0]: lin_st_cmd 0:init, 1:run, 2:sleep (RW) [2]: comm_header_act 0:comm no act ,1:comm tx header (W) [3]: lin_t_base_man_clr t_base_timer clear, re-counting from 0ms (W) [4]: comm_force_run 1: abort current action, re-run now (W) [5]: response_discard 1:discard response, not keep in buf (W) [6]: tx_wake_up_sig, 1:tx wake_up signal (W) 0x0 Address offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 517 Ver 0.8.0 0x16 LIN_RESP1 RW [0]: lin_txst_rx_buf_auto_clr_en, [1]: lin_nonflt_pid_discard_en, no-matched flt_pid received, frame discard [2]: lin_diag_frame_cs_len_auto, auto set frame_checksum classic, frame_len 8 [5:3]: lin_uart_rx_smp_postion_adj, auto set frame_checksum classic, frame_len 8 0x10 0x17 LIN_NODE_TABLE R [3:0]: flt_pid_match_idx, read-back match filtered_pid num [7:4]: schedule_cur_idx, read-back for current comm tx schedule cnt 0x0 0x18 LIN_FRAME0 Volatile [5:0]: lin_pid, comm_mode can set pid resp mode can read pid 0x0 0x19 LIN_FRAME1 - [0]: lin_checksum_type, 1:enhanced, 0:classic (RW) [1]: lin_checksum_sw, 1:checksum by software (RW) [2]: lin_frame_direction, 1:tx 0:rx (Volatile) [6:4]: lin_frame_len, 0~7 map 1~8 (RW) [7]: lin_frame_len_trig, len update trig (W) 0x1a LIN_FRAME2 Volatile [7:0]: lin_checksum lin_checksum_sw == 1: checksum wr val by software lin_checksum_sw == 0: checksum cal by hardware, can be read 0x0 0x1b LIN_COMM0 RW [5:0]: lin_comm_frame_cnt frame slot t_base count, set 0 in adjacent mode [6]: lin_frame_slot_auto 1: frame slot auto by nearest t_base, 0: by slot_cnt or table 0x0 0x1c LIN_CTRL2 RW [7:0]: lin_t_base_cnt_l 5ms t_base_cnt = (12e4 / uart_clkdiv) -1 0x3f 0x1d LIN_CTRL3 RW [2:0]: lin_t_base_cnt_h [7:3]: lin_timeout_cnt_h, timeout for lin bus 1 period 0x1e LIN_CTRL4 RW [7:0]: lin_timeout_cnt_l timeout for lin bus 1 period, counter @ clk_div 0x0 Address offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 518 Ver 0.8.0 0x1f LIN_NODE_FSM R [3:0]: lin_resp_fsm, lin_resp FSM rd [6:4]: lin_comm_fsm, lin_comm FSM rd 0x0 0x20 LIN_STATUS0 W1C [0]: rec_hit_non_flt_pid [1]: rec_hit_pid_err [2]: resp_tx_done [3]: resp_rx_done [4]: resp_checksum_err [5]: frame_err [6]: tx_return_byte_err [7]: hit_flt_pid_tx 0x0 0x21 LIN_STATUS1 W1C [0]: rec_hit_pid [1]: comm_hit_pid, tx header done [2]: resp_timeout, subscriber-node(comm) receive resp timeout [3]: header_timeout, resp-node match break, wait header timeout [4]: comm_frame_slot_done, hit frame slot [5]: comm_hit_schedule_end, comm tx frame num hit schedule set,finish tx_checksum [6]: rec_new_break, resp_task detect another break_fileld [7]: lin_bus_inactive, 4~10s lin-bus inactive, sleep indicator 0x0 0x22 LIN_IRQ0 RW [0]: mask_rec_non_flt_pid, hit_non_flt_pid, no err [1]: mask_rec_header_err, pid parity check error [2]: mask_resp_tx_done, resp tx data done [3]: mask_resp_rx_done, resp rx data done [4]: mask_resp_checksum_err, resp rx checksum err [5]: mask_frame_err, uart frame err, check stop bit [6]: mask_tx_return_byte_err, tx data byte check from rx lin-bus [7]: mask_flt_pid_tx, hit_flt_pid?the pid set tx 0x0 Address offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 519 Ver 0.8.0 0x23 LIN_IRQ1 RW [0]: mask_rec_header, hit_pid, no err [1]: mask_comm_header_done, comm tx header done [2]: mask_resp_timeout, resp_timeout: no resp or no checksum [3]: mask_header_timeout, resp-node match break, wait header timeout [4]: mask_comm_frame_slot_done, hit frame slot [5]: mask_comm_schedule_end, [6]: mask_rec_new_break, [7]: mask_lin_bus_inactive, 4~10s lin-bus inactive, sleep indicator 0x0 0x24 LIN_PID_FILTER0 RW [5:0]: filtered_frame_id [6]: filtered_pid_tx, 1: hit_flt_pid reponse tx 0x0 0x25 LIN_PID_FILTER1 RW [5:0]: filtered_frame_id [6]: filtered_pid_tx, 1:hit_flt_pid reponse tx 0x0 0x26 LIN_PID_FILTER2 RW [5:0]: filtered_frame_id [6]: filtered_pid_tx, 1:hit_flt_pid reponse tx 0x0 0x27 LIN_PID_FILTER3 RW [5:0]: filtered_frame_id [6]: filtered_pid_tx, 1:hit_flt_pid reponse tx 0x0 0x28 LIN_PID_FIL_EN0 RW [0]: flt_pid_en0 [1]: flt_pid_en1 [2]: flt_pid_en2 [3]: flt_pid_en3 [4]: flt_pid_en4 [5]: flt_pid_en5 [6]: flt_pid_en6 [7]: flt_pid_en7 0x0 Address offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 520 Ver 0.8.0 0x29 LIN_PID_FIL_EN1 RW [0]: flt_pid_en8 [1]: flt_pid_en9 [2]: flt_pid_en10 [3]: flt_pid_en11 [4]: flt_pid_en12 [5]: flt_pid_en13 [6]: flt_pid_en14 [7]: flt_pid_en15 0x0 0x2a LIN_FIT_PID_LEN01 RW [2:0]: flt_pid0_len [6:4]: flt_pid1_len 0x0 0x2b LIN_FIT_PID_LEN23 RW [2:0]: flt_pid2_len [6:4]: flt_pid3_len 0x0 0x2c LIN_SCHEDULE0 RW [5:0]: lin_comm_schedule_dly_buf0 0x0 0x2d LIN_SCHEDULE1 RW [5:0]: lin_comm_schedule_dly_buf1 0x0 0x2e LIN_SCHEDULE2 RW [5:0]: lin_comm_schedule_dly_buf2 0x0 0x2f LIN_SCHEDULE3 RW [5:0]: lin_comm_schedule_dly_buf3 0x0 0x30 LIN_FIT_PID_CTRL RW [1:0]: flt_pid_buf_grp_sel, 0~3, sel filtered_pid_group, total 16 pid_buf [2]: fil_pid_buf_wr_en, [3]: flt_pid_buf_clr, clear filter_pid_buf, set 1 [5:4]: comm_schedule_group_sel, 0~3, total 16 schedule buf [6]: lin_schedule_clr, clear all schedule buf cnt [7]: lin_comm_schedule_idx_rst, schedule buf curr_index reset 0x0 0x31 LIN_COMM1 RW [3:0]: lin_schedule_loop_start_idx, schedule dly cnt lookup-table config start-index [7:4]: lin_schedule_loop_end_idx, schedule dly cnt lookup- table config end-index 0x0 0x32 LIN_BUS0 RW [7:0]: lin_tx_wake_up_time 150~500us; 1k: 3~8; 20k: 48~160 0x0 Address offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 521 Ver 0.8.0 0x33 LIN_BUS1 RW [7:0]: lin_bus_inactive_time_cnt_l, 4~10s, using baud-rate counting time 0x0 0x34 LIN_BUS2 RW [7:0]: lin_bus_inactive_time_cnt_m, 4~10s, using baud- rate counting time 0x0 0x35 LIN_BUS3 RW [1:0]: lin_bus_inactive_time_cnt_h, 4~10s, using baud-rate counting time [6:2]: lin_comm_tx_wait_cnt, hit_t_base0?wait uart_clk cyc for sw ready 0x22 Address offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 522 Ver 0.8.0

12 USB

12.1 Overview of USB

The SoC has a high-speed USB interface for communicating with other compatible digital devices. The USB interface acts as a USB 2.0 device controller, responding to requests from a master host controller. The USB high speed interface includes the following features:

• Supports different clocks for AHB for ease of integration
• Supports up to 9 bidirectional endpoints, including control endpoi nt 0
• Ability to choose multiple power rails for low power modes
• AHB Completer interface for accessing Control and Status Registers (CSRs), the Data FIFO, and queues
• Supports only 32-bit data on the AHB
• Supports INCR4, INCR8, INCR16, INCR, and SINGLE transfers on the AHB Completer interface
• Supports Split, Retry, and Error AHB responses on the AHB Requester interface. Split and retry responses are not generated on the AHB Completer i nterface. Error Response is generated on the AHB Completer interface when the transfer size (HSIZE) is not equal to 32 bits.
• Supports internal DMA mode
• Support for a dedicated transmit FIFO for each of the device IN endpoints in DMA modes. Each FIFO can hold multiple packets.
• Active Clock Gating allows the controller to reduce dynamic power consumpti on by gating the AHB and PHY clocks internally within the modules of the controller during the IDLE periods between the USB and AHB traffic. It also gates the RAM clock output when the SPRAM is not accessed by the controller.

12.2 Register Table of USB

The USB related registers are listed in table below, the base address is 0x80280000. Table 12-1 USB-HS Related Registers Address Offset Name Type Description Default Value 0x00 GOTGCTL0 R [7:0] Reserved 0x00 0x01 GOTGCTL1 R [7:0] Reserved 0x00 0x02 GOTGCTL2 R [5:0] Reserved [7:6] MultValIdBC_1_0, Multi Valued ID pin (MultValIdBC) 0x0d NOTE:

• When using USB, the supply voltage must be greater than 3.0V.

Datasheet for Telink TL3828 DS-TL3828-E5 523 Ver 0.8.0 0x03 GOTGCTL3 - [2:0] MultValIdBC_4_2 [3] ChirpEn [4] eUSB2_phy_disc_supp, This field is only applicable to Device mode and must be set to 1'b1 if eUSB2 PHY is used. [7] Testmode_corr_eUSB2, UTMI IF correction for eUSB2 PHY during Test mode. This bit is used to modify the behavior of UTMI 8-bit interface signals during test J and test K sequences when eUSB2 PHY is used. 0x00 0x04 GOTGINT0 R [7:0] Reserved 0x00 0x05 GOTGINT1 R [7:0] Reserved 0x00 0x06 GOTGINT2 R [3:0]: Reserved_19_16 [4]: MultValIpChng [7:5]: RESERVED_23_21 0x00 0x07 GOTGINT3 R [7:0] Reserved 0x00 0x08 GAHBCFG0 - [0]: GlblIntrMsk [4:1]: HBstLen [5]: DMAEn [6]: RESERVED_6 [7]: Reserved_7 0x00 0x09 GAHBCFG1 R [0]: Reserved_8 [7:1]: Reserved_15_9 0x00 0x0a GAHBCFG2 - [4:0]: Reserved_20_16 [5]: RemMemSupp [6]: NotiAllDmaWrit [7]: AHBSingle 0x00 0x0b GAHBCFG3 - [0]: InvDescEndianess [2:1]: LOA_EOP_CHECK_CLKS_BYTE [4:3]: LOA_EOP_CHECK_CLKS_WORD [6:5]: RESERVED1_30_29 [7]: RESERVED1_31 0x0a Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 524 Ver 0.8.0 0x0c GUSBCFG0 - [2:0]: TOutCal [3]: Reserved_3 [4]: Reserved_4 [5]: Reserved_5 [6]: Reserved_6 [7]: DDRSel 0x00 0x0d GUSBCFG1 - [1:0]: Reserved_9_8 [5:2]: USBTrdTim [6]: Reserved_14 [7]: PhyLPwrClkSel 0x14 0x0e GUSBCFG2 - [0]: Reserved_16 [1]: Reserved_17 [2]: ULPIAutoRes [3]: ULPIClkSusM [4]: Reserved_20 [5]: Reserved_21 [6]: Reserved_22 [7]: Reserved_23 0x00 0x0f GUSBCFG3 - [1:0]: Reserved_25_24 [4]: TxEndDelay [5]: Reserved_29 [6]: Reserved_30 [7]: CorruptTxPkt 0x10 0x10 GRSTCTL0 - [0]: CSftRst [1]: PIUFSSftRst [3:2]: Reserved_3_2 [4]: RxFFlsh [5]: TxFFlsh [7:6]: TxFNum_L 0x00 0x11 GRSTCTL1 RW [2:0]: TxFNum_L [5]: Reserved_13 [7:6]: Reserved_15_14 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 525 Ver 0.8.0 0x12 GRSTCTL2 RW [7:0]: Reserved_23_16 0x00 0x13 GRSTCTL3 RW [4:0]: Reserved_28_24 [5]: CSftRstDone [6]: DMAReq [7]: AHBIdle 0x80 0x14 GINTSTS0 - [0]: Reserved_0 [1]: Reserved_1 [2]: Reserved_2 [3]: Sof [4]: RxFLvl [5]: Reserved_5 [6]: GINNakEff [7]: GOUTNakEff 0x00 0x15 GINTSTS1 - [1:0]: Reserved_9_8 [2]: ErlySusp [3]: USBSusp [4]: USBRst [5]: EnumDone [6]: ISOOutDrop [7]: EOPF 0x00 0x16 GINTSTS2 - [0]: RstrDoneInt [1]: Reserved_17 [2]: IEPInt [3]: OEPInt [5:4]: Reserved_21_20 [6]: FetSusp [7]: ResetDet 0x00 0x17 GINTSTS3 - [2:0]: Reserved_26_24 [3]: LPM_Int [4]: Reserved_28 [5]: Reserved_29 [6]: Reserved_30 [7]: WkUpInt 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 526 Ver 0.8.0 0x18 GINTMSK0 - [0]: Reserved_0 [1]: Reserved_1 [2]: OTGIntMsk [3]: SofMsk [4]: RxFLvlMsk [5]: Reserved_5 [6]: GINNakEffMsk [7]: GOUTNakEffMsk 0x00 0x19 GINTMSK1 - [1:0]: Reserved_9_8 [2]: ErlySuspMsk [3]: USBSuspMsk [4]: USBRstMsk [5]: EnumDoneMsk [6]: ISOOutDropMsk [7]: EOPFMsk 0x00 0x1a GINTMSK2 - [0]: RstrDoneIntMsk [1]: EPMisMsk [2]: IEPIntMsk [3]: OEPIntMsk [5:4]: Reserved_21_20 [6]: FetSuspMsk [7]: ResetDetMsk 0x00 0x1b GINTMSK3 - [2:0]: Reserved_26_24 [3]: LPM_IntMsk [6:4]: Reserved_30_28 [7]: WkUpIntMsk 0x00 0x1c GRXSTSR0 R [3:0]: EPNum [7:4]: BCnt_7_4 0x00 0x1d GRXSTSR1 R [6:0]: BCnt_14_8 [7]: DPID_15 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 527 Ver 0.8.0 0x1e GRXSTSR2 R [0]: DPID_16 [4:1]: PktSts [7:5]: FN_23_21 0x00 0x1f GRXSTSR3 R [0]: FN_24 [6:1]: RESERVED_30_25 0x00 0x20 GRXSTSP0 R [3:0]: EPNum [7:4]: BCnt_7_4 0x00 0x21 GRXSTSP1 R [6:0]: BCnt_14_8 [7]: DPID_15 0x00 0x22 GRXSTSP2 R [0]: DPID_16 [4:1]: PktSts [7:5]: FN_23_21 0x00 0x23 GRXSTSP3 R [0]: FN_24 [6:1]: RESERVED_30_25 0x00 0x24 GRXFSIZ0 R [7:0] RxFDep_7_0 0x00 0x25 GRXFSIZ1 R [2:0]: RxFDep_10_8 [7:3]: RESERVED_15_11 0x00 0x26 GRXFSIZ2 R [5:0]: RESERVED_21_16 0x00 0x28 GNPTXFSIZ0 RW [7:0]: INEPTxF0StAddr_7_0 0x00 0x29 GNPTXFSIZ1 RW [2:0]: INEPTxF0StAddr_10_8 0x04 0x2a GNPTXFSIZ2 RW [7:0]: INEPTxF0Dep_23_16 0x00 0x2b GNPTXFSIZ3 RW [0]: INEPTxF0Dep_24 0x01 0x34 GPVNDCTL0 RW [7:0]: RegData 0x00 0x35 GPVNDCTL1 RW [7:0]: VCtrl 0x00 0x36 GPVNDCTL2 - [5:0]: RegAddr [6]: RegWr [7]: RESERVED1_23 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 528 Ver 0.8.0 0x37 GPVNDCTL3 - [0]: RESERVED1_24 [1]: NewRegReq [2]: VStsBsy [3]: VStsDone [6:4]: RESERVED_30_28 [7]: DisUlpiDrvr 0x00 0x38 GGPIO0 R [7:0]: gp_in0 0x00 0x39 GGPIO1 R [7:0]: gp_in1 0x00 0x3a GGPIO2 RW [7:0]: gp_o0 0x00 0x3b GGPIO3 RW [7:0]: gp_o1 0x00 0x40 GSNPSID0 R [7:0]: SynopsysID_0 0x0a 0x41 GSNPSID1 R [7:0]: SynopsysID_1 0x50 0x42 GSNPSID2 R [7:0]: SynopsysID_2 0x32 0x43 GSNPSID3 R [7:0]: SynopsysID_3 0x55 0x44 GHWCFG10 R [7:0]: EpDir_0 0x00 0x45 GHWCFG11 R [7:0]: EpDir_1 0x00 0x46 GHWCFG12 R [7:0]: EpDir_2 0x00 0x47 GHWCFG13 R [7:0]: EpDir_3 0x00 0x48 GHWCFG20 R [7:0]: Reserved_7_0 0x00 0x49 GHWCFG21 R [1:0]: Reserved_9_8 [5:2]: NumDevEps [7:6]: Reserved_15_14 0x00 0x4a GHWCFG22 R [2:0]: Reserved_18_16 [3]: DynFifoSizing [7:4]: Reserved_23_20 0x00 0x4b GHWCFG23 R [7:0]: Reserved_31_24 0x00 0x4c GHWCFG30 R [3:0]: XferSizeWidth [6:4]: PktSizeWidth [7]: Reserved_7 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 529 Ver 0.8.0 0x4d GHWCFG31 R [2:0]: Reserved_10_8 [3]: RstType [5:4]: Reserved_13_12 [6]: BCSupport [7]: LPMMode 0x00 0x4e GHWCFG32 R [7:0]: DfifoDepth_h 0x3e 0x4f GHWCFG33 R [7:0]: DfifoDepth_h 0x03 0x50 GHWCFG40 R [3:0]: NumDevPerioEps [4]: PartialPwrDn [5]: AhbFreq [6]: Hibernation [7]: Reserved_7 0x20 0x51 GHWCFG41 R [0]: Reserved_8 [1]: EnhancedLPMSupt1 [2]: ServIntFlow [3]: ipgisocSupt [4]: ACGSupt [5]: EnhancedLPMSupt [7:6]: Reserved_15_14 0x2e 0x52 GHWCFG42 R [3:0]: NumCtlEps [7:4]: Reserved_23_20 0x00 0x53 GHWCFG43 R [1:0]: Reserved_25_24 [5:2]: INEps [6]: DescDMAEnabled [7]: DescDMA 0x48 0x54 GLPMCFG0 - [0]: LPMCap [1]: AppL1Res [5:2]: HIRD [6]: bRemoteWake [7]: EnblSlpM 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 530 Ver 0.8.0 0x55 GLPMCFG1 - [4:0]: HIRD_Thres [6:5]: CoreL1Res [7]: SlpSts 0x00 0x56 GLPMCFG2 - [0]: L1ResumeOK [3:1]: Reserved_19_17 [7:4]: LPM_Accept_Ctrl 0x00 0x57 GLPMCFG3 - [3:0]: Reserved_27_24 [4]: LPM_EnBESL [5]: LPM_RestoreSlpSts [7:6]: Reserved_31_30 0x00 0x58 GPWRDN0 - [0]: PMUIntSel [1]: PMUActv [2]: Restore [3]: PwrDnClmp [4]: PwrDnRst_n [5]: PwrDnSwtch [6]: Reserved_6 [7]: LnStsChng 0x10 0x59 GPWRDN1 - [0]: LineStageChangeMsk [1]: ResetDetected [2]: ResetDetMsk [3]: DisconnectDetect [4]: Reserved_12 [5]: ConnectDet [6]: ConnDetMsk [7]: Reserved_15 0x00 0x5a GPWRDN2 - [0]: Reserved_16 [1]: StsChngInt [2]: StsChngIntMsk [4:3]: LineState [7:5]: Reserved_23_21 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 531 Ver 0.8.0 0x5b GPWRDN3 - [4:0]: MultValIdBC [5]: ULPI_latch_enable_during_Hib_en 0x00 0x5c GDFIFOCFG0 RW [7:0]: GDFIFOCfg_l 0x00 0x5d GDFIFOCFG1 RW [7:0]: GDFIFOCfg_h 0x04 0x5e GDFIFOCFG2 RW [7:0]: EPInfoBaseAddr_l 0xe8 0x5f GDFIFOCFG3 RW [7:0]: EPInfoBaseAddr_h 0x03 0x64 GREFCLK0 RW [7:0]: SOF_CNT_WKUP_ALERT_7_0 0x00 0x65 GREFCLK1 - [1:0]: SOF_CNT_WKUP_ALERT_9_8 [5:2]: RESERVED [6]: RefclkMode [7]: REFCLKPER_l0 0x00 0x66 GREFCLK2 RW [7:0]: REFCLKPER_l 0x00 0x67 GREFCLK3 RW [7:0]: REFCLKPER_h 0x00 0x68 GINTMSK20 - [0]: WkUpAlertIntMsk [7:1]: RESERVED_7_1 0x00 0x69 GINTMSK21 R [7:0]: RESERVED_15_8 0x00 0x6a GINTMSK22 R [7:0]: RESERVED_23_16 0x00 0x6b GINTMSK23 R [7:0]: RESERVED_31_24 0x00 0x6c GINTSTS20 - [0]: WkUpAlertInt [7:1]: RESERVED_7_1 0x00 0x6d GINTSTS21 R [7:0]: RESERVED_15_8 0x00 0x6e GINTSTS22 R [7:0]: RESERVED_23_16 0x00 0x6f GINTSTS23 R [7:0]: RESERVED_31_24 0x00 0x104 DIEPTXF00 RW [7:0]: INEPnTxFStAddr_7_0 0x00 0x105 DIEPTXF01 RW [2:0]: INEPnTxFStAddr_10_8 0x05 0x106 DIEPTXF02 RW [7:0]: INEPnTxFStAddr_23_16 0x00 0x107 DIEPTXF03 RW [7:0]: INEPnTxFStAddr_24 0x01 0x108 DIEPTXF10 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 532 Ver 0.8.0 0x109 DIEPTXF11 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x05 0x10a DIEPTXF12 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x00 0x10b DIEPTXF13 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x01 0x10c DIEPTXF20 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x00 0x10d DIEPTXF21 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x05 0x10e DIEPTXF22 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x00 0x10f DIEPTXF23 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x01 0x110 DIEPTXF30 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x00 0x111 DIEPTXF31 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x05 0x112 DIEPTXF32 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x00 0x113 DIEPTXF33 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x01 0x114 DIEPTXF40 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x00 0x115 DIEPTXF41 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x05 0x116 DIEPTXF42 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x00 0x117 DIEPTXF43 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x01 0x118 DIEPTXF50 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x00 0x119 DIEPTXF51 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x05 0x11a DIEPTXF52 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x00 0x11b DIEPTXF53 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x01 0x11c DIEPTXF60 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x00 0x11d DIEPTXF61 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x05 0x11e DIEPTXF62 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x00 0x11f DIEPTXF63 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x01 0x120 DIEPTXF70 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x00 0x121 DIEPTXF71 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x05 0x122 DIEPTXF72 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x00 0x123 DIEPTXF73 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x01 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 533 Ver 0.8.0 0x124 DIEPTXF80 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x00 0x125 DIEPTXF81 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x05 0x126 DIEPTXF82 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x00 0x127 DIEPTXF83 RW Device IN Endpoint Transmit FIFO 1 Size Register 0x01 0x400 HCFG0 - [1:0]: DevSpd [2]: NZStsOUTHShk [3]: Reserved_3 [6:4]: Reserved_6_4 [7]: ena32khz_suspend 0x00 0x401 HCFG1 RW [7:0]: resume_valid_period 0x02 0x402 HCFG2 R [7:0]: Reserved_23_16 0x0d 0x403 HCFG3 R [7:0]: Reserved_31_24 0x00 0x800 DCFG0 - [1:0]: DevSpd [2]: NZStsOUTHShk [3]: Reserved_3 [7:4]: DevAddr_7_4 0x00 0x801 DCFG1 - [2:0]: DevAddr_10_8 [4:3]: PerFrInt [5]: EnDevOutNak [6]: XCVRDLY [7]: ErraticIntMsk 0x00 0x802 DCFG2 - [0]: Reserved_16 [1]: ipgisocSupt [6:2]: Reserved_22_18 [7]: DescDMA 0x12 0x803 DCFG3 RW [1:0]: PerSchIntvl [7:2]: ResValid 0x08 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 534 Ver 0.8.0 0x804 DCTL0 - [0]: RmtWkUpSig [1]: SftDiscon [2]: GNPINNakSts [3]: GOUTNakSts [6:4]: TstCtl [7]: SGNPInNak 0x02 0x805 DCTL1 - [0]: CGNPInNak [1]: SGOUTNak [2]: CGOUTNak [3]: PWROnPrgDone [6:5]: GMC [7]: IgnrFrmNum 0x00 0x806 DCTL2 - [0]: NakOnBble [1]: EnContOnBNA [2]: DeepSleepBESLReject [3]: ServInt [7:4]: RESERVED_23_20 0x00 0x807 DCTL3 RW [6:0]: RESERVED_30_24 0x00 0x808 DSTS0 - [0]: SuspSts [2:1]: EnumSpd [3]: ErrticErr [7:4]: RESERVED1 0x02 0x809 DSTS1 R [7:0]: SOFFN_15_8 0x00 0x80a DSTS2 R [5:0]: SOFFN_21_16 [7:6]: DevLnSts 0x00 0x80b DSTS3 R [7:0]: RESERVED_31_24 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 535 Ver 0.8.0 0x810 DIEPMSK0 - [0]: XferComplMsk [1]: EPDisbldMsk [2]: AHBErrMsk [3]: TimeOUTMsk [4]: INTknTXFEmpMsk [5]: INTknEPMisMsk [6]: INEPNakEffMsk [7]: RESERVED1 0x00 0x811 DIEPMSK1 - [0]: TxfifoUndrnMsk [1]: BNAInIntrMsk [2]: NAKMsk [7:6]: RESERVED_15_14 0x00 0x812 DIEPMSK2 R [7:0]: RESERVED_23_16 0x00 0x813 DIEPMSK3 R [7:0]: RESERVED_31_24 0x00 0x814 DOEPMSK0 - [0]: XferComplMsk [1]: EPDisbldMsk [2]: AHBErrMsk [3]: SetUPMsk [4]: OUTTknEPdisMsk [5]: StsPhseRcvdMsk [6]: Back2BackSETup [7]: RESERVED1 0x00 0x815 DOEPMSK1 - [0]: OutPktErrMsk [1]: BnaOutIntrMsk [3]: BbleErrMsk [4]: NAKMsk [5]: NYETMsk [7:6]: RESERVED_15_14 0x00 0x816 DOEPMSK2 R [7:0]: RESERVED_23_16 0x00 0x817 DOEPMSK3 R [7:0]: RESERVED_31_24 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 536 Ver 0.8.0 0x818 DAINT0 R [0]: InEpInt0 [1]: InEpInt1 [2]: InEpInt2 [3]: InEpInt3 [4]: InEpInt4 [5]: InEpInt5 [6]: InEpInt6 [7]: InEpInt7 0x00 0x819 DAINT1 R [0]: InEpInt8 0x00 0x81a DAINT2 R [0]: OutEPInt0 [1]: OutEPInt1 [2]: OutEPInt2 [3]: OutEPInt3 [4]: OutEPInt4 [5]: OutEPInt5 [6]: OutEPInt6 [7]: OutEPInt7 0x00 0x81b DAINT3 R [0]: OutEPInt8 0x00 0x81c DAINTMSK0 RW [0]: InEpMsk0 [1]: InEpMsk1 [2]: InEpMsk2 [3]: InEpMsk3 [4]: InEpMsk4 [5]: InEpMsk5 [6]: InEpMsk6 [7]: InEpMsk7 0x00 0x81d DAINTMSK1 RW [0]: InEpMsk8 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 537 Ver 0.8.0 0x81e DAINTMSK2 RW [0]: OutEPMsk0 [1]: OutEPMsk1 [2]: OutEPMsk2 [3]: OutEPMsk3 [4]: OutEPMsk4 [5]: OutEPMsk5 [6]: OutEPMsk6 [7]: OutEPMsk7 0x00 0x81f DAINTMSK3 RW [0]: OutEPMsk8 0x00 0x830 DTHRCTL0 RW [0]: NonISOThrEn [1]: ISOThrEn [7:2]: TxThrLen_7_2 0x20 0x831 DTHRCTL1 - [2:0]: TxThrLen_10_8 [4:3]: AHBThrRatio [7:5]: RESERVED2_15_13 0x00 0x832 DTHRCTL2 RW [0]: RxThrEn [7:1]: RxThrLen_23_17 0x10 0x833 DTHRCTL3 - [1:0]: RxThrLen_25_24 [2]: RESERVED1 [3]: ArbPrkEn [7:4]: RESERVED_31_28 0x00 0x834 DIEPEMPMSK0 RW [7:0]: InEpTxfEmpMsk_l 0x00 0x835 DIEPEMPMSK1 RW [7:0]: InEpTxfEmpMsk_h 0x00 0x836 DIEPEMPMSK2 R [7:0]: RESERVED_7_0 0x00 0x837 DIEPEMPMSK3 R [7:0]: RESERVED_7_0 0x00 0x900 DIEPCTL00 - [1:0]: MPS [7:2]: RESERVED3_7_2 0x00 0x901 DIEPCTL01 R [2:0]: RESERVED3_10_8 [6:3]: Reserved_14_11 [7]: USBActEP 0x80 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 538 Ver 0.8.0 0x902 DIEPCTL02 - [0]: RESERVED2 [1]: NAKSts [3:2]: EPType [4]: RESERVED1 [5]: Stall [7:6]: TxFNum_23_22 0x00 0x903 DIEPCTL03 - [1:0]: TxFNum_25_24 [2]: CNAK [3]: SNAK [5:4]: RESERVED [6]: EPDis [7]: EPEna 0x00 0x908 DIEPINT00 - [0]: XferCompl [1]: EPDisbld [2]: AHBErr [3]: Reserved_3 [4]: INTknTXFEmp [5]: INTknEPMis [6]: INEPNakEff [7]: TxFEmp 0x80 0x909 DIEPINT01 - [0]: TxfifoUndrnMsk [1]: BNAIntr [3]: Reserved_11 [4]: BbleErr [5]: NAKIntrpt [6]: NYETIntrpt [7]: RESERVED_15 0x00 0x90a DIEPINT02 R [7:0]: RESERVED_23_16 0x00 0x90b DIEPINT03 R [7:0]: RESERVED_31_24 0x00 0x914 DIEPDMA00 RW [7:0]: DMAAddr_0 0x00 0x915 DIEPDMA01 RW [7:0]: DMAAddr_1 0x00 0x916 DIEPDMA02 RW [7:0]: DMAAddr_2 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 539 Ver 0.8.0 0x917 DIEPDMA03 RW [7:0]: DMAAddr_3 0x00 0x918 DTXFSTS00 R [7:0]: NEPTxFSpcAvail_l 0x00 0x919 DTXFSTS01 RW [7:0]: NEPTxFSpcAvail_h 0x01 0x91a DTXFSTS02 R [7:0]: RESERVED_23_16 0x00 0x91b DTXFSTS03 R [7:0]: RESERVED_31_24 0x00 0x91c DIEPDMAB00 R [7:0]: DMABufferAddr_0 0x00 0x91d DIEPDMAB01 R [7:0]: DMABufferAddr_1 0x00 0x91e DIEPDMAB02 R [7:0]: DMABufferAddr_2 0x00 0x91f DIEPDMAB03 R [7:0]: DMABufferAddr_3 0x00 0x920 DIEPCTL10 RW Device Control IN Endpoint Control Register 1 0x00 0x921 DIEPCTL11 RW Device Control IN Endpoint Control Register 1 0x80 0x922 DIEPCTL12 RW Device Control IN Endpoint Control Register 1 0x00 0x923 DIEPCTL13 RW Device Control IN Endpoint Control Register 1 0x00 0x928 DIEPINT10 RW Device IN Endpoint Interrupt Register 1 0x00 0x929 DIEPINT11 RW Device IN Endpoint Interrupt Register 1 0x00 0x92a DIEPINT12 RW Device IN Endpoint Interrupt Register 1 0x00 0x92b DIEPINT13 RW Device IN Endpoint Interrupt Register 1 0x00 0x934 DIEPDMA10 RW Device IN Endpoint DMA Address Register 1 0x00 0x935 DIEPDMA11 RW Device IN Endpoint DMA Address Register 1 0x00 0x936 DIEPDMA12 RW Device IN Endpoint DMA Address Register 1 0x00 0x937 DIEPDMA13 RW Device IN Endpoint DMA Address Register 1 0x00 0x938 DTXFSTS10 RW Device IN Endpoint Transmit FIFO Status Register 1 0x00 0x939 DTXFSTS11 RW Device IN Endpoint Transmit FIFO Status Register 1 0x10 0x93a DTXFSTS12 RW Device IN Endpoint Transmit FIFO Status Register 1 0x00 0x93b DTXFSTS13 RW Device IN Endpoint Transmit FIFO Status Register 1 0x00 0x93c DIEPDMAB10 RW Device IN Endpoint Buffer Address Register 1 0x00 0x93d DIEPDMAB11 RW Device IN Endpoint Buffer Address Register 1 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 540 Ver 0.8.0 0x93e DIEPDMAB12 RW Device IN Endpoint Buffer Address Register 1 0x00 0x93f DIEPDMAB13 RW Device IN Endpoint Buffer Address Register 1 0x00 0x940 DIEPCTL20 RW Device Control IN Endpoint Control Register 1 0x00 0x941 DIEPCTL21 RW Device Control IN Endpoint Control Register 1 0x80 0x942 DIEPCTL22 RW Device Control IN Endpoint Control Register 1 0x00 0x943 DIEPCTL23 RW Device Control IN Endpoint Control Register 1 0x00 0x948 DIEPINT20 RW Device IN Endpoint Interrupt Register 1 0x00 0x949 DIEPINT21 RW Device IN Endpoint Interrupt Register 1 0x00 0x94a DIEPINT22 RW Device IN Endpoint Interrupt Register 1 0x00 0x94b DIEPINT23 RW Device IN Endpoint Interrupt Register 1 0x00 0x954 DIEPDMA20 RW Device IN Endpoint DMA Address Register 1 0x00 0x955 DIEPDMA21 RW Device IN Endpoint DMA Address Register 1 0x00 0x956 DIEPDMA22 RW Device IN Endpoint DMA Address Register 1 0x00 0x957 DIEPDMA23 RW Device IN Endpoint DMA Address Register 1 0x00 0x958 DTXFSTS20 RW Device IN Endpoint Transmit FIFO Status Register 1 0x00 0x959 DTXFSTS21 RW Device IN Endpoint Transmit FIFO Status Register 1 0x01 0x95a DTXFSTS22 RW Device IN Endpoint Transmit FIFO Status Register 1 0x00 0x95b DTXFSTS23 RW Device IN Endpoint Transmit FIFO Status Register 1 0x00 0x95c DIEPDMAB20 RW Device IN Endpoint Buffer Address Register 1 0x00 0x95d DIEPDMAB21 RW Device IN Endpoint Buffer Address Register 1 0x00 0x95e DIEPDMAB22 RW Device IN Endpoint Buffer Address Register 1 0x00 0x95f DIEPDMAB23 RW Device IN Endpoint Buffer Address Register 1 0x00 0x960 DIEPCTL30 RW Device Control IN Endpoint Control Register 1 0x00 0x961 DIEPCTL31 RW Device Control IN Endpoint Control Register 1 0x80 0x962 DIEPCTL32 RW Device Control IN Endpoint Control Register 1 0x00 0x963 DIEPCTL33 RW Device Control IN Endpoint Control Register 1 0x00 0x968 DIEPINT30 RW Device IN Endpoint Interrupt Register 1 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 541 Ver 0.8.0 0x969 DIEPINT31 RW Device IN Endpoint Interrupt Register 1 0x00 0x96a DIEPINT32 RW Device IN Endpoint Interrupt Register 1 0x00 0x96b DIEPINT33 RW Device IN Endpoint Interrupt Register 1 0x00 0x974 DIEPDMA30 RW Device IN Endpoint DMA Address Register 1 0x00 0x975 DIEPDMA31 RW Device IN Endpoint DMA Address Register 1 0x00 0x976 DIEPDMA32 RW Device IN Endpoint DMA Address Register 1 0x00 0x977 DIEPDMA33 RW Device IN Endpoint DMA Address Register 1 0x00 0x978 DTXFSTS30 RW Device IN Endpoint Transmit FIFO Status Register 1 0x00 0x979 DTXFSTS31 RW Device IN Endpoint Transmit FIFO Status Register 1 0x01 0x97a DTXFSTS32 RW Device IN Endpoint Transmit FIFO Status Register 1 0x00 0x97b DTXFSTS33 RW Device IN Endpoint Transmit FIFO Status Register 1 0x00 0x97c DIEPDMAB30 RW Device IN Endpoint Buffer Address Register 1 0x00 0x97d DIEPDMAB31 RW Device IN Endpoint Buffer Address Register 1 0x00 0x97e DIEPDMAB32 RW Device IN Endpoint Buffer Address Register 1 0x00 0x97f DIEPDMAB33 RW Device IN Endpoint Buffer Address Register 1 0x00 0x980 DIEPCTL40 RW Device Control IN Endpoint Control Register 1 0x00 0x981 DIEPCTL41 RW Device Control IN Endpoint Control Register 1 0x80 0x982 DIEPCTL42 RW Device Control IN Endpoint Control Register 1 0x00 0x983 DIEPCTL43 RW Device Control IN Endpoint Control Register 1 0x00 0x988 DIEPINT40 RW Device IN Endpoint Interrupt Register 1 0x00 0x989 DIEPINT41 RW Device IN Endpoint Interrupt Register 1 0x00 0x98a DIEPINT42 RW Device IN Endpoint Interrupt Register 1 0x00 0x98b DIEPINT43 RW Device IN Endpoint Interrupt Register 1 0x00 0x994 DIEPDMA40 RW Device IN Endpoint DMA Address Register 1 0x00 0x995 DIEPDMA41 RW Device IN Endpoint DMA Address Register 1 0x00 0x996 DIEPDMA42 RW Device IN Endpoint DMA Address Register 1 0x00 0x997 DIEPDMA43 RW Device IN Endpoint DMA Address Register 1 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 542 Ver 0.8.0 0x998 DTXFSTS40 RW Device IN Endpoint Transmit FIFO Status Register 1 0x00 0x999 DTXFSTS41 RW Device IN Endpoint Transmit FIFO Status Register 1 0x01 0x99a DTXFSTS42 RW Device IN Endpoint Transmit FIFO Status Register 1 0x00 0x99b DTXFSTS43 RW Device IN Endpoint Transmit FIFO Status Register 1 0x00 0x99c DIEPDMAB40 RW Device IN Endpoint Buffer Address Register 1 0x00 0x99d DIEPDMAB41 RW Device IN Endpoint Buffer Address Register 1 0x00 0x99e DIEPDMAB42 RW Device IN Endpoint Buffer Address Register 1 0x00 0x99f DIEPDMAB43 RW Device IN Endpoint Buffer Address Register 1 0x00 0x9a0 DIEPCTL50 RW Device Control IN Endpoint Control Register 1 0x00 0x9a1 DIEPCTL51 RW Device Control IN Endpoint Control Register 1 0x80 0x9a2 DIEPCTL52 RW Device Control IN Endpoint Control Register 1 0x00 0x9a3 DIEPCTL53 RW Device Control IN Endpoint Control Register 1 0x00 0x9a8 DIEPINT50 RW Device IN Endpoint Interrupt Register 1 0x00 0x9a9 DIEPINT51 RW Device IN Endpoint Interrupt Register 1 0x00 0x9aa DIEPINT52 RW Device IN Endpoint Interrupt Register 1 0x00 0x9ab DIEPINT53 RW Device IN Endpoint Interrupt Register 1 0x00 0x9b4 DIEPDMA50 RW Device IN Endpoint DMA Address Register 1 0x00 0x9b5 DIEPDMA51 RW Device IN Endpoint DMA Address Register 1 0x00 0x9b6 DIEPDMA52 RW Device IN Endpoint DMA Address Register 1 0x00 0x9b7 DIEPDMA53 RW Device IN Endpoint DMA Address Register 1 0x00 0x9b8 DTXFSTS50 RW Device IN Endpoint Transmit FIFO Status Register 1 0x00 0x9b9 DTXFSTS51 RW Device IN Endpoint Transmit FIFO Status Register 1 0x01 0x9ba DTXFSTS52 RW Device IN Endpoint Transmit FIFO Status Register 1 0x00 0x9bb DTXFSTS53 RW Device IN Endpoint Transmit FIFO Status Register 1 0x00 0x9bc DIEPDMAB50 RW Device IN Endpoint Buffer Address Register 1 0x00 0x9bd DIEPDMAB51 RW Device IN Endpoint Buffer Address Register 1 0x00 0x9be DIEPDMAB52 RW Device IN Endpoint Buffer Address Register 1 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 543 Ver 0.8.0 0x9bf DIEPDMAB53 RW Device IN Endpoint Buffer Address Register 1 0x00 0x9c0 DIEPCTL60 RW Device Control IN Endpoint Control Register 1 0x00 0x9c1 DIEPCTL61 RW Device Control IN Endpoint Control Register 1 0x80 0x9c2 DIEPCTL62 RW Device Control IN Endpoint Control Register 1 0x00 0x9c3 DIEPCTL63 RW Device Control IN Endpoint Control Register 1 0x00 0x9c8 DIEPINT60 RW Device IN Endpoint Interrupt Register 1 0x00 0x9c9 DIEPINT61 RW Device IN Endpoint Interrupt Register 1 0x00 0x9ca DIEPINT62 RW Device IN Endpoint Interrupt Register 1 0x00 0x9cb DIEPINT63 RW Device IN Endpoint Interrupt Register 1 0x00 0x9d4 DIEPDMA60 RW Device IN Endpoint DMA Address Register 1 0x00 0x9d5 DIEPDMA61 RW Device IN Endpoint DMA Address Register 1 0x00 0x9d6 DIEPDMA62 RW Device IN Endpoint DMA Address Register 1 0x00 0x9d7 DIEPDMA63 RW Device IN Endpoint DMA Address Register 1 0x00 0x9d8 DTXFSTS60 RW Device IN Endpoint Transmit FIFO Status Register 1 0x00 0x9d9 DTXFSTS61 RW Device IN Endpoint Transmit FIFO Status Register 1 0x01 0x9da DTXFSTS62 RW Device IN Endpoint Transmit FIFO Status Register 1 0x00 0x9db DTXFSTS63 RW Device IN Endpoint Transmit FIFO Status Register 1 0x00 0x9dc DIEPDMAB60 RW Device IN Endpoint Buffer Address Register 1 0x00 0x9dd DIEPDMAB61 RW Device IN Endpoint Buffer Address Register 1 0x00 0x9de DIEPDMAB62 RW Device IN Endpoint Buffer Address Register 1 0x00 0x9df DIEPDMAB63 RW Device IN Endpoint Buffer Address Register 1 0x00 0x9e0 DIEPCTL70 RW Device Control IN Endpoint Control Register 1 0x00 0x9e1 DIEPCTL71 RW Device Control IN Endpoint Control Register 1 0x80 0x9e2 DIEPCTL72 RW Device Control IN Endpoint Control Register 1 0x00 0x9e3 DIEPCTL73 RW Device Control IN Endpoint Control Register 1 0x00 0x9e8 DIEPINT70 RW Device IN Endpoint Interrupt Register 1 0x00 0x9e9 DIEPINT71 RW Device IN Endpoint Interrupt Register 1 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 544 Ver 0.8.0 0x9ea DIEPINT72 RW Device IN Endpoint Interrupt Register 1 0x00 0x9eb DIEPINT73 RW Device IN Endpoint Interrupt Register 1 0x00 0x9f4 DIEPDMA70 RW Device IN Endpoint DMA Address Register 1 0x00 0x9f5 DIEPDMA71 RW Device IN Endpoint DMA Address Register 1 0x00 0x9f6 DIEPDMA72 RW Device IN Endpoint DMA Address Register 1 0x00 0x9f7 DIEPDMA73 RW Device IN Endpoint DMA Address Register 1 0x00 0x9f8 DTXFSTS70 RW Device IN Endpoint Transmit FIFO Status Register 1 0x00 0x9f9 DTXFSTS71 RW Device IN Endpoint Transmit FIFO Status Register 1 0x01 0x9fa DTXFSTS72 RW Device IN Endpoint Transmit FIFO Status Register 1 0x00 0x9fb DTXFSTS73 RW Device IN Endpoint Transmit FIFO Status Register 1 0x00 0x9fc DIEPDMAB70 RW Device IN Endpoint Buffer Address Register 1 0x00 0x9fd DIEPDMAB71 RW Device IN Endpoint Buffer Address Register 1 0x00 0x9fe DIEPDMAB72 RW Device IN Endpoint Buffer Address Register 1 0x00 0x9ff DIEPDMAB73 RW Device IN Endpoint Buffer Address Register 1 0x00 0xa00 DIEPCTL80 RW Device Control IN Endpoint Control Register 1 0x00 0xa01 DIEPCTL81 RW Device Control IN Endpoint Control Register 1 0x80 0xa02 DIEPCTL82 RW Device Control IN Endpoint Control Register 1 0x00 0xa03 DIEPCTL83 RW Device Control IN Endpoint Control Register 1 0x00 0xa08 DIEPINT80 RW Device IN Endpoint Interrupt Register 1 0x00 0xa09 DIEPINT81 RW Device IN Endpoint Interrupt Register 1 0x00 0xa0a DIEPINT82 RW Device IN Endpoint Interrupt Register 1 0x00 0xa0b DIEPINT83 RW Device IN Endpoint Interrupt Register 1 0x00 0xa14 DIEPDMA80 RW Device IN Endpoint DMA Address Register 1 0x00 0xa15 DIEPDMA81 RW Device IN Endpoint DMA Address Register 1 0x00 0xa16 DIEPDMA82 RW Device IN Endpoint DMA Address Register 1 0x00 0xa17 DIEPDMA83 RW Device IN Endpoint DMA Address Register 1 0x00 0xa18 DTXFSTS80 RW Device IN Endpoint Transmit FIFO Status Register 1 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 545 Ver 0.8.0 0xa19 DTXFSTS81 RW Device IN Endpoint Transmit FIFO Status Register 1 0x01 0xa1a DTXFSTS82 RW Device IN Endpoint Transmit FIFO Status Register 1 0x00 0xa1b DTXFSTS83 RW Device IN Endpoint Transmit FIFO Status Register 1 0x00 0xa1c DIEPDMAB80 RW Device IN Endpoint Buffer Address Register 1 0x00 0xa1d DIEPDMAB81 RW Device IN Endpoint Buffer Address Register 1 0x00 0xa1e DIEPDMAB82 RW Device IN Endpoint Buffer Address Register 1 0x00 0xa1f DIEPDMAB83 RW Device IN Endpoint Buffer Address Register 1 0x00 0xb00 DOEPCTL00 R [1:0]: MPS [7:2]: RESERVED3_7_2 0x00 0xb01 DOEPCTL01 R [6:0]: RESERVED3_14_8 [7]: USBActEP 0x80 0xb02 DOEPCTL02 - [0]: RESERVED2 [1]: NAKSts [3:2]: EPType [4]: Snp [5]: Stall [7:6]: RESERVED1_23_22 0x00 0xb03 DOEPCTL03 - [1:0]: RESERVED1_25_24 [2]: CNAK [3]: SNAK [5:4]: RESERVED_29_28 [6]: EPDis [7]: EPEna 0x00 0xb08 DOEPINT00 - [0]: XferCompl [1]: EPDisbld [2]: AHBErr [3]: SetUp [4]: OUTTknEPdis [5]: StsPhseRcvd [6]: Back2BackSETup 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 546 Ver 0.8.0 0xb09 DOEPINT01 - [0]: OutPktErr [1]: BNAIntr [3]: Reserved_11 [4]: BbleErr [5]: NAKIntrpt [6]: NYETIntrpt [7]: Reserved_15 0x00 0xb0a DOEPINT02 R [7:0]: RESERVED_23_16 0x00 0xb0b DOEPINT03 R [7:0]: RESERVED_31_24 0x00 0xb14 DOEPDMA00 RW [7:0]: DMAAddr0 0x00 0xb15 DOEPDMA01 RW [7:0]: DMAAddr1 0x00 0xb16 DOEPDMA02 RW [7:0]: DMAAddr2 0x00 0xb17 DOEPDMA03 RW [7:0]: DMAAddr3 0x00 0xb1c DOEPDMAB00 R [7:0]: DMABufferAddr0 0x00 0xb1d DOEPDMAB01 R [7:0]: DMABufferAddr1 0x00 0xb1e DOEPDMAB02 R [7:0]: DMABufferAddr2 0x00 0xb1f DOEPDMAB03 R [7:0]: DMABufferAddr3 0x00 0xb20 DOEPCTL10 RW Device Control OUT Endpoint Control Register 1 0x00 0xb21 DOEPCTL11 RW Device Control OUT Endpoint Control Register 1 0x80 0xb22 DOEPCTL12 RW Device Control OUT Endpoint Control Register 1 0x00 0xb23 DOEPCTL13 RW Device Control OUT Endpoint Control Register 1 0x00 0xb28 DOEPINT10 RW Device OUT Endpoint Interrupt Register 1 0x00 0xb29 DOEPINT11 RW Device OUT Endpoint Interrupt Register 1 0x00 0xb2a DOEPINT12 RW Device OUT Endpoint Interrupt Register 1 0x00 0xb2b DOEPINT13 RW Device OUT Endpoint Interrupt Register 1 0x00 0xb30 DOEPTSIZ10 RW Device OUT Endpoint Transfer Size Register 1 0x00 0xb31 DOEPTSIZ11 RW Device OUT Endpoint Transfer Size Register 1 0x01 0xb32 DOEPTSIZ12 RW Device OUT Endpoint Transfer Size Register 1 0x02 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 547 Ver 0.8.0 0xb33 DOEPTSIZ13 RW Device OUT Endpoint Transfer Size Register 1 0x03 0xb34 DOEPDMA10 RW Device OUT Endpoint DMA Address Register 1 0x00 0xb35 DOEPDMA11 RW Device OUT Endpoint DMA Address Register 1 0x00 0xb36 DOEPDMA12 RW Device OUT Endpoint DMA Address Register 1 0x00 0xb37 DOEPDMA13 RW Device OUT Endpoint DMA Address Register 1 0x00 0xb3c DOEPDMAB10 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xb3d DOEPDMAB11 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xb3e DOEPDMAB12 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xb3f DOEPDMAB13 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xb40 DOEPCTL20 RW Device Control OUT Endpoint Control Register 1 0x00 0xb41 DOEPCTL21 RW Device Control OUT Endpoint Control Register 1 0x80 0xb42 DOEPCTL22 RW Device Control OUT Endpoint Control Register 1 0x00 0xb43 DOEPCTL23 RW Device Control OUT Endpoint Control Register 1 0x00 0xb48 DOEPINT20 RW Device OUT Endpoint Interrupt Register 1 0x00 0xb49 DOEPINT21 RW Device OUT Endpoint Interrupt Register 1 0x00 0xb4a DOEPINT22 RW Device OUT Endpoint Interrupt Register 1 0x00 0xb4b DOEPINT23 RW Device OUT Endpoint Interrupt Register 1 0x00 0xb50 DOEPTSIZ20 RW Device OUT Endpoint Transfer Size Register 1 0x00 0xb51 DOEPTSIZ21 RW Device OUT Endpoint Transfer Size Register 1 0x01 0xb52 DOEPTSIZ22 RW Device OUT Endpoint Transfer Size Register 1 0x02 0xb53 DOEPTSIZ23 RW Device OUT Endpoint Transfer Size Register 1 0x03 0xb54 DOEPDMA20 RW Device OUT Endpoint DMA Address Register 1 0x00 0xb55 DOEPDMA21 RW Device OUT Endpoint DMA Address Register 1 0x00 0xb56 DOEPDMA22 RW Device OUT Endpoint DMA Address Register 1 0x00 0xb57 DOEPDMA23 RW Device OUT Endpoint DMA Address Register 1 0x00 0xb5c DOEPDMAB20 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xb5d DOEPDMAB21 RW Device OUT Endpoint Buffer Address Register 1 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 548 Ver 0.8.0 0xb5e DOEPDMAB22 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xb5f DOEPDMAB23 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xb60 DOEPCTL30 RW Device Control OUT Endpoint Control Register 1 0x00 0xb61 DOEPCTL31 RW Device Control OUT Endpoint Control Register 1 0x80 0xb62 DOEPCTL32 RW Device Control OUT Endpoint Control Register 1 0x00 0xb63 DOEPCTL33 RW Device Control OUT Endpoint Control Register 1 0x00 0xb68 DOEPINT30 RW Device OUT Endpoint Interrupt Register 1 0x00 0xb69 DOEPINT31 RW Device OUT Endpoint Interrupt Register 1 0x00 0xb6a DOEPINT32 RW Device OUT Endpoint Interrupt Register 1 0x00 0xb6b DOEPINT33 RW Device OUT Endpoint Interrupt Register 1 0x00 0xb70 DOEPTSIZ30 RW Device OUT Endpoint Transfer Size Register 1 0x00 0xb71 DOEPTSIZ31 RW Device OUT Endpoint Transfer Size Register 1 0x01 0xb72 DOEPTSIZ32 RW Device OUT Endpoint Transfer Size Register 1 0x02 0xb73 DOEPTSIZ33 RW Device OUT Endpoint Transfer Size Register 1 0x03 0xb74 DOEPDMA30 RW Device OUT Endpoint DMA Address Register 1 0x00 0xb75 DOEPDMA31 RW Device OUT Endpoint DMA Address Register 1 0x00 0xb76 DOEPDMA32 RW Device OUT Endpoint DMA Address Register 1 0x00 0xb77 DOEPDMA33 RW Device OUT Endpoint DMA Address Register 1 0x00 0xb7c DOEPDMAB30 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xb7d DOEPDMAB31 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xb7e DOEPDMAB32 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xb7f DOEPDMAB33 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xb80 DOEPCTL40 RW Device Control OUT Endpoint Control Register 1 0x00 0xb81 DOEPCTL41 RW Device Control OUT Endpoint Control Register 1 0x80 0xb82 DOEPCTL42 RW Device Control OUT Endpoint Control Register 1 0x00 0xb83 DOEPCTL43 RW Device Control OUT Endpoint Control Register 1 0x00 0xb88 DOEPINT40 RW Device OUT Endpoint Interrupt Register 1 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 549 Ver 0.8.0 0xb89 DOEPINT41 RW Device OUT Endpoint Interrupt Register 1 0x00 0xb8a DOEPINT42 RW Device OUT Endpoint Interrupt Register 1 0x00 0xb8b DOEPINT43 RW Device OUT Endpoint Interrupt Register 1 0x00 0xb90 DOEPTSIZ40 RW Device OUT Endpoint Transfer Size Register 1 0x00 0xb91 DOEPTSIZ41 RW Device OUT Endpoint Transfer Size Register 1 0x01 0xb92 DOEPTSIZ42 RW Device OUT Endpoint Transfer Size Register 1 0x02 0xb93 DOEPTSIZ43 RW Device OUT Endpoint Transfer Size Register 1 0x03 0xb94 DOEPDMA40 RW Device OUT Endpoint DMA Address Register 1 0x00 0xb95 DOEPDMA41 RW Device OUT Endpoint DMA Address Register 1 0x00 0xb96 DOEPDMA42 RW Device OUT Endpoint DMA Address Register 1 0x00 0xb97 DOEPDMA43 RW Device OUT Endpoint DMA Address Register 1 0x00 0xb9c DOEPDMAB40 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xb9d DOEPDMAB41 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xb9e DOEPDMAB42 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xb9f DOEPDMAB43 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xba0 DOEPCTL50 RW Device Control OUT Endpoint Control Register 1 0x00 0xba1 DOEPCTL51 RW Device Control OUT Endpoint Control Register 1 0x80 0xba2 DOEPCTL52 RW Device Control OUT Endpoint Control Register 1 0x00 0xba3 DOEPCTL53 RW Device Control OUT Endpoint Control Register 1 0x00 0xba8 DOEPINT50 RW Device OUT Endpoint Interrupt Register 1 0x00 0xba9 DOEPINT51 RW Device OUT Endpoint Interrupt Register 1 0x00 0xbaa DOEPINT52 RW Device OUT Endpoint Interrupt Register 1 0x00 0xbab DOEPINT53 RW Device OUT Endpoint Interrupt Register 1 0x00 0xbb0 DOEPTSIZ50 RW Device OUT Endpoint Transfer Size Register 1 0x00 0xbb1 DOEPTSIZ51 RW Device OUT Endpoint Transfer Size Register 1 0x01 0xbb2 DOEPTSIZ52 RW Device OUT Endpoint Transfer Size Register 1 0x02 0xbb3 DOEPTSIZ53 RW Device OUT Endpoint Transfer Size Register 1 0x03 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 550 Ver 0.8.0 0xbb4 DOEPDMA50 RW Device OUT Endpoint DMA Address Register 1 0x00 0xbb5 DOEPDMA51 RW Device OUT Endpoint DMA Address Register 1 0x00 0xbb6 DOEPDMA52 RW Device OUT Endpoint DMA Address Register 1 0x00 0xbb7 DOEPDMA53 RW Device OUT Endpoint DMA Address Register 1 0x00 0xbbc DOEPDMAB50 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xbbd DOEPDMAB51 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xbbe DOEPDMAB52 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xbbf DOEPDMAB53 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xbc0 DOEPCTL60 RW Device Control OUT Endpoint Control Register 1 0x00 0xbc1 DOEPCTL61 RW Device Control OUT Endpoint Control Register 1 0x80 0xbc2 DOEPCTL62 RW Device Control OUT Endpoint Control Register 1 0x00 0xbc3 DOEPCTL63 RW Device Control OUT Endpoint Control Register 1 0x00 0xbc8 DOEPINT60 RW Device OUT Endpoint Interrupt Register 1 0x00 0xbc9 DOEPINT61 RW Device OUT Endpoint Interrupt Register 1 0x00 0xbca DOEPINT62 RW Device OUT Endpoint Interrupt Register 1 0x00 0xbcb DOEPINT63 RW Device OUT Endpoint Interrupt Register 1 0x00 0xbd0 DOEPTSIZ60 RW Device OUT Endpoint Transfer Size Register 1 0x00 0xbd1 DOEPTSIZ61 RW Device OUT Endpoint Transfer Size Register 1 0x01 0xbd2 DOEPTSIZ62 RW Device OUT Endpoint Transfer Size Register 1 0x02 0xbd3 DOEPTSIZ63 RW Device OUT Endpoint Transfer Size Register 1 0x03 0xbd4 DOEPDMA60 RW Device OUT Endpoint DMA Address Register 1 0x00 0xbd5 DOEPDMA61 RW Device OUT Endpoint DMA Address Register 1 0x00 0xbd6 DOEPDMA62 RW Device OUT Endpoint DMA Address Register 1 0x00 0xbd7 DOEPDMA63 RW Device OUT Endpoint DMA Address Register 1 0x00 0xbdc DOEPDMAB60 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xbdd DOEPDMAB61 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xbde DOEPDMAB62 RW Device OUT Endpoint Buffer Address Register 1 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 551 Ver 0.8.0 0xbdf DOEPDMAB63 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xbe0 DOEPCTL70 RW Device Control OUT Endpoint Control Register 1 0x00 0xbe1 DOEPCTL71 RW Device Control OUT Endpoint Control Register 1 0x80 0xbe2 DOEPCTL72 RW Device Control OUT Endpoint Control Register 1 0x00 0xbe3 DOEPCTL73 RW Device Control OUT Endpoint Control Register 1 0x00 0xbe8 DOEPINT70 RW Device OUT Endpoint Interrupt Register 1 0x00 0xbe9 DOEPINT71 RW Device OUT Endpoint Interrupt Register 1 0x00 0xbea DOEPINT72 RW Device OUT Endpoint Interrupt Register 1 0x00 0xbeb DOEPINT73 RW Device OUT Endpoint Interrupt Register 1 0x00 0xbf0 DOEPTSIZ70 RW Device OUT Endpoint Transfer Size Register 1 0x00 0xbf1 DOEPTSIZ71 RW Device OUT Endpoint Transfer Size Register 1 0x01 0xbf2 DOEPTSIZ72 RW Device OUT Endpoint Transfer Size Register 1 0x02 0xbf3 DOEPTSIZ73 RW Device OUT Endpoint Transfer Size Register 1 0x03 0xbf4 DOEPDMA70 RW Device OUT Endpoint DMA Address Register 1 0x00 0xbf5 DOEPDMA71 RW Device OUT Endpoint DMA Address Register 1 0x00 0xbf6 DOEPDMA72 RW Device OUT Endpoint DMA Address Register 1 0x00 0xbf7 DOEPDMA73 RW Device OUT Endpoint DMA Address Register 1 0x00 0xbfc DOEPDMAB70 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xbfd DOEPDMAB71 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xbfe DOEPDMAB72 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xbff DOEPDMAB73 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xc00 DOEPCTL80 RW Device Control OUT Endpoint Control Register 1 0x00 0xc01 DOEPCTL81 RW Device Control OUT Endpoint Control Register 1 0x80 0xc02 DOEPCTL82 RW Device Control OUT Endpoint Control Register 1 0x00 0xc03 DOEPCTL83 RW Device Control OUT Endpoint Control Register 1 0x00 0xc08 DOEPINT80 RW Device OUT Endpoint Interrupt Register 1 0x00 0xc09 DOEPINT81 RW Device OUT Endpoint Interrupt Register 1 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 552 Ver 0.8.0 0xc0a DOEPINT82 RW Device OUT Endpoint Interrupt Register 1 0x00 0xc0b DOEPINT83 RW Device OUT Endpoint Interrupt Register 1 0x00 0xc10 DOEPTSIZ80 RW Device OUT Endpoint Transfer Size Register 1 0x00 0xc11 DOEPTSIZ81 RW Device OUT Endpoint Transfer Size Register 1 0x01 0xc12 DOEPTSIZ82 RW Device OUT Endpoint Transfer Size Register 1 0x02 0xc13 DOEPTSIZ83 RW Device OUT Endpoint Transfer Size Register 1 0x03 0xc14 DOEPDMA80 RW Device OUT Endpoint DMA Address Register 1 0x00 0xc15 DOEPDMA81 RW Device OUT Endpoint DMA Address Register 1 0x00 0xc16 DOEPDMA82 RW Device OUT Endpoint DMA Address Register 1 0x00 0xc17 DOEPDMA83 RW Device OUT Endpoint DMA Address Register 1 0x00 0xc1c DOEPDMAB80 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xc1d DOEPDMAB81 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xc1e DOEPDMAB82 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xc1f DOEPDMAB83 RW Device OUT Endpoint Buffer Address Register 1 0x00 0xe00 PCGCCTL0 - Power and Clock Gating Control Register [0]: StopPclk [1]: GateHclk [2]: PwrClmp [3]: RstPdwnModule [5]: Enbl_L1Gating [6]: PhySleep [7]: L1Suspended 0x00 0xe01 PCGCCTL1 - [0]: Reserved_8 [1]: RestoreMode [4:2]: Reserved_12_10 [5]: EssRegRestored [7:6]: prt_clk_sel 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 553 Ver 0.8.0 0xe02 PCGCCTL2 RW Power and Clock Gating Control Register [2:1]: mac_xcvrselect [3]: mac_termselect [7:4]: mac_dev_addr_23_20 0x00 0xe03 PCGCCTL3 RW [2:0]: mac_dev_addr_26_24 [4:3]: p2hd_dev_enum_spd [6:5]: p2hd_prt_spd [7]: if_dev_mode 0x00 0xe04 PCGCCTL10 RW [0]: GateEN [2:1]: counter [3]: RAMGateEN [7:4]: RESERVED_15_8 0x00 0xe05 PCGCCTL11 R [7:0]: RESERVED_15_8 0x00 0xe06 PCGCCTL12 R [7:0]: RESERVED_23_16 0x00 0xe07 PCGCCTL13 R [7:0]: RESERVED_31_24 0x00 0xf00 STAR_FIX_DISABLE0 RW [7:0]: STAR_FIX_DISABLE0 0x00 0xf01 STAR_FIX_DISABLE1 RW [7:0]: STAR_FIX_DISABLE1 0x20 0xf02 STAR_FIX_DISABLE2 RW [7:0]: STAR_FIX_DISABLE2 0x00 0xf03 STAR_FIX_DISABLE3 RW [7:0]: STAR_FIX_DISABLE3 0x00 0x60000 USBPHY_CT0 RW [0]: r_phy_refeclk_mode [1]: r_resved [2]: r_phy_self_test [3]: r_phy_release_auto [4]: r_phy_release_ow [5]: r_phy_pll_en_val [6]: r_phy_suspendm_val [7]: r_phy_rst_val 0x8b Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 554 Ver 0.8.0 0x60001 USBPHY_CT1 RW [0]: r_pwr_switch [1]: r_test_bypass_lp [2]: r_sof_sel [3]: r_suspend_sel [4]: r_suspend_polar [5]: r_resved 0x11 0x60002 USBPHY_CT2 RW [3:0]: pll_en_cnt [7:4]: suspend_cnt 0x21 0x60003 USBPHY_CT3 RW [5:0]: phy_rst_cnt 0x0f 0x60005 USBPHY_CT5 RW [0]: r_suspend_mask 0x00 0x60007 USBPHY_READ RW [0]: phy_test_bist_i [1]: phy_dto_i 0x00 0x60008 USB_TSTAMP0 R Bit 7-0 of System timer tick value that is latched via SOF 0x00 0x60009 USB_TSTAMP1 R Bit15-8 of System timer tick value that is latched via SOF 0x00 0x6000a USB_TSTAMP2 R Bit23-16 of System timer tick value that is latched via SOF 0x00 0x6000b USB_TSTAMP3 R Bit31-24 of System timer tick value that is latched via SOF 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 555 Ver 0.8.0

13 Telink Rapid Keyscan Handler (TRKH)

Telink Rapid Keyscan Handler (TRKH) is Telink proprietary keyscan solution, which includes both digital keyscan and analog keyscan.

13.1 Digital Keyscan

13.1.1 Overview of Digital Keyscan

The SoC supports Telink digital keyscan for detecting 8 rows x 16 columns matrix keyboards, which is essentially a row-column scan. Since the column scan is increased 3 at a time, it supports 8 x 18 keyboards. Telink digital keyscan supports hardware debounce functi on.

13.1.2 Principle of Digital Keyscan

Telink digital keyscan uses the IO ports of PA, PB, PC, PD, PE, PF, PG, PH (PA[5]/PA[6]/PA[7] are not available) to control the reading of keys. It configures 8 I/O lines as row lines and 16 I/O lines as column lines, creating a matrix of 8x16 keys. Each key is positioned at the intersection of a row and column. The digital keyscan performs a row-column scan to identify the speci fic key location and determine its value. Figure 13-1 Digital Keyscan Schematic The chip hardware assigns a number to each I/O port that can be reused for the digital keyscan functionality. Below is the pin assignment table: S0 S1 S2 S3 S12 S13 S14 S15 S0 S1 S2 S3 S12 S13 S14 S15 S0 S1 S2 S3 S12 S13 S14 S15 S0 S1 S2 S3 S12 S13 S14 S15 S0 S1 S2 S3 S12 S13 S14 S15 S0 S1 S2 S3 S12 S13 S14 S15 S0 S1 S2 S3 S12 S13 S14 S15 S0 S1 S2 S3 S12 S13 S14 S15 ROW0 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 Column0 Column1 Column2 Column3 Column12 Column13 Column14 Column15

Datasheet for Telink TL3828 DS-TL3828-E5 556 Ver 0.8.0 Table 13-1 Pad Number for Keyscan Set address 0x80140704~0x80140708 (KS_ROW_SEL) to select 8 pins as rows, then set address 0x80140700~0x80140703 (KS_COL_MSK) to select 16 pins from the remaining pins as columns. The digital keyscan scans keyboards via row-column selection. After scanning, the row-column number is recorded in the KS_KEY buffer, the corresponding row-column number is read in the end_flag int errupt to determi ne the key.

13.1.3 Hardware Debounce

Telink digital keyscan implements the hardware debounce function. The dynamic range of debounce supports 4ms/8ms/12ms/16ms/20ms/24ms multi-block debounce cycle, and supports up to 2 times of debounce cycles. The keyscan compares the data of adjacent debounce cycles, and only deposit it into the FIFO for reporting if they are consistent. Pad Number Pad Number Pad Number Pad Number PA[0] PA_KS_0 PB[0] PA_KS5 PC[0] PB_KS5 PD[0] PC_KS5 PA[1] PA_KS1 PB[1] PA_KS6 PC[1] PB_KS6 PD[1] PC_KS6 PA[2] PA_KS2 PB[2] PA_KS7 PC[2] PB_KS7 PD[2] PC_KS7 PA[3] PA_KS3 PB[3] PB_KS0 PC[3] P C_KS0 PD[3] PD_KS0 PA[4] PA_KS4 PB[4] PB_KS1 PC[4] PC_KS1 PD[4] PD_KS1 - - PB[5] PB_KS2 PC[5] PC_KS2 PD[5] PD_KS2 - - PB[6] PB_KS3 PC[6] PC_KS3 PD[6] PD_KS3 - - PB[7] PB_KS4 PC[7] PC_KS4 PD[7] PD_KS4 PE[0] PD_KS5 PF[0] PA_KS5 PG[0] PB_KS5 PH[0] PC_KS5 PE[1] PD_KS6 PF[1] PA_KS6 PG[1] PB_KS6 PH[1] PC_KS6 PE[2] PD_KS7 PF[2] PA_KS7 PG[2] PB_KS7 PH[2] PC_KS7 PE[3] PA_KS0 PF[3] PB_KS0 PG[3] PC_KS0 PH[3] PD_KS0 PE[4] PA_KS1 PF[4] PB_KS1 PG[4] PC_KS1 PH[4] PD_KS1 PE[5] PA_KS2 PF[5] PB_KS2 PG[5] PC_KS2 PH[5] PD_KS2 PE[6] PA_KS3 PF[6] PB_KS3 PG[6] PC_KS3 PH[6] PD_KS3 PE[7] PA_KS4 PF[7] PB_KS4 PG[7] PC_KS4 PH[7] PD_KS4 NOTE:

• For column, use PB_KS[7:0], PC_KS[7:0], PD_KS[7:1] as much as possible.
• Row number is fixed to 8, if less than 8 rows are to be used, make the unused pins floating.

Datasheet for Telink TL3828 DS-TL3828-E5 557 Ver 0.8.0

13.1.4 Susepend/Wakup

The digital keyscan is able to wake up the system following the debounce cycle. The Keyscan module works on a crystal clock or 32 kHz RC oscillator, so it can work when it is asleep. The interrupts are reported following the debounce cycle (8ms/12ms/16ms), or application layer readouts at regular intervals. The purpose of this is to reduce the time spent on the temporary UI and to reduce power consumpti on.

13.1.5 FIFO Depth

The FIFO is expected to hold 31 keys. If less than 8 keys are expected per debounce cycle, it is necessary to remove all keys in four debounce cycles.

13.1.6 Register Description of Digital Keyscan

The digital keyscan related registers are listed in the following table. The base address for the following keyscan related registers is 0x80140700. Table 13-2 Register Table for Digital Keyscan Address Offset Name Type Description Default Value 0x00 KS_COL_MSK0 RW Keyscan column mask for PD_KS[7:0] 0x00 0x01 KS_COL_MSK1 RW Keyscan column mask for PC_KS[7:0] 0x00 0x02 KS_COL_MSK2 RW Keyscan column mask for PB_KS[7:0] 0x00 0x03 KS_COL_MSK3 RW Keyscan column mask for PA_KS[7:0] 0x00 0x04 KS_ROW_SEL0 RW [4:0]: keyscan row select for row0 [7:5]: keyscan row select for row1[2:0] 0x00 0x05 KS_ROW_SEL1 RW [1:0]: keyscan row select for row1[4:3] [6:2]: keyscan row select for row2 [7]: keyscan row select for row3[0] 0x00 0x06 KS_ROW_SEL2 RW [3:0]: keyscan row select for row3[4:1] [7:4]: keyscan row select for row4[3:0] 0x00 0x07 KS_ROW_SEL3 RW [0]: keyscan row select for row4[4] [5:1]: keyscan row select for row5 [7:6]: keyscan row select for row6[1:0] 0x08 KS_ROW_SEL4 RW 2:0]: keyscan row select for row6[4:2] [7:3]: keyscan row select for row7 0x00 0x09 KS_END_FLG RW [7:0] Keyscan frame end flag 0xff

Datasheet for Telink TL3828 DS-TL3828-E5 558 Ver 0.8.0 0x0a KS_EN RW [0]: Keyscan enable [1]: Keyscan 32k Hz clock enable [2]: Keyscan interrupt enable [3]: Keyscan input invert [4]: Keyscan output invert [5]: Keyscan scan mode select, 1’b0 for mode 0, 1’b1 for mode 1 [6]: Keyscan manually reset [7]: Keyscan tripple check disable 0x07 0x0b KS_FRM_NUM RW [4:0]: Keyscan empty frame counter number [7:5]: debounce_period: debounce period 2->8ms, 3- >12ms, 4->16ms, 5->20ms 0x41 0x0c KS_IRQ R [4:0]: Keyscan read pointer for key buffer [7]: Keyscan interrupt 0x00 0x0d KS_RPTR R [4:0]: Keyscan latched write pointer when frame end [6]: Keyscan cap key detect when in any state [7]: Keyscan state, 1’b0 for IDLE, 1’b1 for SCAN 0x00 0x0e KS_WPTR R [4:0]: Keyscan write pointer for key buffer [5]: Keyscan no key detect when in SCAN state [6]: Keyscan key detect when in IDLE state [7]: Keyscan internal counter128 count enable 0x00 0x0f KS_GATED R [2:0]: CNT_H, Keyscan counter128[6:4] [3]: RXDONE_IRQ, Keyscan dma rxdone status; W1C?clr irq [4]: GATED_CLR, Keyscan 32k Hz clock gated clear [5]: GAYED, Keyscan 32k Hz clock gated [6]: CNT16_EN, Keyscan internal counter16 count enable [7]: KS_WAKE_UP, Keyscan wake up status 0x00 0x10 KS_KEY Volatile [7:0]: KS_KEY, Keyscan key value 0xff 0x11 KS_LPTR R [4:0]: LPTR, Keyscan loop pointer [7:5]: RPTR_RD, Keyscan read pointer when frame end 0x00 0x12 KS_CNT128 R [6:0]: CNT, Keyscan counter128 count value 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 559 Ver 0.8.0 0x13 KS_CNT16 R [3:0]: CNT_16, Keyscan counter16 count value [6:4]: ROW_NUM, Keyscan latched row number 0x00 0x14 KS_CTRL0 RW [0]: pem_event_en, PEM envent [2:1]: pem_task_en, PEM task enable [3]: Not_used [7:4]: ADC_SAMPLE, Sample rate 0x70 0x15 KS_A_EN0 RW [0]: KS_A_IE0, Keyscan interrupt enable for ADC [1]: KS_A_IE1, Keyscan interrupt enable for ADCX2 [2]: CAPTURE_SEL, Cpature sel always on [3]: CAPTURE_IO, Release IO after Capture stop [4]: RXDMA_EN, Keyscan DMA enable [5]: RXDONE_IE, Keyscan rxdone interrupt enable [7:6]: RXDMA_CACHE, Keyscan manually reset_n 0x08 0x16 KS_A_EN1 RW [0]: KS_A_EN, Keyscan-A enable [1]: CLK_A_EN, Keyscan 32k Hz clock enable [2]: MOD_A, Keyscan scan mode select, 1’b0 for mode 0, 1’b1 for mode 1 and Analog scan being to 1 [3]: ADC_EN, Sar ADC0/ADC1 enable [4]: ADC_SEL, Sar ADC1 enable [5]: Not_used [7:6]: io_mux, Keyscan-A output support mux 0x08 0x17 KS_A_SETL0 RW [7:0]: SETL_TIME, Settle time the scan period 0xFF 0x18 KS_A_SETL1 RW [6:0]: SETL_CAPTURE, Settle time when Capture start for ADC0 Setl_capture = 0x18 X 2 0x10 0x19 KS_A_SETL2 RW [6:0]: SETL_CAPTURE1, Settle time when Capture start for ADC1 Setl_capture = 0x19 X 2 0x20 0x1a KS_A_SETL3 RW [7:0]: SETL_TIME_PWR, Settle time the power manager Setl_time_pwr = 0x1a X 4 0xFF 0x1b KS_A_SETL4 RW [7:0]: SETL_TIME_SCAN, Settle time the start time of scan after the Power, Setl_time_scan = 0x1b X 4 0x30 0x1c KS_BUFFER_DMA0 Volatile [7:0]: col_va0 0x00 0x1d KS_BUFFER_DMA1 Volatile [7:0]: col_va1 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 560 Ver 0.8.0 0x1e KS_BUFFER_DMA2 Volatile [7:0]: col_va2 0x00 0x1f KS_BUFFER_DMA3 Volatile [7:0]: col_va3 0x00 0x20 PWR_SETL0 RW [7:0]: PWR_ON0, Power on gpio 0, PWR_ON = 0x20 X 4 0x00 0x21 PWR_SETL1 RW [7:0]: PWR_ON1, Power on gpio 1, PWR_ON = 0x21 X 4 0x10 0x22 PWR_SETL2 RW [7:0]: PWR_ON2, Power on gpio 2, PWR_ON = 0x2 X 4 0x20 0x23 PWR_SETL3 RW [7:0]: PWR_ON3, Power on gpio 3, PWR_ON = 0x23 X 4 0x30 0x24 PWR_SETL4 RW [7:0]: PWR_ON4, Power on gpio 4, PWR_ON = 0x24 X 4 0x40 0x25 PWR_SETL5 RW [7:0]: PWR_ON5, Power on gpio 5, PWR_ON = 0x25 X 4 0x50 0x26 PWR_SETL6 RW [7:0]: PWR_ON6, Power on gpio 6, PWR_ON = 0x26 X 4 0x60 0x27 PWR_SETL7 RW [7:0]: PWR_ON7, Power on gpio 7, PWR_ON = 0x27 X 4 0x70 0x28 PWR_DN_SETL0 RW [7:0]: PWR_DOWN0, Power down gpio 0 PWR_DOWN = 0x20 X 4 0x60 0x29 PWR_DN_SETL1 RW [7:0]: PWR_DOWN1, Power down gpio 1 PWR_DOWN = 0x21 X 4 0x70 0x2a PWR_DN_SETL2 RW [7:0]: PWR_DOWN2, Power down gpio 2 PWR_DOWN = 0x2 X 4 0x80 0x2b PWR_DN_SETL3 RW [7:0]: PWR_DOWN3, Power down gpio 3 PWR_DOWN = 0x23 X 4 0x90 0x2c PWR_DN_SETL4 RW [7:0]: PWR_DOWN4, Power down gpio 4 PWR_DOWN = 0x24 X 4 0xa0 0x2d PWR_DN_SETL5 RW [7:0]: PWR_DOWN5, Power down gpio 5 PWR_DOWN = 0x25 X 4 0xb0 0x2e PWR_DN_SETL6 RW [7:0]: PWR_DOWN6, Power down gpio 6 PWR_DOWN = 0x26 X 4 0xc0 0x2f PWR_DN_SETL7 RW [7:0]: PWR_DOWN7, Power down gpio 7 PWR_DOWN = 0x27 X 4 0xd0 0x30 KS_BUFFER_0 Volatile [7:0]: col_lat_read0 0x00 0x31 KS_BUFFER_1 Volatile [7:0]: col_lat_read1 0x00 0x32 KS_BUFFER_2 Volatile [7:0]: col_lat_read2 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 561 Ver 0.8.0 0x33 KS_BUFFER_3 Volatile [7:0]: col_lat_read3 0x00 0x34 KSA_STATUS R [0]: FRM_END, Keyscan-A ADC interrupt and W1C clear irq [1]: FRM_END1, Keyscan-A 2X ADC interrupt and W1C clear irq [2]: KS_WAKEA_UP, Keyscan wake-A up status [3]: KS_WAKEA1_UP, Keyscan wake-A1 up status [4]: SCNA_EN, Keyscan-A SCAN enable [7:5]: CNT_CAPTURE1, Capture1 cnt for ADC1 0x00 0x35 PWR_PTR R [7:0]: CNT_PWR, Keyscan-A Power cnt 0x00 0x36 SCAN_PTR R [7:0]: CNT_SCAN, Keyscan-A SCAN cnt 0x00 0x37 CAPTURE_PTR R [3:0]: CNT_CAPTURE_IO, Keyscan-A CAPTUTE IO cnt [6:4]: CNT_CAPTURE, Capture cnt for ADC0 [7]: CAPTURE_EN, capture enable 0x00 0x38 KS_A_EN2 RW [0]: PWR_SWITCH_MANUAL, Manual configure Power gpio enable [1]: CHANNEL_SWITCH_MANUAL, Manual configure Channel switch enable [2]: IRQ_DLY_EN, Keyscan interrupt delay enable for ADC [3]: SETL_TIME_SCAN2_EN, Scan X2 during each power on [4]: SCAN2_EN_IO, Scan X2 during each power on and reduce the Hall key time via IO, need SETL_TIME_SCAN2_EN to 1 [5]: SCAN2_EN, Scan X2 during each power on and reduce the Hall key time via scan [6]: Not_used, 0x04 0x39 PWR_SWITCH_VAL RW [7:0]: PWR_SWITCH_VAL, Manually configure Power gpio 0x00 0x3a CHANNEL_SWITCH_ VAL RW [3:0]: CHANNEL_SWITCH_VAL, Manually configure channel switch 0x00 0x3b KS_A_SETL5 RW [7:0]: SETL_TIME_SCAN2_EN, Settle time the second start time of scan after the Power Setl_time_scan2 = 0x3 X 4 0x80 Address Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 562 Ver 0.8.0

13.2 Analog Keyscan

13.2.1 Overview of Analog Keyscan

The analog keyscan collects ADC data corresponding to 128 keys using the SAR ADC and keyscan control logic. The SAR ADC supports up to 16 channels. The keyscan supports up to 8 rows and 16 columns, and up to 128 keys.

13.2.2 Features of Analog Keyscan

The features of analog keyscan are:

• Supports DMA function
• Maximum 12-bit conversion rate of 2 M samples/s sampling rate
• Up to 8 rows and 16 columns (select from 32 pi ns)
• Normal (Max to 8 MHz) operating mode
• SAR x 2

13.2.3 Block Diagram of Analog Keyscan

The main components of the Analog Scan are keyscan, sar_adc_ctrl_dig, sar_adc, and the external device Analog Switch. The key matrix can be configured with 8 rows x 16 columns of GPIOs. (note: it is important to see when the actual number of keys is small, whether the configuration ensures proper operation). Each Analog Switch has 16 inputs correspondi ng to the Nth column of each row of the key matrix. Depending on the number of columns, the outputs of 8 external Analog Switches are fed to the SAR ADC, which can be switched by adc_sel_ain in sar_adc_ctrl_dig, where adc_sel_ain is controlled by the hardware of keyscan module. The SAR ADC stores the sampled data of each key directly into SRAM via DMA. The following figure shows the block di agram of the analog keyscan with one ADC and the analog switch corresponding to 16-MUX-1. Figure 13-2 Block Diagram of Analog Keyscan with One ADC

Datasheet for Telink TL3828 DS-TL3828-E5 563 Ver 0.8.0 The following figure shows the block diagram of the analog keyscan with two ADCs and the analog switch corresponding to 16-MUX-1. Figure 13-3 Block Diagram of Analog Keyscan with Two ADCs The analog switch 16-MUX-1 solution only requires 8 ADC channels as analog switches, needing just 8 IO pins without pulling additional IOs from the digital side. Additionally, 8 IO pins are needed for power control and 4 for channel switching. Two channels of sar_adc_ctrl_di g report the data, keyscan regulates the sampling interval of two ADCs, and the time can be configured. The two ADCs are responsible for 128/2 keys respectively, which is equivalent to collecting 128/2 keys twice in 125µs.

13.2.4 Power-on and Scan

13.2.4.1 Power-on

The power-on time is configurable. A typical power-on time is 40µs. The power-on solution is as below. Table 13-3 Power-on and Power-off Time The timing sequence diagram for the analog keyscan i s shown as below. Symbol Parameter Test Condition Min. Typ. Max. Unit tPON Power-on time T = 25°C - 40 - µs tPOFF Power-off time T = 25°C - 1 - µs

Datasheet for Telink TL3828 DS-TL3828-E5 564 Ver 0.8.0 Figure 13-4 Timing Sequence of Analog Keyscan

13.2.4.2 Scanning

(1) One ADC mode Refer to Figure 13-2 Block Diagram of Analog Keyscan with One ADC, the scanning rule is as below.

• The first row is powered up and waiting for 40us, start scanning
• The second row is powered up after 10us of the first row power-up;
• The third row is powered up after 20us of the first row power-up;
• The fourth row is powered up after 30us of the first row power-up;
• The fi fth row is powered up after 40us of the first row power-up, while the first row is powered off;
• The sixth row is powered up after 50us of the first row power-up, while the second row is powered off;
• The seventh row is powered up after 60us of the first row power-up, while the third row is powered off;
• The eighth row is powered up after 70us of the first row power-up, while the fourth row i s powered off;
• After the eighth row is powered up for 20us (scanning), all rows are powered off. The second row is powered up after the first row is powered up for 10us, which will see the stabilization of the magnetic or optical axes affecting the time calculation; therefore, it is recommended that the power-up of each row can be adjusted by setting the parameters, and designing with 200ns or 500ns. The keypad acqui res values as follows Key values are acquired within 20us of powering up each row. Channel Switch: ...

Datasheet for Telink TL3828 DS-TL3828-E5 565 Ver 0.8.0 (2) Two ADCs mode Refer to Figure 13-3 Block Diagram of Analog Keyscan with Two ADCs, the scanning rule is as below.

• The first row is powered up and waiting for 40us, start scanning
• The second row is powered up after 10us of the first row power-up;
• The third row is powered up after 20us of the first row power-up;
• The fourth row is powered up after 30us of the first row power-up;
• The fi fth row is powered up after 40us of the first row power-up, while the first row is powered off;
• The sixth row is powered up after 50us of the first row power-up, while the second row is powered off;
• The seventh row is powered up after 60us of the first row power-up, while the third row is powered off;
• The eighth row is powered up after 70us of the first row power-up, while the fourth row i s powered off;
• After the eighth row is powered up for 20us (scanning), all rows are powered off. The keypad acquires values as follows Key values are acquired within 20us of power up for each row. Channel Switch: First ADC is responsible for Analog Swich 0 - 3. ... The second ADC is responsible for Analog Swich 4 - 7. ... Through DMA it uploads data, 125us/62.5us interrupt comes once, make sure that the second bunch of data wi ll not overwrite the first.

Datasheet for Telink TL3828 DS-TL3828-E5 566 Ver 0.8.0

14 SAR ADC

The SoC integrates two identical SAR ADC module, SAR ADC0 and SAR ADC1. SAR ADC0 can be used to sample analog input signals such as battery voltage and temperature sensor. SAR ADC1 is identical to SAR0 in all features, except it lacks battery voltage sampling. Here take the SAR ADC0 as an example. The diagram of SAR ADC0 module is shown in figure below. Figure 14-1 Diagram of ADC0

14.1 Power On/Down

The SAR ADC is disabled by default. To power on the ADC, the analog register adc_pd (afe_0x27c<5>) should be set as 1’b0.

14.2 ADC Clock

The ADC clock is derived from sar_adc_dig_clk, with frequency dividing factor configured via the analog register adc_clk_div (afe_0x274<3:0>). There are three selectable clock sources for sar_adc_dig_clk: RC_24M derived from 24 MHz RC oscillator, 24 MHz crystal, and pll clk. The sources are selectable via register SC_BASE (0x80140800)+0x1b[5:4], SC_BASE (0x80140800)+0x1b[3:0] (divide) and SAR_BASE 0x80101400)+0x29[3:0] are used as divider. sar_adc_dig_clk = source clk / (SC_BASE+0x1b[3:0]*SAR_BASE+0x29[3:0]) ADC clock frequency (marked as FADC_clk) = sar_adc_dig_clk / (adc_clk_div+1) NOTE: The highest sample rate of SAR ADC is 2MHz. In this case, set SC_BASE+0x1b[5:4] to 2’b11 to select pll clk as the source clok of sar_adc_dig_clk. After clock division, the sar_adc_dig_clk and FADC_clk should be 48MHz. PC[1] PC[6] 0x1 0x2 0x7 adc_ain_p adc_ain_n adc_en_diff PC[0] ADC Differential mode positive input negative input afe_0x26c<6> FIFO afe_0x272<3> Set to 0 to enable translate data to fifo PC[2] 0x3 PC[3] 0x4 PC[4] 0x5 PC[7] 0x8 PC[5] 0x6 vbat (P port) 0xb gnd (N port) 0xb temp. sensor 0x9

Datasheet for Telink TL3828 DS-TL3828-E5 567 Ver 0.8.0

14.3 ADC Control in Auto Mode

14.3.1 Set Max State and Enable Channel

The SAR ADC supports up to 3 channels including left channel, right channel and Misc channel. The left, right and Misc channels all consist of one “Set” state and one “Capture” state.

• The digital register r_max_scnt (0x28[6:4]) serves to set the max state index. As shown below, the r_max_scnt should be set as 0x06.
• The Misc channel can be enabled via r_en_misc (0x2a[0]).
• The left channel can only be enabled via r_en_left (0x2a[1]) when the misc channel is enabled.
• The right channel can only be enabled via r_en_right (0x2a[2]) when the left channel i s enabled. 14.3.2 “Set” State The length of “Set” state for the Misc channel is configurable via the digital register r_max_s_m (0x06[3:0]). “Set” state duration (marked as Tsd) = r_max_s_m / sar_adc_dig_clk. The length of “Set” state for the left channel is configurable via the digital register r_max_s_l (0x07[3:0]). “Set” state duration (marked as Tsd) = r_max_s_l / sar_adc_dig_clk. The length of “Set” state for the right channel is configurable via the digital register r_max_s_r (0x08[3:0]). “Set” state duration (marked as Tsd) = r_max_s_r / sar_adc_dig_clk. Each “Set” state serves to set ADC control signals for the Misc/left/right channel via corresponding registers, including:
• adc_en_diff: afe_0x26c<6>. MUST set as 1’b1 to select differential input mode.
• adc_ain_p: digital register 0x34[3:0] (Misc channel), 0x35[3:0] (left channel), 0x36[3:0] (right channel). Select positive input in differential mode.
• adc_ain_n: digital register 0x34[7:4] (Misc channel), 0x35[7:4] (left channel), 0x36[7:4] (right channel). Select negative input in differential mode.
• adc_vref: digital register 0x06[7:6] (Misc channel), 0x07[7:6] (left channel), 0x 08[7:6] (right channel). Set reference voltage VREF. ADC maximum input range is determined by the ADC reference voltage.
• adc_sel_ai_scale: digital register 0x06[5:4] (Misc channel), 0x07[5:4] (left channel), 0x08[5:4] (right channel). Set scaling factor for ADC analog input as 1 (default), or 1/4, or 1/8. By setting this scaling factor, ADC maximum input range can be extended based on the VREF. For example, suppose the VREF is set as 1.2V: Since the scaling factor is 1 by default, the ADC maximum input range should be 0 ~ 1.2V (negative input is GND). Set Capture 1 2 3 4 5 6 Set Capture Set Capture

Datasheet for Telink TL3828 DS-TL3828-E5 568 Ver 0.8.0 If the scaling factor is set as 1/8, in theory ADC maximum input range should change to 0 ~ 9.6V, due to the maximum (negative input is GND). But limited by input voltage of the chip’s PAD, the actual range is 0 ~ 3.6V.

• adc_res: afe_0x26c<1:0>. Set resolution as 8/10/12 bits. ADC data is always 16-bit format no matter what the resolution is set. For example, 12 bits resolution indicates ADC data consists of 12-bit valid data and 4-bit sign extension bit.
• Digital register 0x03[3:0] (Misc channel), 0x03[7:4] (left channel), 0x04[3:0] (right channel). Set sampling time which determi nes the speed to stabilize input signals. Sampling time (marked as Tsamp) = adc_tsamp / FADC_clk. The lower sampling cycle, the shorter ADC convert time. 14.3.3 “Capture” State For the Misc channel, left channel and right channel, at the beginning of their “Capture” state, a “run” signal is issued automatically to start an ADC sampling and conversion process; at the end of “Capture” state, ADC output data is captured.
• The length of “Capture” state of Misc channel is configurable via the digital register r_max_c_m[9:0] “Capture” state duration for Misc channel (marked as Tcd) = r_max_c_m / sar_adc_dig_clk.
• The length of “Capture” state of left channel is configurable via the digital register r_max_c_l[9:0] “Capture” state duration for left channel (marked as Tcd) = r_max_c_l / sar_adc_dig_clk.
• The length of “Capture” state of right channel is configurable via the digital register r_max_c_r[9:0] “Capture” state duration for right channel (marked as Tcd) = r_max_c_r / sar_adc_dig_clk.
• The “VLD” bit (afe_0x276<0>) will be set as 1’b1 at the end of “Capture” state to indicate the ADC data is valid, and this flag bit will be cleared automatically.
• The 16-bit ADC output data can be read from the analog register adc_dat[15:0] (afe_0x278<7:0>, afe_0x277<7:0>) while the afe_0x273<0> is set as 1’b0 (default). If the afe_0x273<0> is set as 1’b1, the data in the afe_0x278 and afe_0x277 won’t be updated. NOTE: The total duration “Ttd”, which is the sum of the length of “Set” state and “Capture” state, determines the sampling rate. Sampling frequency (marked as Fs) = 1 / Ttd

Datasheet for Telink TL3828 DS-TL3828-E5 569 Ver 0.8.0

14.3.4 Usage Case with Detailed Register Setting

14.3.4.1 1-channel Sampling for Misc Channel Figure 14-2 Misc Channel Sampling In this case, set the digital register 0x2a[0] to 1'b1 to enable the Misc channel. Set the maximum state index to “2” by configuring the digital register 0x28[6:4] to 3'h2. The total duration (marked as Ttd) = (1 * r_max_s_m + 1 * r_max_c_m) / sar_adc_dig_clk. 14.3.4.2 2-channel Sampling for Misc and Left Channel Figure 14-3 Misc and Left Channel Sampling In this case, set the digital register 0x2a[1:0] to 2’b11 to enable the Misc channel and left channel. Set the maximum state index to “4” by configuring the digital register 0x28[6:4] to 3’h4. The total duration (marked as Ttd) = (r_max_s_m + r_max_c_m + r_max_s_l + r_max_m_l) / sar_adc_dig_clk. MISC r_max_s_m set capture r_max_c_m MISC r_max_s_m set capture r_max_c_m Left r_max_s_l set capture r_max_c_l

Datasheet for Telink TL3828 DS-TL3828-E5 570 Ver 0.8.0 14.3.4.3 3-channel Sampling for Misc, Left and Left Channel Figure 14-4 Misc, Left and Right Channel Sampling In this case, set the digital register 0x2a[2:0] to 3’b111 to enable the Misc channel, left channel and right channel. Set the maximum state index to “6” by configuring the digital register 0x28[6:4] to 3’h6. The total duration (marked as T td) = (r_max_s_m + r_max_c_m + r_max_s_l + r_max_m_l + r_max_s_r + Table 14-1 Overall Register Setting Table 14-2 Register Setting for L/R/M Channel Function Register Setting P; power on the ADC afe_0x27c<5> = 1’b0 Set FADC_clk (ADC clock frequency) afe_0x274<3:0> = 5 FADC_clk = sar_adc_dig_clk / (5+1) Enable the Misc, left and right channel digital register 0x2a[2:0] = 3’b111 Set the max state index as “6” digital register 0x28[6:4] = 3’h6 Function Left Channel Register Setting Right Channel Register Setting Misc Channel Register Setting Set Tsd (“Set” state duration) SAR_ADC digital register 0x07[3:0] = 4’d10 SAR_ADC digital register 0x08[3:0] = 4’d10 SAR_ADC digital register 0x06[3:0] = 4’d10 Set Tcd (“Capture” state duration) SAR_ADC digital register 9’h1ea SAR_ADC digital register 9’h1ea SAR_ADC digital register 9’h1ea Ttd_* Ttd_l = sar_adc_dig_clk Ttd_r = sar_adc_dig_clk Ttd_m = sar_adc_dig_clk Ttd (total duration) Ttd = Ttd_l + Ttd_r + Ttd_m Fs (Sampling frequency) Fs = 1 / Ttd = sar_adc_dig_clk / 1500 MISC r_max_s_m set capture r_max_c_m Left r_max_s_l set capture set capture r_max_c_r Right

Datasheet for Telink TL3828 DS-TL3828-E5 571 Ver 0.8.0

14.4 ADC Trigger Mode

The trigger mode allows users to control the number of ADC samples captured per trigger signal. Set the digital register 0x31 to 8’d8 to define 8 sampling cycles per trigger. Set the digital register 0x2a[7] to 1’b1 to enable trigger mode. Then, write 1’b1 to the digital register 0x30[2] to initiate a single trigger. Example: To enable the Misc, Left, and Right channels with 8 sample times per trigger signal, configure the registers as follows: Step 1 Set the digital register 0x2a[2:0] to 3’b111 to enable the Misc, Left, and Right channels. Step 2 Set the maximum state index to 6 by configuring the digital register 0x28[6:4] to 3’h6. Step 3 Set the digital register 0x31 to 8’d8 to define 8 sample times per channel. Step 4 Set the digital register 0x2a[7] to 1’b1 to enable trigger mode. Step 5 Then, write 1’b1 to the digital register 0x30[2] to initiate a single trigger. Select single_ended input afe_0x26c<6> = 1 differential input Set input channel SAR_ADC digital register 0x35 = 0x12 Select PC[0] as positive input and PC[1] as negative input SAR_ADC digital register 0x36 = 0x34 Select PC[2] as positive input and PC[3] as negative input SAR_ADC digital register 0x34 = 0x56 Select PC[4] as positive input and PC[5] as negative input Set scaling factor for ADC analog input SAR_ADC digital register 0x07[5:4] = 2’b00 scaling factor: 1 ADC maximum input range: 0 ~ +1.2V SAR_ADC digital register 0x08[5:4] = 2’b00 scaling factor: 1 ADC maximum input range: 0 ~ +1.2V SAR_ADC digital register 0x06[5:4] = 2’b00 scaling factor: 1 ADC maximum input range: 0 ~ +1.2V Set resolution afe_0x26c<1:0> = 0, resolution: 8 bits afe_0x26c<1:0> = 1, resolution: 10 bits afe_0x26c<1:0> = 2, resolution: 12 bits Set Tsamp (determines the speed to stabilize input before sampling) SAR_ADC digital register 0x03[7:4]=2 Tsamp = adc_tsamp / FADC_clk SAR_ADC digital register 0x04[3:0]=2 Tsamp = adc_tsamp / FADC_clk SAR_ADC digital register 0x03[3:0]=2 Tsamp = adc_tsamp / FADC_clk Function Left Channel Register Setting Right Channel Register Setting Misc Channel Register Setting

Datasheet for Telink TL3828 DS-TL3828-E5 572 Ver 0.8.0

14.5 ADC Oversampling

Oversampling is a simple averaging filter. The maximum resolution of the ADC is 12 bits. These 12 bits are used for the integer part, while the remaining 4 bits represent the fractional part, corresponding to decimal The table below shows the specific number of oversampling and data accuracy: Table 14-3 Oversampling Configuration Example 1 – 2x Oversampling When the oversampling setti ng is 2x, 2 consecutive samples are summed, resulting in one additional bit of resolution (13 bits total). Bit [11:0] represents the integer part, and bit 12 is the fractional part.

• Set the digital register 0x01[4] to 1’b1 to enable oversampling.
• Set the digital register 0x01[3:0] to 4’b0 to select 2x oversampling. Example 2 – 4096x Oversampling: With a 4096x setting, 4096 consecutive samples are accumulated, resulting in 12 extra bits. To maintain a 16- bit result, the data must be right-shifted by 8 bits.
• Set the digital register 0x01[4] to 1’b1 to enable oversampling.
• Set the digital register 0x01[3:0] to 4’d11 to select 4096x oversampling.

14.6 ADC Keyscan Mode

Keyscan mode is specifically used for Keyscan. Oversampling Setting Number of Right Shifts Resulting Resolution (bits) 2x 0 13 4x 0 14 8x 0 15 16x 0 16 32x 1 16 64x 2 16 128x 3 16 256x 4 16 512x 5 16 1024x 6 16 2048x 7 16 4096x 8 16

Datasheet for Telink TL3828 DS-TL3828-E5 573 Ver 0.8.0 In this case, set the digital register 0x01[5] to 1’b1 and set 0x2a[7] to 1’b1 to enable keyscan mode, set {0x32[3:0],0x31[7:0]} to 12’b1 to configure the ADC to perform one sampling operation for each keyscan signal. In keyscan mode, only the Misc channel can be enabled. Set the digital register 0x2a[2:0] to 3’b1 to enable the Misc channel. The registers 0x38[7:0] to 0x3F[7:0] are used to configure the pad selections for keyscan mode. The scanning order follows the rotation sequences below:

• Positive Pad Rotation Sequence: 0x38[3:0] -> 0x38[7:4] -> 0x39[3:0] -> 0x39[7:4] -> 0x3a[3:0] -
• Negative Pad Rotation Sequence:0x3c[3:0] -> 0x3c[7:4] -> 0x 3d[3:0] -> 0x3d[7:4] -> 0x3e[3:0] -

14.7 Battery Voltage Sampling

When sampling the battery voltage, set the SAR_ADC digital register 0x34[3:0] = 4’hb, 0x35[3:0] = 4’hb, 0x05[5:4] to determine the sampling range of VBAT of the Misc (m), Left (l), and Right (r) channels.

14.8 Register Description of SAR ADC

14.8.1 Digital Register

The SAR ADC related digital registers are listed in the table below. For SAR ADC0 related registers, the base address is 0x80101400; For SAR ADC1 related regi sters, the base address is 0x80104400. Table 14-4 SAR ADC Related Digital Registers Offset Name Type Description Default Value 0x00 M_CONFIG RW [0]: r_m_config, m channel config by software 0x00 NOTE:

• Set 0x05[1:0] = 2’b01, 0x05[3:2] = 2’b01, 0x05[5:4] = 2’b01, the maximum sampling range of VBAT is 0 ~ 4.8V

Datasheet for Telink TL3828 DS-TL3828-E5 574 Ver 0.8.0 0x01 Oversampling RW [3:0]: oversample_max_cnt 0: 2x 1: 4x 2: 8x 3: 16x 4: 32x 5: 64x 6: 128x 7: 256x 8: 512x 9: 1024x 10: 2048x else: 4096x [4]: oversample_en [5]: pad_auto_mux_en 0x0 0x03 TSAMP1 RW [3:0]: r_tsampm, misc channel tsamp [7:4]: r_tsampl, left channel tsamp 0x00 0x04 TSAMP2 RW [3:0]: r_tsampr, right channel tsamp 0x00 0x05 VBAT_DIV RW [1:0]: misc_channel_vbat_div [3:2]: left_channel_vbat_div [5:4]: right_channel_vbat_div 0x00 0x06 M_CHANNEL_SET_STATE RW [3:0]: r_max_s_m, m_channel set state_cnt [5:4]: m_channel_sel_ai_scale [7:6]: m_channel_sel_vref 0x00 0x07 L_CHANNEL_SET_STATE RW [3:0]: r_max_s_l, l_channel set state_cnt [5:4]: l_channel_sel_ai_scale [7:6]: l_channel_sel_vref 0x00 0x08 R_CHANNEL_SET_STATE RW [3:0]: r_max_s_r, r_channel set state_cnt [5:4]: r_channel_sel_ai_scale [7:6]: r_channel_sel_vref 0x00 0x0a M_CHANNEL_CAPTURE_S TATE_L RW [7:0]: r_max_c_m_l, m_channel capture state_cnt_low 0x00 Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 575 Ver 0.8.0 0x0b M_CHANNEL_CAPTURE_S TATE_H RW [1:0]: r_max_c_m_h, m_channel capture state_cnt_high 0x00 0x0c L_CHANNEL_CAPTURE_S TATE_L RW [7:0]: r_max_c_l_l, l_channel capture state_cnt_low 0x00 0x0d L_CHANNEL_CAPTURE_S TATE_H RW [1:0:] r_max_c_l_h, l_channel capture state_cnt_high 0x00 0x0e R_CHANNEL_CAPTURE_S TATE_L RW [7:0]: r_max_c_r_l, r_channel capture state_cnt_low 0x00 0x0f R_CHANNEL_CAPTURE_S TATE_H RW [1:0]: r_max_c_r_h, r_channel capture state_cnt_high 0x00 0x28 CONFIG0 RW [6:4]: scnt_max state number max, the value equal the number of channel * 2 0x00 0x29 CONFIG1 RW [3:0]: sar_adc_clk_div, sar adc system clk divider number [4]: rsvd [5]: adc_mode, adc function adc mode set0 0x10 0x2a CONFIG2 RW [0]: adc misc channel enable [1]: l_channel_enable [2]: r_channel_enable [3]: rsvd [5]: clk_enable, sar adc system clk enable [6]: sar_rx_interrupt_enable [7]: rx fifo overflow (R) 0x00 0x2b RXFIFO_TRIG_NUM RW [3:0]: rx fifo number [7:4]: bufcnt, read the number of data in fifo (READ ONLY) 0x00 0x2c RXFIFO_DAT0 RW [7:0]: rxfifo_dat0 0x00 0x2d RXFIFO_DAT1 RW [7:0]: rxfifo_dat1 0x00 0x2e RXFIFO_DAT2 RW [7:0]: rxfifo_dat2 0x00 0x2f RXFIFO_DAT3 RW [7:0]: rxfifo_dat3 0x00 Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 576 Ver 0.8.0 0x30 SOFT_CONTROL RW [0]: sar_irq_rx_status (WRITE 1 CLEAR) [1]: fifo_clr (WRITE 1 CLEAR) [2]: trig_start (write 1 to start trig) [7]: soft_start (write 1 to start) 0x00 0x31 SAMPLE_TIMES_LOW RW [7:0]: sample times[7:0] when trig mode 0x01 0x32 SAMPLE_TIMES_HIGH RW [3:0]: sample times[11:8] when trig mode [4]: pem_task_enable [5]: pem_event0_enable [6]: pem_event1_enable 0x00 0x33 FIFO_STATUS R [0]: fifo_overrun [1]: fifo_underrun 0x00 0x34 R_MUXM_POS_NEG RW [3:0]: r_muxm_positive_input [7:4]: r_muxm_negative_input 0x00 0x35 R_MUXL_POS_NEG RW [3:0]:r_muxl_positive_input [7:4]:r_muxl_negative_input 0x00 0x36 R_MUXR_POS_NEG RW [3:0]: r_muxr_positive_input [7:4]: r_muxr_negative_input 0x00 0x38 PAD_AUTO_P_0 RW [3:0]: ain_p_pad_0 [7:4]: ain_p_pad_1 0x00 0x39 PAD_AUTO_P_1 RW [3:0]: ain_p_pad_2 [7:4]: ain_p_pad_3 0x00 0x3a PAD_AUTO_P_2 RW [3:0]: ain_p_pad_4 [7:4]: ain_p_pad_5 0x00 0x3b PAD_AUTO_P_3 RW [3:0]: ain_p_pad_6 [7:4]: ain_p_pad_7 0x00 0x3c PAD_AUTO_N_0 RW [3:0]: ain_n_pad_0 [7:4]: ain_n_pad_1 0x00 0x3d PAD_AUTO_N_1 RW [3:0]: ain_n_pad_2 [7:4]: ain_n_pad_3 0x00 0x3e PAD_AUTO_N_2 RW [3:0]: ain_n_pad_4 [7:4]: ain_n_pad_5 0x00 Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 577 Ver 0.8.0

14.8.2 Analog Register

The SAR ADC0 related analog registers are listed in the table below. Table 14-5 SAR ADC0 Analog Registers 0x3f PAD_AUTO_N_3 RW [3:0]: ain_n_pad_6 [7:4]: ain_n_pad_7 0x00 Address Default Value Description afe_0x26c<1:0> 10 adc_resolution 0: 8bits 1: 10bits 2: 12bits afe_0x26c<6> 0 adc_en_diffm 1: diffrential mode 0: single_ended mode afe_0x272<3> 0 r_auto_not_en 0: send adc sample data to digcore 1: not send adc sample data to digcore afe_0x273<0> 0 hold_md 0: latch misc channel data 1: not latch misc channel data afe_0x273<1> 0 Dwa dunction enable 1: enable 0: disable afe_0x273<2> 0 ana_rd_en 0: enable misc channel data to be read directly by ana reg 1: disable misc channel data to be read directly by ana reg afe_0x274<3:0> 11 adc_div_mod Clk division factor = adc_div_mod+1 afe_0x276<0> read only madc_vld afe_0x277<7:0> read only r_misc1: misc channel data low 8 bits afe_0x278<7:0> read only r_misc2: misc channel data high 8 bits Offset Name Type Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 578 Ver 0.8.0 The SAR ADC1 related analog registers are listed in the table below. Table 14-6 SAR ADC1 Analog Registers afe_0x27c<5> 0 adc_pd Address Default Value Description afe_0x36c<1:0> 10 adc_resolution 0: 8bits 1: 10bits 2: 12bits afe_0x36c<6> 0 adc_en_diffm 1: diffrential mode 0: single_ended mode afe_0x372<3> 0 r_auto_not_en 0: send adc sample data to digcore 1: not send adc sample data to digcore afe_0x373<0> 0 hold_md 0: latch misc channel data 1: not latch misc channel data afe_0x273<1> 0 Dwa dunction enable 1: enable 0: disable afe_0x373<2> 0 ana_rd_en 0: enable misc channel data to be read directly by ana reg 1: disable misc channel data to be read directly by ana reg afe_0x374<3:0> 11 adc_div_mod Clk division factor = adc_div_mod+1 afe_0x376<0> read only madc_vld afe_0x377<7:0> read only r_misc1: misc channel data low 8 bits afe_0x378<7:0> read only r_misc2: misc channel data high 8 bits afe_0x37c<5> 0 adc_pd Address Default Value Description

Datasheet for Telink TL3828 DS-TL3828-E5 579 Ver 0.8.0

15 SD ADC

15.1 Overview of SD ADC

The SoC integrates one SD ADC module, which can be used to sample audio input signals and analog input signals such as battery voltage. The SD ADC provides 16-bit resolution and supports selectable sampling clocks of 1 MHz or 2 MHz, with configurable downsampling factors of 64, 128, or 256. The architecture of SD ADC module is shown in the figure below. Figure 15-1 Architecture of SD ADC module The data flow of SD ADC module i s shown in the figure below. Figure 15-2 Data flow of SD ADC module The SD ADC data comes from analog SD ADC, uses op_mode to gate data to DC channel, after CIC filter, the data will be written into FIFO.

15.2 Configuration of SD ADC

15.2.1 Power On/Off

The SD ADC is disabled by default. To power on the SD ADC, the analog register 0x8e[6] should be set as 1'b0.

15.2.2 ADC Clock

The SD ADC clock depends on the operation mode. There are four SD ADC operation modes:

• Audio PGA MUX_SW MUX_SW BUFFER BUFFER Ȉǻ Sinc3 digital filter MUX_SW MUX_SW AMIC vbat ai_p<2:0> aio<9:0> audio_p avss ai_n<2:0> aio<9:0> audio_n aip_sel ain_sel opmode opmode ADC output SD ADC DATA op_mode DC data CIC FIFO

Datasheet for Telink TL3828 DS-TL3828-E5 580 Ver 0.8.0

• 1-channel DC In Audio mode, the SD ADC clock frequency varies with the audio sample rate which can be configured by register CODEC_BASE+0x0a[5:1] (refer to Table 10-11 CODEC Related Registers). In 1-channel DC mode, the SD ADC clock = pclk / (2 x (DC_BASE+0x0c[6:0] + 1)). The SD ADC clock must not exceed 2 MHz in these modes.

15.2.3 Usage Case with Detailed Register Setting

(1) Sample audio data Set DC_BASE+0x0d[2:0] to 3’b100 to select audio mode. (2) Sample DC data Set DC_BASE+0x 0d[2:0] to 3'b001 to select 1-channel DC mode, set DC_BASE+0x0b[6:4] to 3'b0 to select a DC down-sample rate of 64. Set DC_BASE+0x0c[6:0] to ensure the SD ADC working clock is not exceed 2MHz.

15.3 Register Table of SD ADC

15.3.1 Digital Register

The SD ADC related digital registers are listed in the table below, the base address of the following registers is 0x80240280 (DC_BASE). Table 15-1 SD ADC Digital Registers Address offset Name Type Description Reset Value 0x0b DEC_RATE R/W [6:4]: DC channel cic filter down sample rate 0:64; 1:128; 2:256; else:256 0x0 0x0c DFIFO_DC_CLK_DIV R/W [6:0]: sd adc working clock dividing factor Sd adc working freq = pclk / 2(0x0c[6:0] + 1) (only in operation mode 3 and 4 valid) 0x17 0x0d DC_MODE_CONFIG R/W [2:0]: operation mode 3'b001: sample 1 channel DC data only 3'b010: rsvd 3'b011: rsvd 3'b100: sample audio data only Else: off [7:4]: DC drop number 0x00 0x10 DFIFO_DC_MODE R/W [7]: r_mask, set to 1 to enable interrupt 0x80

Datasheet for Telink TL3828 DS-TL3828-E5 581 Ver 0.8.0

15.3.2 Analog Register

The SD ADC related analog registers are listed in the table below. Table 15-2 SD ADC Analog Registers 0x13 IRQ_FIFO2 R [3]: interrupt. (Write1 to clear) [7]: irq status 1: fifo data num > rxfifo_trig_num 0: fifo data num <= rxfifo_trig_num 0x00 0x14 RXFIFO2_TRIG_NUM R/W [4:0]: rxfifo_trig_num 0x00 0x15 RXFIFO2_CLR W [0]: rxfifo_wrptr_clr 0x0 0x16 RXFIFO2_ST R [0]: rxfifo_rdptr_clr [4]: rxfifo2_overrun 0x00 0x17 RXFIFO2_NUM R [4:0]: data number remain in fifo 0x00 0x20 RXFIFO2_R_DAT0 R [7:0]: rxfifo_r_dat0 0x00 0x21 RXFIFO2_R_DAT1 R [7:0]: rxfifo_r_dat1 0x00 0x22 RXFIFO2_R_DAT2 R [7:0]: rxfifo_r_dat2 0x00 0x23 RXFIFO2_R_DAT3 R [7:0]: rxfifo_r_dat3 0x00 Address Default Value Description afe_0x7d<2> 1 1:power down audio; 0: power on audio (internal pm_top pin pg_audio_en_o = !pg_audio_en) afe_0x10c<1> 0 xtal_24M clock to analog 0:turn off; 1:turn on. afe_0x10c<2> 0 0: DEM function of sigma-delta ADC is disabled; 1: DEM function of sigma-delta ADC is enabled afe_0x10c<4:3> 11 PD signal for two ADC buffers 00: power on afe_0x10c<6> 0 Selecting positive signal sent to adc_buffer between ai_p(aio)_div and vbat_div. 0 for ai_p(aio)_div; 1 for vbat_div. Address offset Name Type Description Reset Value

Datasheet for Telink TL3828 DS-TL3828-E5 582 Ver 0.8.0 afe_0x10d<1:0> 00 Selecting dividing ratio of vbat. 00: 1/8 01: 1/4 10: 1/2 11: 3/4 afe_0x10d<2> 0 0: Unmute PGA; 1: Mute PGA afe_0x10d<3> 0 0: Enable PGA input; 1: Disable PGA input afe_0x10d<7:4> 1000 1111 for min PGA gain; 0000 for max PGA gain afe_0x10e<1:0> 11 Control the filtering cap value in PGA afe_0x10e<3:2> 11 Control the driving ability of VMID afe_0x10e<4> 1 PD signal for PGA Set to 1 when performing DC measurement afe_0x10e<5> 1 PD signal for CODEC Bias Set to 0 to power on the ADC analog system afe_0x10e<6> 1 PD signal for ADC Set to 0 to power on ADC core circuit afe_0x10e<7> 1 PD signal for VMID Set to 0 to provide ADC reference voltage afe_0x10f<3:0> 0000 Low-power mode enable signal. <3> for PGA and <2:0> for ADC. 0: default mode 1: low-power mode afe_0x10f<6:4> 000 Control the selection of test signal from ADC afe_0x10f<7> 0 vbat detector enble signal 0:disable 1:enable Set to 1 when measuring VBAT; Set to 0 when measuring GPIO. Address Default Value Description

Datasheet for Telink TL3828 DS-TL3828-E5 583 Ver 0.8.0 afe_0x110<3:0> 1111 Selecting one among 13 negative analog inputs. 0000~1111: aio<0> to aio<9> 0000: aio<0>, PC[0] 0001: aio<1>, PC[1] 0010: aio<2>, PC[2] 0011: aio<3>, PC[3] 0100: aio<4>, PC[4] 0101: aio<5>, PC[5] 0110: aio<6>, PB[4] 0111: aio<7>, PB[5] 1000: aio<8>, PB[6] 1001: aio<9>, PB[7] 1101~1111: reserved afe_0x110<7:4> 1111 Selecting one among 13 positive analog inputs. 0000~1111: aio<0> to aio<9> 1101~1111: reserved afe_0x111<1:0> 11 Selecting dividing ratio of negative analog input. 00: 1/8 01: 1/4 10: 1/2 11: 1 afe_0x111<3:2> 11 Selecting dividing ratio of negative analog input. 00: 1/8 01: 1/4 10: 1/2 11: 1 afe_0x111<4> 0 Enable signal for global chopping function afe_0x111<5> 0 Enable signal for bypassing adc_buffer. afe_0x111<7> 0 Fs6M_clk_inv signal Address Default Value Description

Datasheet for Telink TL3828 DS-TL3828-E5 584 Ver 0.8.0 afe_0x112<3:0> 1111 Selecting one among 13 negative analog inputs. 0000~1111: aio<0> to aio<9> 1101~1111: reserved afe_0x112<7:4> 1111 Selecting one among 13 positive analog inputs. 0000~1111: aio<0> to aio<9> 1101~1111: reserved Address Default Value Description

Datasheet for Telink TL3828 DS-TL3828-E5 585 Ver 0.8.0

16 Capacitive Touch Button (CTB)

16.1 Overview of CTB

The CTB (capacitive touch button) is a configurable module designed to handle multiple analog measurement channels and facilitate interactions with external analog signals. This module's flexibility and configurability make it ideal for applications requiring synchronized multi-channel analog measurements with efficient data handling and low power operation. The CTB features include:

• Programmable number of enabled buttons (up to 16 buttons)
• Programmable i nterrupt lines
• Programmable number of cycles per sample
• Programmable number of samples per 1 reading
• Programmable step size value for slew rate limit0er filter
• Programmable Butterworth filter coefficient
• Option to bypass Butterworth filter
• Programmable number of debounce filter
• Separated calibration module
• Programmable scan ti me

16.2 Block Diagram of CTB

The diagram of CTB module is shown in figure below.

Datasheet for Telink TL3828 DS-TL3828-E5 586 Ver 0.8.0 Figure 16-1 Block Diagram of CTB module The CTB_AON_TOP is designed to control the CTB block. This block is highly programmable. Up to 16 buttons can be enabled during runtime and support up to 2 buttons during sleep. It has a slew rate limiter and Butterworth filters with different parameters to reject impulse noise and white noise. And support debounce filter for high noise environments. Sample time, reading time and Scan ti me are all programmable. This block is run by 32kHz clock input and have a synchronous reset. It has interrupt line for wake-up and different interrupt line as error flag for any wrong behavior observed from analog side. A separated calibration module to calibrate the threshold during the run time. Here shows the flow of signal processing, including SRL filter and Butterworth filter:

Datasheet for Telink TL3828 DS-TL3828-E5 587 Ver 0.8.0 Figure 16-2 Signal Processing Flow of CTB module

Datasheet for Telink TL3828 DS-TL3828-E5 588 Ver 0.8.0

16.3 Timing Diagram

16.3.1 Different Period Types

The different period types are illustrated in the following figure. Figure 16-3 Period Types of CTB module

• Sample_period is configured by cycles_per_sample input. And it represents number of cycles from 32kHz for each sample.
• reading_period = samples_per_reading * cycles_per_sample
• number of channels in active = 16
• Scan_period >= 16 * reading_period (required to be around 20ms)

16.3.2 Scan Period with Debounce by 2

The scan period of CTB is illustrated i n the following figure. Figure 16-4 Scan Period of CTB module It is the waveform captured when configuring 2 samples per reading.

• After 2 samples, 1 reading is generated and filtered.
• If the filtered reading is higher than button threshold, the debounce_counter increments.
• Start scan the next channel. And after scanning all enabled channels, clock will be gated.
• When scan period is completed and start scan again channel 0. If the channel 0 readi ng is also higher than threshold, the debounce_counter will increment and rise the wkup_irq. Ch0 Sample Ch0 Sample Ch1 Sample Ch1 Sample Clock Gated debounce_counter_ch0 debounce_counter_ch1 Ch0 Sample Ch0 Sample Ch1 Sample Ch1 Sample Clock Gated debounce_counter_ch0=2 ch0 touched flag) debounce_counter_ch1=2 ch1 touched flag) sample_period reading_period scan_period

Datasheet for Telink TL3828 DS-TL3828-E5 589 Ver 0.8.0

16.3.3 Sample Period

The timing sequence of sample period is shown in the following figure. Figure 16-5 Sample Period of CTB module

• ctb_ana_en is high in the beginning of every channel scanning.
• After 1 cycle of clk_32k, the start count is asserted.
• Counter value is changing during the sample period (programmable by cycles_per_sample) till cmpout is high.
• ctb_ana_en and ctb_ana_startcount signals are low in same time that counter value and ctb_ana_cmpout_flag i s checked.
• If ctb_ana_cmpout_flag is high and counter value is higher than threshold, the flag wkup_irq is high.
• If ctb_ana_cmpout_flag is low in the end of sample period or counter value less than switch_cap_val, the error_irq is raised.

16.3.4 Reading Period with Oversampling by 2

The timing sequence of reading period with oversampling by 2 is shown in the following figure. Figure 16-6 Reading Period with Oversampling

• It is the timing diagram when oversample i s configured by 2 by samples_per_reading.
• Take N successive samples from same channel and process on them to generate 1 reading.
• The irq will only assert or not in the end of number of samples per reading from the same channel configured by debounce_target.

16.3.5 Calibration

The timing sequence of calibration is shown in the following figure. clk_32k channel_num ctb_ana_en ctb_ana_startcount ctb_ana_counter_val ctb_ana_cmpout_flag wkup_irq error_irq clk_32k channel_num ctb_ana_en ctb_ana_startcount ctb_ana_counter_val ctb_ana_cmpout_flag irq_status[0] irq_status[1]

Datasheet for Telink TL3828 DS-TL3828-E5 590 Ver 0.8.0 Figure 16-7 Calibration of CTB module

• Calibration will be done in active mode after power up with processor.
• All the samples values are assumed no touch on CTB.
• Take N successive samples from same channel.
• Processor should be configured and enabled only 1 channel per 1 time.
• Average the value together and take margin to define the digital_word value.
• The calbr_done is asserted, wait the processor to take the result and assi gn it to the pmu_reg or reg_ana for each channel.
• The calbr_rst should be raised and down before starting the calibration of the next channel.
• 2 calibrations are needed, one for setting digital_word (for changing lstepcode to fstepcode) and the other to update the threshold.

16.4 Implementation Description

16.4.1 CTB SRL Filter

The slew rate limiter is used to reject the impulse noise and limit the change between the new sample and the pervi ous sample by only the step size. The typical operation is that in first sample the reading_val will equal the new_sample_val (counter value came from analog block) and in next sample SRL will compare the new sample with the value that stored in the reading_val register. If the difference is less than ± step size (afe_0x93[3:0]), the reading_val will equal new_sample_val; if the difference is more than that, the reading_val will equal (new_sample_val ± step size). This behavior will be repeated till samples_counter equals samples_per_reading(afe_0x91[7:4]). Therefore, SRL filter takes number of sample and process them, then output 1 readi ng value. The behavior of SRL should be skipped if CTB is programmed to take 1 sample per every reading. Another way to initialize the reading_val when sample_counter=0 is to set the initial value to the previous_reading value via ctb_srl_scan_history_sel (afe_0x92[7] == 1'b1) instead of the new value of the analog module counter.

16.4.2 CTB Butterworth Filter

The Butterworth filter is desi gned to reject the white noise. It works after SRL on readings value. The filter equation is: y[n] = x[n] + x[n-1] + Ay[n-1] clk_32k calbr_en channel_num accu_en calbr_rst calbr_done

Datasheet for Telink TL3828 DS-TL3828-E5 591 Ver 0.8.0 The coefficient is programmable via filter_coef_sel(afe_0x92[1:0]):

• 0: A= 0.5
• 1: A=0.75
• 2: A=0.875
• 3: A=0.9375 To bypass the effect of Butterworth filter, filter_bw_bypass (set afe_0x93[5] to 1'b1) is added to bypass the filter output to the reading_val that came from SRL filter. Every coefficient has a different DC gain, therefore a gain control reg filter_gain_sel(afe_0x9f[1:0]) i s added to remove it:
• 2'b00: divide by 4
• 2'b01: divide by 8
• 2'b10: divide by 16
• 2'b11: divide by 32

16.4.3 CTB IRQ CTRL

The Butterworth filter output will be compared with the threshold value of current channel:

• CH0: {afe_0x84[4:0], afe_0x83[7:0]}
• CH1: {afe_0x86[4:0], afe_0x85[7:0]}
• CH2: {afe_0x1b7[4:0], afe_0x1b6[7:0]}
• CH3: {afe_0x1b9[4:0], afe_0x1b8[7:0]}
• CH4: {afe_0x1bb[4:0], afe_0x1ba[7:0]}
• CH5: {afe_0x1bd[4:0], afe_0x 1bc[7:0]}
• CH6: {afe_0x1bf[4:0], afe_0x1be[7:0]}
• CH7: {afe_0x1c1[4:0], afe_0x1c0[7:0]}
• CH8: {afe_0x1c3[4:0], afe_0x1c2[7:0]}
• CH9: {afe_0x1c5[4:0], afe_0x1c4[7:0]}
• CH10: {afe_0x1c7[4:0], afe_0x1c6[7:0]}
• CH11: {afe_0x1c9[4:0], afe_0x1c8[7:0]}
• CH12: {afe_0x1cb[4:0], afe_0x1ca[7:0]}
• CH13: {afe_0x1cd[4:0], afe_0x1cc[7:0]}
• CH14: {afe_0x1cf[4:0], afe_0x1ce[7:0]}
• CH15: {afe_0x1d1[4:0], afe_0x1d0[7:0]} If i t is greater than current threshold, the debounce_counter will be incremented; if not greater than that, the counter will be reset to zero. The debounce_counter value also will be compared, if it is equal or greater than debounce_target (afe_0x91[2:0]), the irq_val will equal 1 and the irq of the current channel will be fired. The debounce_target is the same for all channels. And irq_en[x ] ({afe_0x 90,afe_0x8f}) should be equal 1 to enable the interrupt of corresponding channel. All the irq lines can cause output wkup_irq(afe_0x64[5]). The irq vector of all channels are output also as irq_status (afe_0xac,afe_0xab}) and can be read from pmu_reg to figure out which channel is pressed now.

Datasheet for Telink TL3828 DS-TL3828-E5 592 Ver 0.8.0

16.4.4 CTB Calibration

The CTB calibration is used to calibrate and calculate the threshold and switch_cap_val for every channel. Set Calbr_en (afe_0x99[0]) to 1 to enable calibration mode. Set ctb_calbr_iteration_num (afe_0x99[5:4]) to decide to take the average number of reading values.

• 2'b00: 4
• 2'b01: 8
• 2'b10: 16
• 2'b11: 4 Set the calbr_type (afe_0x99[2]) to 1 to choose output the average value whi ch is used for switch_cap_val. Set the calbr_type (afe_0x99[2]) to 0 to output the thre_updated.

16.4.5 Calibration Procedure

The calibration procedure is as below. 1. Disable ctb_clk:

• Set ctb_clk_en (afe_0x94[0]) to 0 to disable the CTB clock. 2. Disable All Channels and Enable Target Channel:
• Set {afe_0x96[7:0], afe_0x95[7:0]} to disable all CTB channels. Then, enable only the channel to be calibrated via ctb_channels_en. 3. Enable Cali bration Mode:
• Set ctb_calbr_en (afe_0x99[0]) to 1 to enable calibration mode.
• Set ctb_calbr_type (afe_0x99[2]) to choose calibration type.
• Set ctb_calbr_iterations (afe_0x99[5:4]) to define the number of calibration iterations. 4. Enable ctb_clk:
• Set ctb_clk_en (afe_0x94[0]) to 1 to enable the CTB clock. 5. Wait for Calibration to Complete:
• Wait until ctb_calbr_done (afe_0x1f7[0]) becomes high.
• Then, read the cali bration count from ctb_calbr_count ({afe0x1f0[3:0], afe_0x1ef[7:0]}).
• Use this value to update the corresponding threshold or switch_cap_val. 6. Disable ctb_clk:
• Set ctb_clk_en (afe_0x94[0]) to 0 again to disable the CTB clock. 7. Reset Calibration Module:
• Set ctb_calbr_rst (afe_0x99[3]) to 1 to reset the calibration logic. 8. Check Done Signal:
• After reset, ctb_calbr_done (afe_0x1f7[0]) should be low. 9. Repeat for Next Ch annel:
• Disable all channels again.
• Enable the next channel to be calibrated.
• Repeat steps 3–8 for each remaining channel.

Datasheet for Telink TL3828 DS-TL3828-E5 593 Ver 0.8.0 Figure 16-8 Calibration Procedure of CTB module

16.5 Usage Case with Detailed Register Setting

In normal mode, the channel 0, 1, 2 are enabled, the Butterworth filter is enabled, the Butterworth filter coefficient is set to 0, the Butterworth filter gain sel is set to 0, the debounce_target is set to 2, the samples_per_reading is set to 2, the cycles_per_sample is set to 15, the srl_step_size is set to 5, the scan_time_target is set to 15: Table 16-1 Register Setting in Normal Mode Function Register Setting Channel 0, 1, 2 enable afe_0x95 = 0x07 Scan time target set to 15 afe_0x9d = 0x0f Ctb_irq_enable afe_0x8f = 0x07 Cycles_per_sample set to 15 afe_0x97 = 0x0f Samples_per_reading set to 2 afe_0x91<7:4> = 4’d2 Debounce target set to 2 afe_0x91<3:0> = 4’d2 Srl_step_size set to 5 afe_0x93<4:0> = 5’d5 Filter_butterworth_bypass set to 0 afe_0x93<5> = 1’d0 Bw_filter_coef_sel set to 0 afe_0x92<1:0> set to 2’d0 Bw_filter_gain_sel set to 0 afe_0x9f<1:0> set to 2’d0 Error_irq_en afe_0x9c<1:0> set to 2’d3 Ch 0 threshold set to 83 {afe_0x84<4:0>, afe_0x83<7:0>} = 13’d83 C h 1 threshold set to 83 {afe_0x86<4:0>, afe_0x85<7:0>} = 13’d83 Ch 2 threshold set to 83 {afe_0x1b7<4:0>, afe_0x1b6<7:0>} = 13’d83 Ch 0 large step capacitance cfg afe_0x8b<4:0> = 5’d22

Datasheet for Telink TL3828 DS-TL3828-E5 594 Ver 0.8.0 In calibration mode, the channel 0 is enabled, the calibration iterations is set to 16, get the threshold value, the Butterworth filter is disabled, the samples_per_reading is set to 2, the cycles_per_sample is set to 15, the srl_step_size is set to 5. Table 16-2 Register Setting in Calibration Mode Ch 0 fine step capacitance cfg afe_0x8c<4:0> = 5’d2 Ch 1 large step capacitance cfg afe_0x8d<4:0> = 5’d22 Ch 1 fine step capacitance cfg afe_0x8e<4:0> = 5’d2 Ch 2 large step capacitance cfg afe_0x19a<4:0> = 5’d22 Ch 2 fine step capacitance cfg afe_0x19b<4:0> = 5’d2 Ch 0 switch_cap_val set to 79 {afe_0x88<4:0>, afe_0x87<7:0>} = 13’d79 Ch 1 switch_cap_val set to 79 {afe_0x8a<4:0>, afe_0x89<7:0>} = 13’d79 Ch 2 switch_cap_val set to 79 {afe_0x1d3<4:0>, afe_0x1d2<7:0>} = 13’d79 Ctb as wake up source afe_0x40<5> = 1’d1 Ctb scan enable afe_0xb0<2> = 1’d1 Ctb rst_sync set to 1 afe_0x94<1> = 1’d1 Ctb clk en afe_0x94<0> = 1’d1 Ctb active top clk en afe_0x1ee<1> = 1’d1 Ctb rst_sync set to 0 afe_0x94<1> = 1’d0 Ctb irq clr set to 1 {afe_0x9b<7:0>, afe_0x9a<7:0>} = 16’hffff Ctb irq clr set to 0 {afe_0x9b<7:0>, afe_0x9a<7:0>} = 16’h0 Function Register Setting disable ctb_clk qfe_0x94<0> = 1’d0 Channel 2 enable {afe_0x96[7:0], afe_0x95[7:0]} = 16’d4 Ctb calibration type set to 1 to get switch_cap_value afe_0x99<2> = 1’d1 Ctb calibration iterations set to 16 afe_0x99<5:4> = 2’d2 Calibration finished flag rst set to 1 afe_0x99<1> = 1’d1 Calibration finished flag rst set to 0 afe_0x99<1> = 1’d0 Butterworth filter bypass afe_0x93<5> = 1’d1 Srl_step_size set to 5 afe_0x93<4:0> = 5’d5 Function Register Setting

Datasheet for Telink TL3828 DS-TL3828-E5 595 Ver 0.8.0 The switch_cap_val is used to switch lstep_cap_val and fstep_cap_val (lstep_cap_val should be larger than fstep_cap_val), the purpose of it is to do trade off between detect speed and accuracy. In calibration process, switch_cap_val should be large enough in order to get the accurate switch_cap_val for normal mode. After getting the switch_cap_val, another calibration process is needed to get the threshold value for each channel: Table 16-3 Register Setting in Switching Modes Channel 2 lstep_cap_value set to 20 afe_0x19a<4:0> = 5’d20 Channel 2 fstep_cap_value set to 2 afe_0x19b<4:0> = 5’d2 Channel 2 switch_cap_value set to 500 {afe_0x1d3<4:0>, afe_0x1d2<7:0>} = 13’d500 Ctb scan enable afe_0xb0<2> = 1’d1 Ctb_calbr_en afe_0x99<0> = 1’d1 Ctb_calbr_rst set to 1 afe_0x99<3> = 1’d1 Ctb_calbr_rst set to 0 afe_0x99<3> = 1’d0 Ctb active top clk en afe_0x1ee<1> = 1’d1 Ctb clk en afe_0x94<0> = 1’d1 Read ctb_calbr_done signal Read (afe_0x1f7<0>) Read ctb_calbr_counter_val(when ctb_calbr_done == 1’b1) Read ({afe_0x1f0<4:0>, afe_0x1ef<7:0>}) Set channel 2 switch_cap_val = ctb_calbr_counter_val - 5 Ctb active top clk disable afe_0x1ee<1> = 1’d0 Ctb clk disable afe_0x94<0> = 1’d Ctb_calbr_rst set to 1 afe_0x99<3> = 1’d1 Function Register Setting disable ctb_clk afe_0x94<0> = 1’d0 Channel 2 enable {afe_0x96[7:0], afe_0x95[7:0]} = 16’d4 Ctb calibration type set to 0 to get threshold value afe_0x99<2> = 1’d0 Ctb calibration iterations set to 16 afe_0x99<5:4> = 2’d2 Calibration finished flag rst set to 1 afe_0x99<1> = 1’d1 Calibration finished flag rst set to 0 afe_0x99<1> = 1’d0 Butterworth filter bypass afe_0x93<5> = 1’d1 Function Register Setting

Datasheet for Telink TL3828 DS-TL3828-E5 596 Ver 0.8.0

16.6 Register Description of CTB

The CTB related analog registers are listed as below. Table 16-4 CTB Related Analog Registers Srl_step_size set to 5 afe_0x93<4:0> = 5’d5 Channel 2 lstep_cap_value set to 20 afe_0x19a<4:0> = 5’d20 Channel 2 fstep_cap_value set to 2 afe_0x19b<4:0> = 5’d2 Channel 2 switch_cap_value set to the value from the first calibration process Ctb scan enable afe_0xb0<2> = 1’d1 Ctb_calbr_en afe_0x99<0> = 1’d1 Ctb_calbr_rst set to 1 afe_0x99<3> = 1’d1 Ctb_calbr_rst set to 0 afe_0x99<3> = 1’d0 Ctb active top clk en afe_0x1ee<1> = 1’d1 Ctb clk en afe_0x94<0> = 1’d1 Read ctb_calbr_done signal Read (afe_0x1f7<0>) Read ctb_calbr_counter_val (when ctb_calbr_done == 1’b1) Set channel 2 threshold_val = ctb_calbr_counter_val Ctb active top clk disable afe_0x1ee<1> = 1’d0 Ctb clk disable afe_0x94<0> = 1’d Ctb_calbr_rst set to 1 afe_0x99<3> = 1’d1 Address Name Default Value Description afe_0x80<0> pm_ctbcmp_out_dbg 0 ctb cmpout flag for debug afe_0x80<1> pm_ctbcmp_out_sel 0 sel source of ctb cmpout signal 0: signal from ctb ana part 1: pm_ctbcmp_out_dbg afe_0x80<2> pm_ctb_startcount_dbg 0 pm_ctb_startcount_dbg signal Function Register Setting

Datasheet for Telink TL3828 DS-TL3828-E5 597 Ver 0.8.0 afe_0x80<3> pm_ctb_startcount_sel 0 sel source of ctb_startcount signal 0: from ctb fsm in ctb_aon_top 1: pm_ctb_startcount_dbg afe_0x80<4> pm_ctbcounter_out_sel 0 sel source of ctb counter out 0: signal from ctb ana part 1: pm_ctb_counter_out_dbg afe_0x81<7:0> pm_ctbcounter_out_dbg_b0 00000000 pm_ctbcounter_out_dbg [7:0] afe_0x82<4:0> pm_ctbcounter_out_dbg_b1 0 pm_ctbcounter_out_dbg [12:8] afe_0x83<7:0> ctb_thre_ch0_byte0 01100000 Threshold value of channel 0[7:0] afe_0x84<4:0> ctb_thre_ch0_byte1 0 Threshold value of channel 0[12:8] afe_0x85<7:0> ctb_thre_ch1_byte0 01100000 Threshold value of channel 1[7:0] afe_0x86<4:0> ctb_thre_ch1_byte1 0 Threshold value of channel 1[12:8] afe_0x87<7:0> ctb_switch_cap_val_ch0 _byte0 01010101 CH0 compare value to switch large step to fine step capacitors ladde[7:0] afe_0x88<4:0> ctb_switch_cap_val_ch0 _byte1 00000 CH0 compare value to switch large step to fine step capacitors ladde[12:8] afe_0x89<7:0> ctb_switch_cap_val_ch1 _byte0 01010101 CH1 compare value to switch large step to fine step capacitors ladde[7:0] afe_0x8a<4:0> ctb_switch_cap_val_ch1 _byte1 00000 CH1 compare value to switch large step to fine step capacitors ladde[12:8] afe_0x8b<4:0> ctb_lstep_cfg_ch0 00000 Configuration of large step capacitors of channel 0 afe_0x8c<4:0> ctb_fstep_cfg_ch0 00000 Configuration of fine step capacitors of channel 0 afe_0x8d<4:0> ctb_lstep_cfg_ch1 00000 Configuration of large step capacitors of channel 1 afe_0x8e<4:0> ctb_fstep_cfg_ch1 00000 Configuration of fine step capacitors of channel 1 afe_0x8f<7:0> ctb_irq_en_byte0 00000000 ctb wkup irq en[7:0] afe_0x90<7:0> ctb_irq_en_byte1 00000000 ctb wkup irq en[15:8] afe_0x91<3:0> ctb_debounce_target 0010 Number of successive touched readings required before firing the irq afe_0x91<7:4> ctb_samples_per_reading 0100 Number of samples per every reading for SRL filter Address Name Default Value Description

Datasheet for Telink TL3828 DS-TL3828-E5 598 Ver 0.8.0 afe_0x92<5:0> ctb_filter_coff_sel 110100 [0]: adding y/64 in BW filter [1]: adding y/32 in BW filter [2]: adding y/16 in BW filter [3]: adding y/8 in BW filter [4]: adding y/4 in BW filter [5]: adding y/2 in BW filter afe_0x92<6> ctb_filter_sign_sel 0 0: add 1:minus afe_0x92<7> ctb_srl_scan_history_sel 0 0:srl filter takes the new sample value for 1st sample. 1:srl filter takes the previous reading value for 1st sample. afe_0x93<4:0> ctb_srl_step_size 00101 Step size for slew rate limiter filter. afe_0x93<5> ctb_filter_bw_bypass 0 0:not bypass butterworth filter 1:bypass butterworth filter afe_0x94<0> ctb_clk_en 0 ctb_clk_enable afe_0x94<1> ctb_rst_sync 0 Synchronous reset for all registers in CTB afe_0x94<7:4> ctb_interval_sel 0000 ctb_interval_sel afe_0x95<7:0> ctb_channels_en_byte0 00000000 ctb_channel_enable[7:0] afe_0x96<7:0> ctb_channels_en_byte1 00000000 ctb_channel_enable[15:8] afe_0x97<7:0> ctb_cycles_per_sample_b0 00000100 Number of cycles for every sample for channel[7:0] afe_0x98<0> ctb_cycles_per_sample_b1 0 Number of cycles for every sample for channel[8] afe_0x99<0> ctb_calbr_en 0 Enable the calibration state machine afe_0x99<1> ctb_clabr_finished_flag_rst 0 reset the calibration flag afe_0x99<2> ctb_calbr_type 0 0: output value equals the updated threshold value 1: output value equals the updated switch_cap_val. afe_0x99<3> ctb_calbr_rst 0 Synchronous reset for the calibration block. afe_0x99<5:4> ctb_calbr_iteration_num 00 Number of iteration for calibration engine. 0: four iterations 1: eight iterations 2: sixteen iteration Address Name Default Value Description

Datasheet for Telink TL3828 DS-TL3828-E5 599 Ver 0.8.0 afe_0x9a<7:0> ctb_irq_clr_b0 00000000 ctb irq clr[7:0] afe_0x9b<7:0> ctb_irq_clr_b1 00000000 ctb irq clr[15:8] afe_0x9c<1:0> ctb_error_irq_en 11 ctb error irq enable afe_0x9d<7:0> ctb_scan_time_target_b0 00000000 scan time for enabled channel[7:0] afe_0x9e<7:0> ctb_scan_time_target_b1 00000000 scan time for enabled channel[15:8] afe_0x9f<2:0> ctb_filter_gain_sel 000 000: divide by 1 001: divide by 2 010: divide by 4 011: divide by 8 100: divide by 16 101: divide by 32 110: divide by 64 111: divide by 128 afe_0xa0<7:0> ctb status read only [0]:rsvd [1]:pm_en_ctb_o (Enable signal for analog block) [2]: pm_ctb_startcount_o [6:3]:pm_ctb_chsel_o [7]:pm_ctbcmp_out_i afe_0xa1<7:0> ctb stepcode read only [4:0]:pm_ctb_fstepcode_o [7:5]:pm_ctb_lstepcode_o[2:0] afe_0xa2<7:0> ctb step code read only [1:0]:pm_ctb_lstepcode_o[4:3] [7:2]:pm_ctb_lstepword[5:0] afe_0xa3<7:0> ctb_lstepword read only [6:0]:pm_ctb_lstepword[12:6] [7]:rsvd afe_0xa4<7:0> pm_ctb_counter_out read only [7:0]:pm_ctbcounter_out_i[7:0] afe_0xa5<7:0> pm_ctb_counter_out read only [4:0]:pm_ctbcounter_out_i[12:8] [7:5]:rsvd afe_0xa6<7:0> pm_ctbcounter_out_fsm read only pm_ctbcounter_out_fsm[7:0] afe_0xa7<7:0> pm_ctbcounter_out_fsm read only [4:0]:pm_ctbounter_out_fsm[12:8] [5]:pm_ctbcmp_out_fsm [7:6]:rsvd Address Name Default Value Description

Datasheet for Telink TL3828 DS-TL3828-E5 600 Ver 0.8.0 afe_0xa8<7:0> ctb_error_irq_status read only [1:0]:ctb_error_irq_status [7:2]:rsvd afe_0xa9<7:0> ctb_count_o read only ctb_count_o[7:0] afe_0xaa<7:0> ctb_count_o read only [4:0]:ctb_count_o[12:8] [7:5]:rsvd afe_0xab<7:0> ctb_irq_status read only ctb_irq_status[7:0] afe_0xac<7:0> ctb_irq_status read only ctb_irq_status[15:8] afe_0xad<7:0> ctb channel num read only [3:0]:ctb_channel_num [7:4]:rsvd afe_0xae<0> ctb_error_irq read only ctb error interrupt afe_0xae<1> ctb_irq read only ctb interrupt afe_0xae<2> ctb_decision_en read only Enable for decision logic from FSM afe_0xae<3> ctb_irq_val read only Current counter value is upper thresold or not. afe_0xaf<7:0> ctb_reg00_o 0000 0011 [7]:tmux_da_vddh [6]:da_ctbbootstrapen [5]:da_ctb_cmphprmode [4:0]:da_ctb_oscitrim afe_0xb0<1:0> tmux_reg_buffa_vddh_o 0 [1:0]:tmux_reg_buffa_vddh_o afe_0xb0<2> scan_en 1 scan enable afe_0x19a<4:0> ctb_lstep_cfg_ch2 00000 Configuration of large step capacitors of channel 2 afe_0x19b<4:0> ctb_fstep_cfg_ch2 00000 Configuration of fine step capacitors of channel 2 afe_0x19c<4:0> ctb_lstep_cfg_ch3 00000 Configuration of large step capacitors of channel 3 afe_0x19d<4:0> ctb_fstep_cfg_ch3 00000 Configuration of fine step capacitors of channel 3 afe_0x19e<4:0> ctb_lstep_cfg_ch4 00000 Configuration of large step capacitors of channel 4 afe_0x19f<4:0> ctb_fstep_cfg_ch4 00000 Configuration of fine step capacitors of channel 4 afe_0x1a0<4:0> ctb_lstep_cfg_ch5 00000 Configuration of large step capacitors of channel 5 afe_0x1a1<4:0> ctb_fstep_cfg_ch5 00000 Configuration of fine step capacitors of channel 5 afe_0x1a2<4:0> ctb_lstep_cfg_ch6 00000 Configuration of large step capacitors of channel 6 afe_0x1a3<4:0> ctb_fstep_cfg_ch6 00000 Configuration of fine step capacitors of channel 6 Address Name Default Value Description

Datasheet for Telink TL3828 DS-TL3828-E5 601 Ver 0.8.0 afe_0x1a4<4:0> ctb_lstep_cfg_ch7 00000 Configuration of large step capacitors of channel 7 afe_0x1a5<4:0> ctb_fstep_cfg_ch7 00000 Configuration of fine step capacitors of channel 7 afe_0x1a6<4:0> ctb_lstep_cfg_ch8 00000 Configuration of large step capacitors of channel 8 afe_0x1a7<4:0> ctb_fstep_cfg_ch8 00000 Configuration of fine step capacitors of channel 8 afe_0x1a8<4:0> ctb_lstep_cfg_ch9 00000 Configuration of large step capacitors of channel 9 afe_0x1a9<4:0> ctb_fstep_cfg_ch9 00000 Configuration of fine step capacitors of channel 9 afe_0x1aa<4:0> ctb_lstep_cfg_ch10 00000 Configuration of large step capacitors of channel 10 afe_0x1ab<4:0> ctb_fstep_cfg_ch10 00000 Configuration of fine step capacitors of channel 10 afe_0x1ac<4:0> ctb_lstep_cfg_ch11 00000 Configuration of large step capacitors of channel 11 afe_0x1ad<4:0> ctb_fstep_cfg_ch11 00000 Configuration of fine step capacitors of channel 11 afe_0x1ae<4:0> ctb_lstep_cfg_ch12 00000 Configuration of large step capacitors of channel 12 afe_0x1af<4:0> ctb_fstep_cfg_ch12 00000 Configuration of fine step capacitors of channel 12 afe_0x1b0<4:0> ctb_lstep_cfg_ch13 00000 Configuration of large step capacitors of channel 13 afe_0x1b1<4:0> ctb_fstep_cfg_ch13 00000 Configuration of fine step capacitors of channel 13 afe_0x1b2<4:0> ctb_lstep_cfg_ch14 00000 Configuration of large step capacitors of channel 14 afe_0x1b3<4:0> ctb_fstep_cfg_ch14 00000 Configuration of fine step capacitors of channel 14 afe_0x1b4<4:0> ctb_lstep_cfg_ch15 00000 Configuration of large step capacitors of channel 15 afe_0x1b5<4:0> ctb_fstep_cfg_ch15 00000 Configuration of fine step capacitors of channel 15 afe_0x1b6<7:0> ctb_thre_ch2_byte0 01100000 Threshold value of channel 2[7:0] afe_0x1b7<4:0> ctb_thre_ch2_byte1 0 Threshold value of channel 2[12:8] afe_0x1b8<7:0> ctb_thre_ch3_byte0 01100000 Threshold value of channel 3[7:0] afe_0x1b9<4:0> ctb_thre_ch3_byte1 0 Threshold value of channel 3[12:8] afe_0x1ba<7:0> ctb_thre_ch4_byte0 01100000 Threshold value of channel 4[7:0] afe_0x1bb<4:0> ctb_thre_ch4_byte1 0 Threshold value of channel 4[12:8] afe_0x1bc<7:0> ctb_thre_ch5_byte0 01100000 Threshold value of channel 5[7:0] afe_0x1bd<4:0> ctb_thre_ch5_byte1 0 Threshold value of channel 5[12:8] afe_0x1be<7:0> ctb_thre_ch6_byte0 01100000 Threshold value of channel 6[7:0] afe_0x1bf<4:0> ctb_thre_ch6_byte1 0 Threshold value of channel 6[12:8] Address Name Default Value Description

Datasheet for Telink TL3828 DS-TL3828-E5 602 Ver 0.8.0 afe_0x1c0<7:0> ctb_thre_ch7_byte0 01100000 Threshold value of channel 7[7:0] afe_0x1c1<4:0> ctb_thre_ch7_byte1 0 Threshold value of channel 7[12:8] afe_0x1c2<7:0> ctb_thre_ch8_byte0 01100000 Threshold value of channel 8[7:0] afe_0x1c3<4:0> ctb_thre_ch8_byte1 0 Threshold value of channel 8[12:8] afe_0x1c4<7:0> ctb_thre_ch9_byte0 01100000 Threshold value of channel 9[7:0] afe_0x1c5<4:0> ctb_thre_ch9_byte1 0 Threshold value of channel 9[12:8] afe_0x1c6<7:0> ctb_thre_ch10_byte0 01100000 Threshold value of channel 10[7:0] afe_0x1c7<4:0> ctb_thre_ch10_byte1 0 Threshold value of channel 10[12:8] afe_0x1c8<7:0> ctb_thre_ch11_byte0 01100000 Threshold value of channel 11[7:0] afe_0x1c9<4:0> ctb_thre_ch11_byte1 0 Threshold value of channel 11[12:8] afe_0x1ca<7:0> ctb_thre_ch12_byte0 01100000 Threshold value of channel 12[7:0] afe_0x1cb<4:0> ctb_thre_ch12_byte1 0 Threshold value of channel 12[12:8] afe_0x1cc<7:0> ctb_thre_ch13_byte0 01100000 Threshold value of channel 13[7:0] afe_0x1cd<4:0> ctb_thre_ch13_byte1 0 Threshold value of channel 13[12:8] afe_0x1ce<7:0> ctb_thre_ch14_byte0 01100000 Threshold value of channel 14[7:0] afe_0x1cf<4:0> ctb_thre_ch14_byte1 0 Threshold value of channel 14[12:8] afe_0x1d0<7:0> ctb_thre_ch15_byte0 01100000 Threshold value of channel 15[7:0] afe_0x1d1<4:0> ctb_thre_ch15_byte1 0 Threshold value of channel 15[12:8] afe_0x1d2<7:0> ctb_switch_cap_val_ch2 _byte0 01010101 CH2 compare value to switch large step to fine step capacitors ladde[7:0] afe_0x1d3<4:0> ctb_switch_cap_val_ch2 _byte1 00000 CH2 compare value to switch large step to fine step capacitors ladde[12:8] afe_0x1d4<7:0> ctb_switch_cap_val_ch3 _byte0 01010101 CH3 compare value to switch large step to fine step capacitors ladde[7:0] afe_0x1d5<4:0> ctb_switch_cap_val_ch3 _byte1 00000 CH3 compare value to switch large step to fine step capacitors ladde[12:8] afe_0x1d6<7:0> ctb_switch_cap_val_ch4 _byte0 01010101 CH5 compare value to switch large step to fine step capacitors ladde[7:0] Address Name Default Value Description

Datasheet for Telink TL3828 DS-TL3828-E5 603 Ver 0.8.0 afe_0x1d7<4:0> ctb_switch_cap_val_ch4 _byte1 00000 CH5 compare value to switch large step to fine step capacitors ladde[12:8] afe_0x1d8<7:0> ctb_switch_cap_val_ch5 _byte0 01010101 CH4 compare value to switch large step to fine step capacitors ladde[7:0] afe_0x1d9<4:0> ctb_switch_cap_val_ch5 _byte1 00000 CH4 compare value to switch large step to fine step capacitors ladde[12:8] afe_0x1da<7:0> ctb_switch_cap_val_ch6 _byte0 01010101 CH6 compare value to switch large step to fine step capacitors ladde[7:0] afe_0x1db<4:0> ctb_switch_cap_val_ch6 _byte1 00000 CH6 compare value to switch large step to fine step capacitors ladde[12:8] afe_0x1dc<7:0> ctb_switch_cap_val_ch7 _byte0 01010101 CH7 compare value to switch large step to fine step capacitors ladde[7:0] afe_0x1dd<4:0> ctb_switch_cap_val_ch7 _byte1 00000 CH7 compare value to switch large step to fine step capacitors ladde[12:8] afe_0x1de<7:0> ctb_switch_cap_val_ch8 _byte0 01010101 CH8 compare value to switch large step to fine step capacitors ladde[7:0] afe_0x1df<4:0> ctb_switch_cap_val_ch8 _byte1 00000 CH8 compare value to switch large step to fine step capacitors ladde[12:8] afe_0x1e0<7:0> ctb_switch_cap_val_ch9 _byte0 01010101 CH9 compare value to switch large step to fine step capacitors ladde[7:0] afe_0x1e1<4:0> ctb_switch_cap_val_ch9 _byte1 00000 CH9 compare value to switch large step to fine step capacitors ladde[12:8] afe_0x1e2<7:0> ctb_switch_cap_val_ch10 _byte0 01010101 CH10 compare value to switch large step to fine step capacitors ladde[7:0] afe_0x1e3<4:0> ctb_switch_cap_val_ch10 _byte1 00000 CH10 compare value to switch large step to fine step capacitors ladde[12:8] afe_0x1e4<7:0> ctb_switch_cap_val_ch11 _byte0 01010101 CH11 compare value to switch large step to fine step capacitors ladde[7:0] afe_0x1e5<4:0> ctb_switch_cap_val_ch11 _byte1 00000 CH11 compare value to switch large step to fine step capacitors ladde[12:8] Address Name Default Value Description

Datasheet for Telink TL3828 DS-TL3828-E5 604 Ver 0.8.0 afe_0x1e6<7:0> ctb_switch_cap_val_ch12 _byte0 01010101 CH12 compare value to switch large step to fine step capacitors ladde[7:0] afe_0x1e7<4:0> ctb_switch_cap_val_ch12 _byte1 00000 CH12 compare value to switch large step to fine step capacitors ladde[12:8] afe_0x1e8<7:0> ctb_switch_cap_val_ch13 _byte0 01010101 CH13 compare value to switch large step to fine step capacitors ladde[7:0] afe_0x1e9<4:0> ctb_switch_cap_val_ch13 _byte1 00000 CH13 compare value to switch large step to fine step capacitors ladde[12:8] afe_0x1ea<7:0> ctb_switch_cap_val_ch14 _byte0 01010101 CH14 compare value to switch large step to fine step capacitors ladde[7:0] afe_0x1eb<4:0> ctb_switch_cap_val_ch14 _byte1 00000 CH14 compare value to switch large step to fine step capacitors ladde[12:8] afe_0x1ec<7:0> ctb_switch_cap_val_ch15 _byte0 01010101 CH15 compare value to switch large step to fine step capacitors ladde[7:0] afe_0x1ed<4:0> ctb_switch_cap_val_ch15 _byte1 00000 CH15 compare value to switch large step to fine step capacitors ladde[12:8] afe_0x1ee<0> ctb_calbr_min_max_en 0 enable recording max and min values without accu_en_i afe_0x1ee<1> ctb_clk_32k_en 0 ctb_clk for ctb_active_top enable afe_0x1ef<4:0> ctb_calbr_counter_val[7:0] read only The output calibration counter value[7:0 afe_0x1f0<4:0> ctb_calbr_counter_val[12:8] read only The output calibration counter value[12:8] afe_0x1f1<7:0> ctb_calbr_max[7:0] read only The maximum value captured[7:0] afe_0x1f2<4:0> ctb_calbr_max[12:8] read only The maximum value captured[12:8] afe_0x1f3<7:0> ctb_calbr_min[7:0] read only The manimum value captured[7:0] afe_0x1f4<4:0> ctb_calbr_min[12:8] read only The manimum value captured[12:8] afe_0x1f5<7:0> ctb_calbr_avg[7:0] read only The average of input values[7:0] afe_0x1f6<4:0> ctb_calbr_avg[12:8] read only The average of input values[12:8] afe_0x1f7<0> ctb_calbr_done read only Flag of calibration process done Address Name Default Value Description

Datasheet for Telink TL3828 DS-TL3828-E5 605 Ver 0.8.0

17 Low Power Comparator

The SoC embeds a low power comparator. This comparator takes two inputs: input derived from external PortB (PB[0]~PB[7]), and reference input derived from internal reference, PB[0], PB[3], or float. By comparing the input voltage multiplied by selected scaling coefficient with reference input voltage, the low power comparator will output high or low level accordingly. Figure 17-1 Block Diagram of Low Power Comparator

17.1 Power On/Down

The low power comparator is powered down by default. The analog register afe_0x06<1> serves to control power state of the low power comparator: By clearing this bit, this comparator will be powered on; by setting this bit to 1’b1, this comparator will be powered down. To use the low power comparator, first set afe_0x06<1> as 1’b0, then the 32K RC clock source is enabled as the comparator clock. In order to improve the robustness of the chip during high-speed operation, the low power comparator (LPC) is used to protect the flash during power-down of the chip. When this function is enabled, the chip power supply voltage is limited to 2.1V to 4.5V, one of PB[1:7] must be reserved for this function, one channel of DMA 0-7 must be reserved for this function; and one channel of PEM must also be reserved for this function. Low power Comparator input reference Reference select Analog Register: afe_0x88[0] afe_0x0d<6:4> Normal mode: afe_0x0b<3>=1 afe_0x0d<7>=0 820mV 872mV 923mV 974mV afe_0x0b<5:4> Scaling select 25% 75%50% 100% afe_0x0d<2:0> Input channel select PB[1] 000 001 010 011 100 101 110 111 111 110 101 100 011 010 001 000 00 01 10 11 afe_0x0d<6:4> Low power mode: afe_0x0b<3>=0 afe_0x0d<7>=1 810mV 862mV 913mV 964mV 111 110 101 100 011 010 001 000 PB[2] PB[3] PB[4] PB[5] PB[6] PB[7] PB[3] PB[0] PB[3] PB[0] PB[0] NOTE: The difference between the input level and the wake-up level needs to be greater than 100mV when using Low Power Comparator wake-up mode to enter sleep.

Datasheet for Telink TL3828 DS-TL3828-E5 606 Ver 0.8.0

17.2 Select Input Channel

Input channel is selectable from the PortB (PB[0]~PB[7]) via the analog register afe_0x0d<2:0>.

17.3 Select Mode and Input Channel for Reference

Generally, it’s needed to set the afe_0x0b<3> as 1’b1 and set afe_0x0d<7> as 1’b0 to select the normal mode. In normal mode, the internal reference is derived from Bandgap and has higher accuracy, but current bias is larger (10 µA); reference voltage input channel is selectable from internal reference of 974 mV, 923 mV, 872 mV and 820 mV, as well as PB[0], PB[3], and float. To select the low power mode, it’s needed to set the afe_0x0b<3> as 1’b0 and set the afe_0x0d<7> as 1’b1. In low power mode, the internal reference is derived from UVLO and has lower accuracy, but current bias is decreased to 50 nA; reference voltage input channel is selectable from internal reference of 964 mV, 913 mV, 862 mV and 810 mV, as well as PB[0], PB[3], and float.

17.4 Select Scaling Coefficient

Equivalent reference voltage equals the selected reference input voltage divided by scaling coefficient. The analog register afe_0x0b<5:4> serves to select one of the four scaling options: 25%, 50%, 75% and 100%.

17.5 Low Power Comparator Output

The low power comparator output is determined by the comparison result of the value of [input voltage *scaling] and reference voltage input. The comparison principle is shown as below:

• If the value of [input voltage *scaling] is larger than reference voltage input, the output will be low (“0”).
• If the value of [input voltage *scaling] is lower than reference voltage input, the output will be high (“1”).
• If the value of [input voltage *scaling] equals reference voltage input, or input channel is selected as float, the output will be uncertain. User can read the output of the low power comparator via the analog register afe_0x88[0]. The output of the low power comparator can be used as signal to wakeup system from low power modes.

17.6 Register Description of Low Power Comparator

Table 17-1 Analog Register Related to Low Power Comparator Address Description Default Value afe_0x06<1> Power down of low current comparator: 1: Power down 0: Power up

Datasheet for Telink TL3828 DS-TL3828-E5 607 Ver 0.8.0 afe_0x0b<3> Reference mode select: 1: ref from BG; 0: ref from UVLO. afe_0x0b<5:4> Reference voltage scaling: 11: 100% 10: 75% 01: 50% 00: 25% afe_0x0d<2:0> channel select of lc comparator: 000: B[0] 001: B[1] 010: B[2] 011: B[3] 100: B[4] 101: B[5] 110: B[6] 111: B[7] 000 afe_0x0d<3> lc_comp_vbus_inen, inner detect point enable: 1: enable; 0: disable afe_0x0d<6:4> lc_comp_refsel<2:0> channel select of lc comparator: 0x000 -> float 0x001 -> 974mV 0x010 -> 923mV 0x011 -> 872mV 0x100 -> 820mV 0x101 -> B[0] 0x110 -> B[3] 0x111 -> avddh 000 afe_0x0d<7> lc_comp_pd_10u power down of 10u current to voltage reference 1: power down; 0: active afe_0x0e<3> lc_cmp_current_option 0 Address Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 608 Ver 0.8.0 afe_0x4b<3> comparator wakeup enable 0 afe_0x4d<0> pd_lc_comp auto 1: auto power down low power comparator Address Description Default Value

Datasheet for Telink TL3828 DS-TL3828-E5 609 Ver 0.8.0

18 Security Solution

18.1 Hardware Security Module (HSM)

The SoC features an integrated Hardware Security Module (HSM), which is an independent secure processing black box avoiding confidential material’s exposure to the outside. It utilizes a proprietary controller and dedicated memory to support accelerated cryptographic operations, secure key management, and random number generation. Its purpose is to provide a secure environment for applications to execute cryptographic services. Currently, the chip's hardware accelerator supports hardware security functions such as hashes, encryption and decryption algorithms, random number generation, signature generation, and verification. The HSM includes the following cryptographic functions:

• Cryptographic Accelerator º Symmetric Key Engine (SKE), supports AES-128/192/256 º Public Key Engine (PKE), supports ECC (ECDH + ECDSA, 192/224/256/521 bits), RSA (512 ~4096 bits) º Hash accelerator, supports SHA-1, SHA224/256/384/512
• True Random Number Generator (TRNG)
• Root of Trust
• Secure Boot
• Secure OTA
• Firmware encryption
• Secure Debug Port Control
• Prevent any unauthorized or maliciously modified software from running
• Signature and verification based on RSA2048 or ECC256
• Secure Key Management
• Secure Attestation

18.1.1 Symmetric Key Engine (SKE)

The SKE module contains a low-power symmetric encryption algorithm engine, and its features include:

• Supports algorithm of AES-128, AES-192, AES-256
• Supports hardware of ECB, CBC, CTR, CFB, OFB, GCM, CCM After power-on reset of the HSM, the SKE is in an idle state. At this time, the SKE waits for operation commands from the HSM core, which are usually triggered by the CPU’s requests. Before calling SKE inside the HSM to perform the operation, the CPU needs to write the data and configuration required for the operation into the share memory, and then trigger HSM to perform the operation through the mailbox. During the operation of SKE, the CPU can query the status by polling HSM to determine whether the operation is finished or not. The following diagram is the SKE decryption block diagram, and the encryption process is similar.

Datasheet for Telink TL3828 DS-TL3828-E5 610 Ver 0.8.0 Figure 18-1 Diagram of SKE Decryption

18.1.2 Public Key Engine (PKE)

The Public Key Engine (PKE) contains a low-power version of the public key cryptography acceleration engine, which can support a variety of asymmetric cryptographic algorithms. It should be noted that to fully implement SM2, ECDSA and ECDH functions, a random number generator module and a Hash module are required. In this version, the following features are available:

• Supports modular operations: modular addition, modular subtraction, modular multiplication, modular exponentiation, modular inverse
• Supports elliptic curve point operations: point addition, point doubling, point multiplication, and verify whether the point is on the curve
• Supports large number operations: large number multiplication
• Supports both interrupt and polling methods for the host computer to query status PKE is designed to accelerate large number operations involved in RSA and Elliptic Curve Cryptography (ECC) operations in public key cryptography. Recently PKE can directly complete modular exponentiation in RSA and point multiplication in ECC. The PKE includes one program memory unit (ROM), one instruction arithmetic unit (IEU), one 32-bit arithmetic unit (ALU), two pseudo-double-ended data RAMs, one register combination with interface module within the independent HSM. According to requests from CPU to the HSM, the PKE can complete the following operations of different precisions:
• RSA: length 512 ~ 4096 bits, 32-bit step
• ECC (prime field): length 192, 224, 256, and 521 bits
• Ed25519/X25519
• SM2 The CPU outside the HSM can obtain the result of target operation finish by PKE through dedicated mailbox and share memory between CPU and HSM. The following diagram is the PKE decryption block diagram, and the encryption process is similar. SKE Core RAM Encrypted Data Decrypted Data HSM Mailbox

Datasheet for Telink TL3828 DS-TL3828-E5 611 Ver 0.8.0 Figure 18-2 Diagram of PKE Decryption

18.1.3 Low-Power Hash Accelerator (HASH)

The HASH contains a low-power hash algorithm engine, and its features include:

• Supports algorithm of MD5, SHA1, SHA224, SHA256, SHA384, SHA512
• Supports hardware of DMA mode
• Supports hardware byte padding
• Supports polling mode or interrupt mode for the host computer to query the status

18.1.4 True Random Number Generator (TRNG)

The True Random Number Generator (TRNG) module contains both a true random number generator and a pseudo-random number generator, and features include:

• Meets NIST SP800-90 a/b/c and GM 0008-2012 design requirements.
• Post-processing algorithm supports CTR-SM4.
• Output random numbers pass NIST SP800-22 and GM 0005-2012 tests.
• Supports online health monitoring of random numbers.
• Supports interrupts.
• Supports shutting down the TRNG module to save power consumption. After power-on reset of the HSM, TRNG is enabled by default. The entropy source loop is configured to be fully enabled by default.

18.2 Secure Boot, Firmware Encryption and Secure Debug

18.2.1 Introduction

The SoC supports security solution including secure boot, firmware encryption and secure debug. These functions are realized by running the first stage bootloader in Boot-ROM code. PKE Core RAM Encrypted Data Decrypted Data HSM Mailbox

Datasheet for Telink TL3828 DS-TL3828-E5 612 Ver 0.8.0 The Secure Boot prevents the chip from running any unauthorized firmware by checking that the firmware being booted is verified by Elliptic Curve Digital Signature Algorithm (ECDSA). The key pair (public key/private key) is generated by Elliptic Curve Cryptography (ECC). The user signs the firmware with a private key through the secure boot tool, and the chip side verifies the signature with a public key before running the firmware. The signature verification ensures that only verified code can be executed, otherwise the firmware is considered tampered and will not be executed. The Secure Boot process follows these steps: On startup, first stage bootloader checks the Secure mode selection bit. If Secure Boot is disabled, a normal boot will be executed. If Secure Boot is enabled, the boot will proceed according to the following steps. First stage bootloader verifies the public key hash, calculates the hash value of the public key (in flash), and compares it with the public key hash (in Secure Storage). Only if they are equal, first stage bootloader will authenticate the firmware (run code) signature. The diagram describing the process of ECDSA key pair generating and signature signing is as below. Figure 18-3 Diagram of Key Pair Generating and Signature Signing In order to protect the firmware from being cloned, the firmware encryption can be used. Firmware encryption adopts a lightweight symmetric cipher algorithm based on Feistel structure (similar structure as used in DES, Triple DES, Blowfish,…) block cipher with eight rounds of iterations, ensuring both security and real-time performance. The firmware stored in the flash is Ciphertext. When the chip is running, it will decrypt the firmware in real time. The Secure Debug allows all debug interfaces such as SWS and JTAG to be locked so that hackers will not be able to access any on-chip information (registers or memories) from these debug interfaces. The user can use the tool to re-enable debug interface again. When dbg_unlock_boot_mode=1, in the first stage bootloader, as shown in the figure below, the chip acts as the SW (Single Wire) master, and the tool acts as the SW slave. After the SWM actively exchanges the random numbers (random1 and random2), the tool will use the debug_key to compute AES ciphertexts by using random1 and random2 as a set of original texts. The chip will do the same, read out the AES ciphertext from the tool and compare it with its own AES ciphertext, and the debug interfaces will be reopened if the two results are the same. When dbg_unlock_boot_mode=0 (default), users can design and verify an authentication mechanism such as challenge-response mechanism in non-first stage bootloader, and set the corresponding registers to re-open the debug interfaces after verification. Private key Public key ECDSA_sign Signature Hash Run code Secure Boot Tool Public key Hash Public key Public key Hash ==? Fail Signature ECDSA_verify Run code Hash Success or Fail Public key Hash First Stage Bootloader eFuse/OTP Flash N Y

Datasheet for Telink TL3828 DS-TL3828-E5 613 Ver 0.8.0 Figure 18-4 Secure debug activation mechanism

18.2.2 Key Management

The Flash Key is used for Firmware Encryption, the Debug Key is used to re-enable debug interface. The flash key and debug key are burned into eFuse directly without any derivation. The chip has a key lock mechanism, once the key lock function is enabled (key_lock=1), the software cannot read the flash key and debug text in the eFuse.

18.2.3 Flash Space

The flash contains several segments of data including code 0 & 1, and their corresponding code descriptor block 0 & 1. When allocating flash, each segment area should not overlap, and the first address of each segment address is recommended to be aligned with the smallest erase unit of flash. The code descriptor block is only present if secure boot with firmware signature verification is enabled. The run code 0, which has a fixed starting address of 0, is the firmware code to be executed. The starting address of run code 1 should be an integer multiple of 4K bytes. It is in plaintext if firmware encryption is not enabled; If the firmware encryption is enabled, the code is stored as ciphertext (encrypted firmware). The code is automatically loaded after power on, and the user should leave a corresponding size of flash space. The code descriptor block provides information about the corresponding firmware code.

• The public key is the public key used to verify the code signature.
• The run code signature is the calculated signature over the running code.
• The run code address is the starting address of the running code.
• The run code size is the length of the code field in Bytes.
• The watchdog target value is the watchdog capture value. This value should be set large enough to allow firmware signature verification process to finish before watchdog resets, please use the default value provided by Telink.

18.2.4 Usage

The chip has two modes: normal mode and secure boot mode. The two modes are configured by mode_selection in eFuse. If mode_seletion is 1, it is secure boot mode. If mode_seletion is 0, it is normal mode. The following decision tree can be used to select appropriate secure mechanisms.

Datasheet for Telink TL3828 DS-TL3828-E5 614 Ver 0.8.0 Figure 18-5 Decision Tree for Secure Boot In normal mode, the firmware runs from address offset 0K/64K/128K/256K/512K/1M/2M/4M/8M bytes of Flash without the code descriptor. In secure boot mode, the firmware needs to verify the signature with the code descriptor. When security is required, typically these 3 combinations below will satisfy most use cases.

• Firmware Signature Verification + Secure Debug
• Firmware Encryption + Secure Debug
• Firmware Signature Verification +Firmware Encryption +Secure Debug There may be other possible configuration bits combinations, but it is not recommended using them except for the above cases. 1. Signature verification only without encryption: Firmware encryption disabled, mode selection set to secure mode. In this case, firmware is stored in plaintext on the Flash, the code descriptor information is used to verify its signature. 2. Encryption only without signature verification: Firmware encryption enabled, mode selection set to normal mode. In this case, the firmware stored on the Flash is encrypted. It is decrypted in real-time during running. 3. Encryption and signature verification: Firmware encryption enabled, mode selection set to secure mode. In this case, firmware is stored in ciphertext on the Flash, and the code descriptor information is used to verify its signature on the original plaintext. After setting up the case above, disable all the debugging interfaces including sws_dbg_enable and jtag_dbg_enable. If the user wants to re-enable debug interface function, use the BDT tool to re-enable the debug interface again. Start Security needed? Use normal mode (default) No Yes Secure Boot mode Normal mode + Firmware Encryption Secure Boot mode + Firmware Encryption Secure Debug Enabled Only firmware signature verification needed Firmware encryption needed Both firmware signature and firmware encryption needed