TC3215CE09T48R

TC3216CE10T48R TELINK | Alldatasheet

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Ver 0.8.1 2026/02/06 Keyword Bluetooth® LE; 2.4 GHz Brief This datasheet is dedicated for Telink Bluetooth LE SoC TC321x (TC3216C, TC3215C, TC3215E, TC3215F, TC3215M). In this datasheet, function block diagram, key features, electrical specifications, and typical applications of the TC321x are introduced.

Datasheet for Telink TC321x DS-TC321x-E7 1 Ver 0.8.1 Published by Telink Semiconductor 10-11/F, Building 1, 61 Shengxia Road, Pudong District, Shanghai, China 201203 © Telink Semiconductor All Rights Reserved Legal Disclaimer This document is provided as-is. Telink Semiconductor reserves the right to make improvements without further notice to this document or any products herein. This document may contain technical inaccuracies or typographical errors. Telink Semiconductor disclaims any and all liability for any errors, inaccuracies or incompleteness contained herein. Copyright © 2026 Telink Semiconductor (Shanghai) Co., Ltd. Information For further information on the technology, product and business term, please contact Telink Semiconductor Company (www.telink-semi.com). For sales or technical support, please send email to the address of: telinksales@telink-semi.com telinksupport@telink-semi.com

Datasheet for Telink TC321x DS-TC321x-E7 2 Ver 0.8.1

Revision History

Version Change Description

0.1.0 Preliminary release

0.2.0 Added chapter 2 ~ 3

0.5.0 Added chapter 4 ~ 18

0.5.1 Updated 1.4 Ordering Information, 1.6.3 Pin assignment of TC3215F, 3.5 Reference Schematic of TC3215F, 3.6 BOM (Bill of Material) of TC3215F 0.5.2 assignment of TC3215M, Table 2-3 RX/TX Current and Sleep Current, Table 2-9 ADC Characteristics, Chapter 3 Reference Design 0.8.0 Updated Figure 1-1 Block Diagram of the System, Table 2-3 RX/TX Current and Sleep Current, Table 2-

9 ADC Characteristics, Table 2-10 Analog Microphone / Line Input to ADC Path, Table 4-1 eFuse

Definition, Table 4-2 Working Modes, Table 4-3 Retention Analog Registers in Deep Sleep, Figure 5-3 Audio CODEC Decimation, 11.4 SPI, 16.1 Overview of SD ADC, Table 18-1 eFuse Data for Secure Debug 0.8.1 Added 2.5 ESD Characteristics, added a note in Chapter 3 Reference Design Deleted Table 1-26 32kHz crystal and digital pull-up in the note of 11.1.2 GPIO Logic Introduction Other minor edits and corrections

Datasheet for Telink TC321x DS-TC321x-E7 3 Ver 0.8.1 Table of Contents

Datasheet for Telink TC321x DS-TC321x-E7 4 Ver 0.8.1

Datasheet for Telink TC321x DS-TC321x-E7 5 Ver 0.8.1

Datasheet for Telink TC321x DS-TC321x-E7 6 Ver 0.8.1

Datasheet for Telink TC321x DS-TC321x-E7 7 Ver 0.8.1

Datasheet for Telink TC321x DS-TC321x-E7 8 Ver 0.8.1

Datasheet for Telink TC321x DS-TC321x-E7 12 Ver 0.8.1 List of Tables

Datasheet for Telink TC321x DS-TC321x-E7 13 Ver 0.8.1

Datasheet for Telink TC321x DS-TC321x-E7 14 Ver 0.8.1

Datasheet for Telink TC321x DS-TC321x-E7 15 Ver 0.8.1

Datasheet for Telink TC321x DS-TC321x-E7 16 Ver 0.8.1

1 Overview

The TC321x is a single System on Chip (SoC) for Bluetooth low energy (LE) and 2.4 GHz proprietary protocol. The TC321x supports standards and industrial alliance specifications including Bluetooth LE and 2.4 GHz proprietary standard. The TC321x combines the features and functions needed for high quality wireless IoT equipments into a single SoC.

1.1 Block Diagram

The TC321x is designed to offer high integration, ultra-low power application capabilities. The system's block diagram is as shown in Figure 1-1. Figure 1-1 Block Diagram of the System The TC321x integrates a low power 32-bit proprietary MCU, 64 KB SRAM including up to 64 KB retention SRAM, with 1024 KB / 512 KB embedded flash (details refer to Table 1-1 Ordering Information of TC321x), up to 16-bit SD ADC, PWM, flexible IO interfaces, and other peripheral blocks required for IoT applications. With the high integration level of TC321x, few external components are needed to satisfy customers' ultra-low cost requirements.

1.2 Key Features

1.2.1 General Features

General features are as follows: GPIO I2C I2S UART PWM Interfaces Swire 24MHz RC Oscillator 32kHz RC Oscillator System PLL Clock 24MHz Crystal Oscillator AMICAES Security Secure Debug Power Management Power-On Reset Power Management Controller Reset LDO/DCDC Bluetooth LE/ 2.4GHz Radio Timer/Watchdog 32kHz LTimer System Timer Timer Memory SRAM Flash RF Core 32-bit Proprietary MCU DMA MSPI GSPI Brown Out QDECADC DMIC SDM IR Keyscan

Datasheet for Telink TC321x DS-TC321x-E7 17 Ver 0.8.1 1. Supports 128-bit Unique ID (UID) 2. Telink 32-bit core system

• 32-bit proprietary micro-controller TC32
• Instruction cache controller
• Maximum running speed up to 48 MHz
• Support SWS debug interface 3. Memory architecture
• Program memory: 1024 KB / 512 KB embedded flash options
• 64 KB SRAM including up to 64 KB retention SRAM
• 128-bit eFuse 4. Timers
• Clock source of 24 MHz Crystal and 24 MHz & 32 kHz embedded RC oscillator
• Three general 32-bit timers with four selectable modes in active mode
• Two watchdog timers, one is always-on (AON)
• A low-frequency 32 kHz timer available in low power mode 5. Security solution
• Secure Debug Port Control
• Prevent any unauthorized or maliciously modified software from running
• Embedded hardware AES 6. A rich set of digital and analog interfaces
• Total 34/21/23/7 GPIOs (details refer to Table 1-1 Ordering Information of TC321x)
• 2 different SPI channels º MSPI: Memory SPI1 – Up to 48 MHz SPI clock – Supports Dual/Single data line – Supports Nor-Flash interface º GSPI: General SPI – Up to 24 MHz SPI clock – Supports Single data line
• 1-channel I2C
• 3-channel UART º one UART supports DMA channel
• Supports SWS debug interface
• Key scan 8*18
• 1-channel I2S
• 2-channel SDM
• Up to 6 channels of differential PWM º IR transmitter with DMA 1. The MSPI interface is used internally and is not available externally; the corresponding pins are not bonded out on the SoC.

Datasheet for Telink TC321x DS-TC321x-E7 18 Ver 0.8.1

• IR Learning hardware º Hardware accelerator for learning º BOM-saving for external components
• One quadrature decoder (QDEC), two-phase input selectable
• Single-channel differential AMIC (Analog MIC) and dual-channel DMIC (Digital MIC) sharing chain
• Up to 16-bit auxiliary SD-ADC 7. Supports OTA upgrade and Secure boot switch, allowing convenient product feature roll outs and upgrades 8. Operating temperature range: -40°C ~ +85°C 9. Completely RoHS-compliant package
• TC3216C/TC3215C, 48-pin QFN, 7x7x0.75mm
• TC3215E, 32-pin QFN, 4x4x0.75mm
• TC3215F, 32-pin QFN, 5x5x0.75mm
• TC3215M, 16-pin TSSOP, 5.02x6.4x1.2mm

1.2.2 RF Features

RF features include: 1. Bluetooth / 2.4 GHz RF transceiver in worldwide 2.4 GHz ISM band 2. Bluetooth LE 1 Mbps and 2 Mbps 3. 2.4 GHz proprietary 1 Mbps / 2 Mbps / 250 kbps / 500 kbps mode 4. Rx Sensitivity: -97 dBm @ LE 1 Mbps, -94 dBm @ LE 2 Mbps mode 5. 1-N-Receiver 6. TX output power: up to +10 dBm @ GFSK modulation 7. 50 Ω matched single-pin antenna input 8. RSSI monitoring with +/-1 dB resolution 9. Auto acknowledgment, retransmission and flow control

1.2.3 Features of Power Management Module

Features of power management module include: 1. Power supply

• VDD: 1.7 V ~ 3.6 V 2. Embedded LDO and DCDC
• DCDC SISO for chip with bypass LDO 3. Battery monitor for low battery voltage detection 4. Brownout detection/shutdown and Power-On-Reset 5. Low power consumption:
• Whole chip, RX mode: 4.1 mA @ 3.3V DCDC, 9.4 mA with LDO
• Whole chip, TX mode @ 0dBm: 4.6 mA @ 3.3V DCDC, 11.1 mA with LDO
• Deep sleep with IO wakeup (without SRAM retention): 0.5 µA
• Deep sleep with IO wakeup (with SRAM retention): 1.5 µA with 32 KB SRAM retention, 1.8 µA with 64 KB SRAM retention

Datasheet for Telink TC321x DS-TC321x-E7 19 Ver 0.8.1

• Deep sleep with IO wakeup with 32 KHz RC oscillator on (without SRAM retention):0.9 µA
• Deep sleep with IO wakeup with 32 KHz RC oscillator on (with SRAM retention): 1.8 µA with 32 KB SRAM retention, 2.1 µA with 64 KB SRAM retention
• Shut down mode: 0.2 µA

1.2.4 Bluetooth LE Features

Bluetooth LE features include: 1. Qualified Bluetooth® LE 5.4, main features include Bluetooth LE 1Mbps and 2Mbps

1.2.5 Flash Features

The TC321xWNF180SOLARIS_A1 embeds flash with features below: 1. Total 1024 / 512 KB 2. Flexible architecture: 4 KB per sector, 64 KB / 32 KB per block 3. Up to 256 bytes per programmable page 4. Write protect all or portions of memory 5. Sector erase (4 KB) 6. Block erase (32 KB / 64 KB) 7. Cycle endurance: 100,000 program/erases 8. Data retention: typical 20-year retention

1.2.6 Concurrent Mode Features

In concurrent mode, the chip supports multiple standards working concurrently. Typical combinations Bluetooth LE + 2.4 GHz. In concurrent modes, stacks can run concurrently with one application state but different protocols for interacting with different devices.

1.3 Typical Applications

The TC321x is an ideal SoC for IoT applications. Its typical applications include, but are not limited to the following:

• Smart RF remote control
• Keyboard, mouse
• Smart home device
• Smart lighting device
• Wireless HID
• Wearable device
• Asset tracking device

Datasheet for Telink TC321x DS-TC321x-E7 20 Ver 0.8.1

1.4 Ordering Information

Table 1-1 Ordering Information of TC321x Product Series Ordering No. SRAM (KB) Flash (KB) BLE 5.4 2.4 GHz SD ADC Pack inga a. Packing method “T&R” means tape and reel. The tape and reel material DO NOT support baking under high temperature. MOQb b. MOQ stands for Minimum Ordering Quantity. TC321x TC3216C E10T48R 64 1024 Y Y 16-bit 34 QFN48c 7x7x0.75mm c. QFN48 for TC3216C: 10x SD ADC channel, 1x AMIC, 1x DMIC, 3x Timer, 1x I2C, 1x I2S, 3x UART, 2x SPI, 6x PWM, 1x IR -40°C ~+85°C T&R 3000 TC3215C E09T48R 64 512 Y Y 16-bit 34 QFN48d 7x7x0.75mm d. QFN48 for TC3215C: 10x SD ADC channel, 1x AMIC, 1x DMIC, 3x Timer, 1x I2C, 1x I2S, 3x UART, 2x SPI, 6x PWM, 1x IR -40°C ~+85°C T&R 3000 TC3215E E09T32R 64 512 Y Y 16-bit 21 QFN32e 4x4x0.75mm e. QFN32 for TC3215E: 9x SD ADC channel, 1x AMIC, 1x DMIC, 3x Timer, 1x I2C, 1x I2S, 3x UART, 2x SPI, 6x PWM, 1x IR -40°C ~+85°C T&R 3000 TC3215F E09T32R 64 512 Y Y 12-bit 23f f. It includes the IR pin. QFN32g 5x5x0.75mm g. QFN32 for TC3215F: 9x SD ADC channel, 1x AMIC, 1x DMIC, 3x Timer, 1x I2C, 1x I2S, 3x UART, 2x SPI, 6x PWM, 1x IR -40°C ~+85°C T&R 3000 TC3215M E09S16R 64 512 Y Y 12-bit 7 TSSOP16h 5.02x6.4x1.2mm h. TSSOP16 for TC3215M: 1x SD ADC channel, 0x AMIC, 1x DMIC, 3x Timer, 1x I2C, 1x I2S, 3x UART, 2x SPI, 6x PWM, 0x IR -40°C ~+85°C T&R 5000

Datasheet for Telink TC321x DS-TC321x-E7 21 Ver 0.8.1

1.5 Package

1.5.1 Package Dimensions of TC3216C/TC3215C

Figure 1-2 Package of TC32156C/TC3215C g

Datasheet for Telink TC321x DS-TC321x-E7 22 Ver 0.8.1 Table 1-2 Mechanical Dimension of TC3216C/TC3215C SYMBOL MILLIMETER MIN NOM MAX A 0.7 0.75 0.8 A1 0 0.02 0.05 A2 - 0.55 - A3 0.203 REF b 0.2 0.25 0.3 b1 0.2 0.25 0.3 D 7 BSC E 7 BSC e 0.5 BSC D2 3.1 3.2 3.3 E2 3.1 3.2 3.3 L 0.3 0.4 0.5 L1 0.125 REF K 1.5 REF aaa 0.1 ccc 0.1 ddd 0.08 eee 0.1 fff 0.1

Datasheet for Telink TC321x DS-TC321x-E7 23 Ver 0.8.1

1.5.2 Package Dimensions of TC3215E

Figure 1-3 Package of TC3215E

Datasheet for Telink TC321x DS-TC321x-E7 24 Ver 0.8.1 Table 1-3 Mechanical Dimension of TC3215E SYMBOL MILLIMETER MIN NOM MAX A 0.7 0.75 0.8 A1 0 0.02 0.05 A2 - 0.55 - A3 0.203 REF b 0.15 0.2 0.25 D 4 BSC E 4 BSC e 0.4 BSC D2 2.7 2.8 2.9 E2 2.7 2.8 2.9 L 0.2 0.3 0.4 K 0.3 REF aaa 0.1 ccc 0.1 ddd 0.08 eee 0.07 fff 0.1

Datasheet for Telink TC321x DS-TC321x-E7 25 Ver 0.8.1

1.5.3 Package Dimensions of TC3215F

Figure 1-4 Package of TC3215F Table 1-4 Mechanical Dimension of TC3215F SYMBOL MILLIMETER MIN NOM MAX A 0.70 0.75 0.80 A1 0 0.02 0.05 b 0.20 0.25 0.30 b1 0.18REF b2 0.20 0.25 0.30 c 0.203REF D 4.90 5.00 5.10 D2 3.40 3.50 3.60 e 0.50BSC Nd 3.50BSC TOP VIEW BOTTOM VIEW SIDE VIEW Laser Mark PIN 1# **Special design: the four corners of the product are designed with four bumps.

Datasheet for Telink TC321x DS-TC321x-E7 26 Ver 0.8.1 Ne 3.50BSC E 4.90 5.00 5.10 E2 3.40 3.50 3.60 L 0.35 0.40 0.45 L1 0.15REF h 0.30 0.35 0.40 K 0.35REF K1 0.225REF SYMBOL MILLIMETER MIN NOM MAX

Datasheet for Telink TC321x DS-TC321x-E7 27 Ver 0.8.1

1.5.4 Package Dimensions of TC3215M

Figure 1-5 Package of TC3215M Table 1-5 Mechanical Dimension of TC3215M SYMBOL MILLIMETER MIN NOM MAX A - - 1.20 A1 0.05 0.10 0.15 A2 0.965 1.000 1.035 ș TOP VIEW SIDE VIEW SIDE VIEW ș ș ș ș

Datasheet for Telink TC321x DS-TC321x-E7 28 Ver 0.8.1 A3 0.415 0.440 0.465 b 0.200 - 0.280 D 4.92 5.02 5.12 E 6.20 6.40 6.60 E1 4.30 4.40 4.50 e 0.65 BSC L 0.45 0.60 0.75 L1 1.00 REF L2 0.25 REF Ɵ 0° - 8° Ɵ1-Ɵ4 12° REF R1 0.15 REF R2 0.15 REF SYMBOL MILLIMETER MIN NOM MAX

Datasheet for Telink TC321x DS-TC321x-E7 29 Ver 0.8.1

1.6 Pin Layout

1.6.1 Pin assignment of TC3216C/TC3215C

Figure 1-6 Pin Assignment of TC3216C/TC3215C Functions of 48 pins are described in table below. Table 1-6 Pin Function of TC3216C/TC3215C No. Pin Name Type Description

1 PB[1] GPIO General Purpose IO

2 PB[0] GPIO General Purpose IO

3 PD[7] GPIO General Purpose IO

48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 PD[7] PD[6] PD[5] PD[4] PD[3] PD[0] DVSS PE[1] VDD1V_DEC VDD1V2 DCDC_SW VDDIO_AMS PB[6] PB[5] PB[4] IR ANT PC[0] PC[1] PC[2] XC2 XC1 POR PA[1] PA[2] PA[3] PA[4] PA[5] PA[6] PA[7] PB[3] PB[2] PB[1] PB[0] GND TC3216C TC3215C VDDF PC[3] VMID PD[1] PE[0] PB[7] PD[2] PC[7] PC[6] PC[5] PC[4] PA[0] NC

Datasheet for Telink TC321x DS-TC321x-E7 30 Ver 0.8.1

4 PD[6] GPIO General Purpose IO

5 PD[5] GPIO General Purpose IO

6 PD[4] GPIO General Purpose IO

7 PD[3] GPIO General Purpose IO

8 PD[2] GPIO General Purpose IO

9 PD[1] GPIO General Purpose IO

10 NC - Not connected

11 PD[0] GPIO General Purpose IO

12 PE[0] GPIO General Purpose IO

13 PE[1] GPIO General Purpose IO

14 DVSS GND Digital core ground

15 VDD1V_DEC PWR 1V digital power supply

16 DCDC_SW Analog Connected with VDCDC via external inductor

17 VDD1V2 PWR 1.2V digital power supply 18 VDDF PWR Internally generated power supply to flash. Connect to GND via external capacitor

19 PB[4] GPIO General Purpose IO

20 PB[5] GPIO General Purpose IO

21 PB[6] GPIO General Purpose IO

22 PB[7] GPIO General Purpose IO

23 IR Analog Infrared radiation learning

24 VDDIO_AMS PWR IO voltage for AMS

25 PC[0] GPIO General Purpose IO

26 PC[1] GPIO General Purpose IO

27 PC[2] GPIO General Purpose IO

28 PC[3] GPIO General Purpose IO

29 VMID Analog Audio pin connecting to external decap

30 XC2 Analog Crystal oscillator pin 2

31 XC1 Analog Crystal oscillator pin 1

No. Pin Name Type Description

Datasheet for Telink TC321x DS-TC321x-E7 31 Ver 0.8.1 The multiplexed functions for GPIO pins are listed as below. Table 1-7 GPIO Pin Mux of TC3216C/TC3215C

32 PC[4] GPIO General Purpose IO

33 PC[5] GPIO General Purpose IO

34 PC[6] GPIO General Purpose IO

35 PC[7] GPIO General Purpose IO

36 POR Analog Power on reset

37 ANT Analog Pin to connect to the antenna through the matching network

38 GND GND Ground

39 PA[0] GPIO General Purpose IO

40 PA[1] GPIO General Purpose IO

41 PA[2] GPIO General Purpose IO

42 PA[3] GPIO General Purpose IO

43 PA[4] GPIO General Purpose IO

44 PA[5] GPIO General Purpose IO

45 PA[6] GPIO General Purpose IO

46 PA[7] GPIO General Purpose IO

47 PB[3] GPIO General Purpose IO

48 PB[2] GPIO General Purpose IO

Pad Default Function1 Function2 Function3 Function4 Function5 Analog Function PA[0] GPIO All functions 1a WIFI_DENY PA_KS0 UART_CTS - - PA[1] GPIO All functions 2b BLE_STATUS PA_KS1 UART1_RX IR_LEARN - PA[2] GPIO All functions 1 BLE_ACTIVITY PA_KS2 UART1_TX IR_LEARN - PA[3] SWS GPIO - - - - - PA[4] GPIO All functions 2 WIFI_DENY PA_KS4 - SWM - PA[5] GPIO All functions 1 BLE_STATUS PA_KS5 - mic_dat - PA[6] GPIO All functions 2 BLE_ACTIVITY PA_KS6 - mic_clk - No. Pin Name Type Description

Datasheet for Telink TC321x DS-TC321x-E7 32 Ver 0.8.1 PA[7] GPIO All functions 1 WIFI_DENY PA_KS7 UART_RX - - PB[0] GPIO All functions 3c BLE_STATUS PB_KS0 SPI_CN IR_LEARN sdadc_aio<0> PB[1] GPIO - - PB_KS1 SPI_CK - sdadc_aio<1> PB[2] GPIO All functions 1 BLE_ACTIVITY PB_KS2 - - sdadc_aio<2> PB[3] GPIO - - PB_KS3 UART2_RTX - sdadc_aio<3> PB[4] GPIO All functions 1 BLE_STATUS PB_KS4 - mic_dat sdadc_aio<4> PB[5] GPIO All functions 2 BLE_ACTIVITY PB_KS5 - mic_clk sdadc_aio<5> PB[6] GPIO All functions 1 WIFI_DENY PB_KS6 - mic_dat sdadc_aio<6> PB[7] GPIO All functions 2 BLE_STATUS PB_KS7 - mic_clk sdadc_aio<7> PC[0] GPIO All functions 1 BLE_ACTIVITY PC_KS0 - mic_dat audio_inn PC[1] GPIO All functions 2 WIFI_DENY PC_KS1 - mic_clk audio_inp PC[2] GPIO All functions 1 BLE_STATUS PC_KS2 - IR_LEARN - PC[3] GPIO All functions 2 BLE_ACTIVITY PC_KS3 - mic_dat diag_hv_ana PC[4] GPIO All functions 1 WIFI_DENY PC_KS4 - mic_clk - PC[5] GPIO All functions 2 BLE_STATUS PC_KS5 - - - PC[6] GPIO All functions 1 BLE_ACTIVITY PC_KS6 - - - PC[7] GPIO All functions 2 WIFI_DENY PC_KS7 - mic_dat - PD[0] GPIO All functions 1 BLE_STATUS PD_KS0 - mic_clk sdadc_aio<8> PD[1] GPIO All functions 2 BLE_ACTIVITY PD_KS1 - - sdadc_aio<9> PD[2] GPIO All functions 1 WIFI_DENY PD_KS2 - - - PD[3] GPIO All functions 2 BLE_STATUS PD_KS3 - - - PD[4] GPIO - - PD_KS4 - IR_LEARN - PD[5] GPIO All functions 2 BLE_ACTIVITY PD_KS5 - - - PD[6] GPIO All functions 1 WIFI_DENY PD_KS6 - CLK_7816 - PD[7] GPIO All functions 2 BLE_STATUS PD_KS7 UART_RTX - - PE[0] GPIO All functions 4d BLE_ACTIVITY SPI_MOSI UART1_TX, UART2_RX mic_dat - Pad Default Function1 Function2 Function3 Function4 Function5 Analog Function

Datasheet for Telink TC321x DS-TC321x-E7 33 Ver 0.8.1 PE[1] GPIO All functions 4 BLE_STATUS SPI_MISO UART2_TX mic_clk - a. “All functions 1” include 28 functions: I2S_DI, I2S_DO, I2S_LR, I2S_CK, SDM_N1, SDM_P1, SDM_N0, SDM_P0, UART1_RX, UART2_TX, SPI_CN, SPI_CK, SPI_MOSI, SPI_MISO, TX_CYC2PA, RX_CYC2LNA, I2C_SDA, I2C_SCL, UART_RX, UART_TX, UART_RTS, UART_CTS, PWM5, PWM4, PWM3, PWM2, PWM1, PWM0. b. “All functions 2” include 28 functions: I2S_DI, I2S_DO, I2S_LR, I2S_CK, SDM_N1, SDM_P1, SDM_N0, SDM_P0, UART1_TX, UART2_RX, SPI_CN, SPI_CK, SPI_MOSI, SPI_MISO, TX_CYC2PA, RX_CYC2LNA, I2C_SDA, I2C_SCL, UART_RX, UART_TX, UART_RTS, UART_CTS, PWM5_N, PWM4_N, PWM3_N, PWM2_N, PWM1_N, PWM0_N. c. “All functions 3” include 27 functions: I2S_DI, I2S_DO, I2S_LR, I2S_CK, SDM_N1, SDM_P1, SDM_N0, SDM_P0, UART1_TX, UART2_RX, UART2_TX, UART2_RTX, UART1_RTX, UART_RTX, I2C_SDA, I2C_SCL, UART_RX, UART_TX, UART_RTS, UART_CTS, PWM5_N, PWM4_N, PWM3_N, PWM2_N, PWM1_N, PWM0_N, CLK_7816. d. “All functions 4” include 11 functions: I2S_DI, I2S_DO, I2S_LR, I2S_CK, SDM_N1, SDM_P1, SDM_N0, SDM_P0, IR_LEARN, UART_RTX, CLK_7816. Pad Default Function1 Function2 Function3 Function4 Function5 Analog Function

Datasheet for Telink TC321x DS-TC321x-E7 34 Ver 0.8.1

1.6.2 Pin assignment of TC3215E

Figure 1-7 Pin Assignment of TC3215E Functions of 32 pins are described in table below. Table 1-8 Pin Function of TC3215E No. Pin Name Type Description

1 ANT Analog Pin to connect to the antenna through the matching network

2 PA[3] GPIO General Purpose IO

3 PA[6] GPIO General Purpose IO

4 PA[7] GPIO General Purpose IO

5 PB[3] GPIO General Purpose IO

6 PB[2] GPIO General Purpose IO

PD[7] PD[5] PD[4] PD[0] PD[3] PD[1] PE[1] VDD1V_DEC DCDC_SW VDD1V2 VDDF PB[4] PB[5] PB[6] IR VDDIO_AMS PC[0] PC[2] VMID PC[1] XC1 XC2 PA[6] ANT PA[7] POR PA[3] PB[0] PB[3] PB[2] PB[1] PD[2]

Datasheet for Telink TC321x DS-TC321x-E7 35 Ver 0.8.1 The multiplexed functions for GPIO pins are listed as below.

7 PB[1] GPIO General Purpose IO

8 PB[0] GPIO General Purpose IO

9 PD[7] GPIO General Purpose IO

10 PD[5] GPIO General Purpose IO

11 PD[4] GPIO General Purpose IO

12 PD[3] GPIO General Purpose IO

13 PD[2] GPIO General Purpose IO

14 PD[1] GPIO General Purpose IO

15 PD[0] GPIO General Purpose IO

16 PE[1] GPIO General Purpose IO

17 VDD1V_DEC PWR 1V digital power supply

18 DCDC_SW Analog Connected with VDCDC via external inductor

19 VDD1V2 PWR 1.2V digital power supply 20 VDDF PWR Internally generated power supply to flash. Connect to GND via external capacitor

21 PB[4] GPIO General Purpose IO

22 PB[5] GPIO General Purpose IO

23 PB[6] GPIO General Purpose IO

24 IR Analog Infrared radiation learning

25 VDDIO_AMS PWR IO voltage for AMS

26 PC[0] GPIO General Purpose IO

27 PC[1] GPIO General Purpose IO

28 PC[2] GPIO General Purpose IO

32 POR Analog Power on reset

No. Pin Name Type Description

Datasheet for Telink TC321x DS-TC321x-E7 36 Ver 0.8.1 Table 1-9 GPIO Pin Mux of TC3215E Pad Default Function1 Function2 Function3 Function4 Function5 Analog Function PA[3] SWS GPIO - - - - - PA[6] GPIO All functions 2a a. “All functions 2” include 28 functions: I2S_DI, I2S_DO, I2S_LR, I2S_CK, SDM_N1, SDM_P1, SDM_N0, SDM_P0, UART1_TX, UART2_RX, SPI_CN, SPI_CK, SPI_MOSI, SPI_MISO, TX_CYC2PA, RX_CYC2LNA, I2C_SDA, I2C_SCL, UART_RX, UART_TX, UART_RTS, UART_CTS, PWM5_N, PWM4_N, PWM3_N, PWM2_N, PWM1_N, PWM0_N. BLE_ACTIVITY PA_KS6 - mic_clk - PA[7] GPIO All functions 1b b. “All functions 1” include 28 functions: I2S_DI, I2S_DO, I2S_LR, I2S_CK, SDM_N1, SDM_P1, SDM_N0, SDM_P0, UART1_RX, UART2_TX, SPI_CN, SPI_CK, SPI_MOSI, SPI_MISO, TX_CYC2PA, RX_CYC2LNA, I2C_SDA, I2C_SCL, UART_RX, UART_TX, UART_RTS, UART_CTS, PWM5, PWM4, PWM3, PWM2, PWM1, PWM0. WIFI_DENY PA_KS7 UART_RX - - PB[0] GPIO All functions 3c BLE_STATUS PB_KS0 SPI_CN IR_LEARN sdadc_aio<0> PB[1] GPIO - - PB_KS1 SPI_CK - sdadc_aio<1> PB[2] GPIO All functions 1 BLE_ACTIVITY PB_KS2 - - sdadc_aio<2> PB[3] GPIO - - PB_KS3 UART2_RTX - sdadc_aio<3> PB[4] GPIO All functions 1 BLE_STATUS PB_KS4 - mic_dat sdadc_aio<4> PB[5] GPIO All functions 2 BLE_ACTIVITY PB_KS5 - mic_clk sdadc_aio<5> PB[6] GPIO All functions 1 WIFI_DENY PB_KS6 - mic_dat sdadc_aio<6> PC[0] GPIO All functions 1 BLE_ACTIVITY PC_KS0 - mic_dat audio_inn PC[1] GPIO All functions 2 WIFI_DENY PC_KS1 - mic_clk audio_inp PC[2] GPIO All functions 1 BLE_STATUS PC_KS2 - IR_LEARN - PD[0] GPIO All functions 1 BLE_STATUS PD_KS0 - mic_clk sdadc_aio<8> PD[1] GPIO All functions 2 BLE_ACTIVITY PD_KS1 - - sdadc_aio<9> PD[2] GPIO All functions 1 WIFI_DENY PD_KS2 - - - PD[3] GPIO All functions 2 BLE_STATUS PD_KS3 - - - PD[4] GPIO - - PD_KS4 - IR_LEARN - PD[5] GPIO All functions 2 BLE_ACTIVITY PD_KS5 - - - PD[7] GPIO All functions 2 BLE_STATUS PD_KS7 UART_RTX - - PE[1] GPIO All functions 4d BLE_STATUS SPI_MISO UART2_TX mic_clk -

Datasheet for Telink TC321x DS-TC321x-E7 37 Ver 0.8.1

1.6.3 Pin assignment of TC3215F

Figure 1-8 Pin Assignment of TC3215F Functions of 32 pins are described in table below. Table 1-10 Pin Function of TC3215F c. “All functions 3” include 27 functions: I2S_DI, I2S_DO, I2S_LR, I2S_CK, SDM_N1, SDM_P1, SDM_N0, SDM_P0, UART1_TX, UART2_RX, UART2_TX, UART2_RTX, UART1_RTX, UART_RTX, I2C_SDA, I2C_SCL, UART_RX, UART_TX, UART_RTS, UART_CTS, PWM5_N, PWM4_N, PWM3_N, PWM2_N, PWM1_N, PWM0_N, CLK_7816. d. “All functions 4” include 11 functions: I2S_DI, I2S_DO, I2S_LR, I2S_CK, SDM_N1, SDM_P1, SDM_N0, SDM_P0, IR_LEARN, UART_RTX, CLK_7816. No. Pin Name Type Description

1 PD[7] GPIO General Purpose IO

2 PD[5] GPIO General Purpose IO

PD[7] PD[5] PD[4] PD[0] PD[3] PD[1] PE[1] VDD1V_DEC DCDC_SW VDD1V2 VDDF PB[4] PB[5] PB[6] IR VDDIO_AMS PC[0] PC[2] VMID PC[1] XC1 XC2 PA[6] ANT PA[7] PC[5] PA[3] PB[0] PB[3] PB[2] PB[1] PD[2]

Datasheet for Telink TC321x DS-TC321x-E7 38 Ver 0.8.1

3 PD[4] GPIO General Purpose IO

4 PD[3] GPIO General Purpose IO

5 PD[2] GPIO General Purpose IO

6 PD[1] GPIO General Purpose IO

7 PD[0] GPIO General Purpose IO

8 PE[1] GPIO General Purpose IO

9 VDD1V_DEC PWR 1V digital power supply

10 DCDC_SW Analog Connected with VDCDC via external inductor

11 VDD1V2 PWR 1.2V digital power supply 12 VDDF PWR Internally generated power supply to flash. Connect to GND via external capacitor

13 PB[4] GPIO General Purpose IO

14 PB[5] GPIO General Purpose IO

15 PB[6] GPIO General Purpose IO

16 IR Analog Infrared radiation learning

17 VDDIO_AMS PWR IO voltage for AMS

18 PC[0] GPIO General Purpose IO

19 PC[1] GPIO General Purpose IO

20 PC[2] GPIO General Purpose IO

21 VMID Analog Audio pin connecting to external decap

22 XC2 Analog Crystal oscillator pin 2

23 XC1 Analog Crystal oscillator pin 1

24 PC[5] GPIO General Purpose IO

25 ANT Analog Pin to connect to the antenna through the matching network

26 PA[3] GPIO General Purpose IO

27 PA[6] GPIO General Purpose IO

28 PA[7] GPIO General Purpose IO

29 PB[3] GPIO General Purpose IO

30 PB[2] GPIO General Purpose IO

No. Pin Name Type Description

Datasheet for Telink TC321x DS-TC321x-E7 39 Ver 0.8.1 The multiplexed functions for GPIO pins are listed as below. Table 1-11 GPIO Pin Mux of TC3215F

31 PB[1] GPIO General Purpose IO

32 PB[0] GPIO General Purpose IO

Pad Default Function1 Function2 Function3 Function4 Function5 Analog Function PA[3] SWS GPIO - - - - - PA[6] GPIO All functions 2a BLE_ACTIVITY PA_KS6 - mic_clk - PA[7] GPIO All functions 1b WIFI_DENY PA_KS7 UART_RX - - PB[0] GPIO All functions 3c BLE_STATUS PB_KS0 SPI_CN IR_LEARN sdadc_aio<0> PB[1] GPIO - - PB_KS1 SPI_CK - sdadc_aio<1> PB[2] GPIO All functions 1 BLE_ACTIVITY PB_KS2 - - sdadc_aio<2> PB[3] GPIO - - PB_KS3 UART2_RTX - sdadc_aio<3> PB[4] GPIO All functions 1 BLE_STATUS PB_KS4 - mic_dat sdadc_aio<4> PB[5] GPIO All functions 2 BLE_ACTIVITY PB_KS5 - mic_clk sdadc_aio<5> PB[6] GPIO All functions 1 WIFI_DENY PB_KS6 - mic_dat sdadc_aio<6> PC[0] GPIO All functions 1 BLE_ACTIVITY PC_KS0 - mic_dat audio_inn PC[1] GPIO All functions 2 WIFI_DENY PC_KS1 - mic_clk audio_inp PC[2] GPIO All functions 1 BLE_STATUS PC_KS2 - IR_LEARN - PC[5] GPIO All functions 2 BLE_STATUS PC_KS5 - - - PD[0] GPIO All functions 1 BLE_STATUS PD_KS0 - mic_clk sdadc_aio<8> PD[1] GPIO All functions 2 BLE_ACTIVITY PD_KS1 - - sdadc_aio<9> PD[2] GPIO All functions 1 WIFI_DENY PD_KS2 - - - PD[3] GPIO All functions 2 BLE_STATUS PD_KS3 - - - PD[4] GPIO - - PD_KS4 - IR_LEARN - PD[5] GPIO All functions 2 BLE_ACTIVITY PD_KS5 - - - PD[7] GPIO All functions 2 BLE_STATUS PD_KS7 UART_RTX - - PE[1] GPIO All functions 4d BLE_STATUS SPI_MISO UART2_TX mic_clk - No. Pin Name Type Description

Datasheet for Telink TC321x DS-TC321x-E7 40 Ver 0.8.1

1.6.4 Pin assignment of TC3215M

Figure 1-9 Pin Assignment of TC3215M Functions of 16 pins are described in table below. Table 1-12 Pin Function of TC3215M a. “All functions 2” include 28 functions: I2S_DI, I2S_DO, I2S_LR, I2S_CK, SDM_N1, SDM_P1, SDM_N0, SDM_P0, UART1_TX, UART2_RX, SPI_CN, SPI_CK, SPI_MOSI, SPI_MISO, TX_CYC2PA, RX_CYC2LNA, I2C_SDA, I2C_SCL, UART_RX, UART_TX, UART_RTS, UART_CTS, PWM5_N, PWM4_N, PWM3_N, PWM2_N, PWM1_N, PWM0_N. b. “All functions 1” include 28 functions: I2S_DI, I2S_DO, I2S_LR, I2S_CK, SDM_N1, SDM_P1, SDM_N0, SDM_P0, UART1_RX, UART2_TX, SPI_CN, SPI_CK, SPI_MOSI, SPI_MISO, TX_CYC2PA, RX_CYC2LNA, I2C_SDA, I2C_SCL, UART_RX, UART_TX, UART_RTS, UART_CTS, PWM5, PWM4, PWM3, PWM2, PWM1, PWM0. c. “All functions 3” include 27 functions: I2S_DI, I2S_DO, I2S_LR, I2S_CK, SDM_N1, SDM_P1, SDM_N0, SDM_P0, UART1_TX, UART2_RX, UART2_TX, UART2_RTX, UART1_RTX, UART_RTX, I2C_SDA, I2C_SCL, UART_RX, UART_TX, UART_RTS, UART_CTS, PWM5_N, PWM4_N, PWM3_N, PWM2_N, PWM1_N, PWM0_N, CLK_7816. d. “All functions 4” include 11 functions: I2S_DI, I2S_DO, I2S_LR, I2S_CK, SDM_N1, SDM_P1, SDM_N0, SDM_P0, IR_LEARN, UART_RTX, CLK_7816. No. Pin Name Type Description

1 PD[4] GPIO General Purpose IO

PD[7] XC1 PA[3]

8 PC[1]

PD[1] VDD1V_DEC DCDC_SW VDD1V2 VDDF VDDIO_AMS PC[0] XC2 AVSS ANT PD[4] PC[2]

Datasheet for Telink TC321x DS-TC321x-E7 41 Ver 0.8.1 The multiplexed functions for GPIO pins are listed as below. Table 1-13 GPIO Pin Mux of TC3215M

2 PD[1] GPIO General Purpose IO

3 VDD1V_DEC PWR 1V digital power supply

4 DCDC_SW Analog Connected with VDCDC via external inductor

5 VDD1V2 PWR 1.2V digital power supply 6 VDDF PWR Internally generated power supply to flash. Connect to GND via external capacitor

7 VDDIO_AMS PWR IO voltage for AMS

8 PC[0] GPIO General Purpose IO

9 PC[1] GPIO General Purpose IO

10 PC[2] GPIO General Purpose IO

11 XC2 Analog Crystal oscillator pin 2

12 XC1 Analog Crystal oscillator pin 1

13 AVSS GND Analog ground

14 ANT Analog Pin to connect to the antenna through the matching network

15 PA[3] GPIO General Purpose IO

16 PD[7] GPIO General Purpose IO

Pad Default Function1 Function2 Function3 Function4 Function5 Analog Function PA[3] SWS GPIO - - - - - PC[0] GPIO All functions 1a a. “All functions 1” include 28 functions: I2S_DI, I2S_DO, I2S_LR, I2S_CK, SDM_N1, SDM_P1, SDM_N0, SDM_P0, UART1_RX, UART2_TX, SPI_CN, SPI_CK, SPI_MOSI, SPI_MISO, TX_CYC2PA, RX_CYC2LNA, I2C_SDA, I2C_SCL, UART_RX, UART_TX, UART_RTS, UART_CTS, PWM5, PWM4, PWM3, PWM2, PWM1, PWM0. BLE_ACTIVITY PC_KS0 - mic_dat audio_inn PC[1] GPIO All functions 2b WIFI_DENY PC_KS1 - mic_clk audio_inp PC[2] GPIO All functions 1 BLE_STATUS PC_KS2 - IR_LEARN - PD[1] GPIO All functions 2 BLE_ACTIVITY PD_KS1 - - sdadc_aio<9> PD[4] GPIO - - PD_KS4 - IR_LEARN - PD[7] GPIO All functions 2 BLE_STATUS PD_KS7 UART_RTX - - No. Pin Name Type Description

Datasheet for Telink TC321x DS-TC321x-E7 42 Ver 0.8.1 Descriptions of each signal are listed in the following tables. Table 1-14 PWM Signal Description Table 1-15 I2C Signal Description Table 1-16 I2S Signal Description b. “All functions 2” include 28 functions: I2S_DI, I2S_DO, I2S_LR, I2S_CK, SDM_N1, SDM_P1, SDM_N0, SDM_P0, UART1_TX, UART2_RX, SPI_CN, SPI_CK, SPI_MOSI, SPI_MISO, TX_CYC2PA, RX_CYC2LNA, I2C_SDA, I2C_SCL, UART_RX, UART_TX, UART_RTS, UART_CTS, PWM5_N, PWM4_N, PWM3_N, PWM2_N, PWM1_N, PWM0_N. Signal Type Description PWM0 DO PWM channel 0 output PWM0_N DO PWM channel 0 inversion output PWM1 DO PWM channel 1 output PWM1_N DO PWM channel 1 inversion output PWM2 DO PWM channel 2 output PWM2_N DO PWM channel 2 inversion output PWM3 DO PWM channel 3 output PWM3_N DO PWM channel 3 inversion output PWM4 DO PWM channel 4 output PWM4_N DO PWM channel 4 inversion output PWM5 DO PWM channel 5 output PWM5_N DO PWM channel 5 inversion output Signal Type Description I2C_SCL DIO I2C SCL I2C_SDA DIO I2C SDA Signal Type Description I2S_DI DI I2S digital input I2S_DO DO I2S digital output I2S_LR DIO I2S left and right channel SEL I2S_CK DIO I2S CLK NOTE: Insufficient pins leads to lack of corresponding function including I2C, I2S, UART, DMIC, and PTA.

Datasheet for Telink TC321x DS-TC321x-E7 43 Ver 0.8.1 Table 1-17 UART Signal Description Table 1-18 Audio Output Signal Description Table 1-19 SPI Signal Description Table 1-20 7816 Signal Description Table 1-21 MIC Signal Description Signal Type Description UART_CTS DI UART Clear to Send signal UART_RTS DO UART Ready to Send signal UART_RTX DIO UART RTX UART_RX DI UART RX UART_TX DO UART TX Signal Type Description SDM_N DO SDM diff output SDM_P DO SDM diff output Signal Type Description SPI_CN DIO SPI CN SPI_CK DIO SPI CLK SPI_MOSI DIO SPI MOSI SPI_MISO DIO SPI MISO Signal Type Description CLK_7816 DO 7816 CLK Signal Type Description MIC_CLK DO MIC CLK MIC_DAT DI MIC DATA IN

Datasheet for Telink TC321x DS-TC321x-E7 44 Ver 0.8.1 Table 1-22 Swire Signal Description Table 1-23 External Power Amplifier, Low Noise Amplifier Signal Description Table 1-24 PTA Signal Description Table 1-25 SD ADC Signal Description Signal Type Description SWM DIO Swire Master SWS DIO Swire Slave Signal Type Description RX_CYC2LNA DO External low noise amplifier TX_CYC2PA DO External power amplifier Signal Type Description BLE_ACTIVITY DIO Bluetooth LE activity BLE_STATUS DIO Bluetooth LE status WIFI_DENY DI WIFI deny Signal Type Description sdadc_aio<0> AIO SD ADC channel 0 sdadc_aio<1> AIO SD ADC channel 1 sdadc_aio<2> AIO SD ADC channel 2 sdadc_aio<3> AIO SD ADC channel 3 sdadc_aio<4> AIO SD ADC channel 4 sdadc_aio<5> AIO SD ADC channel 5 sdadc_aio<6> AIO SD ADC channel 6 sdadc_aio<7> AIO SD ADC channel 7 sdadc_aio<8> AIO SD ADC channel 8 sdadc_aio<9> AIO SD ADC channel 9

Datasheet for Telink TC321x DS-TC321x-E7 45 Ver 0.8.1 NOTE:

• DI: Digital input
• DO: Digital output
• DIO: Digital input/output
• AI: Analog input
• AO: Analog output
• AIO: Analog input/output

Datasheet for Telink TC321x DS-TC321x-E7 46 Ver 0.8.1

2 Electrical Specifications

2.1 Absolute Maximum Rating

Table 2-1 Absolute Maximum Rating

2.2 Recommended Operating Conditions

Table 2-2 Recommend Operating Conditions

2.3 DC Characteristics

Unless otherwise stated, the general test condition is: T = 25°C. Characteristics Sym. Min. Max. Unit Test Condition Battery Power Supply VDD -0.3 3.6 V - Voltage on input pin Vin -0.3 VDD+0.3 V - Output voltage Vout 0 VDD V - Storage temperature range TStr -65 150 °C - Soldering temperature TSld - 260 °C - Item Sym. Min. Typ. Max. Unit Condition Battery Power Supply VDD 1.7 3.3 3.6 V - Supply rise time (from 1.6 V to 1.8 V) TR - - 10 ms - Operating temperature range TOpr -40 - 85 °C - NOTE: The electrical characteristics currently listed in this section are target specifications and only provided for reference. Some data may be updated according to actual test results. NOTE: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Datasheet for Telink TC321x DS-TC321x-E7 47 Ver 0.8.1 Table 2-3 RX/TX Current and Sleep Current Table 2-4 Digital Inputs/Outputs (VDD = 3.3 V, T = 25 °C) Item Sym. Min. Typ. Max. Unit Condition RX Current IRx - 4.1 - mA Whole chip, 3.3 V DCDC, BLE mode - 9.4 - mA Whole chip, LDO mode TX Current ITx - 4.6 - mA Whole chip @ 0 dBm with 3.3 V DCDC, BLE mode - 11.1 - mA Whole chip @ 0 dBm LDO mode Deep sleep with 32 KB SRAM retention IDeep1 - 1.5 - µA Without 32K RCa a. Without 32K RC: The wakeup source is external signal from GPIO input, the internal 32K RC is disabled. Deep sleep with 64 KB SRAM retention - 1.8 - µA Deep sleep without SRAM retention IDeep2 - 0.5 - µA Deep sleep with 32 KB SRAM retention IDeep3 - 1.8 - µA With 32K RCb b. With 32K RC: The wakeup source is 32K RC, it is enabled. Deep sleep with 64 KB SRAM retention - 2.1 - µA Deep sleep without SRAM retention IDeep4 - 0.9 - µA Current in shutdown mode IDown - 0.2 - µA Without 32K RC Item Sym. Min. Typ. Max. Unit Conditions Input high voltage VIH 0.7xVDD - VDD V - Input low voltage VIL VSS - 0.3xVDD V - Output high voltage VOH 0.9xVDD - VDD V - Output low voltage VOL VSS - 0.1xVDD V -

Datasheet for Telink TC321x DS-TC321x-E7 48 Ver 0.8.1

2.4 AC Characteristics

2.4.1 RF Performance

Unless otherwise stated, the general test conditions are: VDD = 3.3 V, T = 25°C. Table 2-5 RF Performance Characteristics Item Sym. Min. Typ. Max. Unit Conditions RF frequency range - 2400 - 2483.5 MHz Programmable in 1 MHz step Data rate Bluetooth LE/2.4GHz proprietary 1 Mbps, ±250 kHz deviation Bluetooth LE/2.4GHz proprietary 2 Mbps, ±500 kHz deviation 2.4GHz proprietary 250 kbps, ±62.5 kHz deviation 2.4GHz proprietary 500 kbps, ±125 kHz deviation Bluetooth LE 1 Mbps RF_RX Performance (±250 kHz Deviation) Sensitivity 1 Mbps - - -97 - dBm - Frequency offset tolerance - -200 - +200 kHz - Co-channel rejection - - 8 - dB Wanted signal at -67 dBm In-band blocking rejection (equal modulation interferenc +1/-1 MHz offset - - -4/-3 - dB Wanted signal at -67 dBm +2/-2 MHz offset - - -41/-41 - dB ≥ 3 MHz offset - - -49 - dB Image rejection - - -38 - dB Wanted signal at -67 dBm; image frequency = RF_channel - 2MHz Bluetooth LE 1 Mbps RF_TX Performance Output power, maximum setting - - 10 - dBm - Output power, minimum setting - - -24 - dBm - Programmable output power range - 34 dB -

Datasheet for Telink TC321x DS-TC321x-E7 49 Ver 0.8.1 Table 2-6 RSSI Characteristics Modulation 20 dB bandwidth - - 1.4 - MHz - Bluetooth LE 2 Mbps RF_RX Performance (±500 kHz Deviation) Sensitivity 2 Mbps - - -94 - dBm - Frequency offset tolerance - -300 - +300 kHz - Co-channel rejection - - 8 - dB Wanted signal at -67 dBm In-band blocking rejection +2/-2 MHz offset - - -4/-4 - dB Wanted signal at -67 dBm +4/-4 MHz offset - - -35/-35 - dB > 6 MHz offset - - -39 - dB Image rejection - - -25 - dB Wanted signal at -67 dBm; image frequency = RF_channel - 3 MHz Bluetooth LE 2 Mbps RF_TX Performance Output power, maximum setting - - 10 - dBm - Output power, minimum setting - - -24 - dBm - Programmable output power range 34 dB - Modulation 20 dB bandwidth - - 2.5 - MHz - Item Sym. Min. Typ. Max. Unit Conditions RSSI range - -100 - 10 dBm - Resolution - - ±1 - dB - Item Sym. Min. Typ. Max. Unit Conditions

Datasheet for Telink TC321x DS-TC321x-E7 50 Ver 0.8.1 Table 2-7 Crystal Characteristics Table 2-8 RC Oscillator Characteristics Table 2-9 ADC Characteristics Item Sym. Min. Typ. Max. Unit Conditions

24 MHz Crystal

(parallel resonant) fNOM - 24 - MHz - Frequency tolerance fTOL -20 - +20 ppm - Load capacitance CL 5 12 18 pF Programmable on chip load cap Equivalent series resistance ESR - 50 100 Ohm - Item Sym. Min. Typ. Max. Unit Conditions

24 MHz RC Oscillator

Nominal frequency fNOM - 24 - MHz - Frequency tolerance fTOL - 1 - % On chip calibration 32 kHz RC Oscillator Nominal frequency fNOM - 32 - kHz - Frequency tolerance fTOL - 0.1 - % On chip calibration Calibration time - - 3 - ms - Item Sym. Min. Typ. Max. Unit Conditions Differential nonlinearity DNL - - 1.5 LSB Integral nonlinearity INL - - 1.5 LSB Effective number of bits ENOB - 14 - bits TC3216C, TC3215C, TC3215E - 11 - bits TC3215F, TC3215M Sampling rate Fs - - 31.25 ksps TC3216C, TC3215C, TC3215E - - 15.625 ksps TC3215F, TC3215M

Datasheet for Telink TC321x DS-TC321x-E7 51 Ver 0.8.1

2.4.2 Audio Performance

2.4.2.1 Analog Input to Digital Output

Measurement conditions: Input sine wave with a frequency of 1kHz, measurement bandwidth 20Hz– Fs / 2 for Fs = 8 to 32 kHz, measurement bandwidth 20 Hz to 20 kHz for Fs = 44.1 kHz to 96 kHz, unless otherwise specified. Table 2-10 Analog Microphone / Line Input to ADC Path

2.4.3 I2S Performance

2.4.3.1 I2S Timing

Figure 2-1 I2S Timing - Master Mode Measurement conditions: VDD = 3.3 V, T = 25°C, I2S_BCK = 3.072 MHz, LRCLK = 48 kHz, unless otherwise specified. Table 2-11 I2S Timing Sequence Parameter Test conditions Min. Typ Max. Unit SNR 500mVp input of 1.02 kHz, 0dB PGA gain - 88.2 - dB THD+N normal performance - -79.4 - dB Symbol Parameter Min. Typ Max. Unit tDL I2S_LR_OUT propagation delay from BCK falling edge 3.8 - 10 ns tDDA I2S_DAT_OUT propagation delay from BCK falling edge 2.2 - 10 ns tDST I2S_DAT_IN setup time to BCK rising edge 9 - - ns tDHT I2S_DAT_IN hold time from BCK rising edge 5 - - ns I2S_BCK I2S_LR_OUT I2S_DAT_OUT I2S_DAT_IN tDST tDHT tDDA tDL

Datasheet for Telink TC321x DS-TC321x-E7 52 Ver 0.8.1

2.5 ESD Characteristics

Table 2-12 HBM/CDM Results

2.6 Storage Conditions

The SoC series is applicable to Moisture Sensitivity Level 3 (based on JEDEC Standard). 1. Calculated shelf life in sealed moisture barrier bag (MBB): 12 months at <40°C and <90% relative humidity (RH) 2. Peak package body temperature: 260°C 3. After bag is opened, devices that are subjected to reflow solder or other high temperature process must be

• Mounted within: 168 hours of factory conditions <=30°C/60% RH, or
• Stored at <10% RH 4. Devices require bake before mounting, if:
• Humidity Indicator Card reads >10% when read at 23 ± 5°C
• Both of the conditions in 3 are not met 5. If baking is required, devices may be baked for 24 hours at 125 ±5°C Note: lf device containers cannot be subjected to high temperature or shorter bake times are desired, please refer to IPC/JEDEC J-STD-033 for bake condition. Model Pin Combinations ESD Sensitivity Result V Class HBM IO vs VSS(+) +2KV Pass JESD22-A114F Class-2: 2000V - <4000V IO vs VSS(-) -2KV Pass IO vs VDD(+) +2KV Pass IO vs VDD(-) -2KV Pass IO vs IO(+) +2KV Pass IO vs IO(-) -2KV Pass VDD vs VSS(+) +2KV Pass VDD vs VSS(-) -2KV Pass VDD vs VDD(+) +2KV Pass VDD vs VDD(-) -2KV Pass CDM ALL Pin(+) +500V Pass JEDEC22-C101F Class C2 500V - <1000V ALL Pin(-) -500V Pass

Datasheet for Telink TC321x DS-TC321x-E7 53 Ver 0.8.1

3 Reference Design

3.1 Reference Schematic of TC3216C/TC3215C

The reference schematic of TC3216C/TC3215C is shown as below. Figure 3-1 Reference Schematic of TC3216C/TC3215C

3.2 BOM (Bill of Material) of TC3216C/TC3215C

The bill of material table for TC3216C/TC3215C reference design is listed as below. Table 3-1 BOM Table for TC3216C/TC3215C Reference Design Quantity Reference Value PCB Footprint Description 1 C1 1.2pF 0402 CAP CER 50V 10% C0G 2 C2,C3 1.5pF 0402 CAP CER 50V 10% C0G

3 C4,C6,C7 NC 0402 Not mount

NOTE: For the schematic design and PCB layout considerations, refer to the TC321x Series Chips Hardware Guideline for more details on the hardware system design based on TC321x series chips. LDO MODE L4=NC L4=6.8uHDC-DC MODE For AntennaFor Certification TL_XC1 TL_XC2 TL_PD7 TL_PD6 TL_PD5 TL_PD4 TL_PD3 TL_PD2 TL_PD1 TL_PD0 TL_PB1 TL_PB0 TL_PE0 TL_PE1 TL_PB7 TL_PB6 TL_PB5 TL_PB4 TL_IR TL_PC1_AUD_IN_P TL_PC0_AUD_IN_N TL_PC3 TL_PC2 TL_XC1 TL_XC2 TL_PC7 TL_PC6 TL_PC5 TL_PC4 TL_ANT TL_PA3_SWS TL_PA2 TL_PA1 TL_PA0 TL_PB3 TL_PA7 TL_PA6 TL_PA5 TL_PA4 TL_PB2 TL_PB1 TL_PB0 TL_PD7 TL_PD6 TL_PD5 TL_PD4 TL_PD3 TL_PD2 TL_PD1 TL_PD0 TL_PE0 TL_PE1 TL_IR TL_PB7 TL_PB6 TL_PB5 TL_PB4 TL_PC3 TL_PC2 TL_PC1_AUD_IN_P TL_PC0_AUD_IN_N TL_PC7 TL_PC5 TL_PC4 TL_PC6 TL_PA6 TL_PA5 TL_PA4 TL_PA2 TL_PA1 TL_PA0 TL_PB2 TL_PB3 TL_PA7 TL_PA3_SWS TL_ANT TL_VDD1VDEC TL_VDD1P25 TL_VDD1P25 TL_VDDF TL_VDDIO_AMS TL_VDDIO_AMS LEFT RIGHT 6.8uH 1 2 0402C3 1.5pF 0402C1 1.2pF 0402C6 Do Not Stuff 0402 C11 1uF 0402 0402C9 10uF 0402C13 10uF 0402 2nH 0402 C8 10nF 24MHz-12pF-+/-10ppm 3 4 0402C4 NC 0402 C5 1uF 0402C2 1.5pF 0402C7 Do Not Stuff J2 UP 0402 1.5nH TC3215C QFN48A PL_V1.2 TC3215C GND2 50 GND4 52 GND3 51 GND5 53 GND1 49 PB2 48 PB3 47 PA7 46 PA6 45 PA5 44 PA4 43 SWS/PA3 42 PA2 41 PA1 40 PA0 39 GND 38 ANT 37 PB11 PB02 PD73 PD64 PD55 PD46 PD37 PD28 PD19 NC10 PD011 PE012 PE113 DVSS14 VDD1V_DEC15 DCDC_SW16 VDD1V217 VDDF18 PB419 PB520 PB621 PB722 IR23 VDDIO_AMS24 POR 36 PC7 35 PC6 34 PC5 33 PC4 32 XC1 31 XC2 30 VMID 29 PC3 28 PC2 27 PC1 26 PC0 25 0402C10 2.2uF 0402C12 0.1uF

Datasheet for Telink TC321x DS-TC321x-E7 54 Ver 0.8.1

2 C5,C11 1uF 0402 CAP CER 16V X5R,±10%

1 C8 10nF 0402 CAP CER 16V X5R,±10%

2 C9,C13 10uF 0402 CAP CER 16V X5R,±10%

1 C10 2.2uF 0402 CAP CER 16V X5R,±10% 1 C12 0.1uF 0402 CAP CER 16V X5R,±10% 1 L1 2nH 0402 IND -- 100MHz 850mA 12.5% 0.11HMS 1 L2 1.5nH 0402 IND -- 100MHz 850mA 12.5% 0.11HMS 1 L3 0R 0402 IND -- 100MHz 850mA 12.5% 0.11HMS 1 L4 6.8uH 1008L IND CHK 1MHz 1.2A 20% DCR 0.33 MPN:DFE252012F-6R8M=P2 1 U1 TC3216C/ TC3215C QFN48 Internal 1024KB/512KB Flash, SRAM 64KB 1 Y1 24MHz-12pF- +/-10ppm 3225 XTAL SMD 3225, 24 MHz, Cl=12pF, total tol.±10ppm MPN: E3SB24E000026E Quantity Reference Value PCB Footprint Description

Datasheet for Telink TC321x DS-TC321x-E7 55 Ver 0.8.1

3.3 Reference Schematic of TC3215E

The reference schematic of TC3215E is shown as below. Figure 3-2 Reference Schematic of TC3215E

3.4 BOM (Bill of Material) of TC3215E

The bill of material table for TC3215E reference design is listed as below. Table 3-2 BOM Table for TC3215E Reference Design Quantity Reference Value PCB Footprint Description

1 C1 1pF 0402 CAP CER 50V 10% C0G

1 C2 2pF 0402 CAP CER 50V 10% C0G

1 C3 1.8pF 0402 CAP CER 50V 10% C0G

3 C4,C5,C6 NC 0402 Not mount

2 C11,C14 1uF 0402 CAP CER 16V X5R,±10%

2 C9,C13 10uF 0603 CAP CER 16V X5R,±10%

For Certification For Antenna DC-DC MODE LDO MODE L4=NC L4=6.8uH TL_ANT TL_IR TL_PB6 TL_PB5 TL_PB4 TL_XC2 TL_XC1 TL_PB0 TL_PE1 TL_PD7 TL_PD5 TL_PD4 TL_PD3 TL_PD2 TL_PD1 TL_PD0 TL_XC1 TL_XC2 TL_PC2 TL_PC1_AUD_IN_P TL_PC0_AUD_IN_N TL_PC1_AUD_IN_P TL_PC0_AUD_IN_N TL_PC2 TL_PB1 TL_PB2 TL_PB3 TL_PA7 TL_PA6 TL_PA3_SWS TL_IR TL_PB6 TL_PB5 TL_PB4 TL_PD7 TL_PD5 TL_PD4 TL_PD3 TL_PD2 TL_PD1 TL_PD0 TL_PE1 TL_ANT TL_PA3_SWS TL_PA6 TL_PA7 TL_PB3 TL_PB2 TL_PB1 TL_PB0 TL_VBAT TL_VBAT TL_VDD1VDEC TL_VDD1P25 TL_VDD1P25 TL_VDDF 0402C12 0.1uF 0402C3 1.8pF 0402 NC 0402C4 NC 0402 C141uF 0402C1 1pF 0402 2nH 0402 C8 10nF 0402C10 2.2uF 0603C13 10uF 0402 NC 0603 10uF 0402C2 2pF LEFT TC3215E QFN32A PL_V2.0 TC3215E ANT1 PA3/SWS2 PA63 PA74 PB35 PB26 PB17 PB08 PD79 PD510 PD411 PD312 PD213 PD114 PD015 PE116 IR 24 PB6 23 PB5 22 PB4 21 VDDF 20 VDD1V2 19 DCDC_SW 18 VDD1V_DEC 17 POR 32 XC1 31 XC2 30 VMID 29 PC2 28 PC1 27 PC0 26 VDDIO_AMS 25 GND 33 0402 0402 C111uF 0402 1nH 24MHz-12pF-+/-10ppm 3 4 L4 6.8uH 12 RIGHT

Datasheet for Telink TC321x DS-TC321x-E7 56 Ver 0.8.1 1 C10 2.2uF 0402 CAP CER 16V X5R,±10% 1 C12 0.1uF 0402 CAP CER 16V X5R,±10% 1 L1 1nH 0402 IND -- 100MHz 850mA 12.5% 0.11HMS 1 L2 2nH 0402 IND -- 100MHz 850mA 12.5% 0.11HMS 1 L3 0R 0402 IND -- 100MHz 850mA 12.5% 0.11HMS 1 L4 6.8uH 1008 IND CHK 1MHz 1.2A 20% DCR 0.33 MPN:DFE252012F-6R8M=P2

1 U1 TC3215E QFN32 Internal 512KB Flash, SRAM 64KB

+/-10ppm 3225 XTAL SMD 3225, 24 MHz, Cl=12pF, total tol.±10ppm MPN: E3SB24E000026E Quantity Reference Value PCB Footprint Description

Datasheet for Telink TC321x DS-TC321x-E7 57 Ver 0.8.1

3.5 Reference Schematic of TC3215F

The reference schematic of TC3215F is shown as below. Figure 3-3 Reference Schematic of TC3215F

3.6 BOM (Bill of Material) of TC3215F

The bill of material table for TC3215F reference design is listed as below. Table 3-3 BOM Table for TC3215F Reference Design Quantity Reference Value PCB Footprint Description 1 C3 1.8pF 0402 CAP CER 50V 10% C0G

1 C11 1uF 0402 CAP CER 16V X5R,±10%

For Certification For Antenna DC-DC MODE LDO MODE L4=NC L4=6.8uH TL_ANT TL_PB1 TL_PB2 TL_PB3 TL_PA7 TL_PA6 TL_IR TL_PB6 TL_PB5 TL_PB4 TL_XC2 TL_XC1 TL_PC1_AUD_IN_P TL_PC0_AUD_IN_N TL_PB0 TL_PE1 TL_PD7 TL_PD5 TL_PD4 TL_PD3 TL_PD2 TL_PD1 TL_PD0 TL_PA3_SWS TL_PC2 TL_PC5 TL_PD7 TL_PD5 TL_PD4 TL_PD3 TL_PD2 TL_PD1 TL_PD0 TL_PE1 TL_PB0 TL_PB1 TL_PB2 TL_PB3 TL_PA7 TL_PA6 TL_PA3_SWS TL_ANT TL_PC5 TL_XC1 TL_XC2 TL_PC2 TL_PC1_AUD_IN_P TL_PC0_AUD_IN_N TL_IR TL_PB6 TL_PB5 TL_PB4 TL_VBAT TL_VBAT 0402C3 1.8pF 0402 NC 0603C13 10uF 0402C4 NC 6.8uH 1 2 0402 C11 1uF 0402C1 1pF 0402 2nH 0402 NC 0603C9 10uF 0402 C8 10nF 0402C12 0.1uF 0402C2 2pF 0402C10 2.2uF LEFT 0402 0402 1nH 24MHz-12pF-+/-10ppm 3 4 RIGHT TC3215F QFN32A PL_V1.7 TC3215F ANT 25 DCDC_SW10 GND 33 IR16 PA6 27PA7 28 PB0 32 PB1 31 PB2 30 PB3 29 PB413 PB514 PB615 PC0 18PC1 19PC2 20 PD07 PD16 PD25 PD34 PD43 PD52 PD71 PE18 PC5 24 SWS/PA3 26 VDD1V211 VDD1V_DEC9 VDDF12 VDDIO_AMS 17 VMID 21 XC1 23 XC2 22 GND 34GND 35GND 36GND 37

Datasheet for Telink TC321x DS-TC321x-E7 58 Ver 0.8.1 1 C10 2.2uF 0402 CAP CER 16V X5R,±10% 1 C12 0.1uF 0402 CAP CER 16V X5R,±10% 1 L1 1nH 0402 IND -- 100MHz 850mA 12.5% 0.11HMS 1 L2 2nH 0402 IND -- 100MHz 850mA 12.5% 0.11HMS 1 L3 0R 0402 IND -- 100MHz 850mA 12.5% 0.11HMS 1 L4 6.8uH 1008 IND CHK 1MHz 1.2A 20% DCR 0.33 MPN:DFE252012F-6R8M=P2

1 U1 TC3215F QFN32 Internal 512KB Flash, SRAM 64KB

+/-10ppm 3225 XTAL SMD 3225, 24 MHz, Cl=12pF, total tol.±10ppm MPN: E3SB24E000026E Quantity Reference Value PCB Footprint Description

Datasheet for Telink TC321x DS-TC321x-E7 59 Ver 0.8.1

3.7 Reference Schematic of TC3215M

The reference schematic of TC3215M is shown as below. Figure 3-4 Reference Schematic of TC3215M

3.8 BOM (Bill of Material) of TC3215M

The bill of material table for TC3215M reference design is listed as below. Table 3-4 BOM Table for TC3215M Reference Design Quantity Reference Value PCB Footprint Description 1 C3 1.8pF 0402 CAP CER 50V 10% C0G 1 C7 2.2uF 0402 CAP CER 16V X5R,±10%

2 C8,C11 10uF 0603 CAP CER 16V X5R,±10%

LDO MODE L4=NC L4=6.8uH For AntennaFor Certification TL_VBAT TL_VDD1VDEC TL_VDD1P25 TL_VDD1P25 TL_VDDF TL_VBAT TC3215M TSSOP16B PL_V2.0 TC3215M PD41 PD12 VDD1V_DEC3 DCDC_SW4 VDD1V25 VDDF6 VDDIO_AMS7 PC08 PD7 16 PA3/SWS 15 ANT 14 AVSS 13 XC1 12 XC2 11 PC2 10 PC1 9 0402C1 1pF 0402C2 2pF 0402 NC 0402C3 1.8pF 0402 NC 0402C4 NC L4 6.8uH 1 2 24MHz-12pF-+/-10ppm 3 4 0402 C10 1uF 0402C7 2.2uF 0603C11 10uF 0402 1nH 0402 2nH 0402 0603C8 10uF 0402C9 0.1uF TL_XC2 TL_XC1 TL_PD7 TL_PD4 TL_PD1 TL_PC2 TL_PC1 TL_PC0 TL_PA3_SWS TL_ANT TL_PD4 TL_PD7 TL_PD1 TL_PA3_SWS TL_ANT TL_XC1 TL_XC2 TL_PC2 TL_PC1 TL_PC0

Datasheet for Telink TC321x DS-TC321x-E7 60 Ver 0.8.1 1 C9 0.1uF 0402 CAP CER 16V X5R,±10%

1 C10 1uF 0402 CAP CER 16V X5R,±10%

1 L1 1nH 0402 IND -- 100MHz 850mA 12.5% 0.11HMS 1 L2 2nH 0402 IND -- 100MHz 850mA 12.5% 0.11HMS 1 L3 0R 0402 IND -- 100MHz 850mA 12.5% 0.11HMS 1 L4 6.8uH 1008 IND CHK 1MHz 1.2A 20% DCR 0.33 MPN:DFE252012F-6R8M=P2

1 U1 TC3215M TSSOP16 Internal 512KB Flash, SRAM 64KB

+/-10ppm 3225 XTAL SMD 3225, 24 MHz, Cl=12pF, total tol.±10ppm MPN: E3SB24E000026E Quantity Reference Value PCB Footprint Description

Datasheet for Telink TC321x DS-TC321x-E7 61 Ver 0.8.1

4 Memory and MCU

4.1 Memory

The SoC embeds 64 KB SRAM (including up to 64 KB with retention in deep sleep) as data memory, 128-bit eFuse, and 1024 / 512 KB internal flash as program memory.

4.1.1 SRAM/Register

The SRAM/register memory map is shown as follows: Figure 4-1 Physical Memory Map Register address: 0x800000 ~ 0x84FFFF. Address for one 32 KB SRAM with retention in deep sleep: 0x840000 ~ 0x847FFF. Address for another 32 KB SRAM with retention in deep sleep: 0x848000 ~ 0x84FFFF. Both register and SRAM address can be accessed (read or write) via debugging interface (SWS/SWM, SPI/I2C interface). Register 0x83FFFF 0x800000 0x840000

32 KB SRAM

(with retention in deep sleep) 0x848000 0x847FFF (with retention in deep sleep) 0x84FFFF 0x850000

Datasheet for Telink TC321x DS-TC321x-E7 62 Ver 0.8.1 Figure 4-2 Register Space 0x00f00 LL rsvd 0x00080 UART 0x00090 IR Learn 0x000a0 SWIRE 0x000b0 rsvd 0x000b4 ALG_REG_M 0x000b8 UART1 0x000c0 QDEC 0x000d0 I2C Address Map 0x000e0 rsvd 0x00100 rsvd 0x00200 Baseband 0x00400 GPIO 0x00500 MCU 0x00600 AES 0x00700 System Timer 0x00740 PWM 0x00780 Keyscan 0x00800 UART2 0x00820 rsvd 0x00830 Audio 0x00a00 DFIFO_Audio 0x00b00 DFIFO_DC 0x00b40 Audio_CIP 0x00b80 Register (Base address: 0x800000) DMA 0x00c00 System Control SPI rsvd MSPI rsvd I2C 0x00000 0x00008 0x0000c 0x00010 0x00020 0x00040FPU 0x01000 AURA 0x01200

Datasheet for Telink TC321x DS-TC321x-E7 63 Ver 0.8.1

4.1.2 Flash

For TC321x, the internal Flash mainly supports page program, sector/block/chip erase operations, and deep power down operation. Please refer to the corresponding SDK for Flash memory operation details. Please note that the 512 KB flash area ranging from 0x7E000 to 0x7FFFF and the 1024 KB flash area ranging from 0xFE000 to 0xFFFFF are reserved for Telink internal use. MCU uses the system frequency to load instructions, and adopts flash driver to access (read/write) Flash with the speed of half of the system clock. 4.1.3 eFuse The chip embeds a 128-bit eFuse. The non-volatile eFuse is defined as below: Table 4-1 eFuse Definition

4.1.4 Unique ID

For chip identification and traceability, the flash is preloaded with 128-bit Unique ID (UID). This UID can be read via the interface in SDK.

4.2 MCU

The chip integrates a powerful 32-bit MCU developed by Telink. The digital core is based on 32-bit RISC, and the length of instructions is 16 bits; four hardware breakpoints are supported. Name Length (Bit) Length (Byte) Description ATE [127:80] 6 Reserved for Telink internal use Interface functions [79:64] 2 [79:75] Reserved for Telink internal use [74] sws_dbg_disable, SWS function disable: 1'b0: enable; 1'b1: disable. [73] Reserved for Telink internal use [72] Key_read_disable, Key read enable: 1'b0: enable; 1'b1: disable. [71:68] Reserved for Telink internal use [67] reserved [66:64] baseband function debug_key [63:32] 4 Debug key, used for re-enable the debug interface SWS reserved [31:0] 4 Reserved for Telink internal use

Datasheet for Telink TC321x DS-TC321x-E7 64 Ver 0.8.1

4.3 Working Modes

The chip supports six working modes, including Active, Idle, Suspend, Deep Sleep with SRAM retention, Deep Sleep without SRAM retention, and Shutdown.

• The Power Management (PM) module is always active in all working modes.
• For modules such as MCU, RF transceiver (Radio), and SRAM, the state depends on working mode, as shown below. Table 4-2 Working Modes Mode Active Idle Suspend Deep Sleep with SRAM Retention Deep Sleep Without SRAM Retention Shutdown MCU active stall stall off off off Radio available available stall/off off off off Audio available available stall/off off off off Wakeup time to Active mode - 0 µs 100 µs Shorter than Deep Sleep without retention, almost same as Suspend 1 ms 10 ms retention SRAMs (with retention in deep sleep) full full full full off off Wakeup on RTC (32K Timer wakeup) - - available available available off Wakeup on pin (IO wakeup) - - available available available on Wakeup on interrupt - available - - - - Wakeup on reset pin (POR) - available available available available on Current Please refer to Section 2.3

Datasheet for Telink TC321x DS-TC321x-E7 65 Ver 0.8.1 Table 4-3 Retention Analog Registers in Deep Sleep Analog registers (0x35 ~ 0x3c) as shown in the table above are retained in deep sleep mode and can be used to store program state information across deep sleep cycles.

• Analog registers 0x35 ~ 0x3c are non-volatile in deep sleep, but are cleared by watchdog reset or chip software reset. Address Type Description Default Value afe_0x35 RW buffer clean at power_on/32K_watchdog/reset pin/watchdog/reboot 11111111 afe_0x36 RW buffer clean at power_on/32K_watchdog/reset pin/watchdog/reboot 00000000 afe_0x37 RW buffer clean at power_on/32K_watchdog/reset pin/watchdog/reboot 00000000 afe_0x38 RW buffer clean at power_on/32K_watchdog/reset pin/watchdog/reboot 00000000 afe_0x39 RW buffer clean at power_on/32K_watchdog/reset pin/watchdog/reboot 00000000 afe_0x3a RW buffer clean at power_on/32K_watchdog/reset pin/watchdog/reboot 00000000 afe_0x3b RW buffer clean at power_on/32K_watchdog/reset pin/watchdog/reboot 00000000 afe_0x3c RW buffer clean at power_on/32K_watchdog/reset pin/watchdog/reboot 11111111 NOTE:
• "active": MCU is at working state.
• "stall": In Idle and Suspend mode, MCU does not work, while its clock is still running.
• "available" for Modules: It's selectable to be at working state, or stall/be powered down if it does not need to work.
• "available"/"on" for wakeup: Corresponding wakeup method is supported.
• "off" for wakeup: Corresponding wakeup method is not supported. º "on": The 32 KB SRAM is powered on and works normally (can be accessed) in Active, Idle and Suspend mode. º "full": Full speed. In Active, Idle and Suspend mode, the 32 KB retention SRAM is powered on and work normally (can be accessed); in Deep Sleep with SRAM retention, the retention SRAM is powered on, however, the contents of the retention SRAM can be retained and cannot be accessed. º "off": The 32 KB SRAM is powered down in two Deep Sleep modes and Shutdown mode. The retention SRAMs are powered down in Deep Sleep without SRAM retention and Shutdown mode.
• Current: º In Deep Sleep without SRAM retention, only the PM module is active, all digital and analog modules are powered down, thus the power consumption is largely decreased. º In Deep Sleep with SRAM retention, the PM module is active, all analog and digital modules except for the retention SRAM is powered down, thus the power consumption is a little higher than in Deep Sleep without SRAM retention, but much lower than in Suspend.

Datasheet for Telink TC321x DS-TC321x-E7 66 Ver 0.8.1

• After POR (Power-On-Reset), all registers are cleared to their default values, including these analog registers. User can set flag in these analog registers correspondingly, so as to check the booting source by reading the flag. For chip software reset, please refer to the following section.

4.4 Reset

The chip supports three types of reset methods, including POR (Power-On-Reset, it varies for different part number according to 1.6 Pin Layout), watchdog reset and software reset. 1. POR: After power on, the whole chip is reset, and all registers are cleared to their default values. 2. Watchdog reset: A programmable watchdog is supported to monitor the system. If watchdog reset is triggered, registers are cleared. 3. Software reset: It is also feasible to carry out software reset for the whole chip or some modules. The base address of the following reset related registers is 0x80001200. Table 4-4 Register Configuration for Software Reset

4.5 Power Management

The multiple-stage Power Management (PM) module is flexible to control power state of the whole chip or individual functional blocks such as MCU, RF Transceiver, and peripherals.

4.5.1 Power-On-Reset (POR) and Brown-Out Detect

Figure 4-3 Control Logic for Power Up/Down Address offset Name Type Description Default Value 0x13a SFT_RST RW [0] RXC_SFT_RST [1] TXC_SFT_RST [2] CAL_SFT_RST [3] TSEQ_SFT_RST [4] DBG_SFT_RST 0x00 UVLO & PL NAND Delay Counter POR Battery / LDO Power up / Power Down Analog register afe_0x3e

Datasheet for Telink TC321x DS-TC321x-E7 67 Ver 0.8.1 The whole chip power up and down is controlled by the UVLO (Ultra-low Voltage Lockout) & PL (Power Logic) module and the external POR pin via the logic shown in the above diagram. UVLO takes the external power supply as input and releases the lock only when the power supply voltage is higher than a preset threshold. The POR pin has an internal pull-up resistor; an external Cap can be connected on the POR pin to control the POR delay. After both UVLO and POR release, there is a further configurable delay before the system reset signal ("Sysrst") is released. The delay is adjusted by analog register afe_0x3e. Since the content of afe_0x3e is reset to default only after power cycle, watchdog reset, or software reset, the delay change using afe_0x3e is only applicable when the chip has not gone through these reset conditions. For example, after deep sleep wakeup, the setting in afe_0x3e takes effect. Table 4-5 Analog Register to Control Delay Counters Figure 4-4 Initial Power-Up Sequence Address Name Type Description Default Value afe_0x3e r_dly RW Wait for Boost LDO ready (base on 16KHz frequency increase counter (8ms)) 10000000 VPOR VDD Reset Vreset UVLO output TDly configurable system reset released Sysrst Initial Power up NAND output DEC1V (VDDDEC)

Datasheet for Telink TC321x DS-TC321x-E7 68 Ver 0.8.1 Figure 4-5 Power-Down Sequence Table 4-6 Characteristics of Initial Power-Up/Power-Down Sequence Symbol Parameter Min Typ Max Unit VPOR VDD voltage when VUVLO turns to high level - 1.62 - V VPdn VDD voltage when VUVLO turns to low level - 1.55 - V TDly Delay counter value Configurable via analog register afe_0x1f Power down VDD VPdn VPOR VPOR - VPdn = POR Hysteresis UVLO output TDly configurable system reset released Sysrst NAND output DEC1V (VDDDEC)

Datasheet for Telink TC321x DS-TC321x-E7 69 Ver 0.8.1

4.5.2 Working Mode Switch

In Active mode, MCU is active, all SRAMs are accessible, and other modules are selectable whether to be at working state. The chip can switch to Idle mode to stall the MCU. In this mode, all SRAMs are still accessible, modules such as RF transceiver, are still selectable whether to be at working state. The chip can be triggered to Active mode by interrupt or POR pin, and the time to switch to Active mode is negligible. To decrease power consumption to different levels, the chip can switch to power saving mode (Suspend, Deep Sleep with SRAM retention, Deep Sleep without SRAM retention, Shutdown) correspondingly. (Please refer to Table 4-2.)

• In Suspend mode, MCU stalls, all SRAMs are still accessible, the PM module is active, modules such as RF transceiver is powered down. The chip can be triggered to Active mode by 32KHz Timer, IO pin or POR pin. It takes 100 µs or so to switch from Suspend mode to Active mode.
• In Deep Sleep with SRAM retention, the PM module is active, analog and digital modules except for the 16 KB retention SRAM is powered down, while the retention SRAM can be retained and not accessible. The chip can be triggered to Active mode by 32KHz Timer, IO pin or POR pin. The time to switch to Active mode is shorter than Deep Sleep without SRAM retention and close to Suspend.
• In Deep Sleep without SRAM retention, only the PM module is active, while analog and digital modules including the retention SRAM is powered down. The chip can be triggered to Active mode by 32KHz Timer, IO pin or POR pin. The time to switch to Active mode is 1 ms or so.
• In Shutdown mode, all digital and analog modules are powered down, and only the PM module is active. The chip can be triggered to Active mode by GPIO pins and POR pin. The time to switch to Active mode is 10 ms or so. User can directly invoke corresponding library function to switch working mode of the chip. If certain module doesn't need to work, user can power down this module in order to save power.

4.5.3 LDO and DCDC

The diagram of LDO and DCDC module is shown as following.

Datasheet for Telink TC321x DS-TC321x-E7 70 Ver 0.8.1 Figure 4-6 LDO and DCDC The chip embedded an eFuse LDO to generate 3.3V for the internal eFuse, and a 1.8 V LDO to generate 1.8 V output voltage for SD ADC module and the internal flash. The embedded 1.25 V LDO/DCDC generates 1.25 V output voltage that serves as input for the internal analog LDO, digital LDO and RF LDO; the three LDOs are responsible for supplying power to the Analog, Digital and RF modules respectively; the power amplifier (PA) of RF can be either powered by RF LDO or directly from battery depending on VANT or VBAT mode, respectively

4.5.4 VBAT and VANT Power-Supply Mode

The RF PA module has two power-supply modes including VBAT mode and VANT mode.

• In VBAT mode, the RF PA module is supplied by 3.3 V voltage regulated from two AA/AAA batteries in series. The maximum output power is related to power supply voltage of RF PA, for example, the maximum output power is 10 dBm at 3.3 V power supply, and 6 dBm at 1.8 V. 3V3 1V8 Analog LDO RF LDO Flash VDD VDD1V25 VDDF Digital Analog Power logic GPIOs Digital LDO RF Transceiver eFuse PA SDADC 1.8V LDO eFuse LDO 1.25V LDO VLINE VDD1V_DEC 1V25 1.25V DCDC AVDD1V25

Datasheet for Telink TC321x DS-TC321x-E7 71 Ver 0.8.1

• In VANT mode, the RF PA module is supplied with 1.4 V voltage by the embedded LDO. In this mode, the output power won’t change with AVDD which is converted from VBAT voltage, and the power stays constantly around 4 dBm. Comparing to the VBAT mode, the VANT mode is more power-saving at the same TX power. When the chip works in VBAT mode, it can be configured to the maximum output power. However, as the VBAT/VDD supply decreases below 3.0 V, the maximum transmit power of TX is then slightly attenuated. The detailed RF transmit power level refers to the code comments in the corresponding driver SDK, in which the RF transmit power level under VBAT mode is the result tested in 3.3 V VBAT voltage.

4.6 Wakeup Sources

The figure below shows the wakeup sources of the SoC. Figure 4-7 Wakeup Sources

4.6.1 Wakeup Source - QDEC & Keyscan

This wakeup source can only wake up the system from suspend mode. For QDEC wakeup, it is mainly used in mouse applications. For Keyscan wakeup, it is detected from keys on the keyboard.

4.6.2 Wakeup Source - 32 kHz Timer

This wakeup source is able to wake up the system from suspend mode or two deep sleep modes.

4.6.3 Wakeup Source - Low Power Comparator

This wakeup source is able to wake up the system from suspend mode or two deep sleep modes. wakeup PM_TOP Suspend_core_wakeup 32kHz timer Low power comparator Wakeup_timer Wakeup_comparator Pad_wakeup QDEC wakeup Keyscan wakeup

Datasheet for Telink TC321x DS-TC321x-E7 72 Ver 0.8.1

4.6.4 Wakeup Source - IO / Pad

This wakeup source is able to wake up the system from suspend mode or two deep sleep modes. And IO wakeup supports high level or low level wakeup which is configurable via polarity control registers.

4.6.5 Register Table

Table 4-7 Analog Register for Wakeup Address Type Description Default Value afe_0x3f R/W PA_polarity wakeup polarity 0: high level wakeup, 1: low level wakeup 0x0 afe_0x40 R/W PB_polarity wakeup polarity 0: high level wakeup, 1: low level wakeup 0x0 afe_0x41 R/W PC_polarity wakeup polarity 0: high level wakeup, 1: low level wakeup 0x0 afe_0x42 R/W PD_polarity wakeup polarity 0: high level wakeup, 1: low level wakeup 0x0 afe_0x43 R/W PE_polarity wakeup polarity 0: high level wakeup, 1: low level wakeup 0x0 afe_0x45 R/W PA wakeup enable 0x0 afe_0x46 R/W PB wakeup enable 0x0 afe_0x47 R/W PC wakeup enable 0x0 afe_0x48 R/W PD wakeup enable 0x0 afe_0x49 R/W PE wakeup enable 0x0 afe_0x4b R/W [0] pad wakeup enable [1] dig wakeup enable [2] timer wakeup enable [6:3] rsvd [7] shutdown wakeup enable 0x0 afe_0x64 R write 1 to clean the status: [0]: wkup pad [1]: rsvd [2]: wkup timer [6:3]: rsvd [7]: 32k watch dog

Datasheet for Telink TC321x DS-TC321x-E7 73 Ver 0.8.1

5 Audio

This chapter includes audio input path, CODEC, and audio output path.

5.1 Audio Input Path

There are three types of audio input path: digital microphone (DMIC), I2S and analog input channel (AMIC). Writing address 0xb11[3:2] to select I2S or microphone input to FIFO0, 0xb11[5:4] to select I2S or microphone input to FIFO1. Writing address 0xb12[7] to select DMIC or AMIC input to CODEC. Address 0xb12[6] should be set as 1'b1/1'b0 to select mono/stereo input for microphone input processing module. Figure 5-1 Audio Input Path The audio data flow direction is as follows. Table 5-1 Audio Data Flow Direction

5.1.1 AMIC Input

Address 0xb12[7] writing 1'b0 to select AMIC as input. Address 0xb11[7:6] serves to enable the right/left channel data of MIC, and it can be set as 2'b11.

5.1.2 DMIC Input

Address 0xb12[7] should be set as 1'b1 to select DMIC as audio input. Data Path Target SRAM FIFO0 FIFO1 DMIC CODEC √ √ AMIC √ √ I2S √ √ CODEC DMIC FIFO I2S SRAM Audio output path Audio ADC AMIC

Datasheet for Telink TC321x DS-TC321x-E7 74 Ver 0.8.1 Address 0xb11[7:6] serves to enable the right/left channel data of MIC, and it can be set as 2'b11. Generally, address 0xb12 bit[7] is set as 1'b1 and 0xb12bit[7:6] is set as 2b'11 to enable DMIC stereo input. After data sampling of DMIC interface, sign extension and audio input processing, the signal can be written into FIFO.

5.1.3 I2S Input

Address 0xb11[3:2] should be set as 2b'01 to select I2S as audio input to FIFO0. Address 0xb11[5:4] should be set as 2'b01 to select I2S as audio input to FIFO1. Digital I2S audio interface supports Master mode only, 16-bit data width, and variable sampling rate: 8K/16K/ 22.05K/24K/32K/44.1K/48K. The sampling rate is determined by I2S clock. Address 0xa00[5]/[4]/[1] should be set to "1" to enable I2S interface, I2S Recorder and I2S Player, respectively. I2S interface includes one configurable clock line, one data line and one channel selection line. Data generated via I2S Recorder is written into FIFO directly.

5.1.4 DFIFO

As shown in Table 5-1, for any type of audio input path, the data is finally written into DFIFO (DMA FIFO) 0 or Address 0xb10[0]/[1] should be set as 1'b1 to enable audio input of DFIFO 0~1. DFIFO supports auto mode and manual mode. It's highly recommended to clear address 0xb2c[0] to select auto mode. Take DFIFO0 as an example:

• Address 0xb00, 0xb01 and 0xb03 serve to set base address for DFIFO0, i.e. starting address to write/ read data into/from DFIFO0.
• Address 0xb02 serves to set depth (i.e. the maximum data number) for DFIFO0. Suppose address 0xb02 is set as 0x01, then the DFIFO0 depth is 4 words, i.e. 16 bytes.
• Current data number (difference value of write-pointer and read-pointer) in DFIFO0 can be read from address 0xb20 and 0xb21.
• User can check current DFIFO0 read pointer/write pointer location by reading address 0xb14~0xb15/ 0xb16~0xb17.
• When current data number in DFIFO0 is less than the underflow threshold set in address 0xb0c, address 0xb13 bit[0] and bit[4] are set as 1'b1 successively, and a FIFO0 low interrupt is generated if enabled via 0xb10[4].
• Address 0xb13[4] is automatically cleared when the data number in DFIFO0 is no less than the threshold; address 0xb13[0] needs to be cleared manually.
• When current data number in DFIFO0 is more than the overflow threshold set in address 0xb0d, address 0xb13 bit[1] and bit[5] are set as 1'b1 successively, and a FIFO0 high interrupt is generated if enabled via 0xb10[5].
• Address 0xb13[5] is automatically cleared when the data number in DFIFO0 is no more than the threshold; address 0xb13[1] needs to be cleared manually.

Datasheet for Telink TC321x DS-TC321x-E7 75 Ver 0.8.1

• When current data number in DFIFO1 is more than the overflow threshold set in address 0xb0e, address 0xb13 bit[2] and bit[6] are set as 1'b1 successively, and a FIFO0 high interrupt is generated if enabled via 0xb10[6].
• Address 0xb13[6] is automatically cleared when the data number in DFIFO1 is no more than the threshold; address 0xb13[2] needs to be cleared manually.

5.1.5 DFIFO Related Register

The audio DFIFO related registers are listed in the table below. The base address for the following registers is 0x800b00. Table 5-2 Audio DFIFO Related Registers Address Offset Name Type Description Reset Value 0x00 DFIFOBA0L RW r_ba0[7:0] 0x00 0x01 DFIFOBA0H RW r_ba0[15:8] 0x40 0x02 DFIFOMAX0 RW r_max0 0x7f 0x03 DFIFOAIDX0 RW [2:0] aidx0, r_aidx0 0x04 0x04 DFIFOBA1L RW r_ba1[7:0] 0x00 0x05 DFIFOBA1H RW r_ba1[15:8] 0x48 0x06 DFIFOMAX1 RW r_max1 0x7f 0x07 DFIFOAIDX1 RW [2:0] aidx1, r_aidx1 0x04 0x0c DFIFORL0 RW r_l0 0x20 0x0d DFIFORH0 RW r_h0 0x60 0x0e DFIFORN1 RW r_n1 0x20 0x10 DFIFOMODE RW r_mode [0] r_en_ain0, dmafifo 0 enable [1] r_en_ain1, dmafifo 1 enable [3] r_en_aout, dmafifo output enable [6:4] r_mask [4]: FIFO0 low interrupt enable [5]: FIFO0 high interrupt enable [6]: FIFO1 high interrupt enable 0x79

Datasheet for Telink TC321x DS-TC321x-E7 76 Ver 0.8.1

5.2 CODEC

The CODEC features include:

• Supports 1-channel ADC
• Supports 2-mono or 1-stereo DMIC 0x11 DFIFOAIN0 RW [1:0] r_dm_if, change sampling point, set 2'b01 [3:2] r_ain0_sel, 0:reserved 1:I2S 2:ADC 3:SDM [5:4] r_ain1_sel [7:6] r_en_ch, mic channel enable;[6]:mic l channel enable;[7]:mic r channel enable 0x21 0x12 DFIFOAIN1 RW [5:0] r_vol, mic vol control: 6'h00:-48db 6'h04:-42db 6'h08:- 36db 6'h0c:-30db 6'h10:-24db 6'h14:-18db 6'h18:-12db 6'h1c:-6db 6'h20:0db 6'h24:6db 6'h28:12db 6'h2c:18db 6'h30:24db 6'h34:30db 6'h38:36db 6'h3c:42db [6] r_mono [7] r_mic_sel, 0:amic 1:dmic 0x20 0x14 DFIFO_RPTR0L Volatile [7:2] rptr0l, rptr0[5:0] 0x00 0x15 DFIFO_RPTR0H Volatile [3:0] rptr0h, rptr0[9:6] 0x00 0x16 DFIFO_WPTR0L Volatile [7:2] wptr0l, wptr0[5:0] 0x00 0x17 DFIFO_WPTR0H Volatile [3:0] wptr0h, wptr0[9:6] 0x00 0x18 DFIFO_RPTR1L Volatile [7:2] rptr1l, rptr1[5:0] 0x00 0x19 DFIFO_RPTR1H Volatile [3:0] rptr1h, rptr1[9:6] 0x00 0x1a DFIFO_WPTR1L Volatile [7:2] wptr1l, wptr1[5:0] 0x00 0x1b DFIFO_WPTR1H Volatile [3:0] wptr1h, wptr1[9:6] 0x00 0x20 DFIFO_N0L R [7:2] n0l, n0[5:0] 0x00 0x21 DFIFO_N0H R [3:0] noh, n0[9:6] 0x24 DFIFO_N1L R [7:2] n1l, n1[5:0] 0x00 0x25 DFIFO_N1H R [3:0] n1h, n1[9:6] 0x00 0x2c DFIFO_MANUAL RW [0] r_f1_manual [1] r_aimc_samp_clk_neg 0x02 Address Offset Name Type Description Reset Value

Datasheet for Telink TC321x DS-TC321x-E7 77 Ver 0.8.1

• MCLK=24MHz

5.2.1 CODEC Input Path

The CODEC input path is illustrated in figure below. Figure 5-2 CODEC Input Path The CODEC input consists of one group of stream (dec), and includes two data paths. The stream is utilized for dual AMIC input. To enable the AMIC input, the dec_en_ch (AUDIO_DFIFO_BASE+0x11[7:6]) should be set to 1 to enable the MIC interface module switch, and the mic_sel (AUDIO_DFIFO_BASE+0x12[7]) should be configured as 0 to select the input source as AMIC. The CODEC supports two DMIC inputs, configure mic_sel to The PGAVOL_IN is controlled via Ana_0x8d[7:4] with a range of 0 ~ 45.2db. Table 5-3 PGA Gain for Different Configurations Code (4 bits) PGA Gain (dB) 0000 45.2 0001 43.5 0010 42.1 0011 40.5 0100 39.1 0101 37.4 0110 36.0 0111 34.6 1000 33.0 1001 30.1 1010 27.0

Datasheet for Telink TC321x DS-TC321x-E7 78 Ver 0.8.1

5.2.2 Decimation Data Path

The following figure shows the data path of the CODEC decimation of this chip. The sampling filter consists of a Cascaded Integrator-Comb (CIC) filter, two half-band filters, a compensation filter, and a High Pass Filter (HPF). The HPF serves the purpose of filtering out any DC bias generated by the input source. The switch is hpf_en(AUDIO_CODEC_BASE+0x00[0]). There are two formats for decimation output, one is 20-bit, the other is 16-bit, Set dec_ain0_mode(AUDIO_DFIFO_BASE+0x3b[0]), dec_ain1_mode(AUDIO_DFIFO_BASE+0x3b[2]) or dec_ain2_mode(AUDIO_DFIFO_BASE+0x3b[4]) to 0 to make output as 16-bit format. Figure 5-3 Audio CODEC Decimation The DIG_GAIN is a gain range of -48dB ~ +42dB, 6dB/step while controlling the digital gain of the left and right channels. The digital gain of the left and right channels of the dec is controlled by configuring dec_vol (AUDIO_DFIFO_BASE+0x12[5:0]). Table 5-4 Digital Gain for Different Configurations 1011 24.0 1100 21.0 1101 15.0 1110 9.0 1111 0 Gain Coded -48dB 0x00 -42dB 0x04 -36dB 0x08 -30dB 0x0c -24dB 0x10 -18dB 0x14 Code (4 bits) PGA Gain (dB)

Datasheet for Telink TC321x DS-TC321x-E7 79 Ver 0.8.1

5.2.3 ALC

The Automatic Level control (ALC) path is shown below and consists of a down-sampling filter, ALC & Noise Gate (NG), and adjustable gain. Figure 5-4 Audio ALC Path The structure of Average filter is shown below and is used to detect the envelope value of the input data. The parameter α=2^(-K1), K1 (AUDIO_CODEC_BASE+0x05[7:4]) can be adjusted to regulate the speed of detecting the following envelope. Figure 5-5 Structure of Average Filter The ALC_SEL (AUDIO_CODEC_BASE+0x21[6:5]) switch is used to enable ALC for both the left and right paths. The ALC module compares the detected envelope value with the configured reference threshold ALCL (AUDIO_CODEC_BASE+0x20[3:0]). If the envelope value exceeds the reference threshold, the gain is reduced, and vice versa. To adjust the gain increase/decrease rate, the ATK (AUDIO_CODEC_BASE+0x22[3:0]) and DCY (AUDIO_CODEC_BASE+0x22[7:4]) parameters can be modified. These parameters control the rate at which the gain increases or decreases. Configure ALC_HLD (AUDIO_CODEC_BASE+0x21[3:0]) when the gain needs -16dB 0x15 -12dB 0x18 -6dB 0x1c 0dB 0x20 +6dB 0x24 +12dB 0x28 +18dB 0x2c +24dB 0x30 +30dB 0x34 +36dB 0x38 +42dB 0x3c Gain Coded

Datasheet for Telink TC321x DS-TC321x-E7 80 Ver 0.8.1 to be reduced to make the gain have a hysteresis time in reducing. For dynamic adjustable gain, if it exceeds the MAXGAIN (AUDIO_CODEC_BASE+0x20[7:4]) value, it is capped at the maximum gain. Similarly, if the gain falls below MINGAIN (AUDIO_CODEC_BASE+0x24[2:0]), it is capped at the minimum gain. Noise gating is used to prevent noise from entering during recording when there is no useful signal. The NGAT (AUDIO_CODEC_BASE+0x23[0]) switch controls the noise gating functionality, while the NGTH (AUDIO_CODEC_BASE+0x23[7:3]) parameter sets the noise threshold. When the detected input signal amplitude falls below the set threshold, it is considered noise. Configuring NGG (AUDIO_CODEC_BASE+0x23[2:1]) as 2'b01 activates signal soft mute in this case. Figure 5-6 Signals before and after ALC

5.2.3.1 Sample Rate of CODEC Input

The master clock mclk of CODEC is divided from pll, the mclk frequency is 24 MHz. Configure codec clk div2 (AUDIO_CODEC_BASE+0x0a[6]) to 1 to make codec master clock 12 MHz. The input path of CODEC supports sampling rate of 8 kHz ~ 48 kHz, obtained by configuring dec_clk_sr (AUDIO_CODEC_BASE+0x0a[5:1]), it supports one mode only, configure clk(AUDIO_CODEC_BASE+0x0a[0]) to 1. Dmic_clk is dec_clk/2; amic clk clock can be selected by r_ck_sel(AUDIO_CODEC_BASE+0x00[1]), configure it to 1 to be dec_clk/2 in line with dmic, configure it to 0 to be dec_clk/12. When using DMIC, configure the sample rate according to Table 5-5 below.When the sample rate is larger than 32k, configure the r_neg(AUDIO_DFIFO_BASE+0x11[5]) to 1. The sample rate of AMIC can be configured according to the two tables below, depending on the clock frequency required for the simulation. NOTE:

• Save the left channel data at DMIC rising edge, save the right channel data at DMIC falling edge.

Datasheet for Telink TC321x DS-TC321x-E7 81 Ver 0.8.1 Table 5-5 Sample Rate of CODEC Input - Part 1 Table 5-6 Sample Rate of CODEC Input - Part 2

5.2.4 CODEC Related Register

The CODEC related registers are listed in the table below. The base address for the following registers is 0x800b80. Table 5-7 CODEC Related Registers MCLK Mclk_real CODEC input sample rate Coded dec_clk dec_clk/2 dec_clk/12 24.000MHz 12.000MHz 8kHz (MCLK_real/1500) 00110, 00100 mclk/6 1MHz 0.167MHz 8.0214kHz (MCLK_real/1496) 10111, 10101 mclk/5.5 1.092MHz 0.182MHz 11.0259kHz (MCLK_real/1088) 11001 mclk/4 1.5MHz 0.25MHz 12kHz (MCLK_real/1000) 01000 mclk/4 1.5MHz 0.25MHz 16kHz (MCLK_real/750) 01010 mclk/3 2MHz 0.333MHz 22.0588kHz (MCLK_real/544) 11011 mclk/2 3MHz 0.5MHz 24kHz (MCLK_real/500) 11100 mclk/2 3MHz 0.5MHz 32kHz (MCLK_real/375) 01101 mclk/3 2MHz - 48kHz (MCLK_real/250) 11110 mclk/2 3MHz - MCLK Mclk_real CODEC input sample rate Coded dec_clk dec_clk/2 dec_clk/12 24.000MHz 12.000MHz 32kHz (Mclk_real/375) 01100 01101 mclk/6 4MHz 0.667MHz 48kHz (Mclk_real/250) 00000 00010 mclk/4 6MHz 1MHz Address Offset Name Type Description Reset Value 0X00 CODEC_R00 RW [0] hpf_en, high-pass filter enable [1] 1'b1:dmic clk;1'b0: according to r_sel_2m; [2] r_sft_zc, cic shift,1'b1:left shift:8;1'b0:left shift:9 [3] r_sel_2m, 1:2M 0:1M [4] dati_soft_mute, mic input softmute enable [5] dato_soft_mute, alc output data softmute enable 0x05

Datasheet for Telink TC321x DS-TC321x-E7 82 Ver 0.8.1 0X05 CODEC_R05 RW [3:0] reserved [7:4] k1, coef for ALC 0x5e 0x0a CODEC_R0a RW [0] clk, 1'b1: supported clk mode. [5:1] clk_sr, sample rate.5'b00110:8k; 5'b10111:8.0214k; 5'b11001:11.0259; 5'b01000:12k; 5'b01010:16k; 5'b11011:22.0588; 5'b11100:24k; 5'b01100:32k; 5'b01101:32k@2MHz;5'b10001:44.118; 5'b00000:48k;5'b11110:48k@3MHz;5'b11111:44.118k@3MHz. [6] clk_div2, clk div2 enable [7] clk_en, clk enable 0x00 0x0b CODEC_R0b RW [0] en_dec, codec rst disable 0x00 0x20 CODEC_R20 RW 12dBFS(default)...4'b1111:-6dBFS. [6:4] maxgain, maxgain for ALC:6db/step;3'b000:-72dB...3'b111:- 30db; 0x7b 0x21 CODEC_R21 RW [3:0] hld, hold time:x2, [6:5] alcsel, alc select.2'b00:no alc;2'b01:right only;2'b10:left only;2'b11:stereo 0x00 0x22 CODEC_R22 RW [3:0] atk, Change the rate of gain increase,X2 [7:4] dcy, Change the gain reduction rate,X2 0x32 0x23 CODEC_R23 RW [0] ngat, Noise gate enable [2:1] ngg, Noise gate type.2'b00:hold PGA gain constant;2'b01:mute output;2'b10:softmute/unmute output;2'b11:reserve [7:3] ngth, Noise gate threshold value,1.5db step;5'b00000:- 0x00 0x24 CODEC_R24 RW [2:0] mingain, mingain,6db step:3'b000:-72db...3'b111:-30db [4] dmic_clk_sel, dmic clk sel. 0x02 Address Offset Name Type Description Reset Value

Datasheet for Telink TC321x DS-TC321x-E7 83 Ver 0.8.1

5.3 Audio Output Path

Audio output path mainly includes Rate Matching module, SDMDAC (Sigma-Delta Modulation DAC) and I2S Player. The audio data fetched from SRAM is processed by the Rate Matching module, then transferred to the SDM/I2S Player as the input signal. Figure 5-7 Audio Output Path

5.3.1 Rate Matching

The rate matching block performs clock rate conversion and data synchronization between two domains: the input audio data is fetched from SRAM which works in system clock domain with 24MHz/32MHz/48MHz clocks and the SDM/I2S which works between 4MHz and 8MHz. When needed, the audio data from SRAM is interpolated to the SDM/I2S input rate. If the audio sampling rate is ClkIn (e.g. 48kHz), and the working clock of SDM/I2S is aclk_i, then the interpolation ratio is given as follows: Where step_i[19:0] is configured in addresses 0xa05~0xa07. Linear interpolation or delay interpolation is used as shown below: Figure 5-8 Linear interpolation Rate Matching I2S Player SRAM SDMDACdata ClkIn

Datasheet for Telink TC321x DS-TC321x-E7 84 Ver 0.8.1 Figure 5-9 Delay interpolation

5.3.2 SDM

The SDM takes 16bits audio data from SRAM and provides 1bit modulated output. Only a simple passive filter network is needed to drive audio device directly. Dither control can be added to the SDM to avoid spurs in output data. There are three dithering options: PN sequence, PN sequence with Shaping, and DC constant; only one type of input is allowed any time. Figure 5-10 Block Diagram of SDM

5.3.3 Register Configuration

Address 0xa00[4:1] should be set to "1" to enable I2S recorder/ISO player/SDM player/I2S player, while bit[0] is to select either mono or stereo audio output. Address 0xa00[7] should be set to "1" to enable the HPF in audio output path. Register VOL_CTRL (address 0xa02) serves to adjust volume level. Address 0xa03[2] serves to select either linear interpolation or delay interpolation for the rate matching block: Setting bit[2] to "1" is to select linear interpolation, while clearing the bit is to select delay interpolation. Input for SDM Dither control is selectable via addresses 0xa0b[6:5], 0xa03[6:5] and 0xa08~0xa09. For the left channel: (1) Address 0xa0b[5] should be set to 1'b1 to select constant DC input. When DC input is used, addresses 0xa0c~0xa0d serve to configure the input constant value. (2) Address 0xa0b[5] should be set to 1'b0 to use PN generator. Address 0xa03[5] serves to enable/mask dither shapping module. There are two PN generators to generate random dithering sequence; address 0xa08 bit[6]/bit[5] is enabling bit of the two PN generators.

Datasheet for Telink TC321x DS-TC321x-E7 85 Ver 0.8.1

• To select PN sequence as input, address 0xa0b[5] and 0xa03[5] should be set to 0, 0xa08[6]/[5]/ [6:5] should be set to 1.
• To select PN sequence with Shapping as input, address 0xa0b[5] should be set to 0, 0xa03[5] and 0xa08[6]/[5]/[6:5] should be set to 1. When PN sequence or PN with Shapping is used, address 0xa08[4:0]/0xa09[4:0] determines the number of bits (ranging from 0 to 16) used in PN1/PN2 generator. For the right channel: (1) Address 0xa0b[6] should be set to 1'b1 to select constant DC input. When DC input is enabled, addresses 0xa0e~0xa0f serve to configure the input constant value. (2) Address 0xa0b[6] should be set to 1'b0 to use PN generator. Address 0xa03[6] serves to enable/mask dither shapping module. There are two PN generators to generate random dithering sequence; address 0xa09 bit[6]/bit[5] is enabling bit of the two PN generators.
• To select PN sequence as input, address 0xa0b[6] and 0xa03[6] should be set to 0, 0xa09[6]/[5]/ [6:5] should be set to 1.
• To select PN sequence with Shapping as input, address 0xa0b[6] should be set to 0, 0xa03[6] and 0xa09[6]/[5]/[6:5] should be set to 1. When PN sequence or PN with Shapping is used, address 0xa0a[4:0]/0xa0b[4:0] determines the number of bits (ranging from 0 to 16) used in PN1/PN2 generator. Address 0xa07, 0xa06 and 0xa05[7:4] are to set step_i[19:0] for the rate matching block, while address 0xa04 is to tune the step_i value. The step_i should be in accordance with the aclk_i provided by SDM/I2S clock.

5.3.4 Audio Output Path Related Register

The audio output path related registers are listed in the table below. The base address for the following registers is 0x800a00. Table 5-8 Audio Output Path Related Registers Address Offset Name Type Description Reset Value 0X00 AUD_EN RW [0]1: mono mode audio output, 0: stereo mode audio output [1]1: enable I2S player, 0: disable I2S player [2]1: enable SDM player, 0: disable SDM player [3]1: enable ISO player, 0: disable ISO player [4]1: enable I2S recorder, 0: disable I2s recorder [5]1: enable interface of I2S, 0: disable interface of I2S [6]1: enable GRP, 0: disable GRP [7]1: enable HPF, 0: disable HPF 0x04 0X01 GRPMID RW [7:0]: Middle of GRP 0x40

Datasheet for Telink TC321x DS-TC321x-E7 86 Ver 0.8.1 0x02 AUD_VOL RW [0]: Add a quarter [1]: Add a half [6:2]: shift left [7] 1: mute, 0: normal 0x40 0x03 AUD_CTRL RW [0]1: not multiply 2 when PWM, 0: mutiply2 [1]1: PWM, 0: not PWM [2]1: linear interpolate, 0: delay interpolate [4:3] reserved [5] 1: left Shapping used, 0: left Shapping not used [6] 1: right Shapping used, 0: right Shapping not used [7]: I2S input left/right channel swap 0x64 0x04 TUNE RW [7:0] tune step_i for rate matching block 0x01 0x05 STEP_L RW [3:0] factor to generate I2S clock [7:4] low 4 bits of rate matching block step_i[3:0] 0x90 0x06 STEP_M RW [7:0] middle byte of rate matching block step_i[11:4] 0xc4 0x07 STEP_H RW [7:0] high byte of rate matching block step_i[19:12] 0x00 0x08 AUD_PN1L RW [4:0] bits used: in pn1 of left channel, range from 0 to 16 [5] 1: pn2 of left enable, 0: pn2 of left disable [6] 1: pn1 of left enable, 0: pn1 of left disable 0x50 0x09 AUD_PN2 RW [4:0] bits used in pn2 of left channel, range from 0 to 16 [5] 1: pn2 of right enable, 0: pn2 of right disable [6] 1: pn1 of right enable, 0: pn1 of right disable 0x40 0x0a AUD_PN1R RW [4:0] bits used in pn1 of right channel, range from 0 to 16 [5] 1: exchange data in between SDMs, 0: not exchanged 0x10 0x0b CONST_SEL RW [4:0] bits used in pn2 of right channel, range from 0 to 16 [5] 1: left channel use const value, 0: left channel use pn [6] 1: right channel use const value, 0: right channel use pn 0x00 0x0c CONST_LL RW [7:0] low byte of left channel const, i.e, const_l[7:0] 0x00 0x0d CONST_LH RW [7:0] high byte of left channel const, i.e.const_l[15:8] 0x00 0x0e CONST_RL RW [7:0] low byte of right channel const, i.e const_r[7:0] 0x00 0x0f CONST_RH RW [7:0] high byte of right channel const, i.e const_r[15:8] 0x00 Address Offset Name Type Description Reset Value

Datasheet for Telink TC321x DS-TC321x-E7 87 Ver 0.8.1 6 BLE/2.4 GHz RF Transceiver

6.1 Block Diagram

The SoC integrates an advanced BLE/2.4 GHz RF transceiver. The RF transceiver works in the worldwide 2.4 GHz ISM (Industrial Scientific Medical) band. The transceiver consists of a fully integrated RF synthesizer, a power amplifier (PA), a low noise amplifier (LNA), a TX filter, a RX filter, a TX DAC, an ADC, a modulator and a demodulator. The transceiver can be configured to work in standard-compliant 1 Mbps BLE mode, 2 Mbps enhancement BLE mode and proprietary 1 Mbps, 2 Mbps, 250 kbps and 500 kbps mode. Figure 6-1 Block Diagram of RF Transceiver The internal PA can deliver a maximum 5 dBm output power, avoiding the need for an external RF PA.

6.2 Air Interface Data Rate and RF Channel Frequency

Air interface data rate, the modulated signaling rate for RF transceiver when transmitting and receiving data, is configurable via related register setting: 250 kbps, 500 kbps, 1 Mbps, 2 Mbps. The RF transceiver can operate with frequency ranging from 2.400 GHz to 2.4835 GHz. The RF channel frequency setting determines the center of the channel. ANT Interface ANT LNA RF Synthesizer PA RX Filter ADC Baseband Demodulator TX DAC TX Filter Baseband Modulator RF Transceiver

Datasheet for Telink TC321x DS-TC321x-E7 88 Ver 0.8.1

6.3 Baseband

The baseband is disabled by default. The corresponding API is available for user to power on/down the baseband and enable/disable clock, so that the baseband can be turned on/off flexibly. The baseband contains dedicated hardware logic to perform fast AGC control, access code correlation, CRC checking, data whitening, encryption/decryption and frequency hopping logic. The baseband supports all features required by Bluetooth specification.

6.3.1 Packet Format

Packet format in standard 1 Mbps BLE mode is shown in Table 6-1. Table 6-1 Packet Format in Standard 1 Mbps BLE Modea a. Packet length 80 bit ~ 2120 bit (80 ~ 2120 µs @ 1 Mbps). Packet format in standard 2 Mbps BLE mode is shown in Table 6-2. Table 6-2 Packet Format in Standard 2 Mbps BLE Mode Packet format in 2.4 GHz proprietary mode is shown in Table 6-3. Table 6-3 Packet Format in Proprietary Mode

6.3.2 RSSI and Frequency Offset

The SoC provides accurate RSSI (Receiver Signal Strength Indicator) and frequency offset indication.

• RSSI can be read from the 1 byte at the tail of each received data packet.
• If no data packet is received (e.g. to perform channel energy measurement when no desired signal is present), real-time RSSI can also be read from specific registers which is updated automatically.
• RSSI monitoring resolution can reach +/-1 dB.
• Frequency offset can be read from the 2 bytes at the tail of the data packet. Valid bits of actual frequency offset may be less than 16 bits, and different valid bits correspond to different tolerance range. LSB MSB Preamble (1 octet) Access Address (4 octets) PDU (2 ~ 257 octets) CRC (3 octets) LSB MSB Preamble (2 octets) Access Address (4 octets) PDU (2 ~ 257 octets) CRC (3 octets) LSB MSB Preamble (8 bits) Address code (configurable 3 ~ 5 bytes) Packet Controller + Payload (1 ~ 63 bytes) CRC (1 ~ 2 bytes)

Datasheet for Telink TC321x DS-TC321x-E7 89 Ver 0.8.1 Telink supplies corresponding drivers for user to read RSSI and frequency offset as needed.

Datasheet for Telink TC321x DS-TC321x-E7 90 Ver 0.8.1

7 Clock

7.1 Clock Sources

The SoC embeds a 24 MHz RC oscillator which can be used as clock source for system. External 24 MHz crystal is available via pin XC1 and XC2, which can provide a Pad_24MHz clock source for system and System Timerand generate a 48MHz clock via a frequency doubler to provide clock source for I2S and CODEC. The block diagram of the clock is shown below. Figure 7-1 Block Diagram of Clock 48M RC_24MRC Oscillator Pad_24M24 MHz Crystal Oscillator FHS MUX CLK PLL {0x70[0], 0x66[7]} System Clock MUXDivider FHS 0x66[4:0] Divider 11 32M 0x66[6:5] Sys_clk Divider Divider I2S_clk {0x67, 0x68} {0x6c, 0x6d} Divider Sys_timer_clk 16M HS divider CODEC_clk Baseband/ Modem RF PLL

Datasheet for Telink TC321x DS-TC321x-E7 91 Ver 0.8.1

7.2 System Clock

There are four selectable clock sources for MCU system clock: RC_24M derived from 24 MHz RC oscillator, High speed clock "FHS", HS divider clock (derived from "FHS" via a frequency divider), 32 MHz clock derived from 48 MHz clock via a 2/3 frequency divider (The 48MHz clock is derived from 24MHz crystal oscillator via a frequency doubler). The high speed clock (FHS) is selectable via address {0x70[0], 0x66[7]} from the following sources: 48 MHz clock (derived from 24MHz crystal oscillator via a frequency doubler), RC_24M (derived from 24 MHz RC oscillator), and Pad_24M (derived from 24MHz crystal oscillator). The digital register CLKSEL (address 0x66) serves to set system clock: System clock source is selectable via bit[6:5]. If address 0x66[6:5] is set to 2’b10 to select the HS divider clock, system clock frequency is adjustable via address 0x66[4:0]. The formula is shown as below: FSystem clock = FFHS / (system clock divider value in address 0x66[4:0])

7.3 Module Clock

7.3.1 System Timer Clock

System Timer clock is derived from 24MHz crystal oscillator via a 2/3 frequency divider. The clock frequency is fixed as 16 MHz.

7.3.2 I2S Clock

I2S clock is derived from 48MHz clock via a frequency divider. The 48MHz clock is derived from 24MHz crystal oscillator via a frequency doubler. Address offset 0x27[7] should be set as 1’b1 to enable I2S clock . I2S clock frequency dividing factor contains step and mod. Address offset 0x27[6:0] and 0x28 serve to set I2S clock step[6:0] and mod[7:0] respectively, and mod should be no less than 2*step. I2S clock frequency, FI2S clock, equals to 48MHz * I2S_step[6:0] / I2S_mod[7:0].

7.3.3 CODEC Clock

CODEC clock pin is derived from 48MHz clock via a frequency divider. Address offset 0x2c[7] serves to enable CODEC clock. CODEC clock frequency dividing factor contains step and mod. Address offset 0x2c[6:0] and 0x6d serve to set CODEC clock step[6:0] and mod[7:0], respectively, and mod should be no less than 2*step. In this situation, CODEC clock frequency, FCODEC clock = 48MHz * CODEC_step[6:0] / CODEC_mod[7:0].

7.4 Register Table

The clock related registers are listed in table below. The base address of the following registers is 0x800040. NOTE: Address 0x66[4:0] should not be set as 0 or 1.

Datasheet for Telink TC321x DS-TC321x-E7 92 Ver 0.8.1 Table 7-1 Clock Register Table Address offset Name Type Description Default Value 0x26 CLKSEL RW System clock select [4:0] sclk_div, system clock divider (must exceed 1). If 0x66[6:5] is set as 2’b10, FSysclk = FFHS / (CLKSEL[4:0]). [6:5] sclk_sel, select system clock source 2'b00: RC_24M from RC oscillator 2'b01: FHS 2'b10: HS divider (see 0x66[4:0]) 2'b11: 16MHz clock (24MHz * 2/3 divider) [7] sclk_hs_sel, FHS select 0x06 0x27 I2S_STEP RW [7] I2S clock enable [6:0] I2S step 0x00 0x28 I2S_MOD RW I2S mod I2S clock = 48MHz*I2S_step[6:0]/I2S_mod[7:0] Mod should be larger than or equal to 2*step. 0x02 0x2c CODEC_STEP RW [7] CODEC clock enable [6:0] CODEC clock step 0x01 0x2d CODEC_MOD RW [7:0] CODEC clock mod CODEC clock = 48MHz*CODEC_step[6:0]/CODEC_mod[7:0] Mod should be larger than or equal to 2*step. 0x02 0x30 CLKSEL_H RW [0] r_sclk_sel_o_h, Clock select 1: 32k, 0: 7816 clk 0x00

Datasheet for Telink TC321x DS-TC321x-E7 93 Ver 0.8.1

8 Timers

8.1 Timer0 ~ Timer2

The SoC supports three timers: Timer0 ~ Timer2. The three timers all support four modes: Mode 0 (System Clock Mode), Mode 1 (GPIO Trigger Mode), Mode 2 (GPIO Pulse Width Mode) and Mode 3 (Tick Mode), which are selectable via the register TMR_CTRL0 (address 0x800620) ~ TMR_CTRL1 (address 0x800621). Timer2 can also be configured as "watchdog" to monitor firmware running.

8.1.1 Mode 0 (System Clock Mode)

In Mode 0, system clock is employed as clock source. After Timer is enabled, Timer Tick (i.e. counting value) is increased by 1 on each positive edge of system clock from preset initial Tick value. Generally the initial Tick value is set to 0. Once current Timer Tick value matches the preset Timer Capture (i.e. timing value), an interrupt is generated, Timer stops counting and Timer status is updated. Steps of setting Timer0 for Mode 0 is taken as an example. Step 1 Set initial Tick value of Timer0 Set Initial value of Tick via registers TMR_TICK0_0 ~ TMR_TICK0_3 (address 0x800630 ~ 0x800633). Address 0x800630 is lowest byte and 0x800633 is highest byte. It’s recommended to clear initial Timer Tick value to Step 2 Set Capture value of Timer0 Set registers TMR_CAPT0_0 ~ TMR_CAPT0_3 (address 0x800624 ~ 0x800627). Address 0x800624 is lowest byte and 0x800627 is highest byte. Step 3 Set Timer0 to Mode 0 and enable Timer0 Set register TMR_CTRL0 (address 0x800620) [2:1] to 2’b00 to select Mode 0; Meanwhile set address 0x800620[0] to 1’b1 to enable Timer0. Timer0 starts counting upward, and Tick value is increased by 1 on each positive edge of system clock until it reaches Timer0 Capture value.

8.1.2 Mode 1 (GPIO Trigger Mode)

In Mode 1, GPIO is employed as clock source. The “m0”/“m1”/“m2” register specifies the GPIO which generates counting signal for Timer0/Timer1/Timer2. After Timer is enabled, Timer Tick (i.e. counting value) is increased by 1 on each positive/negative (configurable) edge of GPIO from preset initial Tick value. Generally the initial Tick value is set to 0. The “Polarity” register specifies the GPIO edge when Timer Tick counting increases. Once current Timer Tick value matches the preset Timer Capture (i.e. timing value), an interrupt is generated and timer stops counting. Steps of setting Timer1 for Mode 1 is taken as an example. Step 1 Set initial Tick value of Timer1 NOTE: Refer to Section 11.1.3 for corresponding “m0”, “m1”, “m2” and “Polarity” register address.

Datasheet for Telink TC321x DS-TC321x-E7 94 Ver 0.8.1 Set Initial value of Tick via registers TMR_TICK1_0 ~ TMR_TICK1_3 (address 0x800634 ~ 0x800637). Address 0x800634 is lowest byte and 0x800637 is highest byte. It’s recommended to clear initial Timer Tick value to Step 2 Set Capture value of Timer1 Set registers TMR_CAPT1_0 ~ TMR_CAPT1_3 (address 0x800628 ~ 0x80062b). Address 0x800628 is lowest byte and 0x80062b is highest byte. Step 3 Select GPIO source and edge for Timer1 Select certain GPIO to be the clock source via setting “m1” register. Select positive edge or negative edge of GPIO input to trigger Timer1 Tick increment via setting “Polarity” register. Step 4 Set Timer1 to Mode 1 and enable Timer1 Set address 0x800620[5:4] to 2’b01 to select Mode 1; Meanwhile set address 0x800620[3] to 1’b1 to enable Timer1. Timer1 starts counting upward, and Timer1 Tick value is increased by 1 on each positive/negative (specified during Step 3) edge of GPIO until it reaches Timer1 Capture value.

8.1.3 Mode 2 (GPIO Pulse Width Mode)

In Mode 2, system clock is employed as the unit to measure the width of GPIO pulse. The “m0”/“m1”/“m2” register specifies the GPIO which generates control signal for Timer0/Timer1/Timer2. After Timer is enabled, Timer Tick is triggered by a positive/negative (configurable) edge of GPIO pulse. Then Timer Tick (i.e. counting value) is increased by 1 on each positive edge of system clock from preset initial Tick value. Generally the initial Tick value is set to 0. The “Polarity” register specifies the GPIO edge when Timer Tick starts counting. While a negative/positive edge of GPIO pulse is detected, an interrupt is generated and timer stops counting. The GPIO pulse width could be calculated in terms of tick count and period of system clock. Steps of setting Timer2 for Mode 2 are taken as an example. Step 1 Set initial Timer2 Tick value Set Initial value of Tick via registers TMR_TICK2_0 ~ TMR_TICK2_3 (address 0x800638 ~ 0x80063b). Address 0x800638 is lowest byte and 0x80063b is highest byte. It’s recommended to clear initial Timer Tick value to Step 2 Select GPIO source and edge for Timer2 Select certain GPIO to be the clock source via setting “m2” register. Select positive edge or negative edge of GPIO input to trigger Timer2 counting start via setting “Polarity” register. Step 3 Set Timer2 to Mode 2 and enable Timer2 Set address 0x800620[7:6] to 2’b01 and address 0x800621 [0] to 1’b1. Timer2 Tick is triggered by a positive/negative (specified during Step 2) edge of GPIO pulse. Timer2 starts counting upward and Timer2 Tick value is increased by 1 on each positive edge of system clock. NOTE: Refer to Section 11.1.3 for corresponding “m0”, “m1”, “m2” and “Polarity” register address.

Datasheet for Telink TC321x DS-TC321x-E7 95 Ver 0.8.1 While a negative/positive edge of GPIO pulse is detected, an interrupt is generated and Timer2 tick stops. Step 4 Read current Timer2 Tick value to calculate GPIO pulse width Read current Timer2 Tick value from address 0x800638 ~ 0x80063b. Then GPIO pulse width is calculated as follows: GPIO pulse width = System clock period * (current Timer2 Tick - intial Timer2 Tick) For initial Timer2 Tick value is set to the recommended value of 0, then: GPIO pulse width = System clock period * current Timer2 Tick

8.1.4 Mode 3 (Tick Mode)

In Mode 3, system clock is employed. After Timer is enabled, Timer Tick starts counting upward, and Timer Tick value is increased by 1 on each positive edge of system clock. This mode could be used as time indicator. There is no interrupt generated. Timer Tick keeps rolling from 0 to 0xffffffff. When Timer tick overflows, it returns to 0 and starts counting upward again. Steps of setting Timer0 for Mode 3 is taken as an example. Step 1 Set initial Tick value of Timer0 Set Initial value of Tick via address 0x800630 ~ 0x800633. Address 0x800630 is lowest byte and address 0x800633 is highest byte. It’s recommended to clear initial Timer Tick value to 0. Step 2 Set Timer0 to Mode 3 and enable Timer0 Set address 0x800620[2:1] to 2’b11 to select Mode 3, meanwhile set address 0x800620[0] to 1’b1 to enable Timer0. Timer0 Tick starts to roll. Step 3 Read current Timer0 Tick value Current Timer0 Tick value can be read from address 0x800630 ~ 0x800633.

8.1.5 Watchdog Timer

Programmable watchdog could reset chip from unexpected hang up or malfunction. Only Timer2 supports Watchdog. Timer2 Tick has 32 bits. Watchdog Capture has only 14 bits, which consists of TMR_CTRL2 (address 0x800622) [6:0] as higher bits and TMR_CTRL1 (address 0x800621) [7:1] as lower bits. The chip is reset when the Timer2 Tick[31:18] matches Watch dog capture. Step 1 Clear Timer2 Tick value Clear registers TMR_TICK2_0 ~TMR_TICK2_3 (address 0x800638 ~ 0x80063b). Address 0x800638 is lowest byte and 0x80063b is highest byte. Step 2 Enable Timer2 Set register TMR_CTRL0 (address 0x800620) [6] to 1’b1 to enable Timer2. Step 3 Set 14-bit Watchdog Capture value and enable Watchdog

Datasheet for Telink TC321x DS-TC321x-E7 96 Ver 0.8.1 Set address 0x800622[6:0] as higher bits of watchdog capture and 0x800621[7:1] as lower bits. Meanwhile set address 0x800622[7] to 1’b1 to enable Watchdog. Then Timer2 Tick starts counting upwards from 0. If bits[31:18] of Timer2 Tick value read from address 0x800638 ~ 0x80063b reaches watchdog capture, the chip is reset, and the status bit in watchdog register is set as 1’b1 automatically. User can read the watchdog status bit after chip reset to check if the reset source is watchdog, and needs to write 1’b1 to this bit to manually clear the flag.

8.1.6 Register Table

The Timer related register are listed in table below. The base address for the following registers is 0x800600. Table 8-1 Register Configuration for Timer0 ~ Timer2 Address offset Name Type Description Default Value 0x20 TMR_CTRL0 RW [0] tmren0, Timer0 enable [2:1] tmr0m_sel, 0:tmr0m0 1:tmr0m1 2:tmr0m2 3:tmr0m3 [3] tmren1, Timer1 enable [5:4] tmr1m_sel, 0:tmr1m0 1:tmr1m1 2:tmr1m2 3:tmr1m3 [6] tmren2, Timer2 enable [7] tmr2m_sel, tmr2m0/1/2/3={r_r01[0],r_r00[7]}==2'h0/1/2/3 0x00 0x21 TMR_CTRL1 RW [0] tmr2m_sel, tmr2m0/1/2/3={r_r01[0],r_r00[7]}==2'h0/1/2/3 [7:1] wdcapt, wdcapt[6:0]=r_r01[7:1] Low bits of watch dog capture. 0x00 0x22 TMR_CTRL2 RW [6:0] wdcapt, wdcapt[13:7]=r_r02[6:0] High bits of watch dog capture. [7] wden, watchdog enable 0x00 0x23 TMR_CTRL3 W1C [0] tmr0_o=tmr0, timer0 status, write 1 to clear [1] tmr1_o=tmr1, timer1 status, write 1 to clear [2] tmr2_o=tmr2, timer2 status, write 1 to clear [3] wdstat, watch dog status, write 1 to clear (If Watchdog is enabled, need to clear it periodically to avoid triggering watchdog reset) 0x00 0x24 TMR_CAPT0_0 RW capt0[7:0], Byte 0 of timer0 capture 0x00 0x25 TMR_CAPT0_1 RW capt0[15:8], Byte 1 of timer0 capture 0x00 0x26 TMR_CAPT0_2 RW capt0[23:16], Byte 2 of timer0 capture 0x00 0x27 TMR_CAPT0_3 RW capt0[31:24], Byte 3 of timer0 capture 0x00

Datasheet for Telink TC321x DS-TC321x-E7 97 Ver 0.8.1 8.2 32K LTIMER The SoC also supports a low frequency (32 kHz) LTIMER in suspend mode or deep sleep mode. This timer can be used as one kind of wakeup source.

8.3 System Timer

The SoC also supports a System Timer. As introduced in Section 7.3.1, the clock frequency for System Timer is fixed as 16 MHz irrespective of system clock. 0x28 TMR_CAPT1_0 RW capt1[7:0], Byte 0 of timer1 capture 0x00 0x29 TMR_CAPT1_1 RW capt1[15:8], Byte 1 of timer1 capture 0x00 0x2a TMR_CAPT1_2 RW capt1[23:16], Byte 2 of timer1 capture 0x00 0x2b TMR_CAPT1_3 RW capt1[31:24], Byte 3 of timer1 capture 0x00 0x2c TMR_CAPT2_0 RW capt2[7:0], Byte 0 of timer2 capture 0x00 0x2d TMR_CAPT2_1 RW capt2[15:8], Byte 1 of timer2 capture 0x00 0x2e TMR_CAPT2_2 RW capt2[23:16], Byte 2 of timer2 capture 0x00 0x2f TMR_CAPT2_3 RW capt2[31:24], Byte 3 of timer2 capture 0x00 0x30 TMR_TICK0_0 RW ticko[7:0], Byte 0 of timer0 ticker 0x00 0x31 TMR_TICK0_1 RW ticko[15:8], Byte 1 of timer0 ticker 0x00 0x32 TMR_TICK0_2 RW ticko[23:16], Byte 2 of timer0 ticker 0x00 0x33 TMR_TICK0_3 RW ticko[31:24], Byte 3 of timer0 ticker 0x00 0x34 TMR_TICK1_0 RW tick1[7:0], Byte 0 of timer1 ticker 0x00 0x35 TMR_TICK1_1 RW tick1[15:8], Byte 1 of timer1 ticker 0x00 0x36 TMR_TICK1_2 RW tick1[23:16], Byte 2 of timer1 ticker 0x00 0x37 TMR_TICK1_3 RW tick1[31:24], Byte 3 of timer1 ticker 0x00 0x38 TMR_TICK2_0 RW tick2[7:0], Byte 0 of timer2 ticker 0x00 0x39 TMR_TICK2_1 RW tick2[15:8], Byte 1 of timer2 ticker 0x00 0x3a TMR_TICK2_2 RW tick2[23:16], Byte 2 of timer2 ticker 0x00 0x3b TMR_TICK2_3 RW tick2[31:24], Byte 3 of timer2 ticker 0x00 Address offset Name Type Description Default Value

Datasheet for Telink TC321x DS-TC321x-E7 98 Ver 0.8.1 In Suspend mode, both System Timer and Timer0 ~ Timer2 stop counting, and 32k Timer starts counting. When the chip restores to Active mode, Timer0 ~ Timer2 continue counting from the number when they stops; in contrast, System Timer continues counting from an adjusted number which is a sum of the number when it stops and an offset calculated from the counting value of 32k Timer during Suspend mode. The system timer related registers are listed in table below. The base address for the registers is 0x800740. Table 8-2 Register Table for System Timer Address offset Name Type Description Default Value 0x00 SYS_TIMER0 Volatile sys_timer_0, sys_timer[7:3]=sys_timer_sync[4:0] [7:3] Byte 0 of system timer counter, write to set initial value. This is the system timer counter. The sys_timer is running @16 MHz, The [2:0] is invalid, therefore, the resolution is 0.5 µs. 0x00 0x01 SYS_TIMER1 Volatile sys_timer1, sys_timer[15:8]=sys_timer_sync[12:5] [7:0] Byte 1 of system timer counter, write to set initial value. This is the system timer counter. 0x00 0x02 SYS_TIMER2 Volatile sys_timer2, sys_timer[23:16]=sys_timer_sync[20:13] [7:0] Byte 2 of system timer counter, write to set initial value. This is the system timer counter. 0x00 0x03 SYS_TIMER3 Volatile sys_timer3, sys_timer[31:24]=sys_timer_sync[28:21] [7:0] Byte 3 of system timer counter, write to set initial value. This is the system timer counter. 0x00 0x04 IRQ_LEVEL0 RW irq_level[7:0], Byte 0 0f system timer counter pulse irq trig value 0xf0 0x05 IRQ_LEVEL1 RW irq_level[15:8], Byte 1 0f system timer counter pulse irq trig value 0x0f 0x06 IRQ_LEVEL2 RW irq_level[23:16], Byte 2 0f system timer counter pulse irq trig value 0x0f 0x07 IRQ_LEVEL3 RW irq_level[31:24], Byte 3 0f system timer counter pulse irq trig value 0x0e 0x08 IRQ_MASK RW [2:0] irq_mask [0] cal done irq mask [1] read 32k timer done irq mask [2] level irq mask 0x00 0x09 IRQ_LIST W1C [1:0] irq_status [0] cal done irq status [1] read 32k timer done irq status 0x00

Datasheet for Telink TC321x DS-TC321x-E7 99 Ver 0.8.1 0x0a SYS_TIMER_ CTRL0 RW [7:4] 32 kHz clock calibration mode (cycles of 32k clock) [3] calibration enable [2] timer auto mode [1] enable system timer [0] write/read mode of 32 kHz timer 1'b1: write; 1'b0: read 0xc1 0x0b SYS_TIMER_ CTRL1 [6] read busy status (R) [5] read update status (W1C) [4] state machine status[1] (R) [3] W: Start 32k count write/read; R: state machine status[0] (RW) [2] cmd_set_tgl (R) [1] W: Stop 16m systimer when using auto mode; R: cmd_sync_tgl (RW) [0] W: Run 16m systimer when using auto mode; R: timer_en status (RW) 0x00 0x0c TIMER_32K0 _SYN RW [7:0]: timer_32k_s[7:0] Byte 0 of 32 kHz Timer write value 0x00 0x0d TIMER_32K1 _SYN RW [7:0] timer_32k_s[15:8] Byte 1 of 32 kHz Timer write value 0x00 0x0e TIMER_32K2 _SYN RW [7:0] timer_32k_s[23:16] Byte 2 of 32 kHz Timer write value 0x00 0x0f TIMER_32K3 _SYN RW [7:0] timer_32k_s[31:24] Byte 3 of 32 kHz Timer write value 0x00 0x10 TIMER_32K0 _LAT R [7:0] timer_32k_l[7:0] Byte 0 of 32 kHz Timer read value 0x00 0x11 TIMER_32K1 _LAT R [7:0] timer_32k_l[15:8] Byte 1 of 32 kHz Timer read value 0x00 0x12 TIMER_32K2 _LAT R [7:0] timer_32k_l[23:16] Byte 2 of 32 kHz Timer read value 0x00 0x13 TIMER_32K3 _LAT R [7:0] timer_32k_l[31:24] Byte 3 of 32 kHz Timer read value 0x00 Address offset Name Type Description Default Value

Datasheet for Telink TC321x DS-TC321x-E7 100 Ver 0.8.1 0x14 TIMER_CAL_ LAT_0 R [7:0] timer_cal_l[7:0] Byte 0 of 32 kHz clock calibration result (representing 16 MHz clock cycle number) 0x00 0x15 TIMER_CAL_ LAT_1 R [7:0] timer_cal_l[15:8] Byte 1 of 32 kHz clock calibration result (representing 16 MHz clock cycle number) 0x00 0x16 TIMER_CAL_ LAT_2 R [7:0] timer_cal_l[23:16] Byte 2 of 32 kHz clock calibration result (representing 16 MHz clock cycle number) 0x00 0x17 TIMER_CAL_ LAT_3 R [7:0] timer_cal_l[26:24] Byte 3 of 32 kHz clock calibration result (representing 16 MHz clock cycle number) 0x00 Address offset Name Type Description Default Value

Datasheet for Telink TC321x DS-TC321x-E7 101 Ver 0.8.1

9 Interrupt System

9.1 Interrupt Structure

The interrupt function is applied to manage dynamic program sequencing based on real-time events triggered by timers, pins and etc. For this SoC, there are 24 interrupt sources in all: 16 types are level-triggered interrupt sources (listed in address 0x800640 ~ 0x800641), and 8 types are edge-triggered interrupt sources (listed in address 0x800642). When CPU receives an interrupt request (IRQ) from certain interrupt source, it determines whether to respond to the IRQ. If CPU decides to respond, it pauses current routine and starts to execute interrupt service subroutine. The program jumps to certain code address and execute IRQ handling commands. After finishing interrupt service subroutine, CPU returns to the breakpoint and continues to execute main function.

9.1.1 Enable/Mask Interrupt Sources

Various interrupt sources could be enabled or masked by the registers MASK_0 ~ MASK_2 (address 0x800640 ~ 0x800642). Interrupt sources of level-triggered type:

• irq_mix (0x800640[7]): I2C Slave mapping mode or SPI Slave interrupt (irq_host_cmd)
• irq_uart (0x800640[6]): UART interrupt
• irq_dfifo (0x800640[5]): DFIFO interrupt
• irq_dma (0x800640[4]): DMA interrupt
• time2, time1, time0 (0x800640[2] ~ 0x800640[0]): Timer2 ~ Timer0 interrupt
• irq_gpio_mux (0x800641[7]): GPIO mux interrupt, please refer to Section 11.1.3
• irq_pwm (0x800641[6]): PWM interrupt
• irq_zb_rt (0x800641[5]): Baseband interrupt Interrupt sources of edge-triggered type:
• gpio2risc[2:0] (0x800642[7] ~ 0x800642[5]): gpio2risc[2] ~ gpio2risc[0] interrupt, please refer to Section 11.1.3.
• irq_stimer (0x800642[4]): System timer interrupt
• pm_irq_tm (0x800642[3]): 32 kHz timer wakeup interrupt
• irq_gpio (0x800642[2]): GPIO interrupt, please refer to Section 11.1.3

9.1.2 Interrupt Mode and Priority

Interrupt mode is typically-used mode. Register IRQMODE (address 0x800643)[0] should be set as 1’b1 to enable interrupt function. IRQ tasks could be set as High or Low priority via the registers PRIO_0 ~ PRIO_2 (address 0x800644 ~ 0x800646). When two or more interrupt sources assert interrupt requests at the same time, the CPU responds depending on respective interrupt priority levels. It’s recommended not to modify priority setting.

Datasheet for Telink TC321x DS-TC321x-E7 102 Ver 0.8.1

9.1.3 Interrupt Source Flag

Three bytes in the registers IRQSRC_0 ~ IRQSRC_2 (address 0x800648 ~ 0x80064a) serve to indicate IRQ sources. Once IRQ occurs from certain source, the corresponding IRQ source flag is set as “1”. User could identify IRQ source by reading address 0x800648 ~ 0x80064a. When handling edge-triggered type interrupt, the corresponding IRQ source flag needs to be cleared via address 0x80064a. As for level-type interrupt, IRQ interrupt source status needs to be cleared by setting corresponding module status register. Take Timer0 IRQ interrupt source for example: First enable the interrupt source by setting address 0x800640 bit[0] as 1’b1; then set address 0x800643 bit[0] as 1’b1 to enable the interrupt. In interrupt handling function, 24-bit data is read from address 0x800648~0x80064a to check which IRQ source is valid; if data bit[0] is 1, it means the Timer0 IRQ source is valid. Register TMR_STATUS (address 0x800623) [0] should be written with 1’b1 to manually clear Timer0 status (refer to Section 8.1.1).

9.2 Register Configuration

The Interrupt related register are listed in table below. The base address for the following registers is 0x800600. Table 9-1 Register Table for Interrupt System Address offset Name Type Description Default Value 0x40 MASK_0 RW Byte 0 interrupt mask, level-triggered type {irq_mix, irq_uart, irq_dfifo, irq_dma, time2, time1, time0} [7] irq_mix, i.e. irq_host_cmd [6] irq_uart [5] irq_dfifo [4] irq_dma [3] rsvd [2] time2 [1] time1 [0] time0 0x00

Datasheet for Telink TC321x DS-TC321x-E7 103 Ver 0.8.1 0x41 MASK_1 RW Byte 1 interrupt mask, level-triggered type {irq_gpio_mux, irq_pwm, irq_zb_rt, irq_udc[4:0], irq_uart1} [7] irq_gpio_mux [6] irq_pwm [5] irq_zb_rt [4] irq_udc[4] [3] irq_udc[3]|irq_uart1 [2] irq_udc[2] [1] irq_udc[1] [0] irq_udc[0] 0x00 0x42 MASK_2 RW Byte 2 interrupt mask, edge-triggered type {gpio2risc[2:0], irq_stimer, pm_irq, irq_gpio} [7] gpio2risc[2] [6] gpio2risc[1] [5] gpio2risc[0] [4] irq_stimer [3] pm_irq_tm [2] irq_gpio [1] rsvd [0] rsvd 0x00 0x43 IRQMODE RW [0] Interrupt enable [1] Reserved (Multi-address enable) 0x00 0x44 PRIO_0 RW Byte 0 of priority 1: High priority; 0: Low priority 0x00 0x45 PRIO_1 RW Byte 1 of priority 0x00 0x46 PRIO_2 RW Byte 2 of priority 0x00 0x48 IRQSAR0 Volatile Byte 0 of interrupt source 0x00 0x49 IRQSAR1 Volatile Byte 1 of interrupt source 0x00 0x4a IRQSAR2 Volatile Byte 2 of interrupt source 0x00 Address offset Name Type Description Default Value

Datasheet for Telink TC321x DS-TC321x-E7 104 Ver 0.8.1

10 DMA

10.1 Introduction

The SoC embeds DMA (Direct Memory Access) module with DMAC. DMAC is a direct memory access controller which transfers regions of data efficiently on bus. DMAC features include:

• Supports up to 8 DMA channels
• Supports up to 8 request/acknowledge pairs for hardware handshaking
• Supports pingpong transfer

10.1.1 Function Description

The DMAC supports up to 8 DMA channels. Each DMA channel provides a set of registers to describe the intended data transfers. Multiple DMA channels can be enabled concurrently, but the DMA controller services one channel at a time. The corresponding peripherals of the 8 DMA channels are fixed, the mapping relation is as below. Table 10-1 Peripherals of 8 DMA channels

10.1.2 Channel Arbitration

The DMA provides fixed priority level for channel arbitration. When more than one channel is accessed at the same time, channel 0 has the highest priority, channel 7 has the lowest priority

10.1.3 PingPong Transfer

This DMA supports PingPong transfer, when the 1st bit of DMA mode register is written 1, it means PingPong transfer is enabled, i.e., after the DMA transfer of the current buffer is completed, it automatically jumps to the next buffer to continue the transfer, and the two buffers are alternated. No. DMA channel Corresponding peripheral

1 DMA channel 0 uart_rx

2 DMA channel 1 uart_tx

3 DMA channel 2 baseband_rx

4 DMA channel 3 baseband_tx

5 DMA channel 4 aes_out

6 DMA channel 5 aes_in

7 DMA channel 6 -

8 DMA channel 7 pwm

Datasheet for Telink TC321x DS-TC321x-E7 105 Ver 0.8.1

10.1.4 Data Order

The data order here refers to the DMA access to the address of the buffer, there are two main modes: increment mode and fixed mode. The increment mode refers to the access to the address of the buffer is self- incrementing, when it reaches the set size, the access to the address of the buffer stays at the last address. The fixed mode means that the address of the access buffer is fixed, in this case, write 1 to bit 2 of the DMA mode register. The Channel4 also supports decrease mode, that is, the address of the access buffer is based on the original starting address of the original setting of the self-decrement.

10.2 DMA Usage Guide

10.2.1 From SRAM to Peripherals

From SRAM to peripherals, only transferring with srcwidth and dstwidth of word is supported. The following are the steps for DMA register configuration: (1) Configure the address DMAnL: addr[7:0] DMAnH: addr[15:8] DMAnHH: addr[18:16] (2) Configure DMA mode DMAnMODE: 0x00 (3) Configure DMA size DMAnSIZE: buffer size = DMAnSIZEx16 bytes (4) Kick dma DMAn_ready: write 1

10.2.2 From Peripherals to SRAM

From peripherals to SRAM, only transferring with srcwidth and dstwidth of word is supported. The following are the steps for DMA register configuration: (1) Configure the address DMAnL: addr[7:0] DMAnH: addr[15:8] DMAnHH: addr[18:16] (2) Configure DMA mode DMAnMODE: 0x01 (3) Configure DMA size DMAnSIZE: buffer size = DMAnSIZEx16 bytes

Datasheet for Telink TC321x DS-TC321x-E7 106 Ver 0.8.1

10.2.3 From SRAM to Baseband

The configuration method for transferring data from SRAM to baseband is the same as that from SRAM to peripheral mentioned above. However, for the previous method, after each DMA transfer, it's necessary to reconfigure the transize register, source address register, and enable control register (en). In comparison, there are some enhanced functionalities for baseband. After enabling tx_multi_en, the DMA automatically loads the source address register. TX has a total of 6 channels (0-5), it is needed to set the FIFO depth of each chn tx_chn_dep (where 0 represents one buffer, 1 represents two buffers, and 2 represents four buffers) and set the size of each buffer buf_size(bb_tx_size) bytes. The channel is fixed on the baseband side for each transfer. After enabling the tx_multi_en of DMA, DMA receives the send request from baseband and views the read/write pointer of the current channel. If the FIFO of the current channel is empty, the DMA reads data from the default buff. If the current channel's FIFO is not empty, the DMA goes to the corresponding rptr of the current channel to read the data. The write pointer of TX is maintained by software while the read pointer is maintained by hardware (incremented every time a tx_commit is received by baseband in multi-mode. In case the baseband does not use multi-mode, the software can neglect maintaining the write pointer, making all txfifos empty; then, the DMA automatically reads data from the default buffer during transmission). Hence, the multi-mode of DMA can be used even when the baseband is in non-multi mode.

10.2.4 From Baseband to SRAM

The same method used for peripheral to SRAM can also be applied to transfer data from baseband to SRAM. Similar to the previous case, after every DMA transfer, configuring destination address register, transize register, and enable control register's en becomes necessary. However, for the Rx channel of baseband, DMA has enhanced functionality. By enabling rx_multi_en, upon completing every DMA transfer, the DMA automatically loads the destination address register. The mechanism for DMA to automatically load the destination registers: Unlike TX which has 6 channels, RX has only one FIFO buffer, therefore only the RX FIFO depth rx_wptr_mask(dma_base+0x10d[4:0]) and the buffer size (bb_rx_size) in bytes need to be set. Whenever a DMA transfer is initiated, DMA reads data from baseband and writes it to the specified address in the destination address register. After completing the transfer, if the received packet is valid, the baseband generates an rx_commit signal to the DMA, which increments the rx_wptr. The next packet of data is then written into the buffer pointed to by rx_wptr. If the rxfifo's depth is zero, incoming data continues to be written to the same location.

10.3 Register Description

The DMA related registers are listed as following, the base address of the following registers is 0x800c00. Table 10-2 DMA Related Registers Address offset Name Type Description Default value 0x00 DMA0AL RW DMA channel 0, memory address low byte 0x00

Datasheet for Telink TC321x DS-TC321x-E7 107 Ver 0.8.1 0x01 DMA0AH RW DMA channel 0, memory address high byte 0x00 0x02 DMA0SIZE RW DMA channel 0, buffer size: DMA0SIZEX16 0x68 0x03 DMA0MODE RW [0]: mode_ext, 1: write to sram 0:read from sram [1]: mode_pp, pingpong buffer enable [2]: mode_fifo, FIFO mode enable [3]: mode_auto, auto mode enable [4]: mode_read, read mode enable [5]: mode_byte, byte mode enable 0x01 0x04 DMA1AL RW DMA channel 1, memory address low byte 0x80 0x05 DMA1AH RW DMA channel 1, memory address high byte 0x80 0x06 DMA1SIZE RW DMA channel 1, buffer size: DMA1SIZEX16 0x20 0x07 DMA1MODE RW [0]: mode_ext, 1: write to sram 0:read from sram [1]: mode_pp, pingpong buffer enable [2]: mode_fifo, FIFO mode enable [3]: mode_auto, auto mode enable [4]: mode_read, read mode enable [5]: mode_byte, byte mode enable 0x00 0x08 DMA2AL RW DMA channel 2, memory address low byte 0x18 0x09 DMA2AH RW DMA channel 2, memory address high byte 0x01 0x0a DMA2SIZE RW DMA channel 2, buffer size: DMA2SIZEX16 0x80 0x0b DMA2MODE RW [0]: mode_ext, 1: write to sram 0:read from sram [1]: mode_pp, pingpong buffer enable [2]: mode_fifo, FIFO mode enable [3]: mode_auto, auto mode enable [4]: mode_read, read mode enable [5]: mode_byte, byte mode enable [7:6]: rx_fifo_mode, rx_fifo_mode=!r_mode2[7:6] 0x25 0x0c DMA3AL RW DMA channel 3, memory address low byte 0x00 0x0d DMA3AH RW DMA channel 3, memory address high byte 0xa8 0x0e DMA3SIZE RW DMA channel 3, buffer size: DMA3SIZEX16 0x60 Address offset Name Type Description Default value

Datasheet for Telink TC321x DS-TC321x-E7 108 Ver 0.8.1 0x0f DMA3MODE RW [0]: mode_ext, 1: write to sram 0:read from sram [1]: mode_pp, pingpong buffer enable [2]: mode_fifo, FIFO mode enable [3]: mode_auto, auto mode enable [4]: mode_read, read mode enable [5]: mode_byte, byte mode enable [7:6]: adr_ack 0x80 0x10 DMA4AL RW DMA channel 4, memory address low byte 0x00 0x11 DMA4AH RW DMA channel 4, memory address high byte 0x00 0x12 DMA4SIZE RW DMA channel 4, buffer size: DMA4SIZEX16 0x14 0x13 DMA4MODE RW [0]: mode_ext, 1: write to sram 0:read from sram [1]: mode_pp, pingpong buffer enable [2]: mode_fifo, FIFO mode enable [3]: mode_auto, auto mode enable [4]: mode_read, read mode enable [5]: mode_byte, byte mode enable 0x01 0x14 DMA5AL RW DMA channel 5, memory address low byte 0x00 0x15 DMA5AH RW DMA channel 5, memory address high byte 0x00 0x16 DMA5SIZE RW DMA channel 5, buffer size: DMA5SIZEX16 0x14 0x17 DMA5MODE RW [0]: mode_ext, 1: write to sram 0:read from sram [1]: mode_pp, pingpong buffer enable [2]: mode_fifo, FIFO mode enable [3]: mode_auto, auto mode enable [4]: mode_read, read mode enable [5]: mode_byte, byte mode enable 0x01 0x18 DMA7AL RW DMA channel 7, memory address low byte 0x00 0x19 DMA7AH RW DMA channel 7, memory address high byte 0x00 0x1a DMA7SIZE RW DMA channel 7, buffer size: DMA7SIZEX16 0x14 Address offset Name Type Description Default value

Datasheet for Telink TC321x DS-TC321x-E7 109 Ver 0.8.1 0x1b DMA7MODE RW [0]: mode_ext, 1: write to sram 0:read from sram [1]: mode_pp, pingpong buffer enable [2]: mode_fifo, FIFO mode enable [3]: mode_auto, auto mode enable [4]: mode_read, read mode enable [5]: mode_byte, byte mode enable 0x01 0x1c DMA_ADRLT RW - 0x00 0x1d DMA_ADRHT RW - 0xa0 0x1e DMA_SIZET RW - 0x08 0x20 DMAEN RW [0]: r_en0 [1]: r_en1 [2]: r_en2 [3]: r_en3 [4]: r_en4 [5]: r_en5 [7]: r_en7 0xbf 0x21 DMAMASK RW [7:0]: dma_irq_o, dma_irq_o=|((r_kpt0|r_kpt1)&r_mask) 0xff 0x22 DMA_TX_EN RW [0]: r_tx_en_commit [1]: r_tx_en_multi [3:2]: r_tx_en_en_buffer, 0:r_tx_en_buffer1 1:r_tx_en_buffer2 2:r_tx_en_buffer4 [4]: r_rx_en_commit 0x11 0x24 DMA_READY0 RW [5:0]: dma_ready0, write1 to 1 [7]: dma_ready0_7, write1 to 1 0x00 0x25 DMA_READY1 RW [5:0]: dma_ready1, write1 to 1 [7]: dma_ready1_7, write1 to 1 0x00 0x26 DMA_PKT0 Volatile [7:0]: dma_pkt0, w1c 0x00 0x27 DMA_PKT1 W1C [7:0]: dma_pkt1, write1 clear 0x00 Address offset Name Type Description Default value

Datasheet for Telink TC321x DS-TC321x-E7 110 Ver 0.8.1 0x28 DMA2_FIFO RW [3:0]: rptr2_set_data [4]: rptr2_clr [5]: rptr2_next [6]: rptr2_set 0x00 0x29 DMA2_FIFO_WPTR R [3:0]: wptr2 0x00 0x2a DMA3_FIFO RW [3:0]: rptr3_set_data [4]: rptr3_clr [5]: rptr3_next [6]: rptr3_set 0x00 0x2b DMA3_FIFO_WPTR R [3:0]: wptr3 0x00 0x2c DMA3_FIFO_AL W [7:0]: dma3_fifo_al, dma3_fifo_addr[7:0] 0x00 0x2d DMA3_FIFO_AH W [7:0]: dma3_fifo_ah, dma3_fifo_addr[15:8], wptr+1 when writing this register 0x00 0x30 DMA_MW0 RW [3:0]: mwptr 0x00 0x31 DMA_MW1 RW [3:0]: mwptr 0x00 0x32 DMA_MW2 RW [3:0]: mwptr 0x00 0x33 DMA_MW3 RW [3:0]: mwptr 0x00 0x34 DMA_MW4 RW [3:0]: mwptr 0x00 0x35 DMA_MW5 RW [3:0]: mwptr 0x00 0x38 DMA_MR0 Volatile [3:0]: mrptr, mrptr [4]: mr_clr, Write DMA_MW0 mwptr to mrptr [5]: mr_next, mrptr increase 1 [6]: mr_set, Set mrptr value 0x00 0x39 DMA_MR1 Volatile [3:0]: mrptr, mrptr [4]: mr_clr, Write DMA_MW1 mwptr to mrptr [5]: mr_next, mrptr increase 1 [6]: mr_set, Set mrptr value 0x00 Address offset Name Type Description Default value

Datasheet for Telink TC321x DS-TC321x-E7 111 Ver 0.8.1 0x3a DMA_MR2 Volatile [3:0]: mrptr, mrptr [4]: mr_clr, Write DMA_MW2 mwptr to mrptr [5]: mr_next, mrptr increase 1 [6]: mr_set, Set mrptr value 0x00 0x3b DMA_MR3 Volatile [3:0]: mrptr, mrptr [4]: mr_clr, Write DMA_MW3 mwptr to mrptr [5]: mr_next, mrptr increase 1 [6]: mr_set, Set mrptr value 0x00 0x3c DMA_MR4 Volatile [3:0]: mrptr, mrptr [4]: mr_clr, Write DMA_MW4 mwptr to mrptr [5]: mr_next, mrptr increase 1 [6]: mr_set, Set mrptr value 0x00 0x3d DMA_MR5 Volatile [3:0]: mrptr, mrptr [4]: mr_clr, Write DMA_MW5 mwptr to mrptr [5]: mr_next, mrptr increase 1 [6]: mr_set, Set mrptr value 0x00 0x40 DMA0AHH RW [2:0]: r_adr0h, r_adr0[18:16] 0x00 0x41 DMA1AHH RW [2:0]: r_adr1h, r_adr1[18:16] 0x00 0x42 DMA2AHH RW [2:0]: r_adr2h, r_adr2[18:16] 0x00 0x43 DMA3AHH RW [2:0]: r_adr3h, r_adr3[18:16] 0x00 0x44 DMA4AHH RW [2:0]: r_adr4h, r_adr4[18:16] 0x00 0x45 DMA5AHH RW [2:0]: r_adr5h, r_adr5[18:16] 0x00 0x46 DMATAHH RW [2:0]: r_adrth, r_adrt[18:16] 0x00 0x47 DMAA3H RW [2:0]: adr_3 0x00 0x48 DMA7AHH RW [2:0]: r_adr7h, r_adr7[18:16] 0x00 Address offset Name Type Description Default value

Datasheet for Telink TC321x DS-TC321x-E7 112 Ver 0.8.1

11 Interface

11.1 GPIO

The TC3216C/TC3215C supports up to 34 GPIOs, TC3215E supports up to 21 GPIOs, TC3215F supports up to 22 GPIOs, TC3215M supports up to 7 GPIOs. All digital IOs can be used as general purpose IOs. All GPIOs have configurable pull-up/pull-down resistor. Please refer to Section 11.1.4 for details.

11.1.1 Basic Configuration

11.1.1.1 GPIO Lookup Table

Table 11-1 GPIO PAD Function Mux Pad Default Function1 Function2 Function3 Function4 Function5 register PA[0] GPIO All functions 1a WIFI_DENY PA_KS0 UART_CTS - 0x548[4:0] PA[1] GPIO All functions 2b BLE_STATUS PA_KS1 UART1_RX IR_LEARN 0x549[4:0] PA[2] GPIO All functions 1 BLE_ACTIVITY PA_KS2 UART1_TX IR_LEARN 0x54a[4:0] PA[3] SWS GPIO - - - - 0x54b[4:0] PA[4] GPIO All functions 2 WIFI_DENY PA_KS4 - SWM 0x54c[4:0] PA[5] GPIO All functions 1 BLE_STATUS PA_KS5 - mic_dat 0x54d[4:0] PA[6] GPIO All functions 2 BLE_ACTIVITY PA_KS6 - mic_clk 0x54e[4:0] PA[7] GPIO All functions 1 WIFI_DENY PA_KS7 UART_RX - 0x54f[4:0] PB[0] GPIO All functions 3c BLE_STATUS PB_KS0 SPI_CN IR_LEARN 0x550[4:0] PB[1] GPIO - - PB_KS1 SPI_CK - 0x551[4:0] PB[2] GPIO All functions 1 BLE_ACTIVITY PB_KS2 - - 0x552[4:0] PB[3] GPIO - - PB_KS3 UART2_RTX - 0x553[4:0] PB[4] GPIO All functions 1 BLE_STATUS PB_KS4 - mic_dat 0x554[4:0] PB[5] sdadc_aio - - - - - 0x555[4:0] PB[6] sdadc_aio - - - - - 0x556[4:0] PB[7] GPIO All functions 2 BLE_STATUS PB_KS7 - mic_clk 0x557[4:0] PC[0] GPIO All functions 1 BLE_ACTIVITY PC_KS0 - mic_dat 0x558[4:0] PC[1] GPIO All functions 2 WIFI_DENY PC_KS1 - mic_clk 0x559[4:0] PC[2] GPIO All functions 1 BLE_STATUS PC_KS2 - IR_LEARN 0x55a[4:0]

Datasheet for Telink TC321x DS-TC321x-E7 113 Ver 0.8.1 The functions included in the “All functions 1”, “All functions 2”, “All functions 3”, and “All functions 4”, are listed in the table below: Table 11-2 GPIO functions PC[3] GPIO All functions 2 BLE_ACTIVITY PC_KS3 - mic_dat 0x55b[4:0] PC[4] GPIO All functions 1 WIFI_DENY PC_KS4 - mic_clk 0x55c[4:0] PC[5] GPIO All functions 2 BLE_STATUS PC_KS5 - - 0x55d[4:0] PC[6] GPIO All functions 1 BLE_ACTIVITY PC_KS6 - - 0x55e[4:0] PC[7] GPIO All functions 2 WIFI_DENY PC_KS7 - mic_dat 0x55f[4:0] PD[0] sdadc_aio - - - - - 0x560[4:0] PD[1] sdadc_aio - - - - - 0x561[4:0] PD[2] GPIO All functions 1 WIFI_DENY PD_KS2 - - 0x562[4:0] PD[3] GPIO All functions 2 BLE_STATUS PD_KS3 - - 0x563[4:0] PD[4] GPIO - - PD_KS4 - IR_LEARN 0x564[4:0] PD[5] GPIO All functions 2 BLE_ACTIVITY PD_KS5 - - 0x565[4:0] PD[6] GPIO All functions 1 WIFI_DENY PD_KS6 - CLK_7816 0x566[4:0] PD[7] GPIO All functions 2 BLE_STATUS PD_KS7 UART_RTX - 0x567[4:0] PE[0] GPIO All functions 4d BLE_ACTIVITY SPI_MOSI UART1_TX, UART2_RX mic_dat 0x56c[4:0] PE[1] GPIO All functions 4 BLE_STATUS SPI_MISO UART2_TX mic_clk 0x56d[4:0] a. “All functions 1” include 28 functions: I2S_DI, I2S_DO, I2S_LR, I2S_CK, SDM_N1, SDM_P1, SDM_N0, SDM_P0, UART1_RX, UART2_TX, SPI_CN, SPI_CK, SPI_MOSI, SPI_MISO, TX_CYC2PA, RX_CYC2LNA, I2C_SDA, I2C_SCL, UART_RX, UART_TX, UART_RTS, UART_CTS, PWM5, PWM4, PWM3, PWM2, PWM1, PWM0. b. “All functions 2” include 28 functions: I2S_DI, I2S_DO, I2S_LR, I2S_CK, SDM_N1, SDM_P1, SDM_N0, SDM_P0, UART1_TX, UART2_RX, SPI_CN, SPI_CK, SPI_MOSI, SPI_MISO, TX_CYC2PA, RX_CYC2LNA, I2C_SDA, I2C_SCL, UART_RX, UART_TX, UART_RTS, UART_CTS, PWM5_N, PWM4_N, PWM3_N, PWM2_N, PWM1_N, PWM0_N. c. “All functions 3” include 27 functions: I2S_DI, I2S_DO, I2S_LR, I2S_CK, SDM_N1, SDM_P1, SDM_N0, SDM_P0, UART1_TX, UART2_RX, UART2_TX, UART2_RTX, UART1_RTX, UART_RTX, I2C_SDA, I2C_SCL, UART_RX, UART_TX, UART_RTS, UART_CTS, PWM5_N, PWM4_N, PWM3_N, PWM2_N, PWM1_N, PWM0_N, CLK_7816. d. “All functions 4” include 11 functions: I2S_DI, I2S_DO, I2S_LR, I2S_CK, SDM_N1, SDM_P1, SDM_N0, SDM_P0, IR_LEARN, UART_RTX, CLK_7816. Register value All functions 1 All functions 2 All functions 3 All functions 4 2 - - - CLK_7816 Pad Default Function1 Function2 Function3 Function4 Function5 register

Datasheet for Telink TC321x DS-TC321x-E7 114 Ver 0.8.1

3 PWM0 PWM0_N PWM0_N UART_RTX

4 PWM1 PWM1_N PWM1_N IR_LEARN

5 PWM2 PWM2_N PWM2_N -

6 PWM3 PWM3_N PWM3_N -

7 PWM4 PWM4_N PWM4_N -

8 PWM5 PWM5_N PWM5_N -

9 UART_CTS UART_CTS UART_CTS -

10 UART_RTS UART_RTS UART_RTS -

11 UART_TX UART_TX UART_TX -

12 UART_RX UART_RX UART_RX -

13 I2C_SCL I2C_SCL I2C_SCL -

14 I2C_SDA I2C_SDA I2C_SDA -

15 RX_CYC2LNA RX_CYC2LNA UART_RTX -

16 TX_CYC2PA TX_CYC2PA UART1_RTX -

17 SPI_MISO SPI_MISO UART2_RTX -

18 SPI_MOSI SPI_MOSI UART2_TX -

19 SPI_CK SPI_CK CLK_7816 -

20 SPI_CN SPI_CN - -

21 UART2_TX UART2_RX UART2_RX -

22 UART1_RX UART1_TX UART1_TX -

24 SDM_P0 SDM_P0 SDM_P0 SDM_P0

25 SDM_N0 SDM_N0 SDM_N0 SDM_N0

26 SDM_P1 SDM_P1 SDM_P1 SDM_P1

27 SDM_N1 SDM_N1 SDM_N1 SDM_N1

28 I2S_CK I2S_CK I2S_CK I2S_CK

29 I2S_LR I2S_LR I2S_LR I2S_LR

30 I2S_DO I2S_DO I2S_DO I2S_DO

31 I2S_DI I2S_DI I2S_DI I2S_DI

Register value All functions 1 All functions 2 All functions 3 All functions 4

Datasheet for Telink TC321x DS-TC321x-E7 115 Ver 0.8.1 Table 11-3 GPIO Setting Pad Input IE OE SR DS0/DS1 Act as GPIO/ Priority output set/ output clear output toggle PA[0] 0x500[0] 0x501[0] 0x502[0] 0x503[0] 0x504[0]/ 0x505[0] 0x506[0]/ 0x507[0] 0x5c0[0]/ 0x5c1[0] 0x5c2[0] PA[1] 0x500[1] 0x501[1] 0x502[1] 0x503[1] 0x504[1]/ 0x505[1] 0x506[1]/ 0x507[1] 0x5c0[1]/ 0x5c1[1] 0x5c2[1] PA[2] 0x500[2] 0x501[2] 0x502[2] 0x503[2] 0x504[2]/ 0x505[2] 0x506[2]/ 0x507[2] 0x5c0[2]/ 0x5c1[2] 0x5c2[2] PA[3] 0x500[3] 0x501[3] 0x502[3] 0x503[3] 0x504[3]/ 0x505[3] 0x506[3]/ 0x507[3] 0x5c0[3]/ 0x5c1[3] 0x5c2[3] PA[4] 0x500[4] 0x501[4] 0x502[4] 0x503[4] 0x504[4]/ 0x505[4] 0x506[4]/ 0x507[4] 0x5c0[4]/ 0x5c1[4] 0x5c2[4] PA[5] 0x500[5] 0x501[5] 0x502[5] 0x503[5] 0x504[5]/ 0x505[5] 0x506[5]/ 0x507[5] 0x5c0[5]/ 0x5c1[5] 0x5c2[5] PA[6] 0x500[6] 0x501[6] 0x502[6] 0x503[6] 0x504[6]/ 0x505[6] 0x506[6]/ 0x507[6] 0x5c0[6]/ 0x5c1[6] 0x5c2[6] PA[7] 0x500[7] 0x501[7] 0x502[7] 0x503[7] 0x504[7]/ 0x505[7] 0x506[7]/ 0x507[7] 0x5c0[7]/ 0x5c1[7] 0x5c2[7] PB[0] 0x508[0] 0x509[0] 0x50a[0] 0x50b[0] 0x50c[0]/ 0x50d[0] 0x50e[0]/ 0x50f[0] 0x5c4[0]/ 0x5c5[0] 0x5c6[0] PB[1] 0x508[1] 0x509[1] 0x50a[1] 0x50b[1] 0x50c[1]/ 0x50d[1] 0x50e[1]/ 0x50f[1] 0x5c4[1]/ 0x5c5[1] 0x5c6[1] PB[2] 0x508[2] 0x509[2] 0x50a[2] 0x50b[2] 0x50c[2]/ 0x50d[2] 0x50e[2]/ 0x50f[2] 0x5c4[2]/ 0x5c5[2] 0x5c6[2] PB[3] 0x508[3] 0x509[3] 0x50a[3] 0x50b[3] 0x50c[3]/ 0x50d[3] 0x50e[3]/ 0x50f[3] 0x5c4[3]/ 0x5c5[3] 0x5c6[3] a2[4]/ a3[4] 0x50e[4]/ 0x50f[4] 0x5c4[4]/ 0x5c5[4] 0x5c6[4] a2[5]/ a3[5] -/0x50f[5] 0x5c4[5]/ 0x5c5[5] 0x5c6[5] a2[6]/ a3[6] -/0x50f[6] 0x5c4[6]/ 0x5c5[6] 0x5c6[6]

Datasheet for Telink TC321x DS-TC321x-E7 116 Ver 0.8.1 a2[7]/ a3[7] 0x50e[7]/ 0x50f[7] 0x5c4[7]/ 0x5c5[7] 0x5c6[7] a6[0]/ a7[0] 0x516[0]/ 0x517[0] 0x5c8[0]/ 0x5c9[0] 0x5ca[0] a6[1]/ a7[1] 0x516[1]/ 0x517[1] 0x5c8[1]/ 0x5c9[1] 0x5ca[1] a6[2]/ a7[2] 0x516[2]/ 0x517[2] 0x5c8[2]/ 0x5c9[2] 0x5ca[2] a6[3]/ a7[3] 0x516[3]/ 0x517[3] 0x5c8[3]/ 0x5c9[3] 0x5ca[3] a6[4]/ a7[4] 0x516[4]/ 0x517[4] 0x5c8[4]/ 0x5c9[4] 0x5ca[4] a6[5]/ a7[5] 0x516[5]/ 0x517[5] 0x5c8[5]/ 0x5c9[5] 0x5ca[5] a6[6]/ a7[6] 0x516[6]/ 0x517[6] 0x5c8[6]/ 0x5c9[6] 0x5ca[6] a6[7]/ a7[7] 0x516[7]/ 0x517[7] 0x5c8[7]/ 0x5c9[7] 0x5ca[7] PD[0] 0x518[0] 0x519[0] 0x51a[0] 0x51b[0] 0x51c[0]/ 0x51d[0] -/0x51f[0] 0x5cc[0]/ 0x5cd[0] 0x5ce[0] PD[1] 0x518[1] 0x519[1] 0x51a[1] 0x51b[1] 0x51c[1]/ 0x51d[1] -/0x51f[1] 0x5cc[1]/ 0x5cd[1] 0x5ce[1] PD[2] 0x518[2] 0x519[2] 0x51a[2] 0x51b[2] 0x51c[2]/ 0x51d[2] 0x51e[2]/ 0x51f[2] 0x5cc[2]/ 0x5cd[2] 0x5ce[2] PD[3] 0x518[3] 0x519[3] 0x51a[3] 0x51b[3] 0x51c[3]/ 0x51d[3] 0x51e[3]/ 0x51f[3] 0x5cc[3]/ 0x5cd[3] 0x5ce[3] PD[4] 0x518[4] 0x519[4] 0x51a[4] 0x51b[4] 0x51c[4]/ 0x51d[4] 0x51e[4]/ 0x51f[4] 0x5cc[4]/ 0x5cd[4] 0x5ce[4] PD[5] 0x518[5] 0x519[5] 0x51a[5] 0x51b[5] 0x51c[5]/ 0x51d[5] 0x51e[5]/ 0x51f[5] 0x5cc[5]/ 0x5cd[5] 0x5ce[5] Pad Input IE OE SR DS0/DS1 Act as GPIO/ Priority output set/ output clear output toggle

Datasheet for Telink TC321x DS-TC321x-E7 117 Ver 0.8.1

11.1.1.2 Multiplexed Functions

Each pin listed in Table 11-3 acts as the function in the “Default Function” column by default.

• PA[3] acts as SWS function by default.
• The other digital IOs act as GPIO function by default. If a pin with multiplexed functions does not act as GPIO function by default, to use it as GPIO, first set the bit in “Act as GPIO” column in as 1’b1. After GPIO function is enabled, if the pin is used as output, the bits “OE” columns should be set as 1’b1, then set the register value in the “Output” column; if the pin is used as input, the bits in “IE” columns should be set as 1’b1, and the input data can be read from the register in the “Input” column. To use a pin as certain multiplexed function (neither the default function nor GPIO function), first clear the bit in “Act as GPIO” column to disable GPIO function, and then configure “Register” column to enable multiplexed function correspondingly. PD[6] 0x518[6] 0x519[6] 0x51a[6] 0x51b[6] 0x51c[6]/ 0x51d[6] 0x51e[6]/ 0x51f[6] 0x5cc[6]/ 0x5cd[6] 0x5ce[6] PD[7] 0x518[7] 0x519[7] 0x51a[7] 0x51b[7] 0x51c[7]/ 0x51d[7] 0x51e[7]/ 0x51f[7] 0x5cc[7]/ 0x5cd[7] 0x5ce[7] PE[0] 0x520[0] 0x521[0] 0x522[0] 0x523[0] 0x524[0]/ 0x525[0] 0x526[0]/ 0x527[0] 0x5d0[0]/ 0x5d1[0] 0x5d2[0] PE[1] 0x520[1] 0x521[1] 0x522[1] 0x523[1] 0x524[1]/ 0x525[1] 0x526[1]/ 0x527[1] 0x5d0[1]/ 0x5d1[1] 0x5d2[1] Pad Input IE OE SR DS0/DS1 Act as GPIO/ Priority output set/ output clear output toggle NOTE:
• IE: Input enable, high active. 1: enable input, 0: disable input.
• OE: Output enable, low active. 1: enable output, 0: disable output.
• Register: See Table 11-3 for configuration of multiplexed functions.
• Input: Read GPI input.
• Output: configure GPO output.
• DS0/DS1/SR: Drive strength and slew rate.
• Act as GPIO: Enable (1) or disable (0) GPIO function.
• Polarity: See Section 11.1.3.
• Priority: “Act as GPIO” has the highest priority. To configure as multiplexed function, disable GPIO function first.
• a0 ~ a7 are analog registers; others are digital registers.
• For all unused GPIOs, corresponding “IE” must be set as 0.
• To use SD ADC pin function, please refer to the corresponding module section.

Datasheet for Telink TC321x DS-TC321x-E7 118 Ver 0.8.1

11.1.1.3 Drive Strength

The registers in the “DS0”, “DS1” and “SR” columns are used to configure the corresponding pin’s driving strength and slew rate. The “DS” configuration takes effect when the pin is used as output. It’s set as the strongest driving level by default. In actual applications, driving strength can be decreased to lower level if necessary. Table 11-4 Drive Strength

11.1.2 GPIO Logic Introduction

Figure 11-1 GPIO Logic Diagram In the figure above, 1. DS0/DS1/SR: drive strength and slew rate 2. OE: output enable, 0: high Z; 1: output 3. O: output value, when OEN is 0, output this value DS0 DS1 SR Drive strength Slew rate 0 0 0 2 mA Fast 0 1 0 4 mA Fast 1 0 0 8 mA Fast 1 1 0 12 mA Fast 0 0 1 2 mA Slow 0 1 1 4 mA Slow 1 0 1 8 mA Slow 1 1 1 12 mA Slow VDD100K ohm OE O I IE(reg_ana/reg_dig) DS0/DS1/SR(reg_ana/reg_dig) PAD Mux_I GPIO_OE Mux_OE GPIO_O Mux_O AS_GPIO GPIO_I 30K~70K ohm 1M ohm 10K ohm

Datasheet for Telink TC321x DS-TC321x-E7 119 Ver 0.8.1 4. I: input value 5. IE: input enable, if IE is 0, C is always zero 6. 1M, 10K pull up and 100K pull down resistors are controlled by analog 3.3V register controller

11.1.3 Connection Relationship Between GPIO and Related Modules

GPIO can be used to generate GPIO interrupt signal for interrupt system, counting or control signal for Timer/ Counter module, or GPIO2RISC and GPIO2MUX interrupt signal for interrupt system. For the “Exclusive Or (XOR)” operation result for input signal from any GPIO pin and respective “Polarity” value, on one hand, it takes “And” operation with “irq” and generates GPIO interrupt request signal; on the other hand, it takes “And” operation with “m0/m1/m2”, and generates counting signal in Mode 1 or control signal in Mode 2 for Timer0/Timer1/Timer2, or generates GPIO2RISC[0]/GPIO2RISC[1]/GPIO2RISC[2] interrupt request signal. GPIO interrupt request signal = | ((input ^ polarity) & irq); Counting (Mode 1) or control (Mode 2) signal for Timer0 = | ((input ^ polarity) & m0); Counting (Mode 1) or control (Mode 2) signal for Timer1 = | ((input ^ polarity) & m1); Counting (Mode 1) or control (Mode 2) signal for Timer2 = | ((input ^ polarity) & m2); GPIO2RISC[0] interrupt request signal = | ((input ^ polarity) & m0); GPIO2RISC[1] interrupt request signal = | ((input ^ polarity) & m1). GPIO2RISC[2] interrupt request signal = | ((input ^ polarity) & m2). GPIO2MUX interrupt request signal = LEV2EDGE (| ((input ^ polarity) & m0)) | LEV2EDGE (| ((input ^ polarity) & m1))... | LEV2EDGE (| ((input ^ polarity) & m7)). NOTE:

• When PAD is set as functional IO, no need to configure GPIO_OE as the functional IO enables Mux_OE.
• When PAD is input, IE should be enabled regardless of functional IO or GPIO, and output to I, AS_GPIO is 1, Mux_I is 1.
• Analog pull-up has two options: 1M, 10k ohm; analog pull-down has only 100k ohm. They can be config- ured via corresponding analog registers.
• The methods to change the output state of GPIO_O, for example, PA group can output 0 and 1 by 0x5c0 (PA_OUTPUT_SET), 0x5c1 (PA_OUTPUT_CLR) can clear the output state of PA, 0x5c2(PA_OUTPUT_TOGGLE) can toggle the output state of PA.
• The GPIO configuration sequence should be: configure the MUX function, and then disable GPIO function. If disable GPIO first and then set function, the default function of the pad may be enabled and causes false output level. NOTE:
• LEV2EDGE is the level/edge interrupt selection function, controlled by 0x577 (GPIO_IRQ_LVL). Please refer to GPIO2MUX signal: for specific use.

Datasheet for Telink TC321x DS-TC321x-E7 120 Ver 0.8.1 Figure 11-2 Logic Relationship Between GPIO and Related Modules Please refer to Table 11-5 and Table 9-1 to learn how to configure GPIO for interrupt system or Timer/Counter (Mode 1 or Mode 2). Enable GPIO function First enable GPIO function, enable IE and disable OEN. Please see Section 11.1.1. GPIO IRQ signal: Select GPIO interrupt trigger edge (positive edge or negative edge) via configuring “ Polarity”, and set corresponding GPIO interrupt enabling bit “Irq”. Then set address 0x574[2] (irq_enable) to enable GPIO IRQ. Finally enable GPIO interrupt (irq_gpio) via address 0x642[2]. User can read addresses 0x578 ~ 0x57b to see which GPIO asserts GPIO interrupt request signal. Note: > PD[7] ~ PD[0]. GPIO_IRQgpio_sel_p[37:0] gpio_sel IRQ[37:0] {pa[7:0],pb[7:0],pc[7:0] pd[7:0],pe[3:0],pf[1:0]} gpio_pol[37:0] POLARITY[37:0] gpio2risc0[37:0] GPIO2RISC[0]_IRQM0[37:0] gpio2risc1[37:0] M1[37:0] Timer0 Timer1 Timer0_IRQ GPIO2RISC[1]_IRQ Timer1_IRQ IRQ_CTRL[1] gpio2risc2[37:0] M2[37:0] Timer2 GPIO2RISC[2]_IRQ Timer2_IRQ

Datasheet for Telink TC321x DS-TC321x-E7 121 Ver 0.8.1 Figure 11-3 GPIO IRQ signal GPIO2MUX signal: Select a set of GPIOs from PA, PB, PC, PD, PF as interrupt source. Set address 0x530 ~ 0x535 (M0), 0x538 ~ 0x53d (M1), 0x540 ~ 0x545 (M2), 0x598 ~ 0x59d (M3), 0x5a0 ~ 0x5a5(M4), 0x5a8 ~ 0x5ad (M5), 0x5b0 ~ 0x5b5 (M6), 0x5b8 ~ 0x5bd(M7) to open the corresponding mux. Then set address 0x576 (gpio_irq_mask) to enable interrupts for the selected GPIO signals. Finally set address 0x577 (gpio_irq_lvl) to set the type of interrupt to be edge sensitive or level sensitive. User can read address 0x56f to see which GPIO asserts interrupt request signal and clear the interrupt through asserting the corresponding bit of 0x56f (GPIO_IRQ_FROM_PAD). GPIO gpio_irq_o gpio_sel_p[37:0] gpio_sel gpio_wakeup1 r_irq_en irq_en[37:0] gpio_pol[37:0] r_inv[37:0] gpio2risc1[37:0] gpio2risc0_1 r_m1[37:0] gpio2risc2[37:0] gpio2risc1_2 r_m2[37:0] PLIC CPU_SYSTEM gpio2risc0[37:0] gpio2risc0_o r_m0[37:0] gpio2risc4[37:0] r_m4[37:0] gpio2risc5[37:0] r_m5[37:0] gpio2risc3[37:0] r_m3[37:0] gpio2risc6[37:0] r_m6[37:0] gpio2risc7[37:0] r_m7[37:0] r_wkup_mux r_wakeup_en gpio_wakeup0 r_irq_mux_en0 gpio_wakeup gpio_new_irq_o r_irq_mux_en1 r_irq_mux_en2

Datasheet for Telink TC321x DS-TC321x-E7 122 Ver 0.8.1 Figure 11-4 GPIO IRQ MUX signal Timer/Counter counting or control signal: Configure “Polarity”. In Timer Mode 1, it determines GPIO edge when Timer Tick counting increases. In Timer Mode 2, it determines GPIO edg;e when Timer Tick starts counting. Then set “m0/m1/m2” to specify the GPIO which generates counting signal (Mode 1)/control signal (Mode 2) for Timer0/Timer1/Timer2. User can read addresses 0x580 ~ 0x583/0x588 ~ 0x58b/0x590 ~ 0x593 to see which GPIO asserts counting signal (in Mode 1) or control signal (in Mode 2) for Timer0/Timer1/Timer2. Note: Timer0: 0x580[7:0] --> GPIO2RISC IRQ signal: Select GPIO2RISC interrupt trigger edge (positive edge or negative edge) via configuring “ Polarity”, and set corresponding GPIO enabling bit “m0”/“m1”/“m2”. Enable GPIO2RISC[0]/GPIO2RISC[1]/GPIO2RISC[2] interrupt, i.e. “gpio2risc[0]” (address 0x642[5])/ “gpio2risc[1]”(address 0x642[6])/“gpio2risc[2]”(address 0x642[7]). Table 11-5 GPIO IRQ Table Pin Input (R) Polarity 1: Active Low 0: Active High m0 m0 m2 m3 PA[0] 0x500[0] 0x507[0] 0x530[0] 0x538[0] 0x540[0] 0x598[0] MUX pa_io_i pa_ie_i pa_i pa_c pa_i_o pa_io_o pa_fs_o MUX ...

39 UART1_RX_I

36 UART1_CTS_I

0x548[5:0] pafo ... 4342 PA_KS0 DBG0 PWM0 DBG_OTP_PCLK DBG_OTP_PAIO1 DBG_OTP_DAT20 DBG_OTP0_DAT13 pa_oen_o pa_ie_o Pad_Mux pa_i_o pa_oen pa_ie pa_oen_i pafoen ... pa_c_i pa_fs PA_KS0_oen DBG0_oen PWM0_oen DBG_OTP_PCLK_oen DBG_OTP_PAIO_oen DBG_OTP_DAT20_oen DBG_OTP0_DAT1_oen pa_pe_o pa_ds_o gpio2risc0 gpio2risc1gpio_pol r_inv (Polarity in LUT) gpio_irq TIMER gpi0 gpi1 as interrupt source r_m1[0] r_m1[37] r_m0[0] r_m0[37] r_wakeup_m[0] (irq in LUT) r_wakeup_m[37] (irq in LUT) ... gpio2risc1[0] gpio2risc1[37] gpio2risc1_or gpio2risc0[0] gpio2risc0[37] gpio2risc0_or ... gpio_sel_p[0] gpio_sel_p[37] gpio_sel... gpio_wakeup_en r_irq_en r_wakeup_en SC gpio_wakeup pc_i_o pc_oen pa_c pa_p PA pa_i pa_oen pa_ie pa_pe pa_ds pc_c pd_p PC pc_i pc_oen pc_ie pc_pe pc_ds Reg_ana pc_ie pc_pe pc_ds irq_lvl & mask irq_lvl & mask irq_lvl & mask r_m2[0] r_m2[37] gpio2risc2[0] gpio2risc2[37] gpio2risc2_or irq_lvl & mask r_m7[0] r_m7[37] gpio2risc7[0] gpio2risc7[37] gpio2risc7_or irq_lvl & mask gpi2 r_irq_mux_en0 ... ... gpio_new_irq_o 4PWM1 4PWM1_oen UART_CTS_I PA_KS0_I SPI_CK_I SPI_CN_I WIFI_DENY_I UART1_RTX_I r_irq_mux_en1 r_irq_mux_en2

Datasheet for Telink TC321x DS-TC321x-E7 123 Ver 0.8.1 PA[1] 0x500[1] 0x507[1] 0x530[1] 0x538[1] 0x540[1] 0x598[1] PA[2] 0x500[2] 0x507[2] 0x530[2] 0x538[2] 0x540[2] 0x598[2] PA[3] 0x500[3] 0x507[3] 0x530[3] 0x538[3] 0x540[3] 0x598[3] PA[4] 0x500[4] 0x507[4] 0x530[4] 0x538[4] 0x540[4] 0x598[4] PA[5] 0x500[5] 0x507[5] 0x530[5] 0x538[5] 0x540[5] 0x598[5] PA[6] 0x500[6] 0x507[6] 0x530[6] 0x538[6] 0x540[6] 0x598[6] PA[7] 0x500[7] 0x507[7] 0x530[7] 0x538[7] 0x540[7] 0x598[7] PB[0] 0x508[0] 0x50f[0] 0x531[0] 0x539[0] 0x541[0] 0x599[0] PB[1] 0x508[1] 0x50f[1] 0x531[1] 0x539[1] 0x541[1] 0x599[1] PB[2] 0x508[2] 0x50f[2] 0x531[2] 0x539[2] 0x541[2] 0x599[2] PB[3] 0x508[3] 0x50f[3] 0x531[3] 0x539[3] 0x541[3] 0x599[3] PB[4] 0x508[4] 0x50f[4] 0x531[4] 0x539[4] 0x541[4] 0x599[4] PB[5] 0x508[5] 0x50f[5] 0x531[5] 0x539[5] 0x541[5] 0x599[5] PB[6] 0x508[6] 0x50f[6] 0x531[6] 0x539[6] 0x541[6] 0x599[6] PB[7] 0x508[7] 0x50f[7] 0x531[7] 0x539[7] 0x541[7] 0x599[7] PC[0] 0x510[0] 0x517[0] 0x532[0] 0x53a[0] 0x542[0] 0x59a[0] PC[1] 0x510[1] 0x517[1] 0x532[1] 0x53a[1] 0x542[1] 0x59a[1] PC[2] 0x510[2] 0x517[2] 0x532[2] 0x53a[2] 0x542[2] 0x59a[2] PC[3] 0x510[3] 0x517[3] 0x532[3] 0x53a[3] 0x542[3] 0x59a[3] PC[4] 0x510[4] 0x517[4] 0x532[4] 0x53a[4] 0x542[4] 0x59a[4] PC[5] 0x510[5] 0x517[5] 0x532[5] 0x53a[5] 0x542[5] 0x59a[5] PC[6] 0x510[6] 0x517[6] 0x532[6] 0x53a[6] 0x542[6] 0x59a[6] PC[7] 0x510[7] 0x517[7] 0x532[7] 0x53a[7] 0x542[7] 0x59a[7] PD[0] 0x518[0] 0x51f[0] 0x533[0] 0x53b[0] 0x543[0] 0x59b[0] PD[1] 0x518[1] 0x51f[1] 0x533[1] 0x53b[1] 0x543[1] 0x59b[1] PD[2] 0x518[2] 0x51f[2] 0x533[2] 0x53b[2] 0x543[2] 0x59b[2] Pin Input (R) Polarity 1: Active Low 0: Active High m0 m0 m2 m3

Datasheet for Telink TC321x DS-TC321x-E7 124 Ver 0.8.1

11.1.4 Pull-Up/Pull-Down Resistor

All GPIOs support configurable pull-up resistor of rank x1 and x100 or pull-down resistor of rank x10 which are all disabled by default. Analog registers afe_0x17<7:0> ~ afe_0x1f<3:0> serve to control the pull-up/pull- down resistor for each GPIO. Take the PA[3] for example: Setting analog register afe_0x17<7:6> to 2’b01/2’b11/2’b10 is to respectively enable pull-up resistor of rank x100/pull-up resistor of rank x1/pull-down resistor of rank x10 for PA[3]; Clearing the two bits (default value) disables pull-up and pull-down resistor for PA[3]. Table 11-6 Analog Registers for Pull-Up/Pull-Down Resistor Control PD[3] 0x518[3] 0x51f[3] 0x533[3] 0x53b[3] 0x543[3] 0x59b[3] PD[4] 0x518[4] 0x51f[4] 0x533[4] 0x53b[4] 0x543[4] 0x59b[4] PD[5] 0x518[5] 0x51f[5] 0x533[5] 0x53b[5] 0x543[5] 0x59b[5] PD[6] 0x518[6] 0x51f[6] 0x533[6] 0x53b[6] 0x543[6] 0x59b[6] PD[7] 0x518[7] 0x51f[7] 0x533[7] 0x53b[7] 0x543[7] 0x59b[7] PE[0] 0x520[0] 0x527[0] 0x534[0] 0x53c[0] 0x544[0] 0x59c[0] PE[1] 0x520[1] 0x527[1] 0x534[1] 0x53c[1] 0x544[1] 0x59c[1] Address Name Description Default Value Rank x10 x100 Typical value (depend on actual application) 10 kOhm 100 kOhm

1 MOhm

PA[3:0] pull up and down select: <7:6>: PA[3] <5:4>: PA[2] <3:2>: PA[1] <1:0>: PA[0] 00: Null 01: x100 pull up 10: x10 pull down 11: x1 pull up 0x00 Pin Input (R) Polarity 1: Active Low 0: Active High m0 m0 m2 m3

Datasheet for Telink TC321x DS-TC321x-E7 125 Ver 0.8.1 PA[7:4] pull up and down select: <7:6>: PA[7] <5:4>: PA[6] <3:2>: PA[5] <1:0>: PA[4] 00: Null 01: x100 pull up 10: x10 pull down 11: x1 pull up 0x00 PB[3:0] pull up and down select: <7:6>: PB[3] <5:4>: PB[2] <3:2>: PB[1] <1:0>: PB[0] 00: Null 01: x100 pull up 10: x10 pull down 11: x1 pull up 0x00 PB[7:4] pull up and down select: <7:6>: PB[7] <5:4>: PB[6] <3:2>: PB[5] <1:0>: PB[4] 00: Null 01: x100 pull up 10: x10 pull down 11: x1 pull up 0x00 Address Name Description Default Value

Datasheet for Telink TC321x DS-TC321x-E7 126 Ver 0.8.1 PC[3:0] pull up and down select: <7:6>: PC[3] <5:4>: PC[2] <3:2>: PC[1] <1:0>: PC[0] 00: Null 01: x100 pull up 10: x10 pull down 11: x1 pull up 0x00 PC[7:4] pull up and down select: <7:6>: PC[7] <5:4>: PC[6] <3:2>: PC[5] <1:0>: PC[4] 00: Null 01: x100 pull up 10: x10 pull down 11: x1 pull up 0x00 PD[3:0] pull up and down select: <7:6>: PD[3] <5:4>: PD[2] <3:2>: PD[1] <1:0>: PD[0] 00: Null 01: x100 pull up 10: x10 pull down 11: x1 pull up 0x00 Address Name Description Default Value

Datasheet for Telink TC321x DS-TC321x-E7 127 Ver 0.8.1

11.2 SWM and SWS

The SoC supports Single Wire interface. SWM (Single Wire Master) and SWS (Single Wire Slave) represent the master and slave device of the single wire communication system developed by Telink. The maximum data rate can be up to 2 Mbps. SWS usage is not supported in power-saving mode (Deep Sleep or Suspend).

11.3 I2C

The SoC embeds I2C hardware module, which could act as Master mode or Slave mode. I2C is a popular inter- IC interface requiring only 2 bus lines, a serial data line (SDA) and a serial clock line (SCL).

11.3.1 Communication Protocol

Telink I2C module supports standard-mode (100 kbps) and fast-mode (400 kbps) with restriction that system clock must be by at least 10x of data rate. Two wires, SDA and SCL (SCK) carry information between Master device and Slave device connected to the bus. Each device is recognized by unique address (ID). Master device is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. Slave device is the device addressed by a Master. PD[7:4] pull up and down select: <7:6>: PD[7] <5:4>: PD[6] <3:2>: PD[5] <1:0>: PD[4] 00: Null 01: x100 pull up 10: x10 pull down 11: x1 pull up 0x00 PE[1:0] pull up and down select: <3:2>: PE[1] <1:0>: PE[0] 00: Null 01: x100 pull up 10: x10 pull down 11: x1 pull up 0x00 Address Name Description Default Value

Datasheet for Telink TC321x DS-TC321x-E7 128 Ver 0.8.1 Both SDA and SCL are bidirectional lines connected to a positive supply voltage via a pull-up resister. It’s recommended to use external 3.3 kOhm pull-up resistor. For standard mode, the internal pull-up resistor of rank x1 can be used instead of the external 3.3 kOhm pull-up. When the bus is free, both lines are HIGH. It’s noted that data in SDA line must keep stable when clock signal in SCL line is at high level, and level state in SDA line is only allowed to change when clock signal in SCL line is at low level. Figure 11-5 I2C Timing Chart

11.3.2 Register Table

The I2C related registers are listed as following, the base address of the following registers is 0x800000. Table 11-7 Register Configuration for I2C Address offset Name Type Description Default Value 0x00 I2CSP RW I2C master clock speed 0x1f 0x01 I2C_ID RW [7:1]: I2C ID 0x5c 0x02 I2CMST RW [0]: master busy [1]: master packet busy [2]: master received status 0 for ACK; 1 for NAK 0x00 0x03 I2CSCT0 RW [0]: address auto increase enable [1]: I2C master enable [2]: enable Mapping Mode [3]: r_clk_stretch_en, suspend transmission by pulling SCL down to low level, and continue transmission after SCL is released to high level 0x01 0x04 I2CAD RW [7:0]: Data buffer in master mode 0x5a 0x05 I2CDW RW [7:0]: Data buffer in master mode 0xf1

Datasheet for Telink TC321x DS-TC321x-E7 129 Ver 0.8.1

11.3.3 I2C Slave Mode

I2C module of the SoC acts as Slave mode by default. I2C slave address can be configured via register I2C_ID (address 0x01) [7:1]. Figure 11-6 Byte Consisted of Slave Address and R/W Flag Bit I2C Slave mode supports two sub modes including Direct Memory Access (DMA) mode and Mapping mode, which is selectable via address 0x03[2]. 0x06 I2CDR RW [7:0]: Data buffer for Read or Write in master mode 0x00 0x07 I2CSCT1 RW [0]: launch ID cycle [1]: launch address cycle (send I2CAD data) [2]: launch data write cycle [3]: launch data read cycle For Master Write: 0: I2CAD & I2CDW, 1: I2CAD & I2CDW & I2CDR. To write 3 bytes: bit[3] = 1; to write 2 bytes: bit[3] = 0. For Master Read: always 1. [4]: launch start cycle [5]: launch stop cycle [6]: enable read ID [7]: enable ACK in read command 0x00 0xe0 I2CMAP_HADR R [6:0]: I2C read address 0x00 0xe1 HOSR_ADR_L RW Low byte of Mapping mode buffer address 0x80 0xe2 HOSR_ADR_M RW Middle byte of Mapping mode buffer address 0xd7 0xe3 HOSR_ADR_H RW High byte of Mapping mode buffer address 0x00 0xe4 I2CMAP_HOST RW [0]: host_cmd_irq_o, I2C host operation has happened. Write 1 to clear. [1]: host_rd_tag_o, I2C host operation has happened and is read operation. Write 1 to clear. 0x00 Address offset Name Type Description Default Value

Datasheet for Telink TC321x DS-TC321x-E7 130 Ver 0.8.1 In I2C Slave mode, Master could initiate transaction anytime. I2C slave module replies with ACK automatically. To monitor the start of I2C transaction, user could set interrupt from GPIO for SDA or SCL.

11.3.3.1 DMA Mode

In DMA mode, other devices (Master) could access (read/write) designated address in Register and/or SRAM of the SoC according to I2C protocol. I2C module of the SoC executes the read/write command from I2C master automatically. But user needs to notice that the system clock shall be at least 10x faster than I2C bit rate. The access address designated by Master is offset by 0x800000. In the SoC, Register address starts from 0x800000 and SRAM address starts from 0x840000. For example, if Addr High (AddrH) is 0x04, Addr Middle (AddrM) is 0x00, and Addr Low (AddrL) is 0xcc, the real address of accessed data is 0x8400cc. In DMA mode, Master could read/write data byte by byte. The designated access address is initial address and it supports auto increment by setting address 0x03[0] to 1’b1. Figure 11-7 Read Format in DMA Mode Figure 11-8 Write Format in DMA Mode

11.3.3.2 Mapping Mode

Mapping mode could be enabled via setting register I2CSCT0 (address 0x03)[2] to 1’b1. In mapping mode, data written and read by I2C master are redirected to specified 128-byte buffer in SRAM. User could specify the initial address of the buffer by configuring registers HOSR_ADR_L (address 0xe1, lower byte), HOSR_ADR_M (address 0xe2, middle byte) and HOSR_ADR_H (address 0xe3, higher byte). The first 64- byte buffer is for written data and following 64-byte buffer is for read data. Every time the data access starts from the beginning of the Write-buffer/Read-buffer after I2C stop condition occurs. The last accessed data address could be checked in register I2CMAP_HADR (address 0xe0) [6:0] which is only updated after I2C STOP occurs. START ID W 8 bits ACK AddrH ACK AddrM ACK DATA ACK 8 bits 8 bits 8 bits Read Format in DMA mode START ID R 8 bits ACK NAK STOP AddrL ACK STOP 8 bits START ID W 8 bits ACK AddrH ACK AddrM ACK 8 bits 8 bits Write Format in DMA mode AddrL ACK DATA ACK STOP 8 bits 8 bits

Datasheet for Telink TC321x DS-TC321x-E7 131 Ver 0.8.1 Figure 11-9 Read Format in Mapping Mode Figure 11-10 Write Format in Mapping Mode

11.3.4 I2C Master Mode

Address 0x03[1] should be set to 1’b1 to enable I2C master mode for the SoC. Address 0x00 serves to set I2C Master clock: FI2C = System Clock / (4 *clock speed configured in address 0x00). A complete I2C protocol contains START, Slave Address, R/W bit, data, ACK and STOP. Slave address could be configured via address 0x01[7:1]. I2C Master (i.e. I2C module of the SoC) could send START, Slave Address, R/W bit, data and STOP cycle by configuring address 0x07. I2C master sends enabled cycles in the correct sequence. Address 0x02 serves to indicate whether Master/Master packet is busy, as well as Master received status. Bit[0] is set to 1 when one byte is being sent, and the bit can be automatically cleared after a start signal/ address byte/acknowledge signal/data /stop signal is sent. Bit[1] is set to 1 when the start signal is sent, and the bit is automatically cleared after the stop signal is sent. Bit[2] indicates whether to succeed in sending acknowledgement signal.

11.3.4.1 I2C Master Write Transfer

I2C Master has 3-byte buffer for write data, which are I2CAD (0x04), I2CDW (0x05) and I2CDR (0x06). Write transfer is completed by I2C master module. For example, to implement an I2C write transfer with 3-byte data, which contains START, Slave Address, Write bit, ACK from Slave, 1st byte, ACK from Slave, 2nd byte, ACK from Slave, 3rd byte, ACK from Slave and STOP, user needs to configure I2C Slave Address to I2C_ID (0x01) [7:1], 1st byte data to I2CAD, 2nd byte data to I2CDW and 3rd byte to I2CDR. To start I2C write transfer, I2CSCT1 (0x07) is configured to 0x3f (0011 1111). I2C Master launches START, Slave address, Write bit, load ACK to I2CMST (0x02) [2], send I2CAD data, load ACK to I2CMST[2], send I2CDW data, load ACK to I2CMST[2], send I2CDR data, load ACK to I2CMST[2] and then STOP sequentially. For I2C write transfer whose data are more than 3 bytes, user could split the cycles according to I2C protocol. DATA ACK 8 bits Read Format in mapping mode START ID R 8 bits ACK NAK STOP START ID W 8 bits ACK DATA ACK STOP 8 bits Write Format in mapping mode

Datasheet for Telink TC321x DS-TC321x-E7 132 Ver 0.8.1

11.3.4.2 I2C Master Read Transfer

I2C Master has one byte buffer for read data, which is I2CDR (0x06). Read transfer is completed by I2C Master. For example, to implement an I2C read transfer with 1 byte data, which contains START, Slave Address, Read bit, ACK from Slave, 1st byte from Slave, ACK by Master and STOP, user needs to configure I2C Slave address to I2C_ID (0x01) [7:1]. To start I2C read transfer, I2CSCT1 (0x07) is configured to 0xf9 (1111 1001). I2C Master launches START, Slave address, Read bit, load ACK to I2CMST (0x02) [2], load data to I2CDR, reply ACK and then STOP sequentially. For I2C read transfer whose data are more than 1 byte, user could split the cycles according to I2C protocol.

11.3.5 I2C and SPI Usage

I2C hardware and SPI hardware modules in the chip share part of the hardware, as a result, when both hardware interfaces are used, the restrictions listed within this section need to be taken into consideration. I2C and SPI hardware cannot be used as Slave at the same time. The other cases are supported, including:

• I2C Slave and SPI Master can be used at the same time.
• I2C Master and SPI Slave can be used at the same time.
• I2C and SPI can be used as Master at the same time. Please refer to corresponding SDK instructions for details.

11.4 SPI

The SoC embeds SPI (Serial Peripheral interface), which could act as Master mode or Slave mode. SPI is a high-speed, half-duplex and synchronous communication bus requiring 4 bus lines including a chip select (CS) line, a data input (DI) line, a data output (DO) line and a clock (CK) line. The SoC embeds two SPI interfaces: memory SPI (MSPI) and general SPI (GSPI). The MSPI interface is used internally and is not available externally; the corresponding pins are not bonded out on the SoC. Therefore, the GSPI is introduced in this section.

11.4.1 SPI Master Mode

SPI for the SoC supports both Master mode and Slave mode and acts as Slave mode by default. Address 0x09 bit[1] should be set to 1’b1 to enable SPI Master mode. Register SPISP is to configure SPI pin and clock: setting address 0x0a bit[7] to 1 is to enable SPI function mode, and corresponding pins can be used as SPI pins; SPI clock = system clock/((clock speed configured in address 0x0a bit[6:0] +1)*2). Address 0x08 serves as the data register. One reading/writing operation of 0x800020 enables the SPI_CK pin to generate 8 SPI clock cycles. Telink SPI supports four standard working modes: Mode 0 ~ Mode 3. Register SPIMODE (address 0x800023) serves to select one of the four SPI modes:

Datasheet for Telink TC321x DS-TC321x-E7 133 Ver 0.8.1 Table 11-8 SPI Master Mode Address 0x800021 bit[0] is to control the CS line: when the bit is set to 1, the CS level is high; when the bit is cleared, the CS level is low. Address 0x800021 bit[2] is the disabling bit for SPI Master output. When the bit is cleared, MCU writes data into address 0x800020, then the SPI_DO pin outputs the data bit by bit during the 8 clock cycles generated by the SPI_CK pin. When the bit is set to 1’b1, SPI_DO output is disabled. Address 0x800021 bit[3] is the enabling bit for SPI Master reading data function. When the bit is set to 1’b1, MCU reads the data from address 0x800020, then the input data from the SPI_DI pin is shifted into address 0x800020 during the 8 clock cycles generated by the SPI_CK pin. When the bit is cleared, SPI Master reading function is disabled. Address 0x800021[5] is the enabling bit for share mode, i.e. whether SPI_DI and SPI_DO share one common line. User can read address 0x800021 bit[6] to get SPI busy status, i.e. whether the 8 clock pulses have been sent.

11.4.2 SPI Slave Mode

SPI for the SoC acts as Slave mode by default. SPI Slave mode supports DMA. User could access registers of the SoC by SPI interface. It’s noted that system clock of the SoC shall be at least 5x faster than SPI clock for reliable connection. Address 0x800022 should be written with data 0xa5 by the SPI host to activate SPI Slave mode. SPI Salve only supports Mode 0 and Mode 3. Table 11-9 SPI Slave Mode SPI Mode CPOL/CPHA SPIMODE Register (Address 0x0b) Mode 0 CPOL = 0, CPHA = 0 bit[0] = 0, bit[1] = 0 Mode 1 CPOL = 0, CPHA = 1 bit[0] = 0, bit[1] = 1 Mode 2 CPOL = 1, CPHA = 0 bit[0] = 1, bit[1] = 0 Mode 3 CPOL = 1, CPHA = 1 bit[0] = 1, bit[1] = 1 CPOL: Clock Polarity When CPOL = 0, SPI_CLK keeps low level in idle state; When CPOL = 1, SPI_CLK keeps high level in idle state. CPHA: Clock Phase When CPHA = 0, data is sampled at the first edge of clock period When CPHA = 1, data is sampled at the latter edge of clock period SPI Slave Mode CPOL/CPHA Mode 0 CPOL = 0, CPHA = 0 Mode 3 CPOL = 1, CPHA = 1

Datasheet for Telink TC321x DS-TC321x-E7 134 Ver 0.8.1 Address 0x800021[4] is dedicated for SPI Slave mode and indicates address auto increment. SPI write command format and read command format are illustrated in the figure below: Figure 11-11 SPI Write/Read Command Format

11.4.3 I2C and SPI Usage

I2C hardware and SPI hardware modules in the chip share part of the hardware, as a result, when both hardware interfaces are used, certain restrictions apply. See Section 11.3.5 for detailed instructions.

11.4.4 Register Table

The SPI related registers are listed as following, the base address of the following registers is 0x800020. Table 11-10 Register Configuration for SPI Receive data at positive edge of SPI MCLK clock. Send data at negative edge of SPI MCLK clock. Address offset Name Type Description Default Value 0x00 SPIDAT RW [6:0]: shift SPI data access [7]: mst_dat SPI master mode 0x00 SPI Slave Mode CPOL/CPHA Addr(High) Addr(Middle) Addr(Low) CMD(Write) 0x00 Data0 Data....SPIDI SPIDO SPI Write Format SPI Read Format Addr(High) Addr(Middle) Addr(Low) CMD(Read) 0x80 Data1 Data0 Data....Data1 SPIDI SPIDO

Datasheet for Telink TC321x DS-TC321x-E7 135 Ver 0.8.1

11.5 UART

11.5.1 Introduction

The SoC embeds UART (Universal Asynchronous Receiver/Transmitter) to implement full-duplex transmission and reception via UART TX and RX interface. Both TX and RX interface are 4-layer FIFO (First In First Out) interface. The UART module also supports ISO7816 protocol to enable communication with ISO/IEC 7816 integrated circuit card, especially smart card. In this mode, half-duplex communication (transmission or reception) is supported via the shared 7816_TRX interface. UART features include:

• Full-duplex operation
• Automatic flow control via RTS and CTS
• 8-bit UART mode, variable baud rate
• Optional even parity bit checking and generation
• Supports 1, 1.5 and 2 STOP bits
• 8 bytes of transmit/receive FIFOs
• Supports ISO7816 protocol
• Supports DMA function (RX supports DMA Linked List Pointer)
• Up to 3 Mbps baud rate
• 3-channel UART (UART0, UART1, UART2) 0x01 SPICT RW [0]: mst_csn [1]: spi_master_o, enable master mode [2]: r_mode_rd [3]: r_mode_re [4]: r_adr_inc [5]: spi_share_o [6]: cycle_w 0x11 0x02 SPISP RW [6:0]: speed SPI clock speed [7]: spi_host_en_o 0x05 0x03 SPIMODE RW [1:0]: spim, spim clk/oen/dat 0x00 Address offset Name Type Description Default Value

Datasheet for Telink TC321x DS-TC321x-E7 136 Ver 0.8.1

11.5.2 Function Description

11.5.2.1 Hardware Flow Control

Hardware flow control is supported via RTS and CTS. Figure 11-12 UART Communication As shown in the figure above, data to be sent is first written into TX buffer by MCU or DMA, then UART module transmits the data from TX buffer to other device via pin TX. Data to be read from other device is first received via pin RX and sent to RX buffer, then the data is read by MCU or DMA. The TX FIFO/RX FIFO depth is 8 bytes, and they are controlled by read and write pointers. For TX FIFO, the write pointer increments by 1 (0x80009d[6:4]) for every byte of data written. For RX FIFO, the read pointer increments by 1 (0x80009d[2:0]) for every byte of data read. The amount of bytes in TX FIFO/RX FIFO can be read from address 0x80009c. If the amount of bytes reaches 8, it means the FIFO is full. In this case, if TX FIFO continues to write data or RX FIFO continues to receive data, it results in data overwriting. If RX buffer of the SoC UART is close to full, the SoC sends a signal (configurable high or low level) via pin RTS to inform other device that it should stop sending data. Similarly, if the SoC receives a signal from pin CTS, it indicates that RX buffer of other device is close to full and the SoC should stop sending data.

11.5.2.2 Receiver

When RX, the usage instructions of NDMA (No DMA) and DMA are as follows. 1. NDMA Since there is no rxdone interrupt under NDMA: if the length of the received data is random, RX level should be set to 1; if the length of the received data is known, RX level should be set to less than 8 (The value is recommended to be below the flow control threshold-0x800098[3:0]) and an integer multiple of the received length; rx_irq interrupt processing: The amount of data in the RX FIFO is obtained through register rx_buf_cnt (0x80009c[3:0]) and read all data RX FIFO by MCU or DMA; The depth size of the UART FIFO is 8. If the time before and after entering the rx_irq interrupt exceeds the time of receiving 8 bytes, the FIFO pointer may be disturbed, resulting in abnormal received data. User can RTS TX RX CTS MCU or DMA Write Read SoC RX RTS TX CTS Other Device RX buffer TX buffer UART Module TX buffer RX buffer UART Module

Datasheet for Telink TC321x DS-TC321x-E7 137 Ver 0.8.1 determine whether register rx_buf_cnt is greater than 8 as an exception, If this exception occurs, it is recommended to use DMA mode to receive. 2. DMA Advantage: Automatically received by DMA hardware, does not require MCU polling receive. Shortcoming: The maximum receive length of DMA is 4075 bytes, if this length is reached, excess data overwrites the previously received data.

11.5.2.3 Receiver Timeout

Receiver timeout is used to handle when the data received per frame does not reach the threshold. Because data read from the Receiver Buffer Register is a multiple of 4 at a time, The rxdone interrupt is required to process the remaining data below the threshold. Figure 11-13 Timeout Flag Used for Data Transmission The Time out counter inside the UART is updated at the STOP bit, and when receiving data stops, the Timeout counter decreases to 0 and generates a rxdone interrupt. Note: If the register rxtimeout_rts_en (0x80009b[3]) is configured to 1 and the RTS is triggered at the same time, causing the timeout counter to pause. The configurable total timeout is determined via registers uart_rxtimeout_o_l and uart_rxtimeout_o_h[1:0]. Total timeout = uart_rxtimeout_o_l * (uart_rxtimeout_o_h + 1) The uart_rxtimeout_o_l register: The setting is transfer one bytes need cycles base on uart_clk. For example, if transfer one bytes (1 start bit+8 bits data+1 priority bit+2 stop bits) total 12 bits, this register setting should be (register uart_ctrl0[3:0]+1)*12. The uart_rxtimeout_o_h[1:0] register: 2’b00: rx timeout time is r_rxtimeout[7:0] 2’b01: rx timeout time is r_rxtimeout[7:0]*2 2’b10: rx timeout time is r_rxtimeout[7:0]*3 3’b11: rx timeout time is r_rxtimeout[7:0]*4 NOTE:

• The DMA Operation threshold is fixed at 4.
• The NDMA Operation threshold can be configured through the register rx_irq_triq_lev (0x99[3:0]).

Datasheet for Telink TC321x DS-TC321x-E7 138 Ver 0.8.1 The register r_rxtimeout (uart_rxtimeout_o_l and uart_rxtimeout_o_h) is for rx dma to decide the end of each transaction. Supposed the interval between each byte in one transaction is very short. The minimum time supported via function timeout the time required for a single transmission of 1 byte data, The maximum time is the maximum value supported via register r_rxtimeout. But registers uart_rxtimeout_o_l and uart_rxtimeout_o_h[1:0] still expect to follow our recommended approach.

11.5.3 Register Description

UART related registers are listed in tables below. For UART0 related register, the base address is 0x800090, for UART1 related register, the base address is 0x8000c0, for UART2 related register, the base address is 0x800820. Table 11-11 Register Configuration for UART Address offset Name Type Description Default Value 0x00 UART_DATA_BUF0 RW Bit7-0 of Transmitter/Receiver Buffer Register (TX/RX FIFO) 0x00 0x01 UART_DATA_BUF1 RW Bit15-8 of Transmitter/Receiver Buffer Register (TX/RX FIFO) 0x00 0x02 UART_DATA_BUF2 RW Bit23-16 of Transmitter/Receiver Buffer Register (TX/RX FIFO) 0x00 0x03 UART_DATA_BUF3 RW Bit31-24 of Transmitter/Receiver Buffer Register (TX/RX FIFO) 0x00 0x04 UART_CLK_DIV_L RW [7:0]: Least significant byte of the uart_clk_div register 0xff 0x05 UART_CLK_DIV_H RW [6:0]: Most significant byte of the uart_clk_div register uart_sclk = sclk/(uart_clk_div[14:0]+1) [7]:enable clock divider 1:enable 0:disable 0x0f 0x06 UART_CTRL0 RW [3:0]: bpwc_o bwpc, bit width, should be larger than 2 Baud rate = uart_sclk/(bwpc+1) [4]: rx_dma_en [5]: tx_dma_en [6]: mask_rx_irq rx interrupt enable [7]: mask_tx_irq tx interrupt enable 0x0f

Datasheet for Telink TC321x DS-TC321x-E7 139 Ver 0.8.1 0x07 UART_CTRL1 RW [0]: tx_cts_polarity Polarity of CTS 0: Active low (0 - End of transmission) 1: Active high (1 - End of transmission) [1]: tx_cts_enable cts enable, 1: enable, 0: disable [2]: parity_enable When this bit is set, a parity bit is generated in transmitted data before the first STOP bit and the parity bit would be checked for the received data. [3]: parity_polarity Even parity select, 1: old parity; 0: even parity (an even number of logic-1 is in the data and parity bits). [5:4]: stop_sel stop bit 00: 1 bit, 01: 1.5 bits, 1x: 2 bits [6]: ttl_enable TX and RX polarity selection, 0: Non-inverting; 1: Inverting [7]: loopback_o Enable loopback mode, 1: enable; 0: disable 0x0e 0x08 UART_CTRL2 RW [3:0]: rts_triq_lev RTS trig level. Trigger RTS when the RX FIFO reaches the threshold. [4]: rts_polarity Polarity of RTS 0: Active high (0-ready for receiving) 1: Active low (1-ready for receiving) [5]: rts_manul_v rts manual value [6]: rts_manul_m rts manual enable [7]: rts_en RTS enable, 1: enable; 0: disable 0xa5 Address offset Name Type Description Default Value

Datasheet for Telink TC321x DS-TC321x-E7 140 Ver 0.8.1 0x09 UART_CTRL3 RW [3:0]: rx_irq_triq_lev rx_irq_trig level. Trigger rx_buf_irq interrupt when the RX FIFO reaches the threshold. [7:4]: tx_irq_trig_lev tx_irq_trig level. Trigger tx_buf_irq interrupt when the TX FIFO under the threshold. 0x44 0x0a UART_RXTIMEOUT_ O_L RW [7:0]: r_rxtimeout_o[7:0] Least significant byte of the r_rxtimeout_o register: The setting is transfer one bytes need cycles base on uart_clk. For example, if transfer one bytes (1 start bit+8bits data+1 priority bit+2 stop bits) total 12 bits, this register setting should be (bwpc+1)*12. 0xc0 0x0b UART_RXTIMEOUT_ O_H RW [1:0]: r_rxtimeout_o[9:8] Most significant byte of the r_rxtimeout register: 2'b00:rx timeout time is r_rxtimeout[7:0] 2'b01:rx timeout time is r_rxtimeout[7:0]*2 2'b10:rx timeout time is r_rxtimeout[7:0]*3 3'b11: rx timeout time is r_rxtimeout[7:0]*4 r_rxtimeout is for rx dma to decide the end of each transaction. Supposed the interval between each byte in one transaction is very short. [2]: rxdone_rts_en 1'b1:rxdone work on rts; 1'b0:rxdone doesn't work on rts [3]: rxtimeout_rts_en RTS controls timeout stop enabling signal [4]: mask_rxdone_irq Enable rxdone_irq interrupt [5]: p7816_en_o 7816 enable [6]: mask_txdone_irq Enable txdone interrupt [7]: mask_err_irq Enable rx_err interrupt 0x0d Address offset Name Type Description Default Value

Datasheet for Telink TC321x DS-TC321x-E7 141 Ver 0.8.1 0x0c UART_BUFCNT R [3:0]: rx_bufcnt This register is increased when there are incoming received data in the Receiver Buffer Register. When there is read data in the Receiver Buffer Register, this register is decremented. [7:4]: tx_bufcnt This register is decremented when there are outgoing sent data in the Transmitter Buffer Register. When there is write data in the Transmitter Buffer Register, this register is increased. 0x00 0x0d UART_STATUS VOLA TILE [2:0]: rbcnt When there is read data in the Receiver Buffer Register, this register is decremented. [3]: irq_o Total interruption of UART. [6:4]: wbcnt (R) W:[4] write 1 to clear rxdone_irq;W: [6] write 1 to clear rx [7]: rx_err R: rx_err, W: write 1 to clear tx 0x00 Address offset Name Type Description Default Value

Datasheet for Telink TC321x DS-TC321x-E7 142 Ver 0.8.1 0x0e UART_TXRX_STATU S VOLA TILE [0]: txdone When the transmitter ends, the UART controller asserts txdone interrupt. W: write 1 to clear txdone [1]: tx_buf_irq When the TX FIFO under the threshold set by the tx_irq_trig register, the UART controller asserts tx_buf_irq interrupt. W: write 1 to clear TX FIFO pointer, and so on. Note: When TX FIFO is greater than the threshold set by the tx_irq_trig register, the tx_buf_irq interrupt clears automatically. [2]: rxdone (R) [3]: rx_buf_irq When the RX FIFO reaches the threshold set by the rx_irq_trig Register, the UART controller asserts rx_buf_irq interrupt. W: write 1 to clear RX FIFO pointer, rx err, and so on. Note: When RX FIFO is below the threshold set by the rx_irq_trig Register, the rx_buf_irq interrupt clears automatically. [4]: rxdone_irq When the receiver ends (the timeout counter decays to 0), the UART controller asserts rxdone_irq interrupt. W: write 1 to clear rxdone_irq [5]: timeout_en 1'b1:enable rxtimeout; 1'b0 disable rxtimeout [6]: auto_rxclr_en (RW) DMA and NDMA mode: auto clr function switch; 1:enable,0:disable [7]: ndma_rxdone_en (RW) NDMA mode: rxdone(timeout) function switch; 1:enable,0:disable;dma mode must disable 0xe0 0x0f UART_STATE VOLA TILE [2:0]: tstate_i [3]: timeout (R) [7:4]: rstate_i rx state machine,W:[6] write 1 to clear sclk_cnt; W:[7] write 1 to clear txdone 0x00 Address offset Name Type Description Default Value

Datasheet for Telink TC321x DS-TC321x-E7 143 Ver 0.8.1 Addresses 0x00 ~ 0x03 serve to write data into TX buffer or read data from RX buffer. Addresses 0x04 ~ 0x05 serve to configure UART clock. Address 0x06 serves to set baud rate (bit[3:0]), enable RX/TX DMA mode (bit[4:5]), and enable RX/TX interrupt (bit[6:7]). Address 0x07 mainly serves to configure CTS. Bit[1] should be set to 1’b1 to enable CTS. Bit[0] serves to configure CTS signal level. Bit[2:3] serve to enable parity bit and select even/odd parity. Bit[5:4] serve to select 1/1.5/2 bits for stop bit. Bit[6] serves to configure whether RX/TX level should be inverted. Address 0x08 serves to configure RTS. Bit[7] and Bit[3:0] serve to enable RTS and configure RTS signal level. Address 0x09 serves to configure the number of bytes in RX/TX buffer to trigger interrupt. The number of bytes in RX/TX buffer can be read from address 0x0c.

Datasheet for Telink TC321x DS-TC321x-E7 144 Ver 0.8.1

12 IR_Learn

12.1 Overview

The function of IR_LEARN module is mainly counting, there is an internal 24-bit counter which can count the pulse width duration (height) and cycle duration of the IR signal carrier.

12.2 Working Principle

The source of the IR signal is selected through register IR_CTRL1[0], when IR_CTRL1[0] is 0, the input of GPIO is selected as the IR signal, when IR_CTRL1[0] is 1, the IR output signal of ANALOG is selected as the IR signal. After register IR_CTRL0[0] is set to 1, the condition that triggers the 24-bit counter to start counting is determined according to the configuration of register IR_CTRL1[6:5]. When register IR_CTRL1[6:5] is configured to 0, the 24-bit counter starts counting when the first rising edge of the IR signal arrives.

• When the level of IR signal goes from high to low, the current counter value is stored in high register as the carrier's high, and if register INT_MASK[0] is set to 1 before that, a high interrupt is generated, and the status of the high interrupt can be read by reading register INT_STAT[0];
• When the level of IR signal is from low to high, the current counter value is stored in cycle register as the carrier's cycle, and the counter is reset to 1. If register INT_MASK[1] is set to 1 before that, a cycle interrupt is generated, and the status of the cycle interrupt can be read by reading register INT_STAT[1];
• When the IR signal is low and the counter value reaches the preset timeout threshold, the current counter value is stored in cycle register as the cycle of the carrier. If register INT_MASK[2] is set to 1 before this, a timeout interrupt is generated and the status of the timeout interrupt can be read by reading register INT_STAT[2]. The timeout interrupt is generated by reading INT_STAT[2].

12.3 Working Mode

The following is an example of bootstrap code learning for the NEC protocol:

Datasheet for Telink TC321x DS-TC321x-E7 145 Ver 0.8.1 Figure 12-1 Bootstrap Code Learning for NEC Protocol The detailed learning procedure is as follows. 1. At the rising edge of the first pulse, the module starts learning and the counter starts counting. At each subsequent rising edge moment, the value of cycle is recorded; 2. Assuming the carrier frequency Fc = 38KHz for the NEC protocol, the carrier cycle Tc is approximately 26316ns; Assuming PCLK = 24MHz, Tclk is approximately 41ns; If cycle * Tclk == Tc, it can be determined that the current cycle is a carrier cycle. If cycle * Tclk! = Tc, then you can determine that the current cycle is a non-carrier cycle. 3. As shown in the figure, cycle0, cycle1, cycle2... cyclen are all carrier cycles; because cycle n+1 is much larger than the value of cycle0~cyclen, it is a non-carrier cycle. If the time sum of all carrier cycles (cycle0, cycle1, cycle2... cyclen) time sum is about equal to 9ms and when cycle n+1 is about equal to 4.5ms, it can be judged that the current wave is the bootstrap code of NEC protocol; 4. The learning of data codes 0 and 1 of the NEC protocol is similar; 5. When the value of the off-carrier cycle is equal to the threshold of the preset timeout, the signal number composed of this off-carrier cycle can be judged as the end code.

12.4 Register Description

The IR_Learn related registers are listed in the following table. The base address for the following IR_Learn related registers is 0x8000a0. Table 12-1 IR_LEARN Related Registers Address Offset Name Type Description Default Value 0x00 IR_CTRL0 R/W [0]: en 1: enable module 0: disable module 0x00 Bootstrap code: 9ms carrier + 4.5ms low level Start to learn Record cycle 0 9ms Record cycle 1 Record cycle 2 Record cycle n Record cycle n+1 Carrier Frequency (Fc): 38KHz Carrier Cycle (Tc): 1/38 ms, about 26316ns 4.5ms

Datasheet for Telink TC321x DS-TC321x-E7 146 Ver 0.8.1 0x01 IR_CTRL1 R/W [0]: ir_sel 1: select analog as ir input signal; 0: select pads as ir input signal. [6:5]: ir_mode 2'b00: After enabling the module, the counter waits for the first rising edge to enter the HIGH state and start counting. 2'b01: After enabling the module, the counter immediately enters the HIGH state and starts counting. 2'b10: After enabling the module, the counter waits for the first falling edge to enter the LOW state and start counting. 2'b11: After enabling the module, the counter immediately enters the LOW state and starts counting. 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TC321x DS-TC321x-E7 147 Ver 0.8.1 0x02 IR_CTRL2 R/W [3:0]: ir_soft_sel ir_soft_sel == 0, sft = 0x2; ir_soft_sel == 1, sft = 0x8; ir_soft_sel == 2, sft = 0x20; ir_soft_sel == 3, sft = 0x80; ir_soft_sel == 4, sft = 0x200; ir_soft_sel == 5, sft = 0x800; ir_soft_sel == 6, sft = 0x2000; ir_soft_sel == 7, sft = 0x8000; ir_soft_sel == 8, sft = 0x20000; ir_soft_sel == 9, sft = 0x80000; ir_soft_sel == 10, sft = 0x200000; other, sft = 0x800000. [7:4]: ir_timeout_sel ir_timeout_sel == 0, timeout = 0x3; ir_timeout_sel == 1, timeout = 0xf; ir_timeout_sel == 2, timeout = 0x3f; ir_timeout_sel == 3, timeout = 0xff; ir_timeout_sel == 4, timeout = 0x3ff; ir_timeout_sel == 5, timeout = 0xfff; ir_timeout_sel == 6, timeout = 0x3fff; ir_timeout_sel == 7, timeout = 0xffff; ir_timeout_sel == 8, timeout = 0x3ffff; ir_timeout_sel == 9, timeout = 0xfffff; ir_timeout_sel == 10, timeout = 0x3fffff; other, timeout = 0xffffff. 0xb0 0x03 IR_CTRL3 R/W [7]: not_carry_clr R: not_carry status, (cnt==sft) W1C: clear not_carry status 0x00 0x04 INT_MASK R/W [0]: high_irq enable [1]: cycle_irq enable [2]: timeout_irq enable 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TC321x DS-TC321x-E7 148 Ver 0.8.1 0x05 INT_STAT Volatile [0]: high_irq, write 1 to clear high_irq [1]: cycle_irq, write 1 to clear cycle_irq [2]: timeout_irq, write 1 to clear timeout_irq 0x00 0x06 CNT_1 R cnt[15:8] 0x00 0x07 CNT_2 R cnt[23:16] 0x00 0x08 HIGH_0 R high[7:0] 0x00 0x09 HIGH_1 R high[15:8] 0x00 0x0a HIGH_2 R high[23:16] 0x00 0x0c CYCLE_0 R cycle[7:0] 0x00 0x0d CYCLE_1 R cycle[15:8] 0x00 0x0e CYCLE_2 R cycle[23:16] 0x00 Address Offset Name Type Description Default Value

Datasheet for Telink TC321x DS-TC32x-E7 149 Ver 0.8.1

13 Keyscan

The SoC supports telink keyscan for detecting 8 rows x 16 columns matrix keyboards, which is essentially a row-column scan. Since the column scan is increased 3 at a time, it supports 8 x 18 keyboards. Telink keyscan supports hardware debounce function.

13.1 Keyscan Principle

Telink keyscan selects 32 I/O ports to control the reading of keys. It configures 8 I/O lines as row lines and 16 I/O lines as column lines, creating a matrix of 8x16 keys. Each key is positioned at the intersection of a row and column. The keyscan performs a row-column scan to identify the specific key location and determine its value. Figure 13-1 Keyscan Schematic The chip hardware assigns a number to each I/O port that can be reused for the Keyscan functionality. Below is the pin assignment table: Table 13-1 Pad Number for Keyscan Pad Number Pad Number Pad Number Pad Number PD[0] PD_KS_0 PC[0] PC_KS_0 PB[0] PB_KS_0 PA[0] PA_KS_0 PD[1] PD_KS_1 PC[1] PC_KS_1 PB[1] PB_KS_1 PA[1] PA_KS_1 PD[2] PD_KS_2 PC[2] PC_KS_2 PB[2] PB_KS_2 PA[2] PA_KS_2 PD[3] PD_KS_3 PC[3] PD_KS_3 PB[3] PB_KS_3 - PA_KS_3 S0 S1 S2 S3 S12 S13 S14 S15 S0 S1 S2 S3 S12 S13 S14 S15 S0 S1 S2 S3 S12 S13 S14 S15 S0 S1 S2 S3 S12 S13 S14 S15 S0 S1 S2 S3 S12 S13 S14 S15 S0 S1 S2 S3 S12 S13 S14 S15 S0 S1 S2 S3 S12 S13 S14 S15 S0 S1 S2 S3 S12 S13 S14 S15 ROW0 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 Column0 Column1 Column2 Column3 Column12 Column13 Column14 Column15

Datasheet for Telink TC321x DS-TC32x-E7 150 Ver 0.8.1 Set address 0x800804 ~ 0x800808 (KS_ROW_SEL) to select 8 pins as rows, then set address 0x800800 ~ 0x800803 (KS_COL_MSK) to select 16 pins from the remaining pins as columns. The keyscan scans keyboards via row-column selection. After scanning, the row-column number is recorded in the KS_KEY buffer, the corresponding row-column number is read in the end_flag interrupt to determine the key.

13.2 Hardware Debounce

Telink keyscan implements the hardware debounce function. The dynamic range of debounce supports 8ms/ 12ms/16ms/20ms/24ms multi-block debounce cycle. The keyscan compares the data of adjacent debounce cycles, and only deposit it into the FIFO for reporting if they are consistent.

13.3 Suspend/Wakeup

The keyscan is able to wake up the system following the debounce cycle. The Keyscan module works on a crystal clock or 32 kHz RC oscillator, so it can work when it is asleep. The interrupts are reported following the debounce cycle (8ms/12ms/16ms), or application layer readouts at regular intervals. The purpose of this is to reduce the time spent on the temporary UI and to reduce power consumption.

13.4 FIFO Depth

FIFO is expected to hold 31 keys. If less than 8 keys are expected per debounce cycle, it is necessary to remove all keys in four debounce cycles.

13.5 Register Table

The keyscan related registers are listed in the following table. The base address for the following keyscan related registers is 0x800800. PD[4] PD_KS_4 PC[4] PC_KS_4 PB[4] PB_KS_4 PA[4] PA_KS_4 PD[5] PD_KS_5 PC[5] PC_KS_5 PB[5] PB_KS_5 PA[5] PA_KS_5 PD[6] PD_KS_6 PC[6] PC_KS_6 PB[6] PB_KS_6 PA[6] PA_KS_6 PD[7] PD_KS_7 PC[7] PC_KS_7 PB[7] PB_KS_7 PA[7] PA_KS_7 Pad Number Pad Number Pad Number Pad Number NOTE:

• PD_KS0[0] is used for rows by default, cannot be used for columns.
• For column, use PB_KS[4:0], PC_KS[7:0], PD_KS[7:1] as much as possible.
• Row number is fixed to 8, if less than 8 rows are to be used, make the unused pins floating.

Datasheet for Telink TC321x DS-TC32x-E7 151 Ver 0.8.1 Table 13-2 Register Table for Keyscan Address offset Name Type Description Default Value 0x00 KS_COL_MSK0 RW [7:0]: KS_COL_MSK0 Keyscan column mask for PD_KS[7:0] 0x00 0x01 KS_COL_MSK1 RW [7:0]: KS_COL_MSK1 Keyscan column mask for PC_KS[7:0] 0x00 0x02 KS_COL_MSK2 RW [7:0]: KS_COL_MSK2 Keyscan column mask for PB_KS[7:0] 0x00 0x03 KS_COL_MSK3 RW [7:0]: KS_COL_MSK3 Keyscan column mask for PA_KS[7:0] 0x00 0x04 KS_ROW_SEL0 RW [4:0]: KS_ROW_SEL0 keyscan row select for row0 [7:5]: KS_ROW_SEL1_L keyscan row select for row1[2:0] 0x00 0x05 KS_ROW_SEL1 RW [1:0]: KS_ROW_SEL1_H keyscan row select for row1[4:3] [6:2]: KS_ROW_SEL2 keyscan row select for row2 [7]: KS_ROW_SEL3_L keyscan row select for row3[0] 0x00 0x06 KS_ROW_SEL2 RW [3:0]: KS_ROW_SEL3_H keyscan row select for row3[4:1] [7:4]: KS_ROW_SEL4_L keyscan row select for row4[3:0] 0x00 0x07 KS_ROW_SEL3 RW [0]: KS_ROW_SEL4_H keyscan row select for row4[4] [5:1]: KS_ROW_SEL5 keyscan row select for row5 [7:6]: KS_ROW_SEL6_L keyscan row select for row6[1:0] 0x00

Datasheet for Telink TC321x DS-TC32x-E7 152 Ver 0.8.1 0x08 KS_ROW_SEL4 RW [2:0]: KS_ROW_SEL6_H keyscan row select for row6[4:2] [7:3]: KS_ROW_SEL7 keyscan row select for row7 0x00 0x09 KS_END_FLG RW [7:0]: END_FLG Keyscan frame end flag 0xff 0x0a KS_EN RW KS_EN [0]: KS_EN, Keyscan enable [1]: CLK_EN, Keyscan 32k Hz clock enable [2]: KS_IE, Keyscan interrupt enable [3]: IN_INV, Keyscan input invert [4]: OUT_INV, Keyscan output invert [5]: MOD, Keyscan scan mode select, 1’b0 for mode 0, 1’b1 for mode 1 [6]: RESET, Keyscan manually reset [7]: tri_chk_dis, Keyscan tripple check disable 0x07 0x0b KS_FRM_NUM RW [4:0]: FRM_NUM Keyscan empty frame counter number [7:5]: debounce_period debounce period 2->8ms, 3->12ms, 4->16ms, 5- >20ms 0x41 0x0c KS_IRQ R [4:0]: RPTR Keyscan read pointer for key buffer [7]: FRM_END Keyscan interrupt 0x00 0x0d KS_RPTR R [4:0]: R_WPTR Keyscan latched write pointer when frame end [6]: KEY_DET_CAP Keyscan cap key detect when in any state [7]: STATE Keyscan state, 1’b0 for IDLE, 1’b1 for SCAN 0x00 Address offset Name Type Description Default Value

Datasheet for Telink TC321x DS-TC32x-E7 153 Ver 0.8.1 0x0e KS_WPTR R [4:0]: WPTR Keyscan write pointer for key buffer [5]: NO_KEY Keyscan no key detect when in SCAN state [6]: KEY_DET Keyscan key detect when in IDLE state [7]: CNT_EN Keyscan internal counter128 count enable 0x00 0x0f KS_GATED R [2:0]: CNT_H Keyscan counter128[6:4] [3]: Reserved [4]: GATED_CLR Keyscan 32k Hz clock gated clear [5]: GAYED Keyscan 32k Hz clock gated [6]: CNT16_EN Keyscan internal counter16 count enable [7]: KS_WAKE_UP Keyscan wake up status; W1C?clr wakeup 0x00 0x10 KS_KEY Volatile [7:0]: KS_KEY Keyscan key value 0xff 0x11 KS_LPTR R [4:0]: LPTR, Keyscan loop pointer [7:5]: Reserved 0x00 0x12 KS_CNT128 R KS_CNT128 [6:0]: CNT, Keyscan counter128 count value [7]: Reserved 0x00 0x13 KS_CNT16 R [3:0]: CNT_16 Keyscan counter16 count value [6:4]: ROW_NUM Keyscan latched row number [7]: Reserved 0x00 Address offset Name Type Description Default Value

Datasheet for Telink TC321x DS-TC321x-E7 154 Ver 0.8.1

14 Quadrature Decoder

The SoC embeds one quadrature decoder (QDEC) which is designed mainly for applications such as wheel. The QDEC implements debounce function to filter out jitter on the two phase inputs, and generates smooth square waves for the two phase.

14.1 Input Pin Selection

The QDEC supports two phase input; each input is selectable from the 8 pins of PortA, PortB, PortC and PortD via setting address 0x8000d2[2:0] (for channel a)/0x8000d3[2:0] (for channel b). Table 14-1 Input Pin Selection

14.2 Common Mode and Double Accuracy Mode

The QDEC embeds an internal hardware counter, which is not connected with bus. Address 0x8000d7[0] serves to select common mode or double accuracy mode. For each wheel rolling step, two pulse edges (rising edge or falling edge) are generated. If address 0x8000d7[0] is cleared to select common mode, the QDEC Counter value (real time counting value) is increased/decreased by 1 only when the same rising/falling edges are detected from the two phase signals. Address 0xd2[2:0]/0xd3[2:0] Pin

0 PA[2]

1 PA[3]

2 PB[6]

3 PB[7]

4 PC[2]

5 PC[3]

6 PD[6]

7 PD[7]

NOTE: To use corresponding IO as QDEC input pin, it's needed first to enable GPIO function, enable "IE" (1) and disable "OEN" (1) for this IO.

Datasheet for Telink TC321x DS-TC321x-E7 155 Ver 0.8.1 Figure 14-1 Common Mode If address 0x8000d7[0] is set to 1’b1 to select double accuracy mode, the QDEC Counter value (real time counting value) is increased/decreased by 1 on each rising/falling edge of the two phase signals; the COUNT0 is increased/decreased by 2 for one wheel rolling. One wheel rolling COUNT0 value increased by 1 Another wheel rolling COUNT0 value increased by 1 One wheel rolling COUNT0 value decreased by 1 Another wheel rolling COUNT0 value decreased by 1

Datasheet for Telink TC321x DS-TC321x-E7 156 Ver 0.8.1 Figure 14-2 Double Accuracy Mode

14.3 Read Real Time Counting Value

Neither can Hardware Counter value be read directly via software, nor can the counting value in address 0x8000d0 be updated automatically. To read real time counting value, first write address 0x8000d8[0] with 1’b1 to load Hardware Counter data into the QDEC_COUNT register, then read address 0x8000d0. One wheel rolling COUNT0 value increased by 1 Another wheel rolling COUNT0 value increased by 1 COUNT0 value increased by 1 COUNT0 value increased by 1 One wheel rolling COUNT0 value decreased by 1 Another wheel rolling COUNT0 value decreased by 1 COUNT0 value decreased by 1 COUNT0 value decreased by 1

Datasheet for Telink TC321x DS-TC321x-E7 157 Ver 0.8.1 Figure 14-3 Read Real Time Counting Value

14.4 QDEC Reset

Address 0x800060[5] serves to reset the QDEC. The QDEC Counter value is cleared to zero.

14.5 Other Configuration

The QDEC supports hardware debouncing. Address 0x8000d1[2:0] serves to set filtering window duration. All jitter with period less than the value is filtered out and thus does not trigger count change. Address 0x8000d1[4] serves to set input signal initial polarity. Address 0x8000d1[5] serves to enable shuttle mode. Shuttle mode allows non-overlapping two phase signals as shown in the following figure. Figure 14-4 Shuttle Mode Hardware Counter Digital Register QDEC_COUNT (address 0xd0) 1) Write “1” to address 0xd8[0] to load data QDEC 2) Read

Datasheet for Telink TC321x DS-TC321x-E7 158 Ver 0.8.1

14.6 Timing Sequence

Figure 14-5 Timing Sequence Chart Table 14-2 Timing QDEC module works based on 32 kHz clock to ensure it can work in suspend mode. QDEC module supports debouncing function, and any signal with width lower than the threshold (i.e. “2^(n+1) *clk_32kHz *3 (n=0x8000d1[2:0])) is regarded as jitter. Therefore, effective signals input from Channel A and B should contain high/low level with width Thpw/Tlpw more than the threshold. The 2^n *clk_32kHz clock is used to synchronize input signal of QDEC module, so the interval between two adjacent rising/falling edges from Channel A and B, which are marked as Triw and Tfiw, should exceed “2^(n+1) *clk_32kHz”. Only when the timing requirements above are met, can QDEC module recognize wheel rolling times correctly. Time Interval Min Value Thpw (High-level pulse width) 2^(n+1) *clk_32kHz *3 (n=0xd1[2:0]) Tlpw (Low-level pulse width) 2^(n+1) *clk_32kHz *3 (n=0xd1[2:0]) Triw (Interval width between two rising edges) 2^(n+1) *clk_32kHz (n=0xd1[2:0]) Tfiw (Interval width between two falling edges) 2^(n+1) *clk_32kHz (n=0xd1[2:0]) One wheel rolling Another wheel rolling Thpw Tlpw A channel B channel One wheel rolling Another wheel rolling Triw Tfiw A channel B channel

Datasheet for Telink TC321x DS-TC321x-E7 159 Ver 0.8.1

14.7 Register Table

The QDEC related registers are listed in the following table. The base address for the following registers is 0x8000d0. Table 14-3 Register Table for QDEC Address offset Name Type Description Default Value 0x00 QDEC_COUNT0 R QDEC Counting value (read to clear): Pulse edge number 0x00 0x01 QDEC_DBNTIME RW [5]: shuttle mode 1 - enable shuttle mode [4]: pola, input signal pola 0 - no signal is low, 1 - no signal is high [2:0]: filter time (can filter 2^n *clk_32k*2 width deglitch) 0x00 0x02 QDEC_CHANNEL_ RW [2:0]: QDEC input pin select for channel A, choose 1 of 8 pins for input channel A 0x00 0x03 QDEC_CHANNEL_ RW [2:0]: QDEC input pin select for channel B, choose 1 of 8 pins for input channel B 0x01 0x06 QDEC_READ R [0]: RSVD 0x00 0x07 QDEC_DOUBLE0 RW [0]: Enable double accuracy mode 0x01 0x08 QDEC_COUNT0_R ELOAD RW [0]: write 1 to load data When load completes it is 0. 0x00

Datasheet for Telink TC321x DS-TC321x-E7 160 Ver 0.8.1

15 PWM

The SoC supports up to 6-channel PWM (Pulse-Width-Modulation) output. Each PWM#n (n = 0 ~ 5) has its corresponding inverted output at PWM#n_N pin.

15.1 Enable PWM

Register PWM_EN (address 0x800780)[5:1] and PWM_EN0 (address 0x800781)[0] serves to enable PWM5 ~ PWM0 respectively via writing “1” for the corresponding bits.

15.2 Set PWM Clock

PWM clock derives from system clock. Register PWM_CLKDIV (address 0x800782) serves to set the frequency dividing factor for PWM clock. Formula below applies: FPWM = FSystem clock / (PWM_CLKDIV+1)

15.3 PWM Waveform, Polarity and Output Inversion

Each PWM channel has independent counter and 2 status including “Count” and “Remaining”. Count and Remaining status form a signal frame.

15.3.1 Waveform of Signal Frame

When PWM#n is enabled, first PWM#n enters Count status and outputs High level signal by default. When PWM#n counter reaches cycles set in register PWM_TCMP#n (address 0x800794 ~ 0x800795, 0x800798 ~ 0x800799, 0x80079c ~ 0x80079d, 0x8007a0 ~ 0x8007a1, 0x8007a4 ~ 0x8007a5, 0x8007a8 ~ 0x8007a9) / PWM_TCMP0_SHADOW (0x8007c4 ~ 0x8007c5), PWM#n enters Remaining status and outputs Low level till PWM#n cycle time configured in register PWM_TMAX#n (address 0x800796 ~ 0x800797, 0x80079a ~ 0x80079b, 0x80079e ~ 0x80079f, 0x8007a2 ~ 0x8007a3, 0x8007a6 ~ 0x8007a7, 0x8007aa ~ 0x8007ab) / PWM_TMAX0_SHADOW (0x8007c6 ~ 0x8007c7) expires. Figure 15-1 A Signal Frame An interruption is generated at the end of each signal frame if enabled via register PWM_MASK (address 0x8007b0[2:7]). CMP MAX Remaining statusCount status

Datasheet for Telink TC321x DS-TC321x-E7 161 Ver 0.8.1

15.3.2 Invert PWM Output

PWM#n and PWM#n_N output could be inverted independently via register PWM_CC0 (address 0x800784) and PWM_CC1 (address 0x800785). When the inversion bit is enabled, waveform of the corresponding PWM channel is inverted completely.

15.3.3 Polarity for Signal Frame

By default, PWM#n outputs High level at Count status and Low level at Remaining status. When the corresponding polarity bit is enabled via register PWM_CC2 (address 0x800786[5:0]), PWM#n outputs Low level at Count status and High level at Remaining status. Figure 15-2 PWM Output Waveform Chart

15.4 PWM Modes

15.4.1 Select PWM Modes

PWM0 supports five modes, including Continuous mode (normal mode, default), Counting mode, IR mode, IR FIFO mode, IR DMA FIFO mode. PWM1 ~ PWM5 only support Continuous mode. Register PWM_MODE (address 0x800783) serves to select PWM0 mode.

15.4.2 Continuous Mode

PWM0 ~ PWM5 all support Continuous mode. In this mode, PWM#n continuously sends out signal frames. PWM#n should be disabled via address 0x800780/0x800781 to stop it; when stopped, the PWM output turns low immediately. During Continuous mode, waveform could be changed freely via PWM_TCMP#n and PWM_TMAX#n. New configuration for PWM_TCMP#n and PWM_TMAX#n takes effect in the next signal frame. PWM#n Signal Frame ( PWM_TMAXn cycles) PWM#n (Invert = High) PWM Clock PWM_INV#n PWM_INV#n (Invert = High) Count Remaining PWM#n (Polarity = High) Count (PWM_TCMPn cycles) Remaining

Datasheet for Telink TC321x DS-TC321x-E7 162 Ver 0.8.1 After each signal frame is finished, corresponding PWM cycle done interrupt flag bit (0x8007b1[2:7]) is automatically set to 1’b1. If the interrupt is enabled by setting PWM_MASK0 (address 0x8007b0[2:7]) as 1’b1, a frame interruption is generated. User needs to write 1’b1 to the flag bit to manually clear it. Figure 15-3 Continuous Mode

15.4.3 Counting Mode

Only PWM0 supports Counting mode. Address 0x800783[3:0] should be set as 4’b0001 to select PWM0 counting mode. In this mode, PWM0 sends out specified number of signal frames which is defined as a pulse group. The number is configured via register PWM_PNUM0 (address 0x8007ac ~ 0x8007ad). After each signal frame is finished, PWM0 cycle done interrupt flag bit (0x8007b1[2]) is automatically set to 1’b1. If the interrupt is enabled by setting PWM_MASK0 (address 0x8007b0[2]) as 1’b1, a frame interruption is generated. User needs to write 1’b1 to the flag bit to manually clear it. After a pulse group is finished, PWM0 is disabled automatically, and PWM0 Pnum interrupt flag bit (0x8007b1[0]) is automatically set to 1’b1. If the interrupt is enabled by setting PWM_MASK0 (address 0x8007b0[0]) as 1’b1, a Pnum interruption is generated. User needs to write 1’b1 to the flag bit to manually clear it. Figure 15-4 Counting Mode (n=0) Counting mode also serves to stop IR mode gracefully. Refer to Section 15.4.4 for details.

15.4.4 IR Mode

Only PWM0 supports IR mode. Address 0x800783[3:0] should be set as 4’b0011 to select PWM0 IR mode. In this mode, specified number of frames is defined as one pulse group. In contrast to Counting mode where PWM0 stops after first pulse group is finished, PWM0 constantly sends pulse groups in IR mode. Continuous mode Int Int Int Int Int Int Signal Frame Signal Frame Signal Frame Signal Frame Signal Frame Signal Frame Int Int Int Counting Mode Pnum_int Counting Mode with Invert = High PWM_EN[n] will be cleared after sending PNUM pulses Pulse group (PWM#n_PNUM pulses) Signal Frame Signal Frame Signal Frame

Datasheet for Telink TC321x DS-TC321x-E7 163 Ver 0.8.1 During IR mode, PWM0 output waveform could also be changed freely via WM_TCMP0, PWM_TMAX0 and PWM_PNUM0. New configuration for PWM_TCMP0, PWM_TMAX0 and PWM_PNUM0 takes effect in the next pulse group. To stop IR mode and complete current pulse group, user can switch PWM0 from IR mode to Counting mode so that PWM0 stops after current pulse group is finished. If PWM0 is disabled directly via PWM_EN0 (0x800781[0]), PWM0 output turns Low immediately despite of current pulse group. After each signal frame/pulse group is finished, PWM0 cycle done interrupt flag bit (0x8007b1[2])/PWM0 Pnum interrupt flag bit (0x8007b1[0]) is automatically set to 1’b1. A frame interruption/Pnum interruption is generated (if enabled by setting address 0x8007b0[2]/0x8007b0[0] as 1’b1). Figure 15-5 IR Mode (n=0)

15.4.5 IR FIFO Mode

IR FIFO mode is designed to allow IR transmission of long code patterns without the continued intervention of MCU, and it is designed as a selectable working mode on PWM0. The IR carrier frequency is divided down from the system clock and can be configured as any normal IR frequencies, e.g. 36 kHz, 38 kHz, 40 kHz, or 56 kHz. Only PWM0 supports IR FIFO mode. Address 0x800783[3:0] should be set as 4’b0111 to select PWM0 IR FIFO mode. An element (“FIFO CFG Data”) is defined as basic unit of IR waveform, and written into FIFO. This element consists of 16 bits, including:

• bit[13:0] defines PWM pulse number of current group.
• bit[14] determines duty cycle and period for current PWM pulse group. º 0: use configuration of TCMP0 and TMAX0 in 0x800794 ~ 0x800797; º 1: use configuration of TCMP0_SHADOW and TMAX0_SHADOW in 0x8007c4 ~ 0x8007c7.
• bit[15] determines whether current PWM pulse group is used as carrier, i.e. whether PWM outputs pulse (1) or low level (0). User should use FIFO_DATA_ENTRY in 0x8007c8 ~ 0x8007cb to write the 16-bit “FIFO CFG Data” into FIFO by byte or half word or word.
• To write by byte, user should successively write 0x8007c8, 0x8007c9, 0x8007ca and 0x8007cb.
• To write by half word, user should successively write 0x8007c8 and 0x8007ca.
• To write by word, user should write 0x8007c8. IR Mode PWM#n_PNUM pulses (1st pulse group) PWM#n_PNUM pulses (2nd pulse group) Int Int Int Int Pnum_int Int Int Int Int Int IntPnum_int PWM_TCMP/TMAX/PNUM set in this pulse group will apply in next pulse group PWM_TCMP/TMAX/PNUM set in this pulse group will apply in next pulse group …… Nth pulse group

Datasheet for Telink TC321x DS-TC321x-E7 164 Ver 0.8.1 FIFO depth is 8 bytes. User can read the register FIFO_SR in 0x8007cd to view FIFO empty/full status and check FIFO data number. Figure 15-6 IR Format Examples When “FIFO CFG Data” is configured in FIFO and PWM0 is enabled via PWM_EN0 (address 0x800781[0]), the configured waveforms are output from PWM0 in sequence. As long as FIFO doesn’t overflow, user can continue to add waveforms during IR waveforms sending process, and long IR code that exceeds the FIFO depth can be implemented this way. After all waveforms are sent, FIFO becomes empty, PWM0 is disabled automatically. The FIFO_CLR register (address 0x8007ce[0]) serves to clear data in FIFO. Writing 1’b1 to this register clears all data in the FIFO. Note that the FIFO can only be cleared when not in active transmission.

15.4.6 IR DMA FIFO Mode

IR DMA FIFO mode is designed to allow IR transmission of long code patterns without occupation of MCU, and it is designed as a selectable working mode on PWM0. The IR carrier frequency is divided down from the system clock and can be configured as any normal IR frequencies, e.g. 36 kHz, 38 kHz, 40 kHz, or 56 kHz. Only PWM0 supports IR DMA FIFO mode. Address 0x800783[3:0] should be set as 4’b1111 to select PWM0 IR DMA FIFO mode. This mode is similar to IR FIFO mode, except that “FIFO CFG Data” is written into FIFO by DMA instead of MCU. User should write the configuration of “FIFO CFG Data” into RAM, and then enable DMA channel 5. DMA automatically writes the configuration into FIFO. Int Signal Frame TCMP0 TMAX0 Current FIFO CFG Data bit[13:0]* TMAX0 Current FIFO CFG Data bit[15] = 1 Next FIFO CFG Data bit[15] = 0 Next FIFO CFG Data bit[13:0]* TMAX0 Current FIFO CFG Data bit[14] = 0 Next FIFO CFG Data bit[14] = 0 Int Signal Frame TCMP0 TMAX0 Current FIFO CFG Data bit[13:0]* TMAX0 Current FIFO CFG Data bit[15] = 1 Next FIFO CFG Data bit[15] = 1 Signal Frame TMAX0_SHADOW Next FIFO CFG Data bit[13:0]* TMAX0_SHADOW TCMP0_ SHADOW Current FIFO CFG Data bit[14] = 0 Next FIFO CFG Data bit[14] = 1

Datasheet for Telink TC321x DS-TC321x-E7 165 Ver 0.8.1 Example 1: Suppose Mark carrier (pulse) frequency1 (F1) = 40 kHz, duty cycle 1/3 Mark carrier (pulse) frequency2 (F2) = 50 kHz, duty cycle 1/2 Space carrier (low level) frequency (F3) = 40 kHz If user wants to make PWM send waveforms in following format (PWM CLK = 24 MHz):

• Burst(20[F1]), i.e. 20 F1 pulses
• Burst(30[F2]),
• Burst(50[F1]) ,
• Burst(50[F2]),
• Burst(20[F1],10[F3]),
• Burst(30[F2],10[F3]) Step 1 Set carrier F1 frequency as 40 kHz, set duty cycle as 1/3. º Set PWM_TMAX0 as 0x258 (i.e. 24 MHz/40 kHz = 600 = 0x258). º Since duty cycle is 1/3, set PWM_TCMP0 as 0xc8 (i.e. 600/3 = 200 = 0xc8). º Set carrier F2 frequency as 50 kHz, set duty cycle as 1/2. º Set PWM_TMAX0_SHADOW as 0x1e0 (i.e. 24 MHz/50 kHz = 480 = 0x1e0). º Since duty cycle is 1/2, set PWM_TCMP0_SHADOW as 0xf0 (i.e. 480/2 = 240 = 0xf0). Step 2 Generate “FIFO CFG Data” sequence. Step 3 Write “FIFO CFG Data” into SRAM in DMA format. º DMA SOURCE ADDRESS+0x00: 0x0000_0010 (DMA transfer-length: 16 bytes) º DMA SOURCE ADDRESS+0x04: 0xc01e_8014 (little endian) º DMA SOURCE ADDRESS+0x08: 0xc032_8032 º DMA SOURCE ADDRESS+0x0c: 0x000a_8014 º DMA SOURCE ADDRESS+0x10: 0x000a_c01e Step 4 Enable DMA channel 5 to send PWM waveforms. º Write 1’b1 to address 0x524[5] to enable DMA channel 5. After all waveforms are sent, FIFO becomes empty, PWM0 is disabled automatically (address 0x800781[0] is automatically cleared). The FIFO mode stop interrupt flag bit (address 0x8007b3[0]) is automatically set as NOTE: In this mode, when DMA channel 5 is enabled, PWM automatically outputs configured waveform, with- out the need to manually enable PWM0 via 0x781[0] (i.e. 0x781[0] is set as 1’b1 automatically).

Datasheet for Telink TC321x DS-TC321x-E7 166 Ver 0.8.1 1’b1. If the interrupt is enabled by setting PWM_MASK1 (address 0x8007b2[0]) as 1’b1, a FIFO mode stop interrupt is generated. User needs to write 1’b1 to the flag bit to manually clear it. Example 2: Suppose carrier frequency is 38 kHz, system clock frequency is 24 MHz, duty cycle is 1/3, and the format of IR code to be sent is shown as below:

• Preamble waveform: 9 ms carrier + 4.5 ms low level.
• Data 1 waveform: 0.56 ms carrier + 0.56 ms low level.
• Data 0 waveform: 0.56 ms carrier + 1.69 ms low level.
• Repeat waveform: 9 ms carrier + 2.25 ms low level + 0.56 ms carrier. Repeat waveform duration is 11.81 ms, interval between two adjacent repeat waveforms is 108 ms.
• End waveform: 0.56 ms carrier. User can follow the steps below to configure related registers: Step 1 Set carrier frequency as 38 kHz, set duty cycle as 1/3. º Set PWM_TMAX0 as 0x277 (i.e. 24 MHz/38 kHz = 631 = 0x277). º Since duty cycle is 1/3, set PWM_TCMP0 as 0xd2 (i.e. 631/3 = 210 = 0xd2). Step 2 Generate “FIFO CFG Data” sequence. º Preamble waveform: º Data 1 waveform: º Data 0 waveform: º Repeat waveform: 108 ms - 11.81 ms = 96.19 ms low level: º End waveform: Step 3 Write “IR CFG Data” into SRAM in DMA format. If user want PWM0 to send IR waveform in following format:
• Preamble+0x5a+Repeat+End
• Preamble: 0x8156, 0x00ab
• 0x5a = 8’b01011010
• Data 0: 0x8015, 0x0040
• Data 1: 0x8015, 0x0015
• Data 0: 0x8015, 0x0040

Datasheet for Telink TC321x DS-TC321x-E7 167 Ver 0.8.1

• Data 1: 0x8015, 0x0015
• Data 1: 0x8015, 0x0015
• Data 0: 0x8015, 0x0040
• Data 1: 0x8015, 0x0015
• Data 0: 0x8015, 0x0040
• Repeat: 0x8156, 0x0056, 0x8015, 0x0e47
• End: 0x8015. User needs to write the configuration information above into source address of DMA channel 5, as shown below:
• DMA SOURCE ADDRESS+0x00: 0x0000_002e (DMA transfer-length: 46 bytes)
• DMA SOURCE ADDRESS+0x04: 0x00ab_8156 (Preamble) (little endian)
• DMA SOURCE ADDRESS+0x08: 0x0040_8015 (Data 0)
• DMA SOURCE ADDRESS+0x0c: 0x0015_8015 (Data 1)
• DMA SOURCE ADDRESS+0x10: 0x0040_8015 (Data 0)
• DMA SOURCE ADDRESS+0x14: 0x0015_8015 (Data 1)
• DMA SOURCE ADDRESS+0x18: 0x0015_8015 (Data 1)
• DMA SOURCE ADDRESS+0x1c: 0x0040_8015 (Data 0)
• DMA SOURCE ADDRESS+0x20: 0x0015_8015 (Data 1)
• DMA SOURCE ADDRESS+0x24: 0x0040_8015 (Data 0)
• DMA SOURCE ADDRESS+0x28: 0x0056_8156 (Repeat)
• DMA SOURCE ADDRESS+0x2c: 0x0e47_8015 (Repeat)
• DMA SOURCE ADDRESS+0x30: 0x8015 (End) Step 4 Enable DMA channel 5 to send PWM waveforms. º Write 1’b1 to address 0x524[5] to enable DMA channel 5. After all waveforms are sent, FIFO becomes empty, PWM0 is disabled automatically (address 0x800781[0] is automatically cleared). The FIFO mode stop interrupt flag bit (address 0x8007b3[0]) is automatically set as 1’b1. If the interrupt is enabled by setting PWM_MASK1 (address 0x8007b2[0]) as 1’b1, a FIFO mode stop interrupt is generated. User needs to write 1’b1 to the flag bit to manually clear it.

15.5 PWM Interrupt

There are 9 interrupt sources from PWM function. After each signal frame, PWM#n (n = 0 ~ 5) generates a frame-done IRQ (Interrupt Request) signal. In Counting mode and IR mode, PWM0 generates a Pnum IRQ signal after completing a pulse group. In IR FIFO mode, PWM0 generates a FIFO mode count IRQ signal when the FIFO_NUM value is less than the FIFO_NUM_LVL, and generates a FIFO mode stop IRQ signal after FIFO becomes empty. In IR DMA FIFO mode, PWM0 generates an IR waveform send done IRQ signal, after DMA has sent all configuration data, FIFO becomes empty and final waveform is sent.

Datasheet for Telink TC321x DS-TC321x-E7 168 Ver 0.8.1 To enable PWM interrupt, the total enabling bit “irq_pwm” (address 0x800641[6], see Chapter 9) should be set as 1’b1. To enable various PWM interrupt sources, PWM_MASK0 (address 0x8007b0[ 7:0]) and PWM_MASK1 (address 0x8007b2[0]) should be set as 1’b1 correspondingly. Interrupt status can be cleared via register PWM_INT0 (address 0x8007b1[7:0]) and PWM_INT1 (address 0x8007b3[0]).

15.6 Register Table

PWM related registers are listed as following.The base address for below registers is 0x800780. Table 15-1 Register Table for PWM Address offset Name Type Description Default Value 0x00 PWM_EN W [1]: 0 - disable PWM1, 1 - enable PWM1 [2]: 0 - disable PWM2, 1 - enable PWM2[3]: 0 - disable PWM3, 1 - enable PWM3 [4]: 0 - disable PWM4, 1 - enable PWM4 [5]: 0 - disable PWM5, 1 - enable PWM5 0x00 0x01 PWM_EN0 W [0]: 0 - disable PWM0, 1 - enable PWM0 0x00 0x02 PWM_CLKDIV RW Set PWM_clk: (PWM_CLKDIV+1)*sys_clk 0x00 0x03 PWM_MODE RW [3:0]: PWM0 mode select 0000 - PWM0 normal mode 0001 - PWM0 count mode 0011 - PWM0 IR mode 0111 - PWM0 IR FIFO mode 1111 - PWM0 IR DMA FIFO mode 0x00 0x04 PWM_CC0 RW [5:0]: 1'b1 invert PWM output 0x00 0x05 PWM_CC1 RW [5:0]: 1'b1 invert PWM_INV output 0x00 0x06 PWM_CC2 RW [5:0]: Signal frame polarity of PWM5 ~ PWM0 1’b0 - high level first 1’b1 - low level first 0x00 0x08 ~ 0x13 - - Reserved - 0x14 PWM_TCMP0_L RW [7:0] bits 7-0 of PWM0's high time or low time (if pola[0] = 1) 0x00 0x15 PWM_TCMP0_H RW [15:8] bits 15-8 of PWM0's high time or low time 0x00

Datasheet for Telink TC321x DS-TC321x-E7 169 Ver 0.8.1 0x16 PWM_TMAX0_L RW [7:0] bits 7-0 of PWM0's cycle time 0x00 0x17 PWM_TMAX0_H RW [15:8] bits 15-8 of PWM0's cycle time 0x00 0x18 PWM_TCMP1_L RW [7:0] bits 7-0 of PWM1's high time or low time (if pola[1] = 1) 0x00 0x19 PWM_TCMP1_H RW [15:8] bits 15-8 of PWM1's high time or low time 0x00 0x1a PWM_TMAX1_L RW [7:0] bits 7-0 of PWM1's cycle time 0x00 0x1b PWM_TMAX1_H RW [15:8] bits 15-8 of PWM1's cycle time 0x00 0x1c PWM_TCMP2_L RW [7:0] bits 7-0 of PWM2's high time or low time (if pola[2] = 1) 0x00 0x1d PWM_TCMP2_H RW [15:8] bits 15-8 of PWM2's high time or low time 0x00 0x1e PWM_TMAX2_L RW [7:0] bits 7-0 of PWM2's cycle time 0x00 0x1f PWM_TMAX2_H RW [15:8] bits 15-8 of PWM2's cycle time 0x00 0x20 PWM_TCMP3_L RW [7:0] bits 7-0 of PWM3's high time or low time 0x00 0x21 PWM_TCMP3_H RW [15:8] bits 15-8 of PWM3's high time or low time 0x00 0x22 PWM_TMAX3_L RW [7:0] bits 7-0 of PWM3's cycle time 0x00 0x23 PWM_TMAX3_H RW [15:8] bits 15-8 of PWM3's cycle time 0x00 0x24 PWM_TCMP4_L RW [7:0] bits 7-0 of PWM4's high time or low time (if pola[4] = 1) 0x00 0x25 PWM_TCMP4_H RW [15:8] bits 15-8 of PWM4's high time or low time 0x00 0x26 PWM_TMAX4_L RW [7:0] bits 7-0 of PWM4's cycle time 0x00 0x27 PWM_TMAX4_H RW [15:8] bits 15-8 of PWM4's cycle time 0x00 0x28 PWM_TCMP5_L RW [7:0] bits 7-0 of PWM5's high time or low time (if pola[5] = 1) 0x00 0x29 PWM_TCMP5_H RW [15:8] bits 15-8 of PWM5's high time or low time 0x00 0x2a PWM_TMAX5_L RW [7:0] bits 7-0 of PWM5's cycle time 0x00 0x2b PWM_TMAX5_H RW [15:8] bits 15-8 of PWM5's cycle time 0x00 0x2c PWM_PNUM_L RW [7:0] bits 7-0 of PWM0 Pulse number in count mode and IR mode 0x00 Address offset Name Type Description Default Value

Datasheet for Telink TC321x DS-TC321x-E7 170 Ver 0.8.1 0x2d PWM_PNUM_H RW [13:8] bits 13-8 of PWM0 Pulse number in count mode and IR mode 0x00 0x2e ~ 0x2f - - Reserved - 0x30 PWM_MASK RW INT mask [0]: PWM0 Pnum int 0 - disable, 1 - enable [1]: PWM0 ir dma fifo mode int 0 - disable, 1 - enable [2]: PWM0 frame int 0 - disable, 1 - enable [3]: PWM1 frame int 0 - disable, 1 - enable [4]: PWM2 frame int 0 - disable, 1 - enable[5]: PWM3 frame int 0 - disable, 1 - enable [6]: PWM4 frame int 0 - disable, 1 - enable [7]: PWM5 frame int 0 - disable, 1 - enable 0x00 0x31 PWM_INT RW INT status, write 1 to clear [0]: PWM0 pnum int (have sent PNUM pulses, PWM_NCNT==PWM_PNUM) [1]: PWM0 ir dma fifo mode int (pnum int & fifo empty in ir dma fifo mode) [2]: PWM0 cycle done int (PWM_CNT==PWM_TMAX) [3]: PWM1 cycle done int (PWM_CNT==PWM_TMAX) [4]: PWM2 cycle done int (PWM_CNT==PWM_TMAX)[5]: PWM3 cycle done int (PWM_CNT==PWM_TMAX) [6]: PWM4 cycle done int (PWM_CNT==PWM_TMAX) [7]: PWM5 cycle done int (PWM_CNT==PWM_TMAX) 0x00 0x32 PWM_MASK_LVL RW [0]: PWM0 fifo mode fifo cnt int mask 0 - disable, 1 - enable 0x00 Address offset Name Type Description Default Value

Datasheet for Telink TC321x DS-TC321x-E7 171 Ver 0.8.1 0x33 PWM_INT_LVL RW INT status, write 1 to clear [0]: fifo mode cnt int, when FIFO_NUM (0x7cd[3:0]) is less than FIFO_NUM_LVL (0x7cc[3:0]) 0x00 0x34 PWM_CNT0_L R [7:0] PWM0 cnt value 0x00 0x35 PWM_CNT0_H R [15:8] PWM0 cnt value 0x00 0x36 PWM_CNT1_L R [7:0] PWM1 cnt value 0x00 0x37 PWM_CNT1_H R [15:8] PWM1 cnt value 0x00 0x38 PWM_CNT2_L R [7:0] PWM2 cnt value 0x00 0x39 PWM_CNT2_H R [15:8] PWM2 cnt value 0x00 0x3a PWM_CNT3_L R [7:0] PWM3 cnt value 0x00 0x3b PWM_CNT3_H - [15:8] PWM3 cnt value 0x00 0x3c PWM_CNT4_L R [7:0] PWM4 cnt value 0x00 0x3d PWM_CNT4_H - [15:8] PWM4 cnt value 0x00 0x3e PWM_CNT5_L R [7:0] PWM5 cnt value 0x00 0x3f PWM_CNT5_H - [15:8] PWM5 cnt value 0x00 0x40 PWM_NCNT_L R [7:0] PWM0 pluse_cnt value 0x00 0x41 PWM_NCNT_H R [15:8] PWM0 pluse_cnt value 0x00 0x42 ~ 0x43 - - Reserved - 0x44 PWM_TCMP_FSK RW [7:0] bits 7-0 of PWM0's high time or low time (if pola[0]=1), if shadow bit (fifo data[14]) is 1'b1 in ir fifo mode or dma fifo mode 0x00 0x45 PWM_TCMP_FSK RW [15:8] bits 15-8 of PWM0's high time or low time, if shadow bit (fifo data[14]) is 1'b1 in ir fifo mode or dma fifo mode 0x00 0x46 PWM_TMAX_FSK RW [7:0] bits 7-0 of PWM0's cycle time, if shadow bit (fifo data[14]) is 1'b1 in ir fifo mode or dma fifo mode 0x00 0x47 PWM_TMAX_FSK RW [15:8] bits 15-8 of PWM0's cycle time, if shadow bit (fifo frame[14]) is 1'b1 in ir fifo mode or dma fifo mode 0x00 0x48 PWM_RDAT_L0 RW Use in IR FIFO mode 0x00 Address offset Name Type Description Default Value

Datasheet for Telink TC321x DS-TC321x-E7 172 Ver 0.8.1 0x49 PWM_RDAT_H0 RW Use in IR FIFO mode 0x00 0x4a PWM_RDAT_L1 RW Use in IR FIFO mode 0x00 0x4b PWM_RDAT_H1 RW Use in IR FIFO mode 0x00 0x4c PWM_FIFO_LVL RW FIFO num int trigger level 0x00 0x4d PWM_TX_CTRL R [3:0]: FIFO DATA NUM (byte) [4]: FIFO EMPTY [5]: FIFO FULL 0x10 0x4e clear0 W1C [0]: clear: write 1 to clear data in FIFO; normal (default): write 0 0x00 Address offset Name Type Description Default Value

Datasheet for Telink TC321x DS-TC321x-E7 173 Ver 0.8.1

16 SD ADC

16.1 Overview of SD ADC

The SoC integrates one SD (Sigma-Delta) ADC module, which can be used for both audio and DC measurement. This section focuses on the DC measurement application. The ADC’s differential inputs are selected through two multiplexers, and the input buffers must be enabled to meet performance requirement. The sigma-delta modulator oversamples the input with a clock Fs and shapes the quantization noise. The sinc3 digital filter removes the out-of-band quantization noise and decimates the modulator output to a low data rate, which in turn generates the final output. Different models of chips support different ADC resolutions, including 12bit and 16bit. The 12-bit chip only supports the sampling clock of 1MHz, downsampling factor of 64. The 16-bit chip supports the sampling clock of 1MHz/2MHz, downsampling factor of 64/128/256. The system architecture of SD ADC module is shown in figure below. Figure 16-1 System Architecture of SD ADC According to Table 1-7 GPIO Pin Mux of TC3216C/TC3215C, the aio<9:0> in the above figure corresponds to GPIO pins PD[1], PD[0], and PB[7:0]. It is recommended to use PB5 as ADC input. If using other GPIOs as ADC input, it is suggested to add board level calibration circuit.

16.2 Analog Registers Description and Configuration

The SD ADC related analog registers are listed as following. Table 16-1 Analog Registers Address Default Value Description afe_0x7d<2> 1 1:power down audio; 0: power on audio (internal pm_top pin pg_audio_en_o = !pg_audio_en) afe_0x8c<1> 0 xtal_24M clock to analog 0:turn off; 1:turn on. afe_0x8c<2> 0 0: DEM function of sigma-delta ADC is disabled; 1: DEM function of sigma-delta ADC is enabled PGA MUX_SW MUX_SW BUFFER BUFFER Ȉǻ Sinc3 digital filter MUX_SW MUX_SW AMIC vbatdiv ai_p<2:0> aio<9:0> audio_p avss ai_n<2:0> aio<9:0> audio_n aip_sel ain_sel opmode opmode ADC output

Datasheet for Telink TC321x DS-TC321x-E7 174 Ver 0.8.1 afe_0x8c<4:3> 11 PD signal for two ADC buffers 00: power on afe_0x8c<6> 0 Selecting positive signal sent to adc_buffer between ai_p(aio)_div and vbat_div. 0 for ai_p(aio)_div; 1 for vbat_div. afe_0x8d<1:0> 00 Selecting dividing ratio of vbat. 00: 1/8 01: 1/4 10: 1/2 11: 3/4 afe_0x8e<4> 1 PD signal for PGA Set to 1 when performing DC measurement afe_0x8e<5> 1 PD signal for CODEC Bias Set to 0 to power on the ADC analog system afe_0x8e<6> 1 PD signal for ADC Set to 0 to power on ADC core circuit afe_0x8e<7> 1 PD signal for VMID Set to 0 to provide ADC reference voltage afe_0x8f<3:0> 0000 Low-power mode enable signal. <3> for PGA and <2:0> for ADC. 0: default mode 1: low-power mode afe_0x8f<6:4> 000 Control the selection of test signal from ADC afe_0x8f<7> 0 vbat detector enable signal 0:disable 1:enable Set to 1 when measuring VBAT; Set to 0 when measuring GPIO. afe_0x90<3:0> 1111 Selecting one among 13 negative analog inputs. 0000~1111: aio<0> to aio<9> 1101~1111: reserved Address Default Value Description

Datasheet for Telink TC321x DS-TC321x-E7 175 Ver 0.8.1 A typical configuration is provided below, using PD[1] and PD[0] as the ADC inputs. Table 16-2 Typical Configuration afe_0x90<7:4> 1111 Selecting one among 13 positive analog inputs. 0000~1111: aio<0> to aio<9> 1101~1111: reserved afe_0x91<1:0> 11 Selecting dividing ratio of negative analog input. 00: 1/8 01: 1/4 10: 1/2 11: 1 afe_0x91<3:2> 11 Selecting dividing ratio of negative analog input. 00: 1/8 01: 1/4 10: 1/2 11: 1 afe_0x91<4> 0 Enable signal for global chopping function afe_0x91<5> 0 Enable signal for bypassing adc_buffer. afe_0x91<7> 0 Fs6M_clk_inv signal afe_0x92<3:0> 1111 Selecting one among 13 negative analog inputs. 0000~1111: aio<0> to aio<9> 1101~1111: reserved afe_0x92<7:4> 1111 Selecting one among 13 positive analog inputs. 0000~1111: aio<0> to aio<9> 1101~1111: reserved Register Address Value Description afe_0x8c 0x22 Configuration for ADC input selection. afe_0x8d 0xF0 Analog configuration settings. afe_0x8e 0x1C Power and reference settings. afe_0x8f 0x00 Input selection for measurement (VBAT or GPIO). Address Default Value Description

Datasheet for Telink TC321x DS-TC321x-E7 176 Ver 0.8.1

16.3 Digital Registers Description and Configuration

The SD ADC related digital registers are listed as following. The base address for below registers is 0x800000. Table 16-3 Digital Registers Description and Configuration afe_0x90 0x98 Input channels configuration (PD[1]/PD[0]). afe_0x91 0x0F Input signal scaling and selection. Address Name Type Description Default Value 0xb12 DFIFOAIN1 RW [7]: r_mic_sel 0:amic 1:dmic 0x20 0xb48 DFIFOBA2L RW [7:0]: r_ba2[7:0] fifo address 0x00 0xb49 DFIFOBA2H RW [7:0]: r_ba2[15:8] fifo address 0x3c 0xb4a DFIFOMAX2 RW [7:0]: fifo depth fifo depth={0xb4a, 2’b11} 0xb4a should be set as 8’b0000_1111 or 8’b0000_0111, make sure 1 are consecutive 0x3f 0xb4b DFIFOAIDX2 RW [6:4]: r_dec dc cic down sample rate 0:64; 1:128; 2:256; else:256 0x04 0xb4c DFIFO_DC_CLK_ DIV RW [6:0]: dc_clk_div clk_fs = sys_clk/2(b4c+1) 0x17 0xb4d OP_MODE RW [2:0]: op_mode 3’b100: audio only 3’b001: 1 channel dc 3’b010: audio + dc (not used) 3’b011: 2 channel dc (not used) 0x0 0xb4f DFIFORN2 RW fifo num threshold to inform irq, the threshold is {b4f, 2’b11} 0x20 0xb50 DFIFO_DC_MODE RW [2]: fifo enable [7]: irq mask 0x80 Register Address Value Description

Datasheet for Telink TC321x DS-TC321x-E7 177 Ver 0.8.1

16.4 Data Acquirement and Processing

The ADC output data is in a 32-bit hexadecimal format. The following steps are used to convert the output data to the corresponding voltage value:

• Convert the hexadecimal ADC output to decimal.
• Divide the decimal value by (OSR^3)*2. The oversampling ratio (OSR) can be 64, 128, or 256, controlled by digital registers.
• If required, average the processed data for noise reduction. 0xb53 IRQ_FIFO - [3]: irq (W1C) [7]: irq status (R) 0x0 0xb5e DFIFO_WPTR2L VOLATILE [7:2]: wptr2l fifo wptr2[5:0] 0x00 0xb5f DFIFO_WPTR2H VOLATILE [3:0]: wptr2h fifo wptr2[9:6] 0x00 Address Name Type Description Default Value

Datasheet for Telink TC321x DS-TC321x-E7 178 Ver 0.8.1

17 AES

The SoC embeds AES module with encryption and decryption function. The input 128-bit plaintext in combination of key is converted into the final output ciphertext via encryption; the 128-bit ciphertext in combination of key can also be converted into 128-bit plaintext via decryption. The AES hardware accelerator provides automatic encryption and decryption. It only takes (1000*system clock cycles) to implement AES encryption/decryption. Suppose system clock is 20 MHz, the time needed for AES encryption/decryption is 50 µs. Both RISC mode and DMA mode are supported for AES operation.

17.1 RISC Mode

For RISC mode, configuration of related registers is as follows:

• Set the value of key via writing registers AES_KEY0 ~ AES_KEY15 (address 0x800710 ~ 0x80071f).
• Set operation method of AES module via register AES_CTRL: set address 0x800700[0] as 1’b1 for decryption method, while clear this bit for encryption method.
• For encryption method, write registers AES-DAT0 ~ AES-DAT3 (address 0x800708 ~ 0x80070b) for four times to set the 128-bit plaintext. After encryption, the 128-bit ciphertext can be obtained by reading address 0x800708 ~ 0x80070b for four times.
• For decryption method, write registers AES-DAT0 ~ AES-DAT3 (address 0x800708 ~ 0x80070b) for four times to set the 128-bit ciphertext. After decryption, the 128-bit plaintext can be obtained by reading address 0x800708 ~ 0x80070b for four times.
• Address 0x800700 bit[1] and bit[2] are read only bits: bit[1] is cleared automatically after quartic writing of address 0x800708 ~ 0x80070b; bit[2] is set as 1 automatically after encryption/decryption, and then cleared automatically after quartic reading of address 0x800708 ~ 0x80070b.

17.2 DMA Mode

As for DMA mode, it is only needed to configure the value of key and encryption/decryption method for AES module.

17.3 AES-CCM

The AES-CCM (Counter with the CBC-MAC) mode is disabled by default. AES output is directly determined by current encryption and decryption, irrespective of previous encryption and decryption result. If 0x800700[7] is set as 1’b1 to enable AES-CCM mode, AES output also takes previous encryption and decryption result into consideration.

17.4 Register Table

The AES related registers are listed in the following table. The base address for the AES related registers is 0x800700.

Datasheet for Telink TC321x DS-TC321x-E7 179 Ver 0.8.1 Table 17-1 Register Table Related to AES Address offset Name Type Description Default Value 0x00 AES_CTRL RW [0] mode 1: decrypt, 0: encrypt [1] dma_brdy 1: dma to aes direction need data (R) [2] dma_drdy 1: aes to dma direction need data, aes is done (R) [7] m_xor 1: xor mode 0x02 0x01 AES_DCNT R [1:0] write/read data count 0x00 0x08 AES_DAT0 VOLATILE [7:0] bdrdat0 aesdat[0:7], w: data to be processed, r: aes processed done data 0x00 0x09 AES_DAT1 VOLATILE [7:0] bdrdat1, aesdat[8:15] 0x00 0x0a AES_DAT2 VOLATILE [7:0] bdrdat2, aesdat[16:23] 0x00 0x0b AES_DAT3 VOLATILE [7:0] bdrdat3, aesdat[23:31] 0x00 0x10 AES_KEY0 RW [7:0] KEY0, usrkey[0][0:7] 0x00 0x11 AES_KEY1 RW [7:0] KEY1, usrkey[0][8:15] 0x00 0x12 AES_KEY2 RW [7:0] KEY2, usrkey[0][16:23] 0x00 0x13 AES_KEY3 RW [7:0] KEY3, usrkey[0][23:31] 0x00 0x14 AES_KEY4 RW [7:0] KEY4, usrkey[1][0:7] 0x00 0x15 AES_KEY5 RW [7:0] KEY5, usrkey[1][8:15] 0x00 0x16 AES_KEY6 RW [7:0] KEY6, usrkey[1][16:23] 0x00 0x17 AES_KEY7 RW [7:0] KEY7, usrkey[1][23:31] 0x00 0x18 AES_KEY8 RW [7:0] KEY8, usrkey[2][0:7] 0x00 0x19 AES_KEY9 RW [7:0] KEY9, usrkey[2][8:15] 0x00 0x1a AES_KEY10 RW [7:0] KEY10, usrkey[2][16:23] 0x00 0x1b AES_KEY11 RW [7:0] KEY11, usrkey[2][23:31] 0x00 0x1c AES_KEY12 RW [7:0] KEY12, usrkey[3][0:7] 0x00

Datasheet for Telink TC321x DS-TC321x-E7 180 Ver 0.8.1 0x1d AES_KEY13 RW [7:0] KEY13, usrkey[3][8:15] 0x00 0x1e AES_KEY14 RW [7:0] KEY14, usrkey[3][16:23] 0x00 0x1f AES_KEY15 RW [7:0] KEY15, usrkey[3][23:31] 0x00 Address offset Name Type Description Default Value

Datasheet for Telink TC321x DS-TC321x-E7 181 Ver 0.8.1

18 Secure Debug

18.1 Introduction

The Secure Debug allows all debug interfaces such as SWS to be locked so that hackers are not able to access any on-chip information (registers or memories) from these debug interfaces. The user can use SWM to input Secure Debug keys to re-enable debug interface again.

18.2 Key Management

The Debug Key is used to re-enable debug interface. The debug key is burned into eFuse directly without any derivation. The chip has a key lock mechanism, once the key lock function is enabled (key_lock=1), the software cannot read the debug text in the eFuse. 18.3 eFuse Definition The eFuse definition is shown in the table below. Please also check 4.1.3 eFuse for details on eFuse. Table 18-1 eFuse Data for Secure Debug

18.4 Secure Debug Process

18.4.1 Enable Secure Debug

The process of enabling Secure Debug is as follows. Step 1 Write debug_key to the register bit [63:32] of eFuse. Step 2 Read the register bit [63:32] of eFuse, confirm the debug_key is written correctly. Step 3 Write 1 to the register bit [74] of eFuse. Definition Length (Bit)

Description

reserved [31:0] Reserved for Telink internal use debug_key [63:32] Debug key, used for re-enable the SWS debug interface reserved [67] Reserved for Telink internal use Key_read_disable [72] 1: flash key and debug key cannot be read 0: keys can be read sws_dbg_disable [74] 1: disable SWS debug interface 0: enable SWS debug interface

Datasheet for Telink TC321x DS-TC321x-E7 182 Ver 0.8.1

18.4.2 Re-enable Debug Interface

According to the 32bit debug key, write data debug_key[31:24] to the address debug_key[23:0] through SWS to re-enable the SWS debug interface. For example, if 32bit debug key = 0x12345678, write 0x12 to the address 0x345678 through SWS.