TFRA08C13

TFRA08C13 AGERE | Alldatasheet

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Features

■ Eight independent T1/E1 transmit and receive framers. ■ Internal DS1 transmit clock synthesis—no external oscillator necessary. ■ Comprehensive alarm reporting and performance monitoring: — Programmable automatic and on-demand alarm transmission. ■ Automatic facility data link: — Automatic transmission of ESF performance report message. ■ Common 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s TDM highway. ■ Dual- or single-rail line-side I/O. ■ Supports one second polling interval for perfor- mance monitoring. ■ IEEE * Std. 1149.1 JT AG boundary scan. ■ 3.3 V low-power CMOS with 5 V tolerant inputs. ■ Available in 352-pin PBGA. T1/E1 Framer Features ■ Supports T1 framing modes ESF , D4, SLC ®-96, T1DM DDS. ■ Supports G.704 basic and CRC-4 multiframe for- mat E1 framing and procedures consistent with G.706. ■ Supports unframed transmission format. ■ T1 signaling modes: transparent; ESF 2-state, 4-state, and 16-state; D4 2-state and 4-state; SLC -96 2-state, 4-state, 9-state, and 16-state. E1 signaling modes: transparent and CAS. ■ Alarm reporting and performance monitoring per AT & T, ANSI †, and ITU-T standards. ■ Programmable, independent transmit and receive system interfaces at a 2.048 MHz, 4.096 MHz, or 8.192 MHz data rate. Facility Data Link Features ■ HDLC or transparent mode. ■ Automatic transmission of the ESF performance report messages (PRM). ■ Detection of the ESF PRM. ■ Detection of the ANSI ESF FDL bit-oriented codes. ■ 64-byte FIFO in both transmit and receive direc- tions. ■ Programmable FIFO full and empty level interrupt. ■ User-programmable microprocessor interface. Microprocessor Interface ■ 33 MHz read and write access. ■ 12-bit address, 8-bit data interface. ■ Intel‡ or Motorola§ style control interfaces. ■ Directly addressable internal registers. ■ Programmable interrupts.

Applications

■ DS3 and E3 port cards for narrowband DXCs. ■ Multiservice switches. ■ High density DS1 and E1 port cards. ■ Frame relay access devices. ■ Byte-synchronous SDH/SONET mapping. ■ SONET and SDH drop alignment. ■ IP and packet routers. * IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. † ANSI is a registered trademark of American National Standards Institute, Inc. ‡ Intel is a registered trademark of Intel Corporation. § Motorola is a registered trademark of Motorola, Inc.

TFRA08C13 OCTAL T1/E1 Framer October 2000 2 Lucent Technologies Inc.

Lucent Technologies Inc. 3 Preliminary Data Sheet October 2000 TFRA08C13 OCTAL T1/E1 Framer Table of Contents (continued) Contents Page FDL Parameter/Control Registers ((A00—A0E); (A20—A2E); (B00—B0E);

Table of Contents (continued) Tables Page Preliminary Data Sheet TFRA08C13 OCTAL T1/E1 Framer October 2000 6 Lucent Technologies Inc. T able 33. Summary of the Deactivation of SSTSSLB and SSTSLLB Modes as a T able 38. Receive

Table 74. Exchange T ermination and Exchange T ermination Remote Table 75. Network T ermination and Network T ermination Remote End Table 103. Transmit Framer

Table of Contents (continued) Tables Page Preliminary Data Sheet TFRA08C13 OCTAL T1/E1 Framer October 2000 8 Lucent Technologies Inc. T able 137. T ransmission of Remote Frame Alarm and CEPT Automatic T able 143. T able 145. CEPT Time Slot 16 X-Bit Remote Multiframe Alarm and AIS T able 164. FDL Register Set ((A00—A0E); (A20—A2E); (B00—B0E); (B20—B2E)

Table 168. FDL T ransmitter Configuration Control Register (FDL_PR3) Table 170. FDL T ransmitter Idle Character Mask Register (FDL_PR5) Table 171. FDL Receiver Interrupt Level Control Register (FDL_PR6) Table 173. FDL Receiver Match Character Register (FDL_PR8) (A08; A28; B08; B28; C08; C28; D08; D28) ...172 Table 175. FDL T ransmit Table 176. FDL Interrupt Status Register (Clear on Read) (FDL_SR0) Table 179. Receive Table 188. Logic Interface Characteristics (T

TFRA08C13 OCTAL T1/E1 Framer October 2000 10 Lucent Technologies Inc. Lucent T echnologies Inc. Feature Descriptions T1/E1 Framer Feature Descriptions ■ Framing formats: — Compliant with T1 standards ANSI T1.231 (1993), A T&T TR54016, A T&T TR62411 (1998). — Unframed, transparent transmission in T1 and E1 formats. — DS1 extended superframe (ESF). — DS1 superframe (SF): D4; SLC -96; T1DM DDS; T1DM DDS with FDL access. — DS1 independent transmit and receive framing modes when using the ESF and D4 formats. — Compliant with ITU CEPT framing recommenda- tion: 1. G.704 and G.706 basic frame format. CRC-4 multiframe search algorithm. 3. G.706 Annex B: CRC-4 multiframe search algo- rithm with 400 ms timer for interworking of CRC-4 and non-CRC-4 equipment. 4. G.706 Section 4.3.2 Note 2: monitoring of 915 CRC-4 checksum errors for loss of frame state. ■ Framer line codes: — DS1: alternate mark inversion (AMI); binary eight zero code suppression (B8ZS); per-channel zero code suppression; decoding bipolar violation mon- itor; monitoring of eight or fifteen bit intervals with- out positive or negative pulses error indication. — DS1 independent transmit and receive path line code formats when using AMI/ZCS and B8ZS coding. — ITU-CEPT: AMI; high-density bipolar 3 (HDB3) encoding and decoding bipolar violation monitor- ing, monitoring of four bit intervals without positive or negative pulses error indication. — Single-rail option. ■ Signaling: — DS1: extended superframe 2-state, 4-state, and 16-state per-channel robbed bit. — DS1: D4 superframe 2-state and 4-state per- channel robbed bit. — DS1: SLC -96 superframe 2-state, 4-state, 9-state, and 16-state per-channel robbed bit. — DS1: channel-24 message-oriented signaling. — ITU CEPT: channel associated signaling (CAS). — Transparent (all data channels). ■ Alarm reporting, performance monitoring, and main- tenance: — ANSI T1.403-1995, A T&T TR 54016, and ITU G.826 standard error checking. — Error and status counters: 1. Bipolar violations. 2. Errored frame alignment signals. 3. Errored CRC checksum block. 4. CEPT: received E bit = 0. 5. Errored, severely errored, and unavailable seconds. — Selectable errored event monitoring for errored and severely errored seconds processing with programmable thresholds for errored and severely errored second monitoring. — CEPT: Selectable automatic transmission of E bit to the line. — CEPT: Sa6 coded remote end CRC-4 error E bit = 0 events. — Programmable automatic and on-demand alarm transmission: 1. Automatic transmission of remote frame alarm to the line while in loss of frame alignment state. 2. Automatic transmission of alarm indication signal (AIS) to the system while in loss of frame alignment state. — Multiple loopback modes. — Optional automatic line and payload loopback acti- vate and deactivate modes. — CEPT nailed-up connect loopback and CEPT nailed-up broadcast transmission TS-X in TS-0 transmit mode. — Selectable test patterns for line transmission. — Detection of framed and unframed pseudorandom and quasi-random test patterns. — Programmable squelch and idle codes. ■ System interface: — Autonomous transmit and receive system inter- faces. — Independent transmit and receive frame synchro- nization input signals. — Independent transmit and receive system interface clock. — 2.048 Mbits/s, 2.048 MHz concentration highway interface (CHI) default mode. — Optional 4.096 Mbits/s and 8.192 Mbits/s data rates. — Optional 4.096 MHz and 8.192 MHz frequency system clock. — Programmable clock edge for latching frame syn- chronization signals. — Programmable clock edge for latching transmit and receive data. — Programmable bit and byte offset. — Programmable CHI master mode for the genera- tion of the transmit CHI FS from internal logic with timing derived from the receive line clock signal. ■ Digital phase comparator for clock generation in the receive and transmit paths.

as input from the system interface. This document is consistent with that definition. Figure 1. TFRA08C13 Block Diagram (One of Eight Channels)

TFRA08C13 OCTAL T1/E1 Framer October 2000 12 Lucent Technologies Inc. Lucent T echnologies Inc. Functional Description (continued) The Lucent T echnologies Microelectronics Group TFRA08C13 OCT AL T1/E1 Framer provides eight com- plete T1/E1 interfaces each consisting of a fully inte- grated, full-featured, primary rate framer with an HDLC formatter for facility data link access. The TFRA08C13 provides glueless interconnection from a T1 or E1 ana- log line interface to devices interfacing to its CHI; for example, the Lucent T7270 Time-Slot Interchanger or T7115A Synchronous Protocol Data Formatter. The line codes supported in the framer unit include AMI, T1 B8ZS, per-channel T1 zero code suppression, and ITU-CEPT HDB3. The framer supports DS1 superframe (D4, T1DM, SLC -96) and extended superframe (ESF) formats. The framer also supports, ITU-CEPT -E1 basic frame, ITU-CEPT -E1 time slot 0 multiframe, and time slot 16 multiframe formats. The receive framer monitors the following alarms: loss of receive clock, loss of frame, alarm indication signal (AIS), remote frame alarms, and remote multiframe alarms. These alarms are detected as defined by the appropriate ANSI, A T&T , and ITU standards. It is rec- ommended that the LIU/Framer interface be placed in dual rail mode, which allows the framers error/event detector to detect and report code and BPV errors. Performance monitoring as specified by A T&T, ANSI, and ITU is provided through counters monitoring bipo- lar violation, frame bit errors, CRC errors, errored events, errored seconds, bursty errored seconds, severely errored seconds, and unavailable seconds. In-band loopback activation and deactivation codes can be transmitted to the line via the payload or the facility data link. In-band loopback activation and deac- tivation codes in the payload or the facility data link are detected. System, payload, and line loopbacks are programma- ble. The default system interface is a 2.048 Mbits/s data and 2.048 MHz clock CHI serial bus. This CHI interface consists of independent transmit and receive paths. The CHI interface can be reconfigured into several modes: a 2.048 Mbits/s data interface and 4.096 MHz clock interface, a 4.096 Mbits/s data interface and 4.096 MHz clock interface, a 4.096 Mbits/s data inter- face and 8.192 MHz clock interface, a 8.192 Mbits/s data interface and 8.192 MHz clock interface, and 8.192 Mbits/s data interface. The signaling formats supported are T1 per-channel robbed-bit signaling (RBS), channel-24 message-ori- ented signaling (MOS), and ITU-CEPT -E1 channel- associated signaling (CAS). In the T1, RBS mode voice and data channels are programmable. The entire pay- load can be forced into a data-only (no signaling chan- nels) mode, i.e., transparent mode by programming one control bit. Signaling access can be through the on-chip signaling registers or the system CHI port in the associated signaling mode. Data and its associated signaling information can be accessed through the CHI in either DS1 or CEPT -E1 modes. Extraction and insertion of the facility data link in ESF , T1DM, SLC -96, or CEPT -E1 modes are provided through a four-port serial interface or through a micro- processor-accessed, 64-byte FIFO either with HDLC formatting or transparently. In SLC -96 or CEPT -E1 frame formats, a facility data link (FDL) stack (registers in the framer section) is provided for FDL access. The bit-oriented ESF data-link messages defined in ANSI T1.403-1995 are monitored by the receive framer’s facility data link unit. The transmit framer’s facility data link unit overrides the XFDL-FIFO for the transmission of the bit-oriented ESF data-link messages defined in ANSI T1.403-1995. The receive framer includes a two-frame (64-bytes) elastic store buffer for jitter attenuation that performs controlled slips and provides an indication of slip direc- tion. This buffer can be programmed to operate as a function of the receive line clock and can be reduced to one-frame (32-bytes) in length.

MC680X0 or M68360 interface protocol with address and data strobe signals. grid array (PBGA) with 50 mils ball pitch. Figure 2. TFRA08C13 Block Diagram: Receive Section (One of Eight Channels)

• MESSAGE-ORIENTED MESSAGES
• BIT -ORIENTED MESSAGES – ANSI T1.403-1989 ESF FORMA T: – DDS ACCESS SLC-96 FORMA T AND MONITOR: RECEIVE FACILITY DATA LINK EXTRACTER RFRMCK RPD, RND_RBPV RLCK RECEIVE PATTERN MONITOR: – QUASI-RANDOM: 2 20 – 1 – PSEUDORANDOM: 2 15 – 1 – ANSI T1.403 BIT-ORIENTED AND ESF-FDL ACTIVA TE AND DEACTIVA TE LINE LOOPBACK CODES – CEPT AUXILIARY PA TTERN (CEPT = 01) – CEPT ACTIVA TE AND DEACTIVA TE LOOPBACK – CEPT Sa6 CODES – T1/E1 CRC ERRORS RECEIVE FDL HDLC EXTRACTER: – 64-byte RECEIVE FIFO – TRANSP ARENT MODE (NO HDLC FRAMING) – MICROPROCESSOR ACCESS TCHIDA TA/B CODES

14 Lucent Technologies Inc. Lucent T echnologies Inc. Figure 3. TFRA08C13 Block Diagram: Transmit Section (One of Eight Channels)

• BIT -ORIENTED MESSAGES
• MESSAGE-ORIENTED MESSAGES TRANSMIT FDL HDLC INSERTER: – 64-byte TRANSMIT FIFO – TRANSP ARENT MODE – MICROPROCESSOR ACCESS (NO HDLC FRAMING) INSERTER: TFDLCK TFDL LINE FORMAT (AMI; B8ZS; HDB3) TRANSMIT PATTERN GENERATOR: – QUASI-RANDOM: 2 20 – 1 – PSEUDORANDOM: 2 15 – 1 – ANSI T1.403 BIT-ORIENTED AND ESF-FDL LOOPBACK CODES – CEPT AUXILIARY P A TTERN (CEPT = 01) – CEPT ACTIVA TE AND DEACTIVA TE – CEPT Sa6 CODES ACTIVA TE AND DEACTIVA TE LINE LOOPBACK CODES TRANSMIT ELASTIC STORE BUFFER (2 FRAMES) RECEIVE CONCENTRA TION HIGHWAY INTERFACE (RA TE ADAPTER) CHICK CHIFS RCHIDA TA/B TRANSMIT ALARM MONITOR: – LOSS OF SYSTEM BIFRAME ALIGNMENT – SYSTEM ALARM INDICA TION SIGNAL (AIS) TRANSMIT SIGNALING INSERTER: – DS1 ROBBED-BIT SIGNALING (RBS) – CEPT CHANNEL ASSOCIA TED AND – CONCENTRA TION HIGHWAY ACCESS – MICROPROCESSOR ACCESS COMMON-CHANNEL SIGNALING CRC GENERATOR: MUL TIFRAME ENCODERTND, TPD

The package type and pin assignment for the TFRA08C13 is illustrated in Figure 4. Figure 4. Pin Assignment

16 Lucent Technologies Inc. Lucent T echnologies Inc. Table 1. Pin Assignments for 352-Pin PBGA by Pin Number Order

Table 1. Pin Assignments for 352-Pin PBGA by Pin Number Order (continued)

18 Lucent Technologies Inc. Lucent T echnologies Inc. T able 2 shows the list of the TFRA08C13 pins and a functional description for each. Table 2. Pin Descriptions with a 0.1 µF capacitor to VSS , as close to the pin as possible. SSA G 3.3 V Quiet Analog Ground. SSD G 3.3 V Quiet Digital Ground. into a high-impedance state.

• Iu indicates an internal pull-up, Id indicates an internal pull-down.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. ‡ Asserting this pin low will initially force RDY to a low state.

is used as the clock signal source for the internal second pulse timer. The second pulse is used for performance monitoring. Re gister (FRM_PR45 ) (Y8D )). the internal PLL circuitry (refer to the Phase-Lock Loop section). the recovered receive line interface unit clock or the RLCK input signal. The choice of which receive framer clock to use is defined in Table 66. J4 DS1/CEPT [1] Iu DS1/CEPT . Strap to VDD to enable DS1 operation in the framer unit.

• Iu indicates an internal pull-up, Id indicates an internal pull-down.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. ‡ Asserting this pin low will initially force RDY to a low state. Table 2. Pin Descriptions (continued)

20 Lucent Technologies Inc. Lucent T echnologies Inc. frequency signal (1.544 MHz) or a high frequency signal (6.176 MHz). (2.048 MHz) or a high-frequency signal (8.192 MHz). changes on the rising edge of TLCK. TLCK. In the single-rail mode, TPD = transmit framer data.

• Iu indicates an internal pull-up, Id indicates an internal pull-down.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. ‡ Asserting this pin low will initially force RDY to a low state.

latches data link bits on the falling edge of TFDLCK. grammed to one of the XSa bits of the NOT FAS frame time slot 0.

• Iu indicates an internal pull-up, Id indicates an internal pull-down.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. ‡ Asserting this pin low will initially force RDY to a low state.

22 Lucent Technologies Inc. Lucent T echnologies Inc.

1. Global Control Register (GREG8 ) (008)).

2.048 MHz input clock signal used by the receive framer to latch RPD

bipolar violation counter increments once for each rising edge of RLCK.

• Iu indicates an internal pull-up, Id indicates an internal pull-down.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. ‡ Asserting this pin low will initially force RDY to a low state.

• Iu indicates an internal pull-up, Id indicates an internal pull-down.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. ‡ Asserting this pin low will initially force RDY to a low state.

24 Lucent Technologies Inc. Lucent T echnologies Inc. ance state for all inactive time slots. ance state for all inactive time slots.

• Iu indicates an internal pull-up, Id indicates an internal pull-down.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. ‡ Asserting this pin low will initially force RDY to a low state.

high for read accesses; this pin is asserted low for write accesses.

• Iu indicates an internal pull-up, Id indicates an internal pull-down.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. ‡ Asserting this pin low will initially force RDY to a low state.

26 Lucent Technologies Inc. Lucent T echnologies Inc. bus with the contents of the addressed register while DS is low.

• Iu indicates an internal pull-up, Id indicates an internal pull-down.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. ‡ Asserting this pin low will initially force RDY to a low state.

impedance state while CS is high. write access; DT ACK is 1 otherwise. TCK from the boundary-scan test circuitry. for the boundary-scan test circuitry. scan TAP controller to control boundary-scan test operations. initialize/reset the boundary-scan test logic.

• Iu indicates an internal pull-up, Id indicates an internal pull-down.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. ‡ Asserting this pin low will initially force RDY to a low state.

28 Lucent Technologies Inc. Lucent T echnologies Inc.

• Iu indicates an internal pull-up, Id indicates an internal pull-down.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. ‡ Asserting this pin low will initially force RDY to a low state.

connected to the receive framer. Figure 5 illustrates the interfaces of the transmit and receive framer units. Figure 5. Block Diagram of Framer Line Interface

The transmit framer transmits data via the TPD output pin while TND is forced to a 0 state. RND, RCLK, TPD, TND, and TCLK LIU-framer interface. Table 3. AMI Encoding pulses, and no more than 15 zeros may be transmitted consecutively. with a one. The line format (shown in T able 4) limits the data rate of each time slot from 64 kbits/s to 56 kbits/s. (as defined in the signaling control registers with the F and G bits).

32 Lucent Technologies Inc. Lucent T echnologies Inc. simultaneously, only one violation is indicated. Table 4. DS1 ZCS Encoding either RPD or RND). Both excessive zeros and coding violations are indicated as bipolar violations. resents a violation of the bipolar rule and B represents an inserted pulse conforming to the AMI rule. Table 5. DS1 B8ZS Encoding

• Bits 5—6 represent a bipolar violation pair. Bipolar violation with respect to the last previous 1 bit.

The line code used for CEPT is described in ITU Rec. G.703 Section 6.1 as high-density bipolar of order 3 (HDB3). Table 6. ITUHDB3 Coding

34 Lucent Technologies Inc. Lucent T echnologies Inc. and without CRC-4 multiframe formatting. This section describes these framing formats. Table 7. T -Carrier Hierarchy 1.544 Mbits/s T1 data rate.DS1 frames are bundled together to form superframes or extended superframes. Figure 7. T1 Frame Structure

(FRM_PR26 bit 3 or bit 4 must be set to 1). and insert it into bit 7 of time slot 1 of the system data; the other bits of time slot 1 are set to 0. Frame integrity is maintained in both the transmit and receive framer sections. Figure 8. T1 Transparent Frame Structure will insert the 193rd bit of the receive line data into bit 8 of time slot 1 of the transmit system data. bits in time slot 1 are set to 0.

32 TIME-SLOT CHI FRAMETIME SLOT 2 TIME SLOT 3 TIME SLOT 31 TIME SLOT 32

0000000 F B I T

SYSTEM INTERFACE CONTROL REGISTER BITS[2:0] = 000. SYSTEM FRAME SYNC MASK REGISTER FRM_PR26 BIT 3 OR BIT 4 = 1. FRAME INTEGRITY IS MAINT AINED WITH F BIT AND THE SYSTEM P AYLOAD.

36 Lucent Technologies Inc. Lucent T echnologies Inc. D4 superframe format consists of 12 DS1 frames. Table 8 shows the structure of the D4 superframe. Table 8. D4 Superframe Format

1. Frame 1 is transmitted first.
2. Following ANSI T1.403, the bits are numbered 0—2315. Bit 0 is transmitted first. Bits in each DS0 time slot are numbered 1 through 8, and bit

1 of each DS0 is transmitted first.

1. The remote alarm forces bit 2 of each time slot to a 0-state when enabled. The Japanese remote alarm forces framing bit 12 (bit number

2123) to a 1-state when enabled.

1. Signaling option none uses bit 8 for traffic data.
2. Frames 6 and 12 contain the robbed-bit signaling information in bit 8 of each voice channel, when enabled.

The receive framer uses both the FT and FS framing bits during its frame alignment procedure.

TFRA08C13 OCTAL T1/E1 Framer October 2000 38 Lucent Technologies Inc. Lucent T echnologies Inc. Frame Formats (continued) External TFDL Source. Data may be inserted and extracted from the SLC -96 data link from either the external facility data link (TFDL) ports or the SLC -96 data stack. Source selection is controlled by FRM_PR21 bit 6 and FRM_PR29 bit 5—bit 7. The transmit framer synchronizes on TFDL = 000111000111 . . . and forces a superframe boundary based on this pattern. When sourcing an external bit stream, it is the system’s responsibility to ensure that TFDL data contain the line switch field. Table 10. SLC -96 Data Link Block Format Data Link Block Bit Definition Bit Value D 1 (leftmost bit) C 1—concentrator bit 0 or 1 D 2 C 2—concentrator bit 0 or 1 D 3 C 3—concentrator bit 0 or 1 D 4 C 4—concentrator bit 0 or 1 D 5 C 5—concentrator bit 0 or 1 D 6 C 6—concentrator bit 0 or 1 D 7 C 7—concentrator bit 0 or 1 D 8 C 8—concentrator bit 0 or 1 D 9 C 9—concentrator bit 0 or 1 D 10 C 10—concentrator bit 0 or 1 D 11 C 11—concentrator bit 0 or 1 D 12 Spoiler bit 1 0 D 13 Spoiler bit 2 1 D 14 Spoiler bit 3 0 D 15 M 1—maintenance bit 0 or 1 D 16 M 2—maintenance bit 0 or 1 D 17 M 3—maintenance bit 0 or 1 D 18 A1—alarm bit 0 or 1 D 19 A2—alarm bit 0 or 1 D 20 S1—line-switch bit Defined in T able 11 D 21 S2—line-switch bit Defined in T able 11 D 22 S3—line-switch bit Defined in T able 11 D 23 S4—line-switch bit Defined in T able 11 D 24 (rightmost bit) Spoiler bit 4 1

Table 11. SLC -96 Line Switch Message Codes the FDL information in the SLC -96 frame format. parameter registers FRM_PR21 bit 6 = 1 and FRM_PR29 bit 5—bit 7 = x10 (binary). is halted and neither the receive stack interrupt nor receive stack flag are asserted. Table 12. Transmit and Receive SLC -96 Stack Structure with valid data when transmitting stack data. mitted synchronous to the transmit SLC -96 superframe structure. SLC -96 receive stack is not updated when superframe alignment is lost.

1111 I d l e

1 C 2 C 3 C 4 C 5 C 6 C 7 C 8

40 Lucent Technologies Inc. Lucent T echnologies Inc. alignment, error checking, and facility data link transport. T able 13 shows the ESF frame format. Table 13. Extended Superframe (ESF) Structure

1. Frame 1 is transmitted first.
2. The remote alarm is a repeated 1111111100000000 pattern in the DL when enabled.
3. Following ANSI T1.403, the bits are numbered 0—4361. Bit 0 is transmitted first. Bits in each DS0 time slot are numbered 1 through 8, and bit

1 of each DS0 is transmitted first.

1. The C1 to C6 bits are the cyclic redundancy check-6 (CRC-6) checksum bits calculated over the previous extended superframe.
2. Signaling option none uses bit 8 for traffic data.
3. Frames 6, 12, 18, and 24 contain the robbed-bit signaling information in bit 8 of each voice channel, when enabled.

and diagnostics (4 kbits/s).

■ For the purpose of CRC-6 calculation only, every F bit in ESF(n) is set to 1. ESF(n) is altered in no other way. 4631 and the last bit of ESF(n) is the coefficient of the term x0. position of the framing bits. detect a loss of frame alignment is given is T able 14. Table 14. T1 Loss of Frame Alignment Criteria the LFA state, the system may transmit an alarm indication signal (AIS) to the system interface. T or FS) out of 4 consecutive frame bits if FRM_PR10 bit 2 = 1. 2 errored FT bits out of 4 consecutive FT bits if PRM_PR10 bit 2 = 0. SLC -96 2 errored frame bits (F T or FS) out of 4 consecutive frame bits if FRM_PR10 bit 2 = 1. 2 errored FT bits out of 4 consecutive FT bits if FRM_PR10 bit 2 = 0. DDS: Frame 3 errored frame bits (FT or FS) or channel 24 FAS pattern out of 12 consecutive frame bits.

42 Lucent Technologies Inc. Lucent T echnologies Inc. for establishing T1 frame and superframe alignment. Table 15. T1 Frame Alignment Procedures error-free. Once frame alignment is established, then superframe alignment is determined. FS bits must be received error-free to establish superframe alignment. established, then superframe alignment is determined. superframe bit sequence 000111000111. DDS format, there is no search for a superframe structure. ESF Frame and superframe alignment is established simultaneously using the FE framing bit. superframe alignment is established, the CRC-6 receive monitor is enabled.

T o enable signaling, register FRM_PR44 bit 0 (TSIG) must be set to 0. signaling F and G bits. T able 16 shows the state of the transmitted signaling bits as a function of the F and G bits. Table 16. Robbed-Bit Signaling Options

• See register FRM_PR43 bit 3 and bit 4.

setting the F and G bits in the transmit signaling direction. transition from either 0 to 1 or 1 to 0, of the transmitted signaling bit. In the line receive direction, this signaling mode functions identically to the preceding transmit path description.

44 Lucent Technologies Inc. Lucent T echnologies Inc. superframe, while A’ and B’ are transmitted into the next successive SLC -96 12-frame signaling superframe. In the line receive direction, this signaling mode functions identically to the preceding transmit path description. Table 18. 16-State Signaling Format

Figure 11. ITU 2.048 Basic Frame, CRC-4 Multiframe, and Channel Associated Signaling

17 TO 31 ARE ASSIGNED TO TELEPHONE

CHANNELS NUMBERED FROM 1 TO 30.

46 Lucent Technologies Inc. Lucent T echnologies Inc. 8 kHz. The allocation of bits numbered 1 to 8 of the frame is shown in T able 19. Table 19. Allocation of Bits 1 to 8 of the FAS Frame and the NOT FAS Frame ■ Bit 2 of the NOT FAS frames is fixed to 1 to assist in avoiding simulations of the frame alignment signal. Annex C. Bits Sa4—Sa8, where these are not used, should be set to 1 on links crossing an international border. ■ MSB = most significant bit and is transmitted first. ■ LSB = least significant bit and is transmitted last.

framer must be programmed to either transparent framing mode 1 or transparent framing mode 2 (see Table 136. Framer Reset and T ransparent Mode Control Register (FRM_PR26) (Y7A)). Frame integrity is maintained in both the transmit and receive framer sections. Figure 12. CEPT Transparent Frame Structure line payload is transmitted unmodified to the CHI. of receive line data is performed and data is transmitted to the CHI as programmed.

TFRA08C13 OCTAL T1/E1 Framer October 2000 48 Lucent Technologies Inc. Lucent T echnologies Inc. Frame Formats (continued) CEPT Loss of Basic Frame Alignment (LFA) Frame alignment is assumed to be lost when the follow- ing occurs : ■ As described in ITU Rec. G.706 Section 4.1.1, three consecutive incorrect frame alignment signals have been received. ■ So as to limit the effect of spurious frame alignment signals, when bit 2 in time slot 0 in NOT FAS frames has been received with an error on three consecutive occasions. ■ Optionally, as described in ITU Rec. G.706 Section 4.3.2, by exceeding a count of >914 errored CRC-4 blocks out of 1000, with the understanding that a count of ≥915 errored CRC blocks indicates false frame alignment. ■ On demand via the control registers. ■ In the LFA state: ■ No additional FAS or NOT FAS errors are processed. ■ The received remote frame alarm (received A bit) is deactivated. ■ All NOT FAS bit (Si bit, A bit, and Sa4 to Sa8 bits) processing is halted. ■ Receive Sa6 status bits are set to 0. ■ Receive Sa6 code monitoring and counting is halted. ■ All receive Sa stack data updates are halted. The receive Sa stack ready, register FRM_SR4 bit 6 and bit 7, is set to 0. If enabled, the receive Sa stack interrupt bit is set to 0. ■ Receive data link (RFDL) is set to 1 and RFDCLK maintains previous alignment. ■ Optionally, the remote alarm indication (A = 1) may be automatically transmitted to the line if register FRM_PR27 bit 0 is set to 1. ■ Optionally, the alarm indication signal (AIS) may be automatically transmitted to the system if register FRM_PR19 bit 0 is set to 1. ■ If CRC-4 is enabled, loss of CRC-4 multiframe align- ment is forced. ■ If CRC-4 is enabled, the monitoring and processing of CRC-4 checksum errors is halted. ■ If CRC-4 is enabled, all monitoring and processing of received E-bit information is halted. ■ If CRC-4 is enabled, the receive continuous E-bit alarm is deactivated. ■ If CRC-4 is enabled, optionally, E bit = 0 is transmit- ted to the line for the duration of loss of CRC-4 multi- frame alignment if register FRM_PR28 bit 4 is set to ■ If time slot 16 signaling is enabled, loss of the signal- ing multiframe alignment is forced. ■ If time slot 16 signaling is enabled, updating of the signaling data is halted. CEPT Loss of Frame Alignment Recovery Algorithm The receive framer begins the search for basic frame alignment one bit position beyond the position where the LFA state was detected. As defined in ITU Rec. G.706.4.1.2, frame alignment will be assumed to have been recovered when the following sequence is detected as follows: ■ For the first time, the presence of the correct frame alignment signal in frame ■ The absence of the frame alignment signal in the fol- lowing frame detected by verifying that bit 2 of the basic frame is a 1 in frame n + 1. ■ For the second time, the presence of the correct frame alignment in the next frame, n + 2. Failure to meet the second or third bullet above will ini tiate a new basic frame search in frame n + 2.

T able 20 for the complete CRC-4 multiframe. Table 20. ITU CRC-4 Multiframe Structure C1 to C4 = cyclic redundancy check-4 (CRC-4) bits. E = CRC-4 error indication bits. A = remote frame alarm (RFA) bit (active-high); referred to as the A bit. should be set to a binary 1 state.

• The receive E-bit processor will halt the monitoring of the received E bit during the loss of CRC-4 multiframe alignment.

2 C 2 0 011011

4 C 3 0 011011

6 C 4 0 011011

10 C2 0 0 1 1 0 1 1

12 C3 0 0 1 1 0 1 1

13 E 1 A Sa4 Sa5 Sa6 Sa7 Sa8

14 C4 0 0 1 1 0 1 1

15 E 1 A Sa4 Sa5 Sa6 Sa7 Sa8

TFRA08C13 OCTAL T1/E1 Framer October 2000 50 Lucent Technologies Inc. Lucent T echnologies Inc. Frame Formats (continued) The CRC-4 word, located in submultiframe N, is the remainder after multiplication by x4 and then division (modulo 2) by the generator polynomial x4 + x + 1, of the polynomial representation of the submultiframe N – 1. Representing the contents of the submultiframe check block as a polynomial, the first bit in the block, i.e., frame 0, bit 1 or frame 8, bit 1, is taken as being the most significant bit and the least significant bit in the check block is frame 7 or frame 15, bit 256. Similarly, C 1 is defined to be the most significant bit of the remainder and C4 the least significant bit of the remain- der. The encoding procedure, as described in ITU Rec. ■ The CRC-4 bits in the SMF are replaced by binary 0s. ■ The SMF is then acted upon the multiplication/divi- sion process referred to above. ■ The remainder resulting from the multiplication/divi- sion process is stored, ready for insertion into the respective CRC-4 locations of the next SMF . The decoding procedure, as described in ITU Rec. ■ A received SMF is acted upon by the multiplication/ division process referred to above, after having its CRC-4 bits extracted and replaced by 0s. ■ The remainder resulting from this division process is then stored and subsequently compared on a bit-by- bit basis with the CRC bits received in the next SMF . ■ If the remainder calculated in the decoder exactly corresponds to the CRC-4 bits received in the next SMF , it is assumed that the checked SMF is error- free. CEPT Loss of CRC-4 Multiframe Alignment (LTS0MFA) Loss of basic frame alignment forces the receive framer into a loss of CRC-4 multiframe alignment state. This state is reported by way of the status registers FRM_SR1 bit 2. Once basic frame alignment is achieved, a new search for CRC-4 multiframe align- ment is initiated. During a loss of CRC-4 multiframe alignment state the following occurs: ■ The CRC-4 error counter is halted. ■ The CRC-4 error monitoring circuit for errored sec- onds and severely errored seconds is halted. ■ The received E-bit counter is halted. ■ The received E-bit monitoring circuit for errored sec- onds and severely errored seconds at the remote end interface is halted. ■ Receive continuous E-bit monitoring is halted. ■ All receive Sa6 code monitoring and counting func- tions are halted. ■ The updating of the receive Sa stack is halted and the receive Sa stack interrupt is deactivated. ■ Optionally, A = 1 may be automatically transmitted to the line if register FRM_PR27 bit 2 is set to 1. ■ Optionally, E = 0 may be automatically transmitted to the line if register FRM_PR28 bit 4 is set to 1. ■ Optionally, if LTS0MFA monitoring in the perfor- mance counters is enabled, by setting registers FRM_PR14 through FRM_PR17 bit 1 to 1, then these counts are incremented once per second for the duration of the LTS0MFA state.

Lucent Technologies Inc. 51 Preliminary Data Sheet October 2000 TFRA08C13 OCTAL T1/E1 Framer Lucent T echnologies Inc. Frame Formats (continued) CEPT Loss of CRC-4 Multiframe Alignment Recovery Algorithms Several optional algorithms exist in the receive framer. These are selected through programming of register FRM_PR9. CRC-4 Multiframe Alignment Algorithm with 8 ms Timer The default algorithm is as described in ITU Rec. G.706 Section 4.2. The recommendation states that if a condition of assumed frame alignment has been achieved, CRC-4 multiframe alignment is deemed to have occurred if at least two valid CRC-4 multiframe alignment signals can be located within 8 ms, the time separating two CRC-4 multiframe signals being 2 ms or a multiple of 2 ms. The search for the CRC-4 multi- frame alignment signal is made only in bit 1 of NOT FAS frames. If multiframe alignment cannot be achieved within 8 ms, it is assumed that frame align- ment is due to a spurious frame alignment signal and a new parallel search for basic frame alignment is initi- ated. The new search for the basic frame alignment is started at the point just after the location of the assumed spurious frame alignment signal. During this parallel search for basic frame alignment, there is no indication to the system of a receive loss of frame align- ment (RLFA) state. During the parallel search for basic frame alignment and while in primary basic frame align- ment, data will flow through the receive framer to the system interface as defined by the current primary frame alignment. The receive framer will continuously search for CRC-4 multiframe alignment. CRC-4 Multiframe Alignment Algorithm with 100 ms Timer The CRC-4 multiframe alignment with 100 ms timer mode is enabled by setting FRM_PR9 to 0XXXX1X1 (binary). This CRC-4 multiframe reframe mode starts a 100 ms timer upon detection of basic frame alignment. This is a parallel timer to the 8 ms timer. If CRC-4 multi- frame alignment cannot be achieved within the time limit of 100 ms due to the CRC-4 procedure not being implemented at the transmitting side, then an indication is given, and actions are taken equivalent to those specified for loss of basic frame alignment, namely: ■ Optional automatic transmission of A = 1 to the line if register FRM_PR27 bit 3 is set to 1. ■ Optional automatic transmission of E = 0 to the line if register FRM_PR28 bit 5 is set to 1. ■ Optional automatic transmission of AIS to the system if register FRM_PR19 bit 1 is set to 1.

52 Lucent Technologies Inc. Lucent T echnologies Inc. Figure 13. Receive CRC-4 Multiframe Search Algorithm Using the 100 ms Internal Timer

• OPTIONALLY DISABLE TRAFFIC BY TRANSMITTING AIS TO THE SYSTEM
• OPTIONALLY TRANSMIT A = 1 AND E = 0 TO LINE
• INHIBIT INCOMING CRC-4 PERFORMANCE MONITORING BFA SEARCH? IN PRIMARY BFA:
• ENABLE TRAFFIC TO THE SYSTEM
• TRANSMIT A = 0 AND OPTIONALLY E = 0 TO THE LINE
• START 8 ms AND 100 ms TIMERS
• ENABLE PRIMARY BFA LOSS CHECKING PROCESS CRC-4 MFA SEARCH (ITU REC. G.706, SECTION 4.2 - NOTE 2 ) CAN CRC-4 MFA BE FOUND IN 8 ms? PARALLEL BFA SEARCH 100 ms TIMER ELAPSED? YES NO NO NO YES YES ASSUME CRC-4 MULTIFRAME ALIGNMENT:
• CONFIRM PRIMARY BFA ASSOCIATED WITH CRC-4 MFA
• ADJUST PRIMARY BFA IF NECESSARY SET 100 ms TIMER EXPIRATION STATUS BIT TO THE 1 STATE:
• OPTIONALLY TRANSMIT A BIT = 1 TO THE LINE INTERFACE FOR THE DURATION OF LTS0MFA = 1
• OPTIONALLY TRANSMIT AIS TO THE SYSTEM INTERFACE FOR THE START CRC-4 PERFORMANCE MONITORING: CRC-4 COUNT > 914 IN 1 SECOND OR CONTINUE CRC-4 PERFORMANCE MONITORING: YES YES NO NO DURATION OF LTS0MFA = 1 IS 100 ms TRX = 1 YES NO SET INTERNAL 100 ms TIMER EXPIRATION STATUS BIT TO 0:
• IF TRANSMITTING A BIT = 1 TO THE LINE INTERFACE, TRANSMIT A BIT = 0
• IF TRANSMITTING AIS TO THE SYSTEM INTERFACE, ENABLE DATA TRANSMISSION TO THE SYSTEM INTERFACE LFA = 1? GOOD? IS YES NO 100 ms TRX = 1 INTERNAL SET INTERNAL 100 ms TIMER EXPIRATION STATUS BIT TO 1: PRIMARY
• IF TRANSMITTING E = 0 TO THE LINE INTERFACE, TRANSMIT E BIT = 1
• OPTIONALLY TRANSMIT E BIT = 0 TO THE LINE INTERFACE FOR THE DURATION OF LTSOMFA = 1

Figure 14. When the interworking algorithm is enabled, multiframe alignment algorithm. the primary basic frame alignment. — On-demand reframe is requested. CRC-4 multiframe alignment process below it. 8 ms, as described in ITU Rec. G.706 Section 4.2. framing sequence found during the parallel search. plete framing process, and the algorithm is reset.

54 Lucent Technologies Inc. Lucent T echnologies Inc. Figure 14. Receive CRC-4 Multiframe Search Algorithm for Automatic, CRC-4/Non-CRC-4 Equipment

• OPTIONALLY DISABLE TRAFFIC BY TRANSMITTING AIS TO THE SYSTEM
• OPTIONALLY TRANSMIT A BIT = 1 AND E BIT = 0 TO LINE
• INHIBIT INCOMING CRC-4 PERFORMANCE MONITORING BFA SEARCH? IN PRIMARY BFA:
• ENABLE TRAFFIC NOT TRANSMITTING AIS TO THE SYSTEM
• TRANSMIT A = 0 AND OPTIONALLY E = 0 TO THE LINE
• START 400 ms TIMER
• ENABLE PRIMARY BFA LOSS CHECKING PROCESS CRC-4 MFA SEARCH (ITU REC. G.706, SECTION 4.2) CAN CRC-4 MFA BE FOUND IN 8 ms? PARALLEL BFA SEARCH 400 ms TIMER ELAPSED? YES NO NO NO YES YES ASSUME CRC-4-TO-CRC-4 INTERWORKING:
• CONFIRM PRIMARY BFA ASSOCIATED WITH CRC-4 MFA
• ADJUST PRIMARY BFA IF NECESSARY START CRC-4 PERFORMANCE MONITORING: CRC-4 COUNT > 914 IN 1 SECOND OR CONTINUE CRC-4 PERFORMANCE MONITORING: YES YES NO NO
• KEEP A = 0 IN OUTGOING CRC-4 DATA ASSUME CRC-4-TO-NON-CRC-4 INTERWORKING:
• TRANSMIT A BIT = 0 TO THE LINE INTERFACE
• STOP INCOMING CRC-4 PROCESSING
• CONFIRM PRIMARY BFA
• TRANSMIT E BIT = 0 TO THE LINE INTERFACE
• INDICATE “NO CRC-4 MFA” PRIMARY LFA = 1?

line CAS multiframe to the CRC-4 multiframe is arbitrary. Table 21. ITU CEPT Time Slot 16 Channel Associated Signaling Multiframe Structure Frame 0 bits 1—4 define the time slot 16 multiframe alignment. X0—X2 = time slot 16 spare bits defined in FRM_PR41 bit 0—bit 2. YM = yellow alarm, time slot 16 remote multiframe alarm (RMA) bit (1 = alarm condition).

10 A 10 B10 C 10 D 10 A25 B25 C 25 D 25

11 A 11 B11 C 11 D 11 A26 B26 C 26 D 26

12 A 12 B12 C 12 D 12 A27 B27 C 27 D 27

13 A 13 B13 C 13 D 13 A28 B28 C 28 D 28

14 A 14 B14 C 14 D 14 A29 B29 C 29 D 29

15 A 15 B15 C 15 D 15 A30 B30 C 30 D 30

TFRA08C13 OCTAL T1/E1 Framer October 2000 56 Lucent Technologies Inc. Lucent T echnologies Inc. Frame Formats (continued) CEPT Loss of Time Slot 16 Multiframe Align- ment (LTS16MFA) Loss of basic frame alignment forces the receive framer into a loss of time slot 16 signaling multiframe align- ment state. In addition, as defined in ITU Rec. G.732 Section 5.2, time slot 16 signaling multiframe is assumed lost when two consecutive time slot 16 multi- frame 4-bit all-zero patterns is received with an error. In addition, the time slot 16 multiframe is assumed lost when, for a period of two multiframes, all bits in time slot 16 are in state 0. This state is reported by way of the status registers FRM_SR1 bit 1. Once basic frame alignment is achieved, the receive framer will initiate a search for the time slot 16 multiframe alignment. During a loss of time slot 16 multiframe alignment state, the following occurs: ■ The updating of the signaling data is halted. ■ The received control bits forced to the binary 1 state. ■ The received remote multiframe alarm indication sta- tus bit is forced to the binary 0 state. ■ Optionally, the transmit framer can transmit to the line the time slot 16 signaling remote multiframe alarm if register FRM_PR41 bit 4 is set to 1. ■ Optionally, the transmit framer can transmit the alarm indication signal (AIS) in the system transmit time slot 16 data if register FRM_PR44 bit 6 is set to 1. CEPT Loss of Time Slot 16 Multiframe Align- ment Recovery Algorithm The time slot 16 multiframe alignment recovery algo- rithm is as described in ITU Rec. G.732 Section 5.2. The recommendation states that if a condition of assumed frame alignment has been achieved, time slot 16 multiframe alignment is deemed to have occurred when the 4-bit time slot 16 multiframe pattern of 0000 is found in time slot 16 for the first time, and the preced- ing time slot 16 contained at least one bit in the binary 1 state. CEPT Time Slot 0 FAS/NOT FAS Control Bits FAS/NOT FAS Si- and E-Bit Source The Si bit can be used as an 8 kbits/s data link to and from the remote end, or in the CRC-4 mode, it can be used to provide added protection against false frame alignment. The sources for the Si bits that are transmit- ted to the line are the following: ■ CEPT with no CRC-4 and FRM_PR28 bit 0 = 1: the TSiF control bit (FRM_PR28 bit 1) is transmitted in bit 1 of all FAS frames and the TSiNF control bit (FRM_PR28 bit 2) is transmitted in bit 1 of all NOT FAS frames. ■ The CHI system interface (CEPT with no CRC-4 and FRM_PR28 bit 0 = 0) ■ This option requires the received system data (RCHI- DA T A) to maintain a biframe alignment pattern where frames containing Si bit information for the NOT FAS frames have bit 2 of time slot 0 in the binary 1 state followed by frames containing Si bit information for the FAS frames that have bit 2 of time slot 0 in the binary 0 state. This ensures the proper alignment of the Si received system data to the transmit line Si data. Whenever this requirement is not met by the system, the transmit framer will enter a loss of biframe alignment condition (indication is given in the status registers) and then search for the pattern; in the loss of biframe alignment state, transmitted line data is corrupted (only when the system interface is sourcing Sa or Si data). When the transmit framer locates a new biframe alignment pattern, an indica- tion is given in the status registers and the transmit framer resumes normal operations. * Whenever bits (e.g., Si, Sa, etc.) are transmitted from the system transparently, FRM_PR29 must first be momentarily written to 001xxxxx (binary). Otherwise, the transmit framer will not be able to locate the biframe alignment.

Lucent Technologies Inc. 57 Preliminary Data Sheet October 2000 TFRA08C13 OCTAL T1/E1 Framer Lucent T echnologies Inc. CEPT Time Slot 0 FAS/NOT FAS Control Bits (continued) ■ CEPT with CRC-41: manual transmission of E bit = 0: — If FRM_PR28 bit 0 = 0, then the TSiF bit (FRM_PR28 bit 1) is transmitted in bit 1 of frame 13 (E bit) and the TSiNF bit (FRM_PR28 bit 2) is transmitted in bit 1 of frame 15 (E bit). — If FRM_PR28 bit 0 = 1, then each time 0 is written into TSiF (FRM_PR28 bit 1) one E bit = 0 is trans- mitted in frame 13, and each time 0 is written into TSiNF (FRM_PR28 bit 2) one E bit = 0 is transmit- ted in frame 15. ■ CEPT with CRC-41, automatic transmission of E bit = 0: — Optionally, one transmitted E bit is set to 0 by the transmit framer, as described in ITU Rec. G.704 Section 2.3.3.4, for each received errored CRC-4 submultiframe detected by the receive framer if FRM_PR28 bit 3 = 1. — Optionally, as described in ITU Rec. G.704 Sec- tion 2.3.3.4, both E bits are set to 0 while in a received loss of CRC-4 multiframe alignment state 2 if FRM_PR28 bit 4 = 1. — Optionally, when the 100 ms or 400 ms timer is enabled and the timer has expired, as described in ITU Rec. G.706 Section B.2.2, both E bits are set to 0 for the duration of the loss of CRC-4 multi- frame alignment state 2 if FRM_PR28 bit 5 = 1. Otherwise, the E bits are transmitted to the line in the 1 state. NOT FAS A-Bit (CEPT Remote Frame Alarm) Sources The A bit, as described in ITU Rec. G.704 Section 2.3.2, T able 4a/G.704, is the remote alarm indication bit. In undisturbed conditions, this bit is set to 0 and transmitted to the line. In the loss of frame alignment (LFA) state, this bit may be set to 1 and transmitted to the line as determined by register FRM_PR27. The A bit is set to 1 and transmitted to the line for the following conditions: ■ Setting the transmit A bit = 1 control bit by setting register FRM_PR27 bit 7 to 1. ■ Optionally for the following alarm conditions as selected through programming register FRM_PR27. — The duration of loss of basic frame alignment as described in ITU Rec. G.706 Section 4.1.1 3, or ITU Rec. G.706 Section 4.3.24 if register FRM_PR27 bit 0 = 1. — The duration of loss of CRC-4 multiframe align- ment if register FRM_PR27 bit 2 = 1. — The duration of loss of signaling time slot 16 multi- frame alignment if register FRM_PR27 bit 1 = 1. — The duration of loss of CRC-4 multiframe align- ment after either the 100 ms or 400 ms timer expires if register FRM_PR27 bit 3 = 1. — The duration of receive Sa6_8hex 5 if register FRM_PR27 bit 4 = 1. — The duration of receive Sa6_Chex5 if register FRM_PR27 bit 5 = 1. NOT FAS Sa-Bit Sources6 The Sa bits, Sa4—Sa8, in the NOT FAS frame can be a 4 kbits/s data link to and from the remote end. The sources and value for the Sa bits are as follows: ■ The Sa source register FRM_PR29 bit 0—bit 4 if FRM_PR29 bit 7—bit 5 = 000 (binary) and FRM_PR30 bit 4—bit 0 = 11111 (binary). ■ The facility data link external input (TFDL) if register FRM_PR29 bit 7 = 1 and register FRM_PR21 bit 6 = 1. ■ The internal FDL-HDLC if register FRM_PR29 bit 7 = 1 and register FRM_PR21 bit 6 = 0. ■ The Sa transmit stack if register FRM_PR29 bit 7—bit 5 are set to 01x (binary). 1. The receive E-bit processor will halt the monitoring of received E bits during loss of CRC-4 multiframe alignment. 2. Whenever loss of frame alignment occurs, then loss of CRC-4 multiframe alignment is forced. Once frame alignment is estab- lished, then and only then, is the search for CRC-4 multiframe alignment initiated. The receive framer unit, when programmed for CRC-4, can be in a state of LFA and LTS0MFA or in a state of L TS0MFA only, but cannot be in a state of LFA only. 3. LFA is due to framing bit errors. 4. LFA is due to detecting 915 out of 1000 received CRC-4 errored blocks. 5. See T able 29 . Sa6 Bit Coding Recognized by the Receive Framer, for a definition of this Sa6 pattern. 6. Whenever bits (e.g., Si, Sa, etc.) are transmitted from the system transparently, FRM_PR29 must first be momentarily written to 001xxxxx (binary). Otherwise, the transmit framer will not be able to locate the biframe alignment.

5858 Lucent Technologies Inc. transmit framer resumes normal operations. ■ The system transmit interface. Figure 15. Facility Data Link Access Timing of the Transmit and Receive Framer Sections

Sa stack consists of ten 8-bit registers that contain 16 NOT FAS frames of Sa information as shown in T able 22. The transmit stack data may be transmitted either in non-CRC-4 mode or in CRC-4 mode to the line. receive stack interrupts are deactivated. Table 22. Transmit and Receive Sa Stack Structure to the transmit CRC-4 multiframe structure. nous to the CRC-4 multiframe structure.

1 Sa4-1 Sa4-3 Sa4-5 Sa4-7 Sa4-9 Sa4-11 Sa4-13 Sa4-15

2 Sa4-17 Sa4-19 Sa4-21 Sa4-23 Sa4-25 Sa4-27 Sa4-29 Sa4-31

3 Sa5-1 Sa5-3 Sa5-5 Sa5-7 Sa5-9 Sa5-11 Sa5-13 Sa5-15

4 Sa5-17 Sa5-19 Sa5-21 Sa5-23 Sa5-25 Sa5-27 Sa5-29 Sa5-31

5 Sa6-1 Sa6-3 Sa6-5 Sa6-7 Sa6-9 Sa6-11 Sa6-13 Sa6-15

6 Sa6-17 Sa6-19 Sa6-21 Sa6-23 Sa6-25 Sa6-27 Sa6-29 Sa6-31

7 Sa7-1 Sa7-3 Sa7-5 Sa7-7 Sa7-9 Sa7-11 Sa7-13 Sa7-15

8 Sa7-17 Sa7-19 Sa7-21 Sa7-23 Sa7-25 Sa7-27 Sa7-29 Sa7-31

9 Sa8-1 Sa8-3 Sa8-5 Sa8-7 Sa8-9 Sa8-11 Sa8-13 Sa8-15

10 Sa8-17 Sa8-19 Sa8-21 Sa8-23 Sa8-25 Sa8-27 Sa8-29 Sa8-31

60 Lucent Technologies Inc. Lucent T echnologies Inc. Figure 16. Transmit and Receive Sa Stack Accessing Protocol

• BASIC FRAME ALIGNMENT FOUND, OR,
• CRC-4 MULTIFRAME ALIGNMENT FOUND.

31 FRAMES

REGISTERS DURING THIS 1-FRAME INTERVAL. DURING THIS 1-FRAME INTERVAL. CRC-4 DOUBLE MULTIFRAME, ALIGNED TO THE CRC-4 MULTIFRAME. THE INTERNAL RECEIVE STACK INFORMATION REGISTERS. (32 FRAMES), AND DATA IS EXTRACTED ONLY IN THE FRAME ALIGNED STATE. DATA IS EXTRACTED ONLY IN CRC-4 MULTIFRAME ALIGNED STATE.

1 FRAME

Lucent Technologies Inc. 61 Preliminary Data Sheet October 2000 TFRA08C13 OCTAL T1/E1 Framer Lucent T echnologies Inc. CEPT Time Slot 0 FAS/NOT FAS Control Bits (continued) Interrupts indicating that the transmit Sa stack or the receive Sa stack are ready for system access are avail- able, see register FRM_SR4 bit 6 and bit 7. CEPT Time Slot 16 X0—X2 Control Bits Each of the three X bits in frame 0 of the time slot 16 multiframe can be used as a 0.5 kbits/s data link to and from the remote end. The transmitted line X bits are sourced from control register FRM_PR41 bit 0—bit 2. In the loss of TS16 multiframe alignment (LTS16MFA) state, receive X bits are set to 1 in status register FRM_SR53. Signaling Access Signaling information can be accessed by three differ- ent methods: transparently through the CHI, via the control registers, or via the CHI associated signaling mode. Transparent Signaling This mode is enabled by setting register FRM_PR44 bit 0 to 1. Data at the received RCHIDA T A interface passes through the framer undisturbed. The framer generates an arbitrary signaling multiframe in the transmit and receive directions to facilitate the access of signaling information at the system interface. DS1: Robbed-Bit Signaling Microprocessor Control Registers T o enable signaling, register FRM_PR44 bit 0 must be set to 0 (default). The information written into the F and G bits of the transmit signaling registers, FRM_TSR0— FRM_TSR23, define the robbed-bit signaling mode for each channel for both the transmit and receive direc- tions. The per-channel programming allows the system to combine voice channels with data channels within the same frame. The receive-channel robbed-bit signaling mode is always defined by the state of the F and G bits in the corresponding transmit signaling registers for that channel. The received signaling data is stored in the receive signaling registers, FRM_RSR0— FRM_RSR23, while receive framer is in both the frame and superframe alignment states. Updating the receive signaling registers can be inhibited on-demand, by set- ting register FRM_PR44 bit 3 to 1, or automatically when either a framing error event, a loss of frame, or superframe alignment state is detected or a controlled slip event occurs. The signaling inhibit state is valid for at least 32 frames after any one of the following: a framing errored event, a loss of frame and/or super- frame alignment state, or a controlled slip event. In the common channel signaling mode, data written in the transmit signaling registers is transmitted in chan- nel 24 of the transmit line bit stream. The F and G bits are ignored in this mode. The received signaling data from channel 24 is stored in receive signaling registers FRM_RSR0—FRM_RSR23 for T1. Associated Signaling Mode This mode is enabled by setting register FRM_PR44 bit 2 to 1. Signaling information in the associated signaling mode (ASM) is allocated an 8-bit system time slot in conjunc- tion with the payload data information for a particular channel. The default system data rate in the ASM mode is 4.096 Mbits/s. Each system channel consists of an 8-bit payload time slot followed by its correspond- ing 8-bit signaling time slot. The format of the signaling byte is identical to that of the signaling registers. In the ASM mode, writing the transmit signaling regis- ters will corrupt the transmit signaling data. In the trans- mit signaling register ASM (TSR-ASM) format, enabled by setting register FRM_PR44 bit 2 and bit 5 to 1, the system must write into the F and G bit * of the transmit signaling registers to program the robbed-bit signaling state mode of each DS0. The ABCD bits are sourced from the RCHI ports when TSR-ASM mode is enabled. * All other bits in the signaling registers are ignored, while the F and G bits in the received RCHIDA T A stream are ignored.

62 Lucent Technologies Inc. Lucent T echnologies Inc. T able 23 illustrates the ASM time-slot format for valid channels. Table 23. Associated Signaling Mode CHI 2-Byte Time-Slot Format for DS1 Frames

• X indicates bits that are undefined by the framer.

Table 24. Associated Signaling Mode CHI 2-Byte Time-Slot Format for Stuffed Channels

• X indicates bits which are undefined by the framer.

T o enable signaling, register FRM_PR44 bit 0 must be set to 0 (default). ABCD bits of time slot 16 transmitted to the line. The received signaling data from time slot 16 is stored in receive signaling registers FRM_RSR0—FRM_RSR31. ated 8-bit signaling time slot. The format of the signaling byte is identical to the signaling registers. Table 25. Associated Signaling Mode CHI 2-Byte Time-Slot Format for CEPT

• In the CEPT formats, these bits are undefined.

system P bit in the transmitted signaling data is echoed back to the system in the received signaling information.

01111111 XXXXXXXX

66 Lucent Technologies Inc. Lucent T echnologies Inc. Figure 23. Timing Specification for TFS, TLCK, TPD, and TSSFS in CEPT Mode Figure 24. Timing Specification for TFS, TLCK, TPD, and TCRCMFS in CEPT Mode

11 CLOCK CYCLES

Figure 25. Relation Between RLCK1 and Interrupt (Pin AD8) the status registers and all status information should be considered corrupted. by the loss of frame condition for the various framing formats as defined in T able 26.

68 Lucent Technologies Inc. Lucent T echnologies Inc. Table 26. Red Alarm or Loss of Frame Alignment Conditions as for the different framing formats is shown in T able 27. Table 27. Remote Frame Alarm Conditions T or FS) out of 4 consecutive frame bits if FRM_PR10 bit 2 = 1. 2 errored FT bits out of 4 consecutive FT bits if PRM_PR10 bit 2 = 0. SLC -96 2 errored frame bits (F T or FS) out of 4 consecutive frame bits if FRM_PR10 bit 2 = 1. 2 errored FT bits out of 4 consecutive FT bits if FRM_PR10 bit 2 = 0. DDS: Frame 3 errored frame bits (F T or FS) or channel 24 FAS pattern out of 12 consecutive frame bits. errors is enabled in FRM_PR9. loss of frame alignment due to excessive CRC-6 errors is enabled in FRM_PR9. Superframe: D4 Bit 2 of all time slots in the 0 state. Superframe: DDS Bit 6 of time slot 24 in the 0 state. Extended Superframe (ESF) An alternating pattern of eight ones followed by eight 0s in the ESF data link. CEPT: Basic Frame Bit 3 of the NOT FAS frame in the 1 state in three consecutive frames. CEPT: Signaling Multiframe Bit 6 of the time slot 16 signaling frame in the 1 state.

Table 28. Alarm Indication Signal Conditions period of the received frame being less than that of the system frame. One system frame is deleted. received frame being greater than that of the system frame. One system frame is repeated. the LORLCK pin (see T able 69 Interrupt Status Register (FRM_SR0) (Y00)). (GREG8) determine which framer sources the LOPLLCK pin (see T able 69). Figure 26. Timing for Generation of LOPLLCK (Pin F25)

• After a reset, the read and write pointers of the receive path elastic store will be set to a known state.

two consecutive double frame periods (386 bits). is enabled by setting register FRM_PR10 bit 1 to 0. been found. This is enabled by setting register FRM_PR10 bit 1 to 1.

TFRA08C13 OCTAL T1/E1 Framer October 2000 70 Lucent Technologies Inc. Lucent T echnologies Inc. Alarms and Performance Monitoring (continued) ■ Received bipolar violation errors alarm, FRM_SR3 bit 0. This alarm indicates any bipolar decoding error or detection of excessive zeros. ■ Received excessive CRC errors alarm, FRM_SR3 bit 3. In ESF , this alarm is asserted when 320 or more CRC-6 checksum errors are detected within a one second interval. In CEPT, this alarm is asserted when 915 or more CRC-4 checksum errors are detected within a one second interval. ■ The CEPT continuous E-bit alarm (CREBIT) (FRM_SR2 bit 2). CREBIT is asserted when the receive framer detects the following: — Five consecutive seconds where each 1 s interval contains ≥991 received E bits = 0 events. — Simultaneously no LFA occurred. — Optionally, no remote frame alarm (A bit = 1) was detected if register FRM_PR9 bit 0, bit 4, and bit 5 are set to 1. — Optionally, neither Sa6-F hex nor Sa6-Ehex codes were detected if register FRM_PR9 bit 0, bit 4, and bit 6 are set to 1. The 5 s timer is started when the following occurs: — CRC-4 multiframe alignment is achieved. — And optionally, A = 0 is detected if register FRM_PR9 bit 0, bit 4, and bit 5 are set to 1. — And optionally, neither Sa6_F hex* nor Sa6_Ehex* is detected if register FRM_PR9 bit 0, bit 4, and bit 6 are set to 1. The 5 s counter is restarted when the following occurs: — LFA occurs, or — ≥990 E bit = 0 events occur in 1 s, or — Optionally, an A bit = 1 is detected if register FRM_PR9 bit 0, bit 4, and bit 5 are set to 1. — Optionally, a valid Sa6 pattern 1111 (binary) or Sa6 pattern 1110 (binary) code was detected if register FRM_PR9 bit 0, bit 4, and bit 6 are set to 1. This alarm is disabled during loss of frame alignment (LFA) or loss of CRC-4 multiframe alignment (LTS0MFA). ■ Failed state alarm or the unavailable state alarm, FRM_SR5 bit 3 and bit 7 and FRM_SR6 bit 3 and bit 7. This alarm is defined as the unavailable state at the onset of ten consecutive severely errored sec- onds. In this state, the receive framer inhibits incre- menting of the severely errored and errored second counters for the duration of the unavailable state. The receive framer deasserts the unavailable state condi- tion at the onset of ten consecutive errored seconds which were not severely errored. ■ The 4-bit Sa6 codes (FRM_SR2 bit 3—bit 7). Sa6 codes are asserted if three consecutive 4-bit pat- terns have been detected. The alarms are disabled when three consecutive 4-bit Sa6 codes have been detected that are different from the pattern previously detected. The receive framer monitors the Sa6 bits for special codes described in ETSI ETS 300 233: May 1994, Section 9.2. The Sa6 codes are defined in T able 29 and T able 30. The Sa6 codes in T able 29 may be recognized as an asynchronous bit stream in either non-CRC-4 or CRC-4 modes as long as the receive framer is in the basic frame alignment state. In the CRC-4 mode, the receive framer can optionally recognize the received Sa6 codes in T able 29 syn- chronously to the CRC-4 submultiframe structure as long as the receive framer is in the CRC-4 multiframe alignment state (synchronous Sa6 monitoring can be enabled by setting register FRM_PR10 bit 1 to 1). The Sa6 codes in T able 30 are only recognized syn- chronously to the CRC-4 submultiframe and when the receive framer is in CRC-4 multiframe alignment. The detection of three (3) consecutive 4-bit patterns are required to indicate a valid received Sa6 code. The detection of Sa6 codes is indicated in status reg- ister FRM_SR2 bit 3—bit 7. Once set, any three-nib- ble (12-bit) interval that contains any other Sa6 code will clear the current Sa6 status bit. Interrupts may be generated by the Sa6 codes given in Table 29 * See Table 29, for the definition of this Sa6 pattern.

Table 29. Sa6 Bit Coding Recognized by the Receive Framer structure, and are only used for counting NT1 events. Table 30. Sa6 Bit Coding of NT1 Interface Events Recognized by the Receive Framer

72 Lucent Technologies Inc. Lucent T echnologies Inc. Figure 27. The T and V Reference Points for a Typical CEPT E1 Application detected. This alarm is disabled when three or more 10 (binary) patterns are detected in 512 consecutive bits. The search for AUXP is synchronized with the first alternating 10 (binary) pattern as shown in T able 31. Table 31. AUXP Synchronization and Clear Sychronization Process

as required by system needs. DS1 errors are reported in the ET Error registers, FRM_SR20 through FRM_SR35. Table 32. Event Counters Definition register FRM_PR10, bit 2 = 0.

74 Lucent Technologies Inc. Lucent T echnologies Inc. Table 32. Event Counters Definition (continued) consecutive seconds which were not severely errored.

Lucent Technologies Inc. 75 Preliminary Data Sheet October 2000 TFRA08C13 OCTAL T1/E1 Framer Lucent T echnologies Inc. Alarms and Performance Monitoring (continued) Loopback and Transmission Modes Primary Loopback Modes Framer primary loopback mode is controlled by register FRM_PR24. There are seven primary loopback and transmission test modes supported: ■ Line loopback (LLB). ■ Board loopback (BLB). ■ Single time-slot system loopback (STSSLB). ■ Single time-slot line loopback (STSLLB). ■ CEPT nailed-up broadcast transmission (CNUBT). ■ Payload loopback (PLLB). ■ CEPT nailed-up connect loopback (CNUCLB). The loopback and transmission modes are described in detail below: ■ The LLB mode loops the receive line data and clock back to the transmit line. The received data is pro- cessed by the receive framer and transmitted to the system interface. This mode can be selected by set- ting register FRM_PR24 to 001xxxxx (binary). ■ The BLB mode loops the receive system data back to the system after: — The transmit framer processes the data, and — The receive framer processes the data. In the BLB mode, AIS is always transmitted to the line interface. This mode can be selected by setting register FRM_PR24 to 010xxxxx (binary). ■ The STSSLB mode loops one and only one received system time slot back to the transmit system inter- face. The selected looped back time-slot data is not processed by either the transmit framer or the receive framer. The selected time slot does not pass through the receive elastic store buffer and therefore will not be affected by system-AIS, RLFA conditions, or controlled slips events. Once selected, the desired time-slot position has the programmable idle code in register FRM_PR22 transmitted to the line interface one frame before implementing the loopback and for the duration of the loopback. This mode can be selected by setting register FRM_PR24 to 011A 4A3A2A1A0, where A4A3A2A1A0 is the binary address of the selected time slot. ■ The STSLLB mode loops one and only one received line time slot back to the transmit line. The selected time-slot data is looped to the line after being pro- cessed by the receive framer, and it passes through the receive elastic store. The selected time slot has the programmable idle code in register FRM_PR22 transmitted to the system interface one frame before implementing the loopback and for the duration of the loopback. In CEPT , selecting time slot 0 has the effect of deactivating the current loopback mode while no other action will be taken (time slot 0 will not be looped back to the line and should not be cho- sen). This mode can be selected by setting register FRM_PR24 to 100A 4A3A2A1A0, where A4A3A2A1A0 is the binary address of the selected time slot. ■ The CNUBT mode transmits received-line time slot X to the system in time slot X and time slot 0 (of the next frame). Any time slot can be broadcast. This mode can be selected by setting register FRM_PR24 to 101A 4A3A2A1A0 where A4A3A2A1A0 is the binary address of the selected time slot. ■ The PLLB mode loops the received line data and clock back to the transmit line while inserting (replac- ing) the facility data link in the looped back data. T wo variations of the payload loopback are available. In the pass-through framing/CRC bit mode (chosen by setting register FRM_PR24 to 111xxxxx (binary)), the framing and CRC bits are looped back to the line transmit data. In the regenerated framing/CRC bit mode (chosen by setting register FRM_PR24 to 110xxxxx (binary) and register FRM_PR10 bit 3 to 0), the framing and CRC bits are regenerated by the transmit framer. The payload loopback is only available for ESF and CEPT modes. ■ The CNUCLB mode loops received system time slot X back to the system in time slot 0. The selected time slot is not routed through the receive elastic store buffer and, therefore, will not be affected by system- AIS, RLFA conditions, or controlled slips. Any time slot can be looped back to the system. Time slot X transmitted to the line is not affected by this loopback mode. Looping received system time slot 0 has no effect on time slot 0 transmitted to the line, i.e., the transmit framer will always overwrite the FAS and NOT FAS data in time slot 0 transmitted to the line. This mode can be selected by setting register FRM_PR24 to 110A 4A3A2A1A0 and register FRM_PR10 bit 3 to 1, where A4A3A2A1A0 is the binary address of the selected time slot.

76 Lucent Technologies Inc. Lucent T echnologies Inc. ■ Secondary-single time-slot system loopback (S-STSSLB). ■ Secondary-single time-slot line loopback (S-STSLLB). transmitted to the line interface one frame before implementing the loopback and for the duration of the loopback. is looped to the line after being processed by the receive framer and it passes through the receive elastic store. not be looped back to the line and should not be chosen in this mode). mary loopback and test transmission modes. Table 33. Summary of the Deactivation of SSTSSLB and SSTSLLB Modes as a Function of Activating the

78 Lucent Technologies Inc. Lucent T echnologies Inc. these sources may be active at the same time. Signaling must be inhibited while sending these test patterns. register FRM_PR20 bit 0 to 1. ■ The unframed-auxiliary pattern which consists of a continuous bit stream of alternating ones and 0s (. . . 10101010 . . .) enabled by setting register FRM_PR20 bit 1 to 1. and illustrated in Figure 29. — Valid transmit facility data link (TFDL) bit information. Figure 29. 20-Stage Shift Register Used to Generate the Quasi-Random Signal described by ITU Rec. 0.151 and illustrated in Figure 30. — Valid transmit facility data link (TFDL) bit data.

Figure 30. 15-Stage Shift Register Used to Generate the Pseudorandom Signal — Valid transmit facility data link (TFDL) bit data. error can be inserted into the transmitted test pattern by toggling register FRM_PR69 bit 1 from 0 to 1. Table 34. Register FRM_PR69 Test Patterns

80 Lucent Technologies Inc. Lucent T echnologies Inc. terns, and indicates detection in register FRM_SR7 bit 6 and bit 7. pattern is indicated by register FRM_SR7 bit 6 = 1. ure 29. Detection of the pattern is indicated by register FRM_SR7 bit 7 = 1. CEPT mode, the received 256 bit frame must consist of 248 bits of pattern plus 8 bits (TS0) of framing information. detection of these two test patterns. monitor then resumes scanning for pattern candidates. Table 35. Register FRM_PR70 Test Patterns

Lucent Technologies Inc. 81 Preliminary Data Sheet October 2000 TFRA08C13 OCTAL T1/E1 Framer Lucent T echnologies Inc. Alarms and Performance Monitoring (continued) The pattern detector continuously monitors the received line for the particular pattern selected in register FRM_PR70 bit 7—bit 4 (DPTRN). To establish detector lock to the pattern, 256 sequential bits must be detected. Once the detector has locked onto the selected pattern, it will remain locked to the established alignment and count all unexpected bits as single bit errors until register FRM_PR70 bit 2 (DBLKSEL) is set to 0. T o select a pattern or change the pattern to be detected, the following programming sequence must be followed: ■ DBLKSEL (register FRM_PR70 bit 2) is set to 0. ■ The new pattern to be detected is selected by setting register FRM_PR70 bit 7—bit 4 to the desired value. ■ DBLKSEL (register FRM_PR70 bit 2) is set to 1.

82 Lucent Technologies Inc. Lucent T echnologies Inc. Table 36. Automatic Enable Commands

Table 37. On-Demand Commands

■ The FDL pins (RFDL, RFDLCK, TFDL, and TFDLCK). Figure 15 shows the timing of these signals. framed in HDLC format or passed through transparently. Figure 31. TFRA08C13 Facility Data Link Access Timing of the Transmit and Receive Framer Sections along with a status of frame (SF) byte. along with a status of frame (SF) byte. in the FDL receive FIFO (register FDL_SR4). Communications Research, Inc.

match character and all subsequent bytes are placed into the FDL receive FIFO. The FDL interface to the receive framer is illustrated in Figure 32. Figure 32. Block Diagram for the Receive Facility Data Link Interface detection of a valid BOM and then cleared when read. ten into the received ANSI FDL status register FDL_SR3 when the entire code is received. 10 using register FDL_PR0 bit 4—bit 7.

86 Lucent Technologies Inc. Lucent T echnologies Inc. The received ANSI FDL status byte, register FDL_SR3, has the following format. Table 38. Receive ANSI Code receive FDL FIFO along with the status of frame byte. Table 39. Performance Re left most bit (bit 8) first. The definition of each PRM field is shown in T able 40, and octet content is shown in T able 41.

3 TEI EA

5 G 3L VG 4U 1U 2G 5S LG 6

6 F ES EL BG 1 R G 2 N mN l

7 G 3L VG 4U 1U 2G 5S LG 6

8 F ES EL BG 1 R G 2 N mN l

9 G 3L VG 4U 1U 2G 5S LG 6

10 FE SE LB G1 R G2 Nm Nl

11 G3 LV G4 U1 U2 G5 SL G6

12 FE SE LB G1 R G2 Nm Nl

15 Fla

Lucent Technologies Inc. 87 Preliminary Data Sheet October 2000 TFRA08C13 OCTAL T1/E1 Framer Lucent T echnologies Inc. Facility Data Link (continued) Table 40. FDL Performance Report Message Field Definition Table 41. Octet Contents and Definition

Contents

1 01111110 Openin g LAPD Flag 2 00111000 00111010 From CI: SAPI = 14, C/R = 0, EA = 0 From Carrier: SAPI = 14, C/R = 1, EA = 0 3 00000001 TEI = 0, EA = 1 4 00000011 Unacknowled ged Frame 5, 6 Variable Data for Latest Second (T) 7, 8 Variable Data for Previous Second (T – 1) 9, 10 Variable Data for Earlier Second (T – 2) 11, 12 Variable Data for Earlier Second (T – 3) 13, 14 Variable CRC-16 Frame Check Se quence 15 01111110 Closin g LAPD Flag

88 Lucent Technologies Inc. Lucent T echnologies Inc. frames, reconstructs data bytes, provides bit destuffing as necessary, and loads parallel data in the receive FIFO. bytes are stored in the receive FIFO. The SF byte has the following format. Table 42. Receive Status of Frame Byte used and are set to 0. A good frame is implied when the SF status byte is 00 (hex). FDL_SR0 bit 6 (FRIDL) interrupt is issued whenever 15 or more continuous ones have been detected.

Lucent Technologies Inc. 89 Preliminary Data Sheet October 2000 TFRA08C13 OCTAL T1/E1 Framer Lucent T echnologies Inc. Facility Data Link (continued) The receive queue status bits, register FDL_SR2 bit 0—bit 6 (FRQS), are updated as bytes are loaded into the receive FIFO. The SF status byte is included in the byte count. When the first SF status byte is placed in the FIFO, register FDL_SR0 bit 4 (FREOF) is set to 1, and the status freezes until the FIFO is read. As bytes are read from the FIFO, the queue status decrements until it reads 1. The byte read when register FDL_SR2 bit 0—bit 6 = 0000001 and the FREOF bit is 1 is the SF status byte describing the error status of the frame just read. Once the first SF status byte is read from the FIFO, the FIFO status is updated to report the number of bytes to the next SF status byte, if any, or the number of additional bytes present. When FREOF is 0, no SF status byte is currently present in the FIFO, and the FRQS bits report the number of bytes present. As bytes are read from the FIFO, the queue status decre- ments with each read until it reads 0 when the FIFO is totally empty. The FREOF bit is also 0 when the FIFO is completely empty. Thus, the FRQS and FREOF bit pro- vide a mechanism to recognize the end of 1 frame and the beginning of another. Reading the FDL receiver status register does not affect the FIFO buffers. In the event of a receiver overrun, an SF status byte is written to the receive FIFO. Multiple SF status bytes can be present in the FIFO. The FRQS reports only the num- ber of bytes to the first SF status byte. If FRQS is 0, do not read the receive FIFO. A read will result in the cor- ruption of receive FIFO. T o allow users to tailor receiver FIFO service intervals to their systems, the receiver interrupt level bits in reg- ister FDL_PR6 bit 0—bit 5 (FRIL) are provided. These bits are coded in binary and determine when the receiver full interrupt, register FDL_SR0 bit 3 (FRF), is asserted. The interrupt pin transition can be masked by setting register FDL_PR2 bit 3 (FRFIE) to 0. The value programmed in the FRIL bits equals the total number of bytes necessary to be present in the FIFO to trigger an FRF interrupt. The FRF interrupt alone is not sufficient to determine the number of bytes to read, since some of the bytes may be SF status bytes. The FRQS bits and FREOF bit allow the user to determine the number of bytes to read. The FREOF interrupt can be the only interrupt for the final frame of a group of frames, since the number of bytes received to the end of the frame cannot be sufficient to trigger an FRF interrupt. Programming Note: Since the receiver writing to the receive FIFO and the host reading from the receive FIFO are asynchronous events, it is possible for a host read to put the number of bytes in the receive FIFO just below the programmed FRIL level and a receiver write to put it back above the FRIL level. This causes a new FRF interrupt, and has the potential to cause software problems. It is recommended that during service of the FRF interrupt, the FRF interrupt be masked FRFIE = 0, and the interrupt register be read at the end of the ser- vice routine, discarding any FRF interrupt seen, before unmasking the FRF interrupt. Receiver Overrun A receiver overrun occurs if the 64-byte limit of the receiver FIFO is exceeded, i.e., data has been received faster than it has been read out of the receive FIFO. Upon overrun, an SF status byte with the overrun bit (bit 5) set to 1 replaces the last byte in the FIFO. The SF status byte can have other error conditions present. For example, it is unlikely the CRC is correct. Thus, care should be taken to prioritize the possible frame errors in the software service routine. The last byte in the FIFO is overwritten with the SF status byte regard- less of the type of byte (data or SF status) being over- written. The overrun condition is reported in register FDL_SR0 bit 5 and causes the interrupt pin to be asserted if it is not masked (register FDL_PR2 bit 5 (FROVIE)). Data is ignored until the condition is cleared and a new frame begins. The overrun condition is cleared by reading register FDL_SR0 bit 5 and read- ing at least 1 byte from the receive FIFO. Because mul- tiple frames can be present in the FIFO, good frames as well as the overrun frame can be present. The host can determine the overrun frame by looking at the SF status byte.

90 Lucent Technologies Inc. Lucent T echnologies Inc. The FDL interface of the transmit framer is shown in Figure 33, indicating the priority of the FDL sources. mission. Idle code is generated by the FDL unit when no other transmission is enabled. The FDL transmitter is enabled by setting register FDL_PR1 bit 3 to 1. Figure 33. Block Diagram for the Transmit Facility Data Link Interface the ANSI T1.403 ESF bit-oriented messages automatically through the FDL bit in the frame. register FDL_PR10 bit 7 (FTANSI) is set to 1.

transmits the ANSI performance report message once every second. and closing flags) to the PRM messages and transmits it to the framer for transmission to the line. T able 39—T able 41 show the complete format of the PRM HDLC packet. Table 43. HDLC Frame Format 16 bits preceding the closing flag are the frame check sequence, cyclic redundancy check (CRC), bits. is assumed to have been inserted and is deleted (bit destuffing).

TFRA08C13 OCTAL T1/E1 Framer October 2000 92 Lucent Technologies Inc. Lucent T echnologies Inc. Facility Data Link (continued) Flags* All flags have the bit pattern 01111110 and are used for frame synchronization. The FDL HDLC block automati- cally sends two flags between frames. If the chip-con- figuration register FDL_PR0 bit 1 (FLAGS) is cleared to 0, the ones idle byte (11111111) is sent between frames if no data is present in the FIFO. If FLAGS is set to 1, the FDL HDLC block sends continuous flags when the transmit FIFO is empty. The FDL HDLC does not transmit consecutive frames with a shared flag; there- fore, two successive flags will not share the intermedi- ate 0. An opening flag is generated at the beginning of a frame (indicated by the presence of data in the transmit FIFO and the transmitter enable register FDL_PR1 bit 3 = 1). Data is transmitted per the HDLC protocol until a byte is read from the FIFO while register FDL_PR3 bit 7 (FTFC) set to 1. The FDL HDLC block follows this last user data byte with the CRC sequence and a clos- ing flag. The receiver recognizes the 01111110 pattern as a flag. Two successive flags may or may not share the intermediate 0 bit and are identified as two flags (i.e., both 011111101111110 and 0111111001111110 are recognized as flags by the FDL HDLC block). When the second flag is identified, it is treated as the closing flag. As mentioned above, a flag sequence in the user data or CRC bits is prevented by zero-bit insertion and dele- tion. The HDLC receiver recognizes a single flag between frames as both a closing and opening flag. Aborts An abort is indicated by the bit pattern of the sequence 01111111. A frame can be aborted by writing a 1 to register FDL_PR3 bit 6 (FTABT). This causes the last byte written to the transmit FIFO to be replaced with the abort sequence upon transmission. Once a byte is tagged by a write to FTABT , it cannot be cleared by subsequent writes to register FDL_PR3. FTABT has higher priority than FDL transmit frame complete (FTFC), but FTABT and FTFC should never be set to 1 simultaneously since this causes the transmitter to enter an invalid state requiring a transmitter reset to clear. A frame should not be aborted in the very first byte following the opening flag. An easy way to avoid this situation is to first write a dummy byte into the queue and then write the abort command to the queue. When receiving a frame, the receiver recognizes the abort sequence whenever it receives a 0 followed by seven consecutive ones. The receive FDL unit will abort a frame whenever the receive framer detects a loss of frame alignment. This results in the abort bit, and possibly the bad byte count bit and/or bad CRC bits, being set in the status of frame status byte (see T able 42) which is appended to the receive data queue. All subsequent bytes are ignored until a valid opening flag is received. Idles In accordance with the HDLC protocol, the HDLC block recognizes 15 or more contiguous received ones as idle. When the HDLC block receives 15 contiguous ones, the receiver idle bit register FDL_SR0 bit 6 (RIDL) is set. For transmission, the ones idle byte is defined as the binary pattern 11111111 (FF (hex)). If the FLAGS con- trol bit in register FDL_PR0 bit 1 is 0, the ones idle byte is sent as the time-fill byte between frames. A time-fill byte is sent when the transmit FIFO is empty and the transmitter has completed transmission of all previous frames. Frames are sent back-to-back otherwise. CRC-16 For given user data bits, 16 additional bits that consti- tute an error-detecting code (CRC-16) are added by the transmitter. As called for in the HDLC protocol, the frame check sequence bits are transmitted most signifi- cant bit first and are bit stuffed. The cyclic redundancy check (or frame check sequence) is calculated as a function of the transmitted bits by using the ITU-T stan- dard polynomial: x 16 + x 12 + x 5 + 1 The transmitter can be instructed to transmit a cor- rupted CRC by setting register FDL_PR2 bit 7 (FTB- CRC) to 1. As long as the FTBCRC bit is set, the CRC is corrupted for each frame transmitted by logically flip- ping the least significant bit of the transmitted CRC. The receiver performs the same calculation on the received bits after destuffing and compares the results to the received CRC-16 bits. An error indication occurs if, and only if, there is a mismatch. * Regardless of the time-fill byte used, there always is an opening and closing flag with each frame. Back-to-back frames are separated by two flags.

Lucent Technologies Inc. 93 Preliminary Data Sheet October 2000 TFRA08C13 OCTAL T1/E1 Framer Lucent T echnologies Inc. Facility Data Link (continued) Transmit FDL FIFO T ransmit FDL data is loaded into the 64-byte transmit FIFO via the transmit FDL data register, FDL_PR4. The transmit FDL status register indicates how many addi- tional bytes can be added to the transmit FIFO. The transmit FDL interrupt trigger level register FDL_PR3 bit 0—bit 5 (FTIL) can be programmed to tailor service time intervals to the system environment. The transmit- ter empty interrupt bit is set in the FDL interrupt status register FDL_SR0 bit 1 (FTEM) when the transmit FIFO has sufficient empty space to add the number of bytes specified in register FDL_PR3 bit 0—bit 5. There is no interrupt indicated for a transmitter overrun that is writing more data than empty spaces exist. Overrun- ning the transmitter causes the last valid data byte writ- ten to be repeatedly overwritten, resulting in missing data in the frame. Data associated with multiple frames can be written to the transmit FIFO by the controlling microprocessor. However, all frames must be explicitly tagged with a transmit frame complete, register FDL_PR3 bit 7 (FTFC), or a transmit abort, register FDL_PR3 bit 6 (FTABT). The FTFC is tagged onto the last byte of a frame written into the transmitter FIFO and instructs the transmitter to end the frame and attach the CRC and closing flag following the tagged byte. Once written, the FTFC cannot be changed by another write to register FDL_PR3. If FTFC is not written before the last data byte is read out for transmission, an underrun occurs (FDL_SR0 bit 2). When the transmitter has completed a frame, with a closing flag or an abort sequence, reg- ister FDL_SR0 bit 0 (FTDONE) is set to 1. An interrupt is generated if FDL_PR2 bit 0 (FTDIE) is set to 1. Sending 1-Byte Frames Sending 1-byte frames with an empty transmit FIFO is not recommended. If the FIFO is empty, writing two data bytes to the FIFO before setting FTFC provides a minimum of eight TFDLCK periods to set FTFC. When 1 byte is written to the FIFO, FTFC must be written within 1 TFDLCK period to guarantee that it is effective. Thus, 1-byte frames are subject to underrun aborts. One-byte frames cannot be aborted with FTABT . Plac- ing the transmitter in ones-idle mode, register FDL_PR0 bit 1 (FLAGS) = 0, lessens the frequency of underruns. If the transmit FIFO is not empty, then 1-byte frames present no problems. Transmitter Underrun After writing a byte to the transmit queue, the user has eight TFDLCK cycles in which to write the next byte before a transmitter underrun occurs. An underrun occurs when the transmitter has finished transmitting all the bytes in the queue, but the frame has not yet been closed by setting FTFC. When a transmitter underrun occurs, the abort sequence is sent at the end of the last valid byte transmitted. A FTDONE interrupt is generated, and the transmitter reports an underrun abort until the interrupt status register is read. Using the Transmitter Status and Fill Level The transmitter-interrupt level bits, register FDL_PR3 bit 0—bit 5, allow the user to instruct the FDL HDLC block to interrupt the host processor whenever the transmitter has a predetermined number of empty loca- tions. The number of locations selected determines the time between transmitter empty, register FRM_SR0 bit 1 (FTEM), interrupts. The transmitter status bits, regis- ter FDL_SR1, report the number of empty locations in the FDL transmitter FIFO. The transmitter empty dynamic bit, register FDL_SR1 bit 7 (FTED), like the FTEM interrupt bit, is set to 1 when the number of empty locations is less than or equal to the pro- grammed empty level. FTED returns to 0 when the transmitter is filled to above the programmed empty level. Polled interrupt systems can use FTED to deter- mine when they can write to the FDL transmit FIFO. Transparent Mode The FDL HDLC block can be programmed to operate in the transparent mode by setting register FDL_PR9 bit 6 (FTRANS) to 1. In the transparent mode of operation, no HDLC processing is performed on user data. The transparent mode can be exited at any time by setting FDL_PR9 bit 6 (FTRANS) to 0. It is recommended that the transmitter be disabled when changing in and out of transparent mode. The transmitter should be reset by setting FDL_PR1 bit 5 (FTR) to 1 whenever the mode is changed.

9494 Lucent Technologies Inc. ABT) interrupt is not active in the transparent mode. of 111 indicates byte alignment. character to the receive FIFO. Table 44. Receiver O bit appears to affect only the receiver. FDL_PR1 bit 2, is set. Data loaded to receive FIFO immediately. recognized. No data to receive FIFO until match is detected.

The serial link interface can operate in two diagnostic loopback modes: (1) local loopback and (2) remote loopback. cannot be enabled simultaneously. ■ TFDLCK clocks both the transmitter and the receiver. ■ The transmitter and receiver must both be enabled. ■ The transmitter output is internally connected to the receiver input. ■ The RFDL input is ignored. ■ The communication between the transmit and receive FIFO buffers and the microprocessor continues normally. Figure 34. Local Loopback Mode ■ T ransmitted data is retimed with a maximum delay of 2 bits. ■ Received data is retransmitted on the TFDL.

Figure 35. Remote Loopback Mode

2.048 Mbits/s to the line interface clock rate of either

reference and the CHICK signal as the variable signal. phase difference between DIV-CHICK and DIV-RLCK. and setting FRM_PR45 bit 4 to 1.

Figure 36. TFRA08C13 Phase Detector Circuitry

TFRA08C13 OCTAL T1/E1 Framer October 2000 98 Lucent Technologies Inc. Lucent T echnologies Inc. Framer-System Interface DS1 Modes The DS1 framing formats require rate adaptation from the 1.544 Mbits/s line interface bit stream to the system interface which functions at multiples of a 2.048 Mbits/s bit stream. The rate adaptation results in the need for eight stuffed time slots on the system interface since there are only 24 DS1 (1.544 Mbits/s) payload time slots while there are 32 system (2.048 Mbits/s) time slots. Placement of the stuffed time slots is defined by register FRM_PR43 bit 0—bit 2. CEPT Modes The framer maps the line time slots into the corre- sponding system time slot one-to-one. Framing time slot 0, the FAS and NFAS bytes, are placed in system time slot 0. Receive Elastic Store The receive interface between the framer and the sys- tem CHI includes a 2-frame elastic store buffer to enable rate adaptation. The receive line elastic store buffer contains circuitry that monitors the read and write pointers for potential data overrun and underrun (slips) conditions. Whenever this slip circuitry deter- mines that a slip may occur in the receive elastic store buffer, it will adjust the read pointer such that a con- trolled slip is performed. The controlled slip is imple- mented by dropping or repeating a complete frame at the frame boundaries. The occurrence of controlled slips in the receive elastic store are indicated in the sta- tus register FRM_SR3 bit 6 and bit 7. Transmit Elastic Store The transmit interface between the framer and the sys- tem CHI includes a 2-frame elastic store buffer to enable rate adaptation. The line transmit clock applied to PLLCK[1—8] must be phase-locked to CHICK. No indication of a slip in the transmit elastic store is given. Concentration Highway Interface Each framer has a dual, high-speed, serial interface to the system known as the CHI. This flexible bus archi- tecture allows the user to directly interface to other Lucent components which use this interface, as well as to Mitel* and AMD † TDM highway interfaces, with no glue logic. Configured via the highway control registers FRM_PR45 through FRM_PR66, this interface can be set up in a number of different configurations. The following is a list of the CHI features: ■ Lucent T echnologies standard interface for communi- cation devices. ■ T wo pairs of transmit and receive paths to carry data in 8-bit time slots. ■ Programmable definition of highways through offset and clock-edge options which are independent for transmit and receive directions. ■ Programmable idle code substitution of received time slots. ■ Programmable 3-state control of each transmit time slot. ■ Independent transmit and receive framing signals to synchronize each direction of data flow. ■ An 8 kHz frame synchronization signal internally generated from the received line clock. ■ Compatible with Mitel and AMD PCM highways. Supported is the optional configuration of the CHI which presents the signaling information along with the data in any framing modes when the device is pro- grammed for the associated signaling mode (ASM). This mode is discussed in the signaling section. Data can be transmitted or received on either one of two interface ports, called CHIDA T A and CHIDA TAB. The user-supplied clock (CHICLK) controls the timing on the transmit or receive paths. Individual time slots are referenced to the frame synchronization (CHIFS) pulse. Each frame consists of 32 time slots at a pro- grammable data rate of 2.048 Mbits/s, 4.096 Mbits/s, or

8.192 Mbits/s requiring a clock (CHICK) of the same

rate. The clock and data rates of the transmit and receive highways are programmed independently. * Mitel is a registered trademark of Mitel Corporation. † AMD is a registered trademark of Advanced Micro Devices, Inc.

The CHI parameters that define the receive and transmit paths are given in Table 45. Table 45. Summary of the TFRA08C13’s Concentration Highway Interface Parameters forced to a high-impedance state for all CHI transmitted time slots. path is not affected by this mode. allows two CHIs to interleave frames on a common bus. is identical to the timing for CHIFS in CHIMM = 0 mode. falling (or rising) edge of CHICK. rate. The default state (00) enables the 2.048 Mbits/s.

100 Lucent Technologies Inc. Lucent T echnologies Inc. the falling (or rising) edge of CHICK. the falling (or rising) edge of CHICK. time slot. A 0 forces the CHI transmit highway time slot to be 3-stated. ister FRM_PR22 to the line interface. active time slot. A 0 enables TCHIDA T A; a 1 enables the TCHIDA T AB. time slot. A 0 enables RCHIDA T A; a 1 enables the RCHIDA T AB. set is the number of CHICK cycles by which the first bit is delayed. is the number of CHICK cycles by which the first bit is delayed. 16 bits where 8 bits are data and the remaining 8 bits are signaling information. bits define the location of the eight stuffed CHI (unused) time slots. Table 45. Summary of the TFRA08C13’s Concentration Highway Interface Parameters (continued)

bit 2 (ASM) = 0). The frames are 125 ms long and consist of 32 contiguous time slots. In DS1 frame modes, the CHI frame consists of 24 payload time slots and eight stuffed (unused) time slots. In CEPT frame modes, the CHI frame consists of 32 payload time slots.

• The position of the stuffed time is controlled by register FRM_PR43 bit 0—bit 2.

Figure 37. Nominal Concentration Highway Interface Timing (for FRM_PR43 bit 0—bit 2 = 100 (Binary))

8.192 Mbits/s CHI:

4.096 Mbits/s CHI:

2.048 Mbits/s CHI:

24 VALID TIME SLOTS HIGH IMPEDANCE FRAME 2TCHIDA T A

32 VALID TIME SLOTS

24 VALID TIME SLOTS

8 STUFFED

102 Lucent Technologies Inc. Lucent T echnologies Inc. mode is valid only for 4.096 Mbits/s and 8.192 Mbits/s CHI rates. Figure 38. CHIDTS Mode Concentration Highway Interface Timing

8.192 Mbits/s CHI

4.096 Mbits/s CHI

(RCHIDTS) = 0). The frames are 125 ms long and consist of 32 contiguous 16-bit time slots. In CEPT modes, each frame consists of 32 time slots. Each time slot consists of two octets. Figure 39. Associated Signaling Mode Concentration Highway Interface Timing and CHIDTS enabled (registers FRM_PR65 bit 1 (TCHIDTS) = 1 and FRM_PR66 bit 1 (RCHIDTS) = 1).

• High-impedance state for TCHIDA TA and not received (don’t care) for RCHIDA TA.

Figure 40. CHI Timing with ASM and CHIDTS Enabled

1 TIME SLOT

8.192 Mbits/s CHI WITH ASM (ASSOCIA TED SIGNALING MODE) ENABLED

106 Lucent Technologies Inc. Lucent T echnologies Inc. Figure 44. Block Diagram of the TFRA08C13's Boundary-Scan Test Logic

TCK edge rises. Figure 45 shows the T AP controller state diagram. Figure 45. BS TAP Controller State Diagram

108 Lucent Technologies Inc. Lucent T echnologies Inc. Table 47. TAP Controller States in the Data Register Branch Table 48. TAP Controller States in the Instruction Register Branch SELECT -DR This state is used for branching to the test data register control. TCK in the state. The TDO output driver is active. EXIT(1/2)-DR This temporary state causes a branch to a subsequent state. P AUSE-DR The input and output of test data can be interrupted in this state. the falling edge of TCK in this state. SELECT -IR This state is used for branching to the instruction register control. parallel to the rising edge of TCK in this state. of TCK in the state. The TDO output driver is active. EXIT(1/2)-IR This temporary state causes a branch to a subsequent state. P AUSE-IR The input and output of instructions can be interrupted in this state. to the falling edge of TCK in this state.

Table 49. TFRA08C13’s Boundary-Scan Instructions IDCODE 0001 Identification NORMAL Read Manuf. the test-logic-reset controller state and at powerup. tion selects the BS register as the test data register. in the UPDA TE-DR state on the falling edge of TCK.

110 Lucent Technologies Inc. Lucent T echnologies Inc. appears first when the data is being read out. request. Please call 1-800-TECKFAX (1-800-832-5329). Table 50. IDCODE Register pattern at the TFRA08C13 outputs does not become corrupted.

through a 12-bit address bus and an 8-bit data bus. status registers, the INTERRUPT output will deassert. alarm status register bit remains set. Table 51. Microprocessor Configuration Modes

• The DT ACK signal is asynchronous to the MPCLK signal.

112 Lucent Technologies Inc. Lucent T echnologies Inc. same set of pins in all modes. Table 52. Mode [1 and 3] Microprocessor Pin Definitions

1. INTERRUPT output is synchronous to the internal clock source RLCK-LIU. If RLCK_LIU is absent, the reference clock for interrupt timing

becomes an interval 2.048 MHz clock derived from the CHI clock.

1. In the default (reset) mode, INTERRUPT is active-high. It can be made active-low by setting register GREG4 bit 6 to 1.
2. The DTACK output is asynchronous to MPCLK.
3. See T able 2. Pin Descriptions.
4. MPCLK is needed if RDY output is required to be synchronous to MPCLK.

required to be synchronous to MPCLK. Table 53. Micro

may be corrected by a device reset. Table 54. TFRA08C13 Re

• Core registers are common to all circuit blocks on the TFRA08C13.

load of 50 pF . The D[7:0] outputs are rated for a 100 pF load.

• See Product Advisory AY99-041 for more information.

114 Lucent Technologies Inc. Lucent T echnologies Inc. Table 55. Microprocessor Interface I/O Timing Specifications Note: The read and write timing diagrams for all four microprocessor interface modes are shown in Figure 46—Figure 49.

Table 55. Microprocessor Interface I/O Timing Specifications (continued) Note: The read and write timing diagrams for all four microprocessor interface modes are shown in Figure 46—Figure 49.

118 Lucent Technologies Inc. Lucent T echnologies Inc. Both hardware and software resets are provided. for E1, is required to guarantee a complete reset. ing a reset of the global registers. not alter the value of the parameter/control registers. read, the interrupt for that condition is deasserted. Table 56. Status Register and Corresponding Interrupt Enable Register for Functional Blocks mable through register GREG4 bit 4 and bit 6 and may take on the following state, see T able 57 below. Table 57. Asserted Value and Deasserted State for GREG4 Bit 4 and Bit 6 Logic Combinations

01 L o w H i g h —

T able 58 is an overview of the register architecture. The table is a summary of the register function and address. Complete detail of each register is given in the following sections. Table 58. Register Summary

• The most significant digit, designated by Y , is used to identify each framer (for framer 1—framer 8, Y = 2—9, respectively).

120 Lucent Technologies Inc. Lucent T echnologies Inc. Table 58. Register Summary (continued)

• The most significant digit, designated by Y , is used to identify each framer (for framer 1—framer 8, Y = 2—9, respectively).

• The most significant digit, designated by Y , is used to identify each framer (for framer 1—framer 8, Y = 2—9, respectively).

122 Lucent Technologies Inc. Lucent T echnologies Inc.

• The most significant digit, designated by Y , is used to identify each framer (for framer 1—framer 8, Y = 2—9, respectively).

†For FDL 1 and FDL 2, Y = A; for FDL 3 and FDL 4, Y = B; for FDL 5 and FDL 6, Y = C; for FDL 7 and FDL 8, Y = D.

registers is 000 (hex) to 009 (hex). These registers control the eight channels of the TFRA08C13. terminal control register, device identification register, and global internal interface control register. Table 59. Global Register Set (0x000—0x009)

• The following section describes the global registers inT able 60—T able 67.

A bit set to 1 indicates the block has recently generated an interrupt. This register is cleared on read. Table 60. Framer Block Interrupt Status Register (GREG0) (000)

000 FRMR8_I

001 FRMR8IE

002 FDL8_INT

003 FDL8IE

004 Reserved

008 Reserved

009 EIPLLCK8

0 FRMR1_INT Framer 1 Interrupt. A 1 indicates framer 1 generated an interrupt. 1 FRMR2_INT Framer 2 Interrupt. A 1 indicates framer 2 generated an interrupt. 2 FRMR3_INT Framer 3 Interrupt. A 1 indicates framer 3 generated an interrupt. 3 FRMR4_INT Framer 4 Interrupt. A 1 indicates framer 4 generated an interrupt. 4 FRMR5_INT Framer 5 Interrupt. A 1 indicates framer 5 generated an interrupt. 5 FRMR6_INT Framer 6 Interrupt. A 1 indicates framer 6 generated an interrupt. 6 FRMR7_INT Framer 7 Interrupt. A 1 indicates framer 7 generated an interrupt. 7 FRMR8_INT Framer 8 Interrupt. A 1 indicates framer 8 generated an interrupt.

124 Lucent Technologies Inc. Lucent T echnologies Inc. This register enables the individual blocks to assert the interrupt pin high. Table 61. Framer Block Interrupt Enable Register (GREG1) (001) Table 62. FDL Block Interrupt Status Register (GREG2) (002) This register enables the individual blocks to assert the interrupt pin high. Table 63. FDL Block Interrupt Enable Register (GREG3) (003) 0 FRMR1IE Framer 1 Interrupt Enable. A 1 enables framer 1 interrupts. 1 FRMR2IE Framer 2 Interrupt Enable. A 1 enables framer 2 interrupts. 2 FRMR3IE Framer 3 Interrupt Enable. A 1 enables framer 3 interrupts. 3 FRMR4IE Framer 4 Interrupt Enable. A 1 enables framer 4 interrupts. 4 FRMR5IE Framer 5 Interrupt Enable. A 1 enables framer 5 interrupts. 5 FRMR6IE Framer 6 Interrupt Enable. A 1 enables framer 6 interrupts. 6 FRMR7IE Framer 7 Interrupt Enable. A 1 enables framer 7 interrupts. 7 FRMR8IE Framer 8 Interrupt Enable. A 1 enables framer 8 interrupts. 0 FDL1_INT Facility Data Link 1 Interrupt. A 1 indicates FDL1 generated an interrupt. 1 FDL2_INT Facility Data Link 2 Interrupt. A 1 indicates FDL2 generated an interrupt. 2 FDL3_INT Facility Data Link 3 Interrupt. A 1 indicates FDL3 generated an interrupt. 3 FDL4_INT Facility Data Link 4 Interrupt. A 1 indicates FDL4 generated an interrupt. 4 FDL5_INT Facility Data Link 5 Interrupt. A 1 indicates FDL5 generated an interrupt. 5 FDL6_INT Facility Data Link 6 Interrupt. A 1 indicates FDL6 generated an interrupt. 6 FDL7_INT Facility Data Link 7 Interrupt. A 1 indicates FDL7 generated an interrupt. 7 FDL8_INT Facility Data Link 8 Interrupt. A 1 indicates FDL8 generated an interrupt. 0 FDL1IE Facility Data Link 1 Interrupt Enable. A 1 enables FDL 1 interrupts. 1 FDL2IE Facility Data Link 2 Interrupt Enable. A 1 enables FDL 2 interrupts. 2 FDL3IE Facility Data Link 3 Interrupt Enable. A 1 enables FDL 3 interrupts. 3 FDL4IE Facility Data Link 4 Interrupt Enable. A 1 enables FDL 4 interrupts. 4 FDL5IE Facility Data Link 5 Interrupt Enable. A 1 enables FDL 5 interrupts. 5 FDL6IE Facility Data Link 6 Interrupt Enable. A 1 enables FDL 6 interrupts. 6 FDL7IE Facility Data Link 7 Interrupt Enable. A 1 enables FDL 7 interrupts. 7 FDL8IE Facility Data Link 8 Interrupt Enable. A 1 enables FDL 8 interrupts.

Table 64. Global Control Register (GREG4) (004) These bits define the device and version number of this framer circuit. Table 65. Device ID and Version Registers (GREG5— GREG7) (005—007) 0 0 0: FRAMER 1 sources the SECOND pin. 0 0 1: FRAMER 2 sources the SECOND pin. 0 1 0: FRAMER 3 sources the SECOND pin. 0 1 1: FRAMER 4 sources the SECOND pin. 1 0 0: FRAMER 5 sources the SECOND pin. 1 0 1: FRAMER 6 sources the SECOND pin. 1 1 0: FRAMER 7 sources the SECOND pin. 1 1 1: FRAMER 8 sources the SECOND pin.

1 SECCTRL1

2 SECCTRL0

00 P r o grams the interrupt pin to be active HIGH (1-state) when there is an inter-

rupt condition and to be inactive LOW (0-state) when the condition goes away.

01 P r o grams the interrupt pin to be active LOW (0-state) when there is an inter-

10 P r o grams the interrupt pin to be active HIGH (1-state) when there is an inter-

11 P r o grams the interrupt pin to be active LOW (0-state) when there is an inter-

6I P C Interrupt Polarity Control. A 1 inverts the polarity of the interrupt pin (negative polarity).

126 Lucent Technologies Inc. Lucent T echnologies Inc. Table 66. Global Control Register (GREG8) (008) 0 0 0: FRAMER 1 sources the LORLCK and LOPLLCK pins. 0 0 1: FRAMER 2 sources the LORLCK and LOPLLCK pins. 0 1 0: FRAMER 3 sources the LORLCK and LOPLLCK pins. 0 1 1: FRAMER 4 sources the LORLCK and LOPLLCK pins. 1 0 0: FRAMER 5 sources the LORLCK and LOPLLCK pins. 1 0 1: FRAMER 6 sources the LORLCK and LOPLLCK pins. 1 1 0: FRAMER 7 sources the LORLCK and LOPLLCK pins. 1 1 1: FRAMER 8 sources the LORLCK and LOPLLCK pins. CHICK-EPLL and PLLCK-EPLL pins. CHICK-EPLL and PLLCK-EPLL pins. CHICK-EPLL and PLLCK-EPLL pins. CHICK-EPLL and PLLCK-EPLL pins. CHICK-EPLL and PLLCK-EPLL pins. CHICK-EPLL and PLLCK-EPLL pins. CHICK-EPLL and PLLCK-EPLL pins. CHICK-EPLL and PLLCK-EPLL pins.

Table 67. Global PLLCK Control Register (GREG9) (009)

0 EIPLLCK1 Enable Transmit Framer 1’s Internal PLLCK Clock S

1 EIPLLCK2 Enable Transmit Framer 2’s Internal PLLCK Clock Synthesizer. 2 EIPLLCK3 Enable Transmit Framer 3’s Internal PLLCK Clock Synthesizer. 3 EIPLLCK4 Enable Transmit Framer 4’s Internal PLLCK Clock Synthesizer. 4 EIPLLCK5 Enable Transmit Framer 5’s Internal PLLCK Clock Synthesizer. 5 EIPLLCK6 Enable Transmit Framer 6’s Internal PLLCK Clock Synthesizer. 6 EIPLLCK7 Enable Transmit Framer 7’s Internal PLLCK Clock Synthesizer. 7 EIPLLCK8 Enable Transmit Framer 8’s Internal PLLCK Clock Synthesizer.

1. Default values are given in the individual register

Table 68. Framer Status and Control Blocks framer (for framer 1—framer 8, Y = 2—9, respectively). framer 1—framer 8, Y = 2—9, respectively). receive line clock (RFRMCK). read when the given condition is no longer present. registers is stopped when all of the bits are set to 1. of the same COR register to allow it to properly clear.

128 Lucent Technologies Inc. Lucent T echnologies Inc. Registers FRM_SR0—FRM_SR63 report the status of each framer. All are clear-on-read, read-only registers. isters FRM_PR0—FRM_PR7 are set, and the interrupt for the framer block is enabled in register GREG1. Table 69. Interrupt Status Register (FRM_SR0) (Y00) 0F A C Facility Alarm Condition. A 1 indicates a facility alarm occurred (go read FRM_SR1). 1R A C Remote Alarm Condition. A 1 indicates a remote alarm occurred (go read FRM_SR2). FRM_SR5, FRM_SR6, and FRM_SR7). has been transmitted and the transmit signaling data buffers are ready for new data. been received and the receive signaling data buffers must be read. ready for more data or the receive framer SLC -96 stack contains new data.

is no longer present at the time of the read, then the bit is cleared on read. Table 70. Facility Alarm Condition Register (FRM_SR1) (Y01) ment and is currently searching for a new alignment. naling superframe alignment starts once frame alignment is established. mode, register FRM_PR44 bit 0 (TSIG) = 1. SLC -96 is lost. Only valid for SLC -96 mode. This bit is 0 in all other DS1 modes. in bit 0 of this register is the same LFA state as the previous read. (alternating 10 in bit 2 of time slot 0 of each frame) in the receive system data is errored. valid in the CEPT mode. This bit is 0 in all other modes. detected time slot 16 AIS in the CEPT mode. This bit is 0 in the DS1 modes. tern) in the CEPT mode. This bit is 0 in the DS1 modes. pattern from its remote line end.

130 Lucent Technologies Inc. Lucent T echnologies Inc. time of the read, then the bit is cleared on read. Table 71. Remote End Alarm Register (FRM_SR2) (Y02) nese format remote frame alarm. remote frame alarm in the CEPT mode. taining ≥991 E bit = 0 events in each second. This bit is 0 in the DS1 mode. 3S a 6 = 8 Received Sa6 = 8. A 1 indicates the receive framer detected an Sa6 code equal to 1000. This bit is 0 in the DS1 mode.

1. This bit is 0 in the DS1 mode.
2. This bit is 0 in the DS1 mode.
3. This bit is 0 in the DS1 mode.

7 Sa6 = F Received Sa6 = F. A 1 indicates the receive framer detected an Sa6 code equal to 1111. This bit is 0 in the DS1 mode.

A bit set to 1 indicates the receive framer has recently received the given errored event. Table 72. Facility Errored Event Register-1 (FRM_SR3) (Y03) 2 CRCE CRC Errored. A 1 indicates the receive framer detected CRC errors. 13 or 15 of the time slot 0 of CRC-4 multiframe. This bit is 0 in the DS1 modes. formed a control slip due to an elastic buffer overflow condition. performed a control slip due to an elastic buffer underflow condition.

132 Lucent Technologies Inc. Lucent T echnologies Inc. Table 73. Facility Event Register-2 (FRM_SR4) (Y04) ment which differs from the previous alignment. this alignment is established only after primary frame alignment is determined. ence 62411 as a framed 001 pattern where the frame bit is inserted into the pattern. 62411 as a framed 00001 pattern where the frame bit is inserted into the pattern. alignment in the receive framer has been established. SLC -96 D-bit superframe interval. ms of this interrupt. This bit is not updated during LFA. will be transmitted in the next CRC-4 double multiframe interval.

enable registers, FRM_PR14 and FRM_PR15. The thresholds are defined in registers FRM_PR11—FRM_PR13. Table 74. Exchange Termination and Exchange Termination Remote End Interface Status resulting in a ten-second delay in the reporting of this condition. the exchange termination remote end (ET -RE). errored second at the ET -RE. errored second at the ET -RE. used resulting in a ten-second delay in the reporting of this condition.

134 Lucent Technologies Inc. Lucent T echnologies Inc. Table 75. Network Termination and Network Termination Remote End Interface Status in a ten-second delay in the reporting of this condition. the exchange termination remote end (ET -RE). errored second at the ET -RE. errored second at the NT -RE. used resulting in a ten-second delay in the reporting of this condition.

Table 76. Facility Event Register (FRM_SR7) (Y07)

• It is possible for one of these bits to be set to 1, if the received line data is all zeros.

This register contains the 16-bit count of received bipolar violations, line code violations, or excessive zeros. Table 77. Bipolar Violation Counter Registers (FRM_SR8—FRM_SR9) (Y08—Y09) Table 78. Framing Bit Error Counter Registers (FRM_SR10—FRM_SR11) (Y0A—Y0B) seconds that were not severely errored while in the unavailable state at the ET . secutive seconds that were not severely errored while in the unavailable state at the NT . specified by the PTRN configuration bits defined in register FRM_PR70. bit errors in the pattern that it is currently locked onto. 15 – 1 pseudorandom pattern*. cuit is currently detecting the 220 – 1 quasi-random pattern*. FRM_SR8 MSB 7—0 BPV15—BPV8 BPVs Counter. FRM_SR9 LSB 7—0 BPV7—BPV0 BPVs Counter. FRM_SR10 MSB 7—0 FBE15—FBE8 Frame Bit Èrrored Counter. FRM_SR11 LSB 7—0 FBE7—FBE0 Frame Bit Errored Counter.

136 Lucent Technologies Inc. Lucent T echnologies Inc. Table 79. CRC Error Counter Registers (FRM_SR12—FRM_SR13) (Y0C—Y0D) Table 80. E-Bit Counter Registers (FRM_SR14—FRM_SR15) (Y0E—Y0F) Table 81. CRC-4 Errors at NT1 from NT2 Counter Registers (FRM_SR16—FRM_SR17) (Y10—Y11) CRC-4 multiframe. E bits are not counted during loss of CEPT CRC-4 multiframe alignment. Table 82. E Bit at NT1 from NT2 Counter (FRM_SR18—FRM_SR19) (Y12—Y13) FRM_SR12 MSB 7—0 CEC15—CEC8 CRC Errored Counter. FRM_SR13 LSB 7—0 CEC7—CEC0 CRC Errored Counter. FRM_SR14 MSB 7—0 REC15—REC8 E-Bit Counter. FRM_SR15 LSB 7—0 REC7—REC0 E-Bit Counter. FRM_SR16 MSB 7—0 CNT15—CNT8 CRC-4 Errors at NT1 Counter. FRM_SR17 LSB 7—0 CNT7—CNT0 CRC-4 Errors at NT1 Counter. FRM_SR18 MSB 7—0 ENT15—ENT8 E Bit at NT1 Counter. FRM_SR19 LSB 7—0 ENT7—ENT0 E Bit at NT1 Counter.

nals. DS1 error conditions are reported in the ET Errored Registers FRM_SR20—FRM_SR35. Table 83. ET Errored Seconds Counter (FRM_SR20—FRM_SR21) (Y14—Y15) Table 84. ET Bursty Errored Seconds Counter (FRM_SR22—FRM_SR23) (Y16—Y17) Table 85. ET Severely Errored Seconds Counter (FRM_SR24—FRM_SR25) (Y18—Y19) Table 86. ET Unavailable Seconds Counter (FRM_SR26—FRM_SR27) (Y1A—Y1B) Table 87. ET -RE Errored Seconds Counter (FRM_SR28—FRM_SR29) (Y1C—Y1D) Table 88. ET -RE Bursty Errored Seconds Counter (FRM_SR30—FRM_SR31) (Y1E—Y1F) Table 89. ET -RE Severely Errored Seconds Counter (FRM_SR32—FRM_SR33) (Y20—Y21) FRM_SR20 MSB 7—0 ETES15—ETES8 ET Errored Seconds Counter. FRM_SR21 LSB 7—0 ETES7—ETES0 ET Errored Seconds Counter. FRM_SR22 MSB 7—0 ETBES15—ETBES8 ET Bursty Errored Seconds Counter. FRM_SR23 LSB 7—0 ETBES7—ETBES0 ET Bursty Errored Seconds Counter. FRM_SR24 MSB 7—0 ETSES15—ETSES8 ET Severely Errored Seconds Counter. FRM_SR25 LSB 7—0 ETSES7—ETSES0 ET Severely Errored Seconds Counter. FRM_SR26 MSB 7—0 ETUS15—ETUS8 ET Unavailable Seconds Counter Bits. FRM_SR27 LSB 7—0 ETUS7—ETUS0 ET Unavailable Seconds Counter Bits. FRM_SR28 MSB 7—0 ETREES15—ETREES8 ET -RE Errored Seconds Counter. FRM_SR29 LSB 7—0 ETREES7—ETREES0 ET -RE Errored Seconds Counter. FRM_SR30 MSB 7—0 ETREBES15—ETREBES8 ET -RE Bursty Errored Seconds Counter. FRM_SR31 LSB 7—0 ETREBES7—ETREBES0 ET -RE Bursty Errored Seconds Counter. FRM_SR32 MSB 7—0 ETRESES15—ETRESES8 ET -RE Severely Errored Seconds Counter. FRM_SR33 LSB 7—0 ETRESES7—ETRESES0 ET -RE Severely Errored Seconds Counter.

138 Lucent Technologies Inc. Lucent T echnologies Inc. Table 90. ET -RE Unavailable Seconds Counter (FRM_SR34—FRM_SR35) (Y22—Y23) Table 91. NT1 Errored Seconds Counter (FRM_SR36—FRM_SR37) (Y24—Y25) Table 92. NT1 Bursty Errored Seconds Counter (FRM_SR38—FRM_SR39) (Y26—Y27) Table 93. NT1 Severely Errored Seconds Counter (FRM_SR40—FRM_SR41) (Y28—Y29) Table 94. NT1 Unavailable Seconds Counter (FRM_SR42—FRM_SR43) (Y2A—Y2B) Table 95. NT1-RE Errored Seconds Counter (FRM_SR44—FRM_SR45) (Y2C—Y2D) Table 96. NT1-RE Bursty Errored Seconds Counter (FRM_SR46—FRM_SR47) (Y2E—Y2F) Table 97. NT1-RE Severely Errored Seconds Counter (FRM_SR48—FRM_SR49) (Y30—Y31) FRM_SR34 MSB 7—0 ETREUS15—ETRESES8 ET -RE Unavailable Seconds Counter. FRM_SR35 LSB 7—0 ETRESES7—ETRESES0 ET -RE Unavailable Seconds Counter. FRM_SR36 MSB 7—0 NTES15—NTES8 NT1 Errored Seconds Counter. FRM_SR37 LSB 7—0 NTES7—NTES0 NT1 Errored Seconds Counter. FRM_SR38 MSB 7—0 NTBES15—NTBES8 NT1 Bursty Errored Seconds Counter. FRM_SR39 LSB 7—0 NTBES7—NTBES0 NT1 Bursty Errored Seconds Counter. FRM_SR40 MSB 7—0 NTSES15—NTSES8 NT1 Severely Errored Seconds Counter. FRM_SR41 LSB 7—0 NTSES7—NTSES0 NT1 Severely Errored Seconds Counter. FRM_SR42 MSB 7—0 NTUS15—NTUS8 NT1 Unavailable Seconds Counter Bits. FRM_SR43 LSB 7—0 NTUS7—NTUS0 NT1 Unavailable Seconds Counter Bits. FRM_SR44 MSB 7—0 NTREES15—NTREES8 NT1-RE Errored Seconds Counter. FRM_SR45 LSB 7—0 NTREES7—NTREES0 NT1-RE Errored Seconds Counter. FRM_SR46 MSB 7—0 NTREBES15—NTREBES8 NT1-RE Bursty Errored Seconds Counter. FRM_SR47 LSB 7—0 NTREBES7—NTREBES0 NT1-RE Bursty Errored Seconds Counter. FRM_SR48 MSB 7—0 NTRESES15—NTRESES8 NT1-RE Severely Errored Seconds Counter. FRM_SR49 LSB 7—0 NTRESES7—NTRESES0 NT1-RE Severely Errored Seconds Counter.

Table 98. NT1-RE Unavailable Seconds Counter (FRM_SR50—FRM_SR51) (Y32—Y33) slot 0 and the Si bit of FAS time slot 0 while the receive framer was in basic frame alignment. Table 99. Receive NOT -FAS TS0 Register (FRM_SR52) (Y34) Table 100. Receive Sa Register (FRM_SR53) (Y35) Note: The RSP[1:4] are the received spoiler bits. FRM_SR50 MSB 7—0 NTREUS15—NTREUS8 NT1-RE Unavailable Seconds Counter Bits. FRM_SR51 LSB 7—0 NTREUS7—NTREUS0 NT1-RE Unavailable Seconds Counter Bits.

00000 X 2 X 1 X 0

140 Lucent Technologies Inc. Lucent T echnologies Inc. state. In CRC-4 mode, these registers are only updated during the CRC-4 multiframe alignment state. Table 102. CEPT Sa Receive Stack (FRM_SR54—FRM_SR63) (Y36—Y3F) Table 104. Received Signaling Registers: DS1 Format (FRM_RSR0—FRM_RSR23) (Y40—Y58)

• Bit 6 and bit 5 of the DS1 receive signaling registers are copied from bit 6 and bit 5 of the DS1 transmit signaling registers.

Table 105. Receive Signaling Registers: CEPT Format (FRM_RSR0—FRM_RSR31) (Y40—Y5F)

• In PSCO or PSC1 signaling mode, this bit is undefined.

Registers FRM_PR0—FRM_PR70 define the mode configuration of each framer. All are read/write registers. These registers are initially set to a default value upon a hardware reset, which is indicated in the register definition. default value of these registers is 00 (hex). corresponding bit in the status register to assert the interrupt pin. Table 106. Summary of Interrupt Group Enable Registers (FRM_PR0—FRM_PR7) (Y60—Y67)

142 Lucent Technologies Inc. Lucent T echnologies Inc. The default value of this register is 00 (hex). Table 107. Primary Interrupt Group Enable Register (FRM_PR0) (Y60) bit in registers FRM_SR1—FRM_SR7 is set. The default value of these registers is 00 (hex). Table 108. Interrupt Enable Register (FRM_PR1) (Y61) Table 109. Interrupt Enable Register (FRM_PR2) (Y62) Table 110. Interrupt Enable Register (FRM_PR3) (Y63) FRM_SR6, and FRM_SR7 event interrupts. signaling buffers are ready (MOS mode). signaling buffers are ready (MOS mode). the same bit position in the status register. the same bit position in the status register. the same bit position in the status register.

Table 111. Interrupt Enable Register (FRM_PR4) (Y64) Table 112. Interrupt Enable Register (FRM_PR5) (Y65) Table 113. Interrupt Enable Register (FRM_PR6) (Y66) Table 114. Interrupt Enable Register (FRM_PR7) (Y67) The default value of this register is C0 (hex). Table 115. Framer Mode Bits Decoding (FRM_PR8) (Y68) the same bit position in the status register. the same bit position in the status register. the same bit position in the status register. the same bit position in the status register.

144 Lucent Technologies Inc. Lucent T echnologies Inc. Table 116. Line Code Option Bits Decoding (FRM_PR8) (Y68) This register defines the CRC options for the framer. The default setting is 00 (hex). Table 117. CRC Option Bits Decoding (FRM_PR9) (Y69)

The bits in this register enable various control options. The default setting is 00 (hex). Table 118. Alarm Filter Register (FRM_PR10) (Y6A) Bit 6 and bit 7 of FRM_PR10 control the evaluation of the bursty errored parameter as defined in Table 119 below. Table 119. Errored Event Threshold Definition of the Sa6 pattern relative to the receive CRC-4 submultiframe. described in ITU Rec. G.775. and SLC -96 modes. A 1 enables the detection of FT and FS framing bit errors. deassert the remote frame alarm. 0 0 Default values in Table 32. Other Combinations Reserved.

146 Lucent Technologies Inc. Lucent T echnologies Inc. of this register is 00 (hex). Table 120. Errored Second Threshold Register (FRM_PR11) (Y6B) bit 7 = 0. The default value of these registers is 00 (hex). Table 121. Severely Errored Second Threshold Registers (FRM_PR12—FRM_PR13) (Y6C—Y6D) of this register is 00 (hex). Table 122. ET1 Errored Event Enable Register (FRM_PR14) (Y6E) Table 123. ET1 Remote End Errored Event Enable Register (FRM_PR15) (Y6F)

• One occurrence of any one of these events causes an errored second count increment and a severely errored second count increment.

FRM_PR11 EST7—EST0 ES Threshold Register. FRM_PR12 SEST15—SEST8 SES MSB Threshold Register. FRM_PR13 SEST7—SEST0 SES LSB Threshold Register.

responding errored event. The default value of this register is 00 (hex). Table 124. NT1 Errored Event Enable Register (FRM_PR16) (Y70) events, respectively, as referred to the NT -1 remote end interface. The default value of this register is 00 (hex). Table 125. NT1 Remote End Errored Event Enable Registers (FRM_PR17—FRM_PR18) (Y71—Y72) The default value of this register is 00 (hex). Table 126. Automatic AIS to the System and Automatic Loopback Enable Register (FRM_PR19) (Y73)

• One occurrence of any one of these events causes an errored second count increment and a severely errored second count increment.

in the loss of receive frame alignment (RLFA ) state. 3T S A I S Transmit System AIS. A 1 transmits AIS to the system. line loopback on or off commands without system intervention. line ESF FDL loopback on or off command without system intervention. a payload ESF FDL loopback on or off command without system intervention.

148 Lucent Technologies Inc. Lucent T echnologies Inc. The default value of this register is 00 (hex). Table 127. Automatic AIS to the System and Automatic Loopback Enable Register (FRM_PR19) (Y73) ister 10 (hex), then 00 (hex), and finally 20 (hex)). Table 128. Transmit Test Pattern to the Line Enable Register (FRM_PR20) (Y74)

• To transmit test signals using this register, registers FRM_PR69 and FRM_PR70 must be set to 00 (hex).

in the loss of receive frame alignment (RLFA ) state. 3T S A I S Transmit System AIS. A 1 transmits AIS to the system. line loopback on or off commands without system intervention. line ESF FDL loopback on or off command without system intervention. a payload ESF FDL loopback on or off command without system intervention. 0T U F A I S Unframed AIS to Line Interface (All Ones Pattern).

1 TUFAUXP Unframed AUXP to Line Interface in CEPT Mode (Alternating 010101 Unframed

2T P R S Transmit Pseudorandom Signal to Line Interface (215 – 1). 3T Q R S Transmit Quasi-Random Signal to Line Interface (220 – 1) (ANSI T1.403). 4T L L B O N Transmit Framed Payload Line Loopback On Code: 00001. 5T L L B O F F Transmit Framed Payload Line Loopback Off Code: 001. FRM_PR22 is transmitted to the line in all time slots. 7 TICRC Transmit Inverted CRC.

The default value of this register is 00 (hex). Table 129. Framer FDL Control Command Register (FRM_PR21) (Y75) The value programmed in this register is transmitted as the line idle code. The default value is 7F (hex). Table 130. Framer Transmit Line Idle Code Register (FRM_PR22) (Y76) Table 131. Framer System Stuffed Time-Slot Code Register (FRM_PR23) (Y77) 0— Reserved. Must be set to 0. 1— Reserved. Must be set to 0. 2— Reserved. Must be set to 0. 3— Reserved. Must be set to 0. 4 TFDLLAIS Transmit Facility Data Link AIS to the Line. A 1 sends AIS in the line side data link. ter FRM_PR31—FRM_PR35 ). Otherwise, it is sourced from TFDL. 1 transmits the ESF performance report message with the C/R bit = 1. in the stuffed time slots to the system CHI.

150 Lucent Technologies Inc. Lucent T echnologies Inc. back. The default value is 00 (hex) (no loopback). Table 132. Primary Time-Slot Loopback Address Register (FRM_PR24) (Y78) Table 133. Loopback Decoding of Bits LBC[2:0] in FRM_PR24, Bits 7—5 5—7 LBC0—LBC2 Loopback Control Bits[2:0]. 001 Line Loopback (LLB ). The received line data is looped back to the transmit line data. system data and AIS is sent as the line transmit data. payload in place of the looped back time slot. place of the looped back time slot. bit 4—bit 0 is transmitted normally and also placed into time slot 0. tem in the normal format via the CHI. mode is selected if FRM_PR10 bit 3 = 1.

Table 134. Secondary Time-Slot Loopback Address Register (FRM_PR25) (Y79) Table 135. Loopback Decoding of Bits LBC[1:0] in FRM_PR25, Bits 6—5 0—4 STSL BA0—S TSLBA4 Secondary Time-Slot Loopback Address. 5—6 SLBC0—SLBC1 Secondary Loopback Control Bits[1:0].

00 No Loo

01 Secondary Single Time-Slot System Loopback. 10 Secondary Single Time-Slot Line Loopback.

152 Lucent Technologies Inc. Lucent T echnologies Inc. The default value of this register is 00 (hex). Table 136. Framer Reset and Transparent Mode Control Register (FRM_PR26) (Y7A) forced to the default values. This bit is self-cleared. state. This bit must be cleared. reframe commands must have this bit in the 0 state first. unmodified to the line and the receive framer to pass line data unmodified to the system. The receive framer is forced not to align to the input receive data. F-bit position of the receive line data into time slot 0, bit 7 of the TCHIDATA. line time slot 0 is inserted into time slot 0 of TCHIDATA.

4 TFM2 Trans

unmodified to the line. The receive framer functions normally as programmed. places this bit in the F-bit position of the transmit line data. CEPT: RCHIDATA time slot 0 is inserted into time slot 0 of the transmit line data.

5 SYSFSM S

this bit so that the jitter is isolated from the transmit framer.

The default value of this register is 00 (hex). Table 137. Transmission of Remote Frame Alarm and CEPT Automatic Transmission of A Bit = 1 Control alarm to the line whenever the receive framer detects loss of frame alignment (RLFA ). receive framer detects loss of time slot 0 multiframe alignment (RTS0LMFA ). receive framer detects the Sa6 = 1000 pattern. receive framer detects the Sa6 = 1100 pattern. frame alarm for the D4 frame format.

154 Lucent Technologies Inc. Lucent T echnologies Inc. The default value of this register is 00 (hex). Table 138. CEPT Automatic Transmission of E Bit = 0 Control Register (FRM_PR28) (Y7C) (binary). Otherwise, the transmit framer will not be able to locate the biframe alignment. Table 139. Sa4—Sa8 Source Register (FRM_PR29) (Y7D) mits system Si data to the line transparently*. bit 1 of the FAS. In CRC-4 mode, this bit is used for E-bit data in frame 13. line in bit 1 of the NOT FAS. In CRC-4 mode, this bit is used for E-bit data in frame 15. E = 0 to the line whenever the receive framer detects a CRC-4 errored checksum.

4 ATELTS0MFA Automatic Transmit E Bit = 0 for Received Loss of CRC-4 Multiframe Ali

of either the 100 ms or 400 ms timer due to the loss of CRC-4 multiframe alignment. 0—4 TSa4—TSa8 Transmit Sa4—Sa8 Bit. 5—7 SaS5—SaS7 Sa Source Control Bits[2:0].

Table 140. Sa Bits Source Control for Bit 5—Bit 7 in FRM_PR29 (binary). Otherwise, the transmit framer will not be able to locate the biframe alignment. default value of this register is 00 (hex). Table 141. Sa4—Sa8 Control Register (FRM_PR30) (Y7E)

100 A s i n gle Sa bit, selected in register FRM_PR43, is sourced from either the external

101 A s i n gle Sa bit, selected in register FRM_PR43, is sourced from either the external

ently from the system interface*. or transparently from the system interface*. FRM_PR30, or transparently from the system interface*.

001 S a [4:8] bits are transmitted from the system interface transparently through the

000 S a [4:8] bits are sourced by bit 0—bit 4 of this register if enabled in register

FRM_PR30, or transparently from the system interface*. ently from the system interface. y NOT FAS data that is repeated twice.

156 Lucent Technologies Inc. Lucent T echnologies Inc. NOT -FAS words. If CRC-4 is enabled, this data is transmitted to the line synchronously to the CRC-4 multiframe. The default value of these registers is 00 (hex). Table 142. Sa Transmit Stack (FRM_PR31—FRM_PR40) (Y7F—Y88) the FS bit positions. The default value of these registers is 00 (hex). Table 143. SLC-96 Transmit Stack (FRM_PR31—FRM_PR40) (Y7F—Y88) Table 144. Transmit SLC -96 FDL Format

1 XC 2 XC 3 XC 4 XC 5 XC 6 XC 7 XC 8

The default value of this register is 00 (hex). Table 145. CEPT Time Slot 16 X-Bit Remote Multiframe Alarm and AIS Control Register (FRM_PR41) (Y89) T able 146 causes the specified error condition to be generated. In normal operation, it should be set to 00 (hex). The default value of this register is 00 (hex). Table 146. Framer Exercise Register (FRM_PR42) (Y8A) gnaling multiframe time slot 16 X bits. 16 signaling multiframe frame. A 0 transmits the X bits transparently. when the receive framer is in the loss of CEPT signaling (RTS16LMFA ) state. mission of CEPT time slot 16 signaling remote multiframe alarm. slot 16 alarm indication signal. FEX0—FEX5 Framer Exercise Bits 0—5 (FEX0—FEX5 ). See Table 147. FEX6 FEX7 Pulse wide Interval.

158 Lucent Technologies Inc. Lucent T echnologies Inc. Table 147. Framer Exercises, FRM_PR42 Bit 5—Bit 0 (Y8A)

Table 147. Framer Exercises, FRM_PR42 Bit 5—Bit 0 (Y8A) (continued) The default value of this register is 00 (hex). Table 148. DS1 System Interface Control and CEPT FDL Source Control Register (FRM_PR43) (Y8B) content of the stuffed time slot can be programmed using register FRM_PR23. gram the Sa-bit source of the facility data link. y the bit values shown above may be selected. 3S S C SLC -96 Signaling Control (DS1 Only). A 1 enables the SLC -96 9-state signaling mode. A 0 enables 16-state signaling in the SLC -96 framing mode.

160 Lucent Technologies Inc. Lucent T echnologies Inc. This register programs various signaling modes. The default value is 00 (hex). Table 149. Signaling Mode Register (FRM_PR44) (Y8C) device transparently. All channels are treated as data channels. of the signaling combination of ABCD = 0000 to ABCD = 1111. 8 bits are signaling information. gnaling Inhibit. A 1 inhibits updating of the receive signaling buffer. ing information from the receive line. time slot 16 during receive loss of time slot 16 signaling multiframe alignment state. slot 16 of the transmit system data.

default value of this register is 00 (hex). Table 150. CHI Common Control Register (FRM_PR45) (Y8D) transmit and receive interfaces. Concentration Highwa y Interface Data Rate Select.

11 R e s e r v e d

path is not affected by this mode. for all CHI transmitted time slots.

162 Lucent Technologies Inc. Lucent T echnologies Inc. This register defines the common attributes of the transmit and receive CHI. The default value is 00 (hex). Table 151. CHI Common Control Register (FRM_PR46) (Y8E) The default value of this register is 00 (hex). Table 152. CHI Transmit Control Register (FRM_PR47) (Y8F) The default value of this register is 00 (hex). Table 153. CHI Receive Control Register (FRM_PR48) (Y90) in the frame synchronization signal, CHIFS. in the frame synchronization signal, CHIFS. the byte offset from CHIFS to the beginning of the next receive CHI frame on RCHIDATA.

time slot. A 0 forces the CHI transmit highway time slot to be 3-stated. The default value of this register is 00 (hex). Table 154. CHI Transmit Time-Slot Enable Registers (FRM_PR49—FRM_PR52) (Y91—Y94) the corresponding time slot. The default value of this register is FF (hex). Table 155. CHI Receive Time-Slot Enable Registers (FRM_PR53—FRM_PR56) (Y95—Y98) time slot. A 0 enables TCHIDA TA, and a 1 enables TCHIDA T AB. The default value of this register is 00 (hex). Table 156. CHI Transmit Highway Select Registers (FRM_PR57—FRM_PR60) (Y99—Y9C) time slot. A 0 enables RCHIDA TA and a 1 enables RCHIDA TAB. The default value of these registers is 00 (hex). Table 157. CHI Receive Highway Select Registers (FRM_PR61—FRM_PR64) (Y9D—YA0) FRM_PR49 7—0 TTSE31—TTSE24 Transmit Time-Slot Enable Bits 31—24. FRM_PR50 7—0 TTSE23—TTSE16 Transmit Time-Slot Enable Bits 23—16. FRM_PR51 7—0 TTSE15—TTSE8 Transmit Time-Slot Enable Bits 15—8. FRM_PR52 7—0 TTSE7—TTSE0 Transmit Time-Slot Enable Bits 7—0. FRM_PR53 7—0 RTSE31—RTSE24 Receive Time-Slot Enable Bits 31—24. FRM_PR54 7—0 RTSE23—RTSE16 Receive Time-Slot Enable Bits 23—16. FRM_PR55 7—0 RTSE15—RTSE8 Receive Time-Slot Enable Bits 15—8. FRM_PR56 7—0 RTSE7—RTSE0 Receive Time-Slot Enable Bits 7—0. FRM_PR57 7—0 THS31—THS24 Transmit Highway Select Bits 31—24. FRM_PR58 7—0 THS23—THS16 Transmit Highway Select Bits 23—16. FRM_PR59 7—0 THS15—THS8 Transmit Highway Select Bits 15—8. FRM_PR60 7—0 THS7—THS0 Transmit Highway Select Bits 7—0. FRM_PR61 7—0 RHS31—RHS24 Receive Highway Select Bits 31—24. FRM_PR62 7—0 RHS23—RHS16 Receive Highway Select Bits 23—16. FRM_PR63 7—0 RHS15—RHS8 Receive Highway Select Bits 15—8. FRM_PR64 7—0 RHS7—RHS0 Receive Highway Select Bits 7—0.

164 Lucent Technologies Inc. Lucent T echnologies Inc. The default value of this register is 00 (hex). Table 158. CHI Transmit Control Register (FRM_PR65) (YA1) The default value of this register is 00 (hex). Table 159. CHI Receive Control Register (FRM_PR66) (YA2) mode. In this mode, the CHI clock runs at twice the rate of TCHIDATA. ming the byte offset from 0—127. mode. In this mode, the CHI clock runs at twice the rate of RCHIDATA.

Lucent Technologies Inc. 165 Preliminary Data Sheet October 2000 TFRA08C13 OCTAL T1/E1 Framer Lucent T echnologies Inc. Framer Register Architecture (continued) Reserved Parameter/Control Registers Registers FRM_PR67 and FRM_PR68, addresses 6A3 and 6A4 or CA3 and CA4, are reserved. Write these regis- ters to 0. Auxiliary Pattern Generator Control Register (FRM_PR69) The following register programs the auxiliary pattern generator in the transmit framer. The default value of this reg- ister is 00 (hex). Table 160. Auxiliary Pattern Generator Control Register (FRM_PR69) (YA5)*

• To generate test pattern signals using this register, register FRM_PR20 must be set to 00 (hex).

0I T D Invert Transmit Data. Setting this bit to 1 inverts the transmitted pattern. the transmitted test pattern. unframed pattern. A 0 results in a framed pattern (T1 and CEPT).

Description

(all ones) (AIS) QRSS (220 – 1 with zero suppression) 25 – 1 63 (26 – 1) 511 (29 – 1) 511 (29 – 1) reversed 2047 (211 – 1) 2047 (211 – 1) reversed 215 – 1 220 – 1 220 – 1 223 – 1 1:1 (alternating) Generator Polynomial 1+x–17+x–20 1+x–3+x–5 1+x–1+x–6 1+x–5+x–9 1+x–4+x–9 1+x–9+x–11 1+x–2x–11 1+x–14+x–15 1+x–3+x–20 1+x–17+x–20 1+x–18+x–23 Standard O.151 O.153 O.152 O.151 O.153 CB113/CB114 O.151

TFRA08C13 OCTAL T1/E1 Framer October 2000 166 Lucent Technologies Inc. Lucent T echnologies Inc. Framer Register Architecture (continued) Pattern Detector Control Register (FRM_PR70) The following register programs the pattern detector in the receive framer. The default value of this register is 00 (hex). This register must be set to 00 (hex) before a pattern is selected or changed. This register must be set to 00 (hex) to clean register FRM_SR7. Once a selected pattern is detected, the detector remains locked to that align- ment and all differences from the expected are reported an bit errors. Pattern-realignment can only occur following a reset of this register, setting it to 00 (hex). Table 161. Pattern Detector Control Register (FRM_PR70) (YA6)*

• T o generate/detect test pattern signals using this register, register FRM_PR20 must be set to 00 (hex).

inverse of the selected pattern. unframed pattern. A 0 results in a search for a framed pattern (T1 and CEPT). (all ones) (AIS) QRSS (220 – 1 with zero suppression) 25 – 1 63 (26 – 1) 511 (29 – 1) 511 (29 – 1) reversed 2047 (211 – 1) 2047 (211 – 1) reversed 215 – 1 220 – 1 220 – 1 223 – 1 1:1 (alternating) Generator Polynomial 1+x–17+x–20 1+x–3+x–5 1+x–1+x–6 1+x–5+x–9 1+x–4+x–9 1+x–9+x–11 1+x–2x–11 1+x–14+x–15 1+x–3+x–20 1+x–17+x–20 1+x–18+x–23 Standard O.151 O.153 O.152 O.151 O.153 CB113/CB114 O.151

Table 162. Transmit Signaling Registers: DS1 Format (FRM_TSR0—FRM_TSR23) (YE0—YF7) Table 163. Transmit Signaling Registers: CEPT Format (FRM_TSR0—FRM_TSR31) (YE0—YFF)

• In PCS0 or PCS1 signaling mode, this bit is undefined.

168 Lucent Technologies Inc. Lucent T echnologies Inc. Table 164. FDL Register Set ((A00—A0E); (A20—A2E); (B00—B0E); (B20—B2E) (C00—C0E); (C20—C2E);

• For FDL 1 and FDL 2, Y = A; for FDL 3 and FDL 4, Y = B; for FDL 5 and FDL 6, Y = C; for FDL 7 and FDL 8, Y = D.

upon a hardware reset. These registers are all read/write registers. Default states of all bits in this register group are also indicated in the parameter/control register map. Table 165. FDL Configuration Control Register (FDL_PR0) (A00; A20; B00; B20; C00; C20; D00; D20)

• The FRANSIT bits (FDL_PR0 bits 4—7) must be changed only following an FDL reset or when the FDL is idle.

Table 166. FDL Control Register (FDL_PR1) (A01; A21; B01; B21; C01; C21; D01; D21) ate a single interrupt before the interrupt bit is cleared by reading register FDL_SR0. (01111110) in the absence of transmit FDL information. This bit resets to 0. codes needed for indicating a valid code. The default is ten (1010 (binary))*. data interface. This bit resets to 0. ignored. This bit resets to 0. receiver into an inactive state. This bit resets to 0. transmitter into an inactive state. This bit resets to 0. 4F R R FDL Receiver Reset. FRR = 1 generates an internal pulse that resets the FDL receiver. OVERRUN interrupts are cleared. This bit resets to 0. and forced to 1 in the transparent mode. This bit resets to 0. receive FDL FIFO. This bit resets to 0. once per second. The PRM is followed by either idles or flags transmitted after the PRM. When this bit is 0, the transmit FDL expects data from the microprocessor interface.

170 Lucent Technologies Inc. Lucent T echnologies Inc. Table 167. FDL Interrupt Mask Control Register (FDL_PR2) (A02; A22; B02; B22; C02; C22; D02; D22) grammed empty level (see register FDL_PR3). FTEIE is cleared upon reset. is cleared upon reset and is not used in the transparent mode. grammed full level (see register FDL_PR6). FRFIE is cleared upon reset. receiver. FREOFIE is cleared upon reset and is not used in the transparent mode. cleared upon reset and is not used in the transparent mode. ted frames (for test purposes) until the FTBCRC bit is cleared to 0.

Table 168. FDL Transmitter Configuration Control Register (FDL_PR3) (A03; A23; B03; B23; C03; C23; D03;

1. Do not set FT ABT = 1 and FTFC = 1 at the same time.

Table 169. FDL Transmitter FIFO Register (FDL_PR4) (A04; A24; B04; B24; C04; C24; D04; D24) Table 170. FDL Transmitter Idle Character Register (FDL_PR5) (A05; A25; B05; B25; C05; C25; D05; D25) positions in the transmit FIFO which triggers a transmitter-empty (FTEM ) interrupt. FIFO locations is obtained by reading the transmit FDL status register FDL_SR1. ten FTABT. The last value written to FTABT is available for reading. cleared by writing to this bit. Clearing this bit has no effect on a previously written FTFC. The last value written to FTFC is available for reading.

172 Lucent Technologies Inc. Lucent T echnologies Inc. Table 171. FDL Receiver Interrupt Level Control Register (FDL_PR6) (A06; A26; B06; B26; C06; C26; D06; Table 172. FDL Register FDL_PR7 Table 173. FDL Receiver Match Character Register (FDL_PR8) (A08; A28; B08; B28; C08; C28; D08; D28) condition is generated whenever a valid ANSI code is received. the receive FDL unit searches the incoming bit stream for the receiver match character. ion (register FDL_PR9 bit 4 = 0) or only on byte boundaries (register FDL_PR9 bit 4 = 1).

Table 174. FDL Transparent Control Register (FDL_PR9) (A09; A29; B09; B29; C09; C29; D09; D29)

• The octet boundary is relative the first receive clock edge after the receiver has been enabled (ENR, FDL_PR1 bit 2 = 1).

Table 175. FDL Transmit ANSI ESF Bit Codes (FDL_PR10) (A0A; A2A; B0A; B2A; C0A; C2A; D0A; D2A) FDL_PR9 bit 3 (FMSTAT ) is set to 1. A value of 111 (binary) indicates byte alignment. ister FDL_PR9 bit 0—bit 2) are set to 111 (binary). receive FDL unit searches for the receive match character in a sliding window fashion. bit is 0, the transmitter sends ones idle characters when the transmit FIFO is empty. cessing on incoming or outgoing data. form 111111110X0X1X2X3X4X50, where the order of transmission is from left to right.

174 Lucent Technologies Inc. Lucent T echnologies Inc. Table 176. FDL Interrupt Status Register (Clear on Read) (FDL_SR0) (A0B; A2B; B0B; B2B; C0B; C2B; operation of the FIFO. Following an FDL receive FIFO overrun, data extracted prior to the required reset may be corrupted. loaded above the programmed empty level. interrupt is not generated in the transparent mode. register. This interrupt is not generated in the transparent mode. (FDL_PR2 bit 5) is set. This status bit is cleared to 0 by a read of this register*. read of this register. This interrupt is not generated in the transparent mode. FDL_PR6 bit 7 = 1. This status bit is cleared to 0 by a read this register.

Table 177. FDL Transmitter Status Register (FDL_SR1) (A0C; A2C; B0C; B2C; C0C; C2C; D0C; D2C)

• The count of FDL_SR1 bits 0—6 includes SF byte.

Table 178. FDL Receiver Status Register (FDL_SR2) (A0D; A2D; B0D; B2D; C0D; C2D; D0D; D2D) in bit 0—bit 6 of this status register is the number of bytes, including SF byte, that may be read from the FIFO. The 6-bit code extracted from the ANSI code 111111110X0X1X2X3X4X50 is stored in this register. Table 179. Receive ANSI FDL Status Register (FDL_SR3) (A0E; A2E; B0E; B2E; C0E; C2E; D0E; D2E) FDL reset to restore proper FDL operation. Table 180. FDL Receiver FIFO Register (FDL_SR4) (A07; A27; B07; B27; C07; C27; D07; D27) transmit FIFO*. The bits are encoded in binary where bit 0 is the least significant bit. bit 0 is the least significant bit*. bytes up to and including the first SF byte.

176 Lucent Technologies Inc. Lucent T echnologies Inc. Table 181. Global Register Set

framer (for framer 1—framer 8, Y = 2—9, respectively). Table 182. Framer Unit Status Register Map

178 Lucent Technologies Inc. Lucent T echnologies Inc. Table 182. Framer Unit Status Register Map (continued)

• Unbracketed contents are valid for DS1 modes. Bracketed contents, [], are valid for CEPT mode.

framer (for framer 1—framer 8, Y = 2—9, respectively). Table 183. Receive Signaling Registers Map

1. In the DS1 robbed-bit signaling modes, these bits are copied from the corresponding transmit signaling registers. In the CEPT signaling mo

des, these bits are in the 0-state and should be ignored.

1. In the DS1 signaling modes, these registers contain unknown data.
2. In DS1 4-state and 2-state signaling, these bits contain unknown data.
3. In DS1 2-state signaling, these bits contain unknown data.
4. In the CEPT signaling modes, the A-, B-, C-, D-, and P-bit information of these registers contains unknown data.

180 Lucent Technologies Inc. Lucent T echnologies Inc. framer (for framer 1—framer 8, Y = 2—9, respectively). Table 184. Framer Unit Parameter Register Map

0 NTSa6-8

Table 184. Framer Unit Parameter Register Map (continued)

182 Lucent Technologies Inc. Lucent T echnologies Inc.

framer (for framer 1—framer 8, Y = 2—9, respectively). Table 185. Transmit Signaling Registers Map

1. In the normal DS1 robbed-bit signaling modes, these bits define the corresponding receive channel signaling mode and are

copied into the received signaling registers. In the CEPT signaling modes, these bits are ignored.

1. These bits contain unknown data.
2. In DS1 4-state and 2-state signaling modes, these bits contain unknown data.
3. In DS1 2-state signaling mode, these bits contain unknown data.
4. In the CEPT signaling modes, the A-, B-, C-, D-, and P-bit information of these registers contains unknown data.
5. In the DS1 signaling modes, these registers contain unknown data.

5 R/W P G_16 F_16 — D_16 C_16 B_16 A_16 YF0

184 Lucent Technologies Inc. Lucent T echnologies Inc. Table 186. Facility Data Link Register Map

• For FDL 1 and FDL 2, Y = A; for FDL 3 and FDL 4, Y = B; for FDL 5 and FDL 6, Y = C; for FDL 7 and FDL 8, Y = D.

periods can adversely affect device reliability. using these circuit parameters. Table 187. ESD Threshold Voltage

• This maximum rating only applies when the device is powered up with VDD .

TFRA08C13 OCTAL T1/E1 Framer October 2000 186 Lucent Technologies Inc. Lucent T echnologies Inc.

Electrical Characteristics

Logic Interface Characteristics Table 188. Logic Interface Characteristics (TA = –40 °C to +85 °C, VDD = 3.3 V ± 5%, VSS = 0) All buffers use CMOS levels. All inputs are driven between 2.4 V and 0.4 V . An internal pull-up is provided on the 3-STA TE, RESET, DS1/CEPT, MPMODE, CS , MPCK, TDI, TCK, and TMS pins. An internal pull-down is provided on the TRST pin. between these lines and the 3.3 V power plane. Capacitors used for power supply bypassing should be placed as close as possible to the device pins.

Lucent Technologies Inc. 187 Preliminary Data Sheet October 2000 TFRA08C13 OCTAL T1/E1 Framer Lucent T echnologies Inc. Outline Diagram 352-Pin PBGA Dimensions are in millimeters. 5-4407(F).ar.4 SEATING PLANE SOLDER BALL0.60 ± 0.10 0.20 PWB MOLD COMPOUND 35.00 +0.70 –0.00 30.00 A1 BAL L IDENTIFIER ZONE AF AE AD AC AB AA Y W V U T R G 25 SPACES @ 1.27 = 31.75 P N M L K J H 1 2 3 4 5 6 7 8 9 1 0 1 21 4 1 61 8 2 22 4 2 620 11 13 15 17 21 19 23 25 F E D C B A

25 SPACES

0.75 ± 0.15 35.00 ± 0.20 30.00+0.70 –0.00 ± 0.20 @ 1.27 = 31.75 CORNER

TFRA08C13 OCTAL T1/E1 Framer October 2000 Lucent T echnologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. ORCA is a registered trademark of Lucent T echnologies Inc. Foundry is a trademark of Xilinx, Inc. October 2000 DS00-190PDH (Replaces DS99-039T1E1) INTERNET: http://www.lucent.com/micro, or for FPGA information, http://www.lucent.com/orca E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent T echnologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, P A 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA P ACIFIC: Microelectronics Group, Lucent T echnologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent T echnologies (China) Co., Ltd., A-F2, 23/F , Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P . R. China Tel. (86) 21 6440 0468, ext. 325, FAX (86) 21 6440 0652 JAP AN: Microelectronics Group, Lucent T echnologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, T okyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DA T ALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 T echnical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), IT AL Y: (39) 02 6608131 (Milan), SP AIN: (34) 1 807 1441 (Madrid)

Ordering Information

Device Code Package Temperature Comcode (Ordering Number) TFRA08C13 - DB 352-Pin PBGA –40 °C to +85 °C 108269754