TECEV103

TECEV103 ANALOGTECHNOLOGIES | Alldatasheet

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 Copyright 1999 – 2004, Analog Technologies, Inc. All Rights Reserved. Updated: 8/25/04 1 TECEV103 Analog Technologies, Inc. TEC CONTROLLER EVALUATION KIT TECEV103 (updated 06/17/04) Our TEC controller modules can be evaluated conveniently by using this evaluation kit TECEV103 which comes with an evaluation board, TECEVB103 and a TEC controller module of TEC -A1 (there is no internal compensation network in side). The main purpose of using the evaluation board is to tune the compensation network on the board for match ing the characteristics of users’ thermal load. The objectives of the tuning are to minimize the response time of the thermal control loop and the dynamic temperature tracking errors, while keeping the control loop stable. 1. Connection TEC Controller +5V To Thermistor5V Imax = 2A TEC-GND SDNG Figure 1 TEC Controller Evaluation Board TECEV103 RTH TMPS TMPO VDR TMPGD GND Ci 100nF 150nF 330nF 220nF820nF1.5uF 820nF 0 82nF 470nF Cd Vlim 500K 680nF 1uF 3.3uF 680nF 1uF 2.2uF 330nF4.7uF SDNG TECP TMPS TMPO VDR RTH GND TEC+ Rth GND To TEC To power supply probing For oscilloscope probing For multimeter LED On Off Temp. good Ri RdCd Ci Rp To A/D, D/A, and/or microprocessor Wi Power TMPGD TECN TECP TECN 470nF S2 Wd Wp W1 W2 5K 20K On Off CMPIN CDRD CIRP CMPO LEDA LEDC 3V CLHT

 Copyright 1999 – 2012, Analog Technologies, Inc. All Rights Reserved. Updated: 8/25/04 4 TECEV103 Analog Technologies, Inc. between CMPIN and CDRD test points; Rp can be read off between CMPIN and CIRP test points. 4. After the compensation network is tuned properly, we can now adjust set -point temperature to see if the TEC controller can drive the target temperature to a certain range and with high stability . Turn the temperature set - point TMPS potentiometer W1 while monitoring its output voltage at TMPS test point (4th row on either left or right side of the board), watch the LED: when it turns to green, the target temperature is locked to the set -point temperature within 0.1 °C or less. The relationship between the set -point voltage vs. the set -point temperature is given in the datasheet. After seeing the LED lock into the set -point temperature, VDR should be a constant voltage as shown in the oscilloscop e and the voltage between TMPS and TMPO should be very small, less than 10mV. When a standard TEC controller is used, the 10mV represent a 0.07° temperature error. 5. Set output voltage limit. 6. To know more parameters of the TEC controller. a. To know the actual target temperature, use a voltage meter to measure the voltage between the TMP O and the GND pins, the reading result is: target temperature = 15 °C + (TMPO voltage (V))*6.67 °C for approximation (see the curve in the TEC controller data sheet). b. To know how hard the TEC is working, measure the voltage VDR by a voltage meter o r an ADC, TEC voltage = 2.5V – VDR. When the TEC voltage (from the calculation) is positive, it is in cooling mode; when the TEC voltage is negative, it is in heating mode. Cool/ Heat Balance CLHT can be adjusted by W2. TEC maximum voltage can be reduced by reducing W3, make sure Vlim switch is now turned to the on position. c. To try other values of capacitors not provided by the evaluation board for the capacitors in the compensation network, turn the capacitor switches you want to try to the top point, the “0” position, connect the component to the corresponding soldering pads as marked on the evaluation board. d. To shut down the TEC controller, turn the Power switch to the “Off” position, see Figure 2. e. To control the set -point temperature directly by using a DAC, set the set -point temperature POT W1 to the middle point (25 °C), on which the TMPS is about 1.5V, the half value of the reference voltage, connect TMPS test point to the output of the DAC and use this formula for approximation when the input voltage is between 0V and 3V: set-point temperature (°C) = 15 °C + (TMP O voltage (V))*6.67°C. The maximum voltage allowed is Vps (pow er supply). See the curve in the TEC controller data sheet. f. To control the TEC voltage directly by using a DAC, connect VDR to the output of the DAC and use this formula: TEC voltage = 2.5V – VDR (V). g. To shut down the TEC controller by using a microprocessor, turn off the Power switch, connect SDN test point (2nd row from the bottom side, on both left and right columes.) to one of its digital outputs. When pulling low, the TEC controller is shut off. When pulling high SDN, the TEC controller is turned on. h. The evaluation schematic is given in Figure 5. Using the TEC controller for more applications not described here, and/or having any questions, please free to contact us.

Copyright 1999 – 2012, Analog Technologies, Inc. All Rights Reserved. Updated: 8/25/04 5 TECEV103 Analog Technologies, Inc. 12 100 1 2 CI 1 2 CI8 820nF 1 2 CD8 3.3uF CI7 680nF 1 2 CD6 1.5uF CI6 470nF CD5 1uF CI5 330nF CD4 820nF CI3 150nF CD3 680nF CD9 4.7uF 1 2 CI9 1uF CI2 100nF 1 2 CD7 2.2uF CI4 220nF CD2 470nF Cd Rd Ri Rp Ci TECEV-103 ST9P ST9P 1 2R3 1K 2 3 1 4 N1206-4 12R4 100K CD1 330nF SDN 1 2RD CD 2 W1 TMPS TEMPGD1 TEMPSP3 GND4 3V2 TECCRT5 VTEC6 CMIN7 TEMP8 SDNG9 GND 10 RTH 11 TECPOS12 TECNEG13 GNDP 14 GNDP 15 VPS 16 U1 TECA1 CMPO VDR CMPIN TMPO RTH TECP TECN TMPS 1 2 LED1 SML-LX2832SUGC TMPGD 5V L_Pad1 SPT1 S_Pad1 SPT5 RTH-1 S_Pad1 SPT6 RTH-2 (GND) L_Pad1 SPT2 L_Pad1 SPT3 TEC- L_Pad1 SPT4 TEC+ PGND TECN TECP RTH GND TMPGD 2W2 5K VDR 1 2R2 10K SDN WI 2M 3 1 WP 2M WD 500K CI1 82nF CMPIN 10 10 TMPO 1 2RI 1 2RP CMPO1 THM5 CMPO THM3 CMPIN THM1 TMPO THM4 CIRP THM2 CDRD TT1 TEC- TT2 TEC+ TT3 RTH TT4 TMPS TT6 VDR TT7 TMPGD TECN TECP RTH TMPS VDR TMPGD THR1 TEC- TECN THR2 TEC+ TECP THR3 RTH RTH THR4 TMPS TMPS THR5 TMPO VDR 1 THR6 VDR THR7 TMPGD TMPGD TT9 GND THR9 GND GND S_Pad1 SPR1 TEC- TECN S_Pad1 SPR2 TEC+ TECP TT5 TMPO TMPO S_Pad1 SPR3 RTH RTH S_Pad1 SPR4 TMPS TMPS S_Pad1 SPR5 TMPO TMPO S_Pad1 SPR6 VDR VDR S_Pad1 SPR7 TMPGD TMPGD S_Pad1 SPR9 GND GND TMPO TT8 SDN SDN1 THR8 SDN SDN S_Pad1 SPR8 SDN SDN S_Pad1 SPL1 TEC- TECN S_Pad1 SPL2 TEC+ TECP S_Pad1 SPL3 RTH RTH S_Pad1 SPL4 TMPS TMPS S_Pad1 SPL5 TMPO TMPO S_Pad1 SPL6 VDR VDR S_Pad1 SPL7 TMPGD TMPGD S_Pad1 SPL9 GND GND S_Pad1 SPL8 SDN SDN THL1 TEC- TECN THL2 TEC+ TECP THL3 RTH RTH THL4 TMPS TMPS VDR 1 THL6 VDR THL7 TMPGD TMPGD THL9 GND GND THL8 SDN SDN THM8 THM7 LEDC THM6 LEDA LEDALEDC LEDA LEDC 3V Left Side Right Side Top Side Bottom Side GND S_Pad 1 SPM1 LEDA LEDA S_Pad 1 SPM2 LEDC LEDC THM9 CLHT 20K CHB CHB 2 3 MMBT6428 PGND Figure 5 Evaluation Board Schematic