TEC5V6A-DA

TEC5V6A-NT ANALOGTECHNOLOGIES | Alldatasheet

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Copyrights 2000-2022, Analog Technologies, Inc. All Rights Reserved. Updated on 4/28/2022 Email: staff@analogti.com/sales@analogti.com 2 Analog Technologies TEC5V6A-NT High Efficiency TEC Controller SPECIFICATIONS Table 1 Pin Function Descriptions Pin # Pin Name Type Description

1 TEMPGD Digital output

Temperature good indication. It is pulled hi gh when the set-point temperature and the actual desired object temperature are <0.1 °C in temperature differ ence when the set-point temperature range is 20 °C; or <3mV in voltage difference between the voltages of TEMP and TEMPSP nodes. On this pin, there is an internal pull up resistor of 10k tied to the VPS rail. When going low, this pin is pulled down by an open drain FET with a resistance of 250Ω @ VVPS = 5V. *A 100nF capacitor to GND needs to be added to this TEC controller manufactured before March 27 th, 2012. Otherwise, there will be an interference of Vp-p=200mV, f=500kHz. 2 3VR Analog output Reference voltage output, 3V. It can be used by a POT or DAC for setting the set-point temperature voltage on the TEMPSP pin and/or a DAC for measuring the temperature through the TEMP pin. The maximum sourcing current capability is 1.5mA and the maximum sinking is 4mA with a stability of <50ppm/°C max.

3 TEMPSP Analog input

Object set-point temperature input port. It is internally tied by a 10M Ω resistor to the half value of the reference voltage, 1.5V. It is highly recommended to set this pin’s voltage by using the controller’s voltage reference. The lower limit of the setting voltage for this pin is 0.1V. Setting this pin to a <0.1V voltage may cause the controller over cooling the object. This pin can also be set to a voltage that is about 0.2V away from the VPS rail. This pin can be set by using a POT or DAC. 4 GND Ground Signal ground for the POT, ADC, DAC and the thermistor, see Figure 4.

5 TECCRT

TEC control voltage. It can be left unconnected or used to control the TEC voltage directly. Set TECCRT between 0V to VPS, the voltage across TEC will be: TEC voltage = V VPS − 2×VTECCRT. It can also be used to configure the maximum voltage cross the TEC: Max. TEC voltage = V VPS×Rm/(Rm+10k), where Rm is the resistance of the two resistors one between TECCRT to G ND and the other between TECCRT to VPS, see Figure 4.

6 VTEC Analog

TEC voltage indication. TEC voltage = [max. TEC voltage]×[V VPS − 2×V VTEC]/VVPS. When TECCRT is used to control the TEC voltage directly, measure TECCRT to derive the TEC voltage instead, and use this formula: TEC voltage = V VPS − 2×V TECCRT. The maximum driving current of pin VTEC is 30mA and the output voltage swing is 0V to VVPS.

7 CMIN Analog input

Compensation input pin for the thermal control loop. Leave it open in production. When prototyping, use this pin with a tuner on the evaluation board, TECEV104 (produced by ATI) to tune the compensation network to match the characteristics of the thermal load.

8 TEMP Analog

Actual object temperature. It swings from 0V to V VPS, corresponds to 15 °C to 50°C when VVPS equals to 5V. See the curve below.

9 SDNG Digital input

Shut down control. When pulled low, it shuts down the controller. Leave it open or pull it high to activate the controller. The threshold voltage is 1.4V. This pin is internally pulled up by a resistor of 100k to VPS. 10 GND ground Signal ground, internally connected to Pin 4 GND. Can be used for connecting the thermistor 11 RTH Analog input Inverting input to error amplifier.

12 TECPOS Analog

power output Connects to TEC positive terminal

13 TECNEG Analog

14 PGND Power

15 PGND Power

16 VPS Power input Positive power supply rail. The value is 5V. Table 2. Characteristics (Tambient=25°C)

• Object temperature refers to the actual cold side temperature of the TEC, on where the object is mounted.

** Set-point temperature is the temperature desired to have on the object. *** Can be customized to any range according to requirement. **** This TEC controller can only drive the TECs having > 1Ω impedance, which equals VMAX/IMAX. of 0.8Ω. We advise customers to use voltage of 6V as the power supply.

Figure 5. V

Copyrights 2000-2022, Analog Technologies, Inc. All Rights Reserved. Updated on 4/28/2022 Email: staff@analogti.com/sales@analogti.com 8 Analog Technologies TEC5V6A-NT High Efficiency TEC Controller ORDERING INFO Table 3. Part # Description TEC5V6A-NT TEMP =On @SDNG = 0 TECNEG: Linear; TECPOS: Filtered PWM Two 10MΩ resistors on TEMPSP pin: Not removed No internal temperature range setting network SELECTION GUIDE Part # V IN V OUT Dimensions (mm) Difference TEC18V15A 6.0V~18V ±15V 35.7×35.7×7.2 High voltage high current with embedded firmware inside TEC50V20ACH Under Development 12V ~ 50V ±40V 63.0×61.0×16.7 High voltage high current TEMP = On @SDNG= 0 TECNEG: Linear; TECPOS: Filtered PWM； Two 10MΩ resistors on TEMPSP pin: Not removed Max. |VTEMP − VTEMPSP| ≤ 5mV TEMP = On @SDNG = 0 TECNEG: Linear; TECPOS: Filtered PWM Two 10MΩ resistors on TEMPSP pin: Not removed Max. |VTEMP − VTEMPSP| ≤ 2mV TEMP = On @ SDNG= 0 TECNEG: Linear; TECPOS: Filtered PWM Two 10MΩ resistors on TEMPSP pin: Not removed Max. |VTEMP − VTEMPSP| ≤ 0.5mV TEMP =On @SDNG = 0 TECNEG: Linear; TECPOS: Filtered PWM Two 10MΩ resistors on TEMPSP pin: Not removed No internal temperature range setting network TEMP = On @SDNG = 0 TECNEG: Linear; TECPOS: Filtered PWM Two 10MΩ resistors on TEMPSP pin: Not removed Max. |VTEMP − VTEMPSP| ≤ 5mV TEMP = On @SDNG = 0 TECNEG: Linear; TECPOS: Filtered PWM Two 10MΩ resistors on TEMPSP pin: Not removed Max. |VTEMP − VTEMPSP| ≤ 2mV TEMP = On @SDNG = 0 TECNEG: Linear; TECPOS: Filtered PWM Two 10MΩ resistors on TEMPSP pin: Not removed Max. |VTEMP − VTEMPSP| ≤ 0.5mV TEMP = On @SDNG = 0 TECNEG: Linear; TECPOS: Filtered PWM Two 10MΩ resistors on TEMPSP pin: Not removed No internal temperature range setting network

Copyrights 2000-2022, Analog Technologies, Inc. All Rights Reserved. Updated on 4/28/2022 Email: staff@analogti.com/sales@analogti.com 9 Analog Technologies TEC5V6A-NT High Efficiency TEC Controller TEMP = Off @SDNG = 0 TECNEG: Filtered PWM; TECPOS: Linear Two 10MΩ resistors on TEMPSP pin: Not removed Max. |VTEMP − VTEMPSP| ≤ 0.5mV TEMP = Off @SDNG = 0 TECNEG: Filtered PWM; TECPOS: Linear Two 10MΩ resistors on TEMPSP pin: removed TEMP = Off @SDNG = 0 TECNEG: Filtered PWM; TECPOS: Linear Two 10MΩ resistors on TEMPSP pin: Not removed With internal compensation network TEMP = Off @SDNG = 0 TECNEG: Filtered PWM; TECPOS: Linear Two 10MΩ resistors on TEMPSP pin: Not removed Max. |V TEMP − VTEMPSP| ≤ 5mV TEMP = Off @SDNG = 0 TECNEG: Filtered PWM; TECPOS: Linear Two 10MΩ resistors on TEMPSP pin: removed TEMP = Off @SDNG= 0 TECNEG: Filtered PWM; TECPOS: Linear Two 10MΩ resistors on TEMPSP pin: Not removed With internal compensation network TECA1-5V5V-NT 5V ±V VPS 25.4×19.9×8.8 TEMP = Off @SDNG = 0 TECNEG: Filtered PWM; TECPOS: Linear Two 10MΩ resistors on TEMPSP pin: Not removed No internal temperature range setting network TEMP = Off @SDNG = 0 TECNEG: Filtered PWM; TECPOS: Linear Two 10MΩ resistors on TEMPSP pin: Not removed Smaller size NOTICE 1. ATI warrants performance of its products for one year to the sp ecifications applicable at the time of sale, except for those being damaged by excessive abuse. Products found not meeting th e specifications within one year from the date of sale can be exchanged free of charge. 2. ATI reserves the right to make changes to its products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant informatio n to verify, before placing orders, that information being relied on is current and complete. 3. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. Testing and other quality control techniques are utilized to the extent ATI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. 4. Customers are responsible for their applications using ATI components. In order to minimize risks associated with the customers’ applications, adequate design and operating safeguards must be provided by the customers to minimize inherent or procedural hazards. ATI assumes no liability for applications assistance or customer product design. 5. ATI does not warrant or represen t that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ATI covering or relating to any combination, machine, or process in which such products or services might be or are used. ATI’s publication of information regarding any third party’s products or services does not constitute ATI’s approval, warranty or endorsement thereof. 6. IP (Intellectual Property) Ownership: ATI retains the ownership of full rights for special technologies and/or techniques embedded in its products, the designs for mechanics, optics, plus all modifications, improvements, and inventions made by ATI for its products and/or projects.