TCS3471 OSRAM | Alldatasheet
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[v1-01] 2018-Mar-27 Document Feedback TCS3471 Color Light-to-Digital Converter The TCS3471 family of devices provides red, green, blue, and clear light sensing (RGBC) that detects light intensity under a variety of lighting conditions and through a variety of attenuation materials. An internal state machine provides the ability to put the device into a low power mode in between RGBC measurements providing very low average power consumption. The TCS3471 is directly useful in lighting conditions containing minimal IR content such as LED RGB backlight control, reflected LED color sampler, or fluorescent light color temperature detector. With the addition of an IR blocking filter, the device is an excellent ambient light sensor, color temperature monitor, and general purpose color sensor. Ordering Information and Content Guide appear at end of datasheet. Key Benefits & Features The benefits and features of TC S3471, Color Light-to-Digital Converter are listed below: Figure 1: Added Value Of Using TCS3471
- Color Light Sensing
- Programmable Analog Gain , Integration Time, and Interrupt Function with Upper and Lower Thresholds
- Resolution Up to 16 Bits
- Very High Sensitivity - Idea lly Suited for Operation Behind Dark Glass
- Up to 1,000,000:1 Dynamic Range Benefits Features
- Enables Accurate Color and Ambient Light Sensing Under Varying Lighting Conditions • 1M:1 Dynamic Range
- Minimizes Motion / Transient Errors • Four Independent Analog-to-Digital Converters
- Clear-Channel Provides a Reference Allows for Isolation of Color Content
- A Reference-Channel for Color Analysis (Clear Channel Photo-diode)
- Reduces Micro-Processor Interrupt Overhead • Programmable Interrupt Function
- Reduces Board Space Requirements While Simplifying Designs
- Area Efficient 2mm x 2.4mm Dual Flat No-Lead (FN) Package General Description
Document Feedback [v1-01] 2018-Mar-27 TCS3471 − General Description
- Low Power Wait State
- 6 5 μA Typical Current
- Wait Timer is Programmable from 2.4 ms to > 7seconds
- Sleep Mode - 2.5 μA Typical Current
- I²C Interface Compatible
- Up to 400 kHz (I²C Fast Mode)
- Dedicated Interrupt Pin
- Pin and Register Set Compatible with the TCS3x7x Family of Devices
Applications
TCS3471, Color Light-to-Digital Converter is ideal for:
- Color Temperature Sensing
- RGB LED Backlight Control
- Color Display Closed-Loop Feedback Control
- Ambient Light Sensing for Display Brightness Control
- Industrial Process Control
- Medical Diagnostics End Products and Market Segments
- HDTVs, Mobile Handsets, Tabl ets, Laptops, Monitors, PMP (Portable Media Payers)
- Medical Instrumentation
- Consumer Toys
- Industrial/Commercial Lighting
[v1-01] 2018-Mar-27 Document Feedback TCS3471 − General Description Functional Block Diagram The functional blocks of this device are shown below: Figure 2: TCS3471 Block Diagram SDA VDD INT SCL Wait Control Clear ADC Upper Limit Lower Limit Interrupt I2C Interface GND Red ADC Green ADC Blue ADC Clear Data Red Data Green Data Blue Data RGBC Control Blue Green Red Clear
Document Feedback [v1-01] 2018-Mar-27 TCS3471 − Pin Assignments Figure 3: Package FN Dual Flat No-Lead (Top View) Figure 4: Terminal Func tions Pin Diagram: Package Drawing Not to Scale Terminal Type Description Name No. VDD 1 Supply voltage. SCL 2 I I²C Serial clock input terminal - clock signal for I²C serial data. GND 3 Power supply ground. All voltages are referenced to GND. NC 4 Do not connect INT 5 O Interrupt - open drain. SDA 6 I/O I²C Serial data I/O terminal - serial data I/O for I²C. Pin Assignments VDD 1 SCL 2 GND 3
6 SDA
5 INT
[v1-01] 2018-Mar-27 Document Feedback TCS3471 − Detailed Description The TCS3471 light-to-digital device contains a 4 × 4 photodiode array, integrating amplifiers, ADCs, accumulators, clocks, buffers, comparators, a state machine, and an I²C interface. The 4 × 4 photodiode array is composed of red-filtered, green-filtered, blue-filtered, and clear photodiodes — four of each type. Four integrating ADCs simultaneously convert the amplified photodiode currents to a digital value providing up to 16 bits of resolution. Upon completion of the conversion cycle, the conversion result is transferred to the data registers. The transfers are double-buffered to ensure that the integrity of the data is maintained. Communication to the device is accomplished through a fast (up to 400 kHz), two-wire I²C serial bus for easy connection to a microcontroller or embedded controller. The TCS3471 provides a separate pin for level-style interrupts. When interrupts are enabled and a pre-set value is exceeded, the interrupt pin is asserted an d remains asserted until cleared by the controlling firmware. The interrupt feature simplifies and improves system efficiency by eliminating the need to poll a sensor for a light intensity value. An interrupt is generated when the value of an RGBC conversion exceeds either an upper or lower threshold. In addition, a programmable interrupt persistence feature allows the user to determine how many consecutive exceeded thresholds are necessary to trigger an interrupt. Detailed Description
[v1-01] 2018-Mar-27 Document Feedback TCS3471 − Absolute Maximum Ratings Figure 11: Note(s): 1. Specified by design and characterization; not production tested. Symbol Parameter(1) Test Conditions Min Typ Max Unit f(SCL) Clock frequency (I²C) 0 400 kHz t(BUF) Bus free time between start and stop condition 1.3 μs t(HDSTA) Hold time after (repeated) start condition. After this period, the first clock is generated. 0.6 μs t(SUSTA) Repeated start condition setup time 0.6 μs t(SUSTO) Stop condition setup time 0.6 μs t(HDDAT) Data hold time 0 μs t(SUDAT) Data setup time 100 ns t(LOW) SCL clock low period 1.3 μs t(HIGH) SCL clock high period 0.6 μs tF Clock/data fall time 300 ns tR Clock/data rise time 300 ns Ci Input pin capacitance 10 pF
Document Feedback [v1-01] 2018-Mar-27 TCS3471 − Absolute Maximum Ratings Parameter Measurement Information Figure 12: Timing Diagrams SDA SCL StopStart SCLACK t(LOWMEXT) t(LOWMEXT) t(LOWSEXT) SCLACK t(LOWMEXT) Start Condition Stop Condition P SDA t(SUSTO)t(SUDAT)t(HDDAT)t(BUF) VIH VIL SCL t(SUSTA)t(HIGH) t(F)t(R) t(HDSTA) t(LOW) VIH VIL PS S
[v1-01] 2018-Mar-27 Document Feedback TCS3471 − Principles Of Operation System State Machine The TCS3471 provides control of RGBC and power management functionality through an internal state machine ( Figure 17 ). After a power-on-reset, the device is in the sleep mode. As soon as the PON bit is set, the device wi ll move to the start state. It will then continue through the Wait and RGBC states. If these states are enabled, the device will execute each function. If the PON bit is set to 0, the state machine will continue until all conversions are completed and then go into a low power sleep mode. Figure 17: Simplified State Diagram Note(s): In this document, the nomenclature uses the bit field name in italics followed by the register number and bit number to allow the user to easily identify the register and bit that controls the function. For example, the power on (PON) is in register 0, bit 0. This is represented as PON (r0:b0) . Principles Of Operation Sleep Start RGBCWait PON = 1 (r0:b0) PON = 0 (r0:b0)
Document Feedback [v1-01] 2018-Mar-27 TCS3471 − Principles Of Operation RGBC Operation The RGBC engine contains RGBC gain control (AGAIN) and four integrating analog-to-digital converters (ADC) for the RGBC photodiodes. The RGBC integrat ion time (ATIME) impacts both the resolution and the sensit ivity of the RGBC reading. Integration of all four channels occurs simultaneously and upon completion of the conversion cycl e, the results are transferred t o t h e c o l o r d a t a r e g i s t e r s . T h i s d a t a i s a l s o r e f e r r e d t o a s c h a n n e l count . The transfers are double-buffered to ensure that invalid data is not read during the transfer. After the transfer, the device automatically moves to the next state in accordance with the configured state machine. Figure 18: RGBC Operation The registers for programming the integration and wait times are a 2’s compliment values. The actual time can be calculated as follows: ATIME = 256 - Integration Time / 2.4 ms Inversely, the time can be calculated from the register value as follows: Integration Time = 2.4 ms × (256 - ATIME) For example, if a 100ms integration time is needed, the device needs to be programmed to: 256 - (100 / 2.4) = 256 - 42 = 214 = 0xD6 Conversely, the programmed value of 0xC0 would correspond to: AGAIN(r0x0F, b1:0) 1/C0121, 4/C0121, 16/C0121, 60/C0121 Gain CDATAH(r0x15), CDATA(r0x14)Clear ADC Red ADC Green ADC Blue ADC Clear Data Red Data Green Data Blue Data RGBC Control Blue Green Red Clear RDATAH(r0x17), RDATA(r0x16) GDATAH(r0x19), GDATA(r0x18) BDATAH(r0x1B), BDATA(r0x1A) ATIME(r 1) 2.4 ms to 700 ms (EQ1) (EQ2)
[v1-01] 2018-Mar-27 Document Feedback TCS3471 − Principles Of Operation Interrupts The interrupt feature simplifies and improves system efficiency by eliminating the need to poll the sensor for light intensity values outside of a user-defin ed range. While the interrupt function is always enabled and it ’s status is available in the status register (0x13), the output of the interrupt state can be enabled using the RGBC interrupt enable (AIEN) field in the enable register (0x00). Two 16-bit interrupt threshold re gisters allow the user to set limits below and above a desired light level range. An interrupt can be generated when the RGBC Clear data (CDATA) falls outside of the desired light level range, as determined by the values in the RGBC interrupt low threshold registers (AILTx) and RGBC interrupt high threshold regi sters (AIHTx). It is important to note that the low threshold va lue must be less than the high threshold value for proper operation. To further control when an interrupt occurs, the device provides a persistence filter. The persiste nce filter allows the user to specify the number of cons ecutive out-of-range RGBC occurrences before an interrupt is generated. The persistence register (0x0C) allows the user to set the persistence (APERS) value. See the Persistence Register (0x0C) for details on the persistence filter values. Once the persistence filter generates an interrupt, it will continue un til a special function interrupt clear command is received (see Command Register ). Figure 19: Programmable Interrupt Clear ADC Clear Data Clear Upper Limit Lower Limit AIHTH(r07), AIHTL(r06) RGBC Persistence AILTH(r05), AILTL(r04) PPERS(r 0x0C, b3:0)
[v1-01] 2018-Mar-27 Document Feedback TCS3471 − Principles Of Operation I²C Protocols Interface and control are accomplished through an I²C serial compatible interface (standard or fast mode) to a set of registers that provide access to device cont rol functions and output data. The devices support the 7-bit I²C addressing protocol. The I²C standard provides for three types of bus transaction: read, write, and a combined protocol ( Figure 21 ). During a write operation, the first byte written is a command byte followed by data. In a combined protocol, the first byte written is the command byte followed by reading a series of bytes. If a read command is issued, the register address from the previous command will be used for data access. Likewise, if the MSB of the command is not set, the device will write a series of bytes at the address stored in the last valid command with a register address. The command byte contains either control information or a 5-bit register address. The control commands can also be used to clear interrupts. The I²C bus protocol was develo ped by Philips (now NXP). For a complete description of the I²C protocol, please review the NXP I²C design specification at http://www.i2c-bus.org/references/ . Figure 21: I²C Protocols W Data ByteSlave AddressS AA A 811 1 8 Command Code P ... I2C Write Protocol I2C Read Protocol I2C Read Protocol — Combined Format R DataSlave AddressS AA A 811 1 8 Data P ... W Slave AddressSlave AddressS AR A 811 1 7 1 1 Command Code Sr A Data AA 81 8 Data P ... A Acknowledge (0) N Not Acknowledged (1) P Stop Condition R Read (1) S Start Condition Sr Repeated Start Condition W Write (0) ... Continuation of protocol Master-to-Slave Slave-to-Master
Document Feedback [v1-01] 2018-Mar-27 TCS3471 − Register Description The TCS3471 is controlled and mo nitored by data registers and a command register accessed th rough the serial interface. These registers provide for a variety of control functions and can be read to determine results of the ADC conversions. The register set is summarized in Figure 22 . Figure 22: Register Set The mechanics of accessing a spec ific register depends on the specific protocol used. See the section on I²C protocols on the previous pages. In general, the COMMAND register is written first to specify the specific control/status register for the following read/write operations. Address Register Name R/W Register Function Reset Value −− COMMAND W Specifies register address 0x00 0x00 ENABLE R/W Enables states and interrupts 0x00 0x01 ATIME R/W RGBC ADC time 0xFF 0x03 WTIME R/W Wait time 0xFF 0x04 AILTL R/W RGBC interrupt low threshold low byte 0x00 0x05 AILTH R/W RGBC interrupt low threshold high byte 0x00 0x06 AIHTL R/W RGBC interrupt high threshold low byte 0x00 0x07 AIHTH R/W RGBC interrupt hi gh threshold high byte 0x00 0x0C PERS R/W Interrupt persistence filters 0x00 0x0D CONFIG R/W Configuration 0x00 0x0F CONTROL R/W Gain control register 0x00 0x12 ID R Device ID ID 0x13 STATUS R Device status 0x00 0x14 CDATA R Clear ADC low data register 0x00 0x15 CDATAH R Clear ADC high data register 0x00 0x16 RDATA R Red ADC low data register 0x00 0x17 RDATAH R Red ADC high data register 0x00 0x18 GDATA R Green ADC low data register 0x00 0x19 GDATAH R Green ADC high data register 0x00 0x1A BDATA R Blue ADC low data register 0x00 0x1B BDATAH R Blue ADC high data register 0x00 Register Description
[v1-01] 2018-Mar-27 Document Feedback TCS3471 − Register Description Command Register The command registers specifie s the address of the target register for future write and read operations. Figure 23: Command Register 76 5 4 3 2 1 0 COMMAND TYPE ADD Field Bits Description COMMAND 7 Select Command Register. Must write as 1 when addressing COMMAND register. TYPE 6:5 Selects type of transaction to follow in subsequent data transfers: FIELD VALUE INTEGRATION TIME
00 Repeated byte protocol transaction
01 Auto-increment protocol transaction
10 Reserved — Do not use
11 Special function — See description below
Byte protocol will repeatedly read the same register with each data access. Block protocol will provide auto-increment function to read successive bytes. ADD 4:0 Address field/special function field. De pending on the transaction type, see above, this field either specifies a special function command or selects the specific control-status-register for following write and read transactions. The field values listed below apply only to special function commands: FIELD VALUE READ VALUE
00000 Normal — no action
00110 RGBC interrupt clear
other Reserved — Do not write RGBC Interrupt Clear. Clears any pending RGBC interrupt. This special function is self clearing.
Document Feedback [v1-01] 2018-Mar-27 TCS3471 − Register Description Enable Register (0x00) The Enable register is used primarily to power the TCS3471 device on and off, and enable fu nctions and interrupts as shown in Figure 24 . Figure 24: Enable Register Note(s): 1. A minimum interval of 2.4 ms must pass after PO N is asserted before an RGBC can be initiated. 76 5 4 3 2 1 0 Reserved AIEN WEN Reserved AEN PON Field Bits Description Reserved 7:5 Reserved. Write as 0. AIEN 4 RGBC interrupt enable. When asserted, permits RGBC interrupts to be generated. WEN 3 Wait enable. This bit activates the wait feature. Writing a 1 activates the wait timer. Writing a 0 disables the wait timer. Reserved 2 Reserved. Write as 0. AEN 1 RGBC enable. This bit actives the two-channel ADC. Writing a 1 activates the RGBC. Writing a 0 disables the RGBC. PON(1) 0 Power ON. This bit activates the internal oscillator to permit the timers and ADC channels to operate. Writing a 1 activates the oscillator. Writing a 0 disables the oscillator. During reads and writes over the I²C interface, this bit is temporarily overridden and the oscillator is enabled, independent of the state of PON.
Document Feedback [v1-01] 2018-Mar-27 TCS3471 − Register Description RGBC Interrupt Threshold Registers (0x04 - 0x07) The RGBC interrupt threshold registers provides the values to be used as the high and low trigger points for the comparison function for interrupt generation . If the value generated by the clear channel crosses below the lower threshold specified, or above the higher threshold, an interrupt is asserted on the interrupt pin. Figure 27: RGBC Interrupt Threshold Register Register Address Bits Description AILTL 0x04 7:0 RGBC clear channel low threshold lower byte AILTH 0x05 7:0 RGBC clear channel low threshold upper byte AIHTL 0x06 7:0 RGBC clear channel high threshold lower byte AIHTH 0x07 7:0 RGBC clear channel high threshold upper byte
[v1-01] 2018-Mar-27 Document Feedback TCS3471 − Register Description Persistence Register (0x0C) The persistence register controls the filtering interrupt capabilities of the device. Configurable filtering is provided to allow interrupts to be generated after each integration cycle or if the integration has produced a result that is outside of the values specified by the threshol d register for some specified amount of time. Figure 28: Persistence Register 76 5 4 3 2 1 0 Reserved APERS Field Bits Description Reserved 7:4 Reserved. APERS 3:0 Interrupt persistence. Controls rate of interrupt to the host processor. FIELD VALUE MEANING INTERRUPT PERSISTENCE FUNCTION
0000 Every Every RGBC cycle generates an interrupt
0001 1 1 clear channel value outside of threshold range 0010 2 2 clear channel consecutive values out of range 0011 3 3 clear channel consecutive values out of range 0100 5 5 clear channel consecutive values out of range 0101 10 10 clear channel consecutive values out of range 0110 15 15 clear channel consecutive values out of range 0111 20 20 clear channel consecutive values out of range 1000 25 25 clear channel consecutive values out of range 1001 30 30 clear channel consecutive values out of range 1010 35 35 clear channel consecutive values out of range 1011 40 40 clear channel consecutive values out of range 1100 45 45 clear channel consecutive values out of range 1101 50 50 clear channel consecutive values out of range 1110 55 55 clear channel consecutive values out of range 1111 60 60 clear channel consecutive values out of range
Document Feedback [v1-01] 2018-Mar-27 TCS3471 − Register Description RGBC Channel Data Registers (0x14 - 0x1B) Clear, red, green, and blue data is stored as 16-bit values. To ensure the data is read correctly, a two-byte read I²C transaction should be used with a read word protocol bit set in the command register. With this operation, when the lower byte register is read, the upper eight bits are stored into a shadow register, which is read by a subsequent read to the upper byte. The upper register will read the correct value even if additional ADC integration cycles end betw een the reading of the lower and upper registers. Figure 33: ADC Channel Data Registers Register Address Bits Description CDATA 0x14 7:0 Clear data low byte CDATAH 0x15 7:0 Clear data high byte RDATA 0x16 7:0 Red data low byte RDATAH 0x17 7:0 Red data high byte GDATA 0x18 7:0 Green data low byte GDATAH 0x19 7:0 Green data high byte BDATA 0x1A 7:0 Blue data low byte BDATAH 0x1B 7:0 Blue data high byte
[v1-01] 2018-Mar-27 Document Feedback TCS3471 − Application Information: Hardware Typical Hardware Application A typical hardware application circuit is shown in Figure 34 . A 1-μF low-ESR decoupling capacitor should be placed as close as possible to the V DD pin. Figure 34: Typical Application Hardware Circuit VBUS in Figure 34 refers to the I²C bus voltage, which is either VDD or 1.8 V. Be sure to apply the specified I²C bus voltage shown in the Available Options table for the specific device being used. The I²C signals and the Interrupt are open-drain outputs and require pull-up resistors. The pull-up resistor (R P) value is a function of the I²C bus speed, the I²C bus voltage, and the capacitive load. The ams EVM running at 400 kbps, uses 1.5-k Ω resistors. A 10-k Ω pull-up resistor (R PI) can be used for the interrupt line. Application Information: Hardware TCS3471 INT SDA SCL VDD 1 /C0109F GND VBUS RP RP RPI VDD
Document Feedback [v1-01] 2018-Mar-27 TCS3471 − Application Information: Hardware PCB Pad Layouts Suggested PCB pad layout guidelines for the Dual Flat No-Lead (FN) surface mount package are shown in Figure 35 . Note(s): Pads can be extended further if hand soldering is needed. Figure 35: Suggested FN Package PCB Layout Note(s): 1. All linear dimensions are in micrometers. 2. This drawing is subject to change without notice. 400 2500 400 1000 1700 650 1000 650
[v1-01] 2018-Mar-27 Document Feedback TCS3471 − Mechanical Data Figure 36: Package FN — Dual Flat No-Lead Packaging Configuration Note(s): 1. All linear dimensions are in micrometers. 2. The die is centered within the package within a tolerance of ± 75 μm. 3. Package top surface is molded with an electrically nonconduct ive clear plastic compound having an index of refraction of 1.5 5. 4. Contact finish is copper alloy A194 with pre-plated NiPdAu lead finish. 5. This package contains no lead (Pb). 6. This drawing is subject to change without notice. Mechanical Data PACKAGE FN Dual Flat No-Lead 650 BSC 203 /C0043 8 TOP VIEW SIDE VIEW BOTTOM VIEW Lead Free Pb 300 /C0043 50 2000 /C0043 75 2400 /C0043 75 PIN 1 PIN 1 END VIEW 650 /C0043 50 PIN OUT TOP VIEW 750 /C0043 100 295 Nominal 406 /C0043 10 CL of Solder Contacts and Photodiode Array Area (Note B) CL of Solder Contacts of Photodiode Array Area (Note B)CL
125 Nominal
V DD 1 SCL 2 GND 3 496 /C0043 10 Photodiode Active Area Green RoHS
Document Feedback [v1-01] 2018-Mar-27 TCS3471 − Mechanical Data Figure 37: Package FN Carrier Tape Note(s): 1. All linear dimensions are in mi llimeters. Dimension tolerance is ±0.10 mm unless otherwise noted. 2. The dimensions on this drawing are for illustrative purpos es only. Dimensions of an actual carrier may vary slightly. 3. Symbols on drawing A o, Bo, and K o are defined in ANSI EIA Standard 481-B 2001. 4. Each reel is 178 millimeters in diameter and contains 3500 parts. 5. ams packaging tape and reel conform to th e requirements of EIA Standard 481-B. 6. In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape. 7. This drawing is subject to change without notice. Green RoHS TOP VIEW DETAIL A 2.21 /C0043 0.05 Ao 0.254 /C0043 0.02 5/C0053 Max 4.00 8.00 3.50 /C0043 0.05 /C0106 1.504.00 2.00 /C0043 0.05 + 0.30 − 0.10 1.75 B BAA /C0106 0.50 /C0043 0.05 DETAIL B 2.61 /C0043 0.05 Bo 5/C0053 Max 0.83 /C0043 0.05 Ko
Document Feedback [v1-01] 2018-Mar-27 TCS3471 − Manufacturing Information Moisture Sensitivity Optical characteristics of the device can be adversely affected during the soldering process by the release and vaporization of moisture that has been previous ly absorbed into the package. To ensure the package contains the smallest amount of absorbed moisture possible, each device is dry-baked prior to being packed for shipping. Devices are packed in a sealed aluminized envelope with silica gel to protect them from ambient moisture during shipping, handling, and storage before use. The FN package has been assigned a moisture sensitivity level of MSL 3 and the devices should be stored under the following conditions:
- Temperature Range: 5ºC to 50ºC
- Relative Humidity: 60% maximum
- Total Time: 12 months from the date code on the aluminized envelope — if unopened
- Opened Time: 168 hours or fewer Rebaking will be required if the devices have been stored unopened for more than 12 months or if the aluminized envelope has been open for more than 168 hours. If rebaking is required, it should be done at 50ºC for 12 hours.
[v1-01] 2018-Mar-27 Document Feedback TCS3471 − Ordering & Contact Information Figure 40:
Ordering Information
Buy our products or get free samples online at: www.ams.com/ICdirect Technical Support is available at: www.ams.com/Technical-Support Provide feedback about this document at: www.ams.com/Document-Feedback For further information and requests, e-mail us at: ams_sales@ams.com For sales offices, distributors and representatives, please visit: www.ams.com/contact Headquarters ams AG Tobelbader Strasse 30
8141 Premstaetten
Austria, Europe Tel: +43 (0) 3136 500 0 Website: www.ams.com Ordering Code Description Device Address Package - Leads TCS34711FN I²C Vbus = V DD Interface TCS34711 0x39 FN−6 TCS34713FN I²C Vbus = 1.8 V Interface TCS34713 0x39 FN−6 TCS34715FN I²C Vbus = V DD Interface TCS34715 0x29 FN−6 TCS34717FN I²C Vbus = 1.8 V Interface TCS34717 0x29 FN−6 Ordering & Contact Information
Document Feedback [v1-01] 2018-Mar-27 TCS3471 − RoHS Compliant & ams Green Statement RoHS: The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specif ied lead-free processes. ams Green (RoHS compliant and no Sb/Br): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are unde rway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to prov ide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. RoHS Compliant & ams Green Statement
[v1-01] 2018-Mar-27 Document Feedback TCS3471 − Copyrights & Disclaimer Copyright ams AG, Tobelbader St rasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used with out the prior written consent of the copyright owner. Devices sold by ams AG are covered by the warranty and patent indemnification provisions appe aring in its General Terms of Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding th e information set forth herein. ams AG reserves the right to ch ange specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications , such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied wa rranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any th ird party shall arise or flow out of ams AG rendering of technical or other services. Copyrights & Disclaimer
Document Feedback [v1-01] 2018-Mar-27 TCS3471 − Document Status Document Status Product Status Definition Product Preview Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Preliminary Datasheet Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Datasheet Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade Datasheet (discontinued) Discontinued Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs Document Status
[v1-01] 2018-Mar-27 Document Feedback TCS3471 − Revision Information Note(s): 1. Page and figure numbers for the previous version may di ffer from page and figure numbers in the current revision 2. Correction of typographical er rors is not explicitly mentioned. Changes from 1-00 (2016-May-23) to current revision 1-01 (2018-Mar-27) Page Updated Figure 40 33 Revision Information
Document Feedback [v1-01] 2018-Mar-27 TCS3471 − Content Guide
1 General Description
1 Key Benefits & Features
2 Applications
2 End Products and Market Segments
3 Functional Block Diagram
4 Pin Assignments
5 Detailed Description
6A b s o l u t e M a x i m u m R a t i n g s
10 Parameter Measurement Information
11 Typical Operating Characteristics
13 Principles Of Operation
13 System State Machine
14 RGBC Operation
15 Interrupts
16 State Diagram
17 I²C Protocols
18 Register Description
19 Command Register
20 Enable Register (0x00)
21 RGBC Timing Register (0x01)
21 Wait Time Register (0x03)
22 RGBC Interrupt Threshold Registers
(0x04 - 0x07)