TCD2919BFG TOSHIBA | Alldatasheet
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TOSHIBA CCD Linear Image Sensor CCD (Charge Coupled Device) TCD2919BFG
Rev.1.5 2019-01-08 1 © 2017 Toshiba Electronic Devices & Storage Corporation TOSHIBA CCD Linear Image Sensor CCD (Charge Coupled Device) TCD2919BFG The TCD2919BFG is a high sensitive and low dark current 10680 elements 3 lines output CCD color linear image sensor with 10680 elements 1 line output CCD B/W linear image sensor. The device contains a row of 10680 elements × 4 lines photodiodes which provide 48 lines/mm across a A4 size paper. The device is operated by 3.3 V pulse and 10 V power supply.
Features
Number of Image Sensing Elements: 10680 elements 3 lines for Color 10680 elements 1 line for B/W Image Sensing Element Size: 2.625 m by 8.4 m on 2.625 m center for Color 2.625 m by 8.4 m on 2.625 m center for B/W Photo Sensing Region: High sensitive PN photodiode Clock: 2-phase (3.3 V) Power Supply Voltage: 10 V (typ.) Distanced between Photodiode Array: 31.5 m (12 lines) R array – G array, G array – B array 63 m (24 lines) B array – B/W array Internal Circuit: Clamp circuit Package: 22 pin CLCC Color Filter: Red, Green, Blue ABSOLUTE MAXIMUM RATINGS (Note 1) Characteristic Symbol Rating Unit Clock pulse voltage V 0.3 to +8.0 V Shift pulse voltage VSH Reset pulse voltage VRS Clamp pulse voltage VCP Switch pulse voltage VSW Power supply voltage VOD 0.3 to +13.5 V Operating temperature Topr 0 to 60 °C Storage temperature Tstg 25 to +85 °C Note 1: All voltages are with respect to SS terminals (ground). None of the ABSOLUTE MAXIMUM RATINGS must be exceeded, even instantaneously. If any one of the ABSOLUTE MAXIMUM RATINGS is exceeded, the electrical characteristics, reliability and life time of the device cannot be guaranteed. If the ABSOLUTE MAXIMUM RATINGS are exceeded, the device can be permanently damaged or degraded. Create a system design in such a manner that any of the ABSOLUTE MAXIMUM RATINGS will not be exceeded under any circumstances. Pin Connections (top view) SW1 22 1D* OD SS 1 2D 1D SH3 SW2 2A 1A SH1 SH2 OS3 OS1
7 NC SS
1 Red 10680
1B RS
Rev.1.5 2019-01-08 2 © 2017 Toshiba Electronic Devices & Storage Corporation Circuit Diagram D27 D74 D75 D27 D74 D75 CCD analog shift register 1 CCD analog shift register 2 CCD analog shift register 3 CCD ANALOG SHIFT REGISTER 3 CCD analog shift register 4 2D 1D OS2 OS1 OD Shift gate 1 D24 D25 D26 D27 D74 D75 …Photodiode… (Blue) S10679 S10680 D76 D77 D88 D89 Shift gate 2 Shift gate 3 D24 D25 D26 …Photodiode… (Green) S10679 S10680 D76 D77 D88 D89 Shift gate 4 CCD analog shift register 5 Shift gate 5 D24 D25 D26 …Photodiode… (Red) S10679 S10680 D76 D77 D88 D89 CCD analog shift register 6 Clamp Clamp Clamp OS3 4 5 …Photodiode… (B/W) Shift gate 2 1A 2A 9 SW1 Shift gate 1 CCD analog shift register 1 Clamp Clamp RS CP
13 SH3
11 SH1
1D* 1B C SS SS
12 SH2
CCD analog shift register 2 Shift gate 6
Rev.1.5 2019-01-08 3 © 2017 Toshiba Electronic Devices & Storage Corporation Pin Names Pin No. Symbol Name Pin No. Symbol Name
1 SS Ground 22 SW1 Switch gate 1 for color or B/W
2 C Last stage transfer clock for Color 21 1D* Last stage transfer clock (phase 1) for B/W 3 1B Last stage transfer clock (phase 1) for color 20 OD Power
4 RS Reset gate 19 OS3 Output signal 3 (Red)
5 CP Clamp gate 18 OS2 Output signal 2 (Green or B/W)
6 SS Ground 17 OS1 Output signal 1 (Blue or B/W)
7 NC Non connection 16 SS Ground
8 SW2 Switch gate 2 for Hi/Lo amplifier gain 15 2D Transfer clock (phase 2) for B/W
9 2A Transfer clock (phase 2) for color 14 1D Transfer clock (phase 1) for B/W 10 1A Transfer clock (phase 1) for color 13 SH3 Shift gate 3 for B/W
11 SH1 Shift gate 1 for color 12 SH2 Shift gate 2 for B/W
Arrangement of 1st Effective Pixel (S1) Blue photo diode array (10680 pixels 1 line) Green photo diode array (10680 pixels 1 line) 8.4 m Red photo diode array (10680 pixels 1 line) 8.4 m 3 5 7 2 4 6 8 1 2.625 m 8.4 m B/W photo diode array (10680 pixels 1 line) 63 m ( 2.625 m 24 lines) 3 5 7 2 4 6 8 1 3 5 7 2 4 6 8 1 2.625 m 31.5 m ( 2.625 m 12 lines) 31.5 m ( 2.625 m 12 lines) 3 5 7 2 4 6 8 1 8.4 m
Rev.1.5 2019-01-08 4 © 2017 Toshiba Electronic Devices & Storage Corporation Optical/Electrical Characteristics (Color 600 dpi, High Gain Mode) Ta 25°C, VOD 10 V, V VSH VRS VCP 3.3 V (pulse), f 2.5 MHz, fRS 5.0 MHz, tINT (integration time) 11 ms, light source A light source CM500S (t 1.0 mm) Characteristics Symbol Min Typ. Max Unit Note Sensitivity Red RR 17.1 24.5 31.8 V/lxs (Note 2) Green RG 18.7 26.7 34.7 Blue RB 11.1 15.9 20.7 Photo response non uniformity PRNU (1) 10 20 % (Note 3-1) PRNU (3) 3 12 mV (Note 4) Saturation output voltage VSAT 2.0 2.2 V (Note 6) Saturation exposure SE 0.06 0.08 lxs (Note 7) Total transfer efficiency TTE 92 99 % Output impedance ZO 66 250 Random noise ND 1.9 mV (Note 11) Optical/Electrical Characteristics (Color 600 dpi, Low Gain Mode) Ta 25°C, VOD 10 V, V VSH VRS VCP 3.3 V (pulse), f 2.5 MHz, fRS 5.0 MHz, tINT (integration time) 11 ms, light source A light source CM500S (t 1.0 mm) Characteristics Symbol Min Typ. Max Unit Note Sensitivity Red RR 11.6 16.6 21.6 V/lxs (Note 2) Green RG 12.6 18.0 23.4 Blue RB 7.5 10.6 13.8 Photo response non uniformity PRNU (1) 10 20 % (Note 3-2) PRNU (3) 3 12 mV (Note 4) Saturation output voltage VSAT 1.7 1.9 V (Note 6) Saturation exposure SE 0.07 0.11 lxs (Note 7) Total transfer efficiency TTE 92 99 % Output impedance ZO 66 250 Random noise ND 1.3 mV (Note 11)
Rev.1.5 2019-01-08 5 © 2017 Toshiba Electronic Devices & Storage Corporation Optical/Electrical Characteristics (Color 1200 dpi, High Gain Mode) Ta 25°C, VOD 10 V, V VSH VRS VCP 3.3 V (pulse), f 2.5 MHz, fRS 5.0 MHz, tINT (integration time) 11 ms, light source A light source CM500S (t 1.0 mm) Characteristics Symbol Min Typ. Max Unit Note Sensitivity Red RR 8.6 12.2 15.9 V/lxs (Note 2) Green RG 9.4 13.4 17.4 Blue RB 5.6 7.9 10.3 Photo response non uniformity PRNU (1) 10 20 % (Note 3-3) PRNU (3) 3 12 mV (Note 4) Register imbalance RI 1.3 % (Note 5) Saturation output voltage VSAT 1.00 1.42 V (Note 6) Saturation exposure SE 0.06 0.11 lxs (Note 7) Dark signal voltage VDRK 0.6 2.0 mV (Note 8) Dark signal non uniformity DSNU 4.2 10.0 mV DC power dissipation PD 432 578 mW (Note 9) Total transfer efficiency TTE 92 99 % Output impedance ZO 66 250 DC output signal voltage VOS 4.0 5.0 6.0 V (Note 10) Reset noise VRSN 0.4 V Random noise ND 2.1 mV (Note 11) Optical/Electrical Characteristics (Color 1200 dpi, Low Gain Mode) Ta 25°C, VOD 10 V, V VSH VRS VCP 3.3 V (pulse), f 2.5 MHz, fRS 5.0 MHz, tINT (integration time) 11 ms, light source A light source CM500S (t 1.0 mm) Characteristics Symbol Min Typ. Max Unit Note Sensitivity Red RR 5.8 8.3 10.8 V/lxs (Note 2) Green RG 6.3 9.0 11.7 Blue RB 3.7 5.3 6.9 Photo response non uniformity PRNU (1) 10 20 % (Note 3-4) PRNU (3) 3 12 mV (Note 4) Register imbalance RI 1.1 % (Note 5) Saturation output voltage VSAT 0.85 0.95 V (Note 6) Saturation exposure SE 0.07 0.11 lxs (Note 7) Dark signal voltage VDRK 0.4 2.0 mV (Note 8) Dark signal non uniformity DSNU 2.8 10.0 mV DC power dissipation PD 418 578 mW (Note 9) Total transfer efficiency TTE 92 99 % Output impedance ZO 66 250 DC output signal voltage VOS 3.9 4.9 5.9 V (Note 10) Reset noise VRSN 0.4 V Random noise ND 1.3 mV (Note 11)
Rev.1.5 2019-01-08 6 © 2017 Toshiba Electronic Devices & Storage Corporation Optical/Electrical Characteristics (B/W 1200 dpi, High Gain Mode) Ta 25°C, VOD 10 V, V VSH VRS VCP 3.3 V (pulse), f 5.0 MHz, fRS 5.0 MHz, tINT (integration time) 11 ms, light source A light source CM500S (t 1.0 mm) Characteristics Symbol Min Typ. Max Unit Note Sensitivity RB/W 25.8 36.8 47.9 V/lxs (Note 2) Photo response non uniformity PRNU (1) 10 20 % (Note 3-1) PRNU (3) 3 12 mV (Note 4) Saturation output voltage VSAT 2.0 2.2 V (Note 6) Saturation exposure SE 0.04 0.06 lxs (Note 7) Dark signal voltage VDRK 1.1 2.0 mV (Note 8) Dark signal non uniformity DSNU 4.5 10.0 mV DC power dissipation PD 407 578 mW (Note 9) Total transfer efficiency TTE 92 99 % Output impedance ZO 66 250 DC output signal voltage VOS 4.0 5.0 6.0 V (Note 10) Reset noise VRSN 0.4 V Random noise ND 1.8 mV (Note 11) Optical/Electrical Characteristics (B/W 1200 dpi, Low Gain Mode) Ta 25°C, VOD 10 V, V VSH VRS VCP 3.3 V (pulse), f 5.0 MHz, fRS 5.0 MHz, tINT (integration time) 11 ms, light source A light source CM500S (t 1 mm) Characteristics Symbol Min Typ. Max Unit Note Sensitivity RB/W 17.3 24.7 32.1 V/lxs (Note 2) Photo response non uniformity PRNU (1) 10 20 % (Note 3-1) PRNU (3) 3 12 mV (Note 4) Saturation output voltage VSAT 1.7 1.9 V (Note 6) Saturation exposure SE 0.05 0.07 lxs (Note 7) Dark signal voltage VDRK 0.7 2.0 mV (Note 8) Dark signal non uniformity DSNU 2.8 10.0 mV DC power dissipation PD 394 578 mW (Note 9) Total transfer efficiency TTE 92 99 % Output impedance ZO 66 250 DC output signal voltage VOS 3.9 4.9 5.9 V (Note 10) Reset noise VRSN 0.4 V Random noise ND 1.2 mV (Note 11)
Rev.1.5 2019-01-08 7 © 2017 Toshiba Electronic Devices & Storage Corporation Note 2: Sensitivity is defined for each color of signal outputs average when the photosensitive surface is applied with the light of uniform illumination and uniform color temperature. Note 3-1: PRNU (1) is defined for each color on a single chip by the expressions below when the photosensitive surface is applied with the light of uniform illumination and uniform color temperature, where measured approximately 1000 mV of signal output. X X : Average of total signal outputs X: The maximum deviation from X Note 3-2: PRNU (1) is defined for each color on a single chip by the expressions below when the photosensitive surface is applied with the light of uniform illumination and uniform color temperature, where measured approximately 800 mV of signal output. X X : Average of total signal outputs X: The maximum deviation from X Note 3-3: PRNU (1) is defined for each color on a single chip by the expressions below when the photosensitive surface is applied with the light of uniform illumination and uniform color temperature, where measured approximately 500 mV of signal output. X X : Average of total signal outputs X: The maximum deviation from X Note 3-4: PRNU (1) is defined for each color on a single chip by the expressions below when the photosensitive surface is applied with the light of uniform illumination and uniform color temperature, where measured approximately 400 mV of signal output. X X : Average of total signal outputs X: The maximum deviation from X Note 4: PRNU (3) is defined as the maximum voltage with next pixel, where measured approximately 50 mV of signal output. Note 5: Register imbalance is defined as follows. RI 10679 Σ|Xn X(n 1)| n 1 100 (%) 10679 X Note 6: VSAT is defined as the minimum saturation output voltage of all effective pixels. Condition is over exposure situation and VOD 9.5 V. Note 7: Definition of SE: SE(B/W) VSAT SE(Color) VSAT RB/W RG Note 8: VDRK is defined as average dark signal voltage of all effective pixels. DSNU is defined by the difference between average value (VDRK) and the maximum value of the dark voltage. VDRK DSNU OS
Rev.1.5 2019-01-08 8 © 2017 Toshiba Electronic Devices & Storage Corporation Note 9: PD is defined as follows. IOD is DC current dissipation. PD VOD × IOD Measurement condition is VOD 10.5 V and input pulse voltage 5.5 V. Note 10: DC output signal voltage is defined as follows. Reset noise voltage is defined as follows. Note 11: Random noise is defined as the standard deviation (sigma) of the output level difference between two adjacent effective pixels under no illumination (i.e. dark condition) calculated by the following procedure. CP pulse width: 50 ns 1) Two adjacent pixels (pixel n and n1) in one reading are fixed as measurement points. 2) Each of the output levels at video output periods averaged over 200 ns period to get V(n) and V(n1). 3) V(n1) is subtracted from V(n) to get V. V V(n) V(n1) 4) The standard deviation of V is calculated after procedure 2) and 3) are repeated 30 times (30 readings). 30 ΔVi30 1ΔV 2V|Vi|30 5) Procedure 2), 3) and 4) are repeated 10 times to get sigma value. 6) 10 sigma values are averaged. j10 value calculated using the above procedure is observed 2 times larger than that measured relative to the ground level. So we specify the random noise as follows. ND SS VOS VRSN OS Output waveform (effective pixels under dark condition) Video output 200 ns 200 ns Pixel n Pixel n1 Video output
Rev.1.5 2019-01-08 9 © 2017 Toshiba Electronic Devices & Storage Corporation Recommended Operating Conditions (Ta 25°C) For best performance, the device should be used within the Recommended Operating Conditions. Characteristics Symbol Min Typ. Max Unit Clock pulse voltage “H” level V1A, V2A V1D, V2D 3.1 3.3 5.5 V “L” level 0 0 0.1 Last stage clock pulse voltage “H” level V1B, VC, V1D* 3.1 3.3 5.5 V “L” level 0 0 0.1 Shift pulse voltage “H” level VSH 2.7 3.3 5.5 V “L” level 0 0 0.8 Reset pulse voltage “H” level VRS 3.1 3.3 5.5 V “L” level 0 0 0.5 Clamp pulse voltage “H” level VCP 3.1 3.3 5.5 V “L” level 0 0 0.5 Switch pulse voltage “H” level VSW 2.7 3.3 5.5 V “L” level 0 0 0.8 Power supply voltage VOD 9.5 10.0 10.5 V Clock Characteristics (Ta 25°C) For best performance, the device should be used within the Recommended Operating Conditions. Characteristics Symbol Min Typ. Max Unit Clock pulse frequency f 2.5 2.5 35.0 MHz Reset pulse frequency fRS 5.0 5.0 35.0 MHz Clamp pulse frequency fCP 5.0 5.0 35.0 MHz Clock (1A) capacitance for Color (Note 12) C1A 163 pF Clock (2A) capacitance for Color (Note 12) C2A 165 pF Last stage clock capacitance (Note 12) C1B, CC, C1D* 6 pF Clock (1D) capacitance for B/W (Note 12) C1D 72 pF Clock (2D) capacitance for B/W (Note 12) C2D 73 pF Shift gate (SH1) capacitance for Color CSH1 14 pF Shift gate (SH2) capacitance for B/W CSH2 14 pF Shift gate (SH3) capacitance for B/W CSH3 5.3 pF Reset gate capacitance CRS 7 pF Clamp gate capacitance CCP 6 pF Switch gate capacitance CSW 13 pF Note 12: VOD 10 V, Input capacitance per a pin.
Rev.1.5 2019-01-08 10 © 2017 Toshiba Electronic Devices & Storage Corporation Clocking Mode Mode SW1 SW2 SH1 SH2 SH3 1A, 2A 1B C 1D, 2D 1D* RS CP Bi clamp / Line clamp Color High gain 1200 dpi 1A Pulse “L” Pulse Pulse 600 dpi 1A Low gain 1200 dpi 1A Pulse “L” Pulse Pulse 600 dpi 1A B/W High gain 1200 dpi Pulse Pulse “L” Pulse Pulse Pulse 600 dpi Pulse Pulse Low gain 1200 dpi Pulse Pulse “L” Pulse Pulse Pulse 600 dpi Pulse Pulse
Rev.1.5 2019-01-08 11 © 2017 Toshiba Electronic Devices & Storage Corporation Timing Chart 1: Color 1200 dpi Mode (Bit Clamp Mode) SH1 tINT (integration time) 1A, 1B 2A CP RS 1 line readout period (10776 elements) Dummy outputs (24 elements) Light shielded outputs (48 elements) (4 elements) Dummy outputs (6 elements) Test outputs (2 elements) Dummy outputs (8 elements) Dummy outputs (76 elements) Effective outputs (10680 elements) (4 elements) Dummy outputs (20 elements) D80 D89 D90 D88 D75 D73 D21 D22 S10678 S10676 D76 D78 OS1, 2, 3 D26 D23 S10677 D94 D91 D24 D25 D74 D72 S10679 S10680 D77 D79 D86 D81 D92 D93 SW1 (“L”) SH2, 3 (“H”) D95 D85 D70 D27 D71 D69
Rev.1.5 2019-01-08 12 © 2017 Toshiba Electronic Devices & Storage Corporation Timing Chart 2: Color 1200 dpi Mode (Line Clamp Mode) SH1 tINT (integration time) 1A, 1B 2A CP RS D80 D89 D90 D88 D75 D73 D21 D22 S10678 S10676 D76 D78 OS1, 2, 3 D26 D23 S10677 D94 D91 D24 D25 D74 D72 S10679 S10680 D77 D79 D86 D81 D92 D93 SW1 (“L”) SH2, 3 (“H”) D95 D85 D70 D27 D71 D69 D87 1 line readout period (10776 elements) Dummy outputs (24 elements) Light shielded outputs (48 elements) (4 elements) Dummy outputs (6 elements) Test outputs (2 elements) Dummy outputs (8 elements) Dummy outputs (76 elements) Effective outputs (10680 elements) (4 elements) Dummy outputs (20 elements)
Rev.1.5 2019-01-08 13 © 2017 Toshiba Electronic Devices & Storage Corporation Timing Chart 3: Color 600 dpi Mode (Bit Clamp Mode) 2A RS CP OS1, 2, 3 1 line readout period (5388 elements) Dummy outputs (12 elements) Light shielded outputs (24 elements) (2 elements) Dummy outputs (3 elements) Test output (1 element) Dummy outputs (4 elements) Dummy outputs (38 elements) Effective outputs (5340 elements) Dummy outputs (10 elements) D80+D81 D88+D89 D90+D91 D86+D87 S3+S4 D74+D75 D72+D73 D70+D71 D20+D21 D0+D1 S1+S2 D22+D23 S10677+S10678 S10679+S10680 D76+D77 D76+D77 D78+D79 D2+D3 D26+D27 D24+D25 S10675+S10676 D92+D93 D94+D95 1A, 1B, C SW1 (“L”) SH1 tINT (integration time) SH2, 3 (“H”) (2 elements)
Rev.1.5 2019-01-08 14 © 2017 Toshiba Electronic Devices & Storage Corporation Timing Chart 4: Color 600 dpi Mode (Line Clamp Mode) SH1 tINT (integration time) 2A RS OS1, 2, 3 D80+D81 D88+D89 D90+D91 D86+D87 S3+S4 D74+D75 D72+D73 D70+D71 D20+D21 D0+D1 S1+S2 D22+D23 S10677+S10678 S10679+S10680 D76+D77 D78+D79 D2+D3 D26+D27 D24+D25 S10675+S10676 D92+D93 CP 1A, 1B, C D94+D95 SW1 (“L”) SH2, 3 (“H”) 1 line readout period (5388 elements) Dummy outputs (12 elements) Light shielded outputs (24 elements) (2 elements) Dummy outputs (3 elements) Test output (1 element) Dummy outputs (4 elements) Dummy outputs (38 elements) Effective outputs (5340 elements) Dummy outputs (10 elements) (2 elements)
Rev.1.5 2019-01-08 15 © 2017 Toshiba Electronic Devices & Storage Corporation Timing Chart 5: B/W 1200 dpi Mode (Bit Clamp Mode) SH1 (“H”) CP OS2 1 line readout period (2694 elements) Dummy outputs (6 elements) (1 element) Test output (1 element) Dummy outputs (19 elements) Effective outputs (2670 elements) (1 element) Dummy outputs (5 elements) D94 D90 D74 D70 D22 S10679 D78 D82 D26 1A, 2A, 1B, C (“L”) OS1 SW1 (“H”) 2D RS 1D, 1D* D92 D88 D72 D68 D20 S10677 D76 D80 D24 Dummy outputs (2 elements) (1 element) 1 line readout period (2694 elements) Dummy outputs (6 elements) (1 element) Test output (1 element) Dummy outputs (19 elements) (1 element) D87 D91 D95 D75 D71 D23 S10680 D79 D83 D27 D85 D89 D93 D73 D69 D21 S10678 D77 D81 D25 (1 element) Dummy outputs (5 elements) D86 D84 1 line readout period (2694 elements) Dummy outputs (6 elements) (1 element) Test output (1 element) Dummy outputs (19 elements) (1 element) Dummy outputs (5 elements) D94 D90 D74 D70 D22 S10679 D78 D82 D26 D92 D88 D72 D68 D20 S10677 D76 D80 D24 Dummy outputs (2 elements) (1 element) D86 D84 tINT (integration time) SH3 tINT (integration time) SH2 Effective outputs (2670 elements) Light shielded outputs (12 elements) Light shielded outputs (12 elements) Light shielded outputs (12 elements) Dummy outputs (2 elements) Effective outputs (2670 elements)
Rev.1.5 2019-01-08 16 © 2017 Toshiba Electronic Devices & Storage Corporation Timing Chart 6: B/W 1200 dpi Mode (Line Clamp Mode) SH1 (“H”) CP OS2 1 line readout period (2694 elements) Dummy outputs (6 elements) (1 element) Test output (1 element) Dummy outputs (19 elements) Effective outputs (2670 elements) (1 element) Dummy outputs (5 elements) D94 D90 D74 D70 D22 S10679 D78 D82 D26 1A, 2A, 1B, C (“L”) OS1 SW1 (“H”) 2D RS 1D, 1D* D92 D88 D72 D68 D20 S10677 D76 D80 D24 Dummy outputs (2 elements) (1 element) 1 line readout period (2694 elements) Dummy outputs (6 elements) (1 element) Test output (1 element) Dummy outputs (19 elements) Effective outputs (2670 elements) (1 element) D87 D91 D95 D75 D71 D23 S10680 D79 D83 D27 D85 D89 D93 D73 D69 D21 S10678 D77 D81 D25 Dummy outputs (2 elements) (1 element) Dummy outputs (5 elements) D86 D84 1 line readout period (2694 elements) Light shielded outputs (12 elements) (1 element) Test output (1 element) Dummy outputs (19 elements) Effective outputs (2670 elements) (1 element) Dummy outputs (5 elements) D94 D90 D74 D70 D22 S10679 D78 D82 D26 D92 D88 D72 D68 D20 S10677 D76 D80 D24 Dummy outputs (2 elements) (1 element) D86 D84 tINT (integration time) SH2 tINT (integration time) SH3 Light shielded outputs (12 elements) Dummy outputs (6 elements) Light shielded outputs (12 elements)
Rev.1.5 2019-01-08 17 © 2017 Toshiba Electronic Devices & Storage Corporation Timing Chart 7: B/W 600 dpi Mode (Bit Clamp Mode) SH1 (“H”) CP OS2 D71 D74+D75 D77 D62+D63 D58+D59 S3+S4 D11 D66+D67 S10679+S10680 D69 D14+D15 1A, 2A, 1B, C (“L”) OS1 tINT (integration time) SH2, 3 SW1 (“H”) 2D RS 1D, 1D* D70 D72+D73 D76 D60+D61 D56+D57 S1+S2 D10 D64+D65 S10677+S10678 D68 D12+D13 1 line readout period (2694 elements) (1 element) Test output (1 element) Dummy outputs (19 elements) Effective outputs (2670 elements) (1 element) Dummy outputs (5 elements) Dummy outputs (2 elements) (1 element) Dummy outputs (6 elements) Light shielded outputs (12 elements)
Rev.1.5 2019-01-08 18 © 2017 Toshiba Electronic Devices & Storage Corporation Timing Chart 8: B/W 600 dpi Mode (Line Clamp Mode) tINT (integration time) SH2, 3 CP OS2 D71 D74+D75 D77 D62+D63 D58+D59 S3+S4 D11 D66+D67 S10679+S10680 D69 D14+D15 1A, 2A, 1B, C (“L”) OS1 SW1 (“H”) SH1 (“H”) 2D RS 1D, 1D* D70 D72+D73 D76 D60+D61 D56+D57 S1+S2 D10 D64+D65 S10677+S10678 D68 D12+D13 1 line readout period (2694 elements) (1 element) Test output (1 element) Dummy outputs (19 elements) Effective outputs (2670 elements) (1 element) Dummy outputs (5 elements) Dummy outputs (2 elements) (1 elements) Dummy outputs (6 elements) Light shielded outputs (12 elements)
Rev.1.5 2019-01-08 19 © 2017 Toshiba Electronic Devices & Storage Corporation Timing Requirements Cross point timing (Clock pulse voltage 3.3 V) Note 16: Pulse width is the period when voltage difference between 2A and 1B/C, 2D and 1D* is over 3.0 V. Observe the specification strictly because of normal transfer efficiency. Cross point timing (Clock pulse voltage 5.0 V) Note 16: Pulse width is the period when voltage difference between 2A and 1B/C, 2D and 1D* is over 3.0 V. Observe the specification strictly because of normal transfer efficiency. 1A 2A SS
3.5 V (max)
1.5 V (min)
3.0 V (min) 3.0 V (min) 3.1 V 0.1 V 1D 2D SS SS 2A 1B, C 0.5 V (min) 4.5 V (max) t7(Note 16) 3.0 V (min) 3.0 V (min) 3.0 V (min) 3.0 V (min) 3.1 V 0.1 V SS 2D 1D* 0.5 V (min) 4.5 V (max) 3.0 V (min) 3.0 V (min) 3.1 V 0.1 V 3.1 V 0.1 V t7(Note 16) t2 t3 t4 t6 RS CP SH (Note 13) 10 % 10 % 90 % 90 % 90 % 10 % 90 %
3.3 V or 5 V
Note 13: Keep the RS and CP pins “L” level. 1A 2A SS
2.0 V (max)
1.0 V (min)
3.0 V (min) 3.0 V (min) 3.1 V 0.1 V 1D 2D SS SS 2A 1B, C 0.3 V (min) 3.0 V (max) t7(Note 16) 3.0 V (min) 3.0 V (min) 3.0 V (min) 3.0 V (min) 3.1 V 0.1 V SS 2D 1D* 0.3 V (min) 3.0 V (max) 3.0 V (min) 3.0 V (min) 3.1 V 0.1 V 3.1 V 0.1 V t7(Note 16)
Rev.1.5 2019-01-08 20 © 2017 Toshiba Electronic Devices & Storage Corporation Color 1200 dpi mode Color 600 dpi mode 90 % 10 % 2A 1A 10 % Video signal 10 % t19 OS (Line clamp mode) OS (Bit clamp mode) RS CP Video signal 10 % t19 Video signal Video signal 90 % 10 % 90 % 10 % 90 % t15 t17 t18 t16 t13 t14 t12 t10 t11 90 % 90 % t15 10 % 10 % 10 % 90 % 10 % 90 % 10 % 90 % 90 % 10 % 10 %
5.0 V or
3.3 V 3.3 V 3.3 V 3.3 V 10 % 10 % t20 10 % 1B 10 % 90 % 90 % t8’ t8’ t9’ 5.0 V or 3.3 V 3.3 V 10 % t9’ 10 % t20 Video signal 1A 10 % OS (Line clamp mode) OS (Bit clamp mode) RS CP t19 2A 10 % 90 % 90 % 10 % Video signal 3.3 V 3.3 V 3.3 V 3.3 V 10 % 10 % 1B, C 90 % 10 % t9’ 10 % 90 % 10 % 90 % 90 % 10 % t12 t10 t11 90 % 10 % 90 % 10 % t15 90 % t18 t16 t13 90 % 10 % 10 % t17 t14 3.3 V t8’ t20
Rev.1.5 2019-01-08 21 © 2017 Toshiba Electronic Devices & Storage Corporation B/W 1200 dpi mode & B/W 600 dpi mode (SH2 SH3) Video signal 1D 10 % OS (Line clamp mode) OS (Bit clamp mode) RS CP t19 2D 10 % 90 % 90 % 10 % 3.3 V 3.3 V 3.3 V 3.3 V 10 % 10 % t20 1D* 10 % 10 % 90 % 90 % 3.3 V 10 % 90 % 10 % 90 % t8’ t9’ 90 % t18 t16 t13 90 % 10 % 10 % t14 t12 t10 t11 90 % 10 % 90 % 10 % t17 t15 Video signal
Rev.1.5 2019-01-08 22 © 2017 Toshiba Electronic Devices & Storage Corporation Characteristics Symbol Min Typ. (Note 14) Max Unit Pulse timing of SH and 1 t1 120 200 2500 ns t5 1000 1075 2500 ns SH pulse rise time, fall time t2, t4 0 10 ns SH pulse width t3 3000 3500 ns Pulse timing of SH and RS t6 975 ns 1A, 2A pulse width (Note 15) t7 6 90 ns 1D, 2D pulse width (Note 15) 2A, 1B/ C pulse width (Note 16) 2D, 1D* pulse width (Note 16) 1A, 2A pulse rise time, fall time t8, t9 0 15 ns 1D, 2D pulse rise time, fall time 1B, C, 1D* pulse rise time, fall time t8’, t9’ 0 3 8 ns RS pulse rise time, fall time t10, t11 0 10 ns RS pulse width t12 6 15 ns Pulse timing of RS and CP t13 0 0 ns t14 6 50 ns Pulse timing of 1B and CP t15 -2 40 ns Pulse timing of C and CP Pulse timing of 1D* and CP CP pulse rise time, fall time t16, t17 0 10 ns CP pulse width t18 6 40 ns Video data delay time 1B and OS t19 8.5 ns C and OS 8.5 ns 1D* and OS 8.5 ns RS and OS t20 3.1 ns Pulse timing of SH and SW t21 100 500 t3-100 ns Note 14: Measured with fRS 5 MHz. Note 15: Pulse width is the period when voltage difference between 1A and 2A, 1D and 2D is over 3.0 V. Observe the specification strictly because of normal transfer efficiency. Note 16: Pulse width is the period when voltage difference between 2A and 1B/ C, 2D and 1D* is over 3.0 V. Observe the specification strictly because of normal transfer efficiency.
Rev.1.5 2019-01-08 23 © 2017 Toshiba Electronic Devices & Storage Corporation Typical Spectral Response Wavelength [nm] Relative response Spectral Response 400 0.2 0.4 1.0 450 500 550 600 650 700 0.6 0.8 Red Ta 25°C Green Blue Spectral Response Wavelength [nm] Relative response
Rev.1.5 2019-01-08 24 © 2017 Toshiba Electronic Devices & Storage Corporation Typical Drive Circuit (at f 15 MHz or lower) SW1 1D* OD SS C OS2 2A SH1 SS SH2 21 22 19 20 17 18 15 16 14 12 13 2 1 4 3 6 5 8 7 9 11 10 TCD2919BFG IC1, 2: 74AC04 3.3 V 0.1 F/25 V 10 V 47 F/25 V 0.1 F/25 V IC2 OS3 OS2 OS1 10 V 47 F/25 V 0.1 F/25 V CP SS OS3 1B RS 1A SH3 1B 2D 1D SW2 NC OS1 2A 3.3 V 0.1 F/25 V IC1 1D* 1A 2D 1D RS SW2 SH1 CP SH2 SH3 SW1
Rev.1.5 2019-01-08 25 © 2017 Toshiba Electronic Devices & Storage Corporation Typical Drive Circuit SW1 1D* OD SS C OS2 2A SH1 SS SH2 21 22 19 20 17 18 15 16 14 12 13 2 1 4 3 6 5 8 7 9 11 10 TCD2919BFG IC1, 2, 3: 74AC04 3.3 V 0.1 F/25 V 10 V 47 F/25 V 0.1 F/25 V IC3 OS3 OS2 OS1 10 V 47 F/25 V 0.1 F/25 V CP SS OS3 1B RS 1A SH3 2D 1D SW2 NC OS1 3.3 V 0.1 F/25 V IC1 1D* 1A 2D SW2 SH1 1D SH2 SH3 SW1 2A 3.3 V 0.1 F/25 V IC2 CP RS 1B
Rev.1.5 2019-01-08 26 © 2017 Toshiba Electronic Devices & Storage Corporation Cautions 1. Electrostatic Breakdown Store in shorting clip or in conductive foam to avoid electrostatic breakdown. CCD Image Sensor is protected against static electricity, but inferior puncture mode device due to static electricity is sometimes detected. In handing the device, it is necessary to execute the following static electricity preventive measures, in order to prevent the trouble rate increase of the manufacturing system due to static electricity. a. Prevent the generation of static electricity due to friction by making the work with bare hands or by putting on cotton gloves and non-charging working clothes. b. Discharge the static electricity by providing earth plate or earth wire on the floor, door or stand of the work room. c. Ground the tools such as soldering iron, radio cutting pliers of or pincer. d. Ionized air is recommended for discharge when handling CCD image sensors. It is not necessarily required to execute all precaution items for static electricity. It is all right to mitigate the precautions by confirming that the trouble rate within the prescribed range. 2. Incident Light CCD sensor is sensitive to infrared light. Note that infrared light component degrades resolution and PRNU of CCD sensor. 3. Cloudiness of Glass Inside CCD surface mount products may have a haze on the inside of glass, so be careful about following. Even if the haze arises inside of glass, when it is not on the pixel area, there is no problem in quality. Before the aluminum bag is opened, please keep the products in the environment below 30°C90 %RH. And after the aluminum bag is opened, please keep the products in the environment below 30°C60 %RH. Please mount the products within 12 months from sealed date and within 6 months from opening the aluminum bag. (Sealed date is printed on aluminum bag.) 4. Ultrasonic Cleaning Ultrasonic cleaning should not be used with such hermetically-sealed ceramic package as CCD because the bonding wires can become disconnected due to resonance during the cleaning process. 5. Mounting In the case of solder mounting, the devices should be mounted with the window glass protective tape in order to avoid dust or dirt included in reflow machine. 6. Window Glass Protective Tape The window glass protective tape is manufactured from materials in which static charges tend to build up. When removing the tape from CCD sensor after solder mounting, install an ionizer to prevent the tape from being charged with static electricity. When the tape is removed, adhesives will remain in the glass surface. Since these adhesives appear as black or white flaws on the image, please wipe the window glass surface with the cloth into which the organic solvent was infiltrated. Then please attach CCD to a product. Do not reuse the tape.
Rev.1.5 2019-01-08 27 © 2017 Toshiba Electronic Devices & Storage Corporation 7. Soldering Temperature Profile Good temperature profile for each soldering method is as follows. In addition, in case of the repair work accompanied by IC removal, since the degree of parallel may be spoiled with the left solder, please do not carry out and in case of the repair work not accompanied by IC removal, carry out with a soldering iron or , in reflow, only one time. a. Using a soldering iron Complete soldering within three seconds for lead temperatures of up to 350°C. b. Using long infrared rays reflow / hot air reflow Please do reflow at the condition that the package surface (electrode) temperature is on the solder maker's recommendation profile. And that reflow profile is within below condition 1 to 3. 1. Peak temperature: 250°C or less. 2. Time to keep high temperature: 220 to 250°C, 30 to 40 s. 3. Pre. heat: 150 to 190°C, 60 to 120 s 8. Window Glass The dust and stain on the glass window of the package degrade optical performance of CCD sensor. Keep the glass window clean by saturating a cotton swab in alcohol and lightly wiping the surface, and allow the glass to dry, by blowing with filtered dry N2. Care should be taken to avoid mechanical or thermal shock because the glass window is easily to damage. 9. Cleaning Method of the Window Glass Surface Wiping Cloth a. Use soft cloth with a fine mesh. b. The wiping cloth must not cause dust from itself. c. Use a clean wiping cloth necessarily. Cleaner When using solvents, such as alcohol, unavoidably, it is cautious of the next. a. A clean thing with quick-drying. b. After liquid dries, there needs to be no residual substance. c. A thing safe for a human body. And, please observe the use term of a solvent and use the storage container of a solvent to be clean. Be cautious of fire enough. Way of Cleaning First, the surface of window glass is wiped with the wiping cloth into which the cleaner was infiltrated. Please wipe down the surface of window glass at least 2 times or more. Next, the surface of window glass wipes with the dry wiping cloth. Please wipe down the surface of window glass at least 3 times or more. Finally, blow cleaning is performed by dry N2 filtered. If operator wipes the surface of the window glass with the above-mentioned process and dirt still remains, TOSHIBA recommends repeating the clean operation from the beginning. Be cautious of the next thing. a. Don't infiltrate the cleaner too much. b. A wiping portion is performed into the optical range and don't touch the edge of window glass. c. Be sure to wipe in a long direction and the same direction. d. A wiping cloth always uses an unused portion. Wiper
Rev.1.5 2019-01-08 28 © 2017 Toshiba Electronic Devices & Storage Corporation 10. Foot Pattern on the PCB We recommend fig.1 's foot pattern for your PCB(Printed Circuit Board). Unit: mm 1.27 P1.27 × 10 =12.7 41.4 37.6 3.1 6.5 0.67 0.67 fig. 1 11. Mask for Solder Paste Application We recommend metal mask that have the following thickness. Thickness : 0.2 mm. And we recommend that the opened area size on the metal mask is 95 % to 100 % for pads on solder. 12. Temperature Cycle After mounting, if temperature cycle stress is too much, CCD surface mount products have a possibility that a crack may arise in solder. As a method of preventing a solder crack, underfill is effective. 13. Reuse of a Tray We reuse tray in order to reduce plastic waste as we can. Please cooperate with us in reusing for ecology.
Rev.1.5 2019-01-08 29 © 2017 Toshiba Electronic Devices & Storage Corporation 14. Caution for Package Handling Over force on CCD products may cause crack and chip removing on the product. The three point bending strength of this product is the following. (Reference data) If the stress is loaded far from a fulcrum, the stress on the package will be increase. When you will treat CCD on every process, please be careful particularly. For example, soldering on PCB, cutting PCB, wiping on the glass surface, optical assemble and so on. 22CLCC Bearing length 13 mm: The force from upside: 300 [N] The force from downside: 200 [N] Bearing length 36 mm: The force from upside : 150 [N] The force from downside : 80 [N] force(N) force(N) force(N) force(N) Bending Test 13 mm 13 mm 36 mm 36 mm
Rev.1.5 2019-01-08 30 © 2017 Toshiba Electronic Devices & Storage Corporation Application Note (Reference Only): Timing Chart (Color 300 dpi Mode: Bit Clamp Mode) D92+D93 +D94+D95 S1+S2 +S3+S4 D72+D73 +D74+D75 D68+D69 +D70+D71 D20+D21 +D22+D23 D76+D77 +D78+D79 D80+D81 +D82+D83 D0+D1 +D2+D3 D24+D25 +D26+D27 S10677+S10678 +S10679+S10680 D88+D89 +D90+D91 2A RS CP OS1, 2, 3 1 line readout period (2694 elements) Dummy outputs (6 elements) Light shielded outputs (12 elements) (1 element) Dummy output (1 element) Test output (1 element) Dummy outputs (2 elements) Dummy outputs (19 elements) Effective outputs (2670 elements) (1 element) Dummy outputs (5 elements) SH1 tINT (integration time) 1A 1B, C SW1 (“L”) SH2, 3 (“H”)
Rev.1.5 2019-01-08 31 © 2017 Toshiba Electronic Devices & Storage Corporation Application Note (Reference Only): Timing Chart (Color 300 dpi Mode: Line Clamp Mode) D92+D93 +D94+D95 S1+S2 +S3+S4 D72+D73 +D74+D75 D68+D69 +D70+D71 D20+D21 +D22+D23 D76+D77 +D78+D79 D80+D81 +D82+D83 D0+D1 +D2+D3 D24+D25 +D26+D27 S10677+S10678 +S10679+S10680 D88+D89 +D90+D91 2A RS CP OS1, 2, 3 SH1 tINT (integration time) 1A 1B, C SW1 (“L”) SH2, 3 (“H”) 1 line readout period (2694 elements) Dummy outputs (6 elements) Light shielded outputs (12 elements) (1 element) Dummy output (1 element) Test output (1 element) Dummy outputs (2 elements) Dummy outputs (19 elements) Effective outputs (2670 elements) (1 element) Dummy outputs (5 elements)
Rev.1.5 2019-01-08 32 © 2017 Toshiba Electronic Devices & Storage Corporation Timing Example (300 dpi Mode/f 20 MHz/fdata 10 MHz) Conventional timing Wide sampling period timing f 20 MHz 25 ns 25 ns 25 ns 25 ns fdata 10 MHz f 20 MHz 25 ns 25 ns 25 ns 25 ns fdata 10 MHz 6 ns (min) 6 ns (min) S1S2 S3S4 S5S6 S7S8 S1S2 S3S4 S5S6 S7S8 1A 2A 1B RS CP OS 1A 2A 1B RS CP OS
Rev.1.5 2019-01-08 33 © 2017 Toshiba Electronic Devices & Storage Corporation Package Dimensions A: 8.35±0.15 WQFN22-C-R240-1.27
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