TCD2300C TOSHIBA | Alldatasheet
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TOSHIBA CCD LINEAR IMAGE SENSOR CCD(Charge Coupled Device) The TCD2300C which includes sample-and-hold circuit and clamp circuit is a high sensitive and low dark current 3648 elements x3 lines CCD color image sensor. The sensor is designed for color scanner. Nw The device contains a row of 3648 elements x3 lines ee —_ ms) photodiodes which provide a 16 lines/mm across a A4 —< —_“ <ecogiit size paper. The device is operated by 5V pulse, and 12V Qs it nh . power supply. FEATURES WDIP22-C-400-2.54A @ Number of Image Sensing Elements : 3648 elements x3 lines Weight : 4.89 (Typ.) @ Image Sensing Element Size : 8um by 84m on 8m centers @ Photo Sensing Region : High sensitive pn photodiode @ Distance Between Photodiode Array : 96m (12 Lines) @ Clock : 2 phase (5V) @ Internal Circuit : Sample & Hold circuit, Clamp circuit @ Package : 22 pin DIP © Color Filter : Red, Green, Blue PIN CONNECTIONS os2 NC 033 ost MAXIMUM RATINGS (Note 1) sf] Dos vo Fe es -03~8 | v ss F ool we opersing Temperature | Tons [060 feel Fata] es (Note 1) All voltage are with respect to SS terminals (Ground). (TOP VIEW) 2610016802 @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges 35 tet dort inthe moet raced prods: spaicaions. als, please Keep in mind the precautions and condtions sat ford Inthe 1997-06-30 1/14
os $18 ge $2 | CCD ANALOG SHIFT REGISTER 2 Dos s/4 [came als PHOTO. SIS1S ols *o< ¥ ls fee ob S82 222 8 (8) * CCD ANALOG SHIFT REGISTER 1 TT CCD ANALOG SHIFT REGISTER 4 [5] [caw] ols olen PHOTO e/5/2 ols i a Bl fee 35 BBB (} “rl? CCD ANALOG SHIFT REGISTER 3 a | CCD ANALOG SHIFT REGISTER 6 ols len PHOTO SIS/2 ols 033 @)—<] 1 Bet fee ~ ee BBB “pe @ oa hal CCD ANALOG SHIFT REGISTER 5 >——“ ® © o) ® @ ss O® RS $28 $10 $20 38 PIN NAMES Cok T Phase D TR Gates Clock 2 (Phase 2) [8s [eset cate Clock 1 (Phase 1) [___SP___| Sample and Hold Gate Clock 7 (Phase 2) clamp Gate Final Stage Clock (Phase 1) Signal Output 1 Final Stage Clock (Phase 2) [| _0s2__| Signal Output 2 [5 —eround Signal Output 3 [00 | Power | p05 compensation Output Shift Gate 7 Non Connection Shift Gate 2 a 9610016842" @ ‘he products described in this document are subject to foreign exchange and foreign trade control laws © The information contained herein presented only ab a guide for the applications of our products. No responsibilty is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others @ The information contained herein is subject to change without notice 1997-06-30 2/14
OPTICAL/ ELECTRICAL CHARACTERISTICS (Ta=25°C, Vop =12V, Vg = VRg=VsH = Vep=5V (Pulse), ff =0.5MHz, fxg = 1.0MHz, Load Resistance = 100kQ, ty (Integration Time) = 10ms, Light Source =A Light Source +CM500 Filter (t=1.0mm) ) CHARACTERISTIC SYMBOL | min. | ve. | max. | UNIT NOTE Sensttvity Red) [ak ot | [ores | ote Sensitivity (Green) [ore Pt | vies | (Note 2) Sensitivity Blue) [ra — | 05 | — | viies | (note 2) orm PRNU) | — | 10 | 20 | % | (Note 3) Photo Response Non Unvformiy pani) [= [3 [12 | mv woe a | [Register Imbalance ———SC~S RT SCPC | | 8 P| note 8) | Saturation Output Voltage [ Vsar [1.0 | 15 [ — | VT (ote 6) [Saturation Exposure ———~—S~S~CSSESSSS*Y C+ 07 | — | Ts | (Note 2) Dark Signal Voltage VDRK | — [| = [ 20] mv | (ote 8) Dark Signal Non uniformity [psnu [50 [mv ote 9 | Total Transfer Efficiency D7 [s2,—-|-|* |] | Output Impedance a DC Power Dissipation [Pp — | 500 | — [mw DC Offset Voltage [Vos | — | 60 | — |v _| Wote 70) DC Compensation Output Voltage Vpos [| — | 60 | — | v__| (Note 10) Wos-Voos]| | — | 100 [300 [mv | (Note 10) (Note 2) Sensitivity is defined for each color of signal outputs average when the photosensitive surface is applied with the light of uniform illumination and uniform color temperature. (Note 3) PRNU (1) is defined for each color on a single chip by the expressions below when the photosensitive surface is applied with the light of uniform illumination and uniform color temperature. Where 7 is average of total signal outputs and Ax is the maximum deviation from ca The amount of the incident light is shown below. Red = — SE Green =—1 se Bl = ——SE jue z 1997-06-30 3/14
(Note 4) PRNU (3) is defined as maximum voltage with next pixel, where measured 5% of SE (TYP.). (Note 5) RI is defined for each color on a single chip by the expressions below when the photosensitive surface is applied with the light of uniform illumination and uniform color temperature. 3647 = |en-xn +1] 3647 x Where xn and xn +1 are signal outputs of each pixel. % is average of total signal outputs. (Note 6) Vsat is defined as minimum Saturation Output Voltage of all effective pixels. (Note 7) Definition of SE: SE= Sar (Note 8) Vprk is defined as average dark signal voltage of all effective pixels. (Note 9) DSNU is defined as different voltage between VprK and VipK, when VupK is maximum dark voltage. os y York DsNU (Note 10) DC Signal Output Voltage and DC Compensation Output Voltage are defined as follows: os Dos Vos Voos ss ss 1997-06-30 4/14
CHARACTERISTIC SYMBOL } min | ote [max | UNIT NOTE Clock Pulse Voltage V¥0, E J 45 [| 50 | 55 |, | oo [ o2 [| o5 | Final Stage Clock Pulse ee me V6B v Voltage | oo [| o2 | 05 | Shift Pulse Voltage ar eve VsH £ £ $ v_ | (Note 11) | oo [oz [| os | [as [50 | 55 _| ves [oo [02 [os _| | | Sample and Hold Pulse vee - “#5 [50 755 Ty | Note 12) Voltage | oo [oz | os | [4s [50 | 5 Note 13) Clamp Pubs Voltage Ye [00 [02 [os | Y |r Power Supply Voltage [Vop [14 [20 | 30 fv (Note 11) Vg0, E”H” means the high level voltage of Vg0 and VgE when SH pulse is high level. (Note 12) Supply “UY level to SP terminal when sample-and-hold circuit is not used. (Note 13) Supply SH (inversed pulse of SH) to CP terminal when clamp circuit is not used. CLOCK CHARACTERISTICS (Ta = 25°C) CHARACTERISTIC SYMBOL | min. | tye. | max. | UNIT [Clock Pulse Frequency | 05 | 20 | Me | Reset Pulse Frequency | fas | — | 10 [ 40 | Mie | Sample and Hold Pulse Frequency Lisp | — [10 _[40_| ma _| Clamp Pulse Frequency | fee | — | 10 | 40 | MHz | [Clock Capacitance SCS GE | | S| CY Final Stage Clock Capacitance ce | — | wo | — | pF Shift Gate Capacitance [| csu | — | 200 | — | oF | Reset Gate Capacitance [crs | — | 10 | — [ pF Sample and Hold Gate Capacitance Loe | — | 0 | — | pF _| [clamp Gate capacitance ——SSSSSSCSC~d er | | 10 |r 1997-06-30 5/14
a) Sc Be a7 sea \\S veg, N £ eG, —t>F ve etez SEs] 2G a3 4/22 190 — se soa 89 e el soo g 4 90 a Fd g 89ES a ge 2 998s pS © £8) = of of SE = 3a/ § 3] 3] SI a) Ss 2 2 2 es Ze] 8 cl el & os 2 63] 2 3) 8] Phas z_7o & é| ¢é 3 £90, & 5 S$) &] 8 Seo oRSS FI 3 ey gy] @ 2 gz] €] 2 ones — Ed z z z 09g, 08 Z -) FF] # 6S0, fea) | 2 See] B) - sia eae] & via a8) 4 £10 gp) om za z iia 2 Eo] & o1a a 6a, ze 3 33 3 va =a to ge] 3 za ° ta, 0a, E & 2 ¢ ¢ 8 8 5 Ea Ea & a ui 2 fey ” 8 2 o 3 a le 1 q Is aE Z £ & 3 58 5 ° Sz E Po 1997-06-30 6/14
_—| 3.5V (MAX.) a if ie oh 7 . L 0, | Thad ° = = | iar 1997-06-30 7/14
TIMING REQUIREMENTS (Cont'd) CHARACTERISTIC SYMBOL | min. | (None 4) UNIT Pulse Timing of SH and 40, € 0 SH Pulse Rise Time, Fall Time [aw [oe [so | — [ns] SH Pulse Width [3 | 500 | 1000 | — | ns | #1, #2 Pulse Rise Time, Fall Time [ew | of so | — | ns _| RS Pulse Rise Time, Fall Time Pwo | o | 2 | — | ns | RS Pulse Width [ae [40 [80s | Pulse Timing of #18, 428 and RS [| 720 [300 [rs _| SP Pulse Rise Time, Fall Time [uate | o | 2 | — | ns _| 5F Pulse Width [3 [70 [400 fs] Pulse Timing of SP and RS [as | of so | — | s_| Video Data Delay Time (Note 15) [ tie t17 | — [ 70 | — | ons | CP Pulse Rise Time, Fall Time 18, t20 [| o | 2 | — | ns | CF Pulse Width [ta | too | 200 | — | ns _| Pulse Timing of 418, 628 and CP [wr [2 | 50 | — | ns _| Pulse Timing of RS and CP 2 (Note 14) TYP. is the case of frg=1.0MHz (Note 15) Load Resistance is 100kQ 1997-06-30 8/14
0.8} 7 LOA aga Sn re 0.2 AN LATIN LANA WAVE LENGTH A (nm) 9997-06-30 9/14
| 0.1 pF /25V #18 Top +12v “dq ° o<] od glel¢ 0.1p /25V o<] ey eye 10 nF /25V o<| 1500 " L--7 2-4 a er] Dos O me AR EPPA NC OS1 DOS OD SS 418 “CP 42E SH1 g1E NC 082 053 Ss “SP RS 428 $5 420 SH3 $10 SH2 JILL Be 1502 ff sv 0s2 © 0.4 pF 125V | 1500 an Te Co cr 083 © sia! ' com o<] I 5 =! oc] —_ ler-2: Tevaacoae F toc} i—o TRI~4 =: 2SC1815-¥ a)” 1997-06-30 10/14
- Window Glass The dust and stain on the glass window of the package degrade optical performance of CCD sensor. Keep the glass window clean by saturating a cotton swab in alcohol and lightly wiping the surface, and allow the glass to dry, by blowing with filtered dry N2. Care should be taken to avoid mechanical or thermal shock because the glass window is easily to damage. 2. Electrostatic Breakdown Store in shorting clip or in conductive foam to avoid electrostatic breakdown. 3. Incident Light CCD sensor is sensitive to infrared light. Note that infrared light component degrades resolution and PRNU of CCD sensor. 4. Lead Frame Forming Since this package is not shoutagainst mechanical stress, you should not reform the lead frame. We recommend to use a IC-inserter when you assemble to PCB. 1997-06-30 11/14
<Application note> EVEN-ODD UNBALANCE When High-speed draiving standard level of odd-even bits is often unbalanced. For that reason when high-speed draiving CCD you should put a damping resistance in input ¢ pin. 1. WAVEFORM (Sample and Hold ON) fDATA = 2MHz fDATA = 4MHz x4 ft een ponte | | avh | dm! bel | | { | = een oie i» ' aren ae | i! ET Ty ye 2 ete) efits be hemn i | jt . i Pai a Lune lhl Sans Dial MaAae SAA Oe oo fers teres Y reseeees ith ; Foy of WA \\ \\ , os fie a te ed ming hm _ Park, — Swipe aia ave Wai fi | 4 ignal en ed ee Loy (S/H) \\ | i | ficpeeies tact woes Aidan ine Nn sft raitnaaivnnh atten Hone st eee a | gomy 5 £5) todns | | Without A Damping Resistance Without A Damping Resistance rs giE | 1 ' if 1 1 RS mee Jeeps ~ [eid [Fommmmnteen ponte, \\ yy ' - oa uamatis iamababana Sivan bnanadainancirin i i 1 th 4 | f Sere evs Cre Ba. \\sieni Wwnenl Ww \\w atk, wean Ati ME Nl Wm (S/H) an { A i fi ot ; Mw say! wae! \\wviietny! \\w " oes noe re em Jong] 3% 5, 3 | toons | ¢ | | | 2. MEASUREMENT CONDITION Ta=25°C, Vap=Vpp = 12V, Vg1E=Vg10=Vg1B =V42E =V 420 = Vg2B = VRS = VCP = VSP = VSH1 = VSH2 = VSH3 = SV (Pulse), Light Source = Daylight Fluorescent Lamp. Ocilloscope Tektoronix 2465A (400MHz) Probe P6136 10.8pF 1997-06-30 12/14
- DRIVE CIRCUIT (with a damping resistance) Please put a damping resistance in input 41E (15). TCD2300C Bee [2] Gl ca sp O [>e —E] RS O [>e. BS [5 | © FRO Pe “tl — <] oe a o<] oo FO ho $20 a] $2 o<] ov wo ho SH3 o he] SHI o<] oT Foo bo sOrF st gle 150 o<] oF 9997-06-30 13/14
WDIP22-C-400-2.54A (C) Unit : mm (ee | a wo ») 8 ——— re 39) g cH — 3| = * 1 1 a 48.6205 = | 5 © : ‘ae aalaiaaigialal alk 5 3 o 11.6TYP. 0.51+0.15 IO 1.02+0.1 (Note 1) No.1 SENSOR ELEMENT (S1) TO EDGE OF PACKAGE. (Note 2) TOP OF CHIP TO BOTTOM OF PACKAGE. (Note 3) GLASS THICKNES (n=1.5) Weight : 4.8g (Typ.) 1997-06-30 14/14