TC8570A

TC8570AP TOSHIBA | Alldatasheet

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' ~ _ — TOSHIBA (UC/UP) BYE D MM 9097249 0026324 49T METOS3 COMMUNICATION CONTROLLER Il Universal Asynchronous R/T 1. GENERAL DESCRIPTION In micro-peripherals, i8251 is one of the serial communication LSI which have a function of the UART, To accomplish the communication with telephone line, other circuits are needed. These are baud- generator which generator which generates clock signal for communication rate called baud-rate, and additional circuits which controls MODEM. To UART TC8570AP/AF is one of communication LSI constructed with including these peripheral circuits, Internal Block Diagram is shown in FIG.3.1, 2. FEATURES CO 8bit CPU bus compatible O Full double buffering (3 Four independent interrupt priority control functions O Programmable Baud Generator to divide any input clock by 1 to (216-1) and to generate the internal 16 X clock CI Independent receiver clock input O MODEM control function (CTS, RTS, DSR, DTR, CI, and DCD) O 5 to8bit character length

1 Even, odd, or non-parity bit generation and detection

O 1,1.5, or 2 stop bit generation O False start bit detection O Break character transmission and detection G Error detection (break, parity, overrun, and framing error) © Complete status reporting capabilities O Internal diagnostic capabilities (loopback for communication link, interrupt and receiver error simulation) O Allinputs are TT] compatible (except -MSEL input) G Silicon-Gate CMOS construction CO Single +5V power supply © 40 pin DIP or 44 pin mini FP TC8570AP/AF-1 060489 351

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TOSHIBA (UC/UP) BYE D m@ 9097249 OO2b325 Il COMMUNICATION CONTROLLER 3. SYSTEM CONFIGURATION of the UART

3.1 BLOCK DIAGRAM of the UART

DB7-0 S0-2 A0-2 -ALE WR -WR RD -RD -MSEL -RDOUTCSOUT XIN XOUT ee ee READAWRITE CONTROL <_ DIVIDER LATCH (DLL,DLM) BAUD-RATE GENERATOR -BAUDOUT [TRANSMITTER DATA BUFFER TDA) TRANSMITTER SHIFT TRANSMITTER DATA BUFFER (TDB) REGISTER(TSR) sour TRANSMITTER CONTROL <>| LINE CONTROL REGISTER (LCR) RANSM co °' LINE STATUS REGISTER (LSR) Lt RECEIVER CONTROL | RCLK RECEIVER SHIFT SIN LZ REGISTER(RSR) ——— — INTERRUPT IDENT. REGISTER (IIR) ] j—<>| MODEM CONTROL REGISTER (MCR) i‘ cl -DCD <> [_MODEM STATUS REGISTER (MSR)_| Ef -2se -cTS <>[_SCRATCHPAD REGISTER (SCR) MODEM INTERFACE Hour ry -OUT2 ch RTS INTERNAL DATA BUS -DTR FIG.3.1 INTERNAL BLOCK DIAGRAM TC8570AP/AF-2 060489 | 352

TOSHIBA (UC/UP) BYE D MM 9097249 0026326 7b2 METOS3 COMMUNICATION CONTROLLER |]

3.2 EXAMPLE of SYSTEM CONFIGURATION

‘TC8570AP/AF converts data character from the peripheral or the MODEM, serial to parallel, as well as converts data character from CPU, parallel to serial. These are basic function of the UART, such as adjusting data format match with communication protocols and evaluating data format of received matched or not with protocols. As is shown in FIG.8.2 system configuration, the additional circuit in the UART gains maximum performance with used between CPU and MODEM equipment. CPU can read the status of UART any time even if its operation working. ‘The status information is such for , the type and status of the transmitting operation that is just executing, and farther more information i.e. parity, overrun, framing error, interrupt of the break. The complete MODEM control and processor interrupt function will be minimized occupancy of CPU for controlling communication line. cpu TC8570AP/AF, ADDRESS BUS XIN > enb Vy Gi crystat LATCH A0~2 XOUT > exp [DECODER ] ~CS2 “BA DECODER cst vee [] +5v -12v +12v Co lcso -DTR > JOR -RD -RTS es fe out! Fa Ow -WR -OUT2 | BH || LINE DRIVER ||: “ALE “cl me = RD -DCD k- RECEIVER GND: WR -DSR RS-232C -cTs CONNECTOR DATA BUS |<» p87~0 (To MODEM) souT -RDOUT |_| csOUT SIN INTR INTRPT RESET RESET FIG.3.2 SYSTEM CONFIGURATION TC8570AP/AF-3 060489 353

TOSHIBA (UC/UP) BYE D M@ 9097249 0026327 bT9 MMTOS3 il COMMUNICATION CONTROLLER 4. PIN DESCRIPTION

4.1 PINCONFIGURATION

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_ oO ns a -- —=—n- TOSHIBA (UC/UP) BYE D MM@ 9097249 0026328 535 METOS3 COMMUNICATION CONTROLLER |]

4.2 PINFUNCTION

note) The number in parentheses shows pin number of the Flat package 8 a a 2@n| oar fio | 4 (43)| DB3___| 10 | These terminals are 8 bit bidirectional bus to communicate between [sa | psa [10 | meUarTand he cr. 7a | pss [10 | | 8@ | oer fio | RCLK This terminal is input of the 16X baud rate clock for the receiver section of the UART. == 106) | sin This terminal is serial data input from the communication link =o: (peripheral device, MODEM, or Data Set). == This terminal is the composite serial data output for the == communication link (peripheral device, MODEM, or Data Set). SOUTis | — =—= 117) | souT set to the marking (logic 1) state upon a RESET operation. If the co- | = == operation mode (-MSEL=0) is selected, SOUT is set to the marking when -ALE is “L". Jz@ [co [| This signal indicates that the chip is selected. it can not be done data 13) | cst | 1 [communication between the UART andthe CPU antl cSOUT ose pet co] ce [| This terminal supplies the 16 X clock signal of baud rate clock to the transfer section of the UART. The clock rate is equal to the oscillator 15 (11)| -BAUDOUT frequency divided by the value in the Baud Generator Divider Latches. -BAUDOUT may be used to the standard frequency of receiver section by tying this terminal to RCLK. 16 (12)|_xiN_____|_1_ | This terminal connects to crystal resonator or external clock signal. 17.03)| xcur [© [ris outeet is inverted signal of XIN and connected to crystal [sca we | When WR is “High” or -WR is “Low” while the chip is selected, it permits the CPU to write data or control words into the selected 1915) wR __| 1 registerof the UART. 20(16)| GND _| & [Ground terminal of IC. Connect to system ground. 21 (18) [2 ‘| 1 | When RD is “High” or -RD is “Low” while the chip is selected, it permits the CPU to read data or status information from the selected Lez] ro | 1 [registerofthe UaRT. TC8570AP/AF-5 060489 355

TOSHIBA (UC/UP) BYE D MM 9097249 0026329 471 METOS3 Il COMMUNICATION CONTROLLER note) The number in parentheses shows pin number of the Flat package | no. | PIN NAME [10 | FUNCTION Whenever the CPU is reading data from the UART, this signal is "Low". 23 (20) | -RDOUT This signal can use the enable signal to connect the transceiver to the external data bus. This signal indicates that the chip is selected. It cannot be done data 24 (21) | CSOUT communication between the UART and the CPU until CSOUT signal is "High". This input is used to latch the address (AQ, A1, A2) and chip select (CSO, 51, -CS2) signals with the edge from “Low” to “High”. When the address and chip select signals are stable for the duration of a read or 25 (22) | -ALE a write operation, -ALE ties permanently “Low”. If these are not stable, it is necessary to be active “Low”. When the co-operation mode (-MSEL = 0) is selected, this terminal is not the latch signal but the output enable signals of DB7-0 and SOUT. weal a a7 apa || These inputs are used to select the register of the UART for the duration of a read or a write operation. ae@[ ao | | When this terminal is “High” or open, the UART is normal operation. If it terminal ties permanently “Low” and RESET is “High”, it changes _MSEL the co-operation mode. At this time, -ALE loses a part of latch signals for address (AO, A1, A2) and chip select (CSO, C51, -CS2). Also, SOUT is “High” during -ALE is “Low” and the data bus becomes high- impedance state. The other outputs are not influenced. This terminal is set to “High” whenever any one of the following interrupt types has an active “High” condition and is enabled via the Interrupt Enable register : Receiver Error, Received Data Ready, 30 (27) | INTRPT Transmitter Data Buffer Empty, and MODEM Status. INTRPT signal is reset to “Low” upon the appropriate interrupt service or a RESET operation. This terminal is an output released for user. It can set to an active 31 (29) | -ouT2 “Low” by programming -OUT2 of the MODEM Control Register to "High" upon a RESET operation. -OUT2 signal is forced to its inactive "High" during loop mode operation. ‘When this terminal is “Low”, it informs the MODEM or Data Set that 32 (30) | -RTS ‘the UART is ready to transmit data. -RTS signal is set to “High” upon a RESET operation. -RTS signal is forced to its inactive “High" during loop mode operation. When this terminal is “Low”, it informs the MODEM or Data Set that -DTR the UART is ready to communicate. -DTR signal is set to “High” upon a RESET operation. -DTR signal is forced to its inactive “High” during loop mode operation. TC8570AP/AF-6 | 060489 | 356

a TOSHIBA (UC/UP) BYE D MM@ 9097249 0026330 193 METOS3 COMMUNICATION CONTROLLER ||] note) The number in parentheses shows pin number of the Flat package [ no. | PINNAME [10 | FUNCTION This terminal is an output released for user. It can set to an active 3a (32)| -ouT1 “Low" by programming -OUT1 of the MODEM Control Register to “High”. -OUT1 signal is set to “High” upon a RESET operation. -OUT1 signal is forced to its inactive “High” during loop mode operation. When this input is “High”, all registers (except of the Receiver Data, 35 (33) | RESET Transmitter Data Buffer, and Baud Generator) and control logic are cleared, Also, output signal of MODEM are cleared. (TABLE 5.1.9) -CTS signal is a MODEM control function input. The CPU can know its condition by reading CTS of the MODEM Status Register. DCTS of the “cts MODEM Status Register indicates whether -CTS input has changed since the previous reading of the MODEM Status Register. note) If MODEM Status Interrupt is enabled, whenever CTS of the MODEM Status Register, an interrupt is generated. When this input is “Low”, it indicates that the MODEM or Data Set is ready to establish the communication link and transfer data with the 37 (35) UART. -DSR signal is a MODEM control function input. The CPU can know its condition by reading DSR of the MODEM Status Register. DDSR of the MODEM Status Register indicates whether -DSR input has changed since the previous reading of the MODEM Status Register. When this input is “Low”, it indicates that the data carrier has been detected by the MODEM or Data Set. -DCD signal is MODEM control 38 (36) | -pcb function input. The CPU can knowits condition by reading DCD of the MODEM Status Register. DDCD of the MODEM Status Register indicates whether -DCD input has changed since the previous reading of the MODEM Status Register. When this input is “Low”, it indicates that the ringing signal has been received by the MODEM or Data Set. -Cl signal is a MODEM control 39 (37) | -cl function input. The CPU can know its condition by reading Cl of the MODEM Status Register. TECI of the MODEM Status Register indicates whether -Cl input condition has changed from “Low” to"High” since the previous reading of the MODEM Status Register. TC8570AP/AF-7 060489 357

TOSHIBA (UC/UP) BYE D ml 9097249 0026331 O2T MTOSS 5. FUNCTIONAL DESCRIPTION 5.1. INTERNAL REGISTERS The UART includes ten registers. The user can access and control any of the UART register via the CPU. These register are used to control the operations of the UART and to transmit and receive data, (TABLE 5.1) TABLE 5.1 INTERNAL REGISTERS REGISTER/ DATA BIT ADDRESS SYMBOL [aovaby | Rcer otter om [sow | nor | wos | wos | now | os | oz | wor | 00 | TronsmitterData Buffer 1 inerryptenabienegiter en |x | x [x [x | esi | esi [eroser| enon | [2 [rneruptien epiter —om Jak [x |» [x |» |» | aor | woo | ne | [3 [uneconveteginer uc | ouas [sane | sven | ers | ven | sve [st | was | |_4 [move conotnesiner er | x | x [x [toor [oure | ours | is | ome | |_s [uinestausneniser ise |x| temp | rose | ao | re | re | of | ron | |_s _[ooewstawusregiser __|sa_ | oco | cr | ose | sre | ooco | rect | ose Jooras=1)[oiderieen as) fou | ov _| os | os | os | os | oe | or | 0 | [rows [oder oo Jou [os [ow [wr [oon | ow | o | ow | x =: Always “0” *note The RDB and IIR are read-only registers. The TDB is write-only register. Any other registers are possible to read and write, but writing to the Status Registers (LSR, MSR) during the communication are not recommended as these operations are used for diagnostic testing by the interrupt and the simulation of the receiver error. TC8570AP/AF-8 060489 358

TOSHIBA (UC/UP) 6YE D MM 9097249 0026332 Tbh METOS3 COMMUNICATION CONTROLLER ll

5.1.1 LINE CONTROL REGISTER (LCR)

‘The user can specify the format of the asynchronous data communications exchange via the Line Control Register. In addition to specify the format, the user can refer the contents of the Line Control Register for inspection of communication link, this construction can be simple the system program, and eliminate the need for separate storage in system memory of the line characteristics. [a2 [ar [a0 | 0a7 [pes [pas | pea [oes | paz | oer | oxo | Lo [a | a [oie [ sork [sree [ees [ren [sre] wiss_| wiso WLSO,WLS1 (Word Length Select Bit 0-1) ‘These 2 bits specify the number of bits in each transmitted or received serial character, WLS1 WLSO ‘WORD LENGTH po | oo | Sar re ee ee ee STB (Number of Stop Bit) This bit specifies the number of stop bit in each transmitted or received serial character. If STB is "Low, one stop bit is generated in the transmission data. If STB is "High”, 1.5 stop bits are generated when a 5-bit word length is selected. If STB is "High”, 2 stop bits are generated when either a 6, 7, or 8-bit word length is selected. The receiver checks the first stop bit only, regardless of the number of stop bits selected. wiso NUMBER OF STOP BIT a x : NORELATION PEN (Parity Enable) This bit is the Parity Enable bit. When PEN is “High”, a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and stop bit of the serial data. TC8570AP/AF-9 060489 359

TOSHIBA (UC/UP) BYE D MM@ 9097249 0026333 4T2 METOS3 ] l COMMUNICATION CONTROLLER EPS (Even Parity Select) ‘This bit is the Even Parity Select bit, When PEN is "High” and EPS is "Low”, an odd number of logic 1’s is transmitted or checked in the data word bits and parity bit. When PEN is "High” and EPS is "High”, an even of logic 1’s is transmitted or checked. [0 | owaPariy | eee STCP (Stick Parity) "This bit is the Stick Parity bit, When PEN is "High” and STCP is "High”, the parity bit (if EPS is High”) is logic 1, or (if EPS is "Low”) is logic 0. [ew [sree [msi | eaanvar | + | a poo SBRK (Set Break) ‘This bit is the Break Control bit. When SBRK is "High”, the Serial Output (SOUT) is forced to the Spacing (logic 0) state. The break is disabled by setting SBRK to "Low”. The Break Control bit (SBRK) influences only on SOUT and has no effect on the transmitter logic. DLAB (Divider Latch Access Bit) ‘This bit is the Divider Latch Access Bit, It must be set to a logic 1 to access the Divider Latches of the Baud Generator during a read or a write operation, It must be set to a logic 0 to access the Receiver Data Buffer, the Transmitter Data Buffer, or the Interrupt Enable Register. | TC8570AP/AF-10 060489 360

TOSHIBA (UC/UP) BYE D M@ 9097249 0026334 639 METOS3 COMMUNICATION CONTROLLER Il

5.1.2 PROGRAMMABLE BAUD GENERATOR

‘The UART contents the programmable Baud Generator. The programmable Baud Generator divides input clock by the value that is set by the two 8-bit Divider Latches (DDL, DDM), The divided frequency is the output signal of -BAUDOUT as 16 X clock of baud rate. The baud rate of transfer data is the frequency of 1/16 output [az [ar [ao | er [pss | oss | psa | pss | ps2 | vei | 80 | po [ofa] es | sm | os | sr | om | so | oo | ss | Lo fofofe [x | x | | a | a | a | eo | (DLAB = 1) The frequency of the output signal (baud rate X 16) of -BAUDOUT is follows : BAUD16X =B15 x 2154+ B14.x 214 4+B13 x 213.4B12 x 2124+ B11 X 211 ferret sereeseesseesnee + BAX 24-4 B3 X 23 +B2 X 22+B1X214+BO ‘These 16-bit Divider Latches must be set up during initialization in order to ensure the normally occurrence of the baud rate. Upon writing either upper or lower of the Divider Latches, the divided value is immediately loaded into the baud counter. And then, baud counter begins to count. TC8570AP/AF-11 060489 361

=e Se TOSHIBA (UC/UP) BYE D mM 9097249 0026335 775 mmETOS3

5.1.3 LINE STATUS REGISTER (LSR)

‘This 8-bit register provides the status information to CPU about the data transfer. [a [ar [ao [oo [on | oes [bos [oes | oo | on | ooo | Leo [= Trew [rose [oo [re [re | oe [ne RDR (Received Data Ready) This bit indicates the Received Data Ready. RDR s set to a logic 1 whenever a complete incoming character has been received and transmitted into the Receiver Data Buffer. RDR is reset to a logic 0 by reading the data in the Receiver Data Buffer. OE (Overrun Error) ‘This bit indicates the Overrun Error. If next characters are received into Receiver Data Buffer before the contents of Receiver Data Buffer has been read by the CPU, OE is set to a logic 1. Its reset to a logic 0 whenever the CPU reads the contents of the Line Status Register. PE (Parity Error) ‘This bit indicates the Parity Error. It means that when the Parity Enable bit (PEN) of the line Control Register is set, the received data did not have the correct even or odd parity as selected by the Even Parity Select bit (EPS) of the Line Status Register. PE is set to a logic 1 upon detection of a parity error and is reset to a logic 0 whenever the CPU reads the contents of the Line Status Register. FE (Framing Error) ‘This bit indicates the Framing Error. It means that the received data did not have a valid stop bit, FE s set to a logic 1 whenever the stop bit of the received data is detected as a zero (Spacing level). Itis reset to a logic 0 whenever the CPU reads the contents of the Line Status Register. BD (Break Detect) This bit indicates the Break Detect. BD s set to a logic 1 whenever the received data input is held in the Spacing (logic 0) state for a full transmission time (that is, the total of start bit + data bits + parity bit + stop bit), It is reset to a logic 0 whenever the CPU reads the contents of the Line Status Register. *note: OE, PE, FE, and BD are the error conditions that produce the Receiver Status Interrupt whenever any of the corresponding conditions are detected, TC8570AP/AF-12 060489 362

“ae TOSHIBA (UC/UP) BYE D MM 9097249 O02b33b 601 METOS3 ‘TDBE (Transmitter Data Buffer Empty ) This bit indicates the Transmitter Data Buffer Empty. It means that the UART is ready to accept anew character to transfer. When the character is transmitted from the Transmitter Data Buffer to the Transmitter Shift Register, TDBE is set to a logic 1 and the UART occurs the Transmitter Data Buffer by the CPU. TEMP (Transmitter Empty) This bit indicates the Transmitter Empty. TEMP is set to a logic 1 whenever the Transmitter Data Buffer and Transmitter Shift Register are both empty. Itis reset to a logic 0 whenever either the Transmitter Data buffer or Transmitter Shift Register receives a data character. Bit7 ‘This bit is always set to logic 0. TC8570AP/AF-13 060489 363

TOSHIBA (UC/UP) BYE D MM 9097249 0026337 548 MBTOS3 ll COMMUNICATION CONTROLLER

5.1.4 INTERRUPT IDENTIFICATION REGISTER (IIR)

‘The UART has an interrupt function which allows for complete flexibility in interfacing to all popular microprocessors presently available, The UART prioritizes interrupts into four level to realize minimum expense of software during the data transfer, The prioritizing of interrupt are follows Priority 1; Receiver Line Status Priority2 : Received Data Ready Priority8 : ‘Transmitter Data Buffer Empty Priority4 : MODEM Status This information indicates a prioritized interrupts pending. The type of interrupt are stored in the Interrupt Identification Register, The Interrupt Identification Register addressed during chip select time, freezes the highest priority interrupt pending and no other interrupts are acknowledged until the particular interruptis serviced by the CPU. (TABLE 5.1.4) [a [x [mo] oer | one | oes [vee [om [om | on | om | fof: te f= P= f= P= f= Por Poo fine] INTE (Interrupt Flag) ‘This bit can be used in either a hardware prioritization or polled environment to indicate whether an interrupt is occurred or not, When this bit set to a logic 0, an interrupt is occurred and the contents of the Interrupt Identification Register may be used as a pointer to the appropriate interrupt service routine, When INT is set to a logic 1, no interrupt is pending and polling (if used) continues. IDO , 114 (Interrupt iD Bit 0, Bit 1) ‘These two bits indicate the kind of the interrupts occurred with the priority. Bit3-7 ‘These five bits are always set to a logic 0. TC8570AP/AF-14 060489 364

TOSHIBA (UC/UP) b4E D MM 9097249 0026338 444 METOS3 TABLE 5.1.4 INTERRUPT CONTROL FUNCTIONS. [ur __[ priory INTERRUPT RESET INTERRUPT TYPE | INTERRUPT SOURCE [wor [oo | wr | vever CONTROL Overrun Error veri Parity Error ; Receiver Line Status Reading the LSR Framing Error Break Interrupt [+ [oe [0 [2 [received ataneady [receiveroateAvetaie [Reeding thenos | 1 3 | TensmitterdataButter | Reading the IIR oF Empty mpty writing the TD8 Clear to Send Data Set Ready MODEM Status Call indicator Reading the MSR Data carrier Detect

5.1.5 INTERRUPT ENABLE REGISTER (IER)

This register enables the four types ae (DLAB =0) ERDRI (Enable Received Data Ready Interrupt) ‘When this bit sets to a logic 1, the Received Data Ready Interrupt is enabled. ETDBEl (Enable Transmitter Data Buffer Empty Interrupt) ‘When this bit sets to a logic 1, the Transmitter Data Buffer Empty Interrupt is enabled. ELSI (Enable Receiver Line Status Interrupt) ‘When this bit sets to logic 1, the Receiver Line Status Interrupt is enabled. EMSI(Enable MODEM Status Interrupt) When this bit sets to a logic 1, the MODEM Status Interrupt is enabled. Bit4-7 ‘These four bits are always set to a logic 0. TC8570AP/AF-15 060489 365

TOSHIBA (UC/UP) BYE D MM 9097249 0026339 310 METOS3 | I COMMUNICATION CONTROLLER

5.1.6 MODEM CONTROL REGISTER (MCR)

This register controls the interface a MODEM or a Data Set or a peripheral device emulating a MODEM. [ar [ar [ ao | oer [one | oas [pea [om [oom [oni] om | DTR (Data Terminal Ready) ‘This bit controls the Data Terminal Ready (-DTR) output, When this bit is set to a logic 1, the -DTR outputs forced to a logic 0. When this bit is reset to a logic 0, the -DTR output is forced to a logic 1. RTS (Request to Send) This bit controls the Request to Send (-RTS) output. When this bit is set to a logic 1, the -RTS output is forced to a logic 0. When this bit is reset to a logic 0, the -RTS outputis forced to a logic 1. OUT1 (Output 1) This bit controls the Output 1 (-OUT 1) signal released for user, When this bit is set to a logic 1, the -OUT 1 output is forced to a logic 0. When this bit is reset to a logic 0, the -OUT 1 output is forced toa logic 1. OUT2 (Output 2) This bit controls the Output 2 (-OUT 2) signal released for user. When this bit is set to a logic 1, the -OUT 2 output is forced to a logic 0, When this bit is reset to a logic 0, the -OUT 2 output is forced to a logic 1. LOOP This bit supplies a local loop back feature for diagnostic testing of the UART. When LOOP set toa logic 1, the following occurs : The transmitter Serial Output (SOUT) is set to the marking (logic 1) state, the Serial Input (SIN) is disconnected, the output of the Transmitter Shift Register is "loop back” into the Receiver Shift Register input internally, the four MODEM control inputs (-CTS, -DSR, -DCD, and -CI) are disconnected, the four MODEM control outputs (-DTR, -RTS, -OUT1, and -OUT2) are internally connected to the four MODEM control inputs, and the MODEM control output pins are forced to their inactive states (high). Tn the diagnostic mode, the transmitted data is immediately received. This feature allows the CPU to verify the transmitting and receiving data paths of the UART. In the diagnostic mode, the receiver and transmitter interrupts are fully operational. The MODEM Control Interrupts are also operational, but the interrupts source are now the lower four bits of the MODEM Control Register, which are internally connected, instead of the four MODEM control inputs. The interrupts are still controlled by the Interrupt Enable Register. BitS-7 ‘These three bits are always set to a logic 0. TC8570AP/AF-16 060489 | 366

TOSHIBA (UC/UP) bYE D M@™ 9097245 0026340 032 METOS3 COMMUNICATION CONTROLLER ] |

5.1.7 MODEM STATUS REGISTER (MSR)

This register provides the current status of the control lines from the MODEM or peripheral device. In addition to this current status information, the four bits of the MODEM Status Register provide information. These bits are set to a logic 1 whenever a control input from MODEM changes state. They are reset to a logic 0 whenever the CPU reads the MODEM Status Register. [az [at [ao] os7 [ose [as | oes | pes [bez | oer | peo | Li ts fo foo [oa [ose [cts | poco | tec [pose [cts | DCTS (Delta Clear to Send) This bit indicates the change of -CTS input. It indicates that -CTS input to the chip has changed state since the last time read by the CPU. DDSR (Delta Data Set Ready) This bit indicates the change of -DSR input. It indicates that -DSR input to the chip has changed state since the last time read by the CPU. TEC! (trailing Edge Call indicator) ‘This bit indicates the trailing edge of -Cl input. It indicates that -CI input to the chip has changed from an ON (logic 1) to an OFF (logic 0) condition. DDCD (Delta Data Carrier Detect) This bit indicates the changed state since the last time read by the CPU. ‘note “' Whenever DCTS, DDSR, TEDI, or DDCD is set to a logic 1, MODEM Status Interruptis generated. CTS (Clear to Send) This bit is the complement of the -CTS input. If LOOP of the MODEM Status Register is set to a logic 1, this bit is equivalent to RTS in the MODEM Control Register. DSR (Data Set Ready) This bit is the complement of the -DSR input. If LOOP of the MODEM Status Register is set to a logic 1, this bit is equivalent to DTR in the MODEM Control Register. Ci (Call Indicator) This bit is the complement of the -Cl input. If LOOP of the MODEM Status Register is set to a logic 1, this bit is equivalent to OUT! in the MODEM Control Register. DCD (Data Carrier Detect) This bit is the complement of the -DCD input. If LOOP of the MODEM Status Register set to a logic 1, this bit is equivalent to OUT2 in the MODEM Control Register. TC8570AP/AF-17 060489 367

an ’ TOSHIBA (UC/UP) BYE D MM 9097249 0026341 T79 METOSS

5.1.8 SCRATCHPAD REGISTER (SCR)

This Read/Write Register does not entirely control the UART. It is intended as a Scratchpad Register to be used by the programmer to hold data temporarily. When the data output control mode (-MSEL=0) is selected, the contents of CS1 appears DO bit. At this time, CS1 becomes a 1 bit input port. [a [a [a [oer | oes] oes [oer [on on | om | om] Pat fo for | ios Tos [oe Tos [oe | or | boxes

5.1.9 RESET FUNCTION

In reset state, all register (except Receiver Date Buffer (RDB), Transmit Data Buffer (TDB), and Baud-rate generator) and control logic as well as the output signal for MODEM, are cleared. REGISTER/BUFFER/SIGNAL RESET CONDITION RESET CONTROL (REGISTER BIN Interrupt Enable Register (IER) ----0000 Interruptident.Register (ua) | ~~ -- 0 01 | Resetinput | Line Control Register (uc) MODEMControiRegister (MCR) | 00000000 | _ Resetinput | MODEM Status Register ___ (MSR) Serial input (sour) Receiver Line Status interrupt ResetnpuROB Read Transmitter Data Buffer Empty interrupt Reset input/MSR Read — : Always0 x =: External input TC8570AP/AF-18 060489 368

TOSHIBA (UC/UP) 64E D MM 9097249 0026342 905 METOS3 COMMUNICATION CONTROLLER Il 6. ELECTRICAL CHARACTERISTICS

6.1 ABSOLUTE MAXIMUM RATINGS

Operating _ °

6.2 DC CHARACTERISTICS

Ta =-40°C~ + 85°C, Vec = 5V 410% [raranveren [svweor [conmivon [vans [wax | vr |inputHigh Voltage | vm | Sid; | ee | VC | OutputlowVoltage | Vor | le2ama |S | | Vi | Output High Voltage | Von | low=-t1ma Vcc] - | v_| TC8570AP/AF-19 060489 369

TOSHIBA (UC/UP) BYE D M@® 9097249 G02b343 B41 mmTos3 ] l COMMUNICATION CONTROLLER

6.3 AC CHARACTERISTICS

Ta =-40°C~ + 85°C, Vcc = 5VE10% [rarameren | svmwou | wm [rye [| max [unr | [ceckoaetme | we | a0 || [cick High" Pusewiah [we | wo | | | | [clo tow"Pusewiath [mu | 0 || | | [Atrrubewisth ie |] fadaressetTime [we | oo | | | | [chiseecsetuptine [ee | oo || | | [chipseecrHoisTine [te | | | | me [RO,-Ro usewieth [wx | as |_| | = [ResdcyeeDetaytine wee | so [Reedcycetine ime | a6 | [-RDoUTDebeyTime(romAd,-AO) | wo |__| | | | [DstaDeloyTime(romad,-#0) [wo |_| | 5 | = | [DstaFiostDeleytine [tr | 0 | | 100 | we | we -wePuse wnat [tw | 100 | |_| | fwitecyeetine [wwe | 360 | | [me [Data Setup Tine romwa awe) [tow | «0 | | | | [bata Hoid Tine (rome, we) [wo | a | [| rs [esourDelytine to | || 00 | | [address Setup Tine omAD 85)» [wa | | ||» | [adarss Hold Time (rom®O,-A0) * [twa | a0 | | | | [chip eter setupTime(tromaD -R0)* [tex | so | | | me | [chip Selec HoidTine romRO,-R0) * [xs | 20 | |__| = | [address Hola Time (romw, we) * [wa | 20 | [| [chip elect Setup Time ramwn.WR * | te | so [| | |e chip setet Hold Tine (rome, WA)? [ewes | 20 | |_| | [eesereusewiatn Pus | | | [-sauDouToeleytine [ay | | | a5 | me [sauDouT “owievel" watNii=mMiTA| ww | aa | [| a meme few fom | | (fx = 3MHz +3) TC8570AP/AF-20 060489 370

TOSHIBA (UC/UP) B4E D MM 9097249 0026344 788 MTOSS COMMUNICATION CONTROLLER ll PARAMETER SYMBOL [wn Tove. Tmax | UNIT RDB ISR Read io NIRPT ResetOdlay Tine [wa] ao Stop Bit to INTRPT Delay Time [uss [| 1 | +i aid rak Stop Bit to INTRPT (TDBE) Delay Time [us | 8 | || sauvour | UR R ead to INTRPT (TDBE) Reset Delay Time a | Initial TORE INT Reset to Transmit Start Delay 24 | AvDouT Time Cycles MODEM Control NCR Wite to MODEW Output Oday Tine [awa [ae MODEM InputChangetoINTRPTDelayTime | twsi || | 280 | ons | * + Applicable only when -ALE is tied low. TC8570AP/AF-21 060489 371

TOSHIBA (UC/UP) — GYE D MM 9097249 0026345 614 METOS3 || communicaTion CONTROLLER

6.3.1 EXTERNAL LOAD CONDITIONS of TERMINAL

6.3.2 ACINPUT WAVEFORM for TEST

0.4V Ava sin ah

6.3.3 EXTERNAL CLOCK INPUT

t XIN TC8570AP/AF-22 060489 372

TOSHIBA (UC/UP) BYE D MM 9097249 0026346 SSO METOS3 COMMUNICATION CONTROLLER ll READ CYCLE tee -ALE aaa | tce | tec | tra. | -CS2 iaiake atelal Koa XT CS1,CSO Soleatenl Delenkel [sacs | “ CSR — t tr fe ee | RD -RD le WR ACTIVE -WR <_tro_,| -RDOUT tro tor TC8570AP/AF-23 060489 373

TOSHIBA (UC/UP) B4E D MM 9097249 OO2b34? 497 METOS3 | ] COMMUNICATION CONTROLLER WRITE CYCLE |< tic __. ~ALE os tee tes twa | C52 | coat €S1,CSO0 -- - tues | _ CS\\ _— tesw. tw WR -WR | or RD ACTIVE -RD tow |_toF | TC8570AP/AF-24 060489 : 374

EE es — — ee TOSHIBA (UC/UP) G4E D MM 9097249 0026348 323 METOS3 COMMUNICATION CONTROLLER || -BAUDOUT TIMING dxs| XIN teau || -BAUDOUT (+1) teau il -BAUDOUT (+2) —|\\* teau -BAUDOUT (#3) -BAUDOUT (=N,N> 3) RECEIVER TIMING RCLK SAMPLE CLK SIN (Recein i: ~| SAMPLE cLK >| <- trsi INTRPT (Data Ready or Receiver Error) | trst (Read RDB,LSR) RD TC8570AP/AF-25 060489 375

TOSHIBA (UC/UP) BYE D BM 9097249 0026349 2bT MTOSS |] COMMUNICATION CONTROLLER TRANSMITTER TIMING rangitt Date) srarr/ vata (6-8) X eanity/ syor, \\ START t INTRPT (TDBE) -WR (TDI ‘tri >| RD (IIR) ) Kacrive)X RD MODEM CONTROL TIMING -RTS,-DTR -OUT1,-OUT2 -CTS,-DSR -DCD INTRPT (MSR) - SR) sn XX tusi -Ccl \\ Vi, TC8570AP/AF-26 060489 376

TOSHIBA (UC/UP) = BYE Ds 9097249 0026350 Tal MTOS3 COMMUNICATION CONTROLLER Il 7. PACKAGE DIMENSION DIP40-P-600 UNIT: mm 40 21 __ el; 1 20 2 | 51.3MAX lz 15.2440.25 a = é 0.25 +01. \\ 5 0.5 £0.15 ii 2s4x025 28 jo~ is? = 1440.15 co TC8570AP/AF-27 060489 377

TOSHIBA (UC/UP) BYE D MM 9097249 0026351 916 MTOSS | COMMUNICATION CONTROLLER QFP44-P-1414F UNIT: mm 16.9 £0.3 14.0+0.2 3.0TYP | Tan AAT AAA AL HHOGHEEKaag DUO OHA and = E= — Eas |raoto2 |ie9t03 3.0TvP, — — 44..crert Fea2 v HHOUOGHGHOOo HHH CHEER OOH i 3.0TYP, i [os] TYP. 0.3501 w4 2.740.2 sal {7 YO nae | 1.15202 | Detail fiqure of A TC8570AP/AF-28 060489 378