TC850 TELCOM | Alldatasheet
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3-77TELCOM SEMICONDUCTOR, INC. TC850
FEATURES
n 15-bit Resolution Plus Sign Bit n Up to 40 Conversions per Second n 12 Conversions per Second Guaranteed n Integrating ADC Technique — Monotonic — High Noise Immunity — Auto-Zeroed Amplifiers Eliminate Offset Trimming µVP-P n Flexible Operational Control — Continuous or On-Demand Conversions — Data Valid Output n Bus Compatible, 3-State Data Outputs — 8-Bit Data Bus — Simple µP Interface — Two Chip Enables — Read ADC Result Like Memory n n 40-Pin Dual-in-Line or 44-Pin PLCC Packages GENERAL DESCRIPTION The TC850 is a monolithic CMOS analog-to-digital converter (ADC) with resolution of 15-bits plus sign. It combines a chopper-stabilized buffer and integrator with a unique multiple-slope integration technique that increases conversion speed. The result is 16 times improvement in speed over previous 15-bit, monolithic integrating ADCs (from 2.5 conversions per sec up to 40 per sec). Faster conversion speed is especially welcome in systems with human interface, such as digital scales. The TC850 incorporates an ADC and a µP-compatible digital interface. Only a voltage reference and a few noncriti- cal passive components are required to form a complete 15- bit plus sign ADC. CMOS processing provides the TC850 with high- impedance differential inputs. Input bias current is typically only 30pA, permitting direct interface to sensors. Input sensitivity of 100µV per least significant bit (LSB) eliminates the need for precision external amplifiers. The internal amplifiers are auto-zeroed, guaranteeing a zero digital output with 0V analog input. Zero adjustment potentiometers or calibrations are not required. The TC850 outputs data on an 8-bit, 3-state bus. Digital inputs are CMOS compatible; outputs are TTL/CMOS com- patible. Chip-enable and byte-select inputs combined with an end-of-conversion output ensures easy interfacing to a wide variety of microprocessors. Conversions can be per- formed continuously or on command. In continuous mode, data is read as three consecutive bytes and manipulation of address lines is not required. Operating from ±5V supplies, the TC850 dissipates only 20mW. It is packaged in 40-pin plastic or ceramic dual-in- line packages (DIPs) and in a 44-pin plastic leaded chip carrier (PLCC), surface-mount package.
ORDERING INFORMATION
Part No. Package Temperature Range TC850CLW 44-Pin PLCC 0 °C to +70°C TC850CPL 40-Pin Plastic DIP 0 °C to +70°C TC850IJL 40-Pin CerDIP – 25 °C to +85°C TC850ILW 44-Pin PLCC – 25 °C to +85°C FUNCTIONAL BLOCK DIAGRAM 15-BIT, FAST-INTEGRATING CMOS ANALOG-TO-DIGITAL CONVERTER REF 1+ – BUF INT IN BUFFER INTEGRATOR COMPARATOR32 232425363439 15 8 DB7 TC850 REF R INT C INT INT OUT IN+ 6-BIT UP/DOWN COUNTER REF 2 DB0 9-BIT UP/DOWN COUNTER . . . .5 3 WRCONT/ DEMAND ANALOG MUX IN– COMMON 22 40 +5V–5V OSC 2 17 7 L/H OVR/ POL RD CS CEOSC 1 A/D CONTROL SEQUENCER DATA LATCH OCTAL 2-INPUT MUX 3-STATE DATA BUS CLOCK OSCILLATOR BUS INTERFACE DECODE LOGIC TC850-4 11/5/96
3-78 TELCOM SEMICONDUCTOR, INC. ABSOLUTE MAXIMUM RATINGS* Voltage Reference Input Ambient Operating Temperature Range ELECTRICAL CHARACTERISTICS: VS = ±5V, fCLK = 61.44 kHz, VFS = 3.2768V, TA = 25°C, Fig. 1 Test Circuit, unless otherwise specified. Symbol Parameter Test Conditions Min Typ Max Unit Zero-Scale Error V IN = 0V ±0.25 ±0.5 LSB End Point Linearity Error –V FS ≤ VIN ≤ +V FS — ±1 ±2 LSB Differential Nonlinearity — ±0.1 ±0.5 LSB IIN Input Leakage Current V IN = 0V, TA = 25°C — 30 75 pA VCMR Common-Mode Voltage Range Over Operating Temperature Range V SS + 1.5 — V DD – 1.5 V CMRR Common-Mode Rejection Ratio V IN = 0V, VCM = ±1V — 80 — dB Full-Scale Gain Temperature External Ref Temperature Coefficient Coefficient = 0 ppm/ °C — 2 5 ppm/ °C 0°C ≤ TA ≤ +70°C Zero-Scale Error V IN = 0V — 0.3 2 µV/°C Temperature Coefficient 0 °C ≤ TA ≤ +70°C Full-Scale Magnitude V IN = ±3.275V — 0.5 2 LSB Symmetry Error eN Input Noise Not Exceeded 95% of Time — 30 — µVP-P IS+ Positive Supply Current — 2 3.5 mA IS– Negative Supply Current — 2 3.5 mA VOH Output High Voltage I O = 500 µA 3.5 4.9 — V VOL Output Low Voltage I O = 1.6 mA — 0.15 0.4 V IOP Output Leakage Current Pins 8 – 15, High-Impedance State — 0.1 1 µA VIH Input High Voltage Note 3 3.5 2.3 — V IL Input Low Voltage Note 3 — 2.1 1 V IPU Input Pull-Up Current Pins 2, 3, 4, 6, 7; V IN = 0V — 4 — µA IPD Input Pull-Down Current Pins 1, 5; V IN = 5V — 14 — µA IOSC Oscillator Output Current Pin 18, V OUT = 2.5V — 140 — µA C IN Input Capacitance Pins 1 – 7, 17 — 1 — pF C OUT Output Capacitance Pins 8 – 15, High-Impedance State — 15 — pF tCE Chip-Enable Access Time CS or CE, RD = LOW (Note 1) — 230 450 nsec tRE Read-Enable Access Time CS = HIGH, CE = LOW (Note 1) — 190 450 nsec tDHC Data Hold From CS or CE RD = LOW (Note 1) — 250 450 nsec tDHR Data Hold From RD CS = HIGH, CE = LOW (Note 1) — 210 450 nsec tOP OVR/POL Data Access Time CS = HIGH, CE = LOW, RD = LOW (Note 1) — 140 300 nsec Package Power Dissipation (TA ≤ 70°C) *Static-sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static fields. Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to Absolute Maximum Rating Conditions for extended periods may affect device reliability. 15-BIT, FAST-INTEGRATING CMOS ANALOG-TO-DIGITAL CONVERTER TC850
3-79TELCOM SEMICONDUCTOR, INC. ELECTRICAL CHARACTERISTICS (Cont.) Symbol Parameter Test Conditions Min Typ Max Unit tLH Low/High Byte Access Time CS = HIGH, CE = LOW, RD = LOW (Note 1) — 140 300 nsec Clock Setup Time Positive or Negative Pulse Width 100 — — nsec tWRE RD Minimum Pulse Width CS = HIGH, CE = LOW (Note 2) 450 230 — nsec tWRD RD Minimum Delay Time CS = HIGH, CE = LOW (Note 2) 150 50 — nsec tWWR WR Minimum Pulse Width CS = HIGH, CE = LOW, Demand Mode 75 25 — nsec Clock Setup Time Positive or Negative Pulse Width 100 — — nsec NOTES: 1. Demand mode, CONT/DEMAND = LOW. Figure 10 timing diagram. CL = 100pF. 2. Continuous mode, CONT/DEMAND = HIGH. Figure 12 timing diagram. 3. Digital inputs have CMOS logic levels and internal pull-up/pull-down resistors. For TTL compatibility, external pull-up resistors to VCC are recommended. TC850CPL TC850IJL COMMON C BUFB BUFFER INTIN INTOUT COMP NC = NO INTERNAL CONNECTION GND C INTA C BUFA C INTB IN– IN+ REF – TEST OSC 2 OSC 1 BUSY DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 L/H OVR/POL CONT/DEMAND RD CE CS WR VSS VDD REF 1 REF 2 C REF1 C REF1 – C REF2 – C REF2 C REF2 COMMON INTIN INTOUT COMP 18 19 20 21 23 24 6543 1 4 4 2 43 42 41 40 25 26 27 28 3214 3115 3016 2917
12 TC850CLW
IN– NC NCNC IN+ REF – TEST GND OSC 2 OSC 1 DB0 DB1 DB2 DB3 DB4 NC DB5 DB6 DB7 CS CE WR RD CONT/DEMAND OVR/POL L/H BUFFER BUSY VSS VDD REF 1 REF 2 C REF1 C REF1 – C REF2 PIN CONFIGURATIONS TC850 15-BIT, FAST-INTEGRATING CMOS ANALOG-TO-DIGITAL CONVERTER
3-80 TELCOM SEMICONDUCTOR, INC. 15-BIT, FAST-INTEGRATING CMOS ANALOG-TO-DIGITAL CONVERTER TC850 PIN DESCRIPTIONS 40-Pin DIP Pin No. Symbol Description 1 CS Chip select, active HIGH. Logically ANDed with CE to enable read and write inputs. (See note 4.) 2 CE Chip enable, active LOW. (See note 5.) 3 WR Write input, active LOW. When chip is selected (CS = HIGH and CE = LOW) and in demand mode (CONT/DEMAND = LOW), a logic LOW on WR starts a conversion. (See note 4.) 4 RD Read input, active LOW. When CS = HIGH and CE = LOW, a logic LOW on RD enables the 3-state data outputs. (See note 5.) 5 CONT/DEMAND Conversion control input. When CONT/DEMAND = LOW, conversions are initiated by the WR input. When CONT/DEMAND = HIGH, conversions are performed continuously. (See note 4.) 6 OVR/POL Overrange/polarity data-select input. When making conversions in the demand mode (CONT/ DEMAND = LOW), OVR/POL controls the data output on DB7 when the high-order byte is active. (See note 5.) 7 L/H Low/high byte-select input. When CONT/DEMAND = LOW, this input controls whether low- byte or high-byte data is enabled on DB0 through DB7. (See note 5.) 8 DB7 Most significant data bit output. When reading the A/D conversion result, the polarity, overrange, and DB7 data are output on this pin. (See text.) 9 – 15 DB6–DB0 Data outputs DB6–DB0. 3-state, bus compatible. 16 BUSY A/D conversion status output. BUSY goes to a logic HIGH at the beginning of the deintegrate phase and goes LOW when conversion is complete. The falling edge of BUSY can be used to generate a µP interrupt. 17 OSC 1 Crystal oscillator connection or external oscillator input. 18 OSC 2 Crystal oscillator connection. 19 TEST For factory testing purposes only. Do not make external connection to this pin. 20 DGND Digital ground connection. 21 COMP Connection for comparator auto-zero capacitor. Bypass to V SS with 0.1 µF. 22 V SS Negative power supply connection, typically – 5V. 23 INT OUT Output of the integrator amplifier. Connect to CINT. 24 INT IN Input to the integrator amplifier. Connect to summing node of RINT and CINT. 25 BUFFER Output of the input buffer. Connect to R INT. 26 C BUFB Connection for buffer auto-zero capacitor. Bypass to VSS with 0.1 µF. 27 C BUFA Connection to buffer auto-zero capacitor. Bypass to VSS with 0.1 µF. 28 C INTA Connection for integrator auto-zero capacitor. Bypass to VSS with 0.1 µF. 29 C INTB Connection for integrator auto-zero capacitor. Bypass to VSS with 0.1 µF. 30 COMMON Analog common. 31 IN – Negative differential analog input. 30 COMMON Analog common. 33 REF 2+ Positive input for reference voltage VREF2 . (VREF2 = VREF1 /64) 34 C REF2 + Positive connection for VREF2 reference capacitor. 35 C REF2 – Negative connection for VREF2 reference capacitor. 36 REF – Negative input for reference voltages. 37 C REF1 – Negative connection for VREF1 reference capacitor. 38 C REF1 + Positive connection for VREF1 reference capacitor. 39 REF 1+ Positive input for VREF1 . 40 V DD Positive power supply connection, typically +5V. NOTES: 4. This pin incorporates a pull-down resistor to DGND. 5. This pin incorporates a pull-up resistor to VDD .
3-81TELCOM SEMICONDUCTOR, INC. fabrication process is used. 15-bit resolution up to 40 conversions per second. capacitor is rapidly discharged to yield a resolution of 9 bits. very high resolution and accuracy. the need for zero-offset adjustments. for expensive, precision passive components. tRI = Reference voltage integration time (variable). Figure 1. Standard Circuit Configuration NOTES: Unless otherwise specified, all 0.1µF capacitors are film dielectric. Ceramic capacitors are not recommended.
3-83TELCOM SEMICONDUCTOR, INC. performs up to three overrange deintegrate subphases. Each subphase occupies a maximum of 64 clock pulses. offset, while retaining full 15-bit resolution. subphases: (1) fast, (2) slow, and (3) overrange deintegrate. pulses, yielding 9 bits of resolution. Figure 4. Conversion Timing TC850 signal-integrate period is 256 clock periods, or counts.
1280 CLOCK CYCLES
3-85TELCOM SEMICONDUCTOR, INC. Table 1. Bus Interface Truth Table
1 X X X X High-Impedance State
NOTES: 1. Pin numbers refer to 40-pin DIP.
- Extended overrange operation: Although rated at 15 bits (±32,767 counts) of resolution, the TC850 provides an additional 191 counts
3.2958V. The extended resolution is signified by the overrange bit being high and the low-order byte contents being between 0 and 190.
- Continuous mode data transfer:
(1) The first byte read will be the high-order byte, with DB7 = polarity. (2) The second byte read will contain the low-order byte. (3) The third byte read will again be the high-order byte, but with DB7 = overrange. b. All three data bytes must be read within 443-1/2 clock cycles after the falling edge of BUSY. inputs can remain enabled through the entire data transfer sequence.
3-86 TELCOM SEMICONDUCTOR, INC. 15-BIT, FAST-INTEGRATING CMOS ANALOG-TO-DIGITAL CONVERTER TC850 R INT = . Pin Description (Digital) Chip Select and Chip Enable (CS and CE) The CS and CE inputs permit easy interfacing to a variety of digital bus systems. CE is active LOW while CS is active HIGH. These inputs are logically ANDed internally and are used to enable the RD and WR inputs. Write Enable Input (WR) The write input is used to initiate a conversion when the TC850 is in demand mode. CS and CE must be active for the WR input to be recognized. The status of the data bus is meaningless during the WR pulse, because no data is actually written into the TC850. Read Enable Input (RD) The read input, combined with CS and CE, enables the 3-state data bus outputs. Also, in continuous mode, the rising edge of the RD input activates an internal byte counter to sequentially read the three data bytes. Low/High Byte Select (L/H) The L/H input determines whether the low (least signifi- cant) byte or high (most significant) byte of data is placed on the 3-state data bus. This input is meaningful only when the TC850 is in the demand mode. In the continuous mode, data must be read in three predetermined bytes, so the L/H input is ignored. Overrange/Polarity Bit Select (OVR/POL) The TC850 provides 15 bits of resolution, plus polarity and overrange bits. Thus, 17 bits of information must be transferred on an 8-bit data bus. To accomplish this, the overrange and polarity bits are multiplexed onto data bit DB7 of the most significant byte. When OVR/POL is HIGH, DB7 of the high byte contains the overrange status (HIGH = analog input overrange, LOW = input within full scale). When OVR/POL is LOW, DB7 is HIGH for positive analog input polarity and LOW for negative polarity. The OVR/POL input is meaningful only when CS, CE, and RD are active, and L/ H is LOW (i.e., the most significant byte is selected). OVR/ POL is ignored when the TC850 is in continuous mode. Continuous/Demand Mode Input (CONT/DEMAND) This input controls the TC850 operating mode. When CONT/DEMAND is HIGH, the TC850 performs conversions continuously. In continuous mode, data must be read in the prescribed sequence shown in Table I. Also, all three data bytes must be read within 443-1/2 internal clock cycles after the BUSY output goes low. After 443-1/2 clock cycles data will be lost. When CONT/DEMAND is LOW, the TC850 begins a conversion each time CS and CE are active and WR is pulsed LOW. The conversion is complete and data can be read after the falling edge of the BUSY output. In demand mode, data can be read in any sequence, and remains valid until WR is again pulsed LOW. Busy Output (BUSY) The BUSY output is used to convey an end-of-conver- sion to external logic. BUSY goes HIGH at the beginning of the deintegrate phase and goes LOW at the end of the conversion cycle. Data is valid on the falling edge of BUSY. The output-high period is fixed at 836 clock periods, regard- less of the analog input value. BUSY is active during continuous and demand mode operation. This output can also be used to generate an end-of- conversion interrupt in µP-based systems. Noninterrupt- driven systems can poll BUSY to determine when data is valid. ANALOG SECTION APPLICATIONS Component Selection Reference Voltage The typical value for reference voltage VREF1 is 1.6384V. This value yields a full-scale voltage of 3.2768V and resolu- tion of 100µV per step. The V REF2 value is derived by dividing VREF1 by 64. Thus, typical VREF2 value is 1.6384V/64, or 25.6mV. The VREF2 value should be adjusted within ±1% to maintain 15-bit accuracy for the total conversion process; i.e., V REF2 = ±1%. The reference voltage is not limited to exactly 1.6384V, however, because the TC850 performs a ratiometric con- version. Therefore, the conversion result will be: Digital counts = • 16384. VIN VREF1 For a full-scale voltage of 3.2768V, values of RINT between 120kΩ and 150kΩ are acceptable. VFULL SCALE 25 µA The full-scale voltage can range from 3.2V to 3.5V. Full- scale voltages of less than 3.2V will result in increased noise in the least significant bits, while a full-scale above 3.5V will exceed the input common-mode range. Integration Resistor The TC850 buffer supplies 25µA of integrator charging current with minimal linearity error. R INT is easily calculated: VREF1
3-89TELCOM SEMICONDUCTOR, INC. Figure 9. Conversion Timing, Demand Mode Figure 10. Bus Output Timing, Demand Mode
836 CLOCK CYCLES
1100 CLOCK CYCLES
319 CLOCK
0 T0 6
or remain LOW during the entire DATA-READ sequence (i.e., µP I/O port interface).
3-90 TELCOM SEMICONDUCTOR, INC.
1280 INTERNAL CLOCK CYCLES
Figure 11. Conversion Timing, Continuous Mode Figure 12. Bus Output Timing, Continuous Mode