TC835

TC835 TELCOM | Alldatasheet

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Technical content

3-65TELCOM SEMICONDUCTOR, INC. TC835

FEATURES

n Upgrade of Pin-Compatible TC7135, ICL7135, MAX7135 and SI7135 n Guaranteed 200 kHz Operation n Single 5V Operation With TC7660 n Multiplexed BCD Data Output n UART and Microprocessor Interface n Control Outputs for Auto-Ranging n No Sample and Hold Required

APPLICATIONS

n Personal Computer Data Acquisition n Scales, Panel Meters, Process Controls n HP-IL Bus Instrumentation

ORDERING INFORMATION

Part No. Package Range TC835CBU 64-Pin PQFP 0 °C to +70°C TC835CKW 44-Pin PQFP 0 °C to +70°C TC835CPI 28-Pin Plastic DIP 0 °C to +70°C NOTE: Tape and reel available for 44-pin PQFP packages. PERSONAL COMPUTER DATA ACQUISITION A/D CONVERTER GENERAL DESCRIPTION The TC835 is a low-power, 4-1/2 digit (0.005% resolu- tion), BCD analog-to-digital converter (ADC) that has been characterized for 200 kHz clock rate operation. The five conversions per second rate is nearly twice as fast as the ICL7135 or TC7135. The TC835 (like the TC7135) does not use the external diode-resistor roll-over error compen- sation circuits required by the ICL7135. The multiplexed BCD data output is perfect for interfac- ing to personal computers. The low-cost, greater than 14- bit high-resolution, and 100 µV sensitivity makes the TC835 exceptionally cost-effective. Microprocessor-based data acquisition systems are supported by the BUSY and STROBE outputs, along with the RUN/HOLD input of the TC835. The overrange, under- range, busy, and run/hold control functions and multiplexed BCD data outputs make the TC835 the ideal converter for µP-based scales and measurement systems and intelligent panel meters.* The TC835 interfaces with full-function LCD and LED display decoder/drivers. The UNDERRANGE and OVERRANGE outputs may be used to implement an auto- ranging scheme or special display functions. *See Application Notes 16 and 17 for microprocessor interface tech- niques. DATA BUS CONTROL ADDRESS BUS 6522 -VIA- PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 CA1 CA2 PB5 PB4 PB0 PB3 PB2PB1 CHANNEL SELECTION GAIN SELECTION SEL 157 POL OR UR STB R/H V+ REF CAP BUF AZ INT INPUT+ VR INPUT– ANALOG COMMON DGND REF VOLTAGE GAIN: 10, 20, 50, 100 15V 15V CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 DIFFERENTIAL MULTIPLEXER DG529 D A D B WR A 1 A 0 EN 5V+ fIN fIN LH0084 TC835 TYPICAL APPLICATION TC835-8 11/5/96

3-66 TELCOM SEMICONDUCTOR, INC. PERSONAL COMPUTER DATA ACQUISITION A/D CONVERTER TC835 ABSOLUTE MAXIMUM RATINGS* (Note 1) + to V– (Note 2) NOTES: 1. Functional operation is not implied. 2. Limit input current to under 100 µA if input voltages exceed supply voltage. 3. Full-scale voltage = 2V. 4. V IN = 0V. 6. External reference temperature coefficient less than 0.01 ppm/°C. 7. – 2V ≤ VIN ≤ +2V. Error of reading from best fit straight line. 8. |VIN| = 1.9959. 9. Test circuit shown in Figure 1. 10. Specification related to clock frequency range over which the TC835 correctly performs its various functions. Increased errors result at higher operating frequencies. ELECTRICAL CHARACTERISTICS: TA = +25°C, fCLOCK = 200 kHz, V+ = +5V, V– = – 5V, unless otherwise specified. Symbol Parameter Test Conditions Min Typ Max Unit Analog Display Reading With Notes 3 and 4 –0.0000 ±0.0000 +0.0000 Display Zero Volt Input Reading TC Z Zero Reading V IN = 0V — 0.5 2 µV/°C Temperature Coefficient Note 5 TC FS Full-Scale V IN = 2V — — 5 ppm/ °C Temperature Coefficient Notes 5 and 6 NL Nonlinearity Error Note 7 — 0.5 1 Count DNL Differential Linearity Error Note 7 — 0.01 — LSB Display Reading in V IN = VREF +0.9996 +0.9998 +1.0000 Display Ratiometric Operation Note 3 Reading ±FSE ± Full-Scale Symmetry –V IN = +VIN — 0.5 1 Count Error (Roll-Over Error) Note 8 IIN Input Leakage Current Note 4 — 1 10 pA eN Noise Peak-to-Peak Value Not Exceeded 95% of Time —1 5— µVP-P Digital IIL Input Low Current V IN = 0V — 10 100 µA IIH Input High Current V IN = +5V — 0.08 10 µA VOL Output Low Voltage I OL = 1.6 mA — 0.2 0.4 V VOH Output High Voltage B1, B2, B4, B8, D1–D 5 IOH = 1 mA 2.4 4.4 5 V Busy, Polarity, Overrange, IOH = 10 µA 4.9 4.99 5 V Underrange, Strobe fCLK Clock Frequency Note 10 0 200 1200 kHz Power Supply V + Positive Supply Voltage 4 5 6 V V – Negative Supply Voltage – 3 – 5 – 8 V I+ Positive Supply Current fCLK = 0 Hz — 1 3 mA I– Negative Supply Current fCLK = 0 Hz — 0.7 3 mA PD Power Dissipation f CLK = 0 Hz — 8.5 30 mW Package Power Dissipation (TA ≤ 70°C) *Static-sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static fields. Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to Absolute Maximum Rating Conditions for extended periods may affect device reliability.

3-67TELCOM SEMICONDUCTOR, INC. PERSONAL COMPUTER DATA ACQUISITION A/D CONVERTER TC835 PIN CONFIGURATIONS TC835CKW 12 13 14 15 17 18 44 43 42 41 39 3840 37 36 35 34 19 20 21 22 268 259 2410 2311 NC NC NC ANALOG COM REF IN UR OR STROBE NC NC NC NC RUN/HOLD DGND POLARITY NC NC CLK IN NC INT OUT AZ IN BUFF OUT REF CAP– –INPUT +INPUT NC NC REF CAP+ NC NC (MSD) D5 (LSB) B1 (MSB) B8 NC NC D1 (LSD) BUSY NOTES: TC835CPI RUN/HOLD STROBE OVERRANGE D1 (LSD) BUSY CLOCK IN POLARITY DIGTAL GND UNDERRANGE (LSB) B1 (MSD) D5 V + +INPUT – INPUT C REF C REF BUFF OUT AZ IN INT OUT ANALOG COM REF IN V – B8 (MSD) 1. NC = No internal connection. 2. Pins 9, 25, 40 and 56 are connected to the die substrate. The potential at these pins is approximately V+. No external connections should be made. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 61 60 59 58 57 56 55 54 53 52 51 50 4964 TC835CBU INT OUT NC AZ IN NC +INPUT NC BUFF OUT BUF CAP– NC SUB BUF CAP+ NC –INPUT NC NC NC NC NC NC STROBE RUN/HOLD DGND POL SUB CLK IN BUSY NC NC NC NOTES 1 & 2 NC NC NC NC NC NC NC NC OVERRANGE UNDERRANGE SUB REF IN ANALOG COM NC NC NC NC NC NC SUB NC NC NC NC

3-69TELCOM SEMICONDUCTOR, INC. sive approximation converters in high-noise environments. Figure 4. Basic Dual-Slope Converter tRI = Reference voltage integration time (variable).

1 V R tRI ,

3-70 TELCOM SEMICONDUCTOR, INC. Table 1. Internal Analog Gate Status *NOTE: Assumes a positive polarity input signal. SWRI would be closed for a negative input signal. condition exists, the phase is extended to 6200 clock cycles. swing within 0.3V of either supply without loss of linearity.

3-72 TELCOM SEMICONDUCTOR, INC. through the D1 digit drive pulse. next reference-integration phase. BUSY. The bit is set low at the next signal-integration phase. A positive input is registered by a logic "1" polarity signal. Figure 8. Strobe Signal Pulses Low Five Times per Conversion PULSE IS DEPENDENT ON ANALOG INPUT. determined correctly. This is useful in null applications. wide, except D5, which is 201 clock pulses wide. ing visual display indication. condition, all data bits are at a logic "0" state.

3-73TELCOM SEMICONDUCTOR, INC. TC835 PERSONAL COMPUTER DATA ACQUISITION A/D CONVERTER The stability of the reference voltage is a major factor in the overall absolute accuracy of the converter. For this reason, it is recommended that a high-quality reference be used where high-accuracy absolute measurements are being made. Suitable references are: Part Type Manufacturer TC04A TelCom Semiconductor TC9491 TelCom Semiconductor APPLICATIONS INFORMATION Component Value Selection The integrating resistor is determined by the full-scale input voltage and the output current of the buffer used to charge the integrator capacitor. Both the buffer amplifier and the integrator have a class A output stage, with 100 µA of quiescent current. A 20 µA drive current gives negligible linearity errors. Values of 5 µA to 40 µA give good results. The exact value of an integrating resistor for a 20 µA current is easily calculated. R INT = Integrating Capacitor The product of integrating resistor and capacitor should be selected to give the maximum voltage swing that ensures the tolerance buildup will not saturate the integrator swing (approximately 0.3V from either supply). For ±5V supplies and ANALOG COMMON tied to supply ground, a ±3.5V to ±4V full-scale integrator swing is adequate. A 0.10 µF to 0.47 µF is recommended. In general, the value of C INT is given by: C INT = [10,000 × clock period] × IINT Integrator output voltage swing (10,000) (clock period) (20 µA) Integrator output voltage swing A very important characteristic of the integrating capaci- tor is that it has low dielectric absorption to prevent rollover or ratiometric errors. A good test for dielectric absorption is to use the capacitor with the input tied to the reference. This ratiometric condition should read half-scale 0.9999, any deviation is probably due to dielectric absorption. Polypro- pylene capacitors give undetectable errors at reasonable cost. Polystyrene and polycarbonate capacitors may also be used in less critical applications. Auto-Zero and Reference Capacitors The size of the auto-zero capacitor has some influence on the noise of the system. A large capacitor reduces the noise. The reference capacitor should be large enough such that stray capacitance to ground from its nodes is negligible. The dielectric absorption of the reference capacitor and auto-zero capacitor are only important at power-on, or when the circuit is recovering from an overload. Smaller or cheaper capacitors can be used if accurate readings are not required for the first few seconds of recovery. Reference Voltage The analog input required to generate a full-scale output is V IN = 2 VREF . Conversion Timing Line Frequency Rejection A signal integration period at a multiple of the 60 Hz line frequency will maximize 60 Hz "line noise" rejection. A 200 kHz clock frequency will reject 60 Hz and 400 Hz noise. This corresponds to five readings per second. full-scale voltage 20 µA Conversion Rate vs Clock Frequency Oscillator Frequency Conversion Rate (kHz) (Conv/Sec) 100 2.5 120 3 200 5 300 7.5 400 10 800 20 1200 30 Oscillator Frequency (kHz) 60 Hz 50 Hz 400 Hz 50.000 • • • 53.333 — — • 66.667 • — • 80.000 — — • 83.333 — • • 100.000 • • • 125.000 — • • 133.333 — — • 166.667 — — • 200.000 • — • 250.000 — • • The conversion rate is easily calculated: Conversion Rate (Readings 1/sec) = Line Frequency Rejection Clock Frequency (Hz) 4000

3-74 TELCOM SEMICONDUCTOR, INC. PERSONAL COMPUTER DATA ACQUISITION A/D CONVERTER TC835 Power Supplies and Grounds Power Supplies The TC835 is designed to work from ±5V supplies. For single +5V operation, a TC7660 can provide a – 5V supply. Grounding Systems should use separate digital and analog ground systems to avoid loss of accuracy. Displays and Driver Circuits TelCom Semiconductor manufactures two display de- coder/driver circuits to interface the TC835 to an LCD or LED display. Each drive has 28 outputs for driving four 7-segment digit displays. Device Package Description TC7211AIPL 40-Pin Epoxy 4-Digit LCD Driver/Decoder Several sources exist for LCD and LED display: Display Manufacturer Address Type Hewlett Packard 640 Page Mill Rd. LED Components Palo Alto, CA 94304 Litronix, Inc. 19000 Homestead Rd. LED Cupertino, CA 94010 AND 720 Palomar Ave. LCD and Sunnyvale, CA 94086 LED Epson America, Inc. 3415 Kanhi Kawa St. LCD Torrance, CA 90505 For many dedicated applications where the input signal is always of one polarity, the delay of the comparator need not be a limitation. Since the nonlinearity and noise do not increase substantially with frequency, clock rates of up to ~1 MHz may be used. For a fixed clock frequency, the extra count or counts caused by comparator delay will be a constant and can be subtracted out digitally. The clock frequency may be extended above 200 kHz without this error, however, by using a low-value resistor in series with the integrating capacitor. The effect of the resistor is to introduce a small pedestal voltage on to the integrator output at the beginning of the reference integrate phase. By careful selection of the ratio between this resistor and the integrating resistor (a few tens of ohms in the recommended circuit), the comparator delay can be com- pensated and the maximum clock frequency extended by approximately a factor of 3. At higher frequencies, ringing and second-order breaks will cause significant nonlinearities in the first few counts of the instrument. The minimum clock frequency is established by leakage on the auto-zero and reference capacitors. With most de- vices, measurement cycles as long as 10 seconds give no measurable leakage error. The clock used should be free from significant phase or frequency jitter. Several suitable low-cost oscillators are shown in the applications section. The multiplexed output means that if the display takes significant current from the logic supply, the clock should have good PSRR. Zero-Crossing Flip-Flop The flip-flop interrogates the data once every clock pulse after the transients of the previous clock pulse and half-clock pulse have died down. False zero-crossings caused by clock pulses are not recognized. Of course, the flip-flop delays the true zero-crossing by up to one count in every instance, and if a correction were not made, the display would always be one count too high. Therefore, the counter is disabled for one clock pulse at the beginning of the reference integrate (deintegrate) phase. This one-count delay compensates for the delay of the zero-crossing flip- flop, and allows the correct number to be latched into the display. Similarly, a one-count delay at the beginning of auto-zero gives an overload display of 0000 instead of 0001. No delay occurs during signal integrate, so that true ratiometric readings result. High-Speed Operation The maximum conversion rate of most dual-slope A/D converters is limited by the frequency response of the comparator. The comparator in this circuit follows the inte- grator ramp with a 3 µsec delay, and at a clock frequency of 200 kHz (5 µsec period), half of the first reference integrate clock period is lost in delay. This means that the meter reading will change from 0 to 1 with a 50 µV input, 1 to 2 with 150 µV, 2 to 3 at 250 µV, etc. This transition at midpoint is considered desirable by most users; however, if the clock frequency is increased appreciably above 200 kHz, the instrument will flash "1" on noise peaks even when the input is shorted.

3-75TELCOM SEMICONDUCTOR, INC. TC835 PERSONAL COMPUTER DATA ACQUISITION A/D CONVERTER TYPICAL APPLICATIONS DIAGRAMS 4-1/2 Digit ADC With Multiplexed Common Anode LED Display 20 19 18 17 12 1121 5 9–15 bc 777 7 7447 BLANK MSD ON ZERO D1 D2 D3 D4 D5 INT OUT AZ IN BUFF OUT fIN +INPUT –INPUT ANALOG COMMON V – REF IN POL C REF +5V +5V 0.33µF 200 kHz ANALOG INPUT 1 µF 100 kΩ 1 µF 4.7 kΩ 1 µF –5V 100 kΩ 100 kΩ 6.8 kΩ D B C A RBI V + C REF TC04 TC835 R 2 R 1 fO GATES ARE 74C04 C R 1 R2 R 1 + R2 2 C(0.41 RP + 0.7 R1) 1. fO = , RP = a. If R1 = R2 = R1, f ≅ 0.55/RC b. If R2 >> R1, f ≅ 0.45/R1C c. If R2 << R1, f ≅ 0.72/R1C 2. Examples: a. f = 120 kHz, C = 420 pF R 1 = R2 ≈ 10.9 kΩ b. f = 120 kHz, C = 420 pF, R2 = 50 kΩ R 1 = 8.93 kΩ c. f = 120 kHz, C = 220 pF, R2 = 5 kΩ R 1 = 27.3 kΩ RC Oscillator Circuit Comparator Clock Circuits +5V VOUT 390 pF 30 kΩ 16 kΩ 0.22 µF 16 kΩ 1 kΩ +5V VOUT 100 kΩ 100 kΩ 50 kΩ 10 pF 2 kΩ 0.1 µF LM311 LM311 56 kΩ

3-76 TELCOM SEMICONDUCTOR, INC. PERSONAL COMPUTER DATA ACQUISITION A/D CONVERTER TC835 TYPICAL APPLICATIONS DIAGRAMS 4-1/2 Digit ADC with Multiplexed Common Cathode LED Display TC04 REF IN ANALOG GND INT OUT AZ IN BUFF OUT C REF +5V –5V6.8V UR DGND POLARITY OR STROBE RUN/HOLD CLK IN BUSY SET VREF = 1V 1.22V 100 kΩ ANALOG GND 0.33 µF 100 kΩ 1 µF kΩ 150Ω +5V 150Ω +5V CD4513 BE 1 µF –INPUT +INPUT D5 (MSD) B1 (LSB) (LSD) D1 (MSB) B8 100 kΩ SIG IN 0.1 µF +5V fOSC = 200 kHz C REF V – TC835 TC04 TC7211A INT OUT AZ IN BUFF OUT +INPUT –INPUT ANALOG COMMON REF IN V – POL V + STROBE OR BP GND Q RS D CLK CD4071 +5V 1/4 CD4030 4-1/2 DIGIT LCD SEGMENT DRIVE +5V +5V –5V 1/4 CD4081 1/2 CD4030 CD4081 1/4 CD4030 CD4013 6.8 kΩ 100 kΩ 100 kΩ 100 kΩ 0.33 µF 1 µF ANALOG INPUT 200 kHz 22 fIN TC835 TC7660 +5V (–5V) V + V – 10 µF 10 µF TC835 Negative Supply Voltage Generator